stats.txt revision 10628
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.410782 # Number of seconds simulated 4sim_ticks 47410781652000 # Number of ticks simulated 5final_tick 47410781652000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 787433 # Simulator instruction rate (inst/s) 8host_op_rate 926573 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 41969003911 # Simulator tick rate (ticks/s) 10host_mem_usage 699232 # Number of bytes of host memory used 11host_seconds 1129.66 # Real time elapsed on the host 12sim_insts 889532971 # Number of instructions simulated 13sim_ops 1046714541 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 154432 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 156800 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 3551860 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 14084888 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 14587840 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 66560 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 59904 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 2809592 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 8562400 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 11943680 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 428992 # Number of bytes read from this memory 27system.physmem.bytes_read::total 56406948 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 3551860 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 2809592 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 6361452 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 74353408 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 34system.physmem.bytes_written::total 74374224 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 2413 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 2450 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 95905 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 220098 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 227935 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 1040 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 936 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 43988 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 133802 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 186620 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 6703 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 921890 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 1161772 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 50system.physmem.num_writes::total 1164375 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 3257 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 3307 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 74917 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 297082 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 307690 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 1404 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 1264 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 59261 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 180600 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 251919 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 9048 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 1189749 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 74917 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 59261 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 134177 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 1568281 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::total 1568720 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 1568281 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 3257 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 3307 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 74917 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 297521 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 307690 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 1404 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 1264 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 59261 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 180600 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 251919 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 9048 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 2758469 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 921890 # Number of read requests accepted 84system.physmem.writeReqs 1829645 # Number of write requests accepted 85system.physmem.readBursts 921890 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 1829645 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 58978368 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 22592 # Total number of bytes read from write queue 89system.physmem.bytesWritten 116660480 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 56406948 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 116951504 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 353 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 6803 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 114603 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 54393 # Per bank write bursts 96system.physmem.perBankRdBursts::1 56084 # Per bank write bursts 97system.physmem.perBankRdBursts::2 54659 # Per bank write bursts 98system.physmem.perBankRdBursts::3 58883 # Per bank write bursts 99system.physmem.perBankRdBursts::4 54974 # Per bank write bursts 100system.physmem.perBankRdBursts::5 58047 # Per bank write bursts 101system.physmem.perBankRdBursts::6 51881 # Per bank write bursts 102system.physmem.perBankRdBursts::7 58759 # Per bank write bursts 103system.physmem.perBankRdBursts::8 52533 # Per bank write bursts 104system.physmem.perBankRdBursts::9 95950 # Per bank write bursts 105system.physmem.perBankRdBursts::10 53815 # Per bank write bursts 106system.physmem.perBankRdBursts::11 56993 # Per bank write bursts 107system.physmem.perBankRdBursts::12 52328 # Per bank write bursts 108system.physmem.perBankRdBursts::13 55917 # Per bank write bursts 109system.physmem.perBankRdBursts::14 52932 # Per bank write bursts 110system.physmem.perBankRdBursts::15 53389 # Per bank write bursts 111system.physmem.perBankWrBursts::0 113787 # Per bank write bursts 112system.physmem.perBankWrBursts::1 117144 # Per bank write bursts 113system.physmem.perBankWrBursts::2 115098 # Per bank write bursts 114system.physmem.perBankWrBursts::3 118536 # Per bank write bursts 115system.physmem.perBankWrBursts::4 116769 # Per bank write bursts 116system.physmem.perBankWrBursts::5 120895 # Per bank write bursts 117system.physmem.perBankWrBursts::6 109520 # Per bank write bursts 118system.physmem.perBankWrBursts::7 112924 # Per bank write bursts 119system.physmem.perBankWrBursts::8 111914 # Per bank write bursts 120system.physmem.perBankWrBursts::9 117541 # Per bank write bursts 121system.physmem.perBankWrBursts::10 111832 # Per bank write bursts 122system.physmem.perBankWrBursts::11 116807 # Per bank write bursts 123system.physmem.perBankWrBursts::12 108182 # Per bank write bursts 124system.physmem.perBankWrBursts::13 109739 # Per bank write bursts 125system.physmem.perBankWrBursts::14 110202 # Per bank write bursts 126system.physmem.perBankWrBursts::15 111930 # Per bank write bursts 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 128system.physmem.numWrRetry 2 # Number of times write queue was full causing retry 129system.physmem.totGap 47410778671000 # Total gap between requests 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 43195 # Read request sizes (log2) 133system.physmem.readPktSize::3 37 # Read request sizes (log2) 134system.physmem.readPktSize::4 5 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) 136system.physmem.readPktSize::6 878653 # Read request sizes (log2) 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 2 # Write request sizes (log2) 140system.physmem.writePktSize::3 2601 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) 143system.physmem.writePktSize::6 1827042 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 652905 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 75815 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 40303 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 33479 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 29162 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 25818 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 22543 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 19321 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 15689 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 2492 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 1008 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 754 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 600 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 460 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 351 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 292 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 214 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 179 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 82 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 63 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 176system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::15 54841 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 74169 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 96317 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 106970 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 112981 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 116642 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 107891 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 106380 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 105711 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 108843 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 109894 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 108607 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 105867 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 106408 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 98436 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 96529 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 94372 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 91211 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 4176 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 3101 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 2283 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 1802 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 1394 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 1150 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 899 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 725 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 589 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 554 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 484 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 413 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 392 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 373 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 345 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 326 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 302 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 273 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 268 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 219 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 188 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 154 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 105 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 80 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 55 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 39 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 26 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 23 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 5 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 6 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 1000117 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 175.617981 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 106.594305 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 248.236984 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 645970 64.59% 64.59% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 191036 19.10% 83.69% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 45051 4.50% 88.20% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 21747 2.17% 90.37% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 15328 1.53% 91.90% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 10644 1.06% 92.97% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 8285 0.83% 93.80% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 7295 0.73% 94.52% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 54761 5.48% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 1000117 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 87721 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 10.505238 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 108.849756 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-1023 87718 100.00% 100.00% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::total 87721 # Reads before turning the bus around for writes 262system.physmem.wrPerTurnAround::samples 87721 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::mean 20.779745 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::gmean 19.605058 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::stdev 11.125024 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::16-19 56948 64.92% 64.92% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::20-23 16031 18.27% 83.19% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::24-27 6972 7.95% 91.14% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::28-31 3738 4.26% 95.40% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::32-35 1084 1.24% 96.64% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::36-39 357 0.41% 97.05% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::40-43 239 0.27% 97.32% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::44-47 271 0.31% 97.63% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::48-51 649 0.74% 98.37% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::52-55 108 0.12% 98.49% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::56-59 85 0.10% 98.59% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::60-63 76 0.09% 98.67% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::64-67 135 0.15% 98.83% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::68-71 76 0.09% 98.91% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::72-75 51 0.06% 98.97% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::76-79 73 0.08% 99.06% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::80-83 134 0.15% 99.21% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::84-87 41 0.05% 99.26% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::88-91 31 0.04% 99.29% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::92-95 49 0.06% 99.35% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::96-99 179 0.20% 99.55% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::100-103 16 0.02% 99.57% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::104-107 31 0.04% 99.60% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::108-111 14 0.02% 99.62% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::112-115 43 0.05% 99.67% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::116-119 12 0.01% 99.68% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::120-123 20 0.02% 99.71% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::124-127 30 0.03% 99.74% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::128-131 97 0.11% 99.85% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::132-135 18 0.02% 99.87% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::136-139 14 0.02% 99.89% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::140-143 10 0.01% 99.90% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::144-147 13 0.01% 99.91% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::148-151 11 0.01% 99.93% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::152-155 6 0.01% 99.93% # Writes before turning the bus around for reads 301system.physmem.wrPerTurnAround::156-159 6 0.01% 99.94% # Writes before turning the bus around for reads 302system.physmem.wrPerTurnAround::160-163 14 0.02% 99.96% # Writes before turning the bus around for reads 303system.physmem.wrPerTurnAround::164-167 1 0.00% 99.96% # Writes before turning the bus around for reads 304system.physmem.wrPerTurnAround::168-171 2 0.00% 99.96% # Writes before turning the bus around for reads 305system.physmem.wrPerTurnAround::172-175 3 0.00% 99.96% # Writes before turning the bus around for reads 306system.physmem.wrPerTurnAround::176-179 12 0.01% 99.98% # Writes before turning the bus around for reads 307system.physmem.wrPerTurnAround::184-187 2 0.00% 99.98% # Writes before turning the bus around for reads 308system.physmem.wrPerTurnAround::188-191 1 0.00% 99.98% # Writes before turning the bus around for reads 309system.physmem.wrPerTurnAround::192-195 1 0.00% 99.98% # Writes before turning the bus around for reads 310system.physmem.wrPerTurnAround::200-203 3 0.00% 99.98% # Writes before turning the bus around for reads 311system.physmem.wrPerTurnAround::204-207 1 0.00% 99.99% # Writes before turning the bus around for reads 312system.physmem.wrPerTurnAround::212-215 3 0.00% 99.99% # Writes before turning the bus around for reads 313system.physmem.wrPerTurnAround::220-223 3 0.00% 99.99% # Writes before turning the bus around for reads 314system.physmem.wrPerTurnAround::224-227 4 0.00% 100.00% # Writes before turning the bus around for reads 315system.physmem.wrPerTurnAround::228-231 3 0.00% 100.00% # Writes before turning the bus around for reads 316system.physmem.wrPerTurnAround::total 87721 # Writes before turning the bus around for reads 317system.physmem.totQLat 32913462781 # Total ticks spent queuing 318system.physmem.totMemAccLat 50192281531 # Total ticks spent from burst creation until serviced by the DRAM 319system.physmem.totBusLat 4607685000 # Total ticks spent in databus transfers 320system.physmem.avgQLat 35715.83 # Average queueing delay per DRAM burst 321system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 322system.physmem.avgMemAccLat 54465.83 # Average memory access latency per DRAM burst 323system.physmem.avgRdBW 1.24 # Average DRAM read bandwidth in MiByte/s 324system.physmem.avgWrBW 2.46 # Average achieved write bandwidth in MiByte/s 325system.physmem.avgRdBWSys 1.19 # Average system read bandwidth in MiByte/s 326system.physmem.avgWrBWSys 2.47 # Average system write bandwidth in MiByte/s 327system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 328system.physmem.busUtil 0.03 # Data bus utilization in percentage 329system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 330system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 331system.physmem.avgRdQLen 1.25 # Average read queue length when enqueuing 332system.physmem.avgWrQLen 25.28 # Average write queue length when enqueuing 333system.physmem.readRowHits 687654 # Number of row buffer hits during reads 334system.physmem.writeRowHits 1056585 # Number of row buffer hits during writes 335system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads 336system.physmem.writeRowHitRate 57.96 # Row buffer hit rate for writes 337system.physmem.avgGap 17230665.31 # Average gap between requests 338system.physmem.pageHitRate 63.56 # Row buffer hit rate, read and write combined 339system.physmem_0.actEnergy 3832851960 # Energy for activate commands per rank (pJ) 340system.physmem_0.preEnergy 2091337875 # Energy for precharge commands per rank (pJ) 341system.physmem_0.readEnergy 3491865000 # Energy for read commands per rank (pJ) 342system.physmem_0.writeEnergy 5991881040 # Energy for write commands per rank (pJ) 343system.physmem_0.refreshEnergy 3096641673840 # Energy for refresh commands per rank (pJ) 344system.physmem_0.actBackEnergy 1200455054145 # Energy for active background per rank (pJ) 345system.physmem_0.preBackEnergy 27393437346750 # Energy for precharge background per rank (pJ) 346system.physmem_0.totalEnergy 31705942010610 # Total energy per rank (pJ) 347system.physmem_0.averagePower 668.749637 # Core power per rank (mW) 348system.physmem_0.memoryStateTime::IDLE 45570820980751 # Time in different power states 349system.physmem_0.memoryStateTime::REF 1583150140000 # Time in different power states 350system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 351system.physmem_0.memoryStateTime::ACT 256810103749 # Time in different power states 352system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 353system.physmem_1.actEnergy 3728032560 # Energy for activate commands per rank (pJ) 354system.physmem_1.preEnergy 2034144750 # Energy for precharge commands per rank (pJ) 355system.physmem_1.readEnergy 3696084600 # Energy for read commands per rank (pJ) 356system.physmem_1.writeEnergy 5819992560 # Energy for write commands per rank (pJ) 357system.physmem_1.refreshEnergy 3096641673840 # Energy for refresh commands per rank (pJ) 358system.physmem_1.actBackEnergy 1191404828700 # Energy for active background per rank (pJ) 359system.physmem_1.preBackEnergy 27401376141000 # Energy for precharge background per rank (pJ) 360system.physmem_1.totalEnergy 31704700898010 # Total energy per rank (pJ) 361system.physmem_1.averagePower 668.723459 # Core power per rank (mW) 362system.physmem_1.memoryStateTime::IDLE 45584059811251 # Time in different power states 363system.physmem_1.memoryStateTime::REF 1583150140000 # Time in different power states 364system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 365system.physmem_1.memoryStateTime::ACT 243570222499 # Time in different power states 366system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 367system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 368system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 369system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 370system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 371system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 372system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 373system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 374system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 375system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 376system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 377system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 378system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 379system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 380system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 381system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 382system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 383system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 384system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 385system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 386system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 387system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 388system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 389system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 390system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 391system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 392system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 393system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 394system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 395system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 396system.cf0.dma_write_full_pages 1670 # Number of full page size DMA writes. 397system.cf0.dma_write_bytes 6842880 # Number of bytes transfered via DMA writes. 398system.cf0.dma_write_txs 1673 # Number of DMA write transactions. 399system.cpu_clk_domain.clock 500 # Clock period in ticks 400system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 401system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 402system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 403system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 404system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 405system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 406system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 407system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 408system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 409system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 410system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 411system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 412system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 413system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 414system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 415system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 416system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 417system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 418system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 419system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 420system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 421system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 422system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 423system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 424system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 425system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 426system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 427system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 428system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 429system.cpu0.dtb.walker.walks 107972 # Table walker walks requested 430system.cpu0.dtb.walker.walksLong 107972 # Table walker walks initiated with long descriptors 431system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9276 # Level at which table walker walks with long descriptors terminate 432system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 83163 # Level at which table walker walks with long descriptors terminate 433system.cpu0.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting 434system.cpu0.dtb.walker.walkWaitTime::samples 107963 # Table walker wait (enqueue to first request) latency 435system.cpu0.dtb.walker.walkWaitTime::0 107963 100.00% 100.00% # Table walker wait (enqueue to first request) latency 436system.cpu0.dtb.walker.walkWaitTime::total 107963 # Table walker wait (enqueue to first request) latency 437system.cpu0.dtb.walker.walkCompletionTime::samples 92448 # Table walker service (enqueue to completion) latency 438system.cpu0.dtb.walker.walkCompletionTime::mean 17595.764614 # Table walker service (enqueue to completion) latency 439system.cpu0.dtb.walker.walkCompletionTime::gmean 15306.328665 # Table walker service (enqueue to completion) latency 440system.cpu0.dtb.walker.walkCompletionTime::stdev 15454.252367 # Table walker service (enqueue to completion) latency 441system.cpu0.dtb.walker.walkCompletionTime::0-65535 91009 98.44% 98.44% # Table walker service (enqueue to completion) latency 442system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1235 1.34% 99.78% # Table walker service (enqueue to completion) latency 443system.cpu0.dtb.walker.walkCompletionTime::131072-196607 66 0.07% 99.85% # Table walker service (enqueue to completion) latency 444system.cpu0.dtb.walker.walkCompletionTime::196608-262143 55 0.06% 99.91% # Table walker service (enqueue to completion) latency 445system.cpu0.dtb.walker.walkCompletionTime::262144-327679 65 0.07% 99.98% # Table walker service (enqueue to completion) latency 446system.cpu0.dtb.walker.walkCompletionTime::327680-393215 12 0.01% 99.99% # Table walker service (enqueue to completion) latency 447system.cpu0.dtb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 448system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 449system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 450system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 451system.cpu0.dtb.walker.walkCompletionTime::total 92448 # Table walker service (enqueue to completion) latency 452system.cpu0.dtb.walker.walksPending::samples -2398441544 # Table walker pending requests distribution 453system.cpu0.dtb.walker.walksPending::mean 0.163884 # Table walker pending requests distribution 454system.cpu0.dtb.walker.walksPending::stdev 0.370170 # Table walker pending requests distribution 455system.cpu0.dtb.walker.walksPending::0 -2005375084 83.61% 83.61% # Table walker pending requests distribution 456system.cpu0.dtb.walker.walksPending::1 -393066460 16.39% 100.00% # Table walker pending requests distribution 457system.cpu0.dtb.walker.walksPending::total -2398441544 # Table walker pending requests distribution 458system.cpu0.dtb.walker.walkPageSizes::4K 83163 89.97% 89.97% # Table walker page sizes translated 459system.cpu0.dtb.walker.walkPageSizes::2M 9276 10.03% 100.00% # Table walker page sizes translated 460system.cpu0.dtb.walker.walkPageSizes::total 92439 # Table walker page sizes translated 461system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 107972 # Table walker requests started/completed, data/inst 462system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 463system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 107972 # Table walker requests started/completed, data/inst 464system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 92439 # Table walker requests started/completed, data/inst 465system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 466system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 92439 # Table walker requests started/completed, data/inst 467system.cpu0.dtb.walker.walkRequestOrigin::total 200411 # Table walker requests started/completed, data/inst 468system.cpu0.dtb.inst_hits 0 # ITB inst hits 469system.cpu0.dtb.inst_misses 0 # ITB inst misses 470system.cpu0.dtb.read_hits 83792624 # DTB read hits 471system.cpu0.dtb.read_misses 78614 # DTB read misses 472system.cpu0.dtb.write_hits 76883618 # DTB write hits 473system.cpu0.dtb.write_misses 29358 # DTB write misses 474system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 475system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 476system.cpu0.dtb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID 477system.cpu0.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID 478system.cpu0.dtb.flush_entries 38297 # Number of entries that have been flushed from TLB 479system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 480system.cpu0.dtb.prefetch_faults 4651 # Number of TLB faults due to prefetch 481system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 482system.cpu0.dtb.perms_faults 10679 # Number of TLB faults due to permissions restrictions 483system.cpu0.dtb.read_accesses 83871238 # DTB read accesses 484system.cpu0.dtb.write_accesses 76912976 # DTB write accesses 485system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 486system.cpu0.dtb.hits 160676242 # DTB hits 487system.cpu0.dtb.misses 107972 # DTB misses 488system.cpu0.dtb.accesses 160784214 # DTB accesses 489system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 490system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 491system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 492system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 493system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 494system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 495system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 496system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 497system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 498system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 499system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 500system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 501system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 502system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 503system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 504system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 505system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 506system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 507system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 508system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 509system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 510system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 511system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 512system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 513system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 514system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 515system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 516system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 517system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 518system.cpu0.itb.walker.walks 64255 # Table walker walks requested 519system.cpu0.itb.walker.walksLong 64255 # Table walker walks initiated with long descriptors 520system.cpu0.itb.walker.walksLongTerminationLevel::Level2 637 # Level at which table walker walks with long descriptors terminate 521system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58227 # Level at which table walker walks with long descriptors terminate 522system.cpu0.itb.walker.walkWaitTime::samples 64255 # Table walker wait (enqueue to first request) latency 523system.cpu0.itb.walker.walkWaitTime::0 64255 100.00% 100.00% # Table walker wait (enqueue to first request) latency 524system.cpu0.itb.walker.walkWaitTime::total 64255 # Table walker wait (enqueue to first request) latency 525system.cpu0.itb.walker.walkCompletionTime::samples 58864 # Table walker service (enqueue to completion) latency 526system.cpu0.itb.walker.walkCompletionTime::mean 20635.902164 # Table walker service (enqueue to completion) latency 527system.cpu0.itb.walker.walkCompletionTime::gmean 17664.674655 # Table walker service (enqueue to completion) latency 528system.cpu0.itb.walker.walkCompletionTime::stdev 19771.927470 # Table walker service (enqueue to completion) latency 529system.cpu0.itb.walker.walkCompletionTime::0-65535 57276 97.30% 97.30% # Table walker service (enqueue to completion) latency 530system.cpu0.itb.walker.walkCompletionTime::65536-131071 1371 2.33% 99.63% # Table walker service (enqueue to completion) latency 531system.cpu0.itb.walker.walkCompletionTime::131072-196607 47 0.08% 99.71% # Table walker service (enqueue to completion) latency 532system.cpu0.itb.walker.walkCompletionTime::196608-262143 91 0.15% 99.87% # Table walker service (enqueue to completion) latency 533system.cpu0.itb.walker.walkCompletionTime::262144-327679 53 0.09% 99.96% # Table walker service (enqueue to completion) latency 534system.cpu0.itb.walker.walkCompletionTime::327680-393215 19 0.03% 99.99% # Table walker service (enqueue to completion) latency 535system.cpu0.itb.walker.walkCompletionTime::393216-458751 5 0.01% 100.00% # Table walker service (enqueue to completion) latency 536system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 537system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 538system.cpu0.itb.walker.walkCompletionTime::total 58864 # Table walker service (enqueue to completion) latency 539system.cpu0.itb.walker.walksPending::samples -673300296 # Table walker pending requests distribution 540system.cpu0.itb.walker.walksPending::0 -673300296 100.00% 100.00% # Table walker pending requests distribution 541system.cpu0.itb.walker.walksPending::total -673300296 # Table walker pending requests distribution 542system.cpu0.itb.walker.walkPageSizes::4K 58227 98.92% 98.92% # Table walker page sizes translated 543system.cpu0.itb.walker.walkPageSizes::2M 637 1.08% 100.00% # Table walker page sizes translated 544system.cpu0.itb.walker.walkPageSizes::total 58864 # Table walker page sizes translated 545system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 546system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 64255 # Table walker requests started/completed, data/inst 547system.cpu0.itb.walker.walkRequestOrigin_Requested::total 64255 # Table walker requests started/completed, data/inst 548system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 549system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 58864 # Table walker requests started/completed, data/inst 550system.cpu0.itb.walker.walkRequestOrigin_Completed::total 58864 # Table walker requests started/completed, data/inst 551system.cpu0.itb.walker.walkRequestOrigin::total 123119 # Table walker requests started/completed, data/inst 552system.cpu0.itb.inst_hits 448595101 # ITB inst hits 553system.cpu0.itb.inst_misses 64255 # ITB inst misses 554system.cpu0.itb.read_hits 0 # DTB read hits 555system.cpu0.itb.read_misses 0 # DTB read misses 556system.cpu0.itb.write_hits 0 # DTB write hits 557system.cpu0.itb.write_misses 0 # DTB write misses 558system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 559system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 560system.cpu0.itb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID 561system.cpu0.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID 562system.cpu0.itb.flush_entries 26739 # Number of entries that have been flushed from TLB 563system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 564system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 565system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 566system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 567system.cpu0.itb.read_accesses 0 # DTB read accesses 568system.cpu0.itb.write_accesses 0 # DTB write accesses 569system.cpu0.itb.inst_accesses 448659356 # ITB inst accesses 570system.cpu0.itb.hits 448595101 # DTB hits 571system.cpu0.itb.misses 64255 # DTB misses 572system.cpu0.itb.accesses 448659356 # DTB accesses 573system.cpu0.numCycles 94821563304 # number of cpu cycles simulated 574system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 575system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 576system.cpu0.committedInsts 448345930 # Number of instructions committed 577system.cpu0.committedOps 527651436 # Number of ops (including micro ops) committed 578system.cpu0.num_int_alu_accesses 484594714 # Number of integer alu accesses 579system.cpu0.num_fp_alu_accesses 558267 # Number of float alu accesses 580system.cpu0.num_func_calls 26890258 # number of times a function call or return occured 581system.cpu0.num_conditional_control_insts 68074268 # number of instructions that are conditional controls 582system.cpu0.num_int_insts 484594714 # number of integer instructions 583system.cpu0.num_fp_insts 558267 # number of float instructions 584system.cpu0.num_int_register_reads 706750752 # number of times the integer registers were read 585system.cpu0.num_int_register_writes 384547382 # number of times the integer registers were written 586system.cpu0.num_fp_register_reads 893879 # number of times the floating registers were read 587system.cpu0.num_fp_register_writes 490056 # number of times the floating registers were written 588system.cpu0.num_cc_register_reads 117567828 # number of times the CC registers were read 589system.cpu0.num_cc_register_writes 117277075 # number of times the CC registers were written 590system.cpu0.num_mem_refs 160668093 # number of memory refs 591system.cpu0.num_load_insts 83788812 # Number of load instructions 592system.cpu0.num_store_insts 76879281 # Number of store instructions 593system.cpu0.num_idle_cycles 93729284290.716034 # Number of idle cycles 594system.cpu0.num_busy_cycles 1092279013.283977 # Number of busy cycles 595system.cpu0.not_idle_fraction 0.011519 # Percentage of non-idle cycles 596system.cpu0.idle_fraction 0.988481 # Percentage of idle cycles 597system.cpu0.Branches 100174256 # Number of branches fetched 598system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 599system.cpu0.op_class::IntAlu 365953478 69.32% 69.32% # Class of executed instruction 600system.cpu0.op_class::IntMult 1186010 0.22% 69.54% # Class of executed instruction 601system.cpu0.op_class::IntDiv 57830 0.01% 69.55% # Class of executed instruction 602system.cpu0.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction 603system.cpu0.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction 604system.cpu0.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction 605system.cpu0.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction 606system.cpu0.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction 607system.cpu0.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction 608system.cpu0.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction 609system.cpu0.op_class::SimdAddAcc 0 0.00% 69.55% # Class of executed instruction 610system.cpu0.op_class::SimdAlu 0 0.00% 69.55% # Class of executed instruction 611system.cpu0.op_class::SimdCmp 0 0.00% 69.55% # Class of executed instruction 612system.cpu0.op_class::SimdCvt 0 0.00% 69.55% # Class of executed instruction 613system.cpu0.op_class::SimdMisc 0 0.00% 69.55% # Class of executed instruction 614system.cpu0.op_class::SimdMult 0 0.00% 69.55% # Class of executed instruction 615system.cpu0.op_class::SimdMultAcc 0 0.00% 69.55% # Class of executed instruction 616system.cpu0.op_class::SimdShift 0 0.00% 69.55% # Class of executed instruction 617system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.55% # Class of executed instruction 618system.cpu0.op_class::SimdSqrt 0 0.00% 69.55% # Class of executed instruction 619system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.55% # Class of executed instruction 620system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction 621system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.55% # Class of executed instruction 622system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.55% # Class of executed instruction 623system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction 624system.cpu0.op_class::SimdFloatMisc 78277 0.01% 69.57% # Class of executed instruction 625system.cpu0.op_class::SimdFloatMult 0 0.00% 69.57% # Class of executed instruction 626system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.57% # Class of executed instruction 627system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.57% # Class of executed instruction 628system.cpu0.op_class::MemRead 83788812 15.87% 85.44% # Class of executed instruction 629system.cpu0.op_class::MemWrite 76879281 14.56% 100.00% # Class of executed instruction 630system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 631system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 632system.cpu0.op_class::total 527943731 # Class of executed instruction 633system.cpu0.kern.inst.arm 0 # number of arm instructions executed 634system.cpu0.kern.inst.quiesce 5474 # number of quiesce instructions executed 635system.cpu0.dcache.tags.replacements 5753925 # number of replacements 636system.cpu0.dcache.tags.tagsinuse 509.684776 # Cycle average of tags in use 637system.cpu0.dcache.tags.total_refs 154679022 # Total number of references to valid blocks. 638system.cpu0.dcache.tags.sampled_refs 5754435 # Sample count of references to valid blocks. 639system.cpu0.dcache.tags.avg_refs 26.879967 # Average number of references to valid blocks. 640system.cpu0.dcache.tags.warmup_cycle 3644714000 # Cycle when the warmup percentage was hit. 641system.cpu0.dcache.tags.occ_blocks::cpu0.data 509.684776 # Average occupied blocks per requestor 642system.cpu0.dcache.tags.occ_percent::cpu0.data 0.995478 # Average percentage of cache occupancy 643system.cpu0.dcache.tags.occ_percent::total 0.995478 # Average percentage of cache occupancy 644system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id 645system.cpu0.dcache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id 646system.cpu0.dcache.tags.age_task_id_blocks_1024::1 390 # Occupied blocks per task id 647system.cpu0.dcache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id 648system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 649system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id 650system.cpu0.dcache.tags.tag_accesses 327127592 # Number of tag accesses 651system.cpu0.dcache.tags.data_accesses 327127592 # Number of data accesses 652system.cpu0.dcache.ReadReq_hits::cpu0.data 77833401 # number of ReadReq hits 653system.cpu0.dcache.ReadReq_hits::total 77833401 # number of ReadReq hits 654system.cpu0.dcache.WriteReq_hits::cpu0.data 72535559 # number of WriteReq hits 655system.cpu0.dcache.WriteReq_hits::total 72535559 # number of WriteReq hits 656system.cpu0.dcache.SoftPFReq_hits::cpu0.data 180949 # number of SoftPFReq hits 657system.cpu0.dcache.SoftPFReq_hits::total 180949 # number of SoftPFReq hits 658system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 117408 # number of WriteInvalidateReq hits 659system.cpu0.dcache.WriteInvalidateReq_hits::total 117408 # number of WriteInvalidateReq hits 660system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1813577 # number of LoadLockedReq hits 661system.cpu0.dcache.LoadLockedReq_hits::total 1813577 # number of LoadLockedReq hits 662system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1784599 # number of StoreCondReq hits 663system.cpu0.dcache.StoreCondReq_hits::total 1784599 # number of StoreCondReq hits 664system.cpu0.dcache.demand_hits::cpu0.data 150368960 # number of demand (read+write) hits 665system.cpu0.dcache.demand_hits::total 150368960 # number of demand (read+write) hits 666system.cpu0.dcache.overall_hits::cpu0.data 150549909 # number of overall hits 667system.cpu0.dcache.overall_hits::total 150549909 # number of overall hits 668system.cpu0.dcache.ReadReq_misses::cpu0.data 3079415 # number of ReadReq misses 669system.cpu0.dcache.ReadReq_misses::total 3079415 # number of ReadReq misses 670system.cpu0.dcache.WriteReq_misses::cpu0.data 1439122 # number of WriteReq misses 671system.cpu0.dcache.WriteReq_misses::total 1439122 # number of WriteReq misses 672system.cpu0.dcache.SoftPFReq_misses::cpu0.data 698265 # number of SoftPFReq misses 673system.cpu0.dcache.SoftPFReq_misses::total 698265 # number of SoftPFReq misses 674system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 782756 # number of WriteInvalidateReq misses 675system.cpu0.dcache.WriteInvalidateReq_misses::total 782756 # number of WriteInvalidateReq misses 676system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 172905 # number of LoadLockedReq misses 677system.cpu0.dcache.LoadLockedReq_misses::total 172905 # number of LoadLockedReq misses 678system.cpu0.dcache.StoreCondReq_misses::cpu0.data 200615 # number of StoreCondReq misses 679system.cpu0.dcache.StoreCondReq_misses::total 200615 # number of StoreCondReq misses 680system.cpu0.dcache.demand_misses::cpu0.data 4518537 # number of demand (read+write) misses 681system.cpu0.dcache.demand_misses::total 4518537 # number of demand (read+write) misses 682system.cpu0.dcache.overall_misses::cpu0.data 5216802 # number of overall misses 683system.cpu0.dcache.overall_misses::total 5216802 # number of overall misses 684system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 45365631768 # number of ReadReq miss cycles 685system.cpu0.dcache.ReadReq_miss_latency::total 45365631768 # number of ReadReq miss cycles 686system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 25986134990 # number of WriteReq miss cycles 687system.cpu0.dcache.WriteReq_miss_latency::total 25986134990 # number of WriteReq miss cycles 688system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 26026367891 # number of WriteInvalidateReq miss cycles 689system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 26026367891 # number of WriteInvalidateReq miss cycles 690system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2610218258 # number of LoadLockedReq miss cycles 691system.cpu0.dcache.LoadLockedReq_miss_latency::total 2610218258 # number of LoadLockedReq miss cycles 692system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4265500897 # number of StoreCondReq miss cycles 693system.cpu0.dcache.StoreCondReq_miss_latency::total 4265500897 # number of StoreCondReq miss cycles 694system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2243000 # number of StoreCondFailReq miss cycles 695system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2243000 # number of StoreCondFailReq miss cycles 696system.cpu0.dcache.demand_miss_latency::cpu0.data 71351766758 # number of demand (read+write) miss cycles 697system.cpu0.dcache.demand_miss_latency::total 71351766758 # number of demand (read+write) miss cycles 698system.cpu0.dcache.overall_miss_latency::cpu0.data 71351766758 # number of overall miss cycles 699system.cpu0.dcache.overall_miss_latency::total 71351766758 # number of overall miss cycles 700system.cpu0.dcache.ReadReq_accesses::cpu0.data 80912816 # number of ReadReq accesses(hits+misses) 701system.cpu0.dcache.ReadReq_accesses::total 80912816 # number of ReadReq accesses(hits+misses) 702system.cpu0.dcache.WriteReq_accesses::cpu0.data 73974681 # number of WriteReq accesses(hits+misses) 703system.cpu0.dcache.WriteReq_accesses::total 73974681 # number of WriteReq accesses(hits+misses) 704system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 879214 # number of SoftPFReq accesses(hits+misses) 705system.cpu0.dcache.SoftPFReq_accesses::total 879214 # number of SoftPFReq accesses(hits+misses) 706system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 900164 # number of WriteInvalidateReq accesses(hits+misses) 707system.cpu0.dcache.WriteInvalidateReq_accesses::total 900164 # number of WriteInvalidateReq accesses(hits+misses) 708system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1986482 # number of LoadLockedReq accesses(hits+misses) 709system.cpu0.dcache.LoadLockedReq_accesses::total 1986482 # number of LoadLockedReq accesses(hits+misses) 710system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1985214 # number of StoreCondReq accesses(hits+misses) 711system.cpu0.dcache.StoreCondReq_accesses::total 1985214 # number of StoreCondReq accesses(hits+misses) 712system.cpu0.dcache.demand_accesses::cpu0.data 154887497 # number of demand (read+write) accesses 713system.cpu0.dcache.demand_accesses::total 154887497 # number of demand (read+write) accesses 714system.cpu0.dcache.overall_accesses::cpu0.data 155766711 # number of overall (read+write) accesses 715system.cpu0.dcache.overall_accesses::total 155766711 # number of overall (read+write) accesses 716system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.038058 # miss rate for ReadReq accesses 717system.cpu0.dcache.ReadReq_miss_rate::total 0.038058 # miss rate for ReadReq accesses 718system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.019454 # miss rate for WriteReq accesses 719system.cpu0.dcache.WriteReq_miss_rate::total 0.019454 # miss rate for WriteReq accesses 720system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.794192 # miss rate for SoftPFReq accesses 721system.cpu0.dcache.SoftPFReq_miss_rate::total 0.794192 # miss rate for SoftPFReq accesses 722system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.869570 # miss rate for WriteInvalidateReq accesses 723system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.869570 # miss rate for WriteInvalidateReq accesses 724system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.087041 # miss rate for LoadLockedReq accesses 725system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.087041 # miss rate for LoadLockedReq accesses 726system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.101055 # miss rate for StoreCondReq accesses 727system.cpu0.dcache.StoreCondReq_miss_rate::total 0.101055 # miss rate for StoreCondReq accesses 728system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029173 # miss rate for demand accesses 729system.cpu0.dcache.demand_miss_rate::total 0.029173 # miss rate for demand accesses 730system.cpu0.dcache.overall_miss_rate::cpu0.data 0.033491 # miss rate for overall accesses 731system.cpu0.dcache.overall_miss_rate::total 0.033491 # miss rate for overall accesses 732system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14731.899328 # average ReadReq miss latency 733system.cpu0.dcache.ReadReq_avg_miss_latency::total 14731.899328 # average ReadReq miss latency 734system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18056.936792 # average WriteReq miss latency 735system.cpu0.dcache.WriteReq_avg_miss_latency::total 18056.936792 # average WriteReq miss latency 736system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 33249.656203 # average WriteInvalidateReq miss latency 737system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 33249.656203 # average WriteInvalidateReq miss latency 738system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15096.256661 # average LoadLockedReq miss latency 739system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15096.256661 # average LoadLockedReq miss latency 740system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21262.123455 # average StoreCondReq miss latency 741system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21262.123455 # average StoreCondReq miss latency 742system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 743system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 744system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15790.900187 # average overall miss latency 745system.cpu0.dcache.demand_avg_miss_latency::total 15790.900187 # average overall miss latency 746system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13677.300146 # average overall miss latency 747system.cpu0.dcache.overall_avg_miss_latency::total 13677.300146 # average overall miss latency 748system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 749system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 750system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 751system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 752system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 753system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 754system.cpu0.dcache.fast_writes 0 # number of fast writes performed 755system.cpu0.dcache.cache_copies 0 # number of cache copies performed 756system.cpu0.dcache.writebacks::writebacks 3895213 # number of writebacks 757system.cpu0.dcache.writebacks::total 3895213 # number of writebacks 758system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 35120 # number of ReadReq MSHR hits 759system.cpu0.dcache.ReadReq_mshr_hits::total 35120 # number of ReadReq MSHR hits 760system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21470 # number of WriteReq MSHR hits 761system.cpu0.dcache.WriteReq_mshr_hits::total 21470 # number of WriteReq MSHR hits 762system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 46933 # number of LoadLockedReq MSHR hits 763system.cpu0.dcache.LoadLockedReq_mshr_hits::total 46933 # number of LoadLockedReq MSHR hits 764system.cpu0.dcache.demand_mshr_hits::cpu0.data 56590 # number of demand (read+write) MSHR hits 765system.cpu0.dcache.demand_mshr_hits::total 56590 # number of demand (read+write) MSHR hits 766system.cpu0.dcache.overall_mshr_hits::cpu0.data 56590 # number of overall MSHR hits 767system.cpu0.dcache.overall_mshr_hits::total 56590 # number of overall MSHR hits 768system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3044295 # number of ReadReq MSHR misses 769system.cpu0.dcache.ReadReq_mshr_misses::total 3044295 # number of ReadReq MSHR misses 770system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1417652 # number of WriteReq MSHR misses 771system.cpu0.dcache.WriteReq_mshr_misses::total 1417652 # number of WriteReq MSHR misses 772system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 692633 # number of SoftPFReq MSHR misses 773system.cpu0.dcache.SoftPFReq_mshr_misses::total 692633 # number of SoftPFReq MSHR misses 774system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 782756 # number of WriteInvalidateReq MSHR misses 775system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 782756 # number of WriteInvalidateReq MSHR misses 776system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 125972 # number of LoadLockedReq MSHR misses 777system.cpu0.dcache.LoadLockedReq_mshr_misses::total 125972 # number of LoadLockedReq MSHR misses 778system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 200615 # number of StoreCondReq MSHR misses 779system.cpu0.dcache.StoreCondReq_mshr_misses::total 200615 # number of StoreCondReq MSHR misses 780system.cpu0.dcache.demand_mshr_misses::cpu0.data 4461947 # number of demand (read+write) MSHR misses 781system.cpu0.dcache.demand_mshr_misses::total 4461947 # number of demand (read+write) MSHR misses 782system.cpu0.dcache.overall_mshr_misses::cpu0.data 5154580 # number of overall MSHR misses 783system.cpu0.dcache.overall_mshr_misses::total 5154580 # number of overall MSHR misses 784system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 37795344499 # number of ReadReq MSHR miss cycles 785system.cpu0.dcache.ReadReq_mshr_miss_latency::total 37795344499 # number of ReadReq MSHR miss cycles 786system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 22579422262 # number of WriteReq MSHR miss cycles 787system.cpu0.dcache.WriteReq_mshr_miss_latency::total 22579422262 # number of WriteReq MSHR miss cycles 788system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14234213672 # number of SoftPFReq MSHR miss cycles 789system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14234213672 # number of SoftPFReq MSHR miss cycles 790system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 24458156109 # number of WriteInvalidateReq MSHR miss cycles 791system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 24458156109 # number of WriteInvalidateReq MSHR miss cycles 792system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1564829744 # number of LoadLockedReq MSHR miss cycles 793system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1564829744 # number of LoadLockedReq MSHR miss cycles 794system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3853276103 # number of StoreCondReq MSHR miss cycles 795system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3853276103 # number of StoreCondReq MSHR miss cycles 796system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2137000 # number of StoreCondFailReq MSHR miss cycles 797system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2137000 # number of StoreCondFailReq MSHR miss cycles 798system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 60374766761 # number of demand (read+write) MSHR miss cycles 799system.cpu0.dcache.demand_mshr_miss_latency::total 60374766761 # number of demand (read+write) MSHR miss cycles 800system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 74608980433 # number of overall MSHR miss cycles 801system.cpu0.dcache.overall_mshr_miss_latency::total 74608980433 # number of overall MSHR miss cycles 802system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2287793998 # number of ReadReq MSHR uncacheable cycles 803system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2287793998 # number of ReadReq MSHR uncacheable cycles 804system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2244465248 # number of WriteReq MSHR uncacheable cycles 805system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2244465248 # number of WriteReq MSHR uncacheable cycles 806system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4532259246 # number of overall MSHR uncacheable cycles 807system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4532259246 # number of overall MSHR uncacheable cycles 808system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037624 # mshr miss rate for ReadReq accesses 809system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037624 # mshr miss rate for ReadReq accesses 810system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019164 # mshr miss rate for WriteReq accesses 811system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019164 # mshr miss rate for WriteReq accesses 812system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.787787 # mshr miss rate for SoftPFReq accesses 813system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.787787 # mshr miss rate for SoftPFReq accesses 814system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.869570 # mshr miss rate for WriteInvalidateReq accesses 815system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.869570 # mshr miss rate for WriteInvalidateReq accesses 816system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063415 # mshr miss rate for LoadLockedReq accesses 817system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063415 # mshr miss rate for LoadLockedReq accesses 818system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.101055 # mshr miss rate for StoreCondReq accesses 819system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.101055 # mshr miss rate for StoreCondReq accesses 820system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028808 # mshr miss rate for demand accesses 821system.cpu0.dcache.demand_mshr_miss_rate::total 0.028808 # mshr miss rate for demand accesses 822system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.033092 # mshr miss rate for overall accesses 823system.cpu0.dcache.overall_mshr_miss_rate::total 0.033092 # mshr miss rate for overall accesses 824system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12415.138644 # average ReadReq mshr miss latency 825system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12415.138644 # average ReadReq mshr miss latency 826system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15927.337782 # average WriteReq mshr miss latency 827system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15927.337782 # average WriteReq mshr miss latency 828system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20550.874232 # average SoftPFReq mshr miss latency 829system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20550.874232 # average SoftPFReq mshr miss latency 830system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 31246.207131 # average WriteInvalidateReq mshr miss latency 831system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 31246.207131 # average WriteInvalidateReq mshr miss latency 832system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12422.044137 # average LoadLockedReq mshr miss latency 833system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12422.044137 # average LoadLockedReq mshr miss latency 834system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19207.318012 # average StoreCondReq mshr miss latency 835system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19207.318012 # average StoreCondReq mshr miss latency 836system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 837system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 838system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13531.036286 # average overall mshr miss latency 839system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13531.036286 # average overall mshr miss latency 840system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14474.308369 # average overall mshr miss latency 841system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14474.308369 # average overall mshr miss latency 842system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 843system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 844system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 845system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 846system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 847system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 848system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 849system.cpu0.icache.tags.replacements 5166576 # number of replacements 850system.cpu0.icache.tags.tagsinuse 511.910022 # Cycle average of tags in use 851system.cpu0.icache.tags.total_refs 443428013 # Total number of references to valid blocks. 852system.cpu0.icache.tags.sampled_refs 5167088 # Sample count of references to valid blocks. 853system.cpu0.icache.tags.avg_refs 85.817778 # Average number of references to valid blocks. 854system.cpu0.icache.tags.warmup_cycle 30209622750 # Cycle when the warmup percentage was hit. 855system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.910022 # Average occupied blocks per requestor 856system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999824 # Average percentage of cache occupancy 857system.cpu0.icache.tags.occ_percent::total 0.999824 # Average percentage of cache occupancy 858system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 859system.cpu0.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id 860system.cpu0.icache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id 861system.cpu0.icache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id 862system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 863system.cpu0.icache.tags.tag_accesses 902357290 # Number of tag accesses 864system.cpu0.icache.tags.data_accesses 902357290 # Number of data accesses 865system.cpu0.icache.ReadReq_hits::cpu0.inst 443428013 # number of ReadReq hits 866system.cpu0.icache.ReadReq_hits::total 443428013 # number of ReadReq hits 867system.cpu0.icache.demand_hits::cpu0.inst 443428013 # number of demand (read+write) hits 868system.cpu0.icache.demand_hits::total 443428013 # number of demand (read+write) hits 869system.cpu0.icache.overall_hits::cpu0.inst 443428013 # number of overall hits 870system.cpu0.icache.overall_hits::total 443428013 # number of overall hits 871system.cpu0.icache.ReadReq_misses::cpu0.inst 5167088 # number of ReadReq misses 872system.cpu0.icache.ReadReq_misses::total 5167088 # number of ReadReq misses 873system.cpu0.icache.demand_misses::cpu0.inst 5167088 # number of demand (read+write) misses 874system.cpu0.icache.demand_misses::total 5167088 # number of demand (read+write) misses 875system.cpu0.icache.overall_misses::cpu0.inst 5167088 # number of overall misses 876system.cpu0.icache.overall_misses::total 5167088 # number of overall misses 877system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 53694723563 # number of ReadReq miss cycles 878system.cpu0.icache.ReadReq_miss_latency::total 53694723563 # number of ReadReq miss cycles 879system.cpu0.icache.demand_miss_latency::cpu0.inst 53694723563 # number of demand (read+write) miss cycles 880system.cpu0.icache.demand_miss_latency::total 53694723563 # number of demand (read+write) miss cycles 881system.cpu0.icache.overall_miss_latency::cpu0.inst 53694723563 # number of overall miss cycles 882system.cpu0.icache.overall_miss_latency::total 53694723563 # number of overall miss cycles 883system.cpu0.icache.ReadReq_accesses::cpu0.inst 448595101 # number of ReadReq accesses(hits+misses) 884system.cpu0.icache.ReadReq_accesses::total 448595101 # number of ReadReq accesses(hits+misses) 885system.cpu0.icache.demand_accesses::cpu0.inst 448595101 # number of demand (read+write) accesses 886system.cpu0.icache.demand_accesses::total 448595101 # number of demand (read+write) accesses 887system.cpu0.icache.overall_accesses::cpu0.inst 448595101 # number of overall (read+write) accesses 888system.cpu0.icache.overall_accesses::total 448595101 # number of overall (read+write) accesses 889system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011518 # miss rate for ReadReq accesses 890system.cpu0.icache.ReadReq_miss_rate::total 0.011518 # miss rate for ReadReq accesses 891system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011518 # miss rate for demand accesses 892system.cpu0.icache.demand_miss_rate::total 0.011518 # miss rate for demand accesses 893system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011518 # miss rate for overall accesses 894system.cpu0.icache.overall_miss_rate::total 0.011518 # miss rate for overall accesses 895system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10391.679717 # average ReadReq miss latency 896system.cpu0.icache.ReadReq_avg_miss_latency::total 10391.679717 # average ReadReq miss latency 897system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10391.679717 # average overall miss latency 898system.cpu0.icache.demand_avg_miss_latency::total 10391.679717 # average overall miss latency 899system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10391.679717 # average overall miss latency 900system.cpu0.icache.overall_avg_miss_latency::total 10391.679717 # average overall miss latency 901system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 902system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 903system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 904system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 905system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 906system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 907system.cpu0.icache.fast_writes 0 # number of fast writes performed 908system.cpu0.icache.cache_copies 0 # number of cache copies performed 909system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5167088 # number of ReadReq MSHR misses 910system.cpu0.icache.ReadReq_mshr_misses::total 5167088 # number of ReadReq MSHR misses 911system.cpu0.icache.demand_mshr_misses::cpu0.inst 5167088 # number of demand (read+write) MSHR misses 912system.cpu0.icache.demand_mshr_misses::total 5167088 # number of demand (read+write) MSHR misses 913system.cpu0.icache.overall_mshr_misses::cpu0.inst 5167088 # number of overall MSHR misses 914system.cpu0.icache.overall_mshr_misses::total 5167088 # number of overall MSHR misses 915system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 45925261947 # number of ReadReq MSHR miss cycles 916system.cpu0.icache.ReadReq_mshr_miss_latency::total 45925261947 # number of ReadReq MSHR miss cycles 917system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 45925261947 # number of demand (read+write) MSHR miss cycles 918system.cpu0.icache.demand_mshr_miss_latency::total 45925261947 # number of demand (read+write) MSHR miss cycles 919system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 45925261947 # number of overall MSHR miss cycles 920system.cpu0.icache.overall_mshr_miss_latency::total 45925261947 # number of overall MSHR miss cycles 921system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3405609750 # number of ReadReq MSHR uncacheable cycles 922system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3405609750 # number of ReadReq MSHR uncacheable cycles 923system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3405609750 # number of overall MSHR uncacheable cycles 924system.cpu0.icache.overall_mshr_uncacheable_latency::total 3405609750 # number of overall MSHR uncacheable cycles 925system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011518 # mshr miss rate for ReadReq accesses 926system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011518 # mshr miss rate for ReadReq accesses 927system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011518 # mshr miss rate for demand accesses 928system.cpu0.icache.demand_mshr_miss_rate::total 0.011518 # mshr miss rate for demand accesses 929system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011518 # mshr miss rate for overall accesses 930system.cpu0.icache.overall_mshr_miss_rate::total 0.011518 # mshr miss rate for overall accesses 931system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8888.035572 # average ReadReq mshr miss latency 932system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8888.035572 # average ReadReq mshr miss latency 933system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8888.035572 # average overall mshr miss latency 934system.cpu0.icache.demand_avg_mshr_miss_latency::total 8888.035572 # average overall mshr miss latency 935system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8888.035572 # average overall mshr miss latency 936system.cpu0.icache.overall_avg_mshr_miss_latency::total 8888.035572 # average overall mshr miss latency 937system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 938system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 939system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 940system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 941system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 942system.cpu0.l2cache.prefetcher.num_hwpf_issued 7865373 # number of hwpf issued 943system.cpu0.l2cache.prefetcher.pfIdentified 7866135 # number of prefetch candidates identified 944system.cpu0.l2cache.prefetcher.pfBufferHit 648 # number of redundant prefetches already in prefetch queue 945system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 946system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 947system.cpu0.l2cache.prefetcher.pfSpanPage 985913 # number of prefetches not generated due to page crossing 948system.cpu0.l2cache.tags.replacements 2427001 # number of replacements 949system.cpu0.l2cache.tags.tagsinuse 16243.780061 # Cycle average of tags in use 950system.cpu0.l2cache.tags.total_refs 11146490 # Total number of references to valid blocks. 951system.cpu0.l2cache.tags.sampled_refs 2442996 # Sample count of references to valid blocks. 952system.cpu0.l2cache.tags.avg_refs 4.562631 # Average number of references to valid blocks. 953system.cpu0.l2cache.tags.warmup_cycle 4729494500 # Cycle when the warmup percentage was hit. 954system.cpu0.l2cache.tags.occ_blocks::writebacks 7283.700781 # Average occupied blocks per requestor 955system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 78.630524 # Average occupied blocks per requestor 956system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 92.657228 # Average occupied blocks per requestor 957system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3931.432813 # Average occupied blocks per requestor 958system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3992.358247 # Average occupied blocks per requestor 959system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 865.000469 # Average occupied blocks per requestor 960system.cpu0.l2cache.tags.occ_percent::writebacks 0.444562 # Average percentage of cache occupancy 961system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004799 # Average percentage of cache occupancy 962system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005655 # Average percentage of cache occupancy 963system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.239956 # Average percentage of cache occupancy 964system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.243674 # Average percentage of cache occupancy 965system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.052795 # Average percentage of cache occupancy 966system.cpu0.l2cache.tags.occ_percent::total 0.991442 # Average percentage of cache occupancy 967system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1466 # Occupied blocks per task id 968system.cpu0.l2cache.tags.occ_task_id_blocks::1023 72 # Occupied blocks per task id 969system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14457 # Occupied blocks per task id 970system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 31 # Occupied blocks per task id 971system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 296 # Occupied blocks per task id 972system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 826 # Occupied blocks per task id 973system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 313 # Occupied blocks per task id 974system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 975system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 23 # Occupied blocks per task id 976system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 41 # Occupied blocks per task id 977system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id 978system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id 979system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 947 # Occupied blocks per task id 980system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4330 # Occupied blocks per task id 981system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6826 # Occupied blocks per task id 982system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2259 # Occupied blocks per task id 983system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.089478 # Percentage of cache occupancy per task id 984system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004395 # Percentage of cache occupancy per task id 985system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.882385 # Percentage of cache occupancy per task id 986system.cpu0.l2cache.tags.tag_accesses 256470983 # Number of tag accesses 987system.cpu0.l2cache.tags.data_accesses 256470983 # Number of data accesses 988system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 224791 # number of ReadReq hits 989system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 150515 # number of ReadReq hits 990system.cpu0.l2cache.ReadReq_hits::cpu0.inst 4652887 # number of ReadReq hits 991system.cpu0.l2cache.ReadReq_hits::cpu0.data 2883530 # number of ReadReq hits 992system.cpu0.l2cache.ReadReq_hits::total 7911723 # number of ReadReq hits 993system.cpu0.l2cache.Writeback_hits::writebacks 3895212 # number of Writeback hits 994system.cpu0.l2cache.Writeback_hits::total 3895212 # number of Writeback hits 995system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 236831 # number of WriteInvalidateReq hits 996system.cpu0.l2cache.WriteInvalidateReq_hits::total 236831 # number of WriteInvalidateReq hits 997system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 106550 # number of UpgradeReq hits 998system.cpu0.l2cache.UpgradeReq_hits::total 106550 # number of UpgradeReq hits 999system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 34358 # number of SCUpgradeReq hits 1000system.cpu0.l2cache.SCUpgradeReq_hits::total 34358 # number of SCUpgradeReq hits 1001system.cpu0.l2cache.ReadExReq_hits::cpu0.data 952634 # number of ReadExReq hits 1002system.cpu0.l2cache.ReadExReq_hits::total 952634 # number of ReadExReq hits 1003system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 224791 # number of demand (read+write) hits 1004system.cpu0.l2cache.demand_hits::cpu0.itb.walker 150515 # number of demand (read+write) hits 1005system.cpu0.l2cache.demand_hits::cpu0.inst 4652887 # number of demand (read+write) hits 1006system.cpu0.l2cache.demand_hits::cpu0.data 3836164 # number of demand (read+write) hits 1007system.cpu0.l2cache.demand_hits::total 8864357 # number of demand (read+write) hits 1008system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 224791 # number of overall hits 1009system.cpu0.l2cache.overall_hits::cpu0.itb.walker 150515 # number of overall hits 1010system.cpu0.l2cache.overall_hits::cpu0.inst 4652887 # number of overall hits 1011system.cpu0.l2cache.overall_hits::cpu0.data 3836164 # number of overall hits 1012system.cpu0.l2cache.overall_hits::total 8864357 # number of overall hits 1013system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10425 # number of ReadReq misses 1014system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9020 # number of ReadReq misses 1015system.cpu0.l2cache.ReadReq_misses::cpu0.inst 514201 # number of ReadReq misses 1016system.cpu0.l2cache.ReadReq_misses::cpu0.data 979370 # number of ReadReq misses 1017system.cpu0.l2cache.ReadReq_misses::total 1513016 # number of ReadReq misses 1018system.cpu0.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses 1019system.cpu0.l2cache.Writeback_misses::total 1 # number of Writeback misses 1020system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 544650 # number of WriteInvalidateReq misses 1021system.cpu0.l2cache.WriteInvalidateReq_misses::total 544650 # number of WriteInvalidateReq misses 1022system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 122779 # number of UpgradeReq misses 1023system.cpu0.l2cache.UpgradeReq_misses::total 122779 # number of UpgradeReq misses 1024system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 166249 # number of SCUpgradeReq misses 1025system.cpu0.l2cache.SCUpgradeReq_misses::total 166249 # number of SCUpgradeReq misses 1026system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 8 # number of SCUpgradeFailReq misses 1027system.cpu0.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses 1028system.cpu0.l2cache.ReadExReq_misses::cpu0.data 253376 # number of ReadExReq misses 1029system.cpu0.l2cache.ReadExReq_misses::total 253376 # number of ReadExReq misses 1030system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10425 # number of demand (read+write) misses 1031system.cpu0.l2cache.demand_misses::cpu0.itb.walker 9020 # number of demand (read+write) misses 1032system.cpu0.l2cache.demand_misses::cpu0.inst 514201 # number of demand (read+write) misses 1033system.cpu0.l2cache.demand_misses::cpu0.data 1232746 # number of demand (read+write) misses 1034system.cpu0.l2cache.demand_misses::total 1766392 # number of demand (read+write) misses 1035system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10425 # number of overall misses 1036system.cpu0.l2cache.overall_misses::cpu0.itb.walker 9020 # number of overall misses 1037system.cpu0.l2cache.overall_misses::cpu0.inst 514201 # number of overall misses 1038system.cpu0.l2cache.overall_misses::cpu0.data 1232746 # number of overall misses 1039system.cpu0.l2cache.overall_misses::total 1766392 # number of overall misses 1040system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 401624493 # number of ReadReq miss cycles 1041system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 376564494 # number of ReadReq miss cycles 1042system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 15423284566 # number of ReadReq miss cycles 1043system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 32417465776 # number of ReadReq miss cycles 1044system.cpu0.l2cache.ReadReq_miss_latency::total 48618939329 # number of ReadReq miss cycles 1045system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 194184961 # number of WriteInvalidateReq miss cycles 1046system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 194184961 # number of WriteInvalidateReq miss cycles 1047system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2456096364 # number of UpgradeReq miss cycles 1048system.cpu0.l2cache.UpgradeReq_miss_latency::total 2456096364 # number of UpgradeReq miss cycles 1049system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3361972231 # number of SCUpgradeReq miss cycles 1050system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3361972231 # number of SCUpgradeReq miss cycles 1051system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2084000 # number of SCUpgradeFailReq miss cycles 1052system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2084000 # number of SCUpgradeFailReq miss cycles 1053system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 11515878505 # number of ReadExReq miss cycles 1054system.cpu0.l2cache.ReadExReq_miss_latency::total 11515878505 # number of ReadExReq miss cycles 1055system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 401624493 # number of demand (read+write) miss cycles 1056system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 376564494 # number of demand (read+write) miss cycles 1057system.cpu0.l2cache.demand_miss_latency::cpu0.inst 15423284566 # number of demand (read+write) miss cycles 1058system.cpu0.l2cache.demand_miss_latency::cpu0.data 43933344281 # number of demand (read+write) miss cycles 1059system.cpu0.l2cache.demand_miss_latency::total 60134817834 # number of demand (read+write) miss cycles 1060system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 401624493 # number of overall miss cycles 1061system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 376564494 # number of overall miss cycles 1062system.cpu0.l2cache.overall_miss_latency::cpu0.inst 15423284566 # number of overall miss cycles 1063system.cpu0.l2cache.overall_miss_latency::cpu0.data 43933344281 # number of overall miss cycles 1064system.cpu0.l2cache.overall_miss_latency::total 60134817834 # number of overall miss cycles 1065system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 235216 # number of ReadReq accesses(hits+misses) 1066system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 159535 # number of ReadReq accesses(hits+misses) 1067system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 5167088 # number of ReadReq accesses(hits+misses) 1068system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3862900 # number of ReadReq accesses(hits+misses) 1069system.cpu0.l2cache.ReadReq_accesses::total 9424739 # number of ReadReq accesses(hits+misses) 1070system.cpu0.l2cache.Writeback_accesses::writebacks 3895213 # number of Writeback accesses(hits+misses) 1071system.cpu0.l2cache.Writeback_accesses::total 3895213 # number of Writeback accesses(hits+misses) 1072system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 781481 # number of WriteInvalidateReq accesses(hits+misses) 1073system.cpu0.l2cache.WriteInvalidateReq_accesses::total 781481 # number of WriteInvalidateReq accesses(hits+misses) 1074system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 229329 # number of UpgradeReq accesses(hits+misses) 1075system.cpu0.l2cache.UpgradeReq_accesses::total 229329 # number of UpgradeReq accesses(hits+misses) 1076system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 200607 # number of SCUpgradeReq accesses(hits+misses) 1077system.cpu0.l2cache.SCUpgradeReq_accesses::total 200607 # number of SCUpgradeReq accesses(hits+misses) 1078system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 8 # number of SCUpgradeFailReq accesses(hits+misses) 1079system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses) 1080system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1206010 # number of ReadExReq accesses(hits+misses) 1081system.cpu0.l2cache.ReadExReq_accesses::total 1206010 # number of ReadExReq accesses(hits+misses) 1082system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 235216 # number of demand (read+write) accesses 1083system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 159535 # number of demand (read+write) accesses 1084system.cpu0.l2cache.demand_accesses::cpu0.inst 5167088 # number of demand (read+write) accesses 1085system.cpu0.l2cache.demand_accesses::cpu0.data 5068910 # number of demand (read+write) accesses 1086system.cpu0.l2cache.demand_accesses::total 10630749 # number of demand (read+write) accesses 1087system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 235216 # number of overall (read+write) accesses 1088system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 159535 # number of overall (read+write) accesses 1089system.cpu0.l2cache.overall_accesses::cpu0.inst 5167088 # number of overall (read+write) accesses 1090system.cpu0.l2cache.overall_accesses::cpu0.data 5068910 # number of overall (read+write) accesses 1091system.cpu0.l2cache.overall_accesses::total 10630749 # number of overall (read+write) accesses 1092system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.044321 # miss rate for ReadReq accesses 1093system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.056539 # miss rate for ReadReq accesses 1094system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.099515 # miss rate for ReadReq accesses 1095system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.253532 # miss rate for ReadReq accesses 1096system.cpu0.l2cache.ReadReq_miss_rate::total 0.160537 # miss rate for ReadReq accesses 1097system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses 1098system.cpu0.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses 1099system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.696946 # miss rate for WriteInvalidateReq accesses 1100system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.696946 # miss rate for WriteInvalidateReq accesses 1101system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.535384 # miss rate for UpgradeReq accesses 1102system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.535384 # miss rate for UpgradeReq accesses 1103system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.828730 # miss rate for SCUpgradeReq accesses 1104system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.828730 # miss rate for SCUpgradeReq accesses 1105system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1106system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1107system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.210094 # miss rate for ReadExReq accesses 1108system.cpu0.l2cache.ReadExReq_miss_rate::total 0.210094 # miss rate for ReadExReq accesses 1109system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.044321 # miss rate for demand accesses 1110system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.056539 # miss rate for demand accesses 1111system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.099515 # miss rate for demand accesses 1112system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.243197 # miss rate for demand accesses 1113system.cpu0.l2cache.demand_miss_rate::total 0.166159 # miss rate for demand accesses 1114system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.044321 # miss rate for overall accesses 1115system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.056539 # miss rate for overall accesses 1116system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.099515 # miss rate for overall accesses 1117system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.243197 # miss rate for overall accesses 1118system.cpu0.l2cache.overall_miss_rate::total 0.166159 # miss rate for overall accesses 1119system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 38525.131223 # average ReadReq miss latency 1120system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 41747.726608 # average ReadReq miss latency 1121system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 29994.660777 # average ReadReq miss latency 1122system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 33100.325491 # average ReadReq miss latency 1123system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32133.790607 # average ReadReq miss latency 1124system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 356.531646 # average WriteInvalidateReq miss latency 1125system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 356.531646 # average WriteInvalidateReq miss latency 1126system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 20004.205638 # average UpgradeReq miss latency 1127system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 20004.205638 # average UpgradeReq miss latency 1128system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20222.510999 # average SCUpgradeReq miss latency 1129system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20222.510999 # average SCUpgradeReq miss latency 1130system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 260500 # average SCUpgradeFailReq miss latency 1131system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 260500 # average SCUpgradeFailReq miss latency 1132system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 45449.760455 # average ReadExReq miss latency 1133system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 45449.760455 # average ReadExReq miss latency 1134system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 38525.131223 # average overall miss latency 1135system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 41747.726608 # average overall miss latency 1136system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 29994.660777 # average overall miss latency 1137system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35638.602178 # average overall miss latency 1138system.cpu0.l2cache.demand_avg_miss_latency::total 34043.868991 # average overall miss latency 1139system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 38525.131223 # average overall miss latency 1140system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 41747.726608 # average overall miss latency 1141system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 29994.660777 # average overall miss latency 1142system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35638.602178 # average overall miss latency 1143system.cpu0.l2cache.overall_avg_miss_latency::total 34043.868991 # average overall miss latency 1144system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1145system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1146system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1147system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1148system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1149system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1150system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1151system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1152system.cpu0.l2cache.writebacks::writebacks 1390929 # number of writebacks 1153system.cpu0.l2cache.writebacks::total 1390929 # number of writebacks 1154system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 412 # number of ReadReq MSHR hits 1155system.cpu0.l2cache.ReadReq_mshr_hits::total 412 # number of ReadReq MSHR hits 1156system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5653 # number of ReadExReq MSHR hits 1157system.cpu0.l2cache.ReadExReq_mshr_hits::total 5653 # number of ReadExReq MSHR hits 1158system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6065 # number of demand (read+write) MSHR hits 1159system.cpu0.l2cache.demand_mshr_hits::total 6065 # number of demand (read+write) MSHR hits 1160system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6065 # number of overall MSHR hits 1161system.cpu0.l2cache.overall_mshr_hits::total 6065 # number of overall MSHR hits 1162system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 10425 # number of ReadReq MSHR misses 1163system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 9020 # number of ReadReq MSHR misses 1164system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 514201 # number of ReadReq MSHR misses 1165system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 978958 # number of ReadReq MSHR misses 1166system.cpu0.l2cache.ReadReq_mshr_misses::total 1512604 # number of ReadReq MSHR misses 1167system.cpu0.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses 1168system.cpu0.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses 1169system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 705771 # number of HardPFReq MSHR misses 1170system.cpu0.l2cache.HardPFReq_mshr_misses::total 705771 # number of HardPFReq MSHR misses 1171system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 544650 # number of WriteInvalidateReq MSHR misses 1172system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 544650 # number of WriteInvalidateReq MSHR misses 1173system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 122779 # number of UpgradeReq MSHR misses 1174system.cpu0.l2cache.UpgradeReq_mshr_misses::total 122779 # number of UpgradeReq MSHR misses 1175system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 166249 # number of SCUpgradeReq MSHR misses 1176system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 166249 # number of SCUpgradeReq MSHR misses 1177system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 8 # number of SCUpgradeFailReq MSHR misses 1178system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses 1179system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 247723 # number of ReadExReq MSHR misses 1180system.cpu0.l2cache.ReadExReq_mshr_misses::total 247723 # number of ReadExReq MSHR misses 1181system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 10425 # number of demand (read+write) MSHR misses 1182system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 9020 # number of demand (read+write) MSHR misses 1183system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 514201 # number of demand (read+write) MSHR misses 1184system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1226681 # number of demand (read+write) MSHR misses 1185system.cpu0.l2cache.demand_mshr_misses::total 1760327 # number of demand (read+write) MSHR misses 1186system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 10425 # number of overall MSHR misses 1187system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 9020 # number of overall MSHR misses 1188system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 514201 # number of overall MSHR misses 1189system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1226681 # number of overall MSHR misses 1190system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 705771 # number of overall MSHR misses 1191system.cpu0.l2cache.overall_mshr_misses::total 2466098 # number of overall MSHR misses 1192system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 327932509 # number of ReadReq MSHR miss cycles 1193system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 312733504 # number of ReadReq MSHR miss cycles 1194system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 11805310434 # number of ReadReq MSHR miss cycles 1195system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 25478803206 # number of ReadReq MSHR miss cycles 1196system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 37924779653 # number of ReadReq MSHR miss cycles 1197system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 34882867408 # number of HardPFReq MSHR miss cycles 1198system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 34882867408 # number of HardPFReq MSHR miss cycles 1199system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 18696199399 # number of WriteInvalidateReq MSHR miss cycles 1200system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 18696199399 # number of WriteInvalidateReq MSHR miss cycles 1201system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2085589258 # number of UpgradeReq MSHR miss cycles 1202system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2085589258 # number of UpgradeReq MSHR miss cycles 1203system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2284466860 # number of SCUpgradeReq MSHR miss cycles 1204system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2284466860 # number of SCUpgradeReq MSHR miss cycles 1205system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1713000 # number of SCUpgradeFailReq MSHR miss cycles 1206system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1713000 # number of SCUpgradeFailReq MSHR miss cycles 1207system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 9147060396 # number of ReadExReq MSHR miss cycles 1208system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 9147060396 # number of ReadExReq MSHR miss cycles 1209system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 327932509 # number of demand (read+write) MSHR miss cycles 1210system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 312733504 # number of demand (read+write) MSHR miss cycles 1211system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 11805310434 # number of demand (read+write) MSHR miss cycles 1212system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 34625863602 # number of demand (read+write) MSHR miss cycles 1213system.cpu0.l2cache.demand_mshr_miss_latency::total 47071840049 # number of demand (read+write) MSHR miss cycles 1214system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 327932509 # number of overall MSHR miss cycles 1215system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 312733504 # number of overall MSHR miss cycles 1216system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 11805310434 # number of overall MSHR miss cycles 1217system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 34625863602 # number of overall MSHR miss cycles 1218system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 34882867408 # number of overall MSHR miss cycles 1219system.cpu0.l2cache.overall_mshr_miss_latency::total 81954707457 # number of overall MSHR miss cycles 1220system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3061864750 # number of ReadReq MSHR uncacheable cycles 1221system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2174725243 # number of ReadReq MSHR uncacheable cycles 1222system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5236589993 # number of ReadReq MSHR uncacheable cycles 1223system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2129495502 # number of WriteReq MSHR uncacheable cycles 1224system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2129495502 # number of WriteReq MSHR uncacheable cycles 1225system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3061864750 # number of overall MSHR uncacheable cycles 1226system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4304220745 # number of overall MSHR uncacheable cycles 1227system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7366085495 # number of overall MSHR uncacheable cycles 1228system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.044321 # mshr miss rate for ReadReq accesses 1229system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.056539 # mshr miss rate for ReadReq accesses 1230system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.099515 # mshr miss rate for ReadReq accesses 1231system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.253426 # mshr miss rate for ReadReq accesses 1232system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.160493 # mshr miss rate for ReadReq accesses 1233system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses 1234system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses 1235system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1236system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1237system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.696946 # mshr miss rate for WriteInvalidateReq accesses 1238system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.696946 # mshr miss rate for WriteInvalidateReq accesses 1239system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.535384 # mshr miss rate for UpgradeReq accesses 1240system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.535384 # mshr miss rate for UpgradeReq accesses 1241system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.828730 # mshr miss rate for SCUpgradeReq accesses 1242system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.828730 # mshr miss rate for SCUpgradeReq accesses 1243system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1244system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1245system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.205407 # mshr miss rate for ReadExReq accesses 1246system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.205407 # mshr miss rate for ReadExReq accesses 1247system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.044321 # mshr miss rate for demand accesses 1248system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.056539 # mshr miss rate for demand accesses 1249system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.099515 # mshr miss rate for demand accesses 1250system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.242001 # mshr miss rate for demand accesses 1251system.cpu0.l2cache.demand_mshr_miss_rate::total 0.165588 # mshr miss rate for demand accesses 1252system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.044321 # mshr miss rate for overall accesses 1253system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.056539 # mshr miss rate for overall accesses 1254system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.099515 # mshr miss rate for overall accesses 1255system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.242001 # mshr miss rate for overall accesses 1256system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1257system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231978 # mshr miss rate for overall accesses 1258system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 31456.355779 # average ReadReq mshr miss latency 1259system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34671.120177 # average ReadReq mshr miss latency 1260system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22958.552072 # average ReadReq mshr miss latency 1261system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 26026.451805 # average ReadReq mshr miss latency 1262system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25072.510487 # average ReadReq mshr miss latency 1263system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49425.192319 # average HardPFReq mshr miss latency 1264system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49425.192319 # average HardPFReq mshr miss latency 1265system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 34326.997887 # average WriteInvalidateReq mshr miss latency 1266system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 34326.997887 # average WriteInvalidateReq mshr miss latency 1267system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16986.530742 # average UpgradeReq mshr miss latency 1268system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16986.530742 # average UpgradeReq mshr miss latency 1269system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13741.236699 # average SCUpgradeReq mshr miss latency 1270system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13741.236699 # average SCUpgradeReq mshr miss latency 1271system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 214125 # average SCUpgradeFailReq mshr miss latency 1272system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 214125 # average SCUpgradeFailReq mshr miss latency 1273system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 36924.550389 # average ReadExReq mshr miss latency 1274system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36924.550389 # average ReadExReq mshr miss latency 1275system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 31456.355779 # average overall mshr miss latency 1276system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34671.120177 # average overall mshr miss latency 1277system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22958.552072 # average overall mshr miss latency 1278system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28227.276368 # average overall mshr miss latency 1279system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26740.395420 # average overall mshr miss latency 1280system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 31456.355779 # average overall mshr miss latency 1281system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34671.120177 # average overall mshr miss latency 1282system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22958.552072 # average overall mshr miss latency 1283system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28227.276368 # average overall mshr miss latency 1284system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49425.192319 # average overall mshr miss latency 1285system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33232.542850 # average overall mshr miss latency 1286system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1287system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1288system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1289system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1290system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1291system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1292system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1293system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1294system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1295system.cpu0.toL2Bus.trans_dist::ReadReq 11541292 # Transaction distribution 1296system.cpu0.toL2Bus.trans_dist::ReadResp 9690709 # Transaction distribution 1297system.cpu0.toL2Bus.trans_dist::WriteReq 15329 # Transaction distribution 1298system.cpu0.toL2Bus.trans_dist::WriteResp 15329 # Transaction distribution 1299system.cpu0.toL2Bus.trans_dist::Writeback 3895213 # Transaction distribution 1300system.cpu0.toL2Bus.trans_dist::HardPFReq 1069383 # Transaction distribution 1301system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1166255 # Transaction distribution 1302system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 781481 # Transaction distribution 1303system.cpu0.toL2Bus.trans_dist::UpgradeReq 444610 # Transaction distribution 1304system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 368177 # Transaction distribution 1305system.cpu0.toL2Bus.trans_dist::UpgradeResp 498972 # Transaction distribution 1306system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 55 # Transaction distribution 1307system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution 1308system.cpu0.toL2Bus.trans_dist::ReadExReq 1328849 # Transaction distribution 1309system.cpu0.toL2Bus.trans_dist::ReadExResp 1215209 # Transaction distribution 1310system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 10420426 # Packet count per connected master and slave (bytes) 1311system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16690518 # Packet count per connected master and slave (bytes) 1312system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 351532 # Packet count per connected master and slave (bytes) 1313system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 549297 # Packet count per connected master and slave (bytes) 1314system.cpu0.toL2Bus.pkt_count::total 28011773 # Packet count per connected master and slave (bytes) 1315system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 330866132 # Cumulative packet size per connected master and slave (bytes) 1316system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 630631769 # Cumulative packet size per connected master and slave (bytes) 1317system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1276280 # Cumulative packet size per connected master and slave (bytes) 1318system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1881728 # Cumulative packet size per connected master and slave (bytes) 1319system.cpu0.toL2Bus.pkt_size::total 964655909 # Cumulative packet size per connected master and slave (bytes) 1320system.cpu0.toL2Bus.snoops 4194903 # Total snoops (count) 1321system.cpu0.toL2Bus.snoop_fanout::samples 19756578 # Request fanout histogram 1322system.cpu0.toL2Bus.snoop_fanout::mean 5.197801 # Request fanout histogram 1323system.cpu0.toL2Bus.snoop_fanout::stdev 0.398341 # Request fanout histogram 1324system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1325system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1326system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1327system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1328system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1329system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1330system.cpu0.toL2Bus.snoop_fanout::5 15848715 80.22% 80.22% # Request fanout histogram 1331system.cpu0.toL2Bus.snoop_fanout::6 3907863 19.78% 100.00% # Request fanout histogram 1332system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1333system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1334system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1335system.cpu0.toL2Bus.snoop_fanout::total 19756578 # Request fanout histogram 1336system.cpu0.toL2Bus.reqLayer0.occupancy 12645685295 # Layer occupancy (ticks) 1337system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 1338system.cpu0.toL2Bus.snoopLayer0.occupancy 194485993 # Layer occupancy (ticks) 1339system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1340system.cpu0.toL2Bus.respLayer0.occupancy 7813325558 # Layer occupancy (ticks) 1341system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1342system.cpu0.toL2Bus.respLayer1.occupancy 8298663367 # Layer occupancy (ticks) 1343system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1344system.cpu0.toL2Bus.respLayer2.occupancy 192341003 # Layer occupancy (ticks) 1345system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1346system.cpu0.toL2Bus.respLayer3.occupancy 314436506 # Layer occupancy (ticks) 1347system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1348system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1349system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1350system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1351system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1352system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1353system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1354system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1355system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1356system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1357system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1358system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1359system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1360system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1361system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1362system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1363system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1364system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1365system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1366system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1367system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1368system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1369system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1370system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1371system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1372system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1373system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1374system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1375system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1376system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1377system.cpu1.dtb.walker.walks 99527 # Table walker walks requested 1378system.cpu1.dtb.walker.walksLong 99527 # Table walker walks initiated with long descriptors 1379system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9603 # Level at which table walker walks with long descriptors terminate 1380system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 74573 # Level at which table walker walks with long descriptors terminate 1381system.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting 1382system.cpu1.dtb.walker.walkWaitTime::samples 99518 # Table walker wait (enqueue to first request) latency 1383system.cpu1.dtb.walker.walkWaitTime::mean 0.271308 # Table walker wait (enqueue to first request) latency 1384system.cpu1.dtb.walker.walkWaitTime::stdev 67.169326 # Table walker wait (enqueue to first request) latency 1385system.cpu1.dtb.walker.walkWaitTime::0-2047 99516 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1386system.cpu1.dtb.walker.walkWaitTime::6144-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1387system.cpu1.dtb.walker.walkWaitTime::18432-20479 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1388system.cpu1.dtb.walker.walkWaitTime::total 99518 # Table walker wait (enqueue to first request) latency 1389system.cpu1.dtb.walker.walkCompletionTime::samples 84185 # Table walker service (enqueue to completion) latency 1390system.cpu1.dtb.walker.walkCompletionTime::mean 16581.674289 # Table walker service (enqueue to completion) latency 1391system.cpu1.dtb.walker.walkCompletionTime::gmean 15037.130908 # Table walker service (enqueue to completion) latency 1392system.cpu1.dtb.walker.walkCompletionTime::stdev 10932.627488 # Table walker service (enqueue to completion) latency 1393system.cpu1.dtb.walker.walkCompletionTime::0-32767 81471 96.78% 96.78% # Table walker service (enqueue to completion) latency 1394system.cpu1.dtb.walker.walkCompletionTime::32768-65535 2185 2.60% 99.37% # Table walker service (enqueue to completion) latency 1395system.cpu1.dtb.walker.walkCompletionTime::65536-98303 285 0.34% 99.71% # Table walker service (enqueue to completion) latency 1396system.cpu1.dtb.walker.walkCompletionTime::98304-131071 159 0.19% 99.90% # Table walker service (enqueue to completion) latency 1397system.cpu1.dtb.walker.walkCompletionTime::131072-163839 19 0.02% 99.92% # Table walker service (enqueue to completion) latency 1398system.cpu1.dtb.walker.walkCompletionTime::163840-196607 14 0.02% 99.94% # Table walker service (enqueue to completion) latency 1399system.cpu1.dtb.walker.walkCompletionTime::196608-229375 18 0.02% 99.96% # Table walker service (enqueue to completion) latency 1400system.cpu1.dtb.walker.walkCompletionTime::229376-262143 4 0.00% 99.96% # Table walker service (enqueue to completion) latency 1401system.cpu1.dtb.walker.walkCompletionTime::262144-294911 15 0.02% 99.98% # Table walker service (enqueue to completion) latency 1402system.cpu1.dtb.walker.walkCompletionTime::294912-327679 5 0.01% 99.99% # Table walker service (enqueue to completion) latency 1403system.cpu1.dtb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency 1404system.cpu1.dtb.walker.walkCompletionTime::360448-393215 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 1405system.cpu1.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1406system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1407system.cpu1.dtb.walker.walkCompletionTime::total 84185 # Table walker service (enqueue to completion) latency 1408system.cpu1.dtb.walker.walksPending::samples -1589468256 # Table walker pending requests distribution 1409system.cpu1.dtb.walker.walksPending::mean 0.778279 # Table walker pending requests distribution 1410system.cpu1.dtb.walker.walksPending::stdev 0.415405 # Table walker pending requests distribution 1411system.cpu1.dtb.walker.walksPending::0 -352419148 22.17% 22.17% # Table walker pending requests distribution 1412system.cpu1.dtb.walker.walksPending::1 -1237049108 77.83% 100.00% # Table walker pending requests distribution 1413system.cpu1.dtb.walker.walksPending::total -1589468256 # Table walker pending requests distribution 1414system.cpu1.dtb.walker.walkPageSizes::4K 74574 88.59% 88.59% # Table walker page sizes translated 1415system.cpu1.dtb.walker.walkPageSizes::2M 9603 11.41% 100.00% # Table walker page sizes translated 1416system.cpu1.dtb.walker.walkPageSizes::total 84177 # Table walker page sizes translated 1417system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 99527 # Table walker requests started/completed, data/inst 1418system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1419system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 99527 # Table walker requests started/completed, data/inst 1420system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 84177 # Table walker requests started/completed, data/inst 1421system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1422system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 84177 # Table walker requests started/completed, data/inst 1423system.cpu1.dtb.walker.walkRequestOrigin::total 183704 # Table walker requests started/completed, data/inst 1424system.cpu1.dtb.inst_hits 0 # ITB inst hits 1425system.cpu1.dtb.inst_misses 0 # ITB inst misses 1426system.cpu1.dtb.read_hits 83767099 # DTB read hits 1427system.cpu1.dtb.read_misses 74857 # DTB read misses 1428system.cpu1.dtb.write_hits 75685520 # DTB write hits 1429system.cpu1.dtb.write_misses 24670 # DTB write misses 1430system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1431system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1432system.cpu1.dtb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID 1433system.cpu1.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID 1434system.cpu1.dtb.flush_entries 36584 # Number of entries that have been flushed from TLB 1435system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 1436system.cpu1.dtb.prefetch_faults 4104 # Number of TLB faults due to prefetch 1437system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1438system.cpu1.dtb.perms_faults 9015 # Number of TLB faults due to permissions restrictions 1439system.cpu1.dtb.read_accesses 83841956 # DTB read accesses 1440system.cpu1.dtb.write_accesses 75710190 # DTB write accesses 1441system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1442system.cpu1.dtb.hits 159452619 # DTB hits 1443system.cpu1.dtb.misses 99527 # DTB misses 1444system.cpu1.dtb.accesses 159552146 # DTB accesses 1445system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1446system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1447system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1448system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1449system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1450system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1451system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1452system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1453system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1454system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1455system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1456system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1457system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1458system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1459system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1460system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1461system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1462system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1463system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1464system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1465system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1466system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1467system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1468system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1469system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1470system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1471system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1472system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1473system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1474system.cpu1.itb.walker.walks 55326 # Table walker walks requested 1475system.cpu1.itb.walker.walksLong 55326 # Table walker walks initiated with long descriptors 1476system.cpu1.itb.walker.walksLongTerminationLevel::Level2 571 # Level at which table walker walks with long descriptors terminate 1477system.cpu1.itb.walker.walksLongTerminationLevel::Level3 49211 # Level at which table walker walks with long descriptors terminate 1478system.cpu1.itb.walker.walkWaitTime::samples 55326 # Table walker wait (enqueue to first request) latency 1479system.cpu1.itb.walker.walkWaitTime::0 55326 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1480system.cpu1.itb.walker.walkWaitTime::total 55326 # Table walker wait (enqueue to first request) latency 1481system.cpu1.itb.walker.walkCompletionTime::samples 49782 # Table walker service (enqueue to completion) latency 1482system.cpu1.itb.walker.walkCompletionTime::mean 18533.691816 # Table walker service (enqueue to completion) latency 1483system.cpu1.itb.walker.walkCompletionTime::gmean 16693.913266 # Table walker service (enqueue to completion) latency 1484system.cpu1.itb.walker.walkCompletionTime::stdev 13345.941074 # Table walker service (enqueue to completion) latency 1485system.cpu1.itb.walker.walkCompletionTime::0-32767 47101 94.61% 94.61% # Table walker service (enqueue to completion) latency 1486system.cpu1.itb.walker.walkCompletionTime::32768-65535 2168 4.35% 98.97% # Table walker service (enqueue to completion) latency 1487system.cpu1.itb.walker.walkCompletionTime::65536-98303 178 0.36% 99.33% # Table walker service (enqueue to completion) latency 1488system.cpu1.itb.walker.walkCompletionTime::98304-131071 248 0.50% 99.83% # Table walker service (enqueue to completion) latency 1489system.cpu1.itb.walker.walkCompletionTime::131072-163839 12 0.02% 99.85% # Table walker service (enqueue to completion) latency 1490system.cpu1.itb.walker.walkCompletionTime::163840-196607 16 0.03% 99.88% # Table walker service (enqueue to completion) latency 1491system.cpu1.itb.walker.walkCompletionTime::196608-229375 24 0.05% 99.93% # Table walker service (enqueue to completion) latency 1492system.cpu1.itb.walker.walkCompletionTime::229376-262143 6 0.01% 99.94% # Table walker service (enqueue to completion) latency 1493system.cpu1.itb.walker.walkCompletionTime::262144-294911 18 0.04% 99.98% # Table walker service (enqueue to completion) latency 1494system.cpu1.itb.walker.walkCompletionTime::294912-327679 3 0.01% 99.98% # Table walker service (enqueue to completion) latency 1495system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency 1496system.cpu1.itb.walker.walkCompletionTime::360448-393215 3 0.01% 100.00% # Table walker service (enqueue to completion) latency 1497system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1498system.cpu1.itb.walker.walkCompletionTime::total 49782 # Table walker service (enqueue to completion) latency 1499system.cpu1.itb.walker.walksPending::samples -1199136648 # Table walker pending requests distribution 1500system.cpu1.itb.walker.walksPending::0 -1199136648 100.00% 100.00% # Table walker pending requests distribution 1501system.cpu1.itb.walker.walksPending::total -1199136648 # Table walker pending requests distribution 1502system.cpu1.itb.walker.walkPageSizes::4K 49211 98.85% 98.85% # Table walker page sizes translated 1503system.cpu1.itb.walker.walkPageSizes::2M 571 1.15% 100.00% # Table walker page sizes translated 1504system.cpu1.itb.walker.walkPageSizes::total 49782 # Table walker page sizes translated 1505system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1506system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 55326 # Table walker requests started/completed, data/inst 1507system.cpu1.itb.walker.walkRequestOrigin_Requested::total 55326 # Table walker requests started/completed, data/inst 1508system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1509system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 49782 # Table walker requests started/completed, data/inst 1510system.cpu1.itb.walker.walkRequestOrigin_Completed::total 49782 # Table walker requests started/completed, data/inst 1511system.cpu1.itb.walker.walkRequestOrigin::total 105108 # Table walker requests started/completed, data/inst 1512system.cpu1.itb.inst_hits 441493680 # ITB inst hits 1513system.cpu1.itb.inst_misses 55326 # ITB inst misses 1514system.cpu1.itb.read_hits 0 # DTB read hits 1515system.cpu1.itb.read_misses 0 # DTB read misses 1516system.cpu1.itb.write_hits 0 # DTB write hits 1517system.cpu1.itb.write_misses 0 # DTB write misses 1518system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1519system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1520system.cpu1.itb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID 1521system.cpu1.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID 1522system.cpu1.itb.flush_entries 25739 # Number of entries that have been flushed from TLB 1523system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1524system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1525system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1526system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1527system.cpu1.itb.read_accesses 0 # DTB read accesses 1528system.cpu1.itb.write_accesses 0 # DTB write accesses 1529system.cpu1.itb.inst_accesses 441549006 # ITB inst accesses 1530system.cpu1.itb.hits 441493680 # DTB hits 1531system.cpu1.itb.misses 55326 # DTB misses 1532system.cpu1.itb.accesses 441549006 # DTB accesses 1533system.cpu1.numCycles 94821563303 # number of cpu cycles simulated 1534system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1535system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1536system.cpu1.committedInsts 441187041 # Number of instructions committed 1537system.cpu1.committedOps 519063105 # Number of ops (including micro ops) committed 1538system.cpu1.num_int_alu_accesses 477531543 # Number of integer alu accesses 1539system.cpu1.num_fp_alu_accesses 364386 # Number of float alu accesses 1540system.cpu1.num_func_calls 26570520 # number of times a function call or return occured 1541system.cpu1.num_conditional_control_insts 66815511 # number of instructions that are conditional controls 1542system.cpu1.num_int_insts 477531543 # number of integer instructions 1543system.cpu1.num_fp_insts 364386 # number of float instructions 1544system.cpu1.num_int_register_reads 690361032 # number of times the integer registers were read 1545system.cpu1.num_int_register_writes 378560518 # number of times the integer registers were written 1546system.cpu1.num_fp_register_reads 602629 # number of times the floating registers were read 1547system.cpu1.num_fp_register_writes 273816 # number of times the floating registers were written 1548system.cpu1.num_cc_register_reads 113424708 # number of times the CC registers were read 1549system.cpu1.num_cc_register_writes 113111436 # number of times the CC registers were written 1550system.cpu1.num_mem_refs 159443034 # number of memory refs 1551system.cpu1.num_load_insts 83763663 # Number of load instructions 1552system.cpu1.num_store_insts 75679371 # Number of store instructions 1553system.cpu1.num_idle_cycles 93795188251.508850 # Number of idle cycles 1554system.cpu1.num_busy_cycles 1026375051.491154 # Number of busy cycles 1555system.cpu1.not_idle_fraction 0.010824 # Percentage of non-idle cycles 1556system.cpu1.idle_fraction 0.989176 # Percentage of idle cycles 1557system.cpu1.Branches 98214896 # Number of branches fetched 1558system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 1559system.cpu1.op_class::IntAlu 358777055 69.08% 69.08% # Class of executed instruction 1560system.cpu1.op_class::IntMult 1052972 0.20% 69.28% # Class of executed instruction 1561system.cpu1.op_class::IntDiv 61499 0.01% 69.29% # Class of executed instruction 1562system.cpu1.op_class::FloatAdd 0 0.00% 69.29% # Class of executed instruction 1563system.cpu1.op_class::FloatCmp 0 0.00% 69.29% # Class of executed instruction 1564system.cpu1.op_class::FloatCvt 0 0.00% 69.29% # Class of executed instruction 1565system.cpu1.op_class::FloatMult 0 0.00% 69.29% # Class of executed instruction 1566system.cpu1.op_class::FloatDiv 0 0.00% 69.29% # Class of executed instruction 1567system.cpu1.op_class::FloatSqrt 0 0.00% 69.29% # Class of executed instruction 1568system.cpu1.op_class::SimdAdd 0 0.00% 69.29% # Class of executed instruction 1569system.cpu1.op_class::SimdAddAcc 0 0.00% 69.29% # Class of executed instruction 1570system.cpu1.op_class::SimdAlu 0 0.00% 69.29% # Class of executed instruction 1571system.cpu1.op_class::SimdCmp 0 0.00% 69.29% # Class of executed instruction 1572system.cpu1.op_class::SimdCvt 0 0.00% 69.29% # Class of executed instruction 1573system.cpu1.op_class::SimdMisc 0 0.00% 69.29% # Class of executed instruction 1574system.cpu1.op_class::SimdMult 0 0.00% 69.29% # Class of executed instruction 1575system.cpu1.op_class::SimdMultAcc 0 0.00% 69.29% # Class of executed instruction 1576system.cpu1.op_class::SimdShift 0 0.00% 69.29% # Class of executed instruction 1577system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.29% # Class of executed instruction 1578system.cpu1.op_class::SimdSqrt 0 0.00% 69.29% # Class of executed instruction 1579system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.29% # Class of executed instruction 1580system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.29% # Class of executed instruction 1581system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.29% # Class of executed instruction 1582system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.29% # Class of executed instruction 1583system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.29% # Class of executed instruction 1584system.cpu1.op_class::SimdFloatMisc 35293 0.01% 69.30% # Class of executed instruction 1585system.cpu1.op_class::SimdFloatMult 0 0.00% 69.30% # Class of executed instruction 1586system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.30% # Class of executed instruction 1587system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.30% # Class of executed instruction 1588system.cpu1.op_class::MemRead 83763663 16.13% 85.43% # Class of executed instruction 1589system.cpu1.op_class::MemWrite 75679371 14.57% 100.00% # Class of executed instruction 1590system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1591system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 1592system.cpu1.op_class::total 519369853 # Class of executed instruction 1593system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1594system.cpu1.kern.inst.quiesce 13999 # number of quiesce instructions executed 1595system.cpu1.dcache.tags.replacements 4977655 # number of replacements 1596system.cpu1.dcache.tags.tagsinuse 421.597899 # Cycle average of tags in use 1597system.cpu1.dcache.tags.total_refs 154271186 # Total number of references to valid blocks. 1598system.cpu1.dcache.tags.sampled_refs 4978165 # Sample count of references to valid blocks. 1599system.cpu1.dcache.tags.avg_refs 30.989569 # Average number of references to valid blocks. 1600system.cpu1.dcache.tags.warmup_cycle 8379002972500 # Cycle when the warmup percentage was hit. 1601system.cpu1.dcache.tags.occ_blocks::cpu1.data 421.597899 # Average occupied blocks per requestor 1602system.cpu1.dcache.tags.occ_percent::cpu1.data 0.823433 # Average percentage of cache occupancy 1603system.cpu1.dcache.tags.occ_percent::total 0.823433 # Average percentage of cache occupancy 1604system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id 1605system.cpu1.dcache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 1606system.cpu1.dcache.tags.age_task_id_blocks_1024::1 442 # Occupied blocks per task id 1607system.cpu1.dcache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id 1608system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id 1609system.cpu1.dcache.tags.tag_accesses 323862009 # Number of tag accesses 1610system.cpu1.dcache.tags.data_accesses 323862009 # Number of data accesses 1611system.cpu1.dcache.ReadReq_hits::cpu1.data 78232018 # number of ReadReq hits 1612system.cpu1.dcache.ReadReq_hits::total 78232018 # number of ReadReq hits 1613system.cpu1.dcache.WriteReq_hits::cpu1.data 71864508 # number of WriteReq hits 1614system.cpu1.dcache.WriteReq_hits::total 71864508 # number of WriteReq hits 1615system.cpu1.dcache.SoftPFReq_hits::cpu1.data 191698 # number of SoftPFReq hits 1616system.cpu1.dcache.SoftPFReq_hits::total 191698 # number of SoftPFReq hits 1617system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 211446 # number of WriteInvalidateReq hits 1618system.cpu1.dcache.WriteInvalidateReq_hits::total 211446 # number of WriteInvalidateReq hits 1619system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1712714 # number of LoadLockedReq hits 1620system.cpu1.dcache.LoadLockedReq_hits::total 1712714 # number of LoadLockedReq hits 1621system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1673213 # number of StoreCondReq hits 1622system.cpu1.dcache.StoreCondReq_hits::total 1673213 # number of StoreCondReq hits 1623system.cpu1.dcache.demand_hits::cpu1.data 150096526 # number of demand (read+write) hits 1624system.cpu1.dcache.demand_hits::total 150096526 # number of demand (read+write) hits 1625system.cpu1.dcache.overall_hits::cpu1.data 150288224 # number of overall hits 1626system.cpu1.dcache.overall_hits::total 150288224 # number of overall hits 1627system.cpu1.dcache.ReadReq_misses::cpu1.data 2870044 # number of ReadReq misses 1628system.cpu1.dcache.ReadReq_misses::total 2870044 # number of ReadReq misses 1629system.cpu1.dcache.WriteReq_misses::cpu1.data 1235849 # number of WriteReq misses 1630system.cpu1.dcache.WriteReq_misses::total 1235849 # number of WriteReq misses 1631system.cpu1.dcache.SoftPFReq_misses::cpu1.data 574884 # number of SoftPFReq misses 1632system.cpu1.dcache.SoftPFReq_misses::total 574884 # number of SoftPFReq misses 1633system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 468795 # number of WriteInvalidateReq misses 1634system.cpu1.dcache.WriteInvalidateReq_misses::total 468795 # number of WriteInvalidateReq misses 1635system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 161452 # number of LoadLockedReq misses 1636system.cpu1.dcache.LoadLockedReq_misses::total 161452 # number of LoadLockedReq misses 1637system.cpu1.dcache.StoreCondReq_misses::cpu1.data 199386 # number of StoreCondReq misses 1638system.cpu1.dcache.StoreCondReq_misses::total 199386 # number of StoreCondReq misses 1639system.cpu1.dcache.demand_misses::cpu1.data 4105893 # number of demand (read+write) misses 1640system.cpu1.dcache.demand_misses::total 4105893 # number of demand (read+write) misses 1641system.cpu1.dcache.overall_misses::cpu1.data 4680777 # number of overall misses 1642system.cpu1.dcache.overall_misses::total 4680777 # number of overall misses 1643system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 39400522531 # number of ReadReq miss cycles 1644system.cpu1.dcache.ReadReq_miss_latency::total 39400522531 # number of ReadReq miss cycles 1645system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 20561069776 # number of WriteReq miss cycles 1646system.cpu1.dcache.WriteReq_miss_latency::total 20561069776 # number of WriteReq miss cycles 1647system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 12119187041 # number of WriteInvalidateReq miss cycles 1648system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 12119187041 # number of WriteInvalidateReq miss cycles 1649system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2308132257 # number of LoadLockedReq miss cycles 1650system.cpu1.dcache.LoadLockedReq_miss_latency::total 2308132257 # number of LoadLockedReq miss cycles 1651system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4261474455 # number of StoreCondReq miss cycles 1652system.cpu1.dcache.StoreCondReq_miss_latency::total 4261474455 # number of StoreCondReq miss cycles 1653system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1966000 # number of StoreCondFailReq miss cycles 1654system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1966000 # number of StoreCondFailReq miss cycles 1655system.cpu1.dcache.demand_miss_latency::cpu1.data 59961592307 # number of demand (read+write) miss cycles 1656system.cpu1.dcache.demand_miss_latency::total 59961592307 # number of demand (read+write) miss cycles 1657system.cpu1.dcache.overall_miss_latency::cpu1.data 59961592307 # number of overall miss cycles 1658system.cpu1.dcache.overall_miss_latency::total 59961592307 # number of overall miss cycles 1659system.cpu1.dcache.ReadReq_accesses::cpu1.data 81102062 # number of ReadReq accesses(hits+misses) 1660system.cpu1.dcache.ReadReq_accesses::total 81102062 # number of ReadReq accesses(hits+misses) 1661system.cpu1.dcache.WriteReq_accesses::cpu1.data 73100357 # number of WriteReq accesses(hits+misses) 1662system.cpu1.dcache.WriteReq_accesses::total 73100357 # number of WriteReq accesses(hits+misses) 1663system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 766582 # number of SoftPFReq accesses(hits+misses) 1664system.cpu1.dcache.SoftPFReq_accesses::total 766582 # number of SoftPFReq accesses(hits+misses) 1665system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 680241 # number of WriteInvalidateReq accesses(hits+misses) 1666system.cpu1.dcache.WriteInvalidateReq_accesses::total 680241 # number of WriteInvalidateReq accesses(hits+misses) 1667system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1874166 # number of LoadLockedReq accesses(hits+misses) 1668system.cpu1.dcache.LoadLockedReq_accesses::total 1874166 # number of LoadLockedReq accesses(hits+misses) 1669system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1872599 # number of StoreCondReq accesses(hits+misses) 1670system.cpu1.dcache.StoreCondReq_accesses::total 1872599 # number of StoreCondReq accesses(hits+misses) 1671system.cpu1.dcache.demand_accesses::cpu1.data 154202419 # number of demand (read+write) accesses 1672system.cpu1.dcache.demand_accesses::total 154202419 # number of demand (read+write) accesses 1673system.cpu1.dcache.overall_accesses::cpu1.data 154969001 # number of overall (read+write) accesses 1674system.cpu1.dcache.overall_accesses::total 154969001 # number of overall (read+write) accesses 1675system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035388 # miss rate for ReadReq accesses 1676system.cpu1.dcache.ReadReq_miss_rate::total 0.035388 # miss rate for ReadReq accesses 1677system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.016906 # miss rate for WriteReq accesses 1678system.cpu1.dcache.WriteReq_miss_rate::total 0.016906 # miss rate for WriteReq accesses 1679system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.749932 # miss rate for SoftPFReq accesses 1680system.cpu1.dcache.SoftPFReq_miss_rate::total 0.749932 # miss rate for SoftPFReq accesses 1681system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.689160 # miss rate for WriteInvalidateReq accesses 1682system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.689160 # miss rate for WriteInvalidateReq accesses 1683system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086146 # miss rate for LoadLockedReq accesses 1684system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086146 # miss rate for LoadLockedReq accesses 1685system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106476 # miss rate for StoreCondReq accesses 1686system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106476 # miss rate for StoreCondReq accesses 1687system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026627 # miss rate for demand accesses 1688system.cpu1.dcache.demand_miss_rate::total 0.026627 # miss rate for demand accesses 1689system.cpu1.dcache.overall_miss_rate::cpu1.data 0.030205 # miss rate for overall accesses 1690system.cpu1.dcache.overall_miss_rate::total 0.030205 # miss rate for overall accesses 1691system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13728.194596 # average ReadReq miss latency 1692system.cpu1.dcache.ReadReq_avg_miss_latency::total 13728.194596 # average ReadReq miss latency 1693system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16637.202260 # average WriteReq miss latency 1694system.cpu1.dcache.WriteReq_avg_miss_latency::total 16637.202260 # average WriteReq miss latency 1695system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 25851.783916 # average WriteInvalidateReq miss latency 1696system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 25851.783916 # average WriteInvalidateReq miss latency 1697system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14296.089593 # average LoadLockedReq miss latency 1698system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14296.089593 # average LoadLockedReq miss latency 1699system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21372.987346 # average StoreCondReq miss latency 1700system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21372.987346 # average StoreCondReq miss latency 1701system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1702system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1703system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14603.788337 # average overall miss latency 1704system.cpu1.dcache.demand_avg_miss_latency::total 14603.788337 # average overall miss latency 1705system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12810.179230 # average overall miss latency 1706system.cpu1.dcache.overall_avg_miss_latency::total 12810.179230 # average overall miss latency 1707system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1708system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1709system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1710system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1711system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1712system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1713system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1714system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1715system.cpu1.dcache.writebacks::writebacks 3230902 # number of writebacks 1716system.cpu1.dcache.writebacks::total 3230902 # number of writebacks 1717system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 11797 # number of ReadReq MSHR hits 1718system.cpu1.dcache.ReadReq_mshr_hits::total 11797 # number of ReadReq MSHR hits 1719system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 280 # number of WriteReq MSHR hits 1720system.cpu1.dcache.WriteReq_mshr_hits::total 280 # number of WriteReq MSHR hits 1721system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 42800 # number of LoadLockedReq MSHR hits 1722system.cpu1.dcache.LoadLockedReq_mshr_hits::total 42800 # number of LoadLockedReq MSHR hits 1723system.cpu1.dcache.demand_mshr_hits::cpu1.data 12077 # number of demand (read+write) MSHR hits 1724system.cpu1.dcache.demand_mshr_hits::total 12077 # number of demand (read+write) MSHR hits 1725system.cpu1.dcache.overall_mshr_hits::cpu1.data 12077 # number of overall MSHR hits 1726system.cpu1.dcache.overall_mshr_hits::total 12077 # number of overall MSHR hits 1727system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2858247 # number of ReadReq MSHR misses 1728system.cpu1.dcache.ReadReq_mshr_misses::total 2858247 # number of ReadReq MSHR misses 1729system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1235569 # number of WriteReq MSHR misses 1730system.cpu1.dcache.WriteReq_mshr_misses::total 1235569 # number of WriteReq MSHR misses 1731system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 574884 # number of SoftPFReq MSHR misses 1732system.cpu1.dcache.SoftPFReq_mshr_misses::total 574884 # number of SoftPFReq MSHR misses 1733system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 468795 # number of WriteInvalidateReq MSHR misses 1734system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 468795 # number of WriteInvalidateReq MSHR misses 1735system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 118652 # number of LoadLockedReq MSHR misses 1736system.cpu1.dcache.LoadLockedReq_mshr_misses::total 118652 # number of LoadLockedReq MSHR misses 1737system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 199386 # number of StoreCondReq MSHR misses 1738system.cpu1.dcache.StoreCondReq_mshr_misses::total 199386 # number of StoreCondReq MSHR misses 1739system.cpu1.dcache.demand_mshr_misses::cpu1.data 4093816 # number of demand (read+write) MSHR misses 1740system.cpu1.dcache.demand_mshr_misses::total 4093816 # number of demand (read+write) MSHR misses 1741system.cpu1.dcache.overall_mshr_misses::cpu1.data 4668700 # number of overall MSHR misses 1742system.cpu1.dcache.overall_mshr_misses::total 4668700 # number of overall MSHR misses 1743system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 33045194740 # number of ReadReq MSHR miss cycles 1744system.cpu1.dcache.ReadReq_mshr_miss_latency::total 33045194740 # number of ReadReq MSHR miss cycles 1745system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 18021373474 # number of WriteReq MSHR miss cycles 1746system.cpu1.dcache.WriteReq_mshr_miss_latency::total 18021373474 # number of WriteReq MSHR miss cycles 1747system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 10397149259 # number of SoftPFReq MSHR miss cycles 1748system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 10397149259 # number of SoftPFReq MSHR miss cycles 1749system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 11178014959 # number of WriteInvalidateReq MSHR miss cycles 1750system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 11178014959 # number of WriteInvalidateReq MSHR miss cycles 1751system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1426804491 # number of LoadLockedReq MSHR miss cycles 1752system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1426804491 # number of LoadLockedReq MSHR miss cycles 1753system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3852246545 # number of StoreCondReq MSHR miss cycles 1754system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3852246545 # number of StoreCondReq MSHR miss cycles 1755system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1872000 # number of StoreCondFailReq MSHR miss cycles 1756system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1872000 # number of StoreCondFailReq MSHR miss cycles 1757system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 51066568214 # number of demand (read+write) MSHR miss cycles 1758system.cpu1.dcache.demand_mshr_miss_latency::total 51066568214 # number of demand (read+write) MSHR miss cycles 1759system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 61463717473 # number of overall MSHR miss cycles 1760system.cpu1.dcache.overall_mshr_miss_latency::total 61463717473 # number of overall MSHR miss cycles 1761system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4074474250 # number of ReadReq MSHR uncacheable cycles 1762system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4074474250 # number of ReadReq MSHR uncacheable cycles 1763system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3958410750 # number of WriteReq MSHR uncacheable cycles 1764system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3958410750 # number of WriteReq MSHR uncacheable cycles 1765system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 8032885000 # number of overall MSHR uncacheable cycles 1766system.cpu1.dcache.overall_mshr_uncacheable_latency::total 8032885000 # number of overall MSHR uncacheable cycles 1767system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035243 # mshr miss rate for ReadReq accesses 1768system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035243 # mshr miss rate for ReadReq accesses 1769system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.016902 # mshr miss rate for WriteReq accesses 1770system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.016902 # mshr miss rate for WriteReq accesses 1771system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.749932 # mshr miss rate for SoftPFReq accesses 1772system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.749932 # mshr miss rate for SoftPFReq accesses 1773system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.689160 # mshr miss rate for WriteInvalidateReq accesses 1774system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.689160 # mshr miss rate for WriteInvalidateReq accesses 1775system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063309 # mshr miss rate for LoadLockedReq accesses 1776system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063309 # mshr miss rate for LoadLockedReq accesses 1777system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106476 # mshr miss rate for StoreCondReq accesses 1778system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106476 # mshr miss rate for StoreCondReq accesses 1779system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026548 # mshr miss rate for demand accesses 1780system.cpu1.dcache.demand_mshr_miss_rate::total 0.026548 # mshr miss rate for demand accesses 1781system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030127 # mshr miss rate for overall accesses 1782system.cpu1.dcache.overall_mshr_miss_rate::total 0.030127 # mshr miss rate for overall accesses 1783system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11561.350275 # average ReadReq mshr miss latency 1784system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11561.350275 # average ReadReq mshr miss latency 1785system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14585.485290 # average WriteReq mshr miss latency 1786system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14585.485290 # average WriteReq mshr miss latency 1787system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18085.647294 # average SoftPFReq mshr miss latency 1788system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18085.647294 # average SoftPFReq mshr miss latency 1789system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 23844.142875 # average WriteInvalidateReq mshr miss latency 1790system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 23844.142875 # average WriteInvalidateReq mshr miss latency 1791system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12025.119602 # average LoadLockedReq mshr miss latency 1792system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12025.119602 # average LoadLockedReq mshr miss latency 1793system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19320.546804 # average StoreCondReq mshr miss latency 1794system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19320.546804 # average StoreCondReq mshr miss latency 1795system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1796system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1797system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12474.075096 # average overall mshr miss latency 1798system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12474.075096 # average overall mshr miss latency 1799system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13165.060396 # average overall mshr miss latency 1800system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13165.060396 # average overall mshr miss latency 1801system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1802system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1803system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1804system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1805system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1806system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1807system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1808system.cpu1.icache.tags.replacements 4937125 # number of replacements 1809system.cpu1.icache.tags.tagsinuse 496.391317 # Cycle average of tags in use 1810system.cpu1.icache.tags.total_refs 436556038 # Total number of references to valid blocks. 1811system.cpu1.icache.tags.sampled_refs 4937637 # Sample count of references to valid blocks. 1812system.cpu1.icache.tags.avg_refs 88.413960 # Average number of references to valid blocks. 1813system.cpu1.icache.tags.warmup_cycle 8378975635000 # Cycle when the warmup percentage was hit. 1814system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.391317 # Average occupied blocks per requestor 1815system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969514 # Average percentage of cache occupancy 1816system.cpu1.icache.tags.occ_percent::total 0.969514 # Average percentage of cache occupancy 1817system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1818system.cpu1.icache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id 1819system.cpu1.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id 1820system.cpu1.icache.tags.age_task_id_blocks_1024::2 239 # Occupied blocks per task id 1821system.cpu1.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id 1822system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1823system.cpu1.icache.tags.tag_accesses 887925002 # Number of tag accesses 1824system.cpu1.icache.tags.data_accesses 887925002 # Number of data accesses 1825system.cpu1.icache.ReadReq_hits::cpu1.inst 436556038 # number of ReadReq hits 1826system.cpu1.icache.ReadReq_hits::total 436556038 # number of ReadReq hits 1827system.cpu1.icache.demand_hits::cpu1.inst 436556038 # number of demand (read+write) hits 1828system.cpu1.icache.demand_hits::total 436556038 # number of demand (read+write) hits 1829system.cpu1.icache.overall_hits::cpu1.inst 436556038 # number of overall hits 1830system.cpu1.icache.overall_hits::total 436556038 # number of overall hits 1831system.cpu1.icache.ReadReq_misses::cpu1.inst 4937642 # number of ReadReq misses 1832system.cpu1.icache.ReadReq_misses::total 4937642 # number of ReadReq misses 1833system.cpu1.icache.demand_misses::cpu1.inst 4937642 # number of demand (read+write) misses 1834system.cpu1.icache.demand_misses::total 4937642 # number of demand (read+write) misses 1835system.cpu1.icache.overall_misses::cpu1.inst 4937642 # number of overall misses 1836system.cpu1.icache.overall_misses::total 4937642 # number of overall misses 1837system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 50835870381 # number of ReadReq miss cycles 1838system.cpu1.icache.ReadReq_miss_latency::total 50835870381 # number of ReadReq miss cycles 1839system.cpu1.icache.demand_miss_latency::cpu1.inst 50835870381 # number of demand (read+write) miss cycles 1840system.cpu1.icache.demand_miss_latency::total 50835870381 # number of demand (read+write) miss cycles 1841system.cpu1.icache.overall_miss_latency::cpu1.inst 50835870381 # number of overall miss cycles 1842system.cpu1.icache.overall_miss_latency::total 50835870381 # number of overall miss cycles 1843system.cpu1.icache.ReadReq_accesses::cpu1.inst 441493680 # number of ReadReq accesses(hits+misses) 1844system.cpu1.icache.ReadReq_accesses::total 441493680 # number of ReadReq accesses(hits+misses) 1845system.cpu1.icache.demand_accesses::cpu1.inst 441493680 # number of demand (read+write) accesses 1846system.cpu1.icache.demand_accesses::total 441493680 # number of demand (read+write) accesses 1847system.cpu1.icache.overall_accesses::cpu1.inst 441493680 # number of overall (read+write) accesses 1848system.cpu1.icache.overall_accesses::total 441493680 # number of overall (read+write) accesses 1849system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011184 # miss rate for ReadReq accesses 1850system.cpu1.icache.ReadReq_miss_rate::total 0.011184 # miss rate for ReadReq accesses 1851system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011184 # miss rate for demand accesses 1852system.cpu1.icache.demand_miss_rate::total 0.011184 # miss rate for demand accesses 1853system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011184 # miss rate for overall accesses 1854system.cpu1.icache.overall_miss_rate::total 0.011184 # miss rate for overall accesses 1855system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10295.576387 # average ReadReq miss latency 1856system.cpu1.icache.ReadReq_avg_miss_latency::total 10295.576387 # average ReadReq miss latency 1857system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10295.576387 # average overall miss latency 1858system.cpu1.icache.demand_avg_miss_latency::total 10295.576387 # average overall miss latency 1859system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10295.576387 # average overall miss latency 1860system.cpu1.icache.overall_avg_miss_latency::total 10295.576387 # average overall miss latency 1861system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1862system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1863system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1864system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1865system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1866system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1867system.cpu1.icache.fast_writes 0 # number of fast writes performed 1868system.cpu1.icache.cache_copies 0 # number of cache copies performed 1869system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4937642 # number of ReadReq MSHR misses 1870system.cpu1.icache.ReadReq_mshr_misses::total 4937642 # number of ReadReq MSHR misses 1871system.cpu1.icache.demand_mshr_misses::cpu1.inst 4937642 # number of demand (read+write) MSHR misses 1872system.cpu1.icache.demand_mshr_misses::total 4937642 # number of demand (read+write) MSHR misses 1873system.cpu1.icache.overall_mshr_misses::cpu1.inst 4937642 # number of overall MSHR misses 1874system.cpu1.icache.overall_mshr_misses::total 4937642 # number of overall MSHR misses 1875system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 43414323627 # number of ReadReq MSHR miss cycles 1876system.cpu1.icache.ReadReq_mshr_miss_latency::total 43414323627 # number of ReadReq MSHR miss cycles 1877system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 43414323627 # number of demand (read+write) MSHR miss cycles 1878system.cpu1.icache.demand_mshr_miss_latency::total 43414323627 # number of demand (read+write) MSHR miss cycles 1879system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 43414323627 # number of overall MSHR miss cycles 1880system.cpu1.icache.overall_mshr_miss_latency::total 43414323627 # number of overall MSHR miss cycles 1881system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8951000 # number of ReadReq MSHR uncacheable cycles 1882system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8951000 # number of ReadReq MSHR uncacheable cycles 1883system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8951000 # number of overall MSHR uncacheable cycles 1884system.cpu1.icache.overall_mshr_uncacheable_latency::total 8951000 # number of overall MSHR uncacheable cycles 1885system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011184 # mshr miss rate for ReadReq accesses 1886system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011184 # mshr miss rate for ReadReq accesses 1887system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011184 # mshr miss rate for demand accesses 1888system.cpu1.icache.demand_mshr_miss_rate::total 0.011184 # mshr miss rate for demand accesses 1889system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011184 # mshr miss rate for overall accesses 1890system.cpu1.icache.overall_mshr_miss_rate::total 0.011184 # mshr miss rate for overall accesses 1891system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8792.521537 # average ReadReq mshr miss latency 1892system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8792.521537 # average ReadReq mshr miss latency 1893system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8792.521537 # average overall mshr miss latency 1894system.cpu1.icache.demand_avg_mshr_miss_latency::total 8792.521537 # average overall mshr miss latency 1895system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8792.521537 # average overall mshr miss latency 1896system.cpu1.icache.overall_avg_mshr_miss_latency::total 8792.521537 # average overall mshr miss latency 1897system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1898system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1899system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1900system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1901system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1902system.cpu1.l2cache.prefetcher.num_hwpf_issued 6896094 # number of hwpf issued 1903system.cpu1.l2cache.prefetcher.pfIdentified 6896721 # number of prefetch candidates identified 1904system.cpu1.l2cache.prefetcher.pfBufferHit 539 # number of redundant prefetches already in prefetch queue 1905system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1906system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1907system.cpu1.l2cache.prefetcher.pfSpanPage 853759 # number of prefetches not generated due to page crossing 1908system.cpu1.l2cache.tags.replacements 1907013 # number of replacements 1909system.cpu1.l2cache.tags.tagsinuse 13040.746764 # Cycle average of tags in use 1910system.cpu1.l2cache.tags.total_refs 10338978 # Total number of references to valid blocks. 1911system.cpu1.l2cache.tags.sampled_refs 1923015 # Sample count of references to valid blocks. 1912system.cpu1.l2cache.tags.avg_refs 5.376442 # Average number of references to valid blocks. 1913system.cpu1.l2cache.tags.warmup_cycle 9789299685500 # Cycle when the warmup percentage was hit. 1914system.cpu1.l2cache.tags.occ_blocks::writebacks 5807.381964 # Average occupied blocks per requestor 1915system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 61.245810 # Average occupied blocks per requestor 1916system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 78.947620 # Average occupied blocks per requestor 1917system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2946.895146 # Average occupied blocks per requestor 1918system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3156.020749 # Average occupied blocks per requestor 1919system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 990.255474 # Average occupied blocks per requestor 1920system.cpu1.l2cache.tags.occ_percent::writebacks 0.354454 # Average percentage of cache occupancy 1921system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003738 # Average percentage of cache occupancy 1922system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004819 # Average percentage of cache occupancy 1923system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.179864 # Average percentage of cache occupancy 1924system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.192628 # Average percentage of cache occupancy 1925system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.060440 # Average percentage of cache occupancy 1926system.cpu1.l2cache.tags.occ_percent::total 0.795944 # Average percentage of cache occupancy 1927system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1412 # Occupied blocks per task id 1928system.cpu1.l2cache.tags.occ_task_id_blocks::1023 94 # Occupied blocks per task id 1929system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14496 # Occupied blocks per task id 1930system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 14 # Occupied blocks per task id 1931system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 26 # Occupied blocks per task id 1932system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 63 # Occupied blocks per task id 1933system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1121 # Occupied blocks per task id 1934system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 188 # Occupied blocks per task id 1935system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id 1936system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 9 # Occupied blocks per task id 1937system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id 1938system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 79 # Occupied blocks per task id 1939system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id 1940system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id 1941system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1044 # Occupied blocks per task id 1942system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1799 # Occupied blocks per task id 1943system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 10295 # Occupied blocks per task id 1944system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1321 # Occupied blocks per task id 1945system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.086182 # Percentage of cache occupancy per task id 1946system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005737 # Percentage of cache occupancy per task id 1947system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.884766 # Percentage of cache occupancy per task id 1948system.cpu1.l2cache.tags.tag_accesses 227501804 # Number of tag accesses 1949system.cpu1.l2cache.tags.data_accesses 227501804 # Number of data accesses 1950system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 207163 # number of ReadReq hits 1951system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 127057 # number of ReadReq hits 1952system.cpu1.l2cache.ReadReq_hits::cpu1.inst 4446186 # number of ReadReq hits 1953system.cpu1.l2cache.ReadReq_hits::cpu1.data 2697591 # number of ReadReq hits 1954system.cpu1.l2cache.ReadReq_hits::total 7477997 # number of ReadReq hits 1955system.cpu1.l2cache.Writeback_hits::writebacks 3230902 # number of Writeback hits 1956system.cpu1.l2cache.Writeback_hits::total 3230902 # number of Writeback hits 1957system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 181429 # number of WriteInvalidateReq hits 1958system.cpu1.l2cache.WriteInvalidateReq_hits::total 181429 # number of WriteInvalidateReq hits 1959system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 59189 # number of UpgradeReq hits 1960system.cpu1.l2cache.UpgradeReq_hits::total 59189 # number of UpgradeReq hits 1961system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 31769 # number of SCUpgradeReq hits 1962system.cpu1.l2cache.SCUpgradeReq_hits::total 31769 # number of SCUpgradeReq hits 1963system.cpu1.l2cache.ReadExReq_hits::cpu1.data 842543 # number of ReadExReq hits 1964system.cpu1.l2cache.ReadExReq_hits::total 842543 # number of ReadExReq hits 1965system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 207163 # number of demand (read+write) hits 1966system.cpu1.l2cache.demand_hits::cpu1.itb.walker 127057 # number of demand (read+write) hits 1967system.cpu1.l2cache.demand_hits::cpu1.inst 4446186 # number of demand (read+write) hits 1968system.cpu1.l2cache.demand_hits::cpu1.data 3540134 # number of demand (read+write) hits 1969system.cpu1.l2cache.demand_hits::total 8320540 # number of demand (read+write) hits 1970system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 207163 # number of overall hits 1971system.cpu1.l2cache.overall_hits::cpu1.itb.walker 127057 # number of overall hits 1972system.cpu1.l2cache.overall_hits::cpu1.inst 4446186 # number of overall hits 1973system.cpu1.l2cache.overall_hits::cpu1.data 3540134 # number of overall hits 1974system.cpu1.l2cache.overall_hits::total 8320540 # number of overall hits 1975system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 8925 # number of ReadReq misses 1976system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 6995 # number of ReadReq misses 1977system.cpu1.l2cache.ReadReq_misses::cpu1.inst 491456 # number of ReadReq misses 1978system.cpu1.l2cache.ReadReq_misses::cpu1.data 854192 # number of ReadReq misses 1979system.cpu1.l2cache.ReadReq_misses::total 1361568 # number of ReadReq misses 1980system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 285701 # number of WriteInvalidateReq misses 1981system.cpu1.l2cache.WriteInvalidateReq_misses::total 285701 # number of WriteInvalidateReq misses 1982system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 127179 # number of UpgradeReq misses 1983system.cpu1.l2cache.UpgradeReq_misses::total 127179 # number of UpgradeReq misses 1984system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 167611 # number of SCUpgradeReq misses 1985system.cpu1.l2cache.SCUpgradeReq_misses::total 167611 # number of SCUpgradeReq misses 1986system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses 1987system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses 1988system.cpu1.l2cache.ReadExReq_misses::cpu1.data 208488 # number of ReadExReq misses 1989system.cpu1.l2cache.ReadExReq_misses::total 208488 # number of ReadExReq misses 1990system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 8925 # number of demand (read+write) misses 1991system.cpu1.l2cache.demand_misses::cpu1.itb.walker 6995 # number of demand (read+write) misses 1992system.cpu1.l2cache.demand_misses::cpu1.inst 491456 # number of demand (read+write) misses 1993system.cpu1.l2cache.demand_misses::cpu1.data 1062680 # number of demand (read+write) misses 1994system.cpu1.l2cache.demand_misses::total 1570056 # number of demand (read+write) misses 1995system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 8925 # number of overall misses 1996system.cpu1.l2cache.overall_misses::cpu1.itb.walker 6995 # number of overall misses 1997system.cpu1.l2cache.overall_misses::cpu1.inst 491456 # number of overall misses 1998system.cpu1.l2cache.overall_misses::cpu1.data 1062680 # number of overall misses 1999system.cpu1.l2cache.overall_misses::total 1570056 # number of overall misses 2000system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 266500250 # number of ReadReq miss cycles 2001system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 219567495 # number of ReadReq miss cycles 2002system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 14267491069 # number of ReadReq miss cycles 2003system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 25122385610 # number of ReadReq miss cycles 2004system.cpu1.l2cache.ReadReq_miss_latency::total 39875944424 # number of ReadReq miss cycles 2005system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 189007871 # number of WriteInvalidateReq miss cycles 2006system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 189007871 # number of WriteInvalidateReq miss cycles 2007system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2544221753 # number of UpgradeReq miss cycles 2008system.cpu1.l2cache.UpgradeReq_miss_latency::total 2544221753 # number of UpgradeReq miss cycles 2009system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3390574541 # number of SCUpgradeReq miss cycles 2010system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3390574541 # number of SCUpgradeReq miss cycles 2011system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1824999 # number of SCUpgradeFailReq miss cycles 2012system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1824999 # number of SCUpgradeFailReq miss cycles 2013system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 8358339864 # number of ReadExReq miss cycles 2014system.cpu1.l2cache.ReadExReq_miss_latency::total 8358339864 # number of ReadExReq miss cycles 2015system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 266500250 # number of demand (read+write) miss cycles 2016system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 219567495 # number of demand (read+write) miss cycles 2017system.cpu1.l2cache.demand_miss_latency::cpu1.inst 14267491069 # number of demand (read+write) miss cycles 2018system.cpu1.l2cache.demand_miss_latency::cpu1.data 33480725474 # number of demand (read+write) miss cycles 2019system.cpu1.l2cache.demand_miss_latency::total 48234284288 # number of demand (read+write) miss cycles 2020system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 266500250 # number of overall miss cycles 2021system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 219567495 # number of overall miss cycles 2022system.cpu1.l2cache.overall_miss_latency::cpu1.inst 14267491069 # number of overall miss cycles 2023system.cpu1.l2cache.overall_miss_latency::cpu1.data 33480725474 # number of overall miss cycles 2024system.cpu1.l2cache.overall_miss_latency::total 48234284288 # number of overall miss cycles 2025system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 216088 # number of ReadReq accesses(hits+misses) 2026system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 134052 # number of ReadReq accesses(hits+misses) 2027system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 4937642 # number of ReadReq accesses(hits+misses) 2028system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3551783 # number of ReadReq accesses(hits+misses) 2029system.cpu1.l2cache.ReadReq_accesses::total 8839565 # number of ReadReq accesses(hits+misses) 2030system.cpu1.l2cache.Writeback_accesses::writebacks 3230902 # number of Writeback accesses(hits+misses) 2031system.cpu1.l2cache.Writeback_accesses::total 3230902 # number of Writeback accesses(hits+misses) 2032system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 467130 # number of WriteInvalidateReq accesses(hits+misses) 2033system.cpu1.l2cache.WriteInvalidateReq_accesses::total 467130 # number of WriteInvalidateReq accesses(hits+misses) 2034system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 186368 # number of UpgradeReq accesses(hits+misses) 2035system.cpu1.l2cache.UpgradeReq_accesses::total 186368 # number of UpgradeReq accesses(hits+misses) 2036system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 199380 # number of SCUpgradeReq accesses(hits+misses) 2037system.cpu1.l2cache.SCUpgradeReq_accesses::total 199380 # number of SCUpgradeReq accesses(hits+misses) 2038system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses) 2039system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) 2040system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1051031 # number of ReadExReq accesses(hits+misses) 2041system.cpu1.l2cache.ReadExReq_accesses::total 1051031 # number of ReadExReq accesses(hits+misses) 2042system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 216088 # number of demand (read+write) accesses 2043system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 134052 # number of demand (read+write) accesses 2044system.cpu1.l2cache.demand_accesses::cpu1.inst 4937642 # number of demand (read+write) accesses 2045system.cpu1.l2cache.demand_accesses::cpu1.data 4602814 # number of demand (read+write) accesses 2046system.cpu1.l2cache.demand_accesses::total 9890596 # number of demand (read+write) accesses 2047system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 216088 # number of overall (read+write) accesses 2048system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 134052 # number of overall (read+write) accesses 2049system.cpu1.l2cache.overall_accesses::cpu1.inst 4937642 # number of overall (read+write) accesses 2050system.cpu1.l2cache.overall_accesses::cpu1.data 4602814 # number of overall (read+write) accesses 2051system.cpu1.l2cache.overall_accesses::total 9890596 # number of overall (read+write) accesses 2052system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.041303 # miss rate for ReadReq accesses 2053system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.052181 # miss rate for ReadReq accesses 2054system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.099533 # miss rate for ReadReq accesses 2055system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.240497 # miss rate for ReadReq accesses 2056system.cpu1.l2cache.ReadReq_miss_rate::total 0.154031 # miss rate for ReadReq accesses 2057system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.611609 # miss rate for WriteInvalidateReq accesses 2058system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.611609 # miss rate for WriteInvalidateReq accesses 2059system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.682408 # miss rate for UpgradeReq accesses 2060system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.682408 # miss rate for UpgradeReq accesses 2061system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.840661 # miss rate for SCUpgradeReq accesses 2062system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.840661 # miss rate for SCUpgradeReq accesses 2063system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2064system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2065system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.198365 # miss rate for ReadExReq accesses 2066system.cpu1.l2cache.ReadExReq_miss_rate::total 0.198365 # miss rate for ReadExReq accesses 2067system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.041303 # miss rate for demand accesses 2068system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.052181 # miss rate for demand accesses 2069system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.099533 # miss rate for demand accesses 2070system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.230876 # miss rate for demand accesses 2071system.cpu1.l2cache.demand_miss_rate::total 0.158742 # miss rate for demand accesses 2072system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.041303 # miss rate for overall accesses 2073system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.052181 # miss rate for overall accesses 2074system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.099533 # miss rate for overall accesses 2075system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.230876 # miss rate for overall accesses 2076system.cpu1.l2cache.overall_miss_rate::total 0.158742 # miss rate for overall accesses 2077system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 29859.971989 # average ReadReq miss latency 2078system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 31389.205861 # average ReadReq miss latency 2079system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 29031.064976 # average ReadReq miss latency 2080system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 29410.701119 # average ReadReq miss latency 2081system.cpu1.l2cache.ReadReq_avg_miss_latency::total 29286.781434 # average ReadReq miss latency 2082system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 661.558311 # average WriteInvalidateReq miss latency 2083system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 661.558311 # average WriteInvalidateReq miss latency 2084system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 20005.046061 # average UpgradeReq miss latency 2085system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 20005.046061 # average UpgradeReq miss latency 2086system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20228.830691 # average SCUpgradeReq miss latency 2087system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20228.830691 # average SCUpgradeReq miss latency 2088system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 304166.500000 # average SCUpgradeFailReq miss latency 2089system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 304166.500000 # average SCUpgradeFailReq miss latency 2090system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 40090.268332 # average ReadExReq miss latency 2091system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 40090.268332 # average ReadExReq miss latency 2092system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 29859.971989 # average overall miss latency 2093system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 31389.205861 # average overall miss latency 2094system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29031.064976 # average overall miss latency 2095system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 31505.933559 # average overall miss latency 2096system.cpu1.l2cache.demand_avg_miss_latency::total 30721.378274 # average overall miss latency 2097system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 29859.971989 # average overall miss latency 2098system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 31389.205861 # average overall miss latency 2099system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29031.064976 # average overall miss latency 2100system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 31505.933559 # average overall miss latency 2101system.cpu1.l2cache.overall_avg_miss_latency::total 30721.378274 # average overall miss latency 2102system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2103system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2104system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2105system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2106system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2107system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2108system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2109system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 2110system.cpu1.l2cache.writebacks::writebacks 911309 # number of writebacks 2111system.cpu1.l2cache.writebacks::total 911309 # number of writebacks 2112system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 380 # number of ReadReq MSHR hits 2113system.cpu1.l2cache.ReadReq_mshr_hits::total 380 # number of ReadReq MSHR hits 2114system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 5401 # number of ReadExReq MSHR hits 2115system.cpu1.l2cache.ReadExReq_mshr_hits::total 5401 # number of ReadExReq MSHR hits 2116system.cpu1.l2cache.demand_mshr_hits::cpu1.data 5781 # number of demand (read+write) MSHR hits 2117system.cpu1.l2cache.demand_mshr_hits::total 5781 # number of demand (read+write) MSHR hits 2118system.cpu1.l2cache.overall_mshr_hits::cpu1.data 5781 # number of overall MSHR hits 2119system.cpu1.l2cache.overall_mshr_hits::total 5781 # number of overall MSHR hits 2120system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 8925 # number of ReadReq MSHR misses 2121system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 6995 # number of ReadReq MSHR misses 2122system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 491456 # number of ReadReq MSHR misses 2123system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 853812 # number of ReadReq MSHR misses 2124system.cpu1.l2cache.ReadReq_mshr_misses::total 1361188 # number of ReadReq MSHR misses 2125system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 639196 # number of HardPFReq MSHR misses 2126system.cpu1.l2cache.HardPFReq_mshr_misses::total 639196 # number of HardPFReq MSHR misses 2127system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 285701 # number of WriteInvalidateReq MSHR misses 2128system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 285701 # number of WriteInvalidateReq MSHR misses 2129system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 127179 # number of UpgradeReq MSHR misses 2130system.cpu1.l2cache.UpgradeReq_mshr_misses::total 127179 # number of UpgradeReq MSHR misses 2131system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 167611 # number of SCUpgradeReq MSHR misses 2132system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 167611 # number of SCUpgradeReq MSHR misses 2133system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 6 # number of SCUpgradeFailReq MSHR misses 2134system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses 2135system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 203087 # number of ReadExReq MSHR misses 2136system.cpu1.l2cache.ReadExReq_mshr_misses::total 203087 # number of ReadExReq MSHR misses 2137system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 8925 # number of demand (read+write) MSHR misses 2138system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 6995 # number of demand (read+write) MSHR misses 2139system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 491456 # number of demand (read+write) MSHR misses 2140system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1056899 # number of demand (read+write) MSHR misses 2141system.cpu1.l2cache.demand_mshr_misses::total 1564275 # number of demand (read+write) MSHR misses 2142system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 8925 # number of overall MSHR misses 2143system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 6995 # number of overall MSHR misses 2144system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 491456 # number of overall MSHR misses 2145system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1056899 # number of overall MSHR misses 2146system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 639196 # number of overall MSHR misses 2147system.cpu1.l2cache.overall_mshr_misses::total 2203471 # number of overall MSHR misses 2148system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 203741250 # number of ReadReq MSHR miss cycles 2149system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 170362507 # number of ReadReq MSHR miss cycles 2150system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 10812394931 # number of ReadReq MSHR miss cycles 2151system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 19078738641 # number of ReadReq MSHR miss cycles 2152system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 30265237329 # number of ReadReq MSHR miss cycles 2153system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 29755594933 # number of HardPFReq MSHR miss cycles 2154system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 29755594933 # number of HardPFReq MSHR miss cycles 2155system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 7736539648 # number of WriteInvalidateReq MSHR miss cycles 2156system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 7736539648 # number of WriteInvalidateReq MSHR miss cycles 2157system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2151571523 # number of UpgradeReq MSHR miss cycles 2158system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2151571523 # number of UpgradeReq MSHR miss cycles 2159system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2290441908 # number of SCUpgradeReq MSHR miss cycles 2160system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2290441908 # number of SCUpgradeReq MSHR miss cycles 2161system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1495999 # number of SCUpgradeFailReq MSHR miss cycles 2162system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1495999 # number of SCUpgradeFailReq MSHR miss cycles 2163system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 6293487581 # number of ReadExReq MSHR miss cycles 2164system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 6293487581 # number of ReadExReq MSHR miss cycles 2165system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 203741250 # number of demand (read+write) MSHR miss cycles 2166system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 170362507 # number of demand (read+write) MSHR miss cycles 2167system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 10812394931 # number of demand (read+write) MSHR miss cycles 2168system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 25372226222 # number of demand (read+write) MSHR miss cycles 2169system.cpu1.l2cache.demand_mshr_miss_latency::total 36558724910 # number of demand (read+write) MSHR miss cycles 2170system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 203741250 # number of overall MSHR miss cycles 2171system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 170362507 # number of overall MSHR miss cycles 2172system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 10812394931 # number of overall MSHR miss cycles 2173system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 25372226222 # number of overall MSHR miss cycles 2174system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 29755594933 # number of overall MSHR miss cycles 2175system.cpu1.l2cache.overall_mshr_miss_latency::total 66314319843 # number of overall MSHR miss cycles 2176system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8087000 # number of ReadReq MSHR uncacheable cycles 2177system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3880010250 # number of ReadReq MSHR uncacheable cycles 2178system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3888097250 # number of ReadReq MSHR uncacheable cycles 2179system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 3784845500 # number of WriteReq MSHR uncacheable cycles 2180system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3784845500 # number of WriteReq MSHR uncacheable cycles 2181system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8087000 # number of overall MSHR uncacheable cycles 2182system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 7664855750 # number of overall MSHR uncacheable cycles 2183system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 7672942750 # number of overall MSHR uncacheable cycles 2184system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.041303 # mshr miss rate for ReadReq accesses 2185system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.052181 # mshr miss rate for ReadReq accesses 2186system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.099533 # mshr miss rate for ReadReq accesses 2187system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.240390 # mshr miss rate for ReadReq accesses 2188system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.153988 # mshr miss rate for ReadReq accesses 2189system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2190system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2191system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.611609 # mshr miss rate for WriteInvalidateReq accesses 2192system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.611609 # mshr miss rate for WriteInvalidateReq accesses 2193system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.682408 # mshr miss rate for UpgradeReq accesses 2194system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.682408 # mshr miss rate for UpgradeReq accesses 2195system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.840661 # mshr miss rate for SCUpgradeReq accesses 2196system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.840661 # mshr miss rate for SCUpgradeReq accesses 2197system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2198system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2199system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.193226 # mshr miss rate for ReadExReq accesses 2200system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.193226 # mshr miss rate for ReadExReq accesses 2201system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.041303 # mshr miss rate for demand accesses 2202system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.052181 # mshr miss rate for demand accesses 2203system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.099533 # mshr miss rate for demand accesses 2204system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.229620 # mshr miss rate for demand accesses 2205system.cpu1.l2cache.demand_mshr_miss_rate::total 0.158158 # mshr miss rate for demand accesses 2206system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.041303 # mshr miss rate for overall accesses 2207system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.052181 # mshr miss rate for overall accesses 2208system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.099533 # mshr miss rate for overall accesses 2209system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.229620 # mshr miss rate for overall accesses 2210system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2211system.cpu1.l2cache.overall_mshr_miss_rate::total 0.222784 # mshr miss rate for overall accesses 2212system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 22828.151261 # average ReadReq mshr miss latency 2213system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 24354.897355 # average ReadReq mshr miss latency 2214system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22000.738481 # average ReadReq mshr miss latency 2215system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 22345.362493 # average ReadReq mshr miss latency 2216system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 22234.428550 # average ReadReq mshr miss latency 2217system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46551.597527 # average HardPFReq mshr miss latency 2218system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 46551.597527 # average HardPFReq mshr miss latency 2219system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 27079.147948 # average WriteInvalidateReq mshr miss latency 2220system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 27079.147948 # average WriteInvalidateReq mshr miss latency 2221system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16917.663474 # average UpgradeReq mshr miss latency 2222system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16917.663474 # average UpgradeReq mshr miss latency 2223system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13665.224287 # average SCUpgradeReq mshr miss latency 2224system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13665.224287 # average SCUpgradeReq mshr miss latency 2225system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 249333.166667 # average SCUpgradeFailReq mshr miss latency 2226system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 249333.166667 # average SCUpgradeFailReq mshr miss latency 2227system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30989.120825 # average ReadExReq mshr miss latency 2228system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30989.120825 # average ReadExReq mshr miss latency 2229system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 22828.151261 # average overall mshr miss latency 2230system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 24354.897355 # average overall mshr miss latency 2231system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22000.738481 # average overall mshr miss latency 2232system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24006.292202 # average overall mshr miss latency 2233system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23371.034447 # average overall mshr miss latency 2234system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 22828.151261 # average overall mshr miss latency 2235system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 24354.897355 # average overall mshr miss latency 2236system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22000.738481 # average overall mshr miss latency 2237system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24006.292202 # average overall mshr miss latency 2238system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46551.597527 # average overall mshr miss latency 2239system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30095.390338 # average overall mshr miss latency 2240system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2241system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2242system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2243system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2244system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2245system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2246system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2247system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2248system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2249system.cpu1.toL2Bus.trans_dist::ReadReq 11132088 # Transaction distribution 2250system.cpu1.toL2Bus.trans_dist::ReadResp 9059631 # Transaction distribution 2251system.cpu1.toL2Bus.trans_dist::WriteReq 23142 # Transaction distribution 2252system.cpu1.toL2Bus.trans_dist::WriteResp 23142 # Transaction distribution 2253system.cpu1.toL2Bus.trans_dist::Writeback 3230902 # Transaction distribution 2254system.cpu1.toL2Bus.trans_dist::HardPFReq 957658 # Transaction distribution 2255system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 2256system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1110389 # Transaction distribution 2257system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 467130 # Transaction distribution 2258system.cpu1.toL2Bus.trans_dist::UpgradeReq 407372 # Transaction distribution 2259system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 365584 # Transaction distribution 2260system.cpu1.toL2Bus.trans_dist::UpgradeResp 452132 # Transaction distribution 2261system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 59 # Transaction distribution 2262system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution 2263system.cpu1.toL2Bus.trans_dist::ReadExReq 1208854 # Transaction distribution 2264system.cpu1.toL2Bus.trans_dist::ReadExResp 1057926 # Transaction distribution 2265system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9875504 # Packet count per connected master and slave (bytes) 2266system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 14402767 # Packet count per connected master and slave (bytes) 2267system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 299311 # Packet count per connected master and slave (bytes) 2268system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 504421 # Packet count per connected master and slave (bytes) 2269system.cpu1.toL2Bus.pkt_count::total 25082003 # Packet count per connected master and slave (bytes) 2270system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 316009528 # Cumulative packet size per connected master and slave (bytes) 2271system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 537745480 # Cumulative packet size per connected master and slave (bytes) 2272system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1072416 # Cumulative packet size per connected master and slave (bytes) 2273system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1728704 # Cumulative packet size per connected master and slave (bytes) 2274system.cpu1.toL2Bus.pkt_size::total 856556128 # Cumulative packet size per connected master and slave (bytes) 2275system.cpu1.toL2Bus.snoops 4579678 # Total snoops (count) 2276system.cpu1.toL2Bus.snoop_fanout::samples 18388489 # Request fanout histogram 2277system.cpu1.toL2Bus.snoop_fanout::mean 5.234421 # Request fanout histogram 2278system.cpu1.toL2Bus.snoop_fanout::stdev 0.423637 # Request fanout histogram 2279system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2280system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2281system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 2282system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 2283system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 2284system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 2285system.cpu1.toL2Bus.snoop_fanout::5 14077834 76.56% 76.56% # Request fanout histogram 2286system.cpu1.toL2Bus.snoop_fanout::6 4310655 23.44% 100.00% # Request fanout histogram 2287system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2288system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 2289system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 2290system.cpu1.toL2Bus.snoop_fanout::total 18388489 # Request fanout histogram 2291system.cpu1.toL2Bus.reqLayer0.occupancy 10772824519 # Layer occupancy (ticks) 2292system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2293system.cpu1.toL2Bus.snoopLayer0.occupancy 181931492 # Layer occupancy (ticks) 2294system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2295system.cpu1.toL2Bus.respLayer0.occupancy 7414134377 # Layer occupancy (ticks) 2296system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2297system.cpu1.toL2Bus.respLayer1.occupancy 7417250282 # Layer occupancy (ticks) 2298system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2299system.cpu1.toL2Bus.respLayer2.occupancy 165377004 # Layer occupancy (ticks) 2300system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2301system.cpu1.toL2Bus.respLayer3.occupancy 288475000 # Layer occupancy (ticks) 2302system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2303system.iobus.trans_dist::ReadReq 40416 # Transaction distribution 2304system.iobus.trans_dist::ReadResp 40416 # Transaction distribution 2305system.iobus.trans_dist::WriteReq 136984 # Transaction distribution 2306system.iobus.trans_dist::WriteResp 30064 # Transaction distribution 2307system.iobus.trans_dist::WriteInvalidateResp 106920 # Transaction distribution 2308system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48038 # Packet count per connected master and slave (bytes) 2309system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2310system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2311system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2312system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2313system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2314system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2315system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2316system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2317system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2318system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29704 # Packet count per connected master and slave (bytes) 2319system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2320system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 2321system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2322system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 2323system.iobus.pkt_count_system.bridge.master::total 123076 # Packet count per connected master and slave (bytes) 2324system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231644 # Packet count per connected master and slave (bytes) 2325system.iobus.pkt_count_system.realview.ide.dma::total 231644 # Packet count per connected master and slave (bytes) 2326system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2327system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 2328system.iobus.pkt_count::total 354800 # Packet count per connected master and slave (bytes) 2329system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48058 # Cumulative packet size per connected master and slave (bytes) 2330system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2331system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2332system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2333system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2334system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2335system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2336system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2337system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2338system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2339system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17645 # Cumulative packet size per connected master and slave (bytes) 2340system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 2341system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 2342system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 2343system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 2344system.iobus.pkt_size_system.bridge.master::total 156137 # Cumulative packet size per connected master and slave (bytes) 2345system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7351344 # Cumulative packet size per connected master and slave (bytes) 2346system.iobus.pkt_size_system.realview.ide.dma::total 7351344 # Cumulative packet size per connected master and slave (bytes) 2347system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2348system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 2349system.iobus.pkt_size::total 7509567 # Cumulative packet size per connected master and slave (bytes) 2350system.iobus.reqLayer0.occupancy 36527000 # Layer occupancy (ticks) 2351system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2352system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 2353system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2354system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 2355system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2356system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 2357system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2358system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 2359system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2360system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 2361system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2362system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 2363system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2364system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 2365system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2366system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 2367system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2368system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 2369system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2370system.iobus.reqLayer23.occupancy 22064000 # Layer occupancy (ticks) 2371system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2372system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 2373system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2374system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 2375system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2376system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 2377system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 2378system.iobus.reqLayer27.occupancy 1044902599 # Layer occupancy (ticks) 2379system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2380system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2381system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 2382system.iobus.respLayer0.occupancy 93015000 # Layer occupancy (ticks) 2383system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2384system.iobus.respLayer3.occupancy 179432954 # Layer occupancy (ticks) 2385system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2386system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) 2387system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 2388system.iocache.tags.replacements 115804 # number of replacements 2389system.iocache.tags.tagsinuse 11.285754 # Cycle average of tags in use 2390system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 2391system.iocache.tags.sampled_refs 115820 # Sample count of references to valid blocks. 2392system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 2393system.iocache.tags.warmup_cycle 9175904776000 # Cycle when the warmup percentage was hit. 2394system.iocache.tags.occ_blocks::realview.ethernet 3.836841 # Average occupied blocks per requestor 2395system.iocache.tags.occ_blocks::realview.ide 7.448912 # Average occupied blocks per requestor 2396system.iocache.tags.occ_percent::realview.ethernet 0.239803 # Average percentage of cache occupancy 2397system.iocache.tags.occ_percent::realview.ide 0.465557 # Average percentage of cache occupancy 2398system.iocache.tags.occ_percent::total 0.705360 # Average percentage of cache occupancy 2399system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2400system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2401system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2402system.iocache.tags.tag_accesses 1042755 # Number of tag accesses 2403system.iocache.tags.data_accesses 1042755 # Number of data accesses 2404system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2405system.iocache.ReadReq_misses::realview.ide 8902 # number of ReadReq misses 2406system.iocache.ReadReq_misses::total 8939 # number of ReadReq misses 2407system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2408system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2409system.iocache.WriteInvalidateReq_misses::realview.ide 106920 # number of WriteInvalidateReq misses 2410system.iocache.WriteInvalidateReq_misses::total 106920 # number of WriteInvalidateReq misses 2411system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 2412system.iocache.demand_misses::realview.ide 8902 # number of demand (read+write) misses 2413system.iocache.demand_misses::total 8942 # number of demand (read+write) misses 2414system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 2415system.iocache.overall_misses::realview.ide 8902 # number of overall misses 2416system.iocache.overall_misses::total 8942 # number of overall misses 2417system.iocache.ReadReq_miss_latency::realview.ethernet 5707000 # number of ReadReq miss cycles 2418system.iocache.ReadReq_miss_latency::realview.ide 1942659591 # number of ReadReq miss cycles 2419system.iocache.ReadReq_miss_latency::total 1948366591 # number of ReadReq miss cycles 2420system.iocache.WriteReq_miss_latency::realview.ethernet 357000 # number of WriteReq miss cycles 2421system.iocache.WriteReq_miss_latency::total 357000 # number of WriteReq miss cycles 2422system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28987663054 # number of WriteInvalidateReq miss cycles 2423system.iocache.WriteInvalidateReq_miss_latency::total 28987663054 # number of WriteInvalidateReq miss cycles 2424system.iocache.demand_miss_latency::realview.ethernet 6064000 # number of demand (read+write) miss cycles 2425system.iocache.demand_miss_latency::realview.ide 1942659591 # number of demand (read+write) miss cycles 2426system.iocache.demand_miss_latency::total 1948723591 # number of demand (read+write) miss cycles 2427system.iocache.overall_miss_latency::realview.ethernet 6064000 # number of overall miss cycles 2428system.iocache.overall_miss_latency::realview.ide 1942659591 # number of overall miss cycles 2429system.iocache.overall_miss_latency::total 1948723591 # number of overall miss cycles 2430system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 2431system.iocache.ReadReq_accesses::realview.ide 8902 # number of ReadReq accesses(hits+misses) 2432system.iocache.ReadReq_accesses::total 8939 # number of ReadReq accesses(hits+misses) 2433system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2434system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2435system.iocache.WriteInvalidateReq_accesses::realview.ide 106920 # number of WriteInvalidateReq accesses(hits+misses) 2436system.iocache.WriteInvalidateReq_accesses::total 106920 # number of WriteInvalidateReq accesses(hits+misses) 2437system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 2438system.iocache.demand_accesses::realview.ide 8902 # number of demand (read+write) accesses 2439system.iocache.demand_accesses::total 8942 # number of demand (read+write) accesses 2440system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 2441system.iocache.overall_accesses::realview.ide 8902 # number of overall (read+write) accesses 2442system.iocache.overall_accesses::total 8942 # number of overall (read+write) accesses 2443system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2444system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2445system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2446system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2447system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2448system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 2449system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 2450system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2451system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2452system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2453system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2454system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2455system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2456system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243 # average ReadReq miss latency 2457system.iocache.ReadReq_avg_miss_latency::realview.ide 218227.318692 # average ReadReq miss latency 2458system.iocache.ReadReq_avg_miss_latency::total 217962.478018 # average ReadReq miss latency 2459system.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency 2460system.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency 2461system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271115.441957 # average WriteInvalidateReq miss latency 2462system.iocache.WriteInvalidateReq_avg_miss_latency::total 271115.441957 # average WriteInvalidateReq miss latency 2463system.iocache.demand_avg_miss_latency::realview.ethernet 151600 # average overall miss latency 2464system.iocache.demand_avg_miss_latency::realview.ide 218227.318692 # average overall miss latency 2465system.iocache.demand_avg_miss_latency::total 217929.276560 # average overall miss latency 2466system.iocache.overall_avg_miss_latency::realview.ethernet 151600 # average overall miss latency 2467system.iocache.overall_avg_miss_latency::realview.ide 218227.318692 # average overall miss latency 2468system.iocache.overall_avg_miss_latency::total 217929.276560 # average overall miss latency 2469system.iocache.blocked_cycles::no_mshrs 228501 # number of cycles access was blocked 2470system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2471system.iocache.blocked::no_mshrs 27689 # number of cycles access was blocked 2472system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2473system.iocache.avg_blocked_cycles::no_mshrs 8.252411 # average number of cycles each access was blocked 2474system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2475system.iocache.fast_writes 0 # number of fast writes performed 2476system.iocache.cache_copies 0 # number of cache copies performed 2477system.iocache.writebacks::writebacks 106887 # number of writebacks 2478system.iocache.writebacks::total 106887 # number of writebacks 2479system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 2480system.iocache.ReadReq_mshr_misses::realview.ide 8902 # number of ReadReq MSHR misses 2481system.iocache.ReadReq_mshr_misses::total 8939 # number of ReadReq MSHR misses 2482system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2483system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2484system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106920 # number of WriteInvalidateReq MSHR misses 2485system.iocache.WriteInvalidateReq_mshr_misses::total 106920 # number of WriteInvalidateReq MSHR misses 2486system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 2487system.iocache.demand_mshr_misses::realview.ide 8902 # number of demand (read+write) MSHR misses 2488system.iocache.demand_mshr_misses::total 8942 # number of demand (read+write) MSHR misses 2489system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 2490system.iocache.overall_mshr_misses::realview.ide 8902 # number of overall MSHR misses 2491system.iocache.overall_mshr_misses::total 8942 # number of overall MSHR misses 2492system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3783000 # number of ReadReq MSHR miss cycles 2493system.iocache.ReadReq_mshr_miss_latency::realview.ide 1479616613 # number of ReadReq MSHR miss cycles 2494system.iocache.ReadReq_mshr_miss_latency::total 1483399613 # number of ReadReq MSHR miss cycles 2495system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 2496system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 2497system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23427435940 # number of WriteInvalidateReq MSHR miss cycles 2498system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23427435940 # number of WriteInvalidateReq MSHR miss cycles 2499system.iocache.demand_mshr_miss_latency::realview.ethernet 3984000 # number of demand (read+write) MSHR miss cycles 2500system.iocache.demand_mshr_miss_latency::realview.ide 1479616613 # number of demand (read+write) MSHR miss cycles 2501system.iocache.demand_mshr_miss_latency::total 1483600613 # number of demand (read+write) MSHR miss cycles 2502system.iocache.overall_mshr_miss_latency::realview.ethernet 3984000 # number of overall MSHR miss cycles 2503system.iocache.overall_mshr_miss_latency::realview.ide 1479616613 # number of overall MSHR miss cycles 2504system.iocache.overall_mshr_miss_latency::total 1483600613 # number of overall MSHR miss cycles 2505system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2506system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2507system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2508system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2509system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2510system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 2511system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 2512system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 2513system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2514system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2515system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 2516system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2517system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2518system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243 # average ReadReq mshr miss latency 2519system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 166211.706695 # average ReadReq mshr miss latency 2520system.iocache.ReadReq_avg_mshr_miss_latency::total 165946.930641 # average ReadReq mshr miss latency 2521system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 2522system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 2523system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219111.821362 # average WriteInvalidateReq mshr miss latency 2524system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219111.821362 # average WriteInvalidateReq mshr miss latency 2525system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency 2526system.iocache.demand_avg_mshr_miss_latency::realview.ide 166211.706695 # average overall mshr miss latency 2527system.iocache.demand_avg_mshr_miss_latency::total 165913.734399 # average overall mshr miss latency 2528system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency 2529system.iocache.overall_avg_mshr_miss_latency::realview.ide 166211.706695 # average overall mshr miss latency 2530system.iocache.overall_avg_mshr_miss_latency::total 165913.734399 # average overall mshr miss latency 2531system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2532system.l2c.tags.replacements 1354462 # number of replacements 2533system.l2c.tags.tagsinuse 64231.297434 # Cycle average of tags in use 2534system.l2c.tags.total_refs 4107458 # Total number of references to valid blocks. 2535system.l2c.tags.sampled_refs 1415378 # Sample count of references to valid blocks. 2536system.l2c.tags.avg_refs 2.902022 # Average number of references to valid blocks. 2537system.l2c.tags.warmup_cycle 9445810500 # Cycle when the warmup percentage was hit. 2538system.l2c.tags.occ_blocks::writebacks 19768.926665 # Average occupied blocks per requestor 2539system.l2c.tags.occ_blocks::cpu0.dtb.walker 228.224478 # Average occupied blocks per requestor 2540system.l2c.tags.occ_blocks::cpu0.itb.walker 327.605712 # Average occupied blocks per requestor 2541system.l2c.tags.occ_blocks::cpu0.inst 4403.400979 # Average occupied blocks per requestor 2542system.l2c.tags.occ_blocks::cpu0.data 13076.363837 # Average occupied blocks per requestor 2543system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14280.609802 # Average occupied blocks per requestor 2544system.l2c.tags.occ_blocks::cpu1.dtb.walker 81.212634 # Average occupied blocks per requestor 2545system.l2c.tags.occ_blocks::cpu1.itb.walker 119.963342 # Average occupied blocks per requestor 2546system.l2c.tags.occ_blocks::cpu1.inst 2392.943065 # Average occupied blocks per requestor 2547system.l2c.tags.occ_blocks::cpu1.data 3574.441825 # Average occupied blocks per requestor 2548system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 5977.605096 # Average occupied blocks per requestor 2549system.l2c.tags.occ_percent::writebacks 0.301650 # Average percentage of cache occupancy 2550system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003482 # Average percentage of cache occupancy 2551system.l2c.tags.occ_percent::cpu0.itb.walker 0.004999 # Average percentage of cache occupancy 2552system.l2c.tags.occ_percent::cpu0.inst 0.067191 # Average percentage of cache occupancy 2553system.l2c.tags.occ_percent::cpu0.data 0.199529 # Average percentage of cache occupancy 2554system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.217905 # Average percentage of cache occupancy 2555system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001239 # Average percentage of cache occupancy 2556system.l2c.tags.occ_percent::cpu1.itb.walker 0.001830 # Average percentage of cache occupancy 2557system.l2c.tags.occ_percent::cpu1.inst 0.036513 # Average percentage of cache occupancy 2558system.l2c.tags.occ_percent::cpu1.data 0.054542 # Average percentage of cache occupancy 2559system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.091211 # Average percentage of cache occupancy 2560system.l2c.tags.occ_percent::total 0.980092 # Average percentage of cache occupancy 2561system.l2c.tags.occ_task_id_blocks::1022 11341 # Occupied blocks per task id 2562system.l2c.tags.occ_task_id_blocks::1023 263 # Occupied blocks per task id 2563system.l2c.tags.occ_task_id_blocks::1024 49312 # Occupied blocks per task id 2564system.l2c.tags.age_task_id_blocks_1022::2 100 # Occupied blocks per task id 2565system.l2c.tags.age_task_id_blocks_1022::3 2022 # Occupied blocks per task id 2566system.l2c.tags.age_task_id_blocks_1022::4 9219 # Occupied blocks per task id 2567system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 2568system.l2c.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 2569system.l2c.tags.age_task_id_blocks_1023::4 259 # Occupied blocks per task id 2570system.l2c.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id 2571system.l2c.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id 2572system.l2c.tags.age_task_id_blocks_1024::2 991 # Occupied blocks per task id 2573system.l2c.tags.age_task_id_blocks_1024::3 9958 # Occupied blocks per task id 2574system.l2c.tags.age_task_id_blocks_1024::4 38095 # Occupied blocks per task id 2575system.l2c.tags.occ_task_id_percent::1022 0.173050 # Percentage of cache occupancy per task id 2576system.l2c.tags.occ_task_id_percent::1023 0.004013 # Percentage of cache occupancy per task id 2577system.l2c.tags.occ_task_id_percent::1024 0.752441 # Percentage of cache occupancy per task id 2578system.l2c.tags.tag_accesses 56299103 # Number of tag accesses 2579system.l2c.tags.data_accesses 56299103 # Number of data accesses 2580system.l2c.ReadReq_hits::cpu0.dtb.walker 5350 # number of ReadReq hits 2581system.l2c.ReadReq_hits::cpu0.itb.walker 4570 # number of ReadReq hits 2582system.l2c.ReadReq_hits::cpu0.inst 461305 # number of ReadReq hits 2583system.l2c.ReadReq_hits::cpu0.data 560254 # number of ReadReq hits 2584system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 286198 # number of ReadReq hits 2585system.l2c.ReadReq_hits::cpu1.dtb.walker 4527 # number of ReadReq hits 2586system.l2c.ReadReq_hits::cpu1.itb.walker 3561 # number of ReadReq hits 2587system.l2c.ReadReq_hits::cpu1.inst 447471 # number of ReadReq hits 2588system.l2c.ReadReq_hits::cpu1.data 478954 # number of ReadReq hits 2589system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 267354 # number of ReadReq hits 2590system.l2c.ReadReq_hits::total 2519544 # number of ReadReq hits 2591system.l2c.Writeback_hits::writebacks 2302237 # number of Writeback hits 2592system.l2c.Writeback_hits::total 2302237 # number of Writeback hits 2593system.l2c.WriteInvalidateReq_hits::cpu0.data 120106 # number of WriteInvalidateReq hits 2594system.l2c.WriteInvalidateReq_hits::cpu1.data 132921 # number of WriteInvalidateReq hits 2595system.l2c.WriteInvalidateReq_hits::total 253027 # number of WriteInvalidateReq hits 2596system.l2c.UpgradeReq_hits::cpu0.data 30097 # number of UpgradeReq hits 2597system.l2c.UpgradeReq_hits::cpu1.data 26085 # number of UpgradeReq hits 2598system.l2c.UpgradeReq_hits::total 56182 # number of UpgradeReq hits 2599system.l2c.SCUpgradeReq_hits::cpu0.data 6492 # number of SCUpgradeReq hits 2600system.l2c.SCUpgradeReq_hits::cpu1.data 6040 # number of SCUpgradeReq hits 2601system.l2c.SCUpgradeReq_hits::total 12532 # number of SCUpgradeReq hits 2602system.l2c.ReadExReq_hits::cpu0.data 53617 # number of ReadExReq hits 2603system.l2c.ReadExReq_hits::cpu1.data 43662 # number of ReadExReq hits 2604system.l2c.ReadExReq_hits::total 97279 # number of ReadExReq hits 2605system.l2c.demand_hits::cpu0.dtb.walker 5350 # number of demand (read+write) hits 2606system.l2c.demand_hits::cpu0.itb.walker 4570 # number of demand (read+write) hits 2607system.l2c.demand_hits::cpu0.inst 461305 # number of demand (read+write) hits 2608system.l2c.demand_hits::cpu0.data 613871 # number of demand (read+write) hits 2609system.l2c.demand_hits::cpu0.l2cache.prefetcher 286198 # number of demand (read+write) hits 2610system.l2c.demand_hits::cpu1.dtb.walker 4527 # number of demand (read+write) hits 2611system.l2c.demand_hits::cpu1.itb.walker 3561 # number of demand (read+write) hits 2612system.l2c.demand_hits::cpu1.inst 447471 # number of demand (read+write) hits 2613system.l2c.demand_hits::cpu1.data 522616 # number of demand (read+write) hits 2614system.l2c.demand_hits::cpu1.l2cache.prefetcher 267354 # number of demand (read+write) hits 2615system.l2c.demand_hits::total 2616823 # number of demand (read+write) hits 2616system.l2c.overall_hits::cpu0.dtb.walker 5350 # number of overall hits 2617system.l2c.overall_hits::cpu0.itb.walker 4570 # number of overall hits 2618system.l2c.overall_hits::cpu0.inst 461305 # number of overall hits 2619system.l2c.overall_hits::cpu0.data 613871 # number of overall hits 2620system.l2c.overall_hits::cpu0.l2cache.prefetcher 286198 # number of overall hits 2621system.l2c.overall_hits::cpu1.dtb.walker 4527 # number of overall hits 2622system.l2c.overall_hits::cpu1.itb.walker 3561 # number of overall hits 2623system.l2c.overall_hits::cpu1.inst 447471 # number of overall hits 2624system.l2c.overall_hits::cpu1.data 522616 # number of overall hits 2625system.l2c.overall_hits::cpu1.l2cache.prefetcher 267354 # number of overall hits 2626system.l2c.overall_hits::total 2616823 # number of overall hits 2627system.l2c.ReadReq_misses::cpu0.dtb.walker 2413 # number of ReadReq misses 2628system.l2c.ReadReq_misses::cpu0.itb.walker 2450 # number of ReadReq misses 2629system.l2c.ReadReq_misses::cpu0.inst 52896 # number of ReadReq misses 2630system.l2c.ReadReq_misses::cpu0.data 145508 # number of ReadReq misses 2631system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 228001 # number of ReadReq misses 2632system.l2c.ReadReq_misses::cpu1.dtb.walker 1040 # number of ReadReq misses 2633system.l2c.ReadReq_misses::cpu1.itb.walker 936 # number of ReadReq misses 2634system.l2c.ReadReq_misses::cpu1.inst 43985 # number of ReadReq misses 2635system.l2c.ReadReq_misses::cpu1.data 87538 # number of ReadReq misses 2636system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 186786 # number of ReadReq misses 2637system.l2c.ReadReq_misses::total 751553 # number of ReadReq misses 2638system.l2c.WriteInvalidateReq_misses::cpu0.data 416232 # number of WriteInvalidateReq misses 2639system.l2c.WriteInvalidateReq_misses::cpu1.data 144931 # number of WriteInvalidateReq misses 2640system.l2c.WriteInvalidateReq_misses::total 561163 # number of WriteInvalidateReq misses 2641system.l2c.UpgradeReq_misses::cpu0.data 42338 # number of UpgradeReq misses 2642system.l2c.UpgradeReq_misses::cpu1.data 43944 # number of UpgradeReq misses 2643system.l2c.UpgradeReq_misses::total 86282 # number of UpgradeReq misses 2644system.l2c.SCUpgradeReq_misses::cpu0.data 11190 # number of SCUpgradeReq misses 2645system.l2c.SCUpgradeReq_misses::cpu1.data 10651 # number of SCUpgradeReq misses 2646system.l2c.SCUpgradeReq_misses::total 21841 # number of SCUpgradeReq misses 2647system.l2c.ReadExReq_misses::cpu0.data 76863 # number of ReadExReq misses 2648system.l2c.ReadExReq_misses::cpu1.data 48194 # number of ReadExReq misses 2649system.l2c.ReadExReq_misses::total 125057 # number of ReadExReq misses 2650system.l2c.demand_misses::cpu0.dtb.walker 2413 # number of demand (read+write) misses 2651system.l2c.demand_misses::cpu0.itb.walker 2450 # number of demand (read+write) misses 2652system.l2c.demand_misses::cpu0.inst 52896 # number of demand (read+write) misses 2653system.l2c.demand_misses::cpu0.data 222371 # number of demand (read+write) misses 2654system.l2c.demand_misses::cpu0.l2cache.prefetcher 228001 # number of demand (read+write) misses 2655system.l2c.demand_misses::cpu1.dtb.walker 1040 # number of demand (read+write) misses 2656system.l2c.demand_misses::cpu1.itb.walker 936 # number of demand (read+write) misses 2657system.l2c.demand_misses::cpu1.inst 43985 # number of demand (read+write) misses 2658system.l2c.demand_misses::cpu1.data 135732 # number of demand (read+write) misses 2659system.l2c.demand_misses::cpu1.l2cache.prefetcher 186786 # number of demand (read+write) misses 2660system.l2c.demand_misses::total 876610 # number of demand (read+write) misses 2661system.l2c.overall_misses::cpu0.dtb.walker 2413 # number of overall misses 2662system.l2c.overall_misses::cpu0.itb.walker 2450 # number of overall misses 2663system.l2c.overall_misses::cpu0.inst 52896 # number of overall misses 2664system.l2c.overall_misses::cpu0.data 222371 # number of overall misses 2665system.l2c.overall_misses::cpu0.l2cache.prefetcher 228001 # number of overall misses 2666system.l2c.overall_misses::cpu1.dtb.walker 1040 # number of overall misses 2667system.l2c.overall_misses::cpu1.itb.walker 936 # number of overall misses 2668system.l2c.overall_misses::cpu1.inst 43985 # number of overall misses 2669system.l2c.overall_misses::cpu1.data 135732 # number of overall misses 2670system.l2c.overall_misses::cpu1.l2cache.prefetcher 186786 # number of overall misses 2671system.l2c.overall_misses::total 876610 # number of overall misses 2672system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 195380250 # number of ReadReq miss cycles 2673system.l2c.ReadReq_miss_latency::cpu0.itb.walker 200494999 # number of ReadReq miss cycles 2674system.l2c.ReadReq_miss_latency::cpu0.inst 4090074480 # number of ReadReq miss cycles 2675system.l2c.ReadReq_miss_latency::cpu0.data 12129961164 # number of ReadReq miss cycles 2676system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 29105524558 # number of ReadReq miss cycles 2677system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 84415498 # number of ReadReq miss cycles 2678system.l2c.ReadReq_miss_latency::cpu1.itb.walker 77437999 # number of ReadReq miss cycles 2679system.l2c.ReadReq_miss_latency::cpu1.inst 3371676973 # number of ReadReq miss cycles 2680system.l2c.ReadReq_miss_latency::cpu1.data 7239872891 # number of ReadReq miss cycles 2681system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 24292116803 # number of ReadReq miss cycles 2682system.l2c.ReadReq_miss_latency::total 80786955615 # number of ReadReq miss cycles 2683system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 28586777 # number of WriteInvalidateReq miss cycles 2684system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 37049410 # number of WriteInvalidateReq miss cycles 2685system.l2c.WriteInvalidateReq_miss_latency::total 65636187 # number of WriteInvalidateReq miss cycles 2686system.l2c.UpgradeReq_miss_latency::cpu0.data 168593848 # number of UpgradeReq miss cycles 2687system.l2c.UpgradeReq_miss_latency::cpu1.data 188274034 # number of UpgradeReq miss cycles 2688system.l2c.UpgradeReq_miss_latency::total 356867882 # number of UpgradeReq miss cycles 2689system.l2c.SCUpgradeReq_miss_latency::cpu0.data 43019164 # number of SCUpgradeReq miss cycles 2690system.l2c.SCUpgradeReq_miss_latency::cpu1.data 45414580 # number of SCUpgradeReq miss cycles 2691system.l2c.SCUpgradeReq_miss_latency::total 88433744 # number of SCUpgradeReq miss cycles 2692system.l2c.ReadExReq_miss_latency::cpu0.data 6101127950 # number of ReadExReq miss cycles 2693system.l2c.ReadExReq_miss_latency::cpu1.data 3658485827 # number of ReadExReq miss cycles 2694system.l2c.ReadExReq_miss_latency::total 9759613777 # number of ReadExReq miss cycles 2695system.l2c.demand_miss_latency::cpu0.dtb.walker 195380250 # number of demand (read+write) miss cycles 2696system.l2c.demand_miss_latency::cpu0.itb.walker 200494999 # number of demand (read+write) miss cycles 2697system.l2c.demand_miss_latency::cpu0.inst 4090074480 # number of demand (read+write) miss cycles 2698system.l2c.demand_miss_latency::cpu0.data 18231089114 # number of demand (read+write) miss cycles 2699system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 29105524558 # number of demand (read+write) miss cycles 2700system.l2c.demand_miss_latency::cpu1.dtb.walker 84415498 # number of demand (read+write) miss cycles 2701system.l2c.demand_miss_latency::cpu1.itb.walker 77437999 # number of demand (read+write) miss cycles 2702system.l2c.demand_miss_latency::cpu1.inst 3371676973 # number of demand (read+write) miss cycles 2703system.l2c.demand_miss_latency::cpu1.data 10898358718 # number of demand (read+write) miss cycles 2704system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 24292116803 # number of demand (read+write) miss cycles 2705system.l2c.demand_miss_latency::total 90546569392 # number of demand (read+write) miss cycles 2706system.l2c.overall_miss_latency::cpu0.dtb.walker 195380250 # number of overall miss cycles 2707system.l2c.overall_miss_latency::cpu0.itb.walker 200494999 # number of overall miss cycles 2708system.l2c.overall_miss_latency::cpu0.inst 4090074480 # number of overall miss cycles 2709system.l2c.overall_miss_latency::cpu0.data 18231089114 # number of overall miss cycles 2710system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 29105524558 # number of overall miss cycles 2711system.l2c.overall_miss_latency::cpu1.dtb.walker 84415498 # number of overall miss cycles 2712system.l2c.overall_miss_latency::cpu1.itb.walker 77437999 # number of overall miss cycles 2713system.l2c.overall_miss_latency::cpu1.inst 3371676973 # number of overall miss cycles 2714system.l2c.overall_miss_latency::cpu1.data 10898358718 # number of overall miss cycles 2715system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 24292116803 # number of overall miss cycles 2716system.l2c.overall_miss_latency::total 90546569392 # number of overall miss cycles 2717system.l2c.ReadReq_accesses::cpu0.dtb.walker 7763 # number of ReadReq accesses(hits+misses) 2718system.l2c.ReadReq_accesses::cpu0.itb.walker 7020 # number of ReadReq accesses(hits+misses) 2719system.l2c.ReadReq_accesses::cpu0.inst 514201 # number of ReadReq accesses(hits+misses) 2720system.l2c.ReadReq_accesses::cpu0.data 705762 # number of ReadReq accesses(hits+misses) 2721system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 514199 # number of ReadReq accesses(hits+misses) 2722system.l2c.ReadReq_accesses::cpu1.dtb.walker 5567 # number of ReadReq accesses(hits+misses) 2723system.l2c.ReadReq_accesses::cpu1.itb.walker 4497 # number of ReadReq accesses(hits+misses) 2724system.l2c.ReadReq_accesses::cpu1.inst 491456 # number of ReadReq accesses(hits+misses) 2725system.l2c.ReadReq_accesses::cpu1.data 566492 # number of ReadReq accesses(hits+misses) 2726system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 454140 # number of ReadReq accesses(hits+misses) 2727system.l2c.ReadReq_accesses::total 3271097 # number of ReadReq accesses(hits+misses) 2728system.l2c.Writeback_accesses::writebacks 2302237 # number of Writeback accesses(hits+misses) 2729system.l2c.Writeback_accesses::total 2302237 # number of Writeback accesses(hits+misses) 2730system.l2c.WriteInvalidateReq_accesses::cpu0.data 536338 # number of WriteInvalidateReq accesses(hits+misses) 2731system.l2c.WriteInvalidateReq_accesses::cpu1.data 277852 # number of WriteInvalidateReq accesses(hits+misses) 2732system.l2c.WriteInvalidateReq_accesses::total 814190 # number of WriteInvalidateReq accesses(hits+misses) 2733system.l2c.UpgradeReq_accesses::cpu0.data 72435 # number of UpgradeReq accesses(hits+misses) 2734system.l2c.UpgradeReq_accesses::cpu1.data 70029 # number of UpgradeReq accesses(hits+misses) 2735system.l2c.UpgradeReq_accesses::total 142464 # number of UpgradeReq accesses(hits+misses) 2736system.l2c.SCUpgradeReq_accesses::cpu0.data 17682 # number of SCUpgradeReq accesses(hits+misses) 2737system.l2c.SCUpgradeReq_accesses::cpu1.data 16691 # number of SCUpgradeReq accesses(hits+misses) 2738system.l2c.SCUpgradeReq_accesses::total 34373 # number of SCUpgradeReq accesses(hits+misses) 2739system.l2c.ReadExReq_accesses::cpu0.data 130480 # number of ReadExReq accesses(hits+misses) 2740system.l2c.ReadExReq_accesses::cpu1.data 91856 # number of ReadExReq accesses(hits+misses) 2741system.l2c.ReadExReq_accesses::total 222336 # number of ReadExReq accesses(hits+misses) 2742system.l2c.demand_accesses::cpu0.dtb.walker 7763 # number of demand (read+write) accesses 2743system.l2c.demand_accesses::cpu0.itb.walker 7020 # number of demand (read+write) accesses 2744system.l2c.demand_accesses::cpu0.inst 514201 # number of demand (read+write) accesses 2745system.l2c.demand_accesses::cpu0.data 836242 # number of demand (read+write) accesses 2746system.l2c.demand_accesses::cpu0.l2cache.prefetcher 514199 # number of demand (read+write) accesses 2747system.l2c.demand_accesses::cpu1.dtb.walker 5567 # number of demand (read+write) accesses 2748system.l2c.demand_accesses::cpu1.itb.walker 4497 # number of demand (read+write) accesses 2749system.l2c.demand_accesses::cpu1.inst 491456 # number of demand (read+write) accesses 2750system.l2c.demand_accesses::cpu1.data 658348 # number of demand (read+write) accesses 2751system.l2c.demand_accesses::cpu1.l2cache.prefetcher 454140 # number of demand (read+write) accesses 2752system.l2c.demand_accesses::total 3493433 # number of demand (read+write) accesses 2753system.l2c.overall_accesses::cpu0.dtb.walker 7763 # number of overall (read+write) accesses 2754system.l2c.overall_accesses::cpu0.itb.walker 7020 # number of overall (read+write) accesses 2755system.l2c.overall_accesses::cpu0.inst 514201 # number of overall (read+write) accesses 2756system.l2c.overall_accesses::cpu0.data 836242 # number of overall (read+write) accesses 2757system.l2c.overall_accesses::cpu0.l2cache.prefetcher 514199 # number of overall (read+write) accesses 2758system.l2c.overall_accesses::cpu1.dtb.walker 5567 # number of overall (read+write) accesses 2759system.l2c.overall_accesses::cpu1.itb.walker 4497 # number of overall (read+write) accesses 2760system.l2c.overall_accesses::cpu1.inst 491456 # number of overall (read+write) accesses 2761system.l2c.overall_accesses::cpu1.data 658348 # number of overall (read+write) accesses 2762system.l2c.overall_accesses::cpu1.l2cache.prefetcher 454140 # number of overall (read+write) accesses 2763system.l2c.overall_accesses::total 3493433 # number of overall (read+write) accesses 2764system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.310833 # miss rate for ReadReq accesses 2765system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.349003 # miss rate for ReadReq accesses 2766system.l2c.ReadReq_miss_rate::cpu0.inst 0.102870 # miss rate for ReadReq accesses 2767system.l2c.ReadReq_miss_rate::cpu0.data 0.206171 # miss rate for ReadReq accesses 2768system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.443410 # miss rate for ReadReq accesses 2769system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.186815 # miss rate for ReadReq accesses 2770system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.208139 # miss rate for ReadReq accesses 2771system.l2c.ReadReq_miss_rate::cpu1.inst 0.089499 # miss rate for ReadReq accesses 2772system.l2c.ReadReq_miss_rate::cpu1.data 0.154526 # miss rate for ReadReq accesses 2773system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.411296 # miss rate for ReadReq accesses 2774system.l2c.ReadReq_miss_rate::total 0.229756 # miss rate for ReadReq accesses 2775system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.776063 # miss rate for WriteInvalidateReq accesses 2776system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.521612 # miss rate for WriteInvalidateReq accesses 2777system.l2c.WriteInvalidateReq_miss_rate::total 0.689229 # miss rate for WriteInvalidateReq accesses 2778system.l2c.UpgradeReq_miss_rate::cpu0.data 0.584496 # miss rate for UpgradeReq accesses 2779system.l2c.UpgradeReq_miss_rate::cpu1.data 0.627511 # miss rate for UpgradeReq accesses 2780system.l2c.UpgradeReq_miss_rate::total 0.605641 # miss rate for UpgradeReq accesses 2781system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.632847 # miss rate for SCUpgradeReq accesses 2782system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.638128 # miss rate for SCUpgradeReq accesses 2783system.l2c.SCUpgradeReq_miss_rate::total 0.635412 # miss rate for SCUpgradeReq accesses 2784system.l2c.ReadExReq_miss_rate::cpu0.data 0.589079 # miss rate for ReadExReq accesses 2785system.l2c.ReadExReq_miss_rate::cpu1.data 0.524669 # miss rate for ReadExReq accesses 2786system.l2c.ReadExReq_miss_rate::total 0.562469 # miss rate for ReadExReq accesses 2787system.l2c.demand_miss_rate::cpu0.dtb.walker 0.310833 # miss rate for demand accesses 2788system.l2c.demand_miss_rate::cpu0.itb.walker 0.349003 # miss rate for demand accesses 2789system.l2c.demand_miss_rate::cpu0.inst 0.102870 # miss rate for demand accesses 2790system.l2c.demand_miss_rate::cpu0.data 0.265917 # miss rate for demand accesses 2791system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.443410 # miss rate for demand accesses 2792system.l2c.demand_miss_rate::cpu1.dtb.walker 0.186815 # miss rate for demand accesses 2793system.l2c.demand_miss_rate::cpu1.itb.walker 0.208139 # miss rate for demand accesses 2794system.l2c.demand_miss_rate::cpu1.inst 0.089499 # miss rate for demand accesses 2795system.l2c.demand_miss_rate::cpu1.data 0.206171 # miss rate for demand accesses 2796system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.411296 # miss rate for demand accesses 2797system.l2c.demand_miss_rate::total 0.250931 # miss rate for demand accesses 2798system.l2c.overall_miss_rate::cpu0.dtb.walker 0.310833 # miss rate for overall accesses 2799system.l2c.overall_miss_rate::cpu0.itb.walker 0.349003 # miss rate for overall accesses 2800system.l2c.overall_miss_rate::cpu0.inst 0.102870 # miss rate for overall accesses 2801system.l2c.overall_miss_rate::cpu0.data 0.265917 # miss rate for overall accesses 2802system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.443410 # miss rate for overall accesses 2803system.l2c.overall_miss_rate::cpu1.dtb.walker 0.186815 # miss rate for overall accesses 2804system.l2c.overall_miss_rate::cpu1.itb.walker 0.208139 # miss rate for overall accesses 2805system.l2c.overall_miss_rate::cpu1.inst 0.089499 # miss rate for overall accesses 2806system.l2c.overall_miss_rate::cpu1.data 0.206171 # miss rate for overall accesses 2807system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.411296 # miss rate for overall accesses 2808system.l2c.overall_miss_rate::total 0.250931 # miss rate for overall accesses 2809system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 80969.850808 # average ReadReq miss latency 2810system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 81834.693469 # average ReadReq miss latency 2811system.l2c.ReadReq_avg_miss_latency::cpu0.inst 77322.944646 # average ReadReq miss latency 2812system.l2c.ReadReq_avg_miss_latency::cpu0.data 83362.847156 # average ReadReq miss latency 2813system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 127655.249573 # average ReadReq miss latency 2814system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 81168.748077 # average ReadReq miss latency 2815system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 82732.904915 # average ReadReq miss latency 2816system.l2c.ReadReq_avg_miss_latency::cpu1.inst 76655.154553 # average ReadReq miss latency 2817system.l2c.ReadReq_avg_miss_latency::cpu1.data 82705.486657 # average ReadReq miss latency 2818system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 130053.198864 # average ReadReq miss latency 2819system.l2c.ReadReq_avg_miss_latency::total 107493.357907 # average ReadReq miss latency 2820system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 68.679912 # average WriteInvalidateReq miss latency 2821system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 255.634819 # average WriteInvalidateReq miss latency 2822system.l2c.WriteInvalidateReq_avg_miss_latency::total 116.964566 # average WriteInvalidateReq miss latency 2823system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3982.092872 # average UpgradeReq miss latency 2824system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4284.408201 # average UpgradeReq miss latency 2825system.l2c.UpgradeReq_avg_miss_latency::total 4136.064092 # average UpgradeReq miss latency 2826system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3844.429312 # average SCUpgradeReq miss latency 2827system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4263.879448 # average SCUpgradeReq miss latency 2828system.l2c.SCUpgradeReq_avg_miss_latency::total 4048.978710 # average SCUpgradeReq miss latency 2829system.l2c.ReadExReq_avg_miss_latency::cpu0.data 79376.656519 # average ReadExReq miss latency 2830system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75911.645163 # average ReadExReq miss latency 2831system.l2c.ReadExReq_avg_miss_latency::total 78041.323373 # average ReadExReq miss latency 2832system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 80969.850808 # average overall miss latency 2833system.l2c.demand_avg_miss_latency::cpu0.itb.walker 81834.693469 # average overall miss latency 2834system.l2c.demand_avg_miss_latency::cpu0.inst 77322.944646 # average overall miss latency 2835system.l2c.demand_avg_miss_latency::cpu0.data 81985.012047 # average overall miss latency 2836system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 127655.249573 # average overall miss latency 2837system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 81168.748077 # average overall miss latency 2838system.l2c.demand_avg_miss_latency::cpu1.itb.walker 82732.904915 # average overall miss latency 2839system.l2c.demand_avg_miss_latency::cpu1.inst 76655.154553 # average overall miss latency 2840system.l2c.demand_avg_miss_latency::cpu1.data 80293.215439 # average overall miss latency 2841system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 130053.198864 # average overall miss latency 2842system.l2c.demand_avg_miss_latency::total 103291.736795 # average overall miss latency 2843system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 80969.850808 # average overall miss latency 2844system.l2c.overall_avg_miss_latency::cpu0.itb.walker 81834.693469 # average overall miss latency 2845system.l2c.overall_avg_miss_latency::cpu0.inst 77322.944646 # average overall miss latency 2846system.l2c.overall_avg_miss_latency::cpu0.data 81985.012047 # average overall miss latency 2847system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 127655.249573 # average overall miss latency 2848system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 81168.748077 # average overall miss latency 2849system.l2c.overall_avg_miss_latency::cpu1.itb.walker 82732.904915 # average overall miss latency 2850system.l2c.overall_avg_miss_latency::cpu1.inst 76655.154553 # average overall miss latency 2851system.l2c.overall_avg_miss_latency::cpu1.data 80293.215439 # average overall miss latency 2852system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 130053.198864 # average overall miss latency 2853system.l2c.overall_avg_miss_latency::total 103291.736795 # average overall miss latency 2854system.l2c.blocked_cycles::no_mshrs 198 # number of cycles access was blocked 2855system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2856system.l2c.blocked::no_mshrs 2 # number of cycles access was blocked 2857system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2858system.l2c.avg_blocked_cycles::no_mshrs 99 # average number of cycles each access was blocked 2859system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2860system.l2c.fast_writes 0 # number of fast writes performed 2861system.l2c.cache_copies 0 # number of cache copies performed 2862system.l2c.writebacks::writebacks 1054885 # number of writebacks 2863system.l2c.writebacks::total 1054885 # number of writebacks 2864system.l2c.ReadReq_mshr_hits::cpu0.inst 92 # number of ReadReq MSHR hits 2865system.l2c.ReadReq_mshr_hits::cpu0.data 68 # number of ReadReq MSHR hits 2866system.l2c.ReadReq_mshr_hits::cpu1.inst 78 # number of ReadReq MSHR hits 2867system.l2c.ReadReq_mshr_hits::cpu1.data 18 # number of ReadReq MSHR hits 2868system.l2c.ReadReq_mshr_hits::total 256 # number of ReadReq MSHR hits 2869system.l2c.demand_mshr_hits::cpu0.inst 92 # number of demand (read+write) MSHR hits 2870system.l2c.demand_mshr_hits::cpu0.data 68 # number of demand (read+write) MSHR hits 2871system.l2c.demand_mshr_hits::cpu1.inst 78 # number of demand (read+write) MSHR hits 2872system.l2c.demand_mshr_hits::cpu1.data 18 # number of demand (read+write) MSHR hits 2873system.l2c.demand_mshr_hits::total 256 # number of demand (read+write) MSHR hits 2874system.l2c.overall_mshr_hits::cpu0.inst 92 # number of overall MSHR hits 2875system.l2c.overall_mshr_hits::cpu0.data 68 # number of overall MSHR hits 2876system.l2c.overall_mshr_hits::cpu1.inst 78 # number of overall MSHR hits 2877system.l2c.overall_mshr_hits::cpu1.data 18 # number of overall MSHR hits 2878system.l2c.overall_mshr_hits::total 256 # number of overall MSHR hits 2879system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 2413 # number of ReadReq MSHR misses 2880system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2450 # number of ReadReq MSHR misses 2881system.l2c.ReadReq_mshr_misses::cpu0.inst 52804 # number of ReadReq MSHR misses 2882system.l2c.ReadReq_mshr_misses::cpu0.data 145440 # number of ReadReq MSHR misses 2883system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 228001 # number of ReadReq MSHR misses 2884system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1040 # number of ReadReq MSHR misses 2885system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 936 # number of ReadReq MSHR misses 2886system.l2c.ReadReq_mshr_misses::cpu1.inst 43907 # number of ReadReq MSHR misses 2887system.l2c.ReadReq_mshr_misses::cpu1.data 87520 # number of ReadReq MSHR misses 2888system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 186786 # number of ReadReq MSHR misses 2889system.l2c.ReadReq_mshr_misses::total 751297 # number of ReadReq MSHR misses 2890system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 416232 # number of WriteInvalidateReq MSHR misses 2891system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 144931 # number of WriteInvalidateReq MSHR misses 2892system.l2c.WriteInvalidateReq_mshr_misses::total 561163 # number of WriteInvalidateReq MSHR misses 2893system.l2c.UpgradeReq_mshr_misses::cpu0.data 42338 # number of UpgradeReq MSHR misses 2894system.l2c.UpgradeReq_mshr_misses::cpu1.data 43944 # number of UpgradeReq MSHR misses 2895system.l2c.UpgradeReq_mshr_misses::total 86282 # number of UpgradeReq MSHR misses 2896system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 11190 # number of SCUpgradeReq MSHR misses 2897system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 10651 # number of SCUpgradeReq MSHR misses 2898system.l2c.SCUpgradeReq_mshr_misses::total 21841 # number of SCUpgradeReq MSHR misses 2899system.l2c.ReadExReq_mshr_misses::cpu0.data 76863 # number of ReadExReq MSHR misses 2900system.l2c.ReadExReq_mshr_misses::cpu1.data 48194 # number of ReadExReq MSHR misses 2901system.l2c.ReadExReq_mshr_misses::total 125057 # number of ReadExReq MSHR misses 2902system.l2c.demand_mshr_misses::cpu0.dtb.walker 2413 # number of demand (read+write) MSHR misses 2903system.l2c.demand_mshr_misses::cpu0.itb.walker 2450 # number of demand (read+write) MSHR misses 2904system.l2c.demand_mshr_misses::cpu0.inst 52804 # number of demand (read+write) MSHR misses 2905system.l2c.demand_mshr_misses::cpu0.data 222303 # number of demand (read+write) MSHR misses 2906system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 228001 # number of demand (read+write) MSHR misses 2907system.l2c.demand_mshr_misses::cpu1.dtb.walker 1040 # number of demand (read+write) MSHR misses 2908system.l2c.demand_mshr_misses::cpu1.itb.walker 936 # number of demand (read+write) MSHR misses 2909system.l2c.demand_mshr_misses::cpu1.inst 43907 # number of demand (read+write) MSHR misses 2910system.l2c.demand_mshr_misses::cpu1.data 135714 # number of demand (read+write) MSHR misses 2911system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 186786 # number of demand (read+write) MSHR misses 2912system.l2c.demand_mshr_misses::total 876354 # number of demand (read+write) MSHR misses 2913system.l2c.overall_mshr_misses::cpu0.dtb.walker 2413 # number of overall MSHR misses 2914system.l2c.overall_mshr_misses::cpu0.itb.walker 2450 # number of overall MSHR misses 2915system.l2c.overall_mshr_misses::cpu0.inst 52804 # number of overall MSHR misses 2916system.l2c.overall_mshr_misses::cpu0.data 222303 # number of overall MSHR misses 2917system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 228001 # number of overall MSHR misses 2918system.l2c.overall_mshr_misses::cpu1.dtb.walker 1040 # number of overall MSHR misses 2919system.l2c.overall_mshr_misses::cpu1.itb.walker 936 # number of overall MSHR misses 2920system.l2c.overall_mshr_misses::cpu1.inst 43907 # number of overall MSHR misses 2921system.l2c.overall_mshr_misses::cpu1.data 135714 # number of overall MSHR misses 2922system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 186786 # number of overall MSHR misses 2923system.l2c.overall_mshr_misses::total 876354 # number of overall MSHR misses 2924system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 165146250 # number of ReadReq MSHR miss cycles 2925system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 169847499 # number of ReadReq MSHR miss cycles 2926system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 3419732984 # number of ReadReq MSHR miss cycles 2927system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10297367216 # number of ReadReq MSHR miss cycles 2928system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 26304444558 # number of ReadReq MSHR miss cycles 2929system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 71400998 # number of ReadReq MSHR miss cycles 2930system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 65754499 # number of ReadReq MSHR miss cycles 2931system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 2814972981 # number of ReadReq MSHR miss cycles 2932system.l2c.ReadReq_mshr_miss_latency::cpu1.data 6141826747 # number of ReadReq MSHR miss cycles 2933system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 21997660303 # number of ReadReq MSHR miss cycles 2934system.l2c.ReadReq_mshr_miss_latency::total 71448154035 # number of ReadReq MSHR miss cycles 2935system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 9351321200 # number of WriteInvalidateReq MSHR miss cycles 2936system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 2933979052 # number of WriteInvalidateReq MSHR miss cycles 2937system.l2c.WriteInvalidateReq_mshr_miss_latency::total 12285300252 # number of WriteInvalidateReq MSHR miss cycles 2938system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 426814585 # number of UpgradeReq MSHR miss cycles 2939system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 447026638 # number of UpgradeReq MSHR miss cycles 2940system.l2c.UpgradeReq_mshr_miss_latency::total 873841223 # number of UpgradeReq MSHR miss cycles 2941system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 112957622 # number of SCUpgradeReq MSHR miss cycles 2942system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 108321571 # number of SCUpgradeReq MSHR miss cycles 2943system.l2c.SCUpgradeReq_mshr_miss_latency::total 221279193 # number of SCUpgradeReq MSHR miss cycles 2944system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5133347486 # number of ReadExReq MSHR miss cycles 2945system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3050003137 # number of ReadExReq MSHR miss cycles 2946system.l2c.ReadExReq_mshr_miss_latency::total 8183350623 # number of ReadExReq MSHR miss cycles 2947system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 165146250 # number of demand (read+write) MSHR miss cycles 2948system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 169847499 # number of demand (read+write) MSHR miss cycles 2949system.l2c.demand_mshr_miss_latency::cpu0.inst 3419732984 # number of demand (read+write) MSHR miss cycles 2950system.l2c.demand_mshr_miss_latency::cpu0.data 15430714702 # number of demand (read+write) MSHR miss cycles 2951system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 26304444558 # number of demand (read+write) MSHR miss cycles 2952system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 71400998 # number of demand (read+write) MSHR miss cycles 2953system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 65754499 # number of demand (read+write) MSHR miss cycles 2954system.l2c.demand_mshr_miss_latency::cpu1.inst 2814972981 # number of demand (read+write) MSHR miss cycles 2955system.l2c.demand_mshr_miss_latency::cpu1.data 9191829884 # number of demand (read+write) MSHR miss cycles 2956system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 21997660303 # number of demand (read+write) MSHR miss cycles 2957system.l2c.demand_mshr_miss_latency::total 79631504658 # number of demand (read+write) MSHR miss cycles 2958system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 165146250 # number of overall MSHR miss cycles 2959system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 169847499 # number of overall MSHR miss cycles 2960system.l2c.overall_mshr_miss_latency::cpu0.inst 3419732984 # number of overall MSHR miss cycles 2961system.l2c.overall_mshr_miss_latency::cpu0.data 15430714702 # number of overall MSHR miss cycles 2962system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 26304444558 # number of overall MSHR miss cycles 2963system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 71400998 # number of overall MSHR miss cycles 2964system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 65754499 # number of overall MSHR miss cycles 2965system.l2c.overall_mshr_miss_latency::cpu1.inst 2814972981 # number of overall MSHR miss cycles 2966system.l2c.overall_mshr_miss_latency::cpu1.data 9191829884 # number of overall MSHR miss cycles 2967system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 21997660303 # number of overall MSHR miss cycles 2968system.l2c.overall_mshr_miss_latency::total 79631504658 # number of overall MSHR miss cycles 2969system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2246197250 # number of ReadReq MSHR uncacheable cycles 2970system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1919142750 # number of ReadReq MSHR uncacheable cycles 2971system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6014500 # number of ReadReq MSHR uncacheable cycles 2972system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3441525748 # number of ReadReq MSHR uncacheable cycles 2973system.l2c.ReadReq_mshr_uncacheable_latency::total 7612880248 # number of ReadReq MSHR uncacheable cycles 2974system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1867778498 # number of WriteReq MSHR uncacheable cycles 2975system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 3390717000 # number of WriteReq MSHR uncacheable cycles 2976system.l2c.WriteReq_mshr_uncacheable_latency::total 5258495498 # number of WriteReq MSHR uncacheable cycles 2977system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2246197250 # number of overall MSHR uncacheable cycles 2978system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3786921248 # number of overall MSHR uncacheable cycles 2979system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6014500 # number of overall MSHR uncacheable cycles 2980system.l2c.overall_mshr_uncacheable_latency::cpu1.data 6832242748 # number of overall MSHR uncacheable cycles 2981system.l2c.overall_mshr_uncacheable_latency::total 12871375746 # number of overall MSHR uncacheable cycles 2982system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.310833 # mshr miss rate for ReadReq accesses 2983system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.349003 # mshr miss rate for ReadReq accesses 2984system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.102691 # mshr miss rate for ReadReq accesses 2985system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.206075 # mshr miss rate for ReadReq accesses 2986system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.443410 # mshr miss rate for ReadReq accesses 2987system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.186815 # mshr miss rate for ReadReq accesses 2988system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.208139 # mshr miss rate for ReadReq accesses 2989system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.089341 # mshr miss rate for ReadReq accesses 2990system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.154495 # mshr miss rate for ReadReq accesses 2991system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.411296 # mshr miss rate for ReadReq accesses 2992system.l2c.ReadReq_mshr_miss_rate::total 0.229677 # mshr miss rate for ReadReq accesses 2993system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.776063 # mshr miss rate for WriteInvalidateReq accesses 2994system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.521612 # mshr miss rate for WriteInvalidateReq accesses 2995system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.689229 # mshr miss rate for WriteInvalidateReq accesses 2996system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.584496 # mshr miss rate for UpgradeReq accesses 2997system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.627511 # mshr miss rate for UpgradeReq accesses 2998system.l2c.UpgradeReq_mshr_miss_rate::total 0.605641 # mshr miss rate for UpgradeReq accesses 2999system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.632847 # mshr miss rate for SCUpgradeReq accesses 3000system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.638128 # mshr miss rate for SCUpgradeReq accesses 3001system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.635412 # mshr miss rate for SCUpgradeReq accesses 3002system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.589079 # mshr miss rate for ReadExReq accesses 3003system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.524669 # mshr miss rate for ReadExReq accesses 3004system.l2c.ReadExReq_mshr_miss_rate::total 0.562469 # mshr miss rate for ReadExReq accesses 3005system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.310833 # mshr miss rate for demand accesses 3006system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.349003 # mshr miss rate for demand accesses 3007system.l2c.demand_mshr_miss_rate::cpu0.inst 0.102691 # mshr miss rate for demand accesses 3008system.l2c.demand_mshr_miss_rate::cpu0.data 0.265836 # mshr miss rate for demand accesses 3009system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.443410 # mshr miss rate for demand accesses 3010system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.186815 # mshr miss rate for demand accesses 3011system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.208139 # mshr miss rate for demand accesses 3012system.l2c.demand_mshr_miss_rate::cpu1.inst 0.089341 # mshr miss rate for demand accesses 3013system.l2c.demand_mshr_miss_rate::cpu1.data 0.206143 # mshr miss rate for demand accesses 3014system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.411296 # mshr miss rate for demand accesses 3015system.l2c.demand_mshr_miss_rate::total 0.250858 # mshr miss rate for demand accesses 3016system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.310833 # mshr miss rate for overall accesses 3017system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.349003 # mshr miss rate for overall accesses 3018system.l2c.overall_mshr_miss_rate::cpu0.inst 0.102691 # mshr miss rate for overall accesses 3019system.l2c.overall_mshr_miss_rate::cpu0.data 0.265836 # mshr miss rate for overall accesses 3020system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.443410 # mshr miss rate for overall accesses 3021system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.186815 # mshr miss rate for overall accesses 3022system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.208139 # mshr miss rate for overall accesses 3023system.l2c.overall_mshr_miss_rate::cpu1.inst 0.089341 # mshr miss rate for overall accesses 3024system.l2c.overall_mshr_miss_rate::cpu1.data 0.206143 # mshr miss rate for overall accesses 3025system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.411296 # mshr miss rate for overall accesses 3026system.l2c.overall_mshr_miss_rate::total 0.250858 # mshr miss rate for overall accesses 3027system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 68440.219644 # average ReadReq mshr miss latency 3028system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 69325.509796 # average ReadReq mshr miss latency 3029system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 64762.763882 # average ReadReq mshr miss latency 3030system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 70801.479758 # average ReadReq mshr miss latency 3031system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115369.864860 # average ReadReq mshr miss latency 3032system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68654.805769 # average ReadReq mshr miss latency 3033system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 70250.533120 # average ReadReq mshr miss latency 3034system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64112.168470 # average ReadReq mshr miss latency 3035system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 70176.265391 # average ReadReq mshr miss latency 3036system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117769.320522 # average ReadReq mshr miss latency 3037system.l2c.ReadReq_avg_mshr_miss_latency::total 95099.746219 # average ReadReq mshr miss latency 3038system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 22466.608046 # average WriteInvalidateReq mshr miss latency 3039system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 20243.971628 # average WriteInvalidateReq mshr miss latency 3040system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 21892.569988 # average WriteInvalidateReq mshr miss latency 3041system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10081.122986 # average UpgradeReq mshr miss latency 3042system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10172.643319 # average UpgradeReq mshr miss latency 3043system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10127.734904 # average UpgradeReq mshr miss latency 3044system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10094.514924 # average SCUpgradeReq mshr miss latency 3045system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10170.084593 # average SCUpgradeReq mshr miss latency 3046system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10131.367291 # average SCUpgradeReq mshr miss latency 3047system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66785.676932 # average ReadExReq mshr miss latency 3048system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63285.951301 # average ReadExReq mshr miss latency 3049system.l2c.ReadExReq_avg_mshr_miss_latency::total 65436.965728 # average ReadExReq mshr miss latency 3050system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 68440.219644 # average overall mshr miss latency 3051system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 69325.509796 # average overall mshr miss latency 3052system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64762.763882 # average overall mshr miss latency 3053system.l2c.demand_avg_mshr_miss_latency::cpu0.data 69412.984539 # average overall mshr miss latency 3054system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115369.864860 # average overall mshr miss latency 3055system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68654.805769 # average overall mshr miss latency 3056system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 70250.533120 # average overall mshr miss latency 3057system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64112.168470 # average overall mshr miss latency 3058system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67729.415418 # average overall mshr miss latency 3059system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117769.320522 # average overall mshr miss latency 3060system.l2c.demand_avg_mshr_miss_latency::total 90866.823975 # average overall mshr miss latency 3061system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 68440.219644 # average overall mshr miss latency 3062system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 69325.509796 # average overall mshr miss latency 3063system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64762.763882 # average overall mshr miss latency 3064system.l2c.overall_avg_mshr_miss_latency::cpu0.data 69412.984539 # average overall mshr miss latency 3065system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115369.864860 # average overall mshr miss latency 3066system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68654.805769 # average overall mshr miss latency 3067system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 70250.533120 # average overall mshr miss latency 3068system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64112.168470 # average overall mshr miss latency 3069system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67729.415418 # average overall mshr miss latency 3070system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117769.320522 # average overall mshr miss latency 3071system.l2c.overall_avg_mshr_miss_latency::total 90866.823975 # average overall mshr miss latency 3072system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 3073system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 3074system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 3075system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 3076system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 3077system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 3078system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 3079system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 3080system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 3081system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 3082system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 3083system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 3084system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 3085system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 3086system.membus.trans_dist::ReadReq 841910 # Transaction distribution 3087system.membus.trans_dist::ReadResp 841910 # Transaction distribution 3088system.membus.trans_dist::WriteReq 38471 # Transaction distribution 3089system.membus.trans_dist::WriteResp 38471 # Transaction distribution 3090system.membus.trans_dist::Writeback 1161772 # Transaction distribution 3091system.membus.trans_dist::WriteInvalidateReq 665270 # Transaction distribution 3092system.membus.trans_dist::WriteInvalidateResp 665270 # Transaction distribution 3093system.membus.trans_dist::UpgradeReq 386597 # Transaction distribution 3094system.membus.trans_dist::SCUpgradeReq 321242 # Transaction distribution 3095system.membus.trans_dist::UpgradeResp 114625 # Transaction distribution 3096system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution 3097system.membus.trans_dist::ReadExReq 138806 # Transaction distribution 3098system.membus.trans_dist::ReadExResp 121371 # Transaction distribution 3099system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123076 # Packet count per connected master and slave (bytes) 3100system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 3101system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25442 # Packet count per connected master and slave (bytes) 3102system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4847759 # Packet count per connected master and slave (bytes) 3103system.membus.pkt_count_system.l2c.mem_side::total 4996369 # Packet count per connected master and slave (bytes) 3104system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336372 # Packet count per connected master and slave (bytes) 3105system.membus.pkt_count_system.iocache.mem_side::total 336372 # Packet count per connected master and slave (bytes) 3106system.membus.pkt_count::total 5332741 # Packet count per connected master and slave (bytes) 3107system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156137 # Cumulative packet size per connected master and slave (bytes) 3108system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 3109system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50884 # Cumulative packet size per connected master and slave (bytes) 3110system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 159245812 # Cumulative packet size per connected master and slave (bytes) 3111system.membus.pkt_size_system.l2c.mem_side::total 159453037 # Cumulative packet size per connected master and slave (bytes) 3112system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14112640 # Cumulative packet size per connected master and slave (bytes) 3113system.membus.pkt_size_system.iocache.mem_side::total 14112640 # Cumulative packet size per connected master and slave (bytes) 3114system.membus.pkt_size::total 173565677 # Cumulative packet size per connected master and slave (bytes) 3115system.membus.snoops 613627 # Total snoops (count) 3116system.membus.snoop_fanout::samples 3433927 # Request fanout histogram 3117system.membus.snoop_fanout::mean 1 # Request fanout histogram 3118system.membus.snoop_fanout::stdev 0 # Request fanout histogram 3119system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3120system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3121system.membus.snoop_fanout::1 3433927 100.00% 100.00% # Request fanout histogram 3122system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3123system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3124system.membus.snoop_fanout::min_value 1 # Request fanout histogram 3125system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3126system.membus.snoop_fanout::total 3433927 # Request fanout histogram 3127system.membus.reqLayer0.occupancy 100976496 # Layer occupancy (ticks) 3128system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3129system.membus.reqLayer1.occupancy 55500 # Layer occupancy (ticks) 3130system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3131system.membus.reqLayer2.occupancy 22065500 # Layer occupancy (ticks) 3132system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3133system.membus.reqLayer5.occupancy 18062213474 # Layer occupancy (ticks) 3134system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3135system.membus.respLayer2.occupancy 9212060141 # Layer occupancy (ticks) 3136system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3137system.membus.respLayer3.occupancy 187637046 # Layer occupancy (ticks) 3138system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3139system.realview.ethernet.txBytes 966 # Bytes Transmitted 3140system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3141system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3142system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3143system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3144system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3145system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3146system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3147system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3148system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 3149system.realview.ethernet.totPackets 3 # Total Packets 3150system.realview.ethernet.totBytes 966 # Total Bytes 3151system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 3152system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 3153system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 3154system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3155system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 3156system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3157system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3158system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 3159system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3160system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3161system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 3162system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3163system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3164system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 3165system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3166system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3167system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 3168system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3169system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3170system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 3171system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3172system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3173system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3174system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3175system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3176system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3177system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3178system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3179system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3180system.realview.ethernet.droppedPackets 0 # number of packets dropped 3181system.toL2Bus.trans_dist::ReadReq 4185645 # Transaction distribution 3182system.toL2Bus.trans_dist::ReadResp 4178412 # Transaction distribution 3183system.toL2Bus.trans_dist::WriteReq 38471 # Transaction distribution 3184system.toL2Bus.trans_dist::WriteResp 38471 # Transaction distribution 3185system.toL2Bus.trans_dist::Writeback 2302237 # Transaction distribution 3186system.toL2Bus.trans_dist::WriteInvalidateReq 921111 # Transaction distribution 3187system.toL2Bus.trans_dist::WriteInvalidateResp 814190 # Transaction distribution 3188system.toL2Bus.trans_dist::UpgradeReq 436280 # Transaction distribution 3189system.toL2Bus.trans_dist::SCUpgradeReq 333774 # Transaction distribution 3190system.toL2Bus.trans_dist::UpgradeResp 770054 # Transaction distribution 3191system.toL2Bus.trans_dist::SCUpgradeFailReq 100 # Transaction distribution 3192system.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution 3193system.toL2Bus.trans_dist::ReadExReq 280654 # Transaction distribution 3194system.toL2Bus.trans_dist::ReadExResp 280654 # Transaction distribution 3195system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7279651 # Packet count per connected master and slave (bytes) 3196system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5709072 # Packet count per connected master and slave (bytes) 3197system.toL2Bus.pkt_count::total 12988723 # Packet count per connected master and slave (bytes) 3198system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 243910125 # Cumulative packet size per connected master and slave (bytes) 3199system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 179631296 # Cumulative packet size per connected master and slave (bytes) 3200system.toL2Bus.pkt_size::total 423541421 # Cumulative packet size per connected master and slave (bytes) 3201system.toL2Bus.snoops 1593139 # Total snoops (count) 3202system.toL2Bus.snoop_fanout::samples 8378399 # Request fanout histogram 3203system.toL2Bus.snoop_fanout::mean 1.013829 # Request fanout histogram 3204system.toL2Bus.snoop_fanout::stdev 0.116780 # Request fanout histogram 3205system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3206system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3207system.toL2Bus.snoop_fanout::1 8262536 98.62% 98.62% # Request fanout histogram 3208system.toL2Bus.snoop_fanout::2 115863 1.38% 100.00% # Request fanout histogram 3209system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3210system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 3211system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3212system.toL2Bus.snoop_fanout::total 8378399 # Request fanout histogram 3213system.toL2Bus.reqLayer0.occupancy 16938572035 # Layer occupancy (ticks) 3214system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3215system.toL2Bus.snoopLayer0.occupancy 7678500 # Layer occupancy (ticks) 3216system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3217system.toL2Bus.respLayer0.occupancy 11018810399 # Layer occupancy (ticks) 3218system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3219system.toL2Bus.respLayer1.occupancy 9692180196 # Layer occupancy (ticks) 3220system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3221 3222---------- End Simulation Statistics ---------- 3223