stats.txt revision 10585
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.398431 # Number of seconds simulated 4sim_ticks 47398431268500 # Number of ticks simulated 5final_tick 47398431268500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 671569 # Simulator instruction rate (inst/s) 8host_op_rate 790318 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 37657329129 # Simulator tick rate (ticks/s) 10host_mem_usage 861000 # Number of bytes of host memory used 11host_seconds 1258.68 # Real time elapsed on the host 12sim_insts 845288376 # Number of instructions simulated 13sim_ops 994755388 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 36416 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 41984 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 768052 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 7936536 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 44723840 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 83456 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 97984 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 589368 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 8667104 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 21031552 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 441920 # Number of bytes read from this memory 27system.physmem.bytes_read::total 84418212 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 768052 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 589368 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 1357420 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 65101248 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 34system.physmem.bytes_written::total 65122064 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 569 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 656 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 52408 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 124030 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 698810 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 1304 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 1531 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 9297 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 135438 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 328618 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 6905 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 1359566 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 1017207 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 50system.physmem.num_writes::total 1019810 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 768 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 886 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 16204 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 167443 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 943572 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 1761 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 2067 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 12434 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 182856 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 443718 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 9324 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 1781034 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 16204 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 12434 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 28639 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 1373490 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::total 1373929 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 1373490 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 768 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 886 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 16204 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 167882 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 943572 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 1761 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 2067 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 12434 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 182856 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 443718 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 9324 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 3154963 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 1359566 # Number of read requests accepted 84system.physmem.writeReqs 1139623 # Number of write requests accepted 85system.physmem.readBursts 1359566 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 1139623 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 86962304 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 49920 # Total number of bytes read from write queue 89system.physmem.bytesWritten 72439488 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 84418212 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 72790096 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 780 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 7732 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 85004 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 81504 # Per bank write bursts 96system.physmem.perBankRdBursts::1 94599 # Per bank write bursts 97system.physmem.perBankRdBursts::2 79086 # Per bank write bursts 98system.physmem.perBankRdBursts::3 89082 # Per bank write bursts 99system.physmem.perBankRdBursts::4 90127 # Per bank write bursts 100system.physmem.perBankRdBursts::5 94039 # Per bank write bursts 101system.physmem.perBankRdBursts::6 78740 # Per bank write bursts 102system.physmem.perBankRdBursts::7 79772 # Per bank write bursts 103system.physmem.perBankRdBursts::8 80197 # Per bank write bursts 104system.physmem.perBankRdBursts::9 124149 # Per bank write bursts 105system.physmem.perBankRdBursts::10 71869 # Per bank write bursts 106system.physmem.perBankRdBursts::11 83577 # Per bank write bursts 107system.physmem.perBankRdBursts::12 73174 # Per bank write bursts 108system.physmem.perBankRdBursts::13 83519 # Per bank write bursts 109system.physmem.perBankRdBursts::14 78794 # Per bank write bursts 110system.physmem.perBankRdBursts::15 76558 # Per bank write bursts 111system.physmem.perBankWrBursts::0 70549 # Per bank write bursts 112system.physmem.perBankWrBursts::1 76959 # Per bank write bursts 113system.physmem.perBankWrBursts::2 69527 # Per bank write bursts 114system.physmem.perBankWrBursts::3 76268 # Per bank write bursts 115system.physmem.perBankWrBursts::4 71760 # Per bank write bursts 116system.physmem.perBankWrBursts::5 76111 # Per bank write bursts 117system.physmem.perBankWrBursts::6 67646 # Per bank write bursts 118system.physmem.perBankWrBursts::7 68141 # Per bank write bursts 119system.physmem.perBankWrBursts::8 69345 # Per bank write bursts 120system.physmem.perBankWrBursts::9 72887 # Per bank write bursts 121system.physmem.perBankWrBursts::10 65485 # Per bank write bursts 122system.physmem.perBankWrBursts::11 73987 # Per bank write bursts 123system.physmem.perBankWrBursts::12 65828 # Per bank write bursts 124system.physmem.perBankWrBursts::13 73935 # Per bank write bursts 125system.physmem.perBankWrBursts::14 66021 # Per bank write bursts 126system.physmem.perBankWrBursts::15 67418 # Per bank write bursts 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 128system.physmem.numWrRetry 5 # Number of times write queue was full causing retry 129system.physmem.totGap 47398428076000 # Total gap between requests 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 43195 # Read request sizes (log2) 133system.physmem.readPktSize::3 37 # Read request sizes (log2) 134system.physmem.readPktSize::4 5 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) 136system.physmem.readPktSize::6 1316329 # Read request sizes (log2) 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 2 # Write request sizes (log2) 140system.physmem.writePktSize::3 2601 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) 143system.physmem.writePktSize::6 1137020 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 566894 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 282234 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 134057 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 101972 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 67644 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 58693 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 53670 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 46721 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 35916 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 3762 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 1955 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 1465 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 1125 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 882 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 709 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 471 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 229 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 184 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 107 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 75 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 3 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 3 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 2 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 176system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::15 16911 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 22466 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 30737 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 39170 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 44059 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 50283 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 58139 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 68202 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 72051 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 76579 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 76851 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 78478 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 78341 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 80363 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 74556 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 75992 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 78312 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 75395 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 11828 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 7611 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 4129 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 1848 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 1099 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 916 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 777 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 712 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 642 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 648 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 562 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 544 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 505 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 463 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 418 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 372 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 356 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 314 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 286 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 239 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 192 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 151 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 100 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 77 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 60 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 45 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 28 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 5 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 648906 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 245.646870 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 142.183985 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 295.195613 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 325424 50.15% 50.15% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 135792 20.93% 71.08% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 50411 7.77% 78.84% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 26706 4.12% 82.96% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 22287 3.43% 86.39% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 16108 2.48% 88.88% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 10950 1.69% 90.56% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 13619 2.10% 92.66% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 47609 7.34% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 648906 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 58676 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 23.156827 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 139.787244 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-1023 58673 99.99% 99.99% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::24576-25599 1 0.00% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::total 58676 # Reads before turning the bus around for writes 262system.physmem.wrPerTurnAround::samples 58676 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::mean 19.290119 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::gmean 17.850822 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::stdev 13.308232 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::16-23 54948 93.65% 93.65% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::24-31 970 1.65% 95.30% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::32-39 598 1.02% 96.32% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::40-47 219 0.37% 96.69% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::48-55 626 1.07% 97.76% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::56-63 147 0.25% 98.01% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::64-71 195 0.33% 98.34% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::72-79 132 0.22% 98.57% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::80-87 184 0.31% 98.88% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::88-95 81 0.14% 99.02% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::96-103 205 0.35% 99.37% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::104-111 24 0.04% 99.41% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::112-119 63 0.11% 99.52% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::120-127 38 0.06% 99.58% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::128-135 129 0.22% 99.80% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::136-143 15 0.03% 99.83% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::144-151 27 0.05% 99.87% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::152-159 11 0.02% 99.89% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::160-167 19 0.03% 99.92% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::168-175 8 0.01% 99.94% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::176-183 11 0.02% 99.96% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::184-191 1 0.00% 99.96% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::192-199 2 0.00% 99.96% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::200-207 5 0.01% 99.97% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::208-215 6 0.01% 99.98% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::216-223 3 0.01% 99.98% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::224-231 4 0.01% 99.99% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::232-239 2 0.00% 99.99% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::248-255 1 0.00% 100.00% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::272-279 1 0.00% 100.00% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::total 58676 # Writes before turning the bus around for reads 298system.physmem.totQLat 69966976258 # Total ticks spent queuing 299system.physmem.totMemAccLat 95444213758 # Total ticks spent from burst creation until serviced by the DRAM 300system.physmem.totBusLat 6793930000 # Total ticks spent in databus transfers 301system.physmem.avgQLat 51492.27 # Average queueing delay per DRAM burst 302system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 303system.physmem.avgMemAccLat 70242.27 # Average memory access latency per DRAM burst 304system.physmem.avgRdBW 1.83 # Average DRAM read bandwidth in MiByte/s 305system.physmem.avgWrBW 1.53 # Average achieved write bandwidth in MiByte/s 306system.physmem.avgRdBWSys 1.78 # Average system read bandwidth in MiByte/s 307system.physmem.avgWrBWSys 1.54 # Average system write bandwidth in MiByte/s 308system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 309system.physmem.busUtil 0.03 # Data bus utilization in percentage 310system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 311system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 312system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing 313system.physmem.avgWrQLen 23.44 # Average write queue length when enqueuing 314system.physmem.readRowHits 1114788 # Number of row buffer hits during reads 315system.physmem.writeRowHits 726958 # Number of row buffer hits during writes 316system.physmem.readRowHitRate 82.04 # Row buffer hit rate for reads 317system.physmem.writeRowHitRate 64.23 # Row buffer hit rate for writes 318system.physmem.avgGap 18965523.65 # Average gap between requests 319system.physmem.pageHitRate 73.95 # Row buffer hit rate, read and write combined 320system.physmem.memoryStateTime::IDLE 45538400789750 # Time in different power states 321system.physmem.memoryStateTime::REF 1582737780000 # Time in different power states 322system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 323system.physmem.memoryStateTime::ACT 277292625250 # Time in different power states 324system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 325system.physmem.actEnergy::0 2564850960 # Energy for activate commands per rank (pJ) 326system.physmem.actEnergy::1 2340878400 # Energy for activate commands per rank (pJ) 327system.physmem.preEnergy::0 1399472250 # Energy for precharge commands per rank (pJ) 328system.physmem.preEnergy::1 1277265000 # Energy for precharge commands per rank (pJ) 329system.physmem.readEnergy::0 5358202200 # Energy for read commands per rank (pJ) 330system.physmem.readEnergy::1 5240320800 # Energy for read commands per rank (pJ) 331system.physmem.writeEnergy::0 3738707280 # Energy for write commands per rank (pJ) 332system.physmem.writeEnergy::1 3595790880 # Energy for write commands per rank (pJ) 333system.physmem.refreshEnergy::0 3095835097680 # Energy for refresh commands per rank (pJ) 334system.physmem.refreshEnergy::1 3095835097680 # Energy for refresh commands per rank (pJ) 335system.physmem.actBackEnergy::0 1171174509540 # Energy for active background per rank (pJ) 336system.physmem.actBackEnergy::1 1161726671475 # Energy for active background per rank (pJ) 337system.physmem.preBackEnergy::0 27411712647750 # Energy for precharge background per rank (pJ) 338system.physmem.preBackEnergy::1 27420000225000 # Energy for precharge background per rank (pJ) 339system.physmem.totalEnergy::0 31691783487660 # Total energy per rank (pJ) 340system.physmem.totalEnergy::1 31690016249235 # Total energy per rank (pJ) 341system.physmem.averagePower::0 668.625157 # Core power per rank (mW) 342system.physmem.averagePower::1 668.587872 # Core power per rank (mW) 343system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 344system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 345system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 346system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 347system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 348system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 349system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 350system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 351system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 352system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 353system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 354system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 355system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 356system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 357system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 358system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 359system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 360system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 361system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 362system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 363system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 364system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 365system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 366system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 367system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 368system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 369system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 370system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 371system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 372system.cf0.dma_write_full_pages 1670 # Number of full page size DMA writes. 373system.cf0.dma_write_bytes 6842880 # Number of bytes transfered via DMA writes. 374system.cf0.dma_write_txs 1673 # Number of DMA write transactions. 375system.cpu_clk_domain.clock 500 # Clock period in ticks 376system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 377system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 378system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 379system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 380system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 381system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 382system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 383system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 384system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 385system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 386system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 387system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 388system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 389system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 390system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 391system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 392system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 393system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 394system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 395system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 396system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 397system.cpu0.dtb.inst_hits 0 # ITB inst hits 398system.cpu0.dtb.inst_misses 0 # ITB inst misses 399system.cpu0.dtb.read_hits 74706058 # DTB read hits 400system.cpu0.dtb.read_misses 64792 # DTB read misses 401system.cpu0.dtb.write_hits 67192400 # DTB write hits 402system.cpu0.dtb.write_misses 21129 # DTB write misses 403system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 404system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 405system.cpu0.dtb.flush_tlb_mva_asid 37660 # Number of times TLB was flushed by MVA & ASID 406system.cpu0.dtb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID 407system.cpu0.dtb.flush_entries 33482 # Number of entries that have been flushed from TLB 408system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 409system.cpu0.dtb.prefetch_faults 3817 # Number of TLB faults due to prefetch 410system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 411system.cpu0.dtb.perms_faults 8375 # Number of TLB faults due to permissions restrictions 412system.cpu0.dtb.read_accesses 74770850 # DTB read accesses 413system.cpu0.dtb.write_accesses 67213529 # DTB write accesses 414system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 415system.cpu0.dtb.hits 141898458 # DTB hits 416system.cpu0.dtb.misses 85921 # DTB misses 417system.cpu0.dtb.accesses 141984379 # DTB accesses 418system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 419system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 420system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 421system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 422system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 423system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 424system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 425system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 426system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 427system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 428system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 429system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 430system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 431system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 432system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 433system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 434system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 435system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 436system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 437system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 438system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 439system.cpu0.itb.inst_hits 397874920 # ITB inst hits 440system.cpu0.itb.inst_misses 49120 # ITB inst misses 441system.cpu0.itb.read_hits 0 # DTB read hits 442system.cpu0.itb.read_misses 0 # DTB read misses 443system.cpu0.itb.write_hits 0 # DTB write hits 444system.cpu0.itb.write_misses 0 # DTB write misses 445system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 446system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 447system.cpu0.itb.flush_tlb_mva_asid 37660 # Number of times TLB was flushed by MVA & ASID 448system.cpu0.itb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID 449system.cpu0.itb.flush_entries 23760 # Number of entries that have been flushed from TLB 450system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 451system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 452system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 453system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 454system.cpu0.itb.read_accesses 0 # DTB read accesses 455system.cpu0.itb.write_accesses 0 # DTB write accesses 456system.cpu0.itb.inst_accesses 397924040 # ITB inst accesses 457system.cpu0.itb.hits 397874920 # DTB hits 458system.cpu0.itb.misses 49120 # DTB misses 459system.cpu0.itb.accesses 397924040 # DTB accesses 460system.cpu0.numCycles 94796862537 # number of cpu cycles simulated 461system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 462system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 463system.cpu0.committedInsts 397643174 # Number of instructions committed 464system.cpu0.committedOps 466635553 # Number of ops (including micro ops) committed 465system.cpu0.num_int_alu_accesses 429030148 # Number of integer alu accesses 466system.cpu0.num_fp_alu_accesses 322477 # Number of float alu accesses 467system.cpu0.num_func_calls 23930039 # number of times a function call or return occured 468system.cpu0.num_conditional_control_insts 59901605 # number of instructions that are conditional controls 469system.cpu0.num_int_insts 429030148 # number of integer instructions 470system.cpu0.num_fp_insts 322477 # number of float instructions 471system.cpu0.num_int_register_reads 621630892 # number of times the integer registers were read 472system.cpu0.num_int_register_writes 340702516 # number of times the integer registers were written 473system.cpu0.num_fp_register_reads 547437 # number of times the floating registers were read 474system.cpu0.num_fp_register_writes 211832 # number of times the floating registers were written 475system.cpu0.num_cc_register_reads 102593685 # number of times the CC registers were read 476system.cpu0.num_cc_register_writes 102325899 # number of times the CC registers were written 477system.cpu0.num_mem_refs 141893093 # number of memory refs 478system.cpu0.num_load_insts 74704433 # Number of load instructions 479system.cpu0.num_store_insts 67188660 # Number of store instructions 480system.cpu0.num_idle_cycles 93886429062.298019 # Number of idle cycles 481system.cpu0.num_busy_cycles 910433474.701981 # Number of busy cycles 482system.cpu0.not_idle_fraction 0.009604 # Percentage of non-idle cycles 483system.cpu0.idle_fraction 0.990396 # Percentage of idle cycles 484system.cpu0.Branches 88352328 # Number of branches fetched 485system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 486system.cpu0.op_class::IntAlu 323823287 69.35% 69.35% # Class of executed instruction 487system.cpu0.op_class::IntMult 1114929 0.24% 69.59% # Class of executed instruction 488system.cpu0.op_class::IntDiv 56737 0.01% 69.61% # Class of executed instruction 489system.cpu0.op_class::FloatAdd 0 0.00% 69.61% # Class of executed instruction 490system.cpu0.op_class::FloatCmp 0 0.00% 69.61% # Class of executed instruction 491system.cpu0.op_class::FloatCvt 0 0.00% 69.61% # Class of executed instruction 492system.cpu0.op_class::FloatMult 0 0.00% 69.61% # Class of executed instruction 493system.cpu0.op_class::FloatDiv 0 0.00% 69.61% # Class of executed instruction 494system.cpu0.op_class::FloatSqrt 0 0.00% 69.61% # Class of executed instruction 495system.cpu0.op_class::SimdAdd 0 0.00% 69.61% # Class of executed instruction 496system.cpu0.op_class::SimdAddAcc 0 0.00% 69.61% # Class of executed instruction 497system.cpu0.op_class::SimdAlu 0 0.00% 69.61% # Class of executed instruction 498system.cpu0.op_class::SimdCmp 0 0.00% 69.61% # Class of executed instruction 499system.cpu0.op_class::SimdCvt 0 0.00% 69.61% # Class of executed instruction 500system.cpu0.op_class::SimdMisc 0 0.00% 69.61% # Class of executed instruction 501system.cpu0.op_class::SimdMult 0 0.00% 69.61% # Class of executed instruction 502system.cpu0.op_class::SimdMultAcc 0 0.00% 69.61% # Class of executed instruction 503system.cpu0.op_class::SimdShift 0 0.00% 69.61% # Class of executed instruction 504system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.61% # Class of executed instruction 505system.cpu0.op_class::SimdSqrt 0 0.00% 69.61% # Class of executed instruction 506system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.61% # Class of executed instruction 507system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.61% # Class of executed instruction 508system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.61% # Class of executed instruction 509system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.61% # Class of executed instruction 510system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.61% # Class of executed instruction 511system.cpu0.op_class::SimdFloatMisc 22377 0.00% 69.61% # Class of executed instruction 512system.cpu0.op_class::SimdFloatMult 0 0.00% 69.61% # Class of executed instruction 513system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.61% # Class of executed instruction 514system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.61% # Class of executed instruction 515system.cpu0.op_class::MemRead 74704433 16.00% 85.61% # Class of executed instruction 516system.cpu0.op_class::MemWrite 67188660 14.39% 100.00% # Class of executed instruction 517system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 518system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 519system.cpu0.op_class::total 466910423 # Class of executed instruction 520system.cpu0.kern.inst.arm 0 # number of arm instructions executed 521system.cpu0.kern.inst.quiesce 5105 # number of quiesce instructions executed 522system.cpu0.dcache.tags.replacements 4859280 # number of replacements 523system.cpu0.dcache.tags.tagsinuse 480.680410 # Cycle average of tags in use 524system.cpu0.dcache.tags.total_refs 136835586 # Total number of references to valid blocks. 525system.cpu0.dcache.tags.sampled_refs 4859789 # Sample count of references to valid blocks. 526system.cpu0.dcache.tags.avg_refs 28.156693 # Average number of references to valid blocks. 527system.cpu0.dcache.tags.warmup_cycle 3644536500 # Cycle when the warmup percentage was hit. 528system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.680410 # Average occupied blocks per requestor 529system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938829 # Average percentage of cache occupancy 530system.cpu0.dcache.tags.occ_percent::total 0.938829 # Average percentage of cache occupancy 531system.cpu0.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id 532system.cpu0.dcache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id 533system.cpu0.dcache.tags.age_task_id_blocks_1024::1 406 # Occupied blocks per task id 534system.cpu0.dcache.tags.age_task_id_blocks_1024::2 9 # Occupied blocks per task id 535system.cpu0.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id 536system.cpu0.dcache.tags.tag_accesses 288671468 # Number of tag accesses 537system.cpu0.dcache.tags.data_accesses 288671468 # Number of data accesses 538system.cpu0.dcache.ReadReq_hits::cpu0.data 69599952 # number of ReadReq hits 539system.cpu0.dcache.ReadReq_hits::total 69599952 # number of ReadReq hits 540system.cpu0.dcache.WriteReq_hits::cpu0.data 63413457 # number of WriteReq hits 541system.cpu0.dcache.WriteReq_hits::total 63413457 # number of WriteReq hits 542system.cpu0.dcache.SoftPFReq_hits::cpu0.data 173858 # number of SoftPFReq hits 543system.cpu0.dcache.SoftPFReq_hits::total 173858 # number of SoftPFReq hits 544system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 133135 # number of WriteInvalidateReq hits 545system.cpu0.dcache.WriteInvalidateReq_hits::total 133135 # number of WriteInvalidateReq hits 546system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1596886 # number of LoadLockedReq hits 547system.cpu0.dcache.LoadLockedReq_hits::total 1596886 # number of LoadLockedReq hits 548system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1561841 # number of StoreCondReq hits 549system.cpu0.dcache.StoreCondReq_hits::total 1561841 # number of StoreCondReq hits 550system.cpu0.dcache.demand_hits::cpu0.data 133013409 # number of demand (read+write) hits 551system.cpu0.dcache.demand_hits::total 133013409 # number of demand (read+write) hits 552system.cpu0.dcache.overall_hits::cpu0.data 133187267 # number of overall hits 553system.cpu0.dcache.overall_hits::total 133187267 # number of overall hits 554system.cpu0.dcache.ReadReq_misses::cpu0.data 2622769 # number of ReadReq misses 555system.cpu0.dcache.ReadReq_misses::total 2622769 # number of ReadReq misses 556system.cpu0.dcache.WriteReq_misses::cpu0.data 1185607 # number of WriteReq misses 557system.cpu0.dcache.WriteReq_misses::total 1185607 # number of WriteReq misses 558system.cpu0.dcache.SoftPFReq_misses::cpu0.data 553155 # number of SoftPFReq misses 559system.cpu0.dcache.SoftPFReq_misses::total 553155 # number of SoftPFReq misses 560system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 697992 # number of WriteInvalidateReq misses 561system.cpu0.dcache.WriteInvalidateReq_misses::total 697992 # number of WriteInvalidateReq misses 562system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 145021 # number of LoadLockedReq misses 563system.cpu0.dcache.LoadLockedReq_misses::total 145021 # number of LoadLockedReq misses 564system.cpu0.dcache.StoreCondReq_misses::cpu0.data 178721 # number of StoreCondReq misses 565system.cpu0.dcache.StoreCondReq_misses::total 178721 # number of StoreCondReq misses 566system.cpu0.dcache.demand_misses::cpu0.data 3808376 # number of demand (read+write) misses 567system.cpu0.dcache.demand_misses::total 3808376 # number of demand (read+write) misses 568system.cpu0.dcache.overall_misses::cpu0.data 4361531 # number of overall misses 569system.cpu0.dcache.overall_misses::total 4361531 # number of overall misses 570system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 36725560788 # number of ReadReq miss cycles 571system.cpu0.dcache.ReadReq_miss_latency::total 36725560788 # number of ReadReq miss cycles 572system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 18496940456 # number of WriteReq miss cycles 573system.cpu0.dcache.WriteReq_miss_latency::total 18496940456 # number of WriteReq miss cycles 574system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 11951080104 # number of WriteInvalidateReq miss cycles 575system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 11951080104 # number of WriteInvalidateReq miss cycles 576system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2007745317 # number of LoadLockedReq miss cycles 577system.cpu0.dcache.LoadLockedReq_miss_latency::total 2007745317 # number of LoadLockedReq miss cycles 578system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3807661334 # number of StoreCondReq miss cycles 579system.cpu0.dcache.StoreCondReq_miss_latency::total 3807661334 # number of StoreCondReq miss cycles 580system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 927000 # number of StoreCondFailReq miss cycles 581system.cpu0.dcache.StoreCondFailReq_miss_latency::total 927000 # number of StoreCondFailReq miss cycles 582system.cpu0.dcache.demand_miss_latency::cpu0.data 55222501244 # number of demand (read+write) miss cycles 583system.cpu0.dcache.demand_miss_latency::total 55222501244 # number of demand (read+write) miss cycles 584system.cpu0.dcache.overall_miss_latency::cpu0.data 55222501244 # number of overall miss cycles 585system.cpu0.dcache.overall_miss_latency::total 55222501244 # number of overall miss cycles 586system.cpu0.dcache.ReadReq_accesses::cpu0.data 72222721 # number of ReadReq accesses(hits+misses) 587system.cpu0.dcache.ReadReq_accesses::total 72222721 # number of ReadReq accesses(hits+misses) 588system.cpu0.dcache.WriteReq_accesses::cpu0.data 64599064 # number of WriteReq accesses(hits+misses) 589system.cpu0.dcache.WriteReq_accesses::total 64599064 # number of WriteReq accesses(hits+misses) 590system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 727013 # number of SoftPFReq accesses(hits+misses) 591system.cpu0.dcache.SoftPFReq_accesses::total 727013 # number of SoftPFReq accesses(hits+misses) 592system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 831127 # number of WriteInvalidateReq accesses(hits+misses) 593system.cpu0.dcache.WriteInvalidateReq_accesses::total 831127 # number of WriteInvalidateReq accesses(hits+misses) 594system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1741907 # number of LoadLockedReq accesses(hits+misses) 595system.cpu0.dcache.LoadLockedReq_accesses::total 1741907 # number of LoadLockedReq accesses(hits+misses) 596system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1740562 # number of StoreCondReq accesses(hits+misses) 597system.cpu0.dcache.StoreCondReq_accesses::total 1740562 # number of StoreCondReq accesses(hits+misses) 598system.cpu0.dcache.demand_accesses::cpu0.data 136821785 # number of demand (read+write) accesses 599system.cpu0.dcache.demand_accesses::total 136821785 # number of demand (read+write) accesses 600system.cpu0.dcache.overall_accesses::cpu0.data 137548798 # number of overall (read+write) accesses 601system.cpu0.dcache.overall_accesses::total 137548798 # number of overall (read+write) accesses 602system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036315 # miss rate for ReadReq accesses 603system.cpu0.dcache.ReadReq_miss_rate::total 0.036315 # miss rate for ReadReq accesses 604system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018353 # miss rate for WriteReq accesses 605system.cpu0.dcache.WriteReq_miss_rate::total 0.018353 # miss rate for WriteReq accesses 606system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.760860 # miss rate for SoftPFReq accesses 607system.cpu0.dcache.SoftPFReq_miss_rate::total 0.760860 # miss rate for SoftPFReq accesses 608system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.839814 # miss rate for WriteInvalidateReq accesses 609system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.839814 # miss rate for WriteInvalidateReq accesses 610system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.083254 # miss rate for LoadLockedReq accesses 611system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.083254 # miss rate for LoadLockedReq accesses 612system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.102680 # miss rate for StoreCondReq accesses 613system.cpu0.dcache.StoreCondReq_miss_rate::total 0.102680 # miss rate for StoreCondReq accesses 614system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027835 # miss rate for demand accesses 615system.cpu0.dcache.demand_miss_rate::total 0.027835 # miss rate for demand accesses 616system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031709 # miss rate for overall accesses 617system.cpu0.dcache.overall_miss_rate::total 0.031709 # miss rate for overall accesses 618system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14002.590693 # average ReadReq miss latency 619system.cpu0.dcache.ReadReq_avg_miss_latency::total 14002.590693 # average ReadReq miss latency 620system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15601.240931 # average WriteReq miss latency 621system.cpu0.dcache.WriteReq_avg_miss_latency::total 15601.240931 # average WriteReq miss latency 622system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 17122.087508 # average WriteInvalidateReq miss latency 623system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 17122.087508 # average WriteInvalidateReq miss latency 624system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13844.514360 # average LoadLockedReq miss latency 625system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13844.514360 # average LoadLockedReq miss latency 626system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21305.058354 # average StoreCondReq miss latency 627system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21305.058354 # average StoreCondReq miss latency 628system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 629system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 630system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14500.275510 # average overall miss latency 631system.cpu0.dcache.demand_avg_miss_latency::total 14500.275510 # average overall miss latency 632system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12661.265332 # average overall miss latency 633system.cpu0.dcache.overall_avg_miss_latency::total 12661.265332 # average overall miss latency 634system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 635system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 636system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 637system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 638system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 639system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 640system.cpu0.dcache.fast_writes 0 # number of fast writes performed 641system.cpu0.dcache.cache_copies 0 # number of cache copies performed 642system.cpu0.dcache.writebacks::writebacks 3276433 # number of writebacks 643system.cpu0.dcache.writebacks::total 3276433 # number of writebacks 644system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 20828 # number of ReadReq MSHR hits 645system.cpu0.dcache.ReadReq_mshr_hits::total 20828 # number of ReadReq MSHR hits 646system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21424 # number of WriteReq MSHR hits 647system.cpu0.dcache.WriteReq_mshr_hits::total 21424 # number of WriteReq MSHR hits 648system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 36174 # number of LoadLockedReq MSHR hits 649system.cpu0.dcache.LoadLockedReq_mshr_hits::total 36174 # number of LoadLockedReq MSHR hits 650system.cpu0.dcache.demand_mshr_hits::cpu0.data 42252 # number of demand (read+write) MSHR hits 651system.cpu0.dcache.demand_mshr_hits::total 42252 # number of demand (read+write) MSHR hits 652system.cpu0.dcache.overall_mshr_hits::cpu0.data 42252 # number of overall MSHR hits 653system.cpu0.dcache.overall_mshr_hits::total 42252 # number of overall MSHR hits 654system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2601941 # number of ReadReq MSHR misses 655system.cpu0.dcache.ReadReq_mshr_misses::total 2601941 # number of ReadReq MSHR misses 656system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1164183 # number of WriteReq MSHR misses 657system.cpu0.dcache.WriteReq_mshr_misses::total 1164183 # number of WriteReq MSHR misses 658system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 551435 # number of SoftPFReq MSHR misses 659system.cpu0.dcache.SoftPFReq_mshr_misses::total 551435 # number of SoftPFReq MSHR misses 660system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 697992 # number of WriteInvalidateReq MSHR misses 661system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 697992 # number of WriteInvalidateReq MSHR misses 662system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 108847 # number of LoadLockedReq MSHR misses 663system.cpu0.dcache.LoadLockedReq_mshr_misses::total 108847 # number of LoadLockedReq MSHR misses 664system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 178721 # number of StoreCondReq MSHR misses 665system.cpu0.dcache.StoreCondReq_mshr_misses::total 178721 # number of StoreCondReq MSHR misses 666system.cpu0.dcache.demand_mshr_misses::cpu0.data 3766124 # number of demand (read+write) MSHR misses 667system.cpu0.dcache.demand_mshr_misses::total 3766124 # number of demand (read+write) MSHR misses 668system.cpu0.dcache.overall_mshr_misses::cpu0.data 4317559 # number of overall MSHR misses 669system.cpu0.dcache.overall_mshr_misses::total 4317559 # number of overall MSHR misses 670system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 30561578872 # number of ReadReq MSHR miss cycles 671system.cpu0.dcache.ReadReq_mshr_miss_latency::total 30561578872 # number of ReadReq MSHR miss cycles 672system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 15647124797 # number of WriteReq MSHR miss cycles 673system.cpu0.dcache.WriteReq_mshr_miss_latency::total 15647124797 # number of WriteReq MSHR miss cycles 674system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 11524265112 # number of SoftPFReq MSHR miss cycles 675system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 11524265112 # number of SoftPFReq MSHR miss cycles 676system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 10542114896 # number of WriteInvalidateReq MSHR miss cycles 677system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 10542114896 # number of WriteInvalidateReq MSHR miss cycles 678system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1234908207 # number of LoadLockedReq MSHR miss cycles 679system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1234908207 # number of LoadLockedReq MSHR miss cycles 680system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3440508666 # number of StoreCondReq MSHR miss cycles 681system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3440508666 # number of StoreCondReq MSHR miss cycles 682system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 879000 # number of StoreCondFailReq MSHR miss cycles 683system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 879000 # number of StoreCondFailReq MSHR miss cycles 684system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 46208703669 # number of demand (read+write) MSHR miss cycles 685system.cpu0.dcache.demand_mshr_miss_latency::total 46208703669 # number of demand (read+write) MSHR miss cycles 686system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 57732968781 # number of overall MSHR miss cycles 687system.cpu0.dcache.overall_mshr_miss_latency::total 57732968781 # number of overall MSHR miss cycles 688system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2384094697 # number of ReadReq MSHR uncacheable cycles 689system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2384094697 # number of ReadReq MSHR uncacheable cycles 690system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2386757695 # number of WriteReq MSHR uncacheable cycles 691system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2386757695 # number of WriteReq MSHR uncacheable cycles 692system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4770852392 # number of overall MSHR uncacheable cycles 693system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4770852392 # number of overall MSHR uncacheable cycles 694system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036027 # mshr miss rate for ReadReq accesses 695system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036027 # mshr miss rate for ReadReq accesses 696system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018022 # mshr miss rate for WriteReq accesses 697system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018022 # mshr miss rate for WriteReq accesses 698system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.758494 # mshr miss rate for SoftPFReq accesses 699system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.758494 # mshr miss rate for SoftPFReq accesses 700system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.839814 # mshr miss rate for WriteInvalidateReq accesses 701system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.839814 # mshr miss rate for WriteInvalidateReq accesses 702system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062487 # mshr miss rate for LoadLockedReq accesses 703system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062487 # mshr miss rate for LoadLockedReq accesses 704system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.102680 # mshr miss rate for StoreCondReq accesses 705system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.102680 # mshr miss rate for StoreCondReq accesses 706system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027526 # mshr miss rate for demand accesses 707system.cpu0.dcache.demand_mshr_miss_rate::total 0.027526 # mshr miss rate for demand accesses 708system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031389 # mshr miss rate for overall accesses 709system.cpu0.dcache.overall_mshr_miss_rate::total 0.031389 # mshr miss rate for overall accesses 710system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11745.684807 # average ReadReq mshr miss latency 711system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11745.684807 # average ReadReq mshr miss latency 712system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 13440.434019 # average WriteReq mshr miss latency 713system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13440.434019 # average WriteReq mshr miss latency 714system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20898.682731 # average SoftPFReq mshr miss latency 715system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20898.682731 # average SoftPFReq mshr miss latency 716system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 15103.489576 # average WriteInvalidateReq mshr miss latency 717system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 15103.489576 # average WriteInvalidateReq mshr miss latency 718system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11345.358228 # average LoadLockedReq mshr miss latency 719system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11345.358228 # average LoadLockedReq mshr miss latency 720system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19250.724123 # average StoreCondReq mshr miss latency 721system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19250.724123 # average StoreCondReq mshr miss latency 722system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 723system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 724system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12269.565120 # average overall mshr miss latency 725system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12269.565120 # average overall mshr miss latency 726system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13371.668756 # average overall mshr miss latency 727system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13371.668756 # average overall mshr miss latency 728system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 729system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 730system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 731system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 732system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 733system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 734system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 735system.cpu0.icache.tags.replacements 4269396 # number of replacements 736system.cpu0.icache.tags.tagsinuse 511.932974 # Cycle average of tags in use 737system.cpu0.icache.tags.total_refs 393605012 # Total number of references to valid blocks. 738system.cpu0.icache.tags.sampled_refs 4269908 # Sample count of references to valid blocks. 739system.cpu0.icache.tags.avg_refs 92.181146 # Average number of references to valid blocks. 740system.cpu0.icache.tags.warmup_cycle 18918806750 # Cycle when the warmup percentage was hit. 741system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.932974 # Average occupied blocks per requestor 742system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999869 # Average percentage of cache occupancy 743system.cpu0.icache.tags.occ_percent::total 0.999869 # Average percentage of cache occupancy 744system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 745system.cpu0.icache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id 746system.cpu0.icache.tags.age_task_id_blocks_1024::1 269 # Occupied blocks per task id 747system.cpu0.icache.tags.age_task_id_blocks_1024::2 222 # Occupied blocks per task id 748system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id 749system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 750system.cpu0.icache.tags.tag_accesses 800019748 # Number of tag accesses 751system.cpu0.icache.tags.data_accesses 800019748 # Number of data accesses 752system.cpu0.icache.ReadReq_hits::cpu0.inst 393605012 # number of ReadReq hits 753system.cpu0.icache.ReadReq_hits::total 393605012 # number of ReadReq hits 754system.cpu0.icache.demand_hits::cpu0.inst 393605012 # number of demand (read+write) hits 755system.cpu0.icache.demand_hits::total 393605012 # number of demand (read+write) hits 756system.cpu0.icache.overall_hits::cpu0.inst 393605012 # number of overall hits 757system.cpu0.icache.overall_hits::total 393605012 # number of overall hits 758system.cpu0.icache.ReadReq_misses::cpu0.inst 4269908 # number of ReadReq misses 759system.cpu0.icache.ReadReq_misses::total 4269908 # number of ReadReq misses 760system.cpu0.icache.demand_misses::cpu0.inst 4269908 # number of demand (read+write) misses 761system.cpu0.icache.demand_misses::total 4269908 # number of demand (read+write) misses 762system.cpu0.icache.overall_misses::cpu0.inst 4269908 # number of overall misses 763system.cpu0.icache.overall_misses::total 4269908 # number of overall misses 764system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 37643365597 # number of ReadReq miss cycles 765system.cpu0.icache.ReadReq_miss_latency::total 37643365597 # number of ReadReq miss cycles 766system.cpu0.icache.demand_miss_latency::cpu0.inst 37643365597 # number of demand (read+write) miss cycles 767system.cpu0.icache.demand_miss_latency::total 37643365597 # number of demand (read+write) miss cycles 768system.cpu0.icache.overall_miss_latency::cpu0.inst 37643365597 # number of overall miss cycles 769system.cpu0.icache.overall_miss_latency::total 37643365597 # number of overall miss cycles 770system.cpu0.icache.ReadReq_accesses::cpu0.inst 397874920 # number of ReadReq accesses(hits+misses) 771system.cpu0.icache.ReadReq_accesses::total 397874920 # number of ReadReq accesses(hits+misses) 772system.cpu0.icache.demand_accesses::cpu0.inst 397874920 # number of demand (read+write) accesses 773system.cpu0.icache.demand_accesses::total 397874920 # number of demand (read+write) accesses 774system.cpu0.icache.overall_accesses::cpu0.inst 397874920 # number of overall (read+write) accesses 775system.cpu0.icache.overall_accesses::total 397874920 # number of overall (read+write) accesses 776system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010732 # miss rate for ReadReq accesses 777system.cpu0.icache.ReadReq_miss_rate::total 0.010732 # miss rate for ReadReq accesses 778system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010732 # miss rate for demand accesses 779system.cpu0.icache.demand_miss_rate::total 0.010732 # miss rate for demand accesses 780system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010732 # miss rate for overall accesses 781system.cpu0.icache.overall_miss_rate::total 0.010732 # miss rate for overall accesses 782system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8815.966432 # average ReadReq miss latency 783system.cpu0.icache.ReadReq_avg_miss_latency::total 8815.966432 # average ReadReq miss latency 784system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8815.966432 # average overall miss latency 785system.cpu0.icache.demand_avg_miss_latency::total 8815.966432 # average overall miss latency 786system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8815.966432 # average overall miss latency 787system.cpu0.icache.overall_avg_miss_latency::total 8815.966432 # average overall miss latency 788system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 789system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 790system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 791system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 792system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 793system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 794system.cpu0.icache.fast_writes 0 # number of fast writes performed 795system.cpu0.icache.cache_copies 0 # number of cache copies performed 796system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4269908 # number of ReadReq MSHR misses 797system.cpu0.icache.ReadReq_mshr_misses::total 4269908 # number of ReadReq MSHR misses 798system.cpu0.icache.demand_mshr_misses::cpu0.inst 4269908 # number of demand (read+write) MSHR misses 799system.cpu0.icache.demand_mshr_misses::total 4269908 # number of demand (read+write) MSHR misses 800system.cpu0.icache.overall_mshr_misses::cpu0.inst 4269908 # number of overall MSHR misses 801system.cpu0.icache.overall_mshr_misses::total 4269908 # number of overall MSHR misses 802system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31235618425 # number of ReadReq MSHR miss cycles 803system.cpu0.icache.ReadReq_mshr_miss_latency::total 31235618425 # number of ReadReq MSHR miss cycles 804system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31235618425 # number of demand (read+write) MSHR miss cycles 805system.cpu0.icache.demand_mshr_miss_latency::total 31235618425 # number of demand (read+write) MSHR miss cycles 806system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31235618425 # number of overall MSHR miss cycles 807system.cpu0.icache.overall_mshr_miss_latency::total 31235618425 # number of overall MSHR miss cycles 808system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3405609750 # number of ReadReq MSHR uncacheable cycles 809system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3405609750 # number of ReadReq MSHR uncacheable cycles 810system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3405609750 # number of overall MSHR uncacheable cycles 811system.cpu0.icache.overall_mshr_uncacheable_latency::total 3405609750 # number of overall MSHR uncacheable cycles 812system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010732 # mshr miss rate for ReadReq accesses 813system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010732 # mshr miss rate for ReadReq accesses 814system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010732 # mshr miss rate for demand accesses 815system.cpu0.icache.demand_mshr_miss_rate::total 0.010732 # mshr miss rate for demand accesses 816system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010732 # mshr miss rate for overall accesses 817system.cpu0.icache.overall_mshr_miss_rate::total 0.010732 # mshr miss rate for overall accesses 818system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7315.290733 # average ReadReq mshr miss latency 819system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7315.290733 # average ReadReq mshr miss latency 820system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7315.290733 # average overall mshr miss latency 821system.cpu0.icache.demand_avg_mshr_miss_latency::total 7315.290733 # average overall mshr miss latency 822system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7315.290733 # average overall mshr miss latency 823system.cpu0.icache.overall_avg_mshr_miss_latency::total 7315.290733 # average overall mshr miss latency 824system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 825system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 826system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 827system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 828system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 829system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 45505774 # number of hwpf identified 830system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 2657797 # number of hwpf that were already in mshr 831system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 39900232 # number of hwpf that were already in the cache 832system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 8744 # number of hwpf that were already in the prefetch queue 833system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 834system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 580 # number of hwpf removed because MSHR allocated 835system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 2938421 # number of hwpf issued 836system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 3808538 # number of hwpf spanning a virtual page 837system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 838system.cpu0.l2cache.tags.replacements 3291824 # number of replacements 839system.cpu0.l2cache.tags.tagsinuse 16191.272385 # Cycle average of tags in use 840system.cpu0.l2cache.tags.total_refs 9909292 # Total number of references to valid blocks. 841system.cpu0.l2cache.tags.sampled_refs 3307923 # Sample count of references to valid blocks. 842system.cpu0.l2cache.tags.avg_refs 2.995624 # Average number of references to valid blocks. 843system.cpu0.l2cache.tags.warmup_cycle 16044231500 # Cycle when the warmup percentage was hit. 844system.cpu0.l2cache.tags.occ_blocks::writebacks 5217.724609 # Average occupied blocks per requestor 845system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 49.949148 # Average occupied blocks per requestor 846system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 58.574202 # Average occupied blocks per requestor 847system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 727.292976 # Average occupied blocks per requestor 848system.cpu0.l2cache.tags.occ_blocks::cpu0.data 2667.900561 # Average occupied blocks per requestor 849system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 7469.830889 # Average occupied blocks per requestor 850system.cpu0.l2cache.tags.occ_percent::writebacks 0.318465 # Average percentage of cache occupancy 851system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003049 # Average percentage of cache occupancy 852system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003575 # Average percentage of cache occupancy 853system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.044390 # Average percentage of cache occupancy 854system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.162836 # Average percentage of cache occupancy 855system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.455922 # Average percentage of cache occupancy 856system.cpu0.l2cache.tags.occ_percent::total 0.988237 # Average percentage of cache occupancy 857system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8632 # Occupied blocks per task id 858system.cpu0.l2cache.tags.occ_task_id_blocks::1023 100 # Occupied blocks per task id 859system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7367 # Occupied blocks per task id 860system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 22 # Occupied blocks per task id 861system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 210 # Occupied blocks per task id 862system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1111 # Occupied blocks per task id 863system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 7012 # Occupied blocks per task id 864system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 277 # Occupied blocks per task id 865system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 6 # Occupied blocks per task id 866system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 10 # Occupied blocks per task id 867system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id 868system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 77 # Occupied blocks per task id 869system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id 870system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1042 # Occupied blocks per task id 871system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1532 # Occupied blocks per task id 872system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4604 # Occupied blocks per task id 873system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 127 # Occupied blocks per task id 874system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.526855 # Percentage of cache occupancy per task id 875system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006104 # Percentage of cache occupancy per task id 876system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.449646 # Percentage of cache occupancy per task id 877system.cpu0.l2cache.tags.tag_accesses 215960486 # Number of tag accesses 878system.cpu0.l2cache.tags.data_accesses 215960486 # Number of data accesses 879system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 166834 # number of ReadReq hits 880system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 106498 # number of ReadReq hits 881system.cpu0.l2cache.ReadReq_hits::cpu0.inst 4104943 # number of ReadReq hits 882system.cpu0.l2cache.ReadReq_hits::cpu0.data 2390641 # number of ReadReq hits 883system.cpu0.l2cache.ReadReq_hits::total 6768916 # number of ReadReq hits 884system.cpu0.l2cache.Writeback_hits::writebacks 3276433 # number of Writeback hits 885system.cpu0.l2cache.Writeback_hits::total 3276433 # number of Writeback hits 886system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 610572 # number of WriteInvalidateReq hits 887system.cpu0.l2cache.WriteInvalidateReq_hits::total 610572 # number of WriteInvalidateReq hits 888system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 75583 # number of UpgradeReq hits 889system.cpu0.l2cache.UpgradeReq_hits::total 75583 # number of UpgradeReq hits 890system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 31346 # number of SCUpgradeReq hits 891system.cpu0.l2cache.SCUpgradeReq_hits::total 31346 # number of SCUpgradeReq hits 892system.cpu0.l2cache.ReadExReq_hits::cpu0.data 814537 # number of ReadExReq hits 893system.cpu0.l2cache.ReadExReq_hits::total 814537 # number of ReadExReq hits 894system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 166834 # number of demand (read+write) hits 895system.cpu0.l2cache.demand_hits::cpu0.itb.walker 106498 # number of demand (read+write) hits 896system.cpu0.l2cache.demand_hits::cpu0.inst 4104943 # number of demand (read+write) hits 897system.cpu0.l2cache.demand_hits::cpu0.data 3205178 # number of demand (read+write) hits 898system.cpu0.l2cache.demand_hits::total 7583453 # number of demand (read+write) hits 899system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 166834 # number of overall hits 900system.cpu0.l2cache.overall_hits::cpu0.itb.walker 106498 # number of overall hits 901system.cpu0.l2cache.overall_hits::cpu0.inst 4104943 # number of overall hits 902system.cpu0.l2cache.overall_hits::cpu0.data 3205178 # number of overall hits 903system.cpu0.l2cache.overall_hits::total 7583453 # number of overall hits 904system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 9451 # number of ReadReq misses 905system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7593 # number of ReadReq misses 906system.cpu0.l2cache.ReadReq_misses::cpu0.inst 164965 # number of ReadReq misses 907system.cpu0.l2cache.ReadReq_misses::cpu0.data 871580 # number of ReadReq misses 908system.cpu0.l2cache.ReadReq_misses::total 1053589 # number of ReadReq misses 909system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 86357 # number of WriteInvalidateReq misses 910system.cpu0.l2cache.WriteInvalidateReq_misses::total 86357 # number of WriteInvalidateReq misses 911system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 106896 # number of UpgradeReq misses 912system.cpu0.l2cache.UpgradeReq_misses::total 106896 # number of UpgradeReq misses 913system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 147374 # number of SCUpgradeReq misses 914system.cpu0.l2cache.SCUpgradeReq_misses::total 147374 # number of SCUpgradeReq misses 915system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses 916system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses 917system.cpu0.l2cache.ReadExReq_misses::cpu0.data 172967 # number of ReadExReq misses 918system.cpu0.l2cache.ReadExReq_misses::total 172967 # number of ReadExReq misses 919system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 9451 # number of demand (read+write) misses 920system.cpu0.l2cache.demand_misses::cpu0.itb.walker 7593 # number of demand (read+write) misses 921system.cpu0.l2cache.demand_misses::cpu0.inst 164965 # number of demand (read+write) misses 922system.cpu0.l2cache.demand_misses::cpu0.data 1044547 # number of demand (read+write) misses 923system.cpu0.l2cache.demand_misses::total 1226556 # number of demand (read+write) misses 924system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 9451 # number of overall misses 925system.cpu0.l2cache.overall_misses::cpu0.itb.walker 7593 # number of overall misses 926system.cpu0.l2cache.overall_misses::cpu0.inst 164965 # number of overall misses 927system.cpu0.l2cache.overall_misses::cpu0.data 1044547 # number of overall misses 928system.cpu0.l2cache.overall_misses::total 1226556 # number of overall misses 929system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 247144715 # number of ReadReq miss cycles 930system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 215825476 # number of ReadReq miss cycles 931system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 4449371565 # number of ReadReq miss cycles 932system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 25701723776 # number of ReadReq miss cycles 933system.cpu0.l2cache.ReadReq_miss_latency::total 30614065532 # number of ReadReq miss cycles 934system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 5651418353 # number of WriteInvalidateReq miss cycles 935system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 5651418353 # number of WriteInvalidateReq miss cycles 936system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2080242902 # number of UpgradeReq miss cycles 937system.cpu0.l2cache.UpgradeReq_miss_latency::total 2080242902 # number of UpgradeReq miss cycles 938system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2994303005 # number of SCUpgradeReq miss cycles 939system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2994303005 # number of SCUpgradeReq miss cycles 940system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 855000 # number of SCUpgradeFailReq miss cycles 941system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 855000 # number of SCUpgradeFailReq miss cycles 942system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 6538293027 # number of ReadExReq miss cycles 943system.cpu0.l2cache.ReadExReq_miss_latency::total 6538293027 # number of ReadExReq miss cycles 944system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 247144715 # number of demand (read+write) miss cycles 945system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 215825476 # number of demand (read+write) miss cycles 946system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4449371565 # number of demand (read+write) miss cycles 947system.cpu0.l2cache.demand_miss_latency::cpu0.data 32240016803 # number of demand (read+write) miss cycles 948system.cpu0.l2cache.demand_miss_latency::total 37152358559 # number of demand (read+write) miss cycles 949system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 247144715 # number of overall miss cycles 950system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 215825476 # number of overall miss cycles 951system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4449371565 # number of overall miss cycles 952system.cpu0.l2cache.overall_miss_latency::cpu0.data 32240016803 # number of overall miss cycles 953system.cpu0.l2cache.overall_miss_latency::total 37152358559 # number of overall miss cycles 954system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 176285 # number of ReadReq accesses(hits+misses) 955system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 114091 # number of ReadReq accesses(hits+misses) 956system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 4269908 # number of ReadReq accesses(hits+misses) 957system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3262221 # number of ReadReq accesses(hits+misses) 958system.cpu0.l2cache.ReadReq_accesses::total 7822505 # number of ReadReq accesses(hits+misses) 959system.cpu0.l2cache.Writeback_accesses::writebacks 3276433 # number of Writeback accesses(hits+misses) 960system.cpu0.l2cache.Writeback_accesses::total 3276433 # number of Writeback accesses(hits+misses) 961system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 696929 # number of WriteInvalidateReq accesses(hits+misses) 962system.cpu0.l2cache.WriteInvalidateReq_accesses::total 696929 # number of WriteInvalidateReq accesses(hits+misses) 963system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 182479 # number of UpgradeReq accesses(hits+misses) 964system.cpu0.l2cache.UpgradeReq_accesses::total 182479 # number of UpgradeReq accesses(hits+misses) 965system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 178720 # number of SCUpgradeReq accesses(hits+misses) 966system.cpu0.l2cache.SCUpgradeReq_accesses::total 178720 # number of SCUpgradeReq accesses(hits+misses) 967system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) 968system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) 969system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 987504 # number of ReadExReq accesses(hits+misses) 970system.cpu0.l2cache.ReadExReq_accesses::total 987504 # number of ReadExReq accesses(hits+misses) 971system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 176285 # number of demand (read+write) accesses 972system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 114091 # number of demand (read+write) accesses 973system.cpu0.l2cache.demand_accesses::cpu0.inst 4269908 # number of demand (read+write) accesses 974system.cpu0.l2cache.demand_accesses::cpu0.data 4249725 # number of demand (read+write) accesses 975system.cpu0.l2cache.demand_accesses::total 8810009 # number of demand (read+write) accesses 976system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 176285 # number of overall (read+write) accesses 977system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 114091 # number of overall (read+write) accesses 978system.cpu0.l2cache.overall_accesses::cpu0.inst 4269908 # number of overall (read+write) accesses 979system.cpu0.l2cache.overall_accesses::cpu0.data 4249725 # number of overall (read+write) accesses 980system.cpu0.l2cache.overall_accesses::total 8810009 # number of overall (read+write) accesses 981system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.053612 # miss rate for ReadReq accesses 982system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.066552 # miss rate for ReadReq accesses 983system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.038634 # miss rate for ReadReq accesses 984system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.267174 # miss rate for ReadReq accesses 985system.cpu0.l2cache.ReadReq_miss_rate::total 0.134687 # miss rate for ReadReq accesses 986system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.123911 # miss rate for WriteInvalidateReq accesses 987system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.123911 # miss rate for WriteInvalidateReq accesses 988system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.585799 # miss rate for UpgradeReq accesses 989system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.585799 # miss rate for UpgradeReq accesses 990system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.824608 # miss rate for SCUpgradeReq accesses 991system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.824608 # miss rate for SCUpgradeReq accesses 992system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 993system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 994system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.175156 # miss rate for ReadExReq accesses 995system.cpu0.l2cache.ReadExReq_miss_rate::total 0.175156 # miss rate for ReadExReq accesses 996system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.053612 # miss rate for demand accesses 997system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.066552 # miss rate for demand accesses 998system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.038634 # miss rate for demand accesses 999system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.245792 # miss rate for demand accesses 1000system.cpu0.l2cache.demand_miss_rate::total 0.139223 # miss rate for demand accesses 1001system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.053612 # miss rate for overall accesses 1002system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.066552 # miss rate for overall accesses 1003system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.038634 # miss rate for overall accesses 1004system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.245792 # miss rate for overall accesses 1005system.cpu0.l2cache.overall_miss_rate::total 0.139223 # miss rate for overall accesses 1006system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26150.112686 # average ReadReq miss latency 1007system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 28424.269195 # average ReadReq miss latency 1008system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 26971.609523 # average ReadReq miss latency 1009system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29488.657124 # average ReadReq miss latency 1010system.cpu0.l2cache.ReadReq_avg_miss_latency::total 29056.933522 # average ReadReq miss latency 1011system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 65442.504406 # average WriteInvalidateReq miss latency 1012system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 65442.504406 # average WriteInvalidateReq miss latency 1013system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 19460.437266 # average UpgradeReq miss latency 1014system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 19460.437266 # average UpgradeReq miss latency 1015system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20317.715506 # average SCUpgradeReq miss latency 1016system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20317.715506 # average SCUpgradeReq miss latency 1017system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 855000 # average SCUpgradeFailReq miss latency 1018system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 855000 # average SCUpgradeFailReq miss latency 1019system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 37800.811872 # average ReadExReq miss latency 1020system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 37800.811872 # average ReadExReq miss latency 1021system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26150.112686 # average overall miss latency 1022system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 28424.269195 # average overall miss latency 1023system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 26971.609523 # average overall miss latency 1024system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 30865.070507 # average overall miss latency 1025system.cpu0.l2cache.demand_avg_miss_latency::total 30289.981508 # average overall miss latency 1026system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26150.112686 # average overall miss latency 1027system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 28424.269195 # average overall miss latency 1028system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 26971.609523 # average overall miss latency 1029system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 30865.070507 # average overall miss latency 1030system.cpu0.l2cache.overall_avg_miss_latency::total 30289.981508 # average overall miss latency 1031system.cpu0.l2cache.blocked_cycles::no_mshrs 52335 # number of cycles access was blocked 1032system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1033system.cpu0.l2cache.blocked::no_mshrs 662 # number of cycles access was blocked 1034system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1035system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 79.055891 # average number of cycles each access was blocked 1036system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1037system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1038system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1039system.cpu0.l2cache.writebacks::writebacks 1358617 # number of writebacks 1040system.cpu0.l2cache.writebacks::total 1358617 # number of writebacks 1041system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 24755 # number of ReadReq MSHR hits 1042system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 5238 # number of ReadReq MSHR hits 1043system.cpu0.l2cache.ReadReq_mshr_hits::total 29993 # number of ReadReq MSHR hits 1044system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.data 37532 # number of WriteInvalidateReq MSHR hits 1045system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total 37532 # number of WriteInvalidateReq MSHR hits 1046system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 2960 # number of ReadExReq MSHR hits 1047system.cpu0.l2cache.ReadExReq_mshr_hits::total 2960 # number of ReadExReq MSHR hits 1048system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 24755 # number of demand (read+write) MSHR hits 1049system.cpu0.l2cache.demand_mshr_hits::cpu0.data 8198 # number of demand (read+write) MSHR hits 1050system.cpu0.l2cache.demand_mshr_hits::total 32953 # number of demand (read+write) MSHR hits 1051system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 24755 # number of overall MSHR hits 1052system.cpu0.l2cache.overall_mshr_hits::cpu0.data 8198 # number of overall MSHR hits 1053system.cpu0.l2cache.overall_mshr_hits::total 32953 # number of overall MSHR hits 1054system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 9451 # number of ReadReq MSHR misses 1055system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 7593 # number of ReadReq MSHR misses 1056system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 140210 # number of ReadReq MSHR misses 1057system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 866342 # number of ReadReq MSHR misses 1058system.cpu0.l2cache.ReadReq_mshr_misses::total 1023596 # number of ReadReq MSHR misses 1059system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 2938301 # number of HardPFReq MSHR misses 1060system.cpu0.l2cache.HardPFReq_mshr_misses::total 2938301 # number of HardPFReq MSHR misses 1061system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 48825 # number of WriteInvalidateReq MSHR misses 1062system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 48825 # number of WriteInvalidateReq MSHR misses 1063system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 106896 # number of UpgradeReq MSHR misses 1064system.cpu0.l2cache.UpgradeReq_mshr_misses::total 106896 # number of UpgradeReq MSHR misses 1065system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 147374 # number of SCUpgradeReq MSHR misses 1066system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 147374 # number of SCUpgradeReq MSHR misses 1067system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses 1068system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses 1069system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 170007 # number of ReadExReq MSHR misses 1070system.cpu0.l2cache.ReadExReq_mshr_misses::total 170007 # number of ReadExReq MSHR misses 1071system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 9451 # number of demand (read+write) MSHR misses 1072system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 7593 # number of demand (read+write) MSHR misses 1073system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 140210 # number of demand (read+write) MSHR misses 1074system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1036349 # number of demand (read+write) MSHR misses 1075system.cpu0.l2cache.demand_mshr_misses::total 1193603 # number of demand (read+write) MSHR misses 1076system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 9451 # number of overall MSHR misses 1077system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 7593 # number of overall MSHR misses 1078system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 140210 # number of overall MSHR misses 1079system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1036349 # number of overall MSHR misses 1080system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 2938301 # number of overall MSHR misses 1081system.cpu0.l2cache.overall_mshr_misses::total 4131904 # number of overall MSHR misses 1082system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 180794801 # number of ReadReq MSHR miss cycles 1083system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 162470030 # number of ReadReq MSHR miss cycles 1084system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 3053904483 # number of ReadReq MSHR miss cycles 1085system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 19401824260 # number of ReadReq MSHR miss cycles 1086system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 22798993574 # number of ReadReq MSHR miss cycles 1087system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 128557799780 # number of HardPFReq MSHR miss cycles 1088system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 128557799780 # number of HardPFReq MSHR miss cycles 1089system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 892232564 # number of WriteInvalidateReq MSHR miss cycles 1090system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 892232564 # number of WriteInvalidateReq MSHR miss cycles 1091system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1781047970 # number of UpgradeReq MSHR miss cycles 1092system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1781047970 # number of UpgradeReq MSHR miss cycles 1093system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2043441791 # number of SCUpgradeReq MSHR miss cycles 1094system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2043441791 # number of SCUpgradeReq MSHR miss cycles 1095system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 687000 # number of SCUpgradeFailReq MSHR miss cycles 1096system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 687000 # number of SCUpgradeFailReq MSHR miss cycles 1097system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 5046326892 # number of ReadExReq MSHR miss cycles 1098system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 5046326892 # number of ReadExReq MSHR miss cycles 1099system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 180794801 # number of demand (read+write) MSHR miss cycles 1100system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 162470030 # number of demand (read+write) MSHR miss cycles 1101system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3053904483 # number of demand (read+write) MSHR miss cycles 1102system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 24448151152 # number of demand (read+write) MSHR miss cycles 1103system.cpu0.l2cache.demand_mshr_miss_latency::total 27845320466 # number of demand (read+write) MSHR miss cycles 1104system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 180794801 # number of overall MSHR miss cycles 1105system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 162470030 # number of overall MSHR miss cycles 1106system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3053904483 # number of overall MSHR miss cycles 1107system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 24448151152 # number of overall MSHR miss cycles 1108system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 128557799780 # number of overall MSHR miss cycles 1109system.cpu0.l2cache.overall_mshr_miss_latency::total 156403120246 # number of overall MSHR miss cycles 1110system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3061864750 # number of ReadReq MSHR uncacheable cycles 1111system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2268534801 # number of ReadReq MSHR uncacheable cycles 1112system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5330399551 # number of ReadReq MSHR uncacheable cycles 1113system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2268405055 # number of WriteReq MSHR uncacheable cycles 1114system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2268405055 # number of WriteReq MSHR uncacheable cycles 1115system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3061864750 # number of overall MSHR uncacheable cycles 1116system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4536939856 # number of overall MSHR uncacheable cycles 1117system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7598804606 # number of overall MSHR uncacheable cycles 1118system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.053612 # mshr miss rate for ReadReq accesses 1119system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.066552 # mshr miss rate for ReadReq accesses 1120system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.032837 # mshr miss rate for ReadReq accesses 1121system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.265568 # mshr miss rate for ReadReq accesses 1122system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.130853 # mshr miss rate for ReadReq accesses 1123system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1124system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1125system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.070057 # mshr miss rate for WriteInvalidateReq accesses 1126system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.070057 # mshr miss rate for WriteInvalidateReq accesses 1127system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.585799 # mshr miss rate for UpgradeReq accesses 1128system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.585799 # mshr miss rate for UpgradeReq accesses 1129system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.824608 # mshr miss rate for SCUpgradeReq accesses 1130system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.824608 # mshr miss rate for SCUpgradeReq accesses 1131system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1132system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1133system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.172158 # mshr miss rate for ReadExReq accesses 1134system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.172158 # mshr miss rate for ReadExReq accesses 1135system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.053612 # mshr miss rate for demand accesses 1136system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.066552 # mshr miss rate for demand accesses 1137system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.032837 # mshr miss rate for demand accesses 1138system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.243863 # mshr miss rate for demand accesses 1139system.cpu0.l2cache.demand_mshr_miss_rate::total 0.135483 # mshr miss rate for demand accesses 1140system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.053612 # mshr miss rate for overall accesses 1141system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.066552 # mshr miss rate for overall accesses 1142system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.032837 # mshr miss rate for overall accesses 1143system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.243863 # mshr miss rate for overall accesses 1144system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1145system.cpu0.l2cache.overall_mshr_miss_rate::total 0.469001 # mshr miss rate for overall accesses 1146system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 19129.700667 # average ReadReq mshr miss latency 1147system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21397.343606 # average ReadReq mshr miss latency 1148system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 21780.932052 # average ReadReq mshr miss latency 1149system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22395.109853 # average ReadReq mshr miss latency 1150system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22273.429726 # average ReadReq mshr miss latency 1151system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43752.426923 # average HardPFReq mshr miss latency 1152system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 43752.426923 # average HardPFReq mshr miss latency 1153system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 18274.092453 # average WriteInvalidateReq mshr miss latency 1154system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 18274.092453 # average WriteInvalidateReq mshr miss latency 1155system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16661.502488 # average UpgradeReq mshr miss latency 1156system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16661.502488 # average UpgradeReq mshr miss latency 1157system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13865.687238 # average SCUpgradeReq mshr miss latency 1158system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13865.687238 # average SCUpgradeReq mshr miss latency 1159system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 687000 # average SCUpgradeFailReq mshr miss latency 1160system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 687000 # average SCUpgradeFailReq mshr miss latency 1161system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 29683.053592 # average ReadExReq mshr miss latency 1162system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 29683.053592 # average ReadExReq mshr miss latency 1163system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19129.700667 # average overall mshr miss latency 1164system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 21397.343606 # average overall mshr miss latency 1165system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 21780.932052 # average overall mshr miss latency 1166system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 23590.654453 # average overall mshr miss latency 1167system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23328.795643 # average overall mshr miss latency 1168system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19129.700667 # average overall mshr miss latency 1169system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 21397.343606 # average overall mshr miss latency 1170system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 21780.932052 # average overall mshr miss latency 1171system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 23590.654453 # average overall mshr miss latency 1172system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43752.426923 # average overall mshr miss latency 1173system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 37852.554233 # average overall mshr miss latency 1174system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1175system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1176system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1177system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1178system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1179system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1180system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1181system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1182system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1183system.cpu0.toL2Bus.trans_dist::ReadReq 11465749 # Transaction distribution 1184system.cpu0.toL2Bus.trans_dist::ReadResp 8074092 # Transaction distribution 1185system.cpu0.toL2Bus.trans_dist::WriteReq 15773 # Transaction distribution 1186system.cpu0.toL2Bus.trans_dist::WriteResp 15773 # Transaction distribution 1187system.cpu0.toL2Bus.trans_dist::Writeback 3276433 # Transaction distribution 1188system.cpu0.toL2Bus.trans_dist::HardPFReq 4228803 # Transaction distribution 1189system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 811507 # Transaction distribution 1190system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 696929 # Transaction distribution 1191system.cpu0.toL2Bus.trans_dist::UpgradeReq 407420 # Transaction distribution 1192system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 328722 # Transaction distribution 1193system.cpu0.toL2Bus.trans_dist::UpgradeResp 423022 # Transaction distribution 1194system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 30 # Transaction distribution 1195system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution 1196system.cpu0.toL2Bus.trans_dist::ReadExReq 1108208 # Transaction distribution 1197system.cpu0.toL2Bus.trans_dist::ReadExResp 995011 # Transaction distribution 1198system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 8626066 # Packet count per connected master and slave (bytes) 1199system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 14109371 # Packet count per connected master and slave (bytes) 1200system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 260774 # Packet count per connected master and slave (bytes) 1201system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 426575 # Packet count per connected master and slave (bytes) 1202system.cpu0.toL2Bus.pkt_count::total 23422786 # Packet count per connected master and slave (bytes) 1203system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 273446612 # Cumulative packet size per connected master and slave (bytes) 1204system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 532438419 # Cumulative packet size per connected master and slave (bytes) 1205system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 912728 # Cumulative packet size per connected master and slave (bytes) 1206system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1410280 # Cumulative packet size per connected master and slave (bytes) 1207system.cpu0.toL2Bus.pkt_size::total 808208039 # Cumulative packet size per connected master and slave (bytes) 1208system.cpu0.toL2Bus.snoops 8581549 # Total snoops (count) 1209system.cpu0.toL2Bus.snoop_fanout::samples 21569506 # Request fanout histogram 1210system.cpu0.toL2Bus.snoop_fanout::mean 5.385644 # Request fanout histogram 1211system.cpu0.toL2Bus.snoop_fanout::stdev 0.486747 # Request fanout histogram 1212system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1213system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1214system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1215system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1216system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1217system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1218system.cpu0.toL2Bus.snoop_fanout::5 13251364 61.44% 61.44% # Request fanout histogram 1219system.cpu0.toL2Bus.snoop_fanout::6 8318142 38.56% 100.00% # Request fanout histogram 1220system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1221system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1222system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1223system.cpu0.toL2Bus.snoop_fanout::total 21569506 # Request fanout histogram 1224system.cpu0.toL2Bus.reqLayer0.occupancy 10644176370 # Layer occupancy (ticks) 1225system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 1226system.cpu0.toL2Bus.snoopLayer0.occupancy 173370992 # Layer occupancy (ticks) 1227system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1228system.cpu0.toL2Bus.respLayer0.occupancy 6459583336 # Layer occupancy (ticks) 1229system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1230system.cpu0.toL2Bus.respLayer1.occupancy 6973558574 # Layer occupancy (ticks) 1231system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1232system.cpu0.toL2Bus.respLayer2.occupancy 146771777 # Layer occupancy (ticks) 1233system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1234system.cpu0.toL2Bus.respLayer3.occupancy 250366041 # Layer occupancy (ticks) 1235system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1236system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1237system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1238system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1239system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1240system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1241system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1242system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1243system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1244system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1245system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1246system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1247system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1248system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1249system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1250system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1251system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1252system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1253system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1254system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1255system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1256system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1257system.cpu1.dtb.inst_hits 0 # ITB inst hits 1258system.cpu1.dtb.inst_misses 0 # ITB inst misses 1259system.cpu1.dtb.read_hits 84980512 # DTB read hits 1260system.cpu1.dtb.read_misses 74547 # DTB read misses 1261system.cpu1.dtb.write_hits 77969612 # DTB write hits 1262system.cpu1.dtb.write_misses 26781 # DTB write misses 1263system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1264system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1265system.cpu1.dtb.flush_tlb_mva_asid 37660 # Number of times TLB was flushed by MVA & ASID 1266system.cpu1.dtb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID 1267system.cpu1.dtb.flush_entries 37319 # Number of entries that have been flushed from TLB 1268system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 1269system.cpu1.dtb.prefetch_faults 4156 # Number of TLB faults due to prefetch 1270system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1271system.cpu1.dtb.perms_faults 10210 # Number of TLB faults due to permissions restrictions 1272system.cpu1.dtb.read_accesses 85055059 # DTB read accesses 1273system.cpu1.dtb.write_accesses 77996393 # DTB write accesses 1274system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1275system.cpu1.dtb.hits 162950124 # DTB hits 1276system.cpu1.dtb.misses 101328 # DTB misses 1277system.cpu1.dtb.accesses 163051452 # DTB accesses 1278system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1279system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1280system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1281system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1282system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1283system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1284system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1285system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1286system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1287system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1288system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1289system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1290system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1291system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1292system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1293system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1294system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1295system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1296system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1297system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1298system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1299system.cpu1.itb.inst_hits 447940407 # ITB inst hits 1300system.cpu1.itb.inst_misses 68561 # ITB inst misses 1301system.cpu1.itb.read_hits 0 # DTB read hits 1302system.cpu1.itb.read_misses 0 # DTB read misses 1303system.cpu1.itb.write_hits 0 # DTB write hits 1304system.cpu1.itb.write_misses 0 # DTB write misses 1305system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1306system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1307system.cpu1.itb.flush_tlb_mva_asid 37660 # Number of times TLB was flushed by MVA & ASID 1308system.cpu1.itb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID 1309system.cpu1.itb.flush_entries 26339 # Number of entries that have been flushed from TLB 1310system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1311system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1312system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1313system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1314system.cpu1.itb.read_accesses 0 # DTB read accesses 1315system.cpu1.itb.write_accesses 0 # DTB write accesses 1316system.cpu1.itb.inst_accesses 448008968 # ITB inst accesses 1317system.cpu1.itb.hits 447940407 # DTB hits 1318system.cpu1.itb.misses 68561 # DTB misses 1319system.cpu1.itb.accesses 448008968 # DTB accesses 1320system.cpu1.numCycles 94796862537 # number of cpu cycles simulated 1321system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1322system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1323system.cpu1.committedInsts 447645202 # Number of instructions committed 1324system.cpu1.committedOps 528119835 # Number of ops (including micro ops) committed 1325system.cpu1.num_int_alu_accesses 486291398 # Number of integer alu accesses 1326system.cpu1.num_fp_alu_accesses 624474 # Number of float alu accesses 1327system.cpu1.num_func_calls 27450761 # number of times a function call or return occured 1328system.cpu1.num_conditional_control_insts 67545606 # number of instructions that are conditional controls 1329system.cpu1.num_int_insts 486291398 # number of integer instructions 1330system.cpu1.num_fp_insts 624474 # number of float instructions 1331system.cpu1.num_int_register_reads 698728829 # number of times the integer registers were read 1332system.cpu1.num_int_register_writes 384530758 # number of times the integer registers were written 1333system.cpu1.num_fp_register_reads 985803 # number of times the floating registers were read 1334system.cpu1.num_fp_register_writes 576512 # number of times the floating registers were written 1335system.cpu1.num_cc_register_reads 114161169 # number of times the CC registers were read 1336system.cpu1.num_cc_register_writes 113813296 # number of times the CC registers were written 1337system.cpu1.num_mem_refs 162934099 # number of memory refs 1338system.cpu1.num_load_insts 84972579 # Number of load instructions 1339system.cpu1.num_store_insts 77961520 # Number of store instructions 1340system.cpu1.num_idle_cycles 93770083152.566025 # Number of idle cycles 1341system.cpu1.num_busy_cycles 1026779384.433978 # Number of busy cycles 1342system.cpu1.not_idle_fraction 0.010831 # Percentage of non-idle cycles 1343system.cpu1.idle_fraction 0.989169 # Percentage of idle cycles 1344system.cpu1.Branches 100081816 # Number of branches fetched 1345system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 1346system.cpu1.op_class::IntAlu 364276895 68.94% 68.94% # Class of executed instruction 1347system.cpu1.op_class::IntMult 1051011 0.20% 69.14% # Class of executed instruction 1348system.cpu1.op_class::IntDiv 60606 0.01% 69.15% # Class of executed instruction 1349system.cpu1.op_class::FloatAdd 0 0.00% 69.15% # Class of executed instruction 1350system.cpu1.op_class::FloatCmp 0 0.00% 69.15% # Class of executed instruction 1351system.cpu1.op_class::FloatCvt 0 0.00% 69.15% # Class of executed instruction 1352system.cpu1.op_class::FloatMult 0 0.00% 69.15% # Class of executed instruction 1353system.cpu1.op_class::FloatDiv 0 0.00% 69.15% # Class of executed instruction 1354system.cpu1.op_class::FloatSqrt 0 0.00% 69.15% # Class of executed instruction 1355system.cpu1.op_class::SimdAdd 0 0.00% 69.15% # Class of executed instruction 1356system.cpu1.op_class::SimdAddAcc 0 0.00% 69.15% # Class of executed instruction 1357system.cpu1.op_class::SimdAlu 0 0.00% 69.15% # Class of executed instruction 1358system.cpu1.op_class::SimdCmp 0 0.00% 69.15% # Class of executed instruction 1359system.cpu1.op_class::SimdCvt 0 0.00% 69.15% # Class of executed instruction 1360system.cpu1.op_class::SimdMisc 0 0.00% 69.15% # Class of executed instruction 1361system.cpu1.op_class::SimdMult 0 0.00% 69.15% # Class of executed instruction 1362system.cpu1.op_class::SimdMultAcc 0 0.00% 69.15% # Class of executed instruction 1363system.cpu1.op_class::SimdShift 0 0.00% 69.15% # Class of executed instruction 1364system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.15% # Class of executed instruction 1365system.cpu1.op_class::SimdSqrt 0 0.00% 69.15% # Class of executed instruction 1366system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.15% # Class of executed instruction 1367system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.15% # Class of executed instruction 1368system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.15% # Class of executed instruction 1369system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.15% # Class of executed instruction 1370system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.15% # Class of executed instruction 1371system.cpu1.op_class::SimdFloatMisc 92495 0.02% 69.17% # Class of executed instruction 1372system.cpu1.op_class::SimdFloatMult 0 0.00% 69.17% # Class of executed instruction 1373system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.17% # Class of executed instruction 1374system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.17% # Class of executed instruction 1375system.cpu1.op_class::MemRead 84972579 16.08% 85.25% # Class of executed instruction 1376system.cpu1.op_class::MemWrite 77961520 14.75% 100.00% # Class of executed instruction 1377system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1378system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 1379system.cpu1.op_class::total 528415149 # Class of executed instruction 1380system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1381system.cpu1.kern.inst.quiesce 13701 # number of quiesce instructions executed 1382system.cpu1.dcache.tags.replacements 5194711 # number of replacements 1383system.cpu1.dcache.tags.tagsinuse 457.134068 # Cycle average of tags in use 1384system.cpu1.dcache.tags.total_refs 157559099 # Total number of references to valid blocks. 1385system.cpu1.dcache.tags.sampled_refs 5195223 # Sample count of references to valid blocks. 1386system.cpu1.dcache.tags.avg_refs 30.327687 # Average number of references to valid blocks. 1387system.cpu1.dcache.tags.warmup_cycle 8367548601000 # Cycle when the warmup percentage was hit. 1388system.cpu1.dcache.tags.occ_blocks::cpu1.data 457.134068 # Average occupied blocks per requestor 1389system.cpu1.dcache.tags.occ_percent::cpu1.data 0.892840 # Average percentage of cache occupancy 1390system.cpu1.dcache.tags.occ_percent::total 0.892840 # Average percentage of cache occupancy 1391system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1392system.cpu1.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id 1393system.cpu1.dcache.tags.age_task_id_blocks_1024::1 415 # Occupied blocks per task id 1394system.cpu1.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 1395system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1396system.cpu1.dcache.tags.tag_accesses 331059949 # Number of tag accesses 1397system.cpu1.dcache.tags.data_accesses 331059949 # Number of data accesses 1398system.cpu1.dcache.ReadReq_hits::cpu1.data 79405575 # number of ReadReq hits 1399system.cpu1.dcache.ReadReq_hits::total 79405575 # number of ReadReq hits 1400system.cpu1.dcache.WriteReq_hits::cpu1.data 74066119 # number of WriteReq hits 1401system.cpu1.dcache.WriteReq_hits::total 74066119 # number of WriteReq hits 1402system.cpu1.dcache.SoftPFReq_hits::cpu1.data 191889 # number of SoftPFReq hits 1403system.cpu1.dcache.SoftPFReq_hits::total 191889 # number of SoftPFReq hits 1404system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 197632 # number of WriteInvalidateReq hits 1405system.cpu1.dcache.WriteInvalidateReq_hits::total 197632 # number of WriteInvalidateReq hits 1406system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1669680 # number of LoadLockedReq hits 1407system.cpu1.dcache.LoadLockedReq_hits::total 1669680 # number of LoadLockedReq hits 1408system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1654141 # number of StoreCondReq hits 1409system.cpu1.dcache.StoreCondReq_hits::total 1654141 # number of StoreCondReq hits 1410system.cpu1.dcache.demand_hits::cpu1.data 153471694 # number of demand (read+write) hits 1411system.cpu1.dcache.demand_hits::total 153471694 # number of demand (read+write) hits 1412system.cpu1.dcache.overall_hits::cpu1.data 153663583 # number of overall hits 1413system.cpu1.dcache.overall_hits::total 153663583 # number of overall hits 1414system.cpu1.dcache.ReadReq_misses::cpu1.data 2946837 # number of ReadReq misses 1415system.cpu1.dcache.ReadReq_misses::total 2946837 # number of ReadReq misses 1416system.cpu1.dcache.WriteReq_misses::cpu1.data 1283113 # number of WriteReq misses 1417system.cpu1.dcache.WriteReq_misses::total 1283113 # number of WriteReq misses 1418system.cpu1.dcache.SoftPFReq_misses::cpu1.data 571898 # number of SoftPFReq misses 1419system.cpu1.dcache.SoftPFReq_misses::total 571898 # number of SoftPFReq misses 1420system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 550709 # number of WriteInvalidateReq misses 1421system.cpu1.dcache.WriteInvalidateReq_misses::total 550709 # number of WriteInvalidateReq misses 1422system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 171203 # number of LoadLockedReq misses 1423system.cpu1.dcache.LoadLockedReq_misses::total 171203 # number of LoadLockedReq misses 1424system.cpu1.dcache.StoreCondReq_misses::cpu1.data 185528 # number of StoreCondReq misses 1425system.cpu1.dcache.StoreCondReq_misses::total 185528 # number of StoreCondReq misses 1426system.cpu1.dcache.demand_misses::cpu1.data 4229950 # number of demand (read+write) misses 1427system.cpu1.dcache.demand_misses::total 4229950 # number of demand (read+write) misses 1428system.cpu1.dcache.overall_misses::cpu1.data 4801848 # number of overall misses 1429system.cpu1.dcache.overall_misses::total 4801848 # number of overall misses 1430system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 41215882509 # number of ReadReq miss cycles 1431system.cpu1.dcache.ReadReq_miss_latency::total 41215882509 # number of ReadReq miss cycles 1432system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 19312866378 # number of WriteReq miss cycles 1433system.cpu1.dcache.WriteReq_miss_latency::total 19312866378 # number of WriteReq miss cycles 1434system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 6595698094 # number of WriteInvalidateReq miss cycles 1435system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 6595698094 # number of WriteInvalidateReq miss cycles 1436system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2383654561 # number of LoadLockedReq miss cycles 1437system.cpu1.dcache.LoadLockedReq_miss_latency::total 2383654561 # number of LoadLockedReq miss cycles 1438system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3901847697 # number of StoreCondReq miss cycles 1439system.cpu1.dcache.StoreCondReq_miss_latency::total 3901847697 # number of StoreCondReq miss cycles 1440system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1095500 # number of StoreCondFailReq miss cycles 1441system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1095500 # number of StoreCondFailReq miss cycles 1442system.cpu1.dcache.demand_miss_latency::cpu1.data 60528748887 # number of demand (read+write) miss cycles 1443system.cpu1.dcache.demand_miss_latency::total 60528748887 # number of demand (read+write) miss cycles 1444system.cpu1.dcache.overall_miss_latency::cpu1.data 60528748887 # number of overall miss cycles 1445system.cpu1.dcache.overall_miss_latency::total 60528748887 # number of overall miss cycles 1446system.cpu1.dcache.ReadReq_accesses::cpu1.data 82352412 # number of ReadReq accesses(hits+misses) 1447system.cpu1.dcache.ReadReq_accesses::total 82352412 # number of ReadReq accesses(hits+misses) 1448system.cpu1.dcache.WriteReq_accesses::cpu1.data 75349232 # number of WriteReq accesses(hits+misses) 1449system.cpu1.dcache.WriteReq_accesses::total 75349232 # number of WriteReq accesses(hits+misses) 1450system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 763787 # number of SoftPFReq accesses(hits+misses) 1451system.cpu1.dcache.SoftPFReq_accesses::total 763787 # number of SoftPFReq accesses(hits+misses) 1452system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 748341 # number of WriteInvalidateReq accesses(hits+misses) 1453system.cpu1.dcache.WriteInvalidateReq_accesses::total 748341 # number of WriteInvalidateReq accesses(hits+misses) 1454system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1840883 # number of LoadLockedReq accesses(hits+misses) 1455system.cpu1.dcache.LoadLockedReq_accesses::total 1840883 # number of LoadLockedReq accesses(hits+misses) 1456system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1839669 # number of StoreCondReq accesses(hits+misses) 1457system.cpu1.dcache.StoreCondReq_accesses::total 1839669 # number of StoreCondReq accesses(hits+misses) 1458system.cpu1.dcache.demand_accesses::cpu1.data 157701644 # number of demand (read+write) accesses 1459system.cpu1.dcache.demand_accesses::total 157701644 # number of demand (read+write) accesses 1460system.cpu1.dcache.overall_accesses::cpu1.data 158465431 # number of overall (read+write) accesses 1461system.cpu1.dcache.overall_accesses::total 158465431 # number of overall (read+write) accesses 1462system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035783 # miss rate for ReadReq accesses 1463system.cpu1.dcache.ReadReq_miss_rate::total 0.035783 # miss rate for ReadReq accesses 1464system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.017029 # miss rate for WriteReq accesses 1465system.cpu1.dcache.WriteReq_miss_rate::total 0.017029 # miss rate for WriteReq accesses 1466system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.748766 # miss rate for SoftPFReq accesses 1467system.cpu1.dcache.SoftPFReq_miss_rate::total 0.748766 # miss rate for SoftPFReq accesses 1468system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.735906 # miss rate for WriteInvalidateReq accesses 1469system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.735906 # miss rate for WriteInvalidateReq accesses 1470system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.093000 # miss rate for LoadLockedReq accesses 1471system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.093000 # miss rate for LoadLockedReq accesses 1472system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100849 # miss rate for StoreCondReq accesses 1473system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100849 # miss rate for StoreCondReq accesses 1474system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026822 # miss rate for demand accesses 1475system.cpu1.dcache.demand_miss_rate::total 0.026822 # miss rate for demand accesses 1476system.cpu1.dcache.overall_miss_rate::cpu1.data 0.030302 # miss rate for overall accesses 1477system.cpu1.dcache.overall_miss_rate::total 0.030302 # miss rate for overall accesses 1478system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13986.481950 # average ReadReq miss latency 1479system.cpu1.dcache.ReadReq_avg_miss_latency::total 13986.481950 # average ReadReq miss latency 1480system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 15051.570967 # average WriteReq miss latency 1481system.cpu1.dcache.WriteReq_avg_miss_latency::total 15051.570967 # average WriteReq miss latency 1482system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 11976.739247 # average WriteInvalidateReq miss latency 1483system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 11976.739247 # average WriteInvalidateReq miss latency 1484system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13922.971916 # average LoadLockedReq miss latency 1485system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13922.971916 # average LoadLockedReq miss latency 1486system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21031.044893 # average StoreCondReq miss latency 1487system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21031.044893 # average StoreCondReq miss latency 1488system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1489system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1490system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14309.566044 # average overall miss latency 1491system.cpu1.dcache.demand_avg_miss_latency::total 14309.566044 # average overall miss latency 1492system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12605.302976 # average overall miss latency 1493system.cpu1.dcache.overall_avg_miss_latency::total 12605.302976 # average overall miss latency 1494system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1495system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1496system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1497system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1498system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1499system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1500system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1501system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1502system.cpu1.dcache.writebacks::writebacks 3397427 # number of writebacks 1503system.cpu1.dcache.writebacks::total 3397427 # number of writebacks 1504system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 14736 # number of ReadReq MSHR hits 1505system.cpu1.dcache.ReadReq_mshr_hits::total 14736 # number of ReadReq MSHR hits 1506system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 407 # number of WriteReq MSHR hits 1507system.cpu1.dcache.WriteReq_mshr_hits::total 407 # number of WriteReq MSHR hits 1508system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 48814 # number of LoadLockedReq MSHR hits 1509system.cpu1.dcache.LoadLockedReq_mshr_hits::total 48814 # number of LoadLockedReq MSHR hits 1510system.cpu1.dcache.demand_mshr_hits::cpu1.data 15143 # number of demand (read+write) MSHR hits 1511system.cpu1.dcache.demand_mshr_hits::total 15143 # number of demand (read+write) MSHR hits 1512system.cpu1.dcache.overall_mshr_hits::cpu1.data 15143 # number of overall MSHR hits 1513system.cpu1.dcache.overall_mshr_hits::total 15143 # number of overall MSHR hits 1514system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2932101 # number of ReadReq MSHR misses 1515system.cpu1.dcache.ReadReq_mshr_misses::total 2932101 # number of ReadReq MSHR misses 1516system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1282706 # number of WriteReq MSHR misses 1517system.cpu1.dcache.WriteReq_mshr_misses::total 1282706 # number of WriteReq MSHR misses 1518system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 571898 # number of SoftPFReq MSHR misses 1519system.cpu1.dcache.SoftPFReq_mshr_misses::total 571898 # number of SoftPFReq MSHR misses 1520system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 550709 # number of WriteInvalidateReq MSHR misses 1521system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 550709 # number of WriteInvalidateReq MSHR misses 1522system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 122389 # number of LoadLockedReq MSHR misses 1523system.cpu1.dcache.LoadLockedReq_mshr_misses::total 122389 # number of LoadLockedReq MSHR misses 1524system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 185528 # number of StoreCondReq MSHR misses 1525system.cpu1.dcache.StoreCondReq_mshr_misses::total 185528 # number of StoreCondReq MSHR misses 1526system.cpu1.dcache.demand_mshr_misses::cpu1.data 4214807 # number of demand (read+write) MSHR misses 1527system.cpu1.dcache.demand_mshr_misses::total 4214807 # number of demand (read+write) MSHR misses 1528system.cpu1.dcache.overall_mshr_misses::cpu1.data 4786705 # number of overall MSHR misses 1529system.cpu1.dcache.overall_mshr_misses::total 4786705 # number of overall MSHR misses 1530system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 34665979416 # number of ReadReq MSHR miss cycles 1531system.cpu1.dcache.ReadReq_mshr_miss_latency::total 34665979416 # number of ReadReq MSHR miss cycles 1532system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 16693598628 # number of WriteReq MSHR miss cycles 1533system.cpu1.dcache.WriteReq_mshr_miss_latency::total 16693598628 # number of WriteReq MSHR miss cycles 1534system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 11612454284 # number of SoftPFReq MSHR miss cycles 1535system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 11612454284 # number of SoftPFReq MSHR miss cycles 1536system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 5490664906 # number of WriteInvalidateReq MSHR miss cycles 1537system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 5490664906 # number of WriteInvalidateReq MSHR miss cycles 1538system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1373965707 # number of LoadLockedReq MSHR miss cycles 1539system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1373965707 # number of LoadLockedReq MSHR miss cycles 1540system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3521472303 # number of StoreCondReq MSHR miss cycles 1541system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3521472303 # number of StoreCondReq MSHR miss cycles 1542system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1037500 # number of StoreCondFailReq MSHR miss cycles 1543system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1037500 # number of StoreCondFailReq MSHR miss cycles 1544system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 51359578044 # number of demand (read+write) MSHR miss cycles 1545system.cpu1.dcache.demand_mshr_miss_latency::total 51359578044 # number of demand (read+write) MSHR miss cycles 1546system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 62972032328 # number of overall MSHR miss cycles 1547system.cpu1.dcache.overall_mshr_miss_latency::total 62972032328 # number of overall MSHR miss cycles 1548system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3972621225 # number of ReadReq MSHR uncacheable cycles 1549system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3972621225 # number of ReadReq MSHR uncacheable cycles 1550system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3807943973 # number of WriteReq MSHR uncacheable cycles 1551system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3807943973 # number of WriteReq MSHR uncacheable cycles 1552system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 7780565198 # number of overall MSHR uncacheable cycles 1553system.cpu1.dcache.overall_mshr_uncacheable_latency::total 7780565198 # number of overall MSHR uncacheable cycles 1554system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035604 # mshr miss rate for ReadReq accesses 1555system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035604 # mshr miss rate for ReadReq accesses 1556system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017023 # mshr miss rate for WriteReq accesses 1557system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017023 # mshr miss rate for WriteReq accesses 1558system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.748766 # mshr miss rate for SoftPFReq accesses 1559system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.748766 # mshr miss rate for SoftPFReq accesses 1560system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.735906 # mshr miss rate for WriteInvalidateReq accesses 1561system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.735906 # mshr miss rate for WriteInvalidateReq accesses 1562system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066484 # mshr miss rate for LoadLockedReq accesses 1563system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066484 # mshr miss rate for LoadLockedReq accesses 1564system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100849 # mshr miss rate for StoreCondReq accesses 1565system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100849 # mshr miss rate for StoreCondReq accesses 1566system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026726 # mshr miss rate for demand accesses 1567system.cpu1.dcache.demand_mshr_miss_rate::total 0.026726 # mshr miss rate for demand accesses 1568system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030207 # mshr miss rate for overall accesses 1569system.cpu1.dcache.overall_mshr_miss_rate::total 0.030207 # mshr miss rate for overall accesses 1570system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11822.914496 # average ReadReq mshr miss latency 1571system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11822.914496 # average ReadReq mshr miss latency 1572system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13014.360756 # average WriteReq mshr miss latency 1573system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13014.360756 # average WriteReq mshr miss latency 1574system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20305.114346 # average SoftPFReq mshr miss latency 1575system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20305.114346 # average SoftPFReq mshr miss latency 1576system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 9970.174640 # average WriteInvalidateReq mshr miss latency 1577system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 9970.174640 # average WriteInvalidateReq mshr miss latency 1578system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11226.218917 # average LoadLockedReq mshr miss latency 1579system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11226.218917 # average LoadLockedReq mshr miss latency 1580system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 18980.813155 # average StoreCondReq mshr miss latency 1581system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18980.813155 # average StoreCondReq mshr miss latency 1582system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1583system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1584system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12185.511233 # average overall mshr miss latency 1585system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12185.511233 # average overall mshr miss latency 1586system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13155.611705 # average overall mshr miss latency 1587system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13155.611705 # average overall mshr miss latency 1588system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1589system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1590system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1591system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1592system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1593system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1594system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1595system.cpu1.icache.tags.replacements 5786522 # number of replacements 1596system.cpu1.icache.tags.tagsinuse 496.339295 # Cycle average of tags in use 1597system.cpu1.icache.tags.total_refs 442153368 # Total number of references to valid blocks. 1598system.cpu1.icache.tags.sampled_refs 5787034 # Sample count of references to valid blocks. 1599system.cpu1.icache.tags.avg_refs 76.404142 # Average number of references to valid blocks. 1600system.cpu1.icache.tags.warmup_cycle 8367526246000 # Cycle when the warmup percentage was hit. 1601system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.339295 # Average occupied blocks per requestor 1602system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969413 # Average percentage of cache occupancy 1603system.cpu1.icache.tags.occ_percent::total 0.969413 # Average percentage of cache occupancy 1604system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1605system.cpu1.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id 1606system.cpu1.icache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id 1607system.cpu1.icache.tags.age_task_id_blocks_1024::2 108 # Occupied blocks per task id 1608system.cpu1.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 1609system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1610system.cpu1.icache.tags.tag_accesses 901667853 # Number of tag accesses 1611system.cpu1.icache.tags.data_accesses 901667853 # Number of data accesses 1612system.cpu1.icache.ReadReq_hits::cpu1.inst 442153368 # number of ReadReq hits 1613system.cpu1.icache.ReadReq_hits::total 442153368 # number of ReadReq hits 1614system.cpu1.icache.demand_hits::cpu1.inst 442153368 # number of demand (read+write) hits 1615system.cpu1.icache.demand_hits::total 442153368 # number of demand (read+write) hits 1616system.cpu1.icache.overall_hits::cpu1.inst 442153368 # number of overall hits 1617system.cpu1.icache.overall_hits::total 442153368 # number of overall hits 1618system.cpu1.icache.ReadReq_misses::cpu1.inst 5787039 # number of ReadReq misses 1619system.cpu1.icache.ReadReq_misses::total 5787039 # number of ReadReq misses 1620system.cpu1.icache.demand_misses::cpu1.inst 5787039 # number of demand (read+write) misses 1621system.cpu1.icache.demand_misses::total 5787039 # number of demand (read+write) misses 1622system.cpu1.icache.overall_misses::cpu1.inst 5787039 # number of overall misses 1623system.cpu1.icache.overall_misses::total 5787039 # number of overall misses 1624system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 50052191468 # number of ReadReq miss cycles 1625system.cpu1.icache.ReadReq_miss_latency::total 50052191468 # number of ReadReq miss cycles 1626system.cpu1.icache.demand_miss_latency::cpu1.inst 50052191468 # number of demand (read+write) miss cycles 1627system.cpu1.icache.demand_miss_latency::total 50052191468 # number of demand (read+write) miss cycles 1628system.cpu1.icache.overall_miss_latency::cpu1.inst 50052191468 # number of overall miss cycles 1629system.cpu1.icache.overall_miss_latency::total 50052191468 # number of overall miss cycles 1630system.cpu1.icache.ReadReq_accesses::cpu1.inst 447940407 # number of ReadReq accesses(hits+misses) 1631system.cpu1.icache.ReadReq_accesses::total 447940407 # number of ReadReq accesses(hits+misses) 1632system.cpu1.icache.demand_accesses::cpu1.inst 447940407 # number of demand (read+write) accesses 1633system.cpu1.icache.demand_accesses::total 447940407 # number of demand (read+write) accesses 1634system.cpu1.icache.overall_accesses::cpu1.inst 447940407 # number of overall (read+write) accesses 1635system.cpu1.icache.overall_accesses::total 447940407 # number of overall (read+write) accesses 1636system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.012919 # miss rate for ReadReq accesses 1637system.cpu1.icache.ReadReq_miss_rate::total 0.012919 # miss rate for ReadReq accesses 1638system.cpu1.icache.demand_miss_rate::cpu1.inst 0.012919 # miss rate for demand accesses 1639system.cpu1.icache.demand_miss_rate::total 0.012919 # miss rate for demand accesses 1640system.cpu1.icache.overall_miss_rate::cpu1.inst 0.012919 # miss rate for overall accesses 1641system.cpu1.icache.overall_miss_rate::total 0.012919 # miss rate for overall accesses 1642system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8649.015752 # average ReadReq miss latency 1643system.cpu1.icache.ReadReq_avg_miss_latency::total 8649.015752 # average ReadReq miss latency 1644system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8649.015752 # average overall miss latency 1645system.cpu1.icache.demand_avg_miss_latency::total 8649.015752 # average overall miss latency 1646system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8649.015752 # average overall miss latency 1647system.cpu1.icache.overall_avg_miss_latency::total 8649.015752 # average overall miss latency 1648system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1649system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1650system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1651system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1652system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1653system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1654system.cpu1.icache.fast_writes 0 # number of fast writes performed 1655system.cpu1.icache.cache_copies 0 # number of cache copies performed 1656system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5787039 # number of ReadReq MSHR misses 1657system.cpu1.icache.ReadReq_mshr_misses::total 5787039 # number of ReadReq MSHR misses 1658system.cpu1.icache.demand_mshr_misses::cpu1.inst 5787039 # number of demand (read+write) MSHR misses 1659system.cpu1.icache.demand_mshr_misses::total 5787039 # number of demand (read+write) MSHR misses 1660system.cpu1.icache.overall_mshr_misses::cpu1.inst 5787039 # number of overall MSHR misses 1661system.cpu1.icache.overall_mshr_misses::total 5787039 # number of overall MSHR misses 1662system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 41368714588 # number of ReadReq MSHR miss cycles 1663system.cpu1.icache.ReadReq_mshr_miss_latency::total 41368714588 # number of ReadReq MSHR miss cycles 1664system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 41368714588 # number of demand (read+write) MSHR miss cycles 1665system.cpu1.icache.demand_mshr_miss_latency::total 41368714588 # number of demand (read+write) MSHR miss cycles 1666system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 41368714588 # number of overall MSHR miss cycles 1667system.cpu1.icache.overall_mshr_miss_latency::total 41368714588 # number of overall MSHR miss cycles 1668system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9075250 # number of ReadReq MSHR uncacheable cycles 1669system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9075250 # number of ReadReq MSHR uncacheable cycles 1670system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9075250 # number of overall MSHR uncacheable cycles 1671system.cpu1.icache.overall_mshr_uncacheable_latency::total 9075250 # number of overall MSHR uncacheable cycles 1672system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.012919 # mshr miss rate for ReadReq accesses 1673system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.012919 # mshr miss rate for ReadReq accesses 1674system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.012919 # mshr miss rate for demand accesses 1675system.cpu1.icache.demand_mshr_miss_rate::total 0.012919 # mshr miss rate for demand accesses 1676system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.012919 # mshr miss rate for overall accesses 1677system.cpu1.icache.overall_mshr_miss_rate::total 0.012919 # mshr miss rate for overall accesses 1678system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7148.511456 # average ReadReq mshr miss latency 1679system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7148.511456 # average ReadReq mshr miss latency 1680system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7148.511456 # average overall mshr miss latency 1681system.cpu1.icache.demand_avg_mshr_miss_latency::total 7148.511456 # average overall mshr miss latency 1682system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7148.511456 # average overall mshr miss latency 1683system.cpu1.icache.overall_avg_mshr_miss_latency::total 7148.511456 # average overall mshr miss latency 1684system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1685system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1686system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1687system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1688system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1689system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 55302288 # number of hwpf identified 1690system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 976452 # number of hwpf that were already in mshr 1691system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 51578919 # number of hwpf that were already in the cache 1692system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 9282 # number of hwpf that were already in the prefetch queue 1693system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 1694system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 584 # number of hwpf removed because MSHR allocated 1695system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 2737051 # number of hwpf issued 1696system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 4557576 # number of hwpf spanning a virtual page 1697system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 1698system.cpu1.l2cache.tags.replacements 3265247 # number of replacements 1699system.cpu1.l2cache.tags.tagsinuse 13732.593717 # Cycle average of tags in use 1700system.cpu1.l2cache.tags.total_refs 11929802 # Total number of references to valid blocks. 1701system.cpu1.l2cache.tags.sampled_refs 3281353 # Sample count of references to valid blocks. 1702system.cpu1.l2cache.tags.avg_refs 3.635635 # Average number of references to valid blocks. 1703system.cpu1.l2cache.tags.warmup_cycle 9719592338000 # Cycle when the warmup percentage was hit. 1704system.cpu1.l2cache.tags.occ_blocks::writebacks 3548.297662 # Average occupied blocks per requestor 1705system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 58.425503 # Average occupied blocks per requestor 1706system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 65.675774 # Average occupied blocks per requestor 1707system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 758.406628 # Average occupied blocks per requestor 1708system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2477.157386 # Average occupied blocks per requestor 1709system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6824.630764 # Average occupied blocks per requestor 1710system.cpu1.l2cache.tags.occ_percent::writebacks 0.216571 # Average percentage of cache occupancy 1711system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003566 # Average percentage of cache occupancy 1712system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004009 # Average percentage of cache occupancy 1713system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.046289 # Average percentage of cache occupancy 1714system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.151194 # Average percentage of cache occupancy 1715system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.416542 # Average percentage of cache occupancy 1716system.cpu1.l2cache.tags.occ_percent::total 0.838171 # Average percentage of cache occupancy 1717system.cpu1.l2cache.tags.occ_task_id_blocks::1022 8592 # Occupied blocks per task id 1718system.cpu1.l2cache.tags.occ_task_id_blocks::1023 40 # Occupied blocks per task id 1719system.cpu1.l2cache.tags.occ_task_id_blocks::1024 7474 # Occupied blocks per task id 1720system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 93 # Occupied blocks per task id 1721system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 541 # Occupied blocks per task id 1722system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2721 # Occupied blocks per task id 1723system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 4842 # Occupied blocks per task id 1724system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 395 # Occupied blocks per task id 1725system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 1726system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 15 # Occupied blocks per task id 1727system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id 1728system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 1729system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 1730system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 810 # Occupied blocks per task id 1731system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 3409 # Occupied blocks per task id 1732system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2963 # Occupied blocks per task id 1733system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 229 # Occupied blocks per task id 1734system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.524414 # Percentage of cache occupancy per task id 1735system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002441 # Percentage of cache occupancy per task id 1736system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.456177 # Percentage of cache occupancy per task id 1737system.cpu1.l2cache.tags.tag_accesses 249010603 # Number of tag accesses 1738system.cpu1.l2cache.tags.data_accesses 249010603 # Number of data accesses 1739system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 204488 # number of ReadReq hits 1740system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 158918 # number of ReadReq hits 1741system.cpu1.l2cache.ReadReq_hits::cpu1.inst 5602514 # number of ReadReq hits 1742system.cpu1.l2cache.ReadReq_hits::cpu1.data 2695724 # number of ReadReq hits 1743system.cpu1.l2cache.ReadReq_hits::total 8661644 # number of ReadReq hits 1744system.cpu1.l2cache.Writeback_hits::writebacks 3397427 # number of Writeback hits 1745system.cpu1.l2cache.Writeback_hits::total 3397427 # number of Writeback hits 1746system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 491178 # number of WriteInvalidateReq hits 1747system.cpu1.l2cache.WriteInvalidateReq_hits::total 491178 # number of WriteInvalidateReq hits 1748system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 77109 # number of UpgradeReq hits 1749system.cpu1.l2cache.UpgradeReq_hits::total 77109 # number of UpgradeReq hits 1750system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 35497 # number of SCUpgradeReq hits 1751system.cpu1.l2cache.SCUpgradeReq_hits::total 35497 # number of SCUpgradeReq hits 1752system.cpu1.l2cache.ReadExReq_hits::cpu1.data 899510 # number of ReadExReq hits 1753system.cpu1.l2cache.ReadExReq_hits::total 899510 # number of ReadExReq hits 1754system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 204488 # number of demand (read+write) hits 1755system.cpu1.l2cache.demand_hits::cpu1.itb.walker 158918 # number of demand (read+write) hits 1756system.cpu1.l2cache.demand_hits::cpu1.inst 5602514 # number of demand (read+write) hits 1757system.cpu1.l2cache.demand_hits::cpu1.data 3595234 # number of demand (read+write) hits 1758system.cpu1.l2cache.demand_hits::total 9561154 # number of demand (read+write) hits 1759system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 204488 # number of overall hits 1760system.cpu1.l2cache.overall_hits::cpu1.itb.walker 158918 # number of overall hits 1761system.cpu1.l2cache.overall_hits::cpu1.inst 5602514 # number of overall hits 1762system.cpu1.l2cache.overall_hits::cpu1.data 3595234 # number of overall hits 1763system.cpu1.l2cache.overall_hits::total 9561154 # number of overall hits 1764system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11072 # number of ReadReq misses 1765system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9747 # number of ReadReq misses 1766system.cpu1.l2cache.ReadReq_misses::cpu1.inst 184525 # number of ReadReq misses 1767system.cpu1.l2cache.ReadReq_misses::cpu1.data 930664 # number of ReadReq misses 1768system.cpu1.l2cache.ReadReq_misses::total 1136008 # number of ReadReq misses 1769system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 58187 # number of WriteInvalidateReq misses 1770system.cpu1.l2cache.WriteInvalidateReq_misses::total 58187 # number of WriteInvalidateReq misses 1771system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 111708 # number of UpgradeReq misses 1772system.cpu1.l2cache.UpgradeReq_misses::total 111708 # number of UpgradeReq misses 1773system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 150027 # number of SCUpgradeReq misses 1774system.cpu1.l2cache.SCUpgradeReq_misses::total 150027 # number of SCUpgradeReq misses 1775system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 4 # number of SCUpgradeFailReq misses 1776system.cpu1.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses 1777system.cpu1.l2cache.ReadExReq_misses::cpu1.data 196006 # number of ReadExReq misses 1778system.cpu1.l2cache.ReadExReq_misses::total 196006 # number of ReadExReq misses 1779system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11072 # number of demand (read+write) misses 1780system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9747 # number of demand (read+write) misses 1781system.cpu1.l2cache.demand_misses::cpu1.inst 184525 # number of demand (read+write) misses 1782system.cpu1.l2cache.demand_misses::cpu1.data 1126670 # number of demand (read+write) misses 1783system.cpu1.l2cache.demand_misses::total 1332014 # number of demand (read+write) misses 1784system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11072 # number of overall misses 1785system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9747 # number of overall misses 1786system.cpu1.l2cache.overall_misses::cpu1.inst 184525 # number of overall misses 1787system.cpu1.l2cache.overall_misses::cpu1.data 1126670 # number of overall misses 1788system.cpu1.l2cache.overall_misses::total 1332014 # number of overall misses 1789system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 339143470 # number of ReadReq miss cycles 1790system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 328936960 # number of ReadReq miss cycles 1791system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 4835548618 # number of ReadReq miss cycles 1792system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 27845292450 # number of ReadReq miss cycles 1793system.cpu1.l2cache.ReadReq_miss_latency::total 33348921498 # number of ReadReq miss cycles 1794system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 1715319866 # number of WriteInvalidateReq miss cycles 1795system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 1715319866 # number of WriteInvalidateReq miss cycles 1796system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2196780170 # number of UpgradeReq miss cycles 1797system.cpu1.l2cache.UpgradeReq_miss_latency::total 2196780170 # number of UpgradeReq miss cycles 1798system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3055684059 # number of SCUpgradeReq miss cycles 1799system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3055684059 # number of SCUpgradeReq miss cycles 1800system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1008500 # number of SCUpgradeFailReq miss cycles 1801system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1008500 # number of SCUpgradeFailReq miss cycles 1802system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 6932150792 # number of ReadExReq miss cycles 1803system.cpu1.l2cache.ReadExReq_miss_latency::total 6932150792 # number of ReadExReq miss cycles 1804system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 339143470 # number of demand (read+write) miss cycles 1805system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 328936960 # number of demand (read+write) miss cycles 1806system.cpu1.l2cache.demand_miss_latency::cpu1.inst 4835548618 # number of demand (read+write) miss cycles 1807system.cpu1.l2cache.demand_miss_latency::cpu1.data 34777443242 # number of demand (read+write) miss cycles 1808system.cpu1.l2cache.demand_miss_latency::total 40281072290 # number of demand (read+write) miss cycles 1809system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 339143470 # number of overall miss cycles 1810system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 328936960 # number of overall miss cycles 1811system.cpu1.l2cache.overall_miss_latency::cpu1.inst 4835548618 # number of overall miss cycles 1812system.cpu1.l2cache.overall_miss_latency::cpu1.data 34777443242 # number of overall miss cycles 1813system.cpu1.l2cache.overall_miss_latency::total 40281072290 # number of overall miss cycles 1814system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 215560 # number of ReadReq accesses(hits+misses) 1815system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 168665 # number of ReadReq accesses(hits+misses) 1816system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 5787039 # number of ReadReq accesses(hits+misses) 1817system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3626388 # number of ReadReq accesses(hits+misses) 1818system.cpu1.l2cache.ReadReq_accesses::total 9797652 # number of ReadReq accesses(hits+misses) 1819system.cpu1.l2cache.Writeback_accesses::writebacks 3397427 # number of Writeback accesses(hits+misses) 1820system.cpu1.l2cache.Writeback_accesses::total 3397427 # number of Writeback accesses(hits+misses) 1821system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 549365 # number of WriteInvalidateReq accesses(hits+misses) 1822system.cpu1.l2cache.WriteInvalidateReq_accesses::total 549365 # number of WriteInvalidateReq accesses(hits+misses) 1823system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 188817 # number of UpgradeReq accesses(hits+misses) 1824system.cpu1.l2cache.UpgradeReq_accesses::total 188817 # number of UpgradeReq accesses(hits+misses) 1825system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 185524 # number of SCUpgradeReq accesses(hits+misses) 1826system.cpu1.l2cache.SCUpgradeReq_accesses::total 185524 # number of SCUpgradeReq accesses(hits+misses) 1827system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 4 # number of SCUpgradeFailReq accesses(hits+misses) 1828system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) 1829system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1095516 # number of ReadExReq accesses(hits+misses) 1830system.cpu1.l2cache.ReadExReq_accesses::total 1095516 # number of ReadExReq accesses(hits+misses) 1831system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 215560 # number of demand (read+write) accesses 1832system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 168665 # number of demand (read+write) accesses 1833system.cpu1.l2cache.demand_accesses::cpu1.inst 5787039 # number of demand (read+write) accesses 1834system.cpu1.l2cache.demand_accesses::cpu1.data 4721904 # number of demand (read+write) accesses 1835system.cpu1.l2cache.demand_accesses::total 10893168 # number of demand (read+write) accesses 1836system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 215560 # number of overall (read+write) accesses 1837system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 168665 # number of overall (read+write) accesses 1838system.cpu1.l2cache.overall_accesses::cpu1.inst 5787039 # number of overall (read+write) accesses 1839system.cpu1.l2cache.overall_accesses::cpu1.data 4721904 # number of overall (read+write) accesses 1840system.cpu1.l2cache.overall_accesses::total 10893168 # number of overall (read+write) accesses 1841system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.051364 # miss rate for ReadReq accesses 1842system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.057789 # miss rate for ReadReq accesses 1843system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.031886 # miss rate for ReadReq accesses 1844system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.256637 # miss rate for ReadReq accesses 1845system.cpu1.l2cache.ReadReq_miss_rate::total 0.115947 # miss rate for ReadReq accesses 1846system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.105917 # miss rate for WriteInvalidateReq accesses 1847system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.105917 # miss rate for WriteInvalidateReq accesses 1848system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.591620 # miss rate for UpgradeReq accesses 1849system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.591620 # miss rate for UpgradeReq accesses 1850system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.808666 # miss rate for SCUpgradeReq accesses 1851system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.808666 # miss rate for SCUpgradeReq accesses 1852system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 1853system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1854system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.178917 # miss rate for ReadExReq accesses 1855system.cpu1.l2cache.ReadExReq_miss_rate::total 0.178917 # miss rate for ReadExReq accesses 1856system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.051364 # miss rate for demand accesses 1857system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.057789 # miss rate for demand accesses 1858system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.031886 # miss rate for demand accesses 1859system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.238605 # miss rate for demand accesses 1860system.cpu1.l2cache.demand_miss_rate::total 0.122280 # miss rate for demand accesses 1861system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.051364 # miss rate for overall accesses 1862system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.057789 # miss rate for overall accesses 1863system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.031886 # miss rate for overall accesses 1864system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.238605 # miss rate for overall accesses 1865system.cpu1.l2cache.overall_miss_rate::total 0.122280 # miss rate for overall accesses 1866system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 30630.732478 # average ReadReq miss latency 1867system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 33747.507951 # average ReadReq miss latency 1868system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 26205.384734 # average ReadReq miss latency 1869system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 29919.812575 # average ReadReq miss latency 1870system.cpu1.l2cache.ReadReq_avg_miss_latency::total 29356.238247 # average ReadReq miss latency 1871system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 29479.434685 # average WriteInvalidateReq miss latency 1872system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 29479.434685 # average WriteInvalidateReq miss latency 1873system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19665.379113 # average UpgradeReq miss latency 1874system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19665.379113 # average UpgradeReq miss latency 1875system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20367.560899 # average SCUpgradeReq miss latency 1876system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20367.560899 # average SCUpgradeReq miss latency 1877system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 252125 # average SCUpgradeFailReq miss latency 1878system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 252125 # average SCUpgradeFailReq miss latency 1879system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 35367.033621 # average ReadExReq miss latency 1880system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 35367.033621 # average ReadExReq miss latency 1881system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 30630.732478 # average overall miss latency 1882system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 33747.507951 # average overall miss latency 1883system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 26205.384734 # average overall miss latency 1884system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 30867.461850 # average overall miss latency 1885system.cpu1.l2cache.demand_avg_miss_latency::total 30240.727417 # average overall miss latency 1886system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 30630.732478 # average overall miss latency 1887system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 33747.507951 # average overall miss latency 1888system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 26205.384734 # average overall miss latency 1889system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 30867.461850 # average overall miss latency 1890system.cpu1.l2cache.overall_avg_miss_latency::total 30240.727417 # average overall miss latency 1891system.cpu1.l2cache.blocked_cycles::no_mshrs 13039 # number of cycles access was blocked 1892system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1893system.cpu1.l2cache.blocked::no_mshrs 326 # number of cycles access was blocked 1894system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1895system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 39.996933 # average number of cycles each access was blocked 1896system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1897system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1898system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 1899system.cpu1.l2cache.writebacks::writebacks 1118692 # number of writebacks 1900system.cpu1.l2cache.writebacks::total 1118692 # number of writebacks 1901system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 28597 # number of ReadReq MSHR hits 1902system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 597 # number of ReadReq MSHR hits 1903system.cpu1.l2cache.ReadReq_mshr_hits::total 29194 # number of ReadReq MSHR hits 1904system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data 9933 # number of WriteInvalidateReq MSHR hits 1905system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total 9933 # number of WriteInvalidateReq MSHR hits 1906system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 2789 # number of ReadExReq MSHR hits 1907system.cpu1.l2cache.ReadExReq_mshr_hits::total 2789 # number of ReadExReq MSHR hits 1908system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 28597 # number of demand (read+write) MSHR hits 1909system.cpu1.l2cache.demand_mshr_hits::cpu1.data 3386 # number of demand (read+write) MSHR hits 1910system.cpu1.l2cache.demand_mshr_hits::total 31983 # number of demand (read+write) MSHR hits 1911system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 28597 # number of overall MSHR hits 1912system.cpu1.l2cache.overall_mshr_hits::cpu1.data 3386 # number of overall MSHR hits 1913system.cpu1.l2cache.overall_mshr_hits::total 31983 # number of overall MSHR hits 1914system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 11072 # number of ReadReq MSHR misses 1915system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9747 # number of ReadReq MSHR misses 1916system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 155928 # number of ReadReq MSHR misses 1917system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 930067 # number of ReadReq MSHR misses 1918system.cpu1.l2cache.ReadReq_mshr_misses::total 1106814 # number of ReadReq MSHR misses 1919system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 2736889 # number of HardPFReq MSHR misses 1920system.cpu1.l2cache.HardPFReq_mshr_misses::total 2736889 # number of HardPFReq MSHR misses 1921system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 48254 # number of WriteInvalidateReq MSHR misses 1922system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 48254 # number of WriteInvalidateReq MSHR misses 1923system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 111708 # number of UpgradeReq MSHR misses 1924system.cpu1.l2cache.UpgradeReq_mshr_misses::total 111708 # number of UpgradeReq MSHR misses 1925system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 150027 # number of SCUpgradeReq MSHR misses 1926system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 150027 # number of SCUpgradeReq MSHR misses 1927system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 4 # number of SCUpgradeFailReq MSHR misses 1928system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses 1929system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 193217 # number of ReadExReq MSHR misses 1930system.cpu1.l2cache.ReadExReq_mshr_misses::total 193217 # number of ReadExReq MSHR misses 1931system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 11072 # number of demand (read+write) MSHR misses 1932system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9747 # number of demand (read+write) MSHR misses 1933system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 155928 # number of demand (read+write) MSHR misses 1934system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1123284 # number of demand (read+write) MSHR misses 1935system.cpu1.l2cache.demand_mshr_misses::total 1300031 # number of demand (read+write) MSHR misses 1936system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 11072 # number of overall MSHR misses 1937system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9747 # number of overall MSHR misses 1938system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 155928 # number of overall MSHR misses 1939system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1123284 # number of overall MSHR misses 1940system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 2736889 # number of overall MSHR misses 1941system.cpu1.l2cache.overall_mshr_misses::total 4036920 # number of overall MSHR misses 1942system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 261197050 # number of ReadReq MSHR miss cycles 1943system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 260217544 # number of ReadReq MSHR miss cycles 1944system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 3279178209 # number of ReadReq MSHR miss cycles 1945system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 21257509518 # number of ReadReq MSHR miss cycles 1946system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 25058102321 # number of ReadReq MSHR miss cycles 1947system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 69697772473 # number of HardPFReq MSHR miss cycles 1948system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 69697772473 # number of HardPFReq MSHR miss cycles 1949system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 739531321 # number of WriteInvalidateReq MSHR miss cycles 1950system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 739531321 # number of WriteInvalidateReq MSHR miss cycles 1951system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 1851219395 # number of UpgradeReq MSHR miss cycles 1952system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 1851219395 # number of UpgradeReq MSHR miss cycles 1953system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2073994150 # number of SCUpgradeReq MSHR miss cycles 1954system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2073994150 # number of SCUpgradeReq MSHR miss cycles 1955system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 805500 # number of SCUpgradeFailReq MSHR miss cycles 1956system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 805500 # number of SCUpgradeFailReq MSHR miss cycles 1957system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 5288290642 # number of ReadExReq MSHR miss cycles 1958system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 5288290642 # number of ReadExReq MSHR miss cycles 1959system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 261197050 # number of demand (read+write) MSHR miss cycles 1960system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 260217544 # number of demand (read+write) MSHR miss cycles 1961system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 3279178209 # number of demand (read+write) MSHR miss cycles 1962system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 26545800160 # number of demand (read+write) MSHR miss cycles 1963system.cpu1.l2cache.demand_mshr_miss_latency::total 30346392963 # number of demand (read+write) MSHR miss cycles 1964system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 261197050 # number of overall MSHR miss cycles 1965system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 260217544 # number of overall MSHR miss cycles 1966system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 3279178209 # number of overall MSHR miss cycles 1967system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 26545800160 # number of overall MSHR miss cycles 1968system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 69697772473 # number of overall MSHR miss cycles 1969system.cpu1.l2cache.overall_mshr_miss_latency::total 100044165436 # number of overall MSHR miss cycles 1970system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8211750 # number of ReadReq MSHR uncacheable cycles 1971system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3785003026 # number of ReadReq MSHR uncacheable cycles 1972system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3793214776 # number of ReadReq MSHR uncacheable cycles 1973system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 3642241027 # number of WriteReq MSHR uncacheable cycles 1974system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3642241027 # number of WriteReq MSHR uncacheable cycles 1975system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8211750 # number of overall MSHR uncacheable cycles 1976system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 7427244053 # number of overall MSHR uncacheable cycles 1977system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 7435455803 # number of overall MSHR uncacheable cycles 1978system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.051364 # mshr miss rate for ReadReq accesses 1979system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.057789 # mshr miss rate for ReadReq accesses 1980system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.026944 # mshr miss rate for ReadReq accesses 1981system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.256472 # mshr miss rate for ReadReq accesses 1982system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.112967 # mshr miss rate for ReadReq accesses 1983system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1984system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1985system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.087836 # mshr miss rate for WriteInvalidateReq accesses 1986system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.087836 # mshr miss rate for WriteInvalidateReq accesses 1987system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.591620 # mshr miss rate for UpgradeReq accesses 1988system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.591620 # mshr miss rate for UpgradeReq accesses 1989system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.808666 # mshr miss rate for SCUpgradeReq accesses 1990system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.808666 # mshr miss rate for SCUpgradeReq accesses 1991system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1992system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1993system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.176371 # mshr miss rate for ReadExReq accesses 1994system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.176371 # mshr miss rate for ReadExReq accesses 1995system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.051364 # mshr miss rate for demand accesses 1996system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.057789 # mshr miss rate for demand accesses 1997system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026944 # mshr miss rate for demand accesses 1998system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.237888 # mshr miss rate for demand accesses 1999system.cpu1.l2cache.demand_mshr_miss_rate::total 0.119344 # mshr miss rate for demand accesses 2000system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.051364 # mshr miss rate for overall accesses 2001system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.057789 # mshr miss rate for overall accesses 2002system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026944 # mshr miss rate for overall accesses 2003system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.237888 # mshr miss rate for overall accesses 2004system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2005system.cpu1.l2cache.overall_mshr_miss_rate::total 0.370592 # mshr miss rate for overall accesses 2006system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 23590.774025 # average ReadReq mshr miss latency 2007system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 26697.193393 # average ReadReq mshr miss latency 2008system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21030.079325 # average ReadReq mshr miss latency 2009system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 22855.890509 # average ReadReq mshr miss latency 2010system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 22639.849443 # average ReadReq mshr miss latency 2011system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 25466.057437 # average HardPFReq mshr miss latency 2012system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 25466.057437 # average HardPFReq mshr miss latency 2013system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 15325.803477 # average WriteInvalidateReq mshr miss latency 2014system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 15325.803477 # average WriteInvalidateReq mshr miss latency 2015system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16571.950039 # average UpgradeReq mshr miss latency 2016system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16571.950039 # average UpgradeReq mshr miss latency 2017system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13824.139322 # average SCUpgradeReq mshr miss latency 2018system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13824.139322 # average SCUpgradeReq mshr miss latency 2019system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 201375 # average SCUpgradeFailReq mshr miss latency 2020system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 201375 # average SCUpgradeFailReq mshr miss latency 2021system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 27369.696466 # average ReadExReq mshr miss latency 2022system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27369.696466 # average ReadExReq mshr miss latency 2023system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 23590.774025 # average overall mshr miss latency 2024system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 26697.193393 # average overall mshr miss latency 2025system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21030.079325 # average overall mshr miss latency 2026system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23632.313965 # average overall mshr miss latency 2027system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23342.822566 # average overall mshr miss latency 2028system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 23590.774025 # average overall mshr miss latency 2029system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 26697.193393 # average overall mshr miss latency 2030system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21030.079325 # average overall mshr miss latency 2031system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23632.313965 # average overall mshr miss latency 2032system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 25466.057437 # average overall mshr miss latency 2033system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24782.300723 # average overall mshr miss latency 2034system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2035system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2036system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2037system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2038system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2039system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2040system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2041system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2042system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2043system.cpu1.toL2Bus.trans_dist::ReadReq 13482596 # Transaction distribution 2044system.cpu1.toL2Bus.trans_dist::ReadResp 10019474 # Transaction distribution 2045system.cpu1.toL2Bus.trans_dist::WriteReq 22090 # Transaction distribution 2046system.cpu1.toL2Bus.trans_dist::WriteResp 22090 # Transaction distribution 2047system.cpu1.toL2Bus.trans_dist::Writeback 3397427 # Transaction distribution 2048system.cpu1.toL2Bus.trans_dist::HardPFReq 3948207 # Transaction distribution 2049system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 669175 # Transaction distribution 2050system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 549365 # Transaction distribution 2051system.cpu1.toL2Bus.trans_dist::UpgradeReq 394300 # Transaction distribution 2052system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 332875 # Transaction distribution 2053system.cpu1.toL2Bus.trans_dist::UpgradeResp 429984 # Transaction distribution 2054system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 28 # Transaction distribution 2055system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution 2056system.cpu1.toL2Bus.trans_dist::ReadExReq 1203009 # Transaction distribution 2057system.cpu1.toL2Bus.trans_dist::ReadExResp 1101184 # Transaction distribution 2058system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11574298 # Packet count per connected master and slave (bytes) 2059system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 14922836 # Packet count per connected master and slave (bytes) 2060system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 373561 # Packet count per connected master and slave (bytes) 2061system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 511408 # Packet count per connected master and slave (bytes) 2062system.cpu1.toL2Bus.pkt_count::total 27382103 # Packet count per connected master and slave (bytes) 2063system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 370370936 # Cumulative packet size per connected master and slave (bytes) 2064system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 560535931 # Cumulative packet size per connected master and slave (bytes) 2065system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1349320 # Cumulative packet size per connected master and slave (bytes) 2066system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1724480 # Cumulative packet size per connected master and slave (bytes) 2067system.cpu1.toL2Bus.pkt_size::total 933980667 # Cumulative packet size per connected master and slave (bytes) 2068system.cpu1.toL2Bus.snoops 8332859 # Total snoops (count) 2069system.cpu1.toL2Bus.snoop_fanout::samples 23404111 # Request fanout histogram 2070system.cpu1.toL2Bus.snoop_fanout::mean 5.344949 # Request fanout histogram 2071system.cpu1.toL2Bus.snoop_fanout::stdev 0.475352 # Request fanout histogram 2072system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2073system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2074system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 2075system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 2076system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 2077system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 2078system.cpu1.toL2Bus.snoop_fanout::5 15330876 65.51% 65.51% # Request fanout histogram 2079system.cpu1.toL2Bus.snoop_fanout::6 8073235 34.49% 100.00% # Request fanout histogram 2080system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2081system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 2082system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 2083system.cpu1.toL2Bus.snoop_fanout::total 23404111 # Request fanout histogram 2084system.cpu1.toL2Bus.reqLayer0.occupancy 11646725084 # Layer occupancy (ticks) 2085system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2086system.cpu1.toL2Bus.snoopLayer0.occupancy 158989494 # Layer occupancy (ticks) 2087system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2088system.cpu1.toL2Bus.respLayer0.occupancy 8682146940 # Layer occupancy (ticks) 2089system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2090system.cpu1.toL2Bus.respLayer1.occupancy 7623277083 # Layer occupancy (ticks) 2091system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2092system.cpu1.toL2Bus.respLayer2.occupancy 205120292 # Layer occupancy (ticks) 2093system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2094system.cpu1.toL2Bus.respLayer3.occupancy 296049290 # Layer occupancy (ticks) 2095system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2096system.iobus.trans_dist::ReadReq 40487 # Transaction distribution 2097system.iobus.trans_dist::ReadResp 40487 # Transaction distribution 2098system.iobus.trans_dist::WriteReq 137083 # Transaction distribution 2099system.iobus.trans_dist::WriteResp 30163 # Transaction distribution 2100system.iobus.trans_dist::WriteInvalidateResp 106920 # Transaction distribution 2101system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48390 # Packet count per connected master and slave (bytes) 2102system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2103system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2104system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2105system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2106system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2107system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2108system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2109system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2110system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2111system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29756 # Packet count per connected master and slave (bytes) 2112system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2113system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 2114system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2115system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 2116system.iobus.pkt_count_system.bridge.master::total 123480 # Packet count per connected master and slave (bytes) 2117system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231580 # Packet count per connected master and slave (bytes) 2118system.iobus.pkt_count_system.realview.ide.dma::total 231580 # Packet count per connected master and slave (bytes) 2119system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2120system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 2121system.iobus.pkt_count::total 355140 # Packet count per connected master and slave (bytes) 2122system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48410 # Cumulative packet size per connected master and slave (bytes) 2123system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2124system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2125system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2126system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2127system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2128system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2129system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2130system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2131system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2132system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17674 # Cumulative packet size per connected master and slave (bytes) 2133system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 2134system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 2135system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 2136system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 2137system.iobus.pkt_size_system.bridge.master::total 156518 # Cumulative packet size per connected master and slave (bytes) 2138system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7351088 # Cumulative packet size per connected master and slave (bytes) 2139system.iobus.pkt_size_system.realview.ide.dma::total 7351088 # Cumulative packet size per connected master and slave (bytes) 2140system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2141system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 2142system.iobus.pkt_size::total 7509692 # Cumulative packet size per connected master and slave (bytes) 2143system.iobus.reqLayer0.occupancy 36789000 # Layer occupancy (ticks) 2144system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2145system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 2146system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2147system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 2148system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2149system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 2150system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2151system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 2152system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2153system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 2154system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2155system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 2156system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2157system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 2158system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2159system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 2160system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2161system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 2162system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2163system.iobus.reqLayer23.occupancy 22103000 # Layer occupancy (ticks) 2164system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2165system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 2166system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2167system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 2168system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2169system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 2170system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 2171system.iobus.reqLayer27.occupancy 1044839337 # Layer occupancy (ticks) 2172system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2173system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2174system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 2175system.iobus.respLayer0.occupancy 93320000 # Layer occupancy (ticks) 2176system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2177system.iobus.respLayer3.occupancy 179372271 # Layer occupancy (ticks) 2178system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2179system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) 2180system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 2181system.iocache.tags.replacements 115786 # number of replacements 2182system.iocache.tags.tagsinuse 11.223287 # Cycle average of tags in use 2183system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 2184system.iocache.tags.sampled_refs 115802 # Sample count of references to valid blocks. 2185system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 2186system.iocache.tags.warmup_cycle 9123835798000 # Cycle when the warmup percentage was hit. 2187system.iocache.tags.occ_blocks::realview.ethernet 7.412555 # Average occupied blocks per requestor 2188system.iocache.tags.occ_blocks::realview.ide 3.810732 # Average occupied blocks per requestor 2189system.iocache.tags.occ_percent::realview.ethernet 0.463285 # Average percentage of cache occupancy 2190system.iocache.tags.occ_percent::realview.ide 0.238171 # Average percentage of cache occupancy 2191system.iocache.tags.occ_percent::total 0.701455 # Average percentage of cache occupancy 2192system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2193system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2194system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2195system.iocache.tags.tag_accesses 1042467 # Number of tag accesses 2196system.iocache.tags.data_accesses 1042467 # Number of data accesses 2197system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2198system.iocache.ReadReq_misses::realview.ide 8870 # number of ReadReq misses 2199system.iocache.ReadReq_misses::total 8907 # number of ReadReq misses 2200system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2201system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2202system.iocache.WriteInvalidateReq_misses::realview.ide 106920 # number of WriteInvalidateReq misses 2203system.iocache.WriteInvalidateReq_misses::total 106920 # number of WriteInvalidateReq misses 2204system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 2205system.iocache.demand_misses::realview.ide 8870 # number of demand (read+write) misses 2206system.iocache.demand_misses::total 8910 # number of demand (read+write) misses 2207system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 2208system.iocache.overall_misses::realview.ide 8870 # number of overall misses 2209system.iocache.overall_misses::total 8910 # number of overall misses 2210system.iocache.ReadReq_miss_latency::realview.ethernet 5627000 # number of ReadReq miss cycles 2211system.iocache.ReadReq_miss_latency::realview.ide 1958941092 # number of ReadReq miss cycles 2212system.iocache.ReadReq_miss_latency::total 1964568092 # number of ReadReq miss cycles 2213system.iocache.WriteReq_miss_latency::realview.ethernet 357000 # number of WriteReq miss cycles 2214system.iocache.WriteReq_miss_latency::total 357000 # number of WriteReq miss cycles 2215system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28897474974 # number of WriteInvalidateReq miss cycles 2216system.iocache.WriteInvalidateReq_miss_latency::total 28897474974 # number of WriteInvalidateReq miss cycles 2217system.iocache.demand_miss_latency::realview.ethernet 5984000 # number of demand (read+write) miss cycles 2218system.iocache.demand_miss_latency::realview.ide 1958941092 # number of demand (read+write) miss cycles 2219system.iocache.demand_miss_latency::total 1964925092 # number of demand (read+write) miss cycles 2220system.iocache.overall_miss_latency::realview.ethernet 5984000 # number of overall miss cycles 2221system.iocache.overall_miss_latency::realview.ide 1958941092 # number of overall miss cycles 2222system.iocache.overall_miss_latency::total 1964925092 # number of overall miss cycles 2223system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 2224system.iocache.ReadReq_accesses::realview.ide 8870 # number of ReadReq accesses(hits+misses) 2225system.iocache.ReadReq_accesses::total 8907 # number of ReadReq accesses(hits+misses) 2226system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2227system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2228system.iocache.WriteInvalidateReq_accesses::realview.ide 106920 # number of WriteInvalidateReq accesses(hits+misses) 2229system.iocache.WriteInvalidateReq_accesses::total 106920 # number of WriteInvalidateReq accesses(hits+misses) 2230system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 2231system.iocache.demand_accesses::realview.ide 8870 # number of demand (read+write) accesses 2232system.iocache.demand_accesses::total 8910 # number of demand (read+write) accesses 2233system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 2234system.iocache.overall_accesses::realview.ide 8870 # number of overall (read+write) accesses 2235system.iocache.overall_accesses::total 8910 # number of overall (read+write) accesses 2236system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2237system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2238system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2239system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2240system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2241system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 2242system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 2243system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2244system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2245system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2246system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2247system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2248system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2249system.iocache.ReadReq_avg_miss_latency::realview.ethernet 152081.081081 # average ReadReq miss latency 2250system.iocache.ReadReq_avg_miss_latency::realview.ide 220850.179481 # average ReadReq miss latency 2251system.iocache.ReadReq_avg_miss_latency::total 220564.510161 # average ReadReq miss latency 2252system.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency 2253system.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency 2254system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270271.932043 # average WriteInvalidateReq miss latency 2255system.iocache.WriteInvalidateReq_avg_miss_latency::total 270271.932043 # average WriteInvalidateReq miss latency 2256system.iocache.demand_avg_miss_latency::realview.ethernet 149600 # average overall miss latency 2257system.iocache.demand_avg_miss_latency::realview.ide 220850.179481 # average overall miss latency 2258system.iocache.demand_avg_miss_latency::total 220530.313356 # average overall miss latency 2259system.iocache.overall_avg_miss_latency::realview.ethernet 149600 # average overall miss latency 2260system.iocache.overall_avg_miss_latency::realview.ide 220850.179481 # average overall miss latency 2261system.iocache.overall_avg_miss_latency::total 220530.313356 # average overall miss latency 2262system.iocache.blocked_cycles::no_mshrs 225288 # number of cycles access was blocked 2263system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2264system.iocache.blocked::no_mshrs 27401 # number of cycles access was blocked 2265system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2266system.iocache.avg_blocked_cycles::no_mshrs 8.221890 # average number of cycles each access was blocked 2267system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2268system.iocache.fast_writes 0 # number of fast writes performed 2269system.iocache.cache_copies 0 # number of cache copies performed 2270system.iocache.writebacks::writebacks 106886 # number of writebacks 2271system.iocache.writebacks::total 106886 # number of writebacks 2272system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 2273system.iocache.ReadReq_mshr_misses::realview.ide 8870 # number of ReadReq MSHR misses 2274system.iocache.ReadReq_mshr_misses::total 8907 # number of ReadReq MSHR misses 2275system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2276system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2277system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106920 # number of WriteInvalidateReq MSHR misses 2278system.iocache.WriteInvalidateReq_mshr_misses::total 106920 # number of WriteInvalidateReq MSHR misses 2279system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 2280system.iocache.demand_mshr_misses::realview.ide 8870 # number of demand (read+write) MSHR misses 2281system.iocache.demand_mshr_misses::total 8910 # number of demand (read+write) MSHR misses 2282system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 2283system.iocache.overall_mshr_misses::realview.ide 8870 # number of overall MSHR misses 2284system.iocache.overall_mshr_misses::total 8910 # number of overall MSHR misses 2285system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3703000 # number of ReadReq MSHR miss cycles 2286system.iocache.ReadReq_mshr_miss_latency::realview.ide 1497575112 # number of ReadReq MSHR miss cycles 2287system.iocache.ReadReq_mshr_miss_latency::total 1501278112 # number of ReadReq MSHR miss cycles 2288system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 2289system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 2290system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23337113496 # number of WriteInvalidateReq MSHR miss cycles 2291system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23337113496 # number of WriteInvalidateReq MSHR miss cycles 2292system.iocache.demand_mshr_miss_latency::realview.ethernet 3904000 # number of demand (read+write) MSHR miss cycles 2293system.iocache.demand_mshr_miss_latency::realview.ide 1497575112 # number of demand (read+write) MSHR miss cycles 2294system.iocache.demand_mshr_miss_latency::total 1501479112 # number of demand (read+write) MSHR miss cycles 2295system.iocache.overall_mshr_miss_latency::realview.ethernet 3904000 # number of overall MSHR miss cycles 2296system.iocache.overall_mshr_miss_latency::realview.ide 1497575112 # number of overall MSHR miss cycles 2297system.iocache.overall_mshr_miss_latency::total 1501479112 # number of overall MSHR miss cycles 2298system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2299system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2300system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2301system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2302system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2303system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 2304system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 2305system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 2306system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2307system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2308system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 2309system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2310system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2311system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 100081.081081 # average ReadReq mshr miss latency 2312system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 168835.976550 # average ReadReq mshr miss latency 2313system.iocache.ReadReq_avg_mshr_miss_latency::total 168550.366229 # average ReadReq mshr miss latency 2314system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 2315system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 2316system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218267.054770 # average WriteInvalidateReq mshr miss latency 2317system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218267.054770 # average WriteInvalidateReq mshr miss latency 2318system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 97600 # average overall mshr miss latency 2319system.iocache.demand_avg_mshr_miss_latency::realview.ide 168835.976550 # average overall mshr miss latency 2320system.iocache.demand_avg_mshr_miss_latency::total 168516.174186 # average overall mshr miss latency 2321system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 97600 # average overall mshr miss latency 2322system.iocache.overall_avg_mshr_miss_latency::realview.ide 168835.976550 # average overall mshr miss latency 2323system.iocache.overall_avg_mshr_miss_latency::total 168516.174186 # average overall mshr miss latency 2324system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2325system.l2c.tags.replacements 1310456 # number of replacements 2326system.l2c.tags.tagsinuse 64677.337118 # Cycle average of tags in use 2327system.l2c.tags.total_refs 7257968 # Total number of references to valid blocks. 2328system.l2c.tags.sampled_refs 1373726 # Sample count of references to valid blocks. 2329system.l2c.tags.avg_refs 5.283418 # Average number of references to valid blocks. 2330system.l2c.tags.warmup_cycle 5621833500 # Cycle when the warmup percentage was hit. 2331system.l2c.tags.occ_blocks::writebacks 9998.305247 # Average occupied blocks per requestor 2332system.l2c.tags.occ_blocks::cpu0.dtb.walker 56.991260 # Average occupied blocks per requestor 2333system.l2c.tags.occ_blocks::cpu0.itb.walker 77.146603 # Average occupied blocks per requestor 2334system.l2c.tags.occ_blocks::cpu0.inst 791.679733 # Average occupied blocks per requestor 2335system.l2c.tags.occ_blocks::cpu0.data 4513.780403 # Average occupied blocks per requestor 2336system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 23818.675732 # Average occupied blocks per requestor 2337system.l2c.tags.occ_blocks::cpu1.dtb.walker 150.211809 # Average occupied blocks per requestor 2338system.l2c.tags.occ_blocks::cpu1.itb.walker 222.184258 # Average occupied blocks per requestor 2339system.l2c.tags.occ_blocks::cpu1.inst 784.998757 # Average occupied blocks per requestor 2340system.l2c.tags.occ_blocks::cpu1.data 7219.989726 # Average occupied blocks per requestor 2341system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17043.373589 # Average occupied blocks per requestor 2342system.l2c.tags.occ_percent::writebacks 0.152562 # Average percentage of cache occupancy 2343system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000870 # Average percentage of cache occupancy 2344system.l2c.tags.occ_percent::cpu0.itb.walker 0.001177 # Average percentage of cache occupancy 2345system.l2c.tags.occ_percent::cpu0.inst 0.012080 # Average percentage of cache occupancy 2346system.l2c.tags.occ_percent::cpu0.data 0.068875 # Average percentage of cache occupancy 2347system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.363444 # Average percentage of cache occupancy 2348system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002292 # Average percentage of cache occupancy 2349system.l2c.tags.occ_percent::cpu1.itb.walker 0.003390 # Average percentage of cache occupancy 2350system.l2c.tags.occ_percent::cpu1.inst 0.011978 # Average percentage of cache occupancy 2351system.l2c.tags.occ_percent::cpu1.data 0.110168 # Average percentage of cache occupancy 2352system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.260061 # Average percentage of cache occupancy 2353system.l2c.tags.occ_percent::total 0.986898 # Average percentage of cache occupancy 2354system.l2c.tags.occ_task_id_blocks::1022 38915 # Occupied blocks per task id 2355system.l2c.tags.occ_task_id_blocks::1023 205 # Occupied blocks per task id 2356system.l2c.tags.occ_task_id_blocks::1024 24150 # Occupied blocks per task id 2357system.l2c.tags.age_task_id_blocks_1022::0 26 # Occupied blocks per task id 2358system.l2c.tags.age_task_id_blocks_1022::1 26 # Occupied blocks per task id 2359system.l2c.tags.age_task_id_blocks_1022::2 487 # Occupied blocks per task id 2360system.l2c.tags.age_task_id_blocks_1022::3 8729 # Occupied blocks per task id 2361system.l2c.tags.age_task_id_blocks_1022::4 29647 # Occupied blocks per task id 2362system.l2c.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id 2363system.l2c.tags.age_task_id_blocks_1023::4 188 # Occupied blocks per task id 2364system.l2c.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id 2365system.l2c.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id 2366system.l2c.tags.age_task_id_blocks_1024::2 550 # Occupied blocks per task id 2367system.l2c.tags.age_task_id_blocks_1024::3 5282 # Occupied blocks per task id 2368system.l2c.tags.age_task_id_blocks_1024::4 18136 # Occupied blocks per task id 2369system.l2c.tags.occ_task_id_percent::1022 0.593796 # Percentage of cache occupancy per task id 2370system.l2c.tags.occ_task_id_percent::1023 0.003128 # Percentage of cache occupancy per task id 2371system.l2c.tags.occ_task_id_percent::1024 0.368500 # Percentage of cache occupancy per task id 2372system.l2c.tags.tag_accesses 74054042 # Number of tag accesses 2373system.l2c.tags.data_accesses 74054042 # Number of data accesses 2374system.l2c.ReadReq_hits::cpu0.dtb.walker 5514 # number of ReadReq hits 2375system.l2c.ReadReq_hits::cpu0.itb.walker 4407 # number of ReadReq hits 2376system.l2c.ReadReq_hits::cpu0.inst 131001 # number of ReadReq hits 2377system.l2c.ReadReq_hits::cpu0.data 549137 # number of ReadReq hits 2378system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 1653135 # number of ReadReq hits 2379system.l2c.ReadReq_hits::cpu1.dtb.walker 7096 # number of ReadReq hits 2380system.l2c.ReadReq_hits::cpu1.itb.walker 6374 # number of ReadReq hits 2381system.l2c.ReadReq_hits::cpu1.inst 146834 # number of ReadReq hits 2382system.l2c.ReadReq_hits::cpu1.data 607953 # number of ReadReq hits 2383system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 1853450 # number of ReadReq hits 2384system.l2c.ReadReq_hits::total 4964901 # number of ReadReq hits 2385system.l2c.Writeback_hits::writebacks 2477309 # number of Writeback hits 2386system.l2c.Writeback_hits::total 2477309 # number of Writeback hits 2387system.l2c.WriteInvalidateReq_hits::cpu0.data 3452 # number of WriteInvalidateReq hits 2388system.l2c.WriteInvalidateReq_hits::cpu1.data 4029 # number of WriteInvalidateReq hits 2389system.l2c.WriteInvalidateReq_hits::total 7481 # number of WriteInvalidateReq hits 2390system.l2c.UpgradeReq_hits::cpu0.data 31717 # number of UpgradeReq hits 2391system.l2c.UpgradeReq_hits::cpu1.data 34608 # number of UpgradeReq hits 2392system.l2c.UpgradeReq_hits::total 66325 # number of UpgradeReq hits 2393system.l2c.SCUpgradeReq_hits::cpu0.data 7299 # number of SCUpgradeReq hits 2394system.l2c.SCUpgradeReq_hits::cpu1.data 8593 # number of SCUpgradeReq hits 2395system.l2c.SCUpgradeReq_hits::total 15892 # number of SCUpgradeReq hits 2396system.l2c.ReadExReq_hits::cpu0.data 45918 # number of ReadExReq hits 2397system.l2c.ReadExReq_hits::cpu1.data 59655 # number of ReadExReq hits 2398system.l2c.ReadExReq_hits::total 105573 # number of ReadExReq hits 2399system.l2c.demand_hits::cpu0.dtb.walker 5514 # number of demand (read+write) hits 2400system.l2c.demand_hits::cpu0.itb.walker 4407 # number of demand (read+write) hits 2401system.l2c.demand_hits::cpu0.inst 131001 # number of demand (read+write) hits 2402system.l2c.demand_hits::cpu0.data 595055 # number of demand (read+write) hits 2403system.l2c.demand_hits::cpu0.l2cache.prefetcher 1653135 # number of demand (read+write) hits 2404system.l2c.demand_hits::cpu1.dtb.walker 7096 # number of demand (read+write) hits 2405system.l2c.demand_hits::cpu1.itb.walker 6374 # number of demand (read+write) hits 2406system.l2c.demand_hits::cpu1.inst 146834 # number of demand (read+write) hits 2407system.l2c.demand_hits::cpu1.data 667608 # number of demand (read+write) hits 2408system.l2c.demand_hits::cpu1.l2cache.prefetcher 1853450 # number of demand (read+write) hits 2409system.l2c.demand_hits::total 5070474 # number of demand (read+write) hits 2410system.l2c.overall_hits::cpu0.dtb.walker 5514 # number of overall hits 2411system.l2c.overall_hits::cpu0.itb.walker 4407 # number of overall hits 2412system.l2c.overall_hits::cpu0.inst 131001 # number of overall hits 2413system.l2c.overall_hits::cpu0.data 595055 # number of overall hits 2414system.l2c.overall_hits::cpu0.l2cache.prefetcher 1653135 # number of overall hits 2415system.l2c.overall_hits::cpu1.dtb.walker 7096 # number of overall hits 2416system.l2c.overall_hits::cpu1.itb.walker 6374 # number of overall hits 2417system.l2c.overall_hits::cpu1.inst 146834 # number of overall hits 2418system.l2c.overall_hits::cpu1.data 667608 # number of overall hits 2419system.l2c.overall_hits::cpu1.l2cache.prefetcher 1853450 # number of overall hits 2420system.l2c.overall_hits::total 5070474 # number of overall hits 2421system.l2c.ReadReq_misses::cpu0.dtb.walker 569 # number of ReadReq misses 2422system.l2c.ReadReq_misses::cpu0.itb.walker 656 # number of ReadReq misses 2423system.l2c.ReadReq_misses::cpu0.inst 9314 # number of ReadReq misses 2424system.l2c.ReadReq_misses::cpu0.data 87213 # number of ReadReq misses 2425system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 698997 # number of ReadReq misses 2426system.l2c.ReadReq_misses::cpu1.dtb.walker 1304 # number of ReadReq misses 2427system.l2c.ReadReq_misses::cpu1.itb.walker 1531 # number of ReadReq misses 2428system.l2c.ReadReq_misses::cpu1.inst 9213 # number of ReadReq misses 2429system.l2c.ReadReq_misses::cpu1.data 99987 # number of ReadReq misses 2430system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 328949 # number of ReadReq misses 2431system.l2c.ReadReq_misses::total 1237733 # number of ReadReq misses 2432system.l2c.WriteInvalidateReq_misses::cpu0.data 9435 # number of WriteInvalidateReq misses 2433system.l2c.WriteInvalidateReq_misses::cpu1.data 3626 # number of WriteInvalidateReq misses 2434system.l2c.WriteInvalidateReq_misses::total 13061 # number of WriteInvalidateReq misses 2435system.l2c.UpgradeReq_misses::cpu0.data 30881 # number of UpgradeReq misses 2436system.l2c.UpgradeReq_misses::cpu1.data 31286 # number of UpgradeReq misses 2437system.l2c.UpgradeReq_misses::total 62167 # number of UpgradeReq misses 2438system.l2c.SCUpgradeReq_misses::cpu0.data 9976 # number of SCUpgradeReq misses 2439system.l2c.SCUpgradeReq_misses::cpu1.data 9599 # number of SCUpgradeReq misses 2440system.l2c.SCUpgradeReq_misses::total 19575 # number of SCUpgradeReq misses 2441system.l2c.ReadExReq_misses::cpu0.data 38485 # number of ReadExReq misses 2442system.l2c.ReadExReq_misses::cpu1.data 37338 # number of ReadExReq misses 2443system.l2c.ReadExReq_misses::total 75823 # number of ReadExReq misses 2444system.l2c.demand_misses::cpu0.dtb.walker 569 # number of demand (read+write) misses 2445system.l2c.demand_misses::cpu0.itb.walker 656 # number of demand (read+write) misses 2446system.l2c.demand_misses::cpu0.inst 9314 # number of demand (read+write) misses 2447system.l2c.demand_misses::cpu0.data 125698 # number of demand (read+write) misses 2448system.l2c.demand_misses::cpu0.l2cache.prefetcher 698997 # number of demand (read+write) misses 2449system.l2c.demand_misses::cpu1.dtb.walker 1304 # number of demand (read+write) misses 2450system.l2c.demand_misses::cpu1.itb.walker 1531 # number of demand (read+write) misses 2451system.l2c.demand_misses::cpu1.inst 9213 # number of demand (read+write) misses 2452system.l2c.demand_misses::cpu1.data 137325 # number of demand (read+write) misses 2453system.l2c.demand_misses::cpu1.l2cache.prefetcher 328949 # number of demand (read+write) misses 2454system.l2c.demand_misses::total 1313556 # number of demand (read+write) misses 2455system.l2c.overall_misses::cpu0.dtb.walker 569 # number of overall misses 2456system.l2c.overall_misses::cpu0.itb.walker 656 # number of overall misses 2457system.l2c.overall_misses::cpu0.inst 9314 # number of overall misses 2458system.l2c.overall_misses::cpu0.data 125698 # number of overall misses 2459system.l2c.overall_misses::cpu0.l2cache.prefetcher 698997 # number of overall misses 2460system.l2c.overall_misses::cpu1.dtb.walker 1304 # number of overall misses 2461system.l2c.overall_misses::cpu1.itb.walker 1531 # number of overall misses 2462system.l2c.overall_misses::cpu1.inst 9213 # number of overall misses 2463system.l2c.overall_misses::cpu1.data 137325 # number of overall misses 2464system.l2c.overall_misses::cpu1.l2cache.prefetcher 328949 # number of overall misses 2465system.l2c.overall_misses::total 1313556 # number of overall misses 2466system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 46419250 # number of ReadReq miss cycles 2467system.l2c.ReadReq_miss_latency::cpu0.itb.walker 56195000 # number of ReadReq miss cycles 2468system.l2c.ReadReq_miss_latency::cpu0.inst 845205741 # number of ReadReq miss cycles 2469system.l2c.ReadReq_miss_latency::cpu0.data 7070866945 # number of ReadReq miss cycles 2470system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 100071825385 # number of ReadReq miss cycles 2471system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 105377999 # number of ReadReq miss cycles 2472system.l2c.ReadReq_miss_latency::cpu1.itb.walker 124997499 # number of ReadReq miss cycles 2473system.l2c.ReadReq_miss_latency::cpu1.inst 812177995 # number of ReadReq miss cycles 2474system.l2c.ReadReq_miss_latency::cpu1.data 7981910698 # number of ReadReq miss cycles 2475system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 38448513875 # number of ReadReq miss cycles 2476system.l2c.ReadReq_miss_latency::total 155563490387 # number of ReadReq miss cycles 2477system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 1840421 # number of WriteInvalidateReq miss cycles 2478system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 2071411 # number of WriteInvalidateReq miss cycles 2479system.l2c.WriteInvalidateReq_miss_latency::total 3911832 # number of WriteInvalidateReq miss cycles 2480system.l2c.UpgradeReq_miss_latency::cpu0.data 134255920 # number of UpgradeReq miss cycles 2481system.l2c.UpgradeReq_miss_latency::cpu1.data 141850516 # number of UpgradeReq miss cycles 2482system.l2c.UpgradeReq_miss_latency::total 276106436 # number of UpgradeReq miss cycles 2483system.l2c.SCUpgradeReq_miss_latency::cpu0.data 49268414 # number of SCUpgradeReq miss cycles 2484system.l2c.SCUpgradeReq_miss_latency::cpu1.data 49362431 # number of SCUpgradeReq miss cycles 2485system.l2c.SCUpgradeReq_miss_latency::total 98630845 # number of SCUpgradeReq miss cycles 2486system.l2c.ReadExReq_miss_latency::cpu0.data 2848027798 # number of ReadExReq miss cycles 2487system.l2c.ReadExReq_miss_latency::cpu1.data 2731267565 # number of ReadExReq miss cycles 2488system.l2c.ReadExReq_miss_latency::total 5579295363 # number of ReadExReq miss cycles 2489system.l2c.demand_miss_latency::cpu0.dtb.walker 46419250 # number of demand (read+write) miss cycles 2490system.l2c.demand_miss_latency::cpu0.itb.walker 56195000 # number of demand (read+write) miss cycles 2491system.l2c.demand_miss_latency::cpu0.inst 845205741 # number of demand (read+write) miss cycles 2492system.l2c.demand_miss_latency::cpu0.data 9918894743 # number of demand (read+write) miss cycles 2493system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 100071825385 # number of demand (read+write) miss cycles 2494system.l2c.demand_miss_latency::cpu1.dtb.walker 105377999 # number of demand (read+write) miss cycles 2495system.l2c.demand_miss_latency::cpu1.itb.walker 124997499 # number of demand (read+write) miss cycles 2496system.l2c.demand_miss_latency::cpu1.inst 812177995 # number of demand (read+write) miss cycles 2497system.l2c.demand_miss_latency::cpu1.data 10713178263 # number of demand (read+write) miss cycles 2498system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 38448513875 # number of demand (read+write) miss cycles 2499system.l2c.demand_miss_latency::total 161142785750 # number of demand (read+write) miss cycles 2500system.l2c.overall_miss_latency::cpu0.dtb.walker 46419250 # number of overall miss cycles 2501system.l2c.overall_miss_latency::cpu0.itb.walker 56195000 # number of overall miss cycles 2502system.l2c.overall_miss_latency::cpu0.inst 845205741 # number of overall miss cycles 2503system.l2c.overall_miss_latency::cpu0.data 9918894743 # number of overall miss cycles 2504system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 100071825385 # number of overall miss cycles 2505system.l2c.overall_miss_latency::cpu1.dtb.walker 105377999 # number of overall miss cycles 2506system.l2c.overall_miss_latency::cpu1.itb.walker 124997499 # number of overall miss cycles 2507system.l2c.overall_miss_latency::cpu1.inst 812177995 # number of overall miss cycles 2508system.l2c.overall_miss_latency::cpu1.data 10713178263 # number of overall miss cycles 2509system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 38448513875 # number of overall miss cycles 2510system.l2c.overall_miss_latency::total 161142785750 # number of overall miss cycles 2511system.l2c.ReadReq_accesses::cpu0.dtb.walker 6083 # number of ReadReq accesses(hits+misses) 2512system.l2c.ReadReq_accesses::cpu0.itb.walker 5063 # number of ReadReq accesses(hits+misses) 2513system.l2c.ReadReq_accesses::cpu0.inst 140315 # number of ReadReq accesses(hits+misses) 2514system.l2c.ReadReq_accesses::cpu0.data 636350 # number of ReadReq accesses(hits+misses) 2515system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 2352132 # number of ReadReq accesses(hits+misses) 2516system.l2c.ReadReq_accesses::cpu1.dtb.walker 8400 # number of ReadReq accesses(hits+misses) 2517system.l2c.ReadReq_accesses::cpu1.itb.walker 7905 # number of ReadReq accesses(hits+misses) 2518system.l2c.ReadReq_accesses::cpu1.inst 156047 # number of ReadReq accesses(hits+misses) 2519system.l2c.ReadReq_accesses::cpu1.data 707940 # number of ReadReq accesses(hits+misses) 2520system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 2182399 # number of ReadReq accesses(hits+misses) 2521system.l2c.ReadReq_accesses::total 6202634 # number of ReadReq accesses(hits+misses) 2522system.l2c.Writeback_accesses::writebacks 2477309 # number of Writeback accesses(hits+misses) 2523system.l2c.Writeback_accesses::total 2477309 # number of Writeback accesses(hits+misses) 2524system.l2c.WriteInvalidateReq_accesses::cpu0.data 12887 # number of WriteInvalidateReq accesses(hits+misses) 2525system.l2c.WriteInvalidateReq_accesses::cpu1.data 7655 # number of WriteInvalidateReq accesses(hits+misses) 2526system.l2c.WriteInvalidateReq_accesses::total 20542 # number of WriteInvalidateReq accesses(hits+misses) 2527system.l2c.UpgradeReq_accesses::cpu0.data 62598 # number of UpgradeReq accesses(hits+misses) 2528system.l2c.UpgradeReq_accesses::cpu1.data 65894 # number of UpgradeReq accesses(hits+misses) 2529system.l2c.UpgradeReq_accesses::total 128492 # number of UpgradeReq accesses(hits+misses) 2530system.l2c.SCUpgradeReq_accesses::cpu0.data 17275 # number of SCUpgradeReq accesses(hits+misses) 2531system.l2c.SCUpgradeReq_accesses::cpu1.data 18192 # number of SCUpgradeReq accesses(hits+misses) 2532system.l2c.SCUpgradeReq_accesses::total 35467 # number of SCUpgradeReq accesses(hits+misses) 2533system.l2c.ReadExReq_accesses::cpu0.data 84403 # number of ReadExReq accesses(hits+misses) 2534system.l2c.ReadExReq_accesses::cpu1.data 96993 # number of ReadExReq accesses(hits+misses) 2535system.l2c.ReadExReq_accesses::total 181396 # number of ReadExReq accesses(hits+misses) 2536system.l2c.demand_accesses::cpu0.dtb.walker 6083 # number of demand (read+write) accesses 2537system.l2c.demand_accesses::cpu0.itb.walker 5063 # number of demand (read+write) accesses 2538system.l2c.demand_accesses::cpu0.inst 140315 # number of demand (read+write) accesses 2539system.l2c.demand_accesses::cpu0.data 720753 # number of demand (read+write) accesses 2540system.l2c.demand_accesses::cpu0.l2cache.prefetcher 2352132 # number of demand (read+write) accesses 2541system.l2c.demand_accesses::cpu1.dtb.walker 8400 # number of demand (read+write) accesses 2542system.l2c.demand_accesses::cpu1.itb.walker 7905 # number of demand (read+write) accesses 2543system.l2c.demand_accesses::cpu1.inst 156047 # number of demand (read+write) accesses 2544system.l2c.demand_accesses::cpu1.data 804933 # number of demand (read+write) accesses 2545system.l2c.demand_accesses::cpu1.l2cache.prefetcher 2182399 # number of demand (read+write) accesses 2546system.l2c.demand_accesses::total 6384030 # number of demand (read+write) accesses 2547system.l2c.overall_accesses::cpu0.dtb.walker 6083 # number of overall (read+write) accesses 2548system.l2c.overall_accesses::cpu0.itb.walker 5063 # number of overall (read+write) accesses 2549system.l2c.overall_accesses::cpu0.inst 140315 # number of overall (read+write) accesses 2550system.l2c.overall_accesses::cpu0.data 720753 # number of overall (read+write) accesses 2551system.l2c.overall_accesses::cpu0.l2cache.prefetcher 2352132 # number of overall (read+write) accesses 2552system.l2c.overall_accesses::cpu1.dtb.walker 8400 # number of overall (read+write) accesses 2553system.l2c.overall_accesses::cpu1.itb.walker 7905 # number of overall (read+write) accesses 2554system.l2c.overall_accesses::cpu1.inst 156047 # number of overall (read+write) accesses 2555system.l2c.overall_accesses::cpu1.data 804933 # number of overall (read+write) accesses 2556system.l2c.overall_accesses::cpu1.l2cache.prefetcher 2182399 # number of overall (read+write) accesses 2557system.l2c.overall_accesses::total 6384030 # number of overall (read+write) accesses 2558system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.093539 # miss rate for ReadReq accesses 2559system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.129567 # miss rate for ReadReq accesses 2560system.l2c.ReadReq_miss_rate::cpu0.inst 0.066379 # miss rate for ReadReq accesses 2561system.l2c.ReadReq_miss_rate::cpu0.data 0.137052 # miss rate for ReadReq accesses 2562system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.297176 # miss rate for ReadReq accesses 2563system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.155238 # miss rate for ReadReq accesses 2564system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.193675 # miss rate for ReadReq accesses 2565system.l2c.ReadReq_miss_rate::cpu1.inst 0.059040 # miss rate for ReadReq accesses 2566system.l2c.ReadReq_miss_rate::cpu1.data 0.141237 # miss rate for ReadReq accesses 2567system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.150728 # miss rate for ReadReq accesses 2568system.l2c.ReadReq_miss_rate::total 0.199550 # miss rate for ReadReq accesses 2569system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.732133 # miss rate for WriteInvalidateReq accesses 2570system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.473677 # miss rate for WriteInvalidateReq accesses 2571system.l2c.WriteInvalidateReq_miss_rate::total 0.635819 # miss rate for WriteInvalidateReq accesses 2572system.l2c.UpgradeReq_miss_rate::cpu0.data 0.493322 # miss rate for UpgradeReq accesses 2573system.l2c.UpgradeReq_miss_rate::cpu1.data 0.474793 # miss rate for UpgradeReq accesses 2574system.l2c.UpgradeReq_miss_rate::total 0.483820 # miss rate for UpgradeReq accesses 2575system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.577482 # miss rate for SCUpgradeReq accesses 2576system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.527650 # miss rate for SCUpgradeReq accesses 2577system.l2c.SCUpgradeReq_miss_rate::total 0.551922 # miss rate for SCUpgradeReq accesses 2578system.l2c.ReadExReq_miss_rate::cpu0.data 0.455967 # miss rate for ReadExReq accesses 2579system.l2c.ReadExReq_miss_rate::cpu1.data 0.384956 # miss rate for ReadExReq accesses 2580system.l2c.ReadExReq_miss_rate::total 0.417997 # miss rate for ReadExReq accesses 2581system.l2c.demand_miss_rate::cpu0.dtb.walker 0.093539 # miss rate for demand accesses 2582system.l2c.demand_miss_rate::cpu0.itb.walker 0.129567 # miss rate for demand accesses 2583system.l2c.demand_miss_rate::cpu0.inst 0.066379 # miss rate for demand accesses 2584system.l2c.demand_miss_rate::cpu0.data 0.174398 # miss rate for demand accesses 2585system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.297176 # miss rate for demand accesses 2586system.l2c.demand_miss_rate::cpu1.dtb.walker 0.155238 # miss rate for demand accesses 2587system.l2c.demand_miss_rate::cpu1.itb.walker 0.193675 # miss rate for demand accesses 2588system.l2c.demand_miss_rate::cpu1.inst 0.059040 # miss rate for demand accesses 2589system.l2c.demand_miss_rate::cpu1.data 0.170604 # miss rate for demand accesses 2590system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.150728 # miss rate for demand accesses 2591system.l2c.demand_miss_rate::total 0.205757 # miss rate for demand accesses 2592system.l2c.overall_miss_rate::cpu0.dtb.walker 0.093539 # miss rate for overall accesses 2593system.l2c.overall_miss_rate::cpu0.itb.walker 0.129567 # miss rate for overall accesses 2594system.l2c.overall_miss_rate::cpu0.inst 0.066379 # miss rate for overall accesses 2595system.l2c.overall_miss_rate::cpu0.data 0.174398 # miss rate for overall accesses 2596system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.297176 # miss rate for overall accesses 2597system.l2c.overall_miss_rate::cpu1.dtb.walker 0.155238 # miss rate for overall accesses 2598system.l2c.overall_miss_rate::cpu1.itb.walker 0.193675 # miss rate for overall accesses 2599system.l2c.overall_miss_rate::cpu1.inst 0.059040 # miss rate for overall accesses 2600system.l2c.overall_miss_rate::cpu1.data 0.170604 # miss rate for overall accesses 2601system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.150728 # miss rate for overall accesses 2602system.l2c.overall_miss_rate::total 0.205757 # miss rate for overall accesses 2603system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 81580.404218 # average ReadReq miss latency 2604system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 85663.109756 # average ReadReq miss latency 2605system.l2c.ReadReq_avg_miss_latency::cpu0.inst 90745.731265 # average ReadReq miss latency 2606system.l2c.ReadReq_avg_miss_latency::cpu0.data 81075.836687 # average ReadReq miss latency 2607system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 143164.885379 # average ReadReq miss latency 2608system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 80811.348926 # average ReadReq miss latency 2609system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 81644.349445 # average ReadReq miss latency 2610system.l2c.ReadReq_avg_miss_latency::cpu1.inst 88155.649083 # average ReadReq miss latency 2611system.l2c.ReadReq_avg_miss_latency::cpu1.data 79829.484813 # average ReadReq miss latency 2612system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 116882.902441 # average ReadReq miss latency 2613system.l2c.ReadReq_avg_miss_latency::total 125684.206842 # average ReadReq miss latency 2614system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 195.063169 # average WriteInvalidateReq miss latency 2615system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 571.266133 # average WriteInvalidateReq miss latency 2616system.l2c.WriteInvalidateReq_avg_miss_latency::total 299.504785 # average WriteInvalidateReq miss latency 2617system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 4347.525015 # average UpgradeReq miss latency 2618system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4533.993352 # average UpgradeReq miss latency 2619system.l2c.UpgradeReq_avg_miss_latency::total 4441.366577 # average UpgradeReq miss latency 2620system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4938.694266 # average SCUpgradeReq miss latency 2621system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5142.455568 # average SCUpgradeReq miss latency 2622system.l2c.SCUpgradeReq_avg_miss_latency::total 5038.612771 # average SCUpgradeReq miss latency 2623system.l2c.ReadExReq_avg_miss_latency::cpu0.data 74003.580564 # average ReadExReq miss latency 2624system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73149.808908 # average ReadExReq miss latency 2625system.l2c.ReadExReq_avg_miss_latency::total 73583.152381 # average ReadExReq miss latency 2626system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 81580.404218 # average overall miss latency 2627system.l2c.demand_avg_miss_latency::cpu0.itb.walker 85663.109756 # average overall miss latency 2628system.l2c.demand_avg_miss_latency::cpu0.inst 90745.731265 # average overall miss latency 2629system.l2c.demand_avg_miss_latency::cpu0.data 78910.521591 # average overall miss latency 2630system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 143164.885379 # average overall miss latency 2631system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 80811.348926 # average overall miss latency 2632system.l2c.demand_avg_miss_latency::cpu1.itb.walker 81644.349445 # average overall miss latency 2633system.l2c.demand_avg_miss_latency::cpu1.inst 88155.649083 # average overall miss latency 2634system.l2c.demand_avg_miss_latency::cpu1.data 78013.313403 # average overall miss latency 2635system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 116882.902441 # average overall miss latency 2636system.l2c.demand_avg_miss_latency::total 122676.753599 # average overall miss latency 2637system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 81580.404218 # average overall miss latency 2638system.l2c.overall_avg_miss_latency::cpu0.itb.walker 85663.109756 # average overall miss latency 2639system.l2c.overall_avg_miss_latency::cpu0.inst 90745.731265 # average overall miss latency 2640system.l2c.overall_avg_miss_latency::cpu0.data 78910.521591 # average overall miss latency 2641system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 143164.885379 # average overall miss latency 2642system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 80811.348926 # average overall miss latency 2643system.l2c.overall_avg_miss_latency::cpu1.itb.walker 81644.349445 # average overall miss latency 2644system.l2c.overall_avg_miss_latency::cpu1.inst 88155.649083 # average overall miss latency 2645system.l2c.overall_avg_miss_latency::cpu1.data 78013.313403 # average overall miss latency 2646system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 116882.902441 # average overall miss latency 2647system.l2c.overall_avg_miss_latency::total 122676.753599 # average overall miss latency 2648system.l2c.blocked_cycles::no_mshrs 4412 # number of cycles access was blocked 2649system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2650system.l2c.blocked::no_mshrs 93 # number of cycles access was blocked 2651system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2652system.l2c.avg_blocked_cycles::no_mshrs 47.440860 # average number of cycles each access was blocked 2653system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2654system.l2c.fast_writes 0 # number of fast writes performed 2655system.l2c.cache_copies 0 # number of cache copies performed 2656system.l2c.writebacks::writebacks 910321 # number of writebacks 2657system.l2c.writebacks::total 910321 # number of writebacks 2658system.l2c.ReadReq_mshr_hits::cpu0.inst 7 # number of ReadReq MSHR hits 2659system.l2c.ReadReq_mshr_hits::cpu0.data 17 # number of ReadReq MSHR hits 2660system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 129 # number of ReadReq MSHR hits 2661system.l2c.ReadReq_mshr_hits::cpu1.inst 10 # number of ReadReq MSHR hits 2662system.l2c.ReadReq_mshr_hits::cpu1.data 10 # number of ReadReq MSHR hits 2663system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 122 # number of ReadReq MSHR hits 2664system.l2c.ReadReq_mshr_hits::total 295 # number of ReadReq MSHR hits 2665system.l2c.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits 2666system.l2c.demand_mshr_hits::cpu0.data 17 # number of demand (read+write) MSHR hits 2667system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 129 # number of demand (read+write) MSHR hits 2668system.l2c.demand_mshr_hits::cpu1.inst 10 # number of demand (read+write) MSHR hits 2669system.l2c.demand_mshr_hits::cpu1.data 10 # number of demand (read+write) MSHR hits 2670system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 122 # number of demand (read+write) MSHR hits 2671system.l2c.demand_mshr_hits::total 295 # number of demand (read+write) MSHR hits 2672system.l2c.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits 2673system.l2c.overall_mshr_hits::cpu0.data 17 # number of overall MSHR hits 2674system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 129 # number of overall MSHR hits 2675system.l2c.overall_mshr_hits::cpu1.inst 10 # number of overall MSHR hits 2676system.l2c.overall_mshr_hits::cpu1.data 10 # number of overall MSHR hits 2677system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 122 # number of overall MSHR hits 2678system.l2c.overall_mshr_hits::total 295 # number of overall MSHR hits 2679system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 569 # number of ReadReq MSHR misses 2680system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 656 # number of ReadReq MSHR misses 2681system.l2c.ReadReq_mshr_misses::cpu0.inst 9307 # number of ReadReq MSHR misses 2682system.l2c.ReadReq_mshr_misses::cpu0.data 87196 # number of ReadReq MSHR misses 2683system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 698868 # number of ReadReq MSHR misses 2684system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1304 # number of ReadReq MSHR misses 2685system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1531 # number of ReadReq MSHR misses 2686system.l2c.ReadReq_mshr_misses::cpu1.inst 9203 # number of ReadReq MSHR misses 2687system.l2c.ReadReq_mshr_misses::cpu1.data 99977 # number of ReadReq MSHR misses 2688system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 328827 # number of ReadReq MSHR misses 2689system.l2c.ReadReq_mshr_misses::total 1237438 # number of ReadReq MSHR misses 2690system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 9435 # number of WriteInvalidateReq MSHR misses 2691system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 3626 # number of WriteInvalidateReq MSHR misses 2692system.l2c.WriteInvalidateReq_mshr_misses::total 13061 # number of WriteInvalidateReq MSHR misses 2693system.l2c.UpgradeReq_mshr_misses::cpu0.data 30881 # number of UpgradeReq MSHR misses 2694system.l2c.UpgradeReq_mshr_misses::cpu1.data 31286 # number of UpgradeReq MSHR misses 2695system.l2c.UpgradeReq_mshr_misses::total 62167 # number of UpgradeReq MSHR misses 2696system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 9976 # number of SCUpgradeReq MSHR misses 2697system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 9599 # number of SCUpgradeReq MSHR misses 2698system.l2c.SCUpgradeReq_mshr_misses::total 19575 # number of SCUpgradeReq MSHR misses 2699system.l2c.ReadExReq_mshr_misses::cpu0.data 38485 # number of ReadExReq MSHR misses 2700system.l2c.ReadExReq_mshr_misses::cpu1.data 37338 # number of ReadExReq MSHR misses 2701system.l2c.ReadExReq_mshr_misses::total 75823 # number of ReadExReq MSHR misses 2702system.l2c.demand_mshr_misses::cpu0.dtb.walker 569 # number of demand (read+write) MSHR misses 2703system.l2c.demand_mshr_misses::cpu0.itb.walker 656 # number of demand (read+write) MSHR misses 2704system.l2c.demand_mshr_misses::cpu0.inst 9307 # number of demand (read+write) MSHR misses 2705system.l2c.demand_mshr_misses::cpu0.data 125681 # number of demand (read+write) MSHR misses 2706system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 698868 # number of demand (read+write) MSHR misses 2707system.l2c.demand_mshr_misses::cpu1.dtb.walker 1304 # number of demand (read+write) MSHR misses 2708system.l2c.demand_mshr_misses::cpu1.itb.walker 1531 # number of demand (read+write) MSHR misses 2709system.l2c.demand_mshr_misses::cpu1.inst 9203 # number of demand (read+write) MSHR misses 2710system.l2c.demand_mshr_misses::cpu1.data 137315 # number of demand (read+write) MSHR misses 2711system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 328827 # number of demand (read+write) MSHR misses 2712system.l2c.demand_mshr_misses::total 1313261 # number of demand (read+write) MSHR misses 2713system.l2c.overall_mshr_misses::cpu0.dtb.walker 569 # number of overall MSHR misses 2714system.l2c.overall_mshr_misses::cpu0.itb.walker 656 # number of overall MSHR misses 2715system.l2c.overall_mshr_misses::cpu0.inst 9307 # number of overall MSHR misses 2716system.l2c.overall_mshr_misses::cpu0.data 125681 # number of overall MSHR misses 2717system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 698868 # number of overall MSHR misses 2718system.l2c.overall_mshr_misses::cpu1.dtb.walker 1304 # number of overall MSHR misses 2719system.l2c.overall_mshr_misses::cpu1.itb.walker 1531 # number of overall MSHR misses 2720system.l2c.overall_mshr_misses::cpu1.inst 9203 # number of overall MSHR misses 2721system.l2c.overall_mshr_misses::cpu1.data 137315 # number of overall MSHR misses 2722system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 328827 # number of overall MSHR misses 2723system.l2c.overall_mshr_misses::total 1313261 # number of overall MSHR misses 2724system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 39310750 # number of ReadReq MSHR miss cycles 2725system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 47990500 # number of ReadReq MSHR miss cycles 2726system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 728789245 # number of ReadReq MSHR miss cycles 2727system.l2c.ReadReq_mshr_miss_latency::cpu0.data 5976245749 # number of ReadReq MSHR miss cycles 2728system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 91523692653 # number of ReadReq MSHR miss cycles 2729system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 89033499 # number of ReadReq MSHR miss cycles 2730system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 105818499 # number of ReadReq MSHR miss cycles 2731system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 697155745 # number of ReadReq MSHR miss cycles 2732system.l2c.ReadReq_mshr_miss_latency::cpu1.data 6727481950 # number of ReadReq MSHR miss cycles 2733system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 34415077377 # number of ReadReq MSHR miss cycles 2734system.l2c.ReadReq_mshr_miss_latency::total 140350595967 # number of ReadReq MSHR miss cycles 2735system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 188587078 # number of WriteInvalidateReq MSHR miss cycles 2736system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 72419588 # number of WriteInvalidateReq MSHR miss cycles 2737system.l2c.WriteInvalidateReq_mshr_miss_latency::total 261006666 # number of WriteInvalidateReq MSHR miss cycles 2738system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 312906599 # number of UpgradeReq MSHR miss cycles 2739system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 316193537 # number of UpgradeReq MSHR miss cycles 2740system.l2c.UpgradeReq_mshr_miss_latency::total 629100136 # number of UpgradeReq MSHR miss cycles 2741system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 101000382 # number of SCUpgradeReq MSHR miss cycles 2742system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 97535510 # number of SCUpgradeReq MSHR miss cycles 2743system.l2c.SCUpgradeReq_mshr_miss_latency::total 198535892 # number of SCUpgradeReq MSHR miss cycles 2744system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2362166158 # number of ReadExReq MSHR miss cycles 2745system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2259616901 # number of ReadExReq MSHR miss cycles 2746system.l2c.ReadExReq_mshr_miss_latency::total 4621783059 # number of ReadExReq MSHR miss cycles 2747system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 39310750 # number of demand (read+write) MSHR miss cycles 2748system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 47990500 # number of demand (read+write) MSHR miss cycles 2749system.l2c.demand_mshr_miss_latency::cpu0.inst 728789245 # number of demand (read+write) MSHR miss cycles 2750system.l2c.demand_mshr_miss_latency::cpu0.data 8338411907 # number of demand (read+write) MSHR miss cycles 2751system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 91523692653 # number of demand (read+write) MSHR miss cycles 2752system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 89033499 # number of demand (read+write) MSHR miss cycles 2753system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 105818499 # number of demand (read+write) MSHR miss cycles 2754system.l2c.demand_mshr_miss_latency::cpu1.inst 697155745 # number of demand (read+write) MSHR miss cycles 2755system.l2c.demand_mshr_miss_latency::cpu1.data 8987098851 # number of demand (read+write) MSHR miss cycles 2756system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 34415077377 # number of demand (read+write) MSHR miss cycles 2757system.l2c.demand_mshr_miss_latency::total 144972379026 # number of demand (read+write) MSHR miss cycles 2758system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 39310750 # number of overall MSHR miss cycles 2759system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 47990500 # number of overall MSHR miss cycles 2760system.l2c.overall_mshr_miss_latency::cpu0.inst 728789245 # number of overall MSHR miss cycles 2761system.l2c.overall_mshr_miss_latency::cpu0.data 8338411907 # number of overall MSHR miss cycles 2762system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 91523692653 # number of overall MSHR miss cycles 2763system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 89033499 # number of overall MSHR miss cycles 2764system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 105818499 # number of overall MSHR miss cycles 2765system.l2c.overall_mshr_miss_latency::cpu1.inst 697155745 # number of overall MSHR miss cycles 2766system.l2c.overall_mshr_miss_latency::cpu1.data 8987098851 # number of overall MSHR miss cycles 2767system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 34415077377 # number of overall MSHR miss cycles 2768system.l2c.overall_mshr_miss_latency::total 144972379026 # number of overall MSHR miss cycles 2769system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2246197250 # number of ReadReq MSHR uncacheable cycles 2770system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2006968250 # number of ReadReq MSHR uncacheable cycles 2771system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6158750 # number of ReadReq MSHR uncacheable cycles 2772system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3361769998 # number of ReadReq MSHR uncacheable cycles 2773system.l2c.ReadReq_mshr_uncacheable_latency::total 7621094248 # number of ReadReq MSHR uncacheable cycles 2774system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1998731000 # number of WriteReq MSHR uncacheable cycles 2775system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 3265755499 # number of WriteReq MSHR uncacheable cycles 2776system.l2c.WriteReq_mshr_uncacheable_latency::total 5264486499 # number of WriteReq MSHR uncacheable cycles 2777system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2246197250 # number of overall MSHR uncacheable cycles 2778system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4005699250 # number of overall MSHR uncacheable cycles 2779system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6158750 # number of overall MSHR uncacheable cycles 2780system.l2c.overall_mshr_uncacheable_latency::cpu1.data 6627525497 # number of overall MSHR uncacheable cycles 2781system.l2c.overall_mshr_uncacheable_latency::total 12885580747 # number of overall MSHR uncacheable cycles 2782system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.093539 # mshr miss rate for ReadReq accesses 2783system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.129567 # mshr miss rate for ReadReq accesses 2784system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.066329 # mshr miss rate for ReadReq accesses 2785system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.137025 # mshr miss rate for ReadReq accesses 2786system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.297121 # mshr miss rate for ReadReq accesses 2787system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.155238 # mshr miss rate for ReadReq accesses 2788system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.193675 # mshr miss rate for ReadReq accesses 2789system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.058976 # mshr miss rate for ReadReq accesses 2790system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.141222 # mshr miss rate for ReadReq accesses 2791system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.150672 # mshr miss rate for ReadReq accesses 2792system.l2c.ReadReq_mshr_miss_rate::total 0.199502 # mshr miss rate for ReadReq accesses 2793system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.732133 # mshr miss rate for WriteInvalidateReq accesses 2794system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.473677 # mshr miss rate for WriteInvalidateReq accesses 2795system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.635819 # mshr miss rate for WriteInvalidateReq accesses 2796system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.493322 # mshr miss rate for UpgradeReq accesses 2797system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.474793 # mshr miss rate for UpgradeReq accesses 2798system.l2c.UpgradeReq_mshr_miss_rate::total 0.483820 # mshr miss rate for UpgradeReq accesses 2799system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.577482 # mshr miss rate for SCUpgradeReq accesses 2800system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.527650 # mshr miss rate for SCUpgradeReq accesses 2801system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.551922 # mshr miss rate for SCUpgradeReq accesses 2802system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.455967 # mshr miss rate for ReadExReq accesses 2803system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.384956 # mshr miss rate for ReadExReq accesses 2804system.l2c.ReadExReq_mshr_miss_rate::total 0.417997 # mshr miss rate for ReadExReq accesses 2805system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.093539 # mshr miss rate for demand accesses 2806system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.129567 # mshr miss rate for demand accesses 2807system.l2c.demand_mshr_miss_rate::cpu0.inst 0.066329 # mshr miss rate for demand accesses 2808system.l2c.demand_mshr_miss_rate::cpu0.data 0.174375 # mshr miss rate for demand accesses 2809system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.297121 # mshr miss rate for demand accesses 2810system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.155238 # mshr miss rate for demand accesses 2811system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.193675 # mshr miss rate for demand accesses 2812system.l2c.demand_mshr_miss_rate::cpu1.inst 0.058976 # mshr miss rate for demand accesses 2813system.l2c.demand_mshr_miss_rate::cpu1.data 0.170592 # mshr miss rate for demand accesses 2814system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.150672 # mshr miss rate for demand accesses 2815system.l2c.demand_mshr_miss_rate::total 0.205710 # mshr miss rate for demand accesses 2816system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.093539 # mshr miss rate for overall accesses 2817system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.129567 # mshr miss rate for overall accesses 2818system.l2c.overall_mshr_miss_rate::cpu0.inst 0.066329 # mshr miss rate for overall accesses 2819system.l2c.overall_mshr_miss_rate::cpu0.data 0.174375 # mshr miss rate for overall accesses 2820system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.297121 # mshr miss rate for overall accesses 2821system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.155238 # mshr miss rate for overall accesses 2822system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.193675 # mshr miss rate for overall accesses 2823system.l2c.overall_mshr_miss_rate::cpu1.inst 0.058976 # mshr miss rate for overall accesses 2824system.l2c.overall_mshr_miss_rate::cpu1.data 0.170592 # mshr miss rate for overall accesses 2825system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.150672 # mshr miss rate for overall accesses 2826system.l2c.overall_mshr_miss_rate::total 0.205710 # mshr miss rate for overall accesses 2827system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 69087.434095 # average ReadReq mshr miss latency 2828system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 73156.250000 # average ReadReq mshr miss latency 2829system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 78305.495326 # average ReadReq mshr miss latency 2830system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68538.072262 # average ReadReq mshr miss latency 2831system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130959.913250 # average ReadReq mshr miss latency 2832system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68277.223160 # average ReadReq mshr miss latency 2833system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 69117.242978 # average ReadReq mshr miss latency 2834system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 75753.096273 # average ReadReq mshr miss latency 2835system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67290.296268 # average ReadReq mshr miss latency 2836system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104660.132462 # average ReadReq mshr miss latency 2837system.l2c.ReadReq_avg_mshr_miss_latency::total 113420.305476 # average ReadReq mshr miss latency 2838system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 19988.031585 # average WriteInvalidateReq mshr miss latency 2839system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 19972.307777 # average WriteInvalidateReq mshr miss latency 2840system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 19983.666335 # average WriteInvalidateReq mshr miss latency 2841system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10132.657589 # average UpgradeReq mshr miss latency 2842system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10106.550438 # average UpgradeReq mshr miss latency 2843system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10119.518973 # average UpgradeReq mshr miss latency 2844system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10124.336608 # average SCUpgradeReq mshr miss latency 2845system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10161.007397 # average SCUpgradeReq mshr miss latency 2846system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10142.318876 # average SCUpgradeReq mshr miss latency 2847system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61378.878992 # average ReadExReq mshr miss latency 2848system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60517.887969 # average ReadExReq mshr miss latency 2849system.l2c.ReadExReq_avg_mshr_miss_latency::total 60954.895731 # average ReadExReq mshr miss latency 2850system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 69087.434095 # average overall mshr miss latency 2851system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 73156.250000 # average overall mshr miss latency 2852system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 78305.495326 # average overall mshr miss latency 2853system.l2c.demand_avg_mshr_miss_latency::cpu0.data 66345.843103 # average overall mshr miss latency 2854system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130959.913250 # average overall mshr miss latency 2855system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68277.223160 # average overall mshr miss latency 2856system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 69117.242978 # average overall mshr miss latency 2857system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75753.096273 # average overall mshr miss latency 2858system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65448.777271 # average overall mshr miss latency 2859system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104660.132462 # average overall mshr miss latency 2860system.l2c.demand_avg_mshr_miss_latency::total 110391.140090 # average overall mshr miss latency 2861system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 69087.434095 # average overall mshr miss latency 2862system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73156.250000 # average overall mshr miss latency 2863system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 78305.495326 # average overall mshr miss latency 2864system.l2c.overall_avg_mshr_miss_latency::cpu0.data 66345.843103 # average overall mshr miss latency 2865system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130959.913250 # average overall mshr miss latency 2866system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68277.223160 # average overall mshr miss latency 2867system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 69117.242978 # average overall mshr miss latency 2868system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75753.096273 # average overall mshr miss latency 2869system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65448.777271 # average overall mshr miss latency 2870system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104660.132462 # average overall mshr miss latency 2871system.l2c.overall_avg_mshr_miss_latency::total 110391.140090 # average overall mshr miss latency 2872system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 2873system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 2874system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2875system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2876system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2877system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 2878system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2879system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2880system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 2881system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 2882system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2883system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2884system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2885system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2886system.membus.trans_dist::ReadReq 1327465 # Transaction distribution 2887system.membus.trans_dist::ReadResp 1327465 # Transaction distribution 2888system.membus.trans_dist::WriteReq 37863 # Transaction distribution 2889system.membus.trans_dist::WriteResp 37863 # Transaction distribution 2890system.membus.trans_dist::Writeback 1017207 # Transaction distribution 2891system.membus.trans_dist::WriteInvalidateReq 119813 # Transaction distribution 2892system.membus.trans_dist::WriteInvalidateResp 119813 # Transaction distribution 2893system.membus.trans_dist::UpgradeReq 367379 # Transaction distribution 2894system.membus.trans_dist::SCUpgradeReq 281461 # Transaction distribution 2895system.membus.trans_dist::UpgradeResp 85028 # Transaction distribution 2896system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution 2897system.membus.trans_dist::ReadExReq 87184 # Transaction distribution 2898system.membus.trans_dist::ReadExResp 72708 # Transaction distribution 2899system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123480 # Packet count per connected master and slave (bytes) 2900system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 2901system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 22714 # Packet count per connected master and slave (bytes) 2902system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4395675 # Packet count per connected master and slave (bytes) 2903system.membus.pkt_count_system.l2c.mem_side::total 4541961 # Packet count per connected master and slave (bytes) 2904system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336541 # Packet count per connected master and slave (bytes) 2905system.membus.pkt_count_system.iocache.mem_side::total 336541 # Packet count per connected master and slave (bytes) 2906system.membus.pkt_count::total 4878502 # Packet count per connected master and slave (bytes) 2907system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156518 # Cumulative packet size per connected master and slave (bytes) 2908system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 2909system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 45428 # Cumulative packet size per connected master and slave (bytes) 2910system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 143082804 # Cumulative packet size per connected master and slave (bytes) 2911system.membus.pkt_size_system.l2c.mem_side::total 143284954 # Cumulative packet size per connected master and slave (bytes) 2912system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14125504 # Cumulative packet size per connected master and slave (bytes) 2913system.membus.pkt_size_system.iocache.mem_side::total 14125504 # Cumulative packet size per connected master and slave (bytes) 2914system.membus.pkt_size::total 157410458 # Cumulative packet size per connected master and slave (bytes) 2915system.membus.snoops 581037 # Total snoops (count) 2916system.membus.snoop_fanout::samples 3119395 # Request fanout histogram 2917system.membus.snoop_fanout::mean 1 # Request fanout histogram 2918system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2919system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2920system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2921system.membus.snoop_fanout::1 3119395 100.00% 100.00% # Request fanout histogram 2922system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2923system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2924system.membus.snoop_fanout::min_value 1 # Request fanout histogram 2925system.membus.snoop_fanout::max_value 1 # Request fanout histogram 2926system.membus.snoop_fanout::total 3119395 # Request fanout histogram 2927system.membus.reqLayer0.occupancy 101251489 # Layer occupancy (ticks) 2928system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2929system.membus.reqLayer1.occupancy 55500 # Layer occupancy (ticks) 2930system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 2931system.membus.reqLayer2.occupancy 19693498 # Layer occupancy (ticks) 2932system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 2933system.membus.reqLayer5.occupancy 11963097483 # Layer occupancy (ticks) 2934system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 2935system.membus.respLayer2.occupancy 12443113804 # Layer occupancy (ticks) 2936system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 2937system.membus.respLayer3.occupancy 187409729 # Layer occupancy (ticks) 2938system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 2939system.realview.ethernet.txBytes 966 # Bytes Transmitted 2940system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 2941system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 2942system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 2943system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 2944system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2945system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2946system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2947system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2948system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 2949system.realview.ethernet.totPackets 3 # Total Packets 2950system.realview.ethernet.totBytes 966 # Total Bytes 2951system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 2952system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 2953system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 2954system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2955system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 2956system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 2957system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 2958system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 2959system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 2960system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 2961system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 2962system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 2963system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 2964system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 2965system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 2966system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 2967system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 2968system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 2969system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 2970system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 2971system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 2972system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 2973system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 2974system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2975system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2976system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 2977system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2978system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 2979system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 2980system.realview.ethernet.droppedPackets 0 # number of packets dropped 2981system.toL2Bus.trans_dist::ReadReq 7096727 # Transaction distribution 2982system.toL2Bus.trans_dist::ReadResp 7089473 # Transaction distribution 2983system.toL2Bus.trans_dist::WriteReq 37863 # Transaction distribution 2984system.toL2Bus.trans_dist::WriteResp 37863 # Transaction distribution 2985system.toL2Bus.trans_dist::Writeback 2477309 # Transaction distribution 2986system.toL2Bus.trans_dist::WriteInvalidateReq 127465 # Transaction distribution 2987system.toL2Bus.trans_dist::WriteInvalidateResp 20542 # Transaction distribution 2988system.toL2Bus.trans_dist::UpgradeReq 430421 # Transaction distribution 2989system.toL2Bus.trans_dist::SCUpgradeReq 297353 # Transaction distribution 2990system.toL2Bus.trans_dist::UpgradeResp 727774 # Transaction distribution 2991system.toL2Bus.trans_dist::SCUpgradeFailReq 53 # Transaction distribution 2992system.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution 2993system.toL2Bus.trans_dist::ReadExReq 228196 # Transaction distribution 2994system.toL2Bus.trans_dist::ReadExResp 228196 # Transaction distribution 2995system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8832957 # Packet count per connected master and slave (bytes) 2996system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8435767 # Packet count per connected master and slave (bytes) 2997system.toL2Bus.pkt_count::total 17268724 # Packet count per connected master and slave (bytes) 2998system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 294458407 # Cumulative packet size per connected master and slave (bytes) 2999system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 274483891 # Cumulative packet size per connected master and slave (bytes) 3000system.toL2Bus.pkt_size::total 568942298 # Cumulative packet size per connected master and slave (bytes) 3001system.toL2Bus.snoops 1532220 # Total snoops (count) 3002system.toL2Bus.snoop_fanout::samples 10576474 # Request fanout histogram 3003system.toL2Bus.snoop_fanout::mean 1.010952 # Request fanout histogram 3004system.toL2Bus.snoop_fanout::stdev 0.104077 # Request fanout histogram 3005system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3006system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3007system.toL2Bus.snoop_fanout::1 10460641 98.90% 98.90% # Request fanout histogram 3008system.toL2Bus.snoop_fanout::2 115833 1.10% 100.00% # Request fanout histogram 3009system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3010system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 3011system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3012system.toL2Bus.snoop_fanout::total 10576474 # Request fanout histogram 3013system.toL2Bus.reqLayer0.occupancy 15316484616 # Layer occupancy (ticks) 3014system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3015system.toL2Bus.snoopLayer0.occupancy 7440499 # Layer occupancy (ticks) 3016system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3017system.toL2Bus.respLayer0.occupancy 16737915607 # Layer occupancy (ticks) 3018system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3019system.toL2Bus.respLayer1.occupancy 16438547163 # Layer occupancy (ticks) 3020system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3021 3022---------- End Simulation Statistics ---------- 3023