stats.txt revision 10535
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.566016 # Number of seconds simulated 4sim_ticks 47566015848000 # Number of ticks simulated 5final_tick 47566015848000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 675626 # Simulator instruction rate (inst/s) 8host_op_rate 794684 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 35963293075 # Simulator tick rate (ticks/s) 10host_mem_usage 873656 # Number of bytes of host memory used 11host_seconds 1322.63 # Real time elapsed on the host 12sim_insts 893600449 # Number of instructions simulated 13sim_ops 1051070162 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 233408 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 408704 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 743028 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 13616152 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 28206528 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 271488 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 437568 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 534776 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 13513568 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 26761152 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 461312 # Number of bytes read from this memory 27system.physmem.bytes_read::total 85187684 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 743028 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 534776 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 1277804 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 43935424 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 56825292 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 43859652 # Number of bytes written to this memory 34system.physmem.bytes_written::realview.ide 6846976 # Number of bytes written to this memory 35system.physmem.bytes_written::total 151467344 # Number of bytes written to this memory 36system.physmem.num_reads::cpu0.dtb.walker 3647 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.itb.walker 6386 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.inst 52017 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.data 212774 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu0.l2cache.prefetcher 440727 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.dtb.walker 4242 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.itb.walker 6837 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.inst 8444 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.data 211164 # Number of read requests responded to by this memory 45system.physmem.num_reads::cpu1.l2cache.prefetcher 418143 # Number of read requests responded to by this memory 46system.physmem.num_reads::realview.ide 7208 # Number of read requests responded to by this memory 47system.physmem.num_reads::total 1371589 # Number of read requests responded to by this memory 48system.physmem.num_writes::writebacks 686491 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu0.data 890172 # Number of write requests responded to by this memory 50system.physmem.num_writes::cpu1.data 685308 # Number of write requests responded to by this memory 51system.physmem.num_writes::realview.ide 106984 # Number of write requests responded to by this memory 52system.physmem.num_writes::total 2368955 # Number of write requests responded to by this memory 53system.physmem.bw_read::cpu0.dtb.walker 4907 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.itb.walker 8592 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.inst 15621 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu0.data 286258 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu0.l2cache.prefetcher 592997 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.dtb.walker 5708 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.itb.walker 9199 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.inst 11243 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::cpu1.data 284101 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::cpu1.l2cache.prefetcher 562611 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_read::realview.ide 9698 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_read::total 1790936 # Total read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::cpu0.inst 15621 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_inst_read::cpu1.inst 11243 # Instruction read bandwidth from this memory (bytes/s) 67system.physmem.bw_inst_read::total 26864 # Instruction read bandwidth from this memory (bytes/s) 68system.physmem.bw_write::writebacks 923673 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::cpu0.data 1194662 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_write::cpu1.data 922080 # Write bandwidth from this memory (bytes/s) 71system.physmem.bw_write::realview.ide 143947 # Write bandwidth from this memory (bytes/s) 72system.physmem.bw_write::total 3184361 # Write bandwidth from this memory (bytes/s) 73system.physmem.bw_total::writebacks 923673 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.dtb.walker 4907 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.itb.walker 8592 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu0.inst 15621 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu0.data 1480920 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu0.l2cache.prefetcher 592997 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.dtb.walker 5708 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.itb.walker 9199 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::cpu1.inst 11243 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::cpu1.data 1206181 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::cpu1.l2cache.prefetcher 562611 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.bw_total::realview.ide 153645 # Total bandwidth to/from this memory (bytes/s) 85system.physmem.bw_total::total 4975296 # Total bandwidth to/from this memory (bytes/s) 86system.physmem.readReqs 1371589 # Number of read requests accepted 87system.physmem.writeReqs 2368955 # Number of write requests accepted 88system.physmem.readBursts 1371589 # Number of DRAM read bursts, including those serviced by the write queue 89system.physmem.writeBursts 2368955 # Number of DRAM write bursts, including those merged in the write queue 90system.physmem.bytesReadDRAM 87480576 # Total number of bytes read from DRAM 91system.physmem.bytesReadWrQ 301120 # Total number of bytes read from write queue 92system.physmem.bytesWritten 145871552 # Total number of bytes written to DRAM 93system.physmem.bytesReadSys 85187684 # Total read bytes from the system interface side 94system.physmem.bytesWrittenSys 151467344 # Total written bytes from the system interface side 95system.physmem.servicedByWrQ 4705 # Number of DRAM read bursts serviced by the write queue 96system.physmem.mergedWrBursts 89687 # Number of DRAM write bursts merged with an existing one 97system.physmem.neitherReadNorWriteReqs 96177 # Number of requests that are neither read nor write 98system.physmem.perBankRdBursts::0 85059 # Per bank write bursts 99system.physmem.perBankRdBursts::1 83413 # Per bank write bursts 100system.physmem.perBankRdBursts::2 77756 # Per bank write bursts 101system.physmem.perBankRdBursts::3 83623 # Per bank write bursts 102system.physmem.perBankRdBursts::4 79267 # Per bank write bursts 103system.physmem.perBankRdBursts::5 92440 # Per bank write bursts 104system.physmem.perBankRdBursts::6 79265 # Per bank write bursts 105system.physmem.perBankRdBursts::7 88179 # Per bank write bursts 106system.physmem.perBankRdBursts::8 75468 # Per bank write bursts 107system.physmem.perBankRdBursts::9 124700 # Per bank write bursts 108system.physmem.perBankRdBursts::10 77875 # Per bank write bursts 109system.physmem.perBankRdBursts::11 89966 # Per bank write bursts 110system.physmem.perBankRdBursts::12 78954 # Per bank write bursts 111system.physmem.perBankRdBursts::13 87199 # Per bank write bursts 112system.physmem.perBankRdBursts::14 85039 # Per bank write bursts 113system.physmem.perBankRdBursts::15 78681 # Per bank write bursts 114system.physmem.perBankWrBursts::0 146127 # Per bank write bursts 115system.physmem.perBankWrBursts::1 131230 # Per bank write bursts 116system.physmem.perBankWrBursts::2 144620 # Per bank write bursts 117system.physmem.perBankWrBursts::3 127213 # Per bank write bursts 118system.physmem.perBankWrBursts::4 148937 # Per bank write bursts 119system.physmem.perBankWrBursts::5 150009 # Per bank write bursts 120system.physmem.perBankWrBursts::6 182023 # Per bank write bursts 121system.physmem.perBankWrBursts::7 144700 # Per bank write bursts 122system.physmem.perBankWrBursts::8 124458 # Per bank write bursts 123system.physmem.perBankWrBursts::9 140305 # Per bank write bursts 124system.physmem.perBankWrBursts::10 119798 # Per bank write bursts 125system.physmem.perBankWrBursts::11 155853 # Per bank write bursts 126system.physmem.perBankWrBursts::12 153554 # Per bank write bursts 127system.physmem.perBankWrBursts::13 129042 # Per bank write bursts 128system.physmem.perBankWrBursts::14 144270 # Per bank write bursts 129system.physmem.perBankWrBursts::15 137104 # Per bank write bursts 130system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 131system.physmem.numWrRetry 9 # Number of times write queue was full causing retry 132system.physmem.totGap 47566012867000 # Total gap between requests 133system.physmem.readPktSize::0 0 # Read request sizes (log2) 134system.physmem.readPktSize::1 0 # Read request sizes (log2) 135system.physmem.readPktSize::2 43195 # Read request sizes (log2) 136system.physmem.readPktSize::3 37 # Read request sizes (log2) 137system.physmem.readPktSize::4 5 # Read request sizes (log2) 138system.physmem.readPktSize::5 0 # Read request sizes (log2) 139system.physmem.readPktSize::6 1328352 # Read request sizes (log2) 140system.physmem.writePktSize::0 0 # Write request sizes (log2) 141system.physmem.writePktSize::1 0 # Write request sizes (log2) 142system.physmem.writePktSize::2 2 # Write request sizes (log2) 143system.physmem.writePktSize::3 2601 # Write request sizes (log2) 144system.physmem.writePktSize::4 0 # Write request sizes (log2) 145system.physmem.writePktSize::5 0 # Write request sizes (log2) 146system.physmem.writePktSize::6 2366352 # Write request sizes (log2) 147system.physmem.rdQLenPdf::0 854051 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::1 158360 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::2 84564 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::3 68503 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::4 51448 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::5 44074 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::6 37830 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::7 31756 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::8 25068 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::9 4404 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::10 1973 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::11 1347 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::12 1006 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::13 782 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::14 591 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::15 416 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::16 292 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::17 229 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::18 108 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::19 76 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 176system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 177system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 178system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 179system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::15 89303 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::16 97776 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::17 118763 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::18 123056 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::19 124315 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::20 149365 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::21 133979 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::22 128880 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::23 131405 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::24 133820 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::25 133411 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::26 132599 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::27 131583 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::28 133798 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::29 128352 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::30 124285 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::31 123534 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::32 120195 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::33 5413 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::34 4121 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::35 2998 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::36 1739 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::37 869 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::38 468 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::39 407 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::40 384 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::41 347 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::42 335 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::43 331 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::44 336 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::45 334 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::46 315 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::47 294 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::48 297 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::49 244 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::50 213 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::51 197 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::52 193 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::53 197 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::54 171 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::55 144 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::56 128 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::57 98 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::58 84 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::59 59 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::60 42 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::61 33 # What write queue length does an incoming req see 241system.physmem.wrQLenPdf::62 21 # What write queue length does an incoming req see 242system.physmem.wrQLenPdf::63 22 # What write queue length does an incoming req see 243system.physmem.bytesPerActivate::samples 832768 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::mean 280.211728 # Bytes accessed per row activation 245system.physmem.bytesPerActivate::gmean 152.211424 # Bytes accessed per row activation 246system.physmem.bytesPerActivate::stdev 337.275385 # Bytes accessed per row activation 247system.physmem.bytesPerActivate::0-127 413524 49.66% 49.66% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::128-255 160093 19.22% 68.88% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::256-383 57236 6.87% 75.75% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::384-511 29306 3.52% 79.27% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::512-639 24972 3.00% 82.27% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::640-767 16042 1.93% 84.20% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::768-895 12534 1.51% 85.70% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::896-1023 12228 1.47% 87.17% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::1024-1151 106833 12.83% 100.00% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::total 832768 # Bytes accessed per row activation 257system.physmem.rdPerTurnAround::samples 117976 # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::mean 11.586017 # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::stdev 192.972695 # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::0-2047 117973 100.00% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::20480-22527 1 0.00% 100.00% # Reads before turning the bus around for writes 262system.physmem.rdPerTurnAround::24576-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 263system.physmem.rdPerTurnAround::57344-59391 1 0.00% 100.00% # Reads before turning the bus around for writes 264system.physmem.rdPerTurnAround::total 117976 # Reads before turning the bus around for writes 265system.physmem.wrPerTurnAround::samples 117976 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::mean 19.319548 # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::gmean 18.993188 # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::stdev 4.933657 # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::16-19 75459 63.96% 63.96% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::20-23 36712 31.12% 95.08% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::24-27 3025 2.56% 97.64% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::28-31 865 0.73% 98.38% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::32-35 773 0.66% 99.03% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::36-39 198 0.17% 99.20% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::40-43 143 0.12% 99.32% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::44-47 73 0.06% 99.38% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::48-51 88 0.07% 99.46% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::52-55 20 0.02% 99.47% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::56-59 14 0.01% 99.49% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::60-63 14 0.01% 99.50% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::64-67 383 0.32% 99.82% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::68-71 36 0.03% 99.85% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::72-75 51 0.04% 99.90% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::76-79 22 0.02% 99.92% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::80-83 46 0.04% 99.95% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::92-95 4 0.00% 99.96% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::96-99 9 0.01% 99.97% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::100-103 1 0.00% 99.97% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::104-107 5 0.00% 99.97% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::108-111 3 0.00% 99.97% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::112-115 6 0.01% 99.98% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::120-123 1 0.00% 99.98% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::124-127 1 0.00% 99.98% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::128-131 16 0.01% 99.99% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::132-135 1 0.00% 99.99% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::136-139 2 0.00% 100.00% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::140-143 4 0.00% 100.00% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::168-171 1 0.00% 100.00% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::total 117976 # Writes before turning the bus around for reads 300system.physmem.totQLat 39242427762 # Total ticks spent queuing 301system.physmem.totMemAccLat 64871502762 # Total ticks spent from burst creation until serviced by the DRAM 302system.physmem.totBusLat 6834420000 # Total ticks spent in databus transfers 303system.physmem.avgQLat 28709.41 # Average queueing delay per DRAM burst 304system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 305system.physmem.avgMemAccLat 47459.41 # Average memory access latency per DRAM burst 306system.physmem.avgRdBW 1.84 # Average DRAM read bandwidth in MiByte/s 307system.physmem.avgWrBW 3.07 # Average achieved write bandwidth in MiByte/s 308system.physmem.avgRdBWSys 1.79 # Average system read bandwidth in MiByte/s 309system.physmem.avgWrBWSys 3.18 # Average system write bandwidth in MiByte/s 310system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 311system.physmem.busUtil 0.04 # Data bus utilization in percentage 312system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 313system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 314system.physmem.avgRdQLen 1.32 # Average read queue length when enqueuing 315system.physmem.avgWrQLen 22.10 # Average write queue length when enqueuing 316system.physmem.readRowHits 1063781 # Number of row buffer hits during reads 317system.physmem.writeRowHits 1749574 # Number of row buffer hits during writes 318system.physmem.readRowHitRate 77.83 # Row buffer hit rate for reads 319system.physmem.writeRowHitRate 76.76 # Row buffer hit rate for writes 320system.physmem.avgGap 12716335.61 # Average gap between requests 321system.physmem.pageHitRate 77.16 # Row buffer hit rate, read and write combined 322system.physmem.memoryStateTime::IDLE 45509072189751 # Time in different power states 323system.physmem.memoryStateTime::REF 1588333760000 # Time in different power states 324system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 325system.physmem.memoryStateTime::ACT 468608703999 # Time in different power states 326system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 327system.physmem.actEnergy::0 3171472920 # Energy for activate commands per rank (pJ) 328system.physmem.actEnergy::1 3124253160 # Energy for activate commands per rank (pJ) 329system.physmem.preEnergy::0 1730466375 # Energy for precharge commands per rank (pJ) 330system.physmem.preEnergy::1 1704701625 # Energy for precharge commands per rank (pJ) 331system.physmem.readEnergy::0 5218192200 # Energy for read commands per rank (pJ) 332system.physmem.readEnergy::1 5443409400 # Energy for read commands per rank (pJ) 333system.physmem.writeEnergy::0 7613086320 # Energy for write commands per rank (pJ) 334system.physmem.writeEnergy::1 7156408320 # Energy for write commands per rank (pJ) 335system.physmem.refreshEnergy::0 3106780834560 # Energy for refresh commands per rank (pJ) 336system.physmem.refreshEnergy::1 3106780834560 # Energy for refresh commands per rank (pJ) 337system.physmem.actBackEnergy::0 1266482203425 # Energy for active background per rank (pJ) 338system.physmem.actBackEnergy::1 1265693181210 # Energy for active background per rank (pJ) 339system.physmem.preBackEnergy::0 27428659482750 # Energy for precharge background per rank (pJ) 340system.physmem.preBackEnergy::1 27429351607500 # Energy for precharge background per rank (pJ) 341system.physmem.totalEnergy::0 31819655738550 # Total energy per rank (pJ) 342system.physmem.totalEnergy::1 31819254395775 # Total energy per rank (pJ) 343system.physmem.averagePower::0 668.957784 # Core power per rank (mW) 344system.physmem.averagePower::1 668.949346 # Core power per rank (mW) 345system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 346system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 347system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 348system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 349system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 350system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 351system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 352system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 353system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 354system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 355system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 356system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 357system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 358system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 359system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 360system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 361system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 362system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 363system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 364system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 365system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 366system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 367system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 368system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 369system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 370system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 371system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 372system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 373system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 374system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. 375system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. 376system.cf0.dma_write_txs 1674 # Number of DMA write transactions. 377system.cpu_clk_domain.clock 500 # Clock period in ticks 378system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 379system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 380system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 381system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 382system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 383system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 384system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 385system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 386system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 387system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 388system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 389system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 390system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 391system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 392system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 393system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 394system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 395system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 396system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 397system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 398system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 399system.cpu0.dtb.inst_hits 0 # ITB inst hits 400system.cpu0.dtb.inst_misses 0 # ITB inst misses 401system.cpu0.dtb.read_hits 86716512 # DTB read hits 402system.cpu0.dtb.read_misses 82712 # DTB read misses 403system.cpu0.dtb.write_hits 78633728 # DTB write hits 404system.cpu0.dtb.write_misses 28389 # DTB write misses 405system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 406system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 407system.cpu0.dtb.flush_tlb_mva_asid 41884 # Number of times TLB was flushed by MVA & ASID 408system.cpu0.dtb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID 409system.cpu0.dtb.flush_entries 34135 # Number of entries that have been flushed from TLB 410system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 411system.cpu0.dtb.prefetch_faults 4682 # Number of TLB faults due to prefetch 412system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 413system.cpu0.dtb.perms_faults 9159 # Number of TLB faults due to permissions restrictions 414system.cpu0.dtb.read_accesses 86799224 # DTB read accesses 415system.cpu0.dtb.write_accesses 78662117 # DTB write accesses 416system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 417system.cpu0.dtb.hits 165350240 # DTB hits 418system.cpu0.dtb.misses 111101 # DTB misses 419system.cpu0.dtb.accesses 165461341 # DTB accesses 420system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 421system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 422system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 423system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 424system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 425system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 426system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 427system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 428system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 429system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 430system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 431system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 432system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 433system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 434system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 435system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 436system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 437system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 438system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 439system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 440system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 441system.cpu0.itb.inst_hits 459685693 # ITB inst hits 442system.cpu0.itb.inst_misses 60045 # ITB inst misses 443system.cpu0.itb.read_hits 0 # DTB read hits 444system.cpu0.itb.read_misses 0 # DTB read misses 445system.cpu0.itb.write_hits 0 # DTB write hits 446system.cpu0.itb.write_misses 0 # DTB write misses 447system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 448system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 449system.cpu0.itb.flush_tlb_mva_asid 41884 # Number of times TLB was flushed by MVA & ASID 450system.cpu0.itb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID 451system.cpu0.itb.flush_entries 24187 # Number of entries that have been flushed from TLB 452system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 453system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 454system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 455system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 456system.cpu0.itb.read_accesses 0 # DTB read accesses 457system.cpu0.itb.write_accesses 0 # DTB write accesses 458system.cpu0.itb.inst_accesses 459745738 # ITB inst accesses 459system.cpu0.itb.hits 459685693 # DTB hits 460system.cpu0.itb.misses 60045 # DTB misses 461system.cpu0.itb.accesses 459745738 # DTB accesses 462system.cpu0.numCycles 95132031682 # number of cpu cycles simulated 463system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 464system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 465system.cpu0.committedInsts 459439593 # Number of instructions committed 466system.cpu0.committedOps 539347874 # Number of ops (including micro ops) committed 467system.cpu0.num_int_alu_accesses 495403687 # Number of integer alu accesses 468system.cpu0.num_fp_alu_accesses 451172 # Number of float alu accesses 469system.cpu0.num_func_calls 27064307 # number of times a function call or return occured 470system.cpu0.num_conditional_control_insts 69711991 # number of instructions that are conditional controls 471system.cpu0.num_int_insts 495403687 # number of integer instructions 472system.cpu0.num_fp_insts 451172 # number of float instructions 473system.cpu0.num_int_register_reads 715734727 # number of times the integer registers were read 474system.cpu0.num_int_register_writes 392523746 # number of times the integer registers were written 475system.cpu0.num_fp_register_reads 749199 # number of times the floating registers were read 476system.cpu0.num_fp_register_writes 337216 # number of times the floating registers were written 477system.cpu0.num_cc_register_reads 119686995 # number of times the CC registers were read 478system.cpu0.num_cc_register_writes 119275623 # number of times the CC registers were written 479system.cpu0.num_mem_refs 165340768 # number of memory refs 480system.cpu0.num_load_insts 86711184 # Number of load instructions 481system.cpu0.num_store_insts 78629584 # Number of store instructions 482system.cpu0.num_idle_cycles 94014587829.536469 # Number of idle cycles 483system.cpu0.num_busy_cycles 1117443852.463529 # Number of busy cycles 484system.cpu0.not_idle_fraction 0.011746 # Percentage of non-idle cycles 485system.cpu0.idle_fraction 0.988254 # Percentage of idle cycles 486system.cpu0.Branches 102470244 # Number of branches fetched 487system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 488system.cpu0.op_class::IntAlu 373021399 69.12% 69.12% # Class of executed instruction 489system.cpu0.op_class::IntMult 1165287 0.22% 69.34% # Class of executed instruction 490system.cpu0.op_class::IntDiv 62749 0.01% 69.35% # Class of executed instruction 491system.cpu0.op_class::FloatAdd 0 0.00% 69.35% # Class of executed instruction 492system.cpu0.op_class::FloatCmp 0 0.00% 69.35% # Class of executed instruction 493system.cpu0.op_class::FloatCvt 0 0.00% 69.35% # Class of executed instruction 494system.cpu0.op_class::FloatMult 0 0.00% 69.35% # Class of executed instruction 495system.cpu0.op_class::FloatDiv 0 0.00% 69.35% # Class of executed instruction 496system.cpu0.op_class::FloatSqrt 0 0.00% 69.35% # Class of executed instruction 497system.cpu0.op_class::SimdAdd 0 0.00% 69.35% # Class of executed instruction 498system.cpu0.op_class::SimdAddAcc 0 0.00% 69.35% # Class of executed instruction 499system.cpu0.op_class::SimdAlu 0 0.00% 69.35% # Class of executed instruction 500system.cpu0.op_class::SimdCmp 0 0.00% 69.35% # Class of executed instruction 501system.cpu0.op_class::SimdCvt 0 0.00% 69.35% # Class of executed instruction 502system.cpu0.op_class::SimdMisc 0 0.00% 69.35% # Class of executed instruction 503system.cpu0.op_class::SimdMult 0 0.00% 69.35% # Class of executed instruction 504system.cpu0.op_class::SimdMultAcc 0 0.00% 69.35% # Class of executed instruction 505system.cpu0.op_class::SimdShift 0 0.00% 69.35% # Class of executed instruction 506system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.35% # Class of executed instruction 507system.cpu0.op_class::SimdSqrt 0 0.00% 69.35% # Class of executed instruction 508system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.35% # Class of executed instruction 509system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.35% # Class of executed instruction 510system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.35% # Class of executed instruction 511system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.35% # Class of executed instruction 512system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.35% # Class of executed instruction 513system.cpu0.op_class::SimdFloatMisc 46895 0.01% 69.36% # Class of executed instruction 514system.cpu0.op_class::SimdFloatMult 0 0.00% 69.36% # Class of executed instruction 515system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.36% # Class of executed instruction 516system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.36% # Class of executed instruction 517system.cpu0.op_class::MemRead 86711184 16.07% 85.43% # Class of executed instruction 518system.cpu0.op_class::MemWrite 78629584 14.57% 100.00% # Class of executed instruction 519system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 520system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 521system.cpu0.op_class::total 539637098 # Class of executed instruction 522system.cpu0.kern.inst.arm 0 # number of arm instructions executed 523system.cpu0.kern.inst.quiesce 5368 # number of quiesce instructions executed 524system.cpu0.dcache.tags.replacements 5553236 # number of replacements 525system.cpu0.dcache.tags.tagsinuse 507.463915 # Cycle average of tags in use 526system.cpu0.dcache.tags.total_refs 159572063 # Total number of references to valid blocks. 527system.cpu0.dcache.tags.sampled_refs 5553747 # Sample count of references to valid blocks. 528system.cpu0.dcache.tags.avg_refs 28.732325 # Average number of references to valid blocks. 529system.cpu0.dcache.tags.warmup_cycle 3644536500 # Cycle when the warmup percentage was hit. 530system.cpu0.dcache.tags.occ_blocks::cpu0.data 507.463915 # Average occupied blocks per requestor 531system.cpu0.dcache.tags.occ_percent::cpu0.data 0.991140 # Average percentage of cache occupancy 532system.cpu0.dcache.tags.occ_percent::total 0.991140 # Average percentage of cache occupancy 533system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 534system.cpu0.dcache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id 535system.cpu0.dcache.tags.age_task_id_blocks_1024::1 348 # Occupied blocks per task id 536system.cpu0.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id 537system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 538system.cpu0.dcache.tags.tag_accesses 336276505 # Number of tag accesses 539system.cpu0.dcache.tags.data_accesses 336276505 # Number of data accesses 540system.cpu0.dcache.ReadReq_hits::cpu0.data 80841388 # number of ReadReq hits 541system.cpu0.dcache.ReadReq_hits::total 80841388 # number of ReadReq hits 542system.cpu0.dcache.WriteReq_hits::cpu0.data 74354122 # number of WriteReq hits 543system.cpu0.dcache.WriteReq_hits::total 74354122 # number of WriteReq hits 544system.cpu0.dcache.SoftPFReq_hits::cpu0.data 186421 # number of SoftPFReq hits 545system.cpu0.dcache.SoftPFReq_hits::total 186421 # number of SoftPFReq hits 546system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 887570 # number of WriteInvalidateReq hits 547system.cpu0.dcache.WriteInvalidateReq_hits::total 887570 # number of WriteInvalidateReq hits 548system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1858688 # number of LoadLockedReq hits 549system.cpu0.dcache.LoadLockedReq_hits::total 1858688 # number of LoadLockedReq hits 550system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1820106 # number of StoreCondReq hits 551system.cpu0.dcache.StoreCondReq_hits::total 1820106 # number of StoreCondReq hits 552system.cpu0.dcache.demand_hits::cpu0.data 155195510 # number of demand (read+write) hits 553system.cpu0.dcache.demand_hits::total 155195510 # number of demand (read+write) hits 554system.cpu0.dcache.overall_hits::cpu0.data 155381931 # number of overall hits 555system.cpu0.dcache.overall_hits::total 155381931 # number of overall hits 556system.cpu0.dcache.ReadReq_misses::cpu0.data 3020518 # number of ReadReq misses 557system.cpu0.dcache.ReadReq_misses::total 3020518 # number of ReadReq misses 558system.cpu0.dcache.WriteReq_misses::cpu0.data 1355895 # number of WriteReq misses 559system.cpu0.dcache.WriteReq_misses::total 1355895 # number of WriteReq misses 560system.cpu0.dcache.SoftPFReq_misses::cpu0.data 638649 # number of SoftPFReq misses 561system.cpu0.dcache.SoftPFReq_misses::total 638649 # number of SoftPFReq misses 562system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 156836 # number of LoadLockedReq misses 563system.cpu0.dcache.LoadLockedReq_misses::total 156836 # number of LoadLockedReq misses 564system.cpu0.dcache.StoreCondReq_misses::cpu0.data 194186 # number of StoreCondReq misses 565system.cpu0.dcache.StoreCondReq_misses::total 194186 # number of StoreCondReq misses 566system.cpu0.dcache.demand_misses::cpu0.data 4376413 # number of demand (read+write) misses 567system.cpu0.dcache.demand_misses::total 4376413 # number of demand (read+write) misses 568system.cpu0.dcache.overall_misses::cpu0.data 5015062 # number of overall misses 569system.cpu0.dcache.overall_misses::total 5015062 # number of overall misses 570system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 44235181893 # number of ReadReq miss cycles 571system.cpu0.dcache.ReadReq_miss_latency::total 44235181893 # number of ReadReq miss cycles 572system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 23644478419 # number of WriteReq miss cycles 573system.cpu0.dcache.WriteReq_miss_latency::total 23644478419 # number of WriteReq miss cycles 574system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2243299062 # number of LoadLockedReq miss cycles 575system.cpu0.dcache.LoadLockedReq_miss_latency::total 2243299062 # number of LoadLockedReq miss cycles 576system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4135736633 # number of StoreCondReq miss cycles 577system.cpu0.dcache.StoreCondReq_miss_latency::total 4135736633 # number of StoreCondReq miss cycles 578system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1563000 # number of StoreCondFailReq miss cycles 579system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1563000 # number of StoreCondFailReq miss cycles 580system.cpu0.dcache.demand_miss_latency::cpu0.data 67879660312 # number of demand (read+write) miss cycles 581system.cpu0.dcache.demand_miss_latency::total 67879660312 # number of demand (read+write) miss cycles 582system.cpu0.dcache.overall_miss_latency::cpu0.data 67879660312 # number of overall miss cycles 583system.cpu0.dcache.overall_miss_latency::total 67879660312 # number of overall miss cycles 584system.cpu0.dcache.ReadReq_accesses::cpu0.data 83861906 # number of ReadReq accesses(hits+misses) 585system.cpu0.dcache.ReadReq_accesses::total 83861906 # number of ReadReq accesses(hits+misses) 586system.cpu0.dcache.WriteReq_accesses::cpu0.data 75710017 # number of WriteReq accesses(hits+misses) 587system.cpu0.dcache.WriteReq_accesses::total 75710017 # number of WriteReq accesses(hits+misses) 588system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 825070 # number of SoftPFReq accesses(hits+misses) 589system.cpu0.dcache.SoftPFReq_accesses::total 825070 # number of SoftPFReq accesses(hits+misses) 590system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 887570 # number of WriteInvalidateReq accesses(hits+misses) 591system.cpu0.dcache.WriteInvalidateReq_accesses::total 887570 # number of WriteInvalidateReq accesses(hits+misses) 592system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2015524 # number of LoadLockedReq accesses(hits+misses) 593system.cpu0.dcache.LoadLockedReq_accesses::total 2015524 # number of LoadLockedReq accesses(hits+misses) 594system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2014292 # number of StoreCondReq accesses(hits+misses) 595system.cpu0.dcache.StoreCondReq_accesses::total 2014292 # number of StoreCondReq accesses(hits+misses) 596system.cpu0.dcache.demand_accesses::cpu0.data 159571923 # number of demand (read+write) accesses 597system.cpu0.dcache.demand_accesses::total 159571923 # number of demand (read+write) accesses 598system.cpu0.dcache.overall_accesses::cpu0.data 160396993 # number of overall (read+write) accesses 599system.cpu0.dcache.overall_accesses::total 160396993 # number of overall (read+write) accesses 600system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036018 # miss rate for ReadReq accesses 601system.cpu0.dcache.ReadReq_miss_rate::total 0.036018 # miss rate for ReadReq accesses 602system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017909 # miss rate for WriteReq accesses 603system.cpu0.dcache.WriteReq_miss_rate::total 0.017909 # miss rate for WriteReq accesses 604system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.774054 # miss rate for SoftPFReq accesses 605system.cpu0.dcache.SoftPFReq_miss_rate::total 0.774054 # miss rate for SoftPFReq accesses 606system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.077814 # miss rate for LoadLockedReq accesses 607system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.077814 # miss rate for LoadLockedReq accesses 608system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.096404 # miss rate for StoreCondReq accesses 609system.cpu0.dcache.StoreCondReq_miss_rate::total 0.096404 # miss rate for StoreCondReq accesses 610system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027426 # miss rate for demand accesses 611system.cpu0.dcache.demand_miss_rate::total 0.027426 # miss rate for demand accesses 612system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031267 # miss rate for overall accesses 613system.cpu0.dcache.overall_miss_rate::total 0.031267 # miss rate for overall accesses 614system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14644.899283 # average ReadReq miss latency 615system.cpu0.dcache.ReadReq_avg_miss_latency::total 14644.899283 # average ReadReq miss latency 616system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17438.281297 # average WriteReq miss latency 617system.cpu0.dcache.WriteReq_avg_miss_latency::total 17438.281297 # average WriteReq miss latency 618system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14303.470262 # average LoadLockedReq miss latency 619system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14303.470262 # average LoadLockedReq miss latency 620system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21297.810517 # average StoreCondReq miss latency 621system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21297.810517 # average StoreCondReq miss latency 622system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 623system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 624system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15510.341531 # average overall miss latency 625system.cpu0.dcache.demand_avg_miss_latency::total 15510.341531 # average overall miss latency 626system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13535.158750 # average overall miss latency 627system.cpu0.dcache.overall_avg_miss_latency::total 13535.158750 # average overall miss latency 628system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 629system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 630system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 631system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 632system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 633system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 634system.cpu0.dcache.fast_writes 887570 # number of fast writes performed 635system.cpu0.dcache.cache_copies 0 # number of cache copies performed 636system.cpu0.dcache.writebacks::writebacks 3048439 # number of writebacks 637system.cpu0.dcache.writebacks::total 3048439 # number of writebacks 638system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 28957 # number of ReadReq MSHR hits 639system.cpu0.dcache.ReadReq_mshr_hits::total 28957 # number of ReadReq MSHR hits 640system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21342 # number of WriteReq MSHR hits 641system.cpu0.dcache.WriteReq_mshr_hits::total 21342 # number of WriteReq MSHR hits 642system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43075 # number of LoadLockedReq MSHR hits 643system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43075 # number of LoadLockedReq MSHR hits 644system.cpu0.dcache.demand_mshr_hits::cpu0.data 50299 # number of demand (read+write) MSHR hits 645system.cpu0.dcache.demand_mshr_hits::total 50299 # number of demand (read+write) MSHR hits 646system.cpu0.dcache.overall_mshr_hits::cpu0.data 50299 # number of overall MSHR hits 647system.cpu0.dcache.overall_mshr_hits::total 50299 # number of overall MSHR hits 648system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2991561 # number of ReadReq MSHR misses 649system.cpu0.dcache.ReadReq_mshr_misses::total 2991561 # number of ReadReq MSHR misses 650system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1334553 # number of WriteReq MSHR misses 651system.cpu0.dcache.WriteReq_mshr_misses::total 1334553 # number of WriteReq MSHR misses 652system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 637409 # number of SoftPFReq MSHR misses 653system.cpu0.dcache.SoftPFReq_mshr_misses::total 637409 # number of SoftPFReq MSHR misses 654system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 113761 # number of LoadLockedReq MSHR misses 655system.cpu0.dcache.LoadLockedReq_mshr_misses::total 113761 # number of LoadLockedReq MSHR misses 656system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 194186 # number of StoreCondReq MSHR misses 657system.cpu0.dcache.StoreCondReq_mshr_misses::total 194186 # number of StoreCondReq MSHR misses 658system.cpu0.dcache.demand_mshr_misses::cpu0.data 4326114 # number of demand (read+write) MSHR misses 659system.cpu0.dcache.demand_mshr_misses::total 4326114 # number of demand (read+write) MSHR misses 660system.cpu0.dcache.overall_mshr_misses::cpu0.data 4963523 # number of overall MSHR misses 661system.cpu0.dcache.overall_mshr_misses::total 4963523 # number of overall MSHR misses 662system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 36853741584 # number of ReadReq MSHR miss cycles 663system.cpu0.dcache.ReadReq_mshr_miss_latency::total 36853741584 # number of ReadReq MSHR miss cycles 664system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 20599874090 # number of WriteReq MSHR miss cycles 665system.cpu0.dcache.WriteReq_mshr_miss_latency::total 20599874090 # number of WriteReq MSHR miss cycles 666system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14249969925 # number of SoftPFReq MSHR miss cycles 667system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14249969925 # number of SoftPFReq MSHR miss cycles 668system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 39555111210 # number of WriteInvalidateReq MSHR miss cycles 669system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 39555111210 # number of WriteInvalidateReq MSHR miss cycles 670system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1322683967 # number of LoadLockedReq MSHR miss cycles 671system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1322683967 # number of LoadLockedReq MSHR miss cycles 672system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3736995367 # number of StoreCondReq MSHR miss cycles 673system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3736995367 # number of StoreCondReq MSHR miss cycles 674system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1491000 # number of StoreCondFailReq MSHR miss cycles 675system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1491000 # number of StoreCondFailReq MSHR miss cycles 676system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 57453615674 # number of demand (read+write) MSHR miss cycles 677system.cpu0.dcache.demand_mshr_miss_latency::total 57453615674 # number of demand (read+write) MSHR miss cycles 678system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 71703585599 # number of overall MSHR miss cycles 679system.cpu0.dcache.overall_mshr_miss_latency::total 71703585599 # number of overall MSHR miss cycles 680system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2269904707 # number of ReadReq MSHR uncacheable cycles 681system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2269904707 # number of ReadReq MSHR uncacheable cycles 682system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2228690449 # number of WriteReq MSHR uncacheable cycles 683system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2228690449 # number of WriteReq MSHR uncacheable cycles 684system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4498595156 # number of overall MSHR uncacheable cycles 685system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4498595156 # number of overall MSHR uncacheable cycles 686system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035672 # mshr miss rate for ReadReq accesses 687system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035672 # mshr miss rate for ReadReq accesses 688system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017627 # mshr miss rate for WriteReq accesses 689system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017627 # mshr miss rate for WriteReq accesses 690system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.772551 # mshr miss rate for SoftPFReq accesses 691system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.772551 # mshr miss rate for SoftPFReq accesses 692system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056442 # mshr miss rate for LoadLockedReq accesses 693system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056442 # mshr miss rate for LoadLockedReq accesses 694system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.096404 # mshr miss rate for StoreCondReq accesses 695system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.096404 # mshr miss rate for StoreCondReq accesses 696system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027111 # mshr miss rate for demand accesses 697system.cpu0.dcache.demand_mshr_miss_rate::total 0.027111 # mshr miss rate for demand accesses 698system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030945 # mshr miss rate for overall accesses 699system.cpu0.dcache.overall_mshr_miss_rate::total 0.030945 # mshr miss rate for overall accesses 700system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12319.234535 # average ReadReq mshr miss latency 701system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12319.234535 # average ReadReq mshr miss latency 702system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15435.785683 # average WriteReq mshr miss latency 703system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15435.785683 # average WriteReq mshr miss latency 704system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22356.085222 # average SoftPFReq mshr miss latency 705system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22356.085222 # average SoftPFReq mshr miss latency 706system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency 707system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 708system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11626.866562 # average LoadLockedReq mshr miss latency 709system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11626.866562 # average LoadLockedReq mshr miss latency 710system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19244.411889 # average StoreCondReq mshr miss latency 711system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19244.411889 # average StoreCondReq mshr miss latency 712system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 713system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 714system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13280.652261 # average overall mshr miss latency 715system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13280.652261 # average overall mshr miss latency 716system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14446.107251 # average overall mshr miss latency 717system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14446.107251 # average overall mshr miss latency 718system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 719system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 720system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 721system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 722system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 723system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 724system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 725system.cpu0.icache.tags.replacements 5136279 # number of replacements 726system.cpu0.icache.tags.tagsinuse 511.921269 # Cycle average of tags in use 727system.cpu0.icache.tags.total_refs 454548902 # Total number of references to valid blocks. 728system.cpu0.icache.tags.sampled_refs 5136791 # Sample count of references to valid blocks. 729system.cpu0.icache.tags.avg_refs 88.488884 # Average number of references to valid blocks. 730system.cpu0.icache.tags.warmup_cycle 24248022750 # Cycle when the warmup percentage was hit. 731system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.921269 # Average occupied blocks per requestor 732system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999846 # Average percentage of cache occupancy 733system.cpu0.icache.tags.occ_percent::total 0.999846 # Average percentage of cache occupancy 734system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 735system.cpu0.icache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id 736system.cpu0.icache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id 737system.cpu0.icache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id 738system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 739system.cpu0.icache.tags.tag_accesses 924508177 # Number of tag accesses 740system.cpu0.icache.tags.data_accesses 924508177 # Number of data accesses 741system.cpu0.icache.ReadReq_hits::cpu0.inst 454548902 # number of ReadReq hits 742system.cpu0.icache.ReadReq_hits::total 454548902 # number of ReadReq hits 743system.cpu0.icache.demand_hits::cpu0.inst 454548902 # number of demand (read+write) hits 744system.cpu0.icache.demand_hits::total 454548902 # number of demand (read+write) hits 745system.cpu0.icache.overall_hits::cpu0.inst 454548902 # number of overall hits 746system.cpu0.icache.overall_hits::total 454548902 # number of overall hits 747system.cpu0.icache.ReadReq_misses::cpu0.inst 5136791 # number of ReadReq misses 748system.cpu0.icache.ReadReq_misses::total 5136791 # number of ReadReq misses 749system.cpu0.icache.demand_misses::cpu0.inst 5136791 # number of demand (read+write) misses 750system.cpu0.icache.demand_misses::total 5136791 # number of demand (read+write) misses 751system.cpu0.icache.overall_misses::cpu0.inst 5136791 # number of overall misses 752system.cpu0.icache.overall_misses::total 5136791 # number of overall misses 753system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 44728233484 # number of ReadReq miss cycles 754system.cpu0.icache.ReadReq_miss_latency::total 44728233484 # number of ReadReq miss cycles 755system.cpu0.icache.demand_miss_latency::cpu0.inst 44728233484 # number of demand (read+write) miss cycles 756system.cpu0.icache.demand_miss_latency::total 44728233484 # number of demand (read+write) miss cycles 757system.cpu0.icache.overall_miss_latency::cpu0.inst 44728233484 # number of overall miss cycles 758system.cpu0.icache.overall_miss_latency::total 44728233484 # number of overall miss cycles 759system.cpu0.icache.ReadReq_accesses::cpu0.inst 459685693 # number of ReadReq accesses(hits+misses) 760system.cpu0.icache.ReadReq_accesses::total 459685693 # number of ReadReq accesses(hits+misses) 761system.cpu0.icache.demand_accesses::cpu0.inst 459685693 # number of demand (read+write) accesses 762system.cpu0.icache.demand_accesses::total 459685693 # number of demand (read+write) accesses 763system.cpu0.icache.overall_accesses::cpu0.inst 459685693 # number of overall (read+write) accesses 764system.cpu0.icache.overall_accesses::total 459685693 # number of overall (read+write) accesses 765system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011175 # miss rate for ReadReq accesses 766system.cpu0.icache.ReadReq_miss_rate::total 0.011175 # miss rate for ReadReq accesses 767system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011175 # miss rate for demand accesses 768system.cpu0.icache.demand_miss_rate::total 0.011175 # miss rate for demand accesses 769system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011175 # miss rate for overall accesses 770system.cpu0.icache.overall_miss_rate::total 0.011175 # miss rate for overall accesses 771system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8707.427163 # average ReadReq miss latency 772system.cpu0.icache.ReadReq_avg_miss_latency::total 8707.427163 # average ReadReq miss latency 773system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8707.427163 # average overall miss latency 774system.cpu0.icache.demand_avg_miss_latency::total 8707.427163 # average overall miss latency 775system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8707.427163 # average overall miss latency 776system.cpu0.icache.overall_avg_miss_latency::total 8707.427163 # average overall miss latency 777system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 778system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 779system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 780system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 781system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 782system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 783system.cpu0.icache.fast_writes 0 # number of fast writes performed 784system.cpu0.icache.cache_copies 0 # number of cache copies performed 785system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5136791 # number of ReadReq MSHR misses 786system.cpu0.icache.ReadReq_mshr_misses::total 5136791 # number of ReadReq MSHR misses 787system.cpu0.icache.demand_mshr_misses::cpu0.inst 5136791 # number of demand (read+write) MSHR misses 788system.cpu0.icache.demand_mshr_misses::total 5136791 # number of demand (read+write) MSHR misses 789system.cpu0.icache.overall_mshr_misses::cpu0.inst 5136791 # number of overall MSHR misses 790system.cpu0.icache.overall_mshr_misses::total 5136791 # number of overall MSHR misses 791system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 37020068050 # number of ReadReq MSHR miss cycles 792system.cpu0.icache.ReadReq_mshr_miss_latency::total 37020068050 # number of ReadReq MSHR miss cycles 793system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 37020068050 # number of demand (read+write) MSHR miss cycles 794system.cpu0.icache.demand_mshr_miss_latency::total 37020068050 # number of demand (read+write) MSHR miss cycles 795system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 37020068050 # number of overall MSHR miss cycles 796system.cpu0.icache.overall_mshr_miss_latency::total 37020068050 # number of overall MSHR miss cycles 797system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3405609750 # number of ReadReq MSHR uncacheable cycles 798system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3405609750 # number of ReadReq MSHR uncacheable cycles 799system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3405609750 # number of overall MSHR uncacheable cycles 800system.cpu0.icache.overall_mshr_uncacheable_latency::total 3405609750 # number of overall MSHR uncacheable cycles 801system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011175 # mshr miss rate for ReadReq accesses 802system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011175 # mshr miss rate for ReadReq accesses 803system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011175 # mshr miss rate for demand accesses 804system.cpu0.icache.demand_mshr_miss_rate::total 0.011175 # mshr miss rate for demand accesses 805system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011175 # mshr miss rate for overall accesses 806system.cpu0.icache.overall_mshr_miss_rate::total 0.011175 # mshr miss rate for overall accesses 807system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7206.847242 # average ReadReq mshr miss latency 808system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7206.847242 # average ReadReq mshr miss latency 809system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7206.847242 # average overall mshr miss latency 810system.cpu0.icache.demand_avg_mshr_miss_latency::total 7206.847242 # average overall mshr miss latency 811system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7206.847242 # average overall mshr miss latency 812system.cpu0.icache.overall_avg_mshr_miss_latency::total 7206.847242 # average overall mshr miss latency 813system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 814system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 815system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 816system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 817system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 818system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 47709911 # number of hwpf identified 819system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 798067 # number of hwpf that were already in mshr 820system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 44351595 # number of hwpf that were already in the cache 821system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 8146 # number of hwpf that were already in the prefetch queue 822system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 823system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 467 # number of hwpf removed because MSHR allocated 824system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 2551636 # number of hwpf issued 825system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 3941553 # number of hwpf spanning a virtual page 826system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 827system.cpu0.l2cache.tags.replacements 3159231 # number of replacements 828system.cpu0.l2cache.tags.tagsinuse 16263.767973 # Cycle average of tags in use 829system.cpu0.l2cache.tags.total_refs 10999510 # Total number of references to valid blocks. 830system.cpu0.l2cache.tags.sampled_refs 3175316 # Sample count of references to valid blocks. 831system.cpu0.l2cache.tags.avg_refs 3.464068 # Average number of references to valid blocks. 832system.cpu0.l2cache.tags.warmup_cycle 20647851500 # Cycle when the warmup percentage was hit. 833system.cpu0.l2cache.tags.occ_blocks::writebacks 3883.106993 # Average occupied blocks per requestor 834system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 48.905367 # Average occupied blocks per requestor 835system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 55.754013 # Average occupied blocks per requestor 836system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 900.341601 # Average occupied blocks per requestor 837system.cpu0.l2cache.tags.occ_blocks::cpu0.data 2586.177603 # Average occupied blocks per requestor 838system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 8789.482396 # Average occupied blocks per requestor 839system.cpu0.l2cache.tags.occ_percent::writebacks 0.237006 # Average percentage of cache occupancy 840system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002985 # Average percentage of cache occupancy 841system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003403 # Average percentage of cache occupancy 842system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.054952 # Average percentage of cache occupancy 843system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.157848 # Average percentage of cache occupancy 844system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.536467 # Average percentage of cache occupancy 845system.cpu0.l2cache.tags.occ_percent::total 0.992662 # Average percentage of cache occupancy 846system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8304 # Occupied blocks per task id 847system.cpu0.l2cache.tags.occ_task_id_blocks::1023 112 # Occupied blocks per task id 848system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7669 # Occupied blocks per task id 849system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 44 # Occupied blocks per task id 850system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 543 # Occupied blocks per task id 851system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 2171 # Occupied blocks per task id 852system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5264 # Occupied blocks per task id 853system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 282 # Occupied blocks per task id 854system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 10 # Occupied blocks per task id 855system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 43 # Occupied blocks per task id 856system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 59 # Occupied blocks per task id 857system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 858system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 738 # Occupied blocks per task id 859system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3430 # Occupied blocks per task id 860system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3305 # Occupied blocks per task id 861system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 150 # Occupied blocks per task id 862system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.506836 # Percentage of cache occupancy per task id 863system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006836 # Percentage of cache occupancy per task id 864system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.468079 # Percentage of cache occupancy per task id 865system.cpu0.l2cache.tags.tag_accesses 240919913 # Number of tag accesses 866system.cpu0.l2cache.tags.data_accesses 240919913 # Number of data accesses 867system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 231031 # number of ReadReq hits 868system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 134927 # number of ReadReq hits 869system.cpu0.l2cache.ReadReq_hits::cpu0.inst 4959117 # number of ReadReq hits 870system.cpu0.l2cache.ReadReq_hits::cpu0.data 2742170 # number of ReadReq hits 871system.cpu0.l2cache.ReadReq_hits::total 8067245 # number of ReadReq hits 872system.cpu0.l2cache.Writeback_hits::writebacks 3048439 # number of Writeback hits 873system.cpu0.l2cache.Writeback_hits::total 3048439 # number of Writeback hits 874system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 86825 # number of UpgradeReq hits 875system.cpu0.l2cache.UpgradeReq_hits::total 86825 # number of UpgradeReq hits 876system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 33826 # number of SCUpgradeReq hits 877system.cpu0.l2cache.SCUpgradeReq_hits::total 33826 # number of SCUpgradeReq hits 878system.cpu0.l2cache.ReadExReq_hits::cpu0.data 910939 # number of ReadExReq hits 879system.cpu0.l2cache.ReadExReq_hits::total 910939 # number of ReadExReq hits 880system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 231031 # number of demand (read+write) hits 881system.cpu0.l2cache.demand_hits::cpu0.itb.walker 134927 # number of demand (read+write) hits 882system.cpu0.l2cache.demand_hits::cpu0.inst 4959117 # number of demand (read+write) hits 883system.cpu0.l2cache.demand_hits::cpu0.data 3653109 # number of demand (read+write) hits 884system.cpu0.l2cache.demand_hits::total 8978184 # number of demand (read+write) hits 885system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 231031 # number of overall hits 886system.cpu0.l2cache.overall_hits::cpu0.itb.walker 134927 # number of overall hits 887system.cpu0.l2cache.overall_hits::cpu0.inst 4959117 # number of overall hits 888system.cpu0.l2cache.overall_hits::cpu0.data 3653109 # number of overall hits 889system.cpu0.l2cache.overall_hits::total 8978184 # number of overall hits 890system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12665 # number of ReadReq misses 891system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 11145 # number of ReadReq misses 892system.cpu0.l2cache.ReadReq_misses::cpu0.inst 177674 # number of ReadReq misses 893system.cpu0.l2cache.ReadReq_misses::cpu0.data 1000560 # number of ReadReq misses 894system.cpu0.l2cache.ReadReq_misses::total 1202044 # number of ReadReq misses 895system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 109590 # number of UpgradeReq misses 896system.cpu0.l2cache.UpgradeReq_misses::total 109590 # number of UpgradeReq misses 897system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 160357 # number of SCUpgradeReq misses 898system.cpu0.l2cache.SCUpgradeReq_misses::total 160357 # number of SCUpgradeReq misses 899system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 3 # number of SCUpgradeFailReq misses 900system.cpu0.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses 901system.cpu0.l2cache.ReadExReq_misses::cpu0.data 232216 # number of ReadExReq misses 902system.cpu0.l2cache.ReadExReq_misses::total 232216 # number of ReadExReq misses 903system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12665 # number of demand (read+write) misses 904system.cpu0.l2cache.demand_misses::cpu0.itb.walker 11145 # number of demand (read+write) misses 905system.cpu0.l2cache.demand_misses::cpu0.inst 177674 # number of demand (read+write) misses 906system.cpu0.l2cache.demand_misses::cpu0.data 1232776 # number of demand (read+write) misses 907system.cpu0.l2cache.demand_misses::total 1434260 # number of demand (read+write) misses 908system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12665 # number of overall misses 909system.cpu0.l2cache.overall_misses::cpu0.itb.walker 11145 # number of overall misses 910system.cpu0.l2cache.overall_misses::cpu0.inst 177674 # number of overall misses 911system.cpu0.l2cache.overall_misses::cpu0.data 1232776 # number of overall misses 912system.cpu0.l2cache.overall_misses::total 1434260 # number of overall misses 913system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 536996706 # number of ReadReq miss cycles 914system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 703824955 # number of ReadReq miss cycles 915system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 4673573829 # number of ReadReq miss cycles 916system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 32218538016 # number of ReadReq miss cycles 917system.cpu0.l2cache.ReadReq_miss_latency::total 38132933506 # number of ReadReq miss cycles 918system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2159798630 # number of UpgradeReq miss cycles 919system.cpu0.l2cache.UpgradeReq_miss_latency::total 2159798630 # number of UpgradeReq miss cycles 920system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3254740509 # number of SCUpgradeReq miss cycles 921system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3254740509 # number of SCUpgradeReq miss cycles 922system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1454999 # number of SCUpgradeFailReq miss cycles 923system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1454999 # number of SCUpgradeFailReq miss cycles 924system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 10558981803 # number of ReadExReq miss cycles 925system.cpu0.l2cache.ReadExReq_miss_latency::total 10558981803 # number of ReadExReq miss cycles 926system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 536996706 # number of demand (read+write) miss cycles 927system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 703824955 # number of demand (read+write) miss cycles 928system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4673573829 # number of demand (read+write) miss cycles 929system.cpu0.l2cache.demand_miss_latency::cpu0.data 42777519819 # number of demand (read+write) miss cycles 930system.cpu0.l2cache.demand_miss_latency::total 48691915309 # number of demand (read+write) miss cycles 931system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 536996706 # number of overall miss cycles 932system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 703824955 # number of overall miss cycles 933system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4673573829 # number of overall miss cycles 934system.cpu0.l2cache.overall_miss_latency::cpu0.data 42777519819 # number of overall miss cycles 935system.cpu0.l2cache.overall_miss_latency::total 48691915309 # number of overall miss cycles 936system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 243696 # number of ReadReq accesses(hits+misses) 937system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 146072 # number of ReadReq accesses(hits+misses) 938system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 5136791 # number of ReadReq accesses(hits+misses) 939system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3742730 # number of ReadReq accesses(hits+misses) 940system.cpu0.l2cache.ReadReq_accesses::total 9269289 # number of ReadReq accesses(hits+misses) 941system.cpu0.l2cache.Writeback_accesses::writebacks 3048439 # number of Writeback accesses(hits+misses) 942system.cpu0.l2cache.Writeback_accesses::total 3048439 # number of Writeback accesses(hits+misses) 943system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 196415 # number of UpgradeReq accesses(hits+misses) 944system.cpu0.l2cache.UpgradeReq_accesses::total 196415 # number of UpgradeReq accesses(hits+misses) 945system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 194183 # number of SCUpgradeReq accesses(hits+misses) 946system.cpu0.l2cache.SCUpgradeReq_accesses::total 194183 # number of SCUpgradeReq accesses(hits+misses) 947system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 3 # number of SCUpgradeFailReq accesses(hits+misses) 948system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) 949system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1143155 # number of ReadExReq accesses(hits+misses) 950system.cpu0.l2cache.ReadExReq_accesses::total 1143155 # number of ReadExReq accesses(hits+misses) 951system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 243696 # number of demand (read+write) accesses 952system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 146072 # number of demand (read+write) accesses 953system.cpu0.l2cache.demand_accesses::cpu0.inst 5136791 # number of demand (read+write) accesses 954system.cpu0.l2cache.demand_accesses::cpu0.data 4885885 # number of demand (read+write) accesses 955system.cpu0.l2cache.demand_accesses::total 10412444 # number of demand (read+write) accesses 956system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 243696 # number of overall (read+write) accesses 957system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 146072 # number of overall (read+write) accesses 958system.cpu0.l2cache.overall_accesses::cpu0.inst 5136791 # number of overall (read+write) accesses 959system.cpu0.l2cache.overall_accesses::cpu0.data 4885885 # number of overall (read+write) accesses 960system.cpu0.l2cache.overall_accesses::total 10412444 # number of overall (read+write) accesses 961system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.051970 # miss rate for ReadReq accesses 962system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.076298 # miss rate for ReadReq accesses 963system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.034589 # miss rate for ReadReq accesses 964system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.267334 # miss rate for ReadReq accesses 965system.cpu0.l2cache.ReadReq_miss_rate::total 0.129680 # miss rate for ReadReq accesses 966system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.557951 # miss rate for UpgradeReq accesses 967system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.557951 # miss rate for UpgradeReq accesses 968system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.825803 # miss rate for SCUpgradeReq accesses 969system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.825803 # miss rate for SCUpgradeReq accesses 970system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 971system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 972system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.203136 # miss rate for ReadExReq accesses 973system.cpu0.l2cache.ReadExReq_miss_rate::total 0.203136 # miss rate for ReadExReq accesses 974system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.051970 # miss rate for demand accesses 975system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.076298 # miss rate for demand accesses 976system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.034589 # miss rate for demand accesses 977system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.252314 # miss rate for demand accesses 978system.cpu0.l2cache.demand_miss_rate::total 0.137745 # miss rate for demand accesses 979system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.051970 # miss rate for overall accesses 980system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.076298 # miss rate for overall accesses 981system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.034589 # miss rate for overall accesses 982system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.252314 # miss rate for overall accesses 983system.cpu0.l2cache.overall_miss_rate::total 0.137745 # miss rate for overall accesses 984system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 42400.055744 # average ReadReq miss latency 985system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 63151.633468 # average ReadReq miss latency 986system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 26304.207869 # average ReadReq miss latency 987system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 32200.505733 # average ReadReq miss latency 988system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31723.409048 # average ReadReq miss latency 989system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 19707.990054 # average UpgradeReq miss latency 990system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 19707.990054 # average UpgradeReq miss latency 991system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20296.840855 # average SCUpgradeReq miss latency 992system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20296.840855 # average SCUpgradeReq miss latency 993system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 484999.666667 # average SCUpgradeFailReq miss latency 994system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 484999.666667 # average SCUpgradeFailReq miss latency 995system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 45470.517979 # average ReadExReq miss latency 996system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 45470.517979 # average ReadExReq miss latency 997system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 42400.055744 # average overall miss latency 998system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 63151.633468 # average overall miss latency 999system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 26304.207869 # average overall miss latency 1000system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 34700.156248 # average overall miss latency 1001system.cpu0.l2cache.demand_avg_miss_latency::total 33949.155180 # average overall miss latency 1002system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 42400.055744 # average overall miss latency 1003system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 63151.633468 # average overall miss latency 1004system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 26304.207869 # average overall miss latency 1005system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 34700.156248 # average overall miss latency 1006system.cpu0.l2cache.overall_avg_miss_latency::total 33949.155180 # average overall miss latency 1007system.cpu0.l2cache.blocked_cycles::no_mshrs 12605 # number of cycles access was blocked 1008system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1009system.cpu0.l2cache.blocked::no_mshrs 256 # number of cycles access was blocked 1010system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1011system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 49.238281 # average number of cycles each access was blocked 1012system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1013system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1014system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1015system.cpu0.l2cache.writebacks::writebacks 1033934 # number of writebacks 1016system.cpu0.l2cache.writebacks::total 1033934 # number of writebacks 1017system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 26777 # number of ReadReq MSHR hits 1018system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 5375 # number of ReadReq MSHR hits 1019system.cpu0.l2cache.ReadReq_mshr_hits::total 32152 # number of ReadReq MSHR hits 1020system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 4949 # number of ReadExReq MSHR hits 1021system.cpu0.l2cache.ReadExReq_mshr_hits::total 4949 # number of ReadExReq MSHR hits 1022system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 26777 # number of demand (read+write) MSHR hits 1023system.cpu0.l2cache.demand_mshr_hits::cpu0.data 10324 # number of demand (read+write) MSHR hits 1024system.cpu0.l2cache.demand_mshr_hits::total 37101 # number of demand (read+write) MSHR hits 1025system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 26777 # number of overall MSHR hits 1026system.cpu0.l2cache.overall_mshr_hits::cpu0.data 10324 # number of overall MSHR hits 1027system.cpu0.l2cache.overall_mshr_hits::total 37101 # number of overall MSHR hits 1028system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 12665 # number of ReadReq MSHR misses 1029system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 11145 # number of ReadReq MSHR misses 1030system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 150897 # number of ReadReq MSHR misses 1031system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 995185 # number of ReadReq MSHR misses 1032system.cpu0.l2cache.ReadReq_mshr_misses::total 1169892 # number of ReadReq MSHR misses 1033system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 2551548 # number of HardPFReq MSHR misses 1034system.cpu0.l2cache.HardPFReq_mshr_misses::total 2551548 # number of HardPFReq MSHR misses 1035system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 109590 # number of UpgradeReq MSHR misses 1036system.cpu0.l2cache.UpgradeReq_mshr_misses::total 109590 # number of UpgradeReq MSHR misses 1037system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 160357 # number of SCUpgradeReq MSHR misses 1038system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 160357 # number of SCUpgradeReq MSHR misses 1039system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 3 # number of SCUpgradeFailReq MSHR misses 1040system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses 1041system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 227267 # number of ReadExReq MSHR misses 1042system.cpu0.l2cache.ReadExReq_mshr_misses::total 227267 # number of ReadExReq MSHR misses 1043system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 12665 # number of demand (read+write) MSHR misses 1044system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 11145 # number of demand (read+write) MSHR misses 1045system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 150897 # number of demand (read+write) MSHR misses 1046system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1222452 # number of demand (read+write) MSHR misses 1047system.cpu0.l2cache.demand_mshr_misses::total 1397159 # number of demand (read+write) MSHR misses 1048system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 12665 # number of overall MSHR misses 1049system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 11145 # number of overall MSHR misses 1050system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 150897 # number of overall MSHR misses 1051system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1222452 # number of overall MSHR misses 1052system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 2551548 # number of overall MSHR misses 1053system.cpu0.l2cache.overall_mshr_misses::total 3948707 # number of overall MSHR misses 1054system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 447628804 # number of ReadReq MSHR miss cycles 1055system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 624653553 # number of ReadReq MSHR miss cycles 1056system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 3182608268 # number of ReadReq MSHR miss cycles 1057system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 25035600452 # number of ReadReq MSHR miss cycles 1058system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 29290491077 # number of ReadReq MSHR miss cycles 1059system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 74439584886 # number of HardPFReq MSHR miss cycles 1060system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 74439584886 # number of HardPFReq MSHR miss cycles 1061system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 32897037766 # number of WriteInvalidateReq MSHR miss cycles 1062system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 32897037766 # number of WriteInvalidateReq MSHR miss cycles 1063system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1861391719 # number of UpgradeReq MSHR miss cycles 1064system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1861391719 # number of UpgradeReq MSHR miss cycles 1065system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2218823079 # number of SCUpgradeReq MSHR miss cycles 1066system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2218823079 # number of SCUpgradeReq MSHR miss cycles 1067system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1202999 # number of SCUpgradeFailReq MSHR miss cycles 1068system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1202999 # number of SCUpgradeFailReq MSHR miss cycles 1069system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 8430579619 # number of ReadExReq MSHR miss cycles 1070system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 8430579619 # number of ReadExReq MSHR miss cycles 1071system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 447628804 # number of demand (read+write) MSHR miss cycles 1072system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 624653553 # number of demand (read+write) MSHR miss cycles 1073system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3182608268 # number of demand (read+write) MSHR miss cycles 1074system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 33466180071 # number of demand (read+write) MSHR miss cycles 1075system.cpu0.l2cache.demand_mshr_miss_latency::total 37721070696 # number of demand (read+write) MSHR miss cycles 1076system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 447628804 # number of overall MSHR miss cycles 1077system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 624653553 # number of overall MSHR miss cycles 1078system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3182608268 # number of overall MSHR miss cycles 1079system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 33466180071 # number of overall MSHR miss cycles 1080system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 74439584886 # number of overall MSHR miss cycles 1081system.cpu0.l2cache.overall_mshr_miss_latency::total 112160655582 # number of overall MSHR miss cycles 1082system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3061864750 # number of ReadReq MSHR uncacheable cycles 1083system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2157592792 # number of ReadReq MSHR uncacheable cycles 1084system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5219457542 # number of ReadReq MSHR uncacheable cycles 1085system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2114914551 # number of WriteReq MSHR uncacheable cycles 1086system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2114914551 # number of WriteReq MSHR uncacheable cycles 1087system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3061864750 # number of overall MSHR uncacheable cycles 1088system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4272507343 # number of overall MSHR uncacheable cycles 1089system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7334372093 # number of overall MSHR uncacheable cycles 1090system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.051970 # mshr miss rate for ReadReq accesses 1091system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.076298 # mshr miss rate for ReadReq accesses 1092system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.029376 # mshr miss rate for ReadReq accesses 1093system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.265898 # mshr miss rate for ReadReq accesses 1094system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.126212 # mshr miss rate for ReadReq accesses 1095system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1096system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1097system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.557951 # mshr miss rate for UpgradeReq accesses 1098system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.557951 # mshr miss rate for UpgradeReq accesses 1099system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.825803 # mshr miss rate for SCUpgradeReq accesses 1100system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.825803 # mshr miss rate for SCUpgradeReq accesses 1101system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1102system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1103system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.198807 # mshr miss rate for ReadExReq accesses 1104system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.198807 # mshr miss rate for ReadExReq accesses 1105system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.051970 # mshr miss rate for demand accesses 1106system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.076298 # mshr miss rate for demand accesses 1107system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.029376 # mshr miss rate for demand accesses 1108system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.250201 # mshr miss rate for demand accesses 1109system.cpu0.l2cache.demand_mshr_miss_rate::total 0.134182 # mshr miss rate for demand accesses 1110system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.051970 # mshr miss rate for overall accesses 1111system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.076298 # mshr miss rate for overall accesses 1112system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.029376 # mshr miss rate for overall accesses 1113system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.250201 # mshr miss rate for overall accesses 1114system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1115system.cpu0.l2cache.overall_mshr_miss_rate::total 0.379230 # mshr miss rate for overall accesses 1116system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 35343.766601 # average ReadReq mshr miss latency 1117system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 56047.873755 # average ReadReq mshr miss latency 1118system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 21091.262702 # average ReadReq mshr miss latency 1119system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 25156.730107 # average ReadReq mshr miss latency 1120system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25036.918858 # average ReadReq mshr miss latency 1121system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 29174.283567 # average HardPFReq mshr miss latency 1122system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 29174.283567 # average HardPFReq mshr miss latency 1123system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency 1124system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 1125system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16985.050817 # average UpgradeReq mshr miss latency 1126system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16985.050817 # average UpgradeReq mshr miss latency 1127system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13836.770949 # average SCUpgradeReq mshr miss latency 1128system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13836.770949 # average SCUpgradeReq mshr miss latency 1129system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 400999.666667 # average SCUpgradeFailReq mshr miss latency 1130system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 400999.666667 # average SCUpgradeFailReq mshr miss latency 1131system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 37095.485130 # average ReadExReq mshr miss latency 1132system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 37095.485130 # average ReadExReq mshr miss latency 1133system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 35343.766601 # average overall mshr miss latency 1134system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 56047.873755 # average overall mshr miss latency 1135system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 21091.262702 # average overall mshr miss latency 1136system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27376.273319 # average overall mshr miss latency 1137system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26998.409412 # average overall mshr miss latency 1138system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 35343.766601 # average overall mshr miss latency 1139system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 56047.873755 # average overall mshr miss latency 1140system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 21091.262702 # average overall mshr miss latency 1141system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27376.273319 # average overall mshr miss latency 1142system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 29174.283567 # average overall mshr miss latency 1143system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 28404.400626 # average overall mshr miss latency 1144system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1145system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1146system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1147system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1148system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1149system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1150system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1151system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1152system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1153system.cpu0.toL2Bus.trans_dist::ReadReq 12709886 # Transaction distribution 1154system.cpu0.toL2Bus.trans_dist::ReadResp 9530898 # Transaction distribution 1155system.cpu0.toL2Bus.trans_dist::WriteReq 15163 # Transaction distribution 1156system.cpu0.toL2Bus.trans_dist::WriteResp 15163 # Transaction distribution 1157system.cpu0.toL2Bus.trans_dist::Writeback 3048439 # Transaction distribution 1158system.cpu0.toL2Bus.trans_dist::HardPFReq 3732092 # Transaction distribution 1159system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1679869 # Transaction distribution 1160system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 887570 # Transaction distribution 1161system.cpu0.toL2Bus.trans_dist::UpgradeReq 380241 # Transaction distribution 1162system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 351950 # Transaction distribution 1163system.cpu0.toL2Bus.trans_dist::UpgradeResp 457079 # Transaction distribution 1164system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 47 # Transaction distribution 1165system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 80 # Transaction distribution 1166system.cpu0.toL2Bus.trans_dist::ReadExReq 1289201 # Transaction distribution 1167system.cpu0.toL2Bus.trans_dist::ReadExResp 1150842 # Transaction distribution 1168system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 10359832 # Packet count per connected master and slave (bytes) 1169system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15601688 # Packet count per connected master and slave (bytes) 1170system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 325277 # Packet count per connected master and slave (bytes) 1171system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 566209 # Packet count per connected master and slave (bytes) 1172system.cpu0.toL2Bus.pkt_count::total 26853006 # Packet count per connected master and slave (bytes) 1173system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 328927124 # Cumulative packet size per connected master and slave (bytes) 1174system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 571100341 # Cumulative packet size per connected master and slave (bytes) 1175system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1168576 # Cumulative packet size per connected master and slave (bytes) 1176system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1949568 # Cumulative packet size per connected master and slave (bytes) 1177system.cpu0.toL2Bus.pkt_size::total 903145609 # Cumulative packet size per connected master and slave (bytes) 1178system.cpu0.toL2Bus.snoops 8562261 # Total snoops (count) 1179system.cpu0.toL2Bus.snoop_fanout::samples 23134597 # Request fanout histogram 1180system.cpu0.toL2Bus.snoop_fanout::mean 5.358060 # Request fanout histogram 1181system.cpu0.toL2Bus.snoop_fanout::stdev 0.479430 # Request fanout histogram 1182system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1183system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1184system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1185system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1186system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1187system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1188system.cpu0.toL2Bus.snoop_fanout::5 14851033 64.19% 64.19% # Request fanout histogram 1189system.cpu0.toL2Bus.snoop_fanout::6 8283564 35.81% 100.00% # Request fanout histogram 1190system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1191system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1192system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1193system.cpu0.toL2Bus.snoop_fanout::total 23134597 # Request fanout histogram 1194system.cpu0.toL2Bus.reqLayer0.occupancy 11405856452 # Layer occupancy (ticks) 1195system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 1196system.cpu0.toL2Bus.snoopLayer0.occupancy 183601993 # Layer occupancy (ticks) 1197system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1198system.cpu0.toL2Bus.respLayer0.occupancy 7759954717 # Layer occupancy (ticks) 1199system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1200system.cpu0.toL2Bus.respLayer1.occupancy 8048372726 # Layer occupancy (ticks) 1201system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1202system.cpu0.toL2Bus.respLayer2.occupancy 179758799 # Layer occupancy (ticks) 1203system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1204system.cpu0.toL2Bus.respLayer3.occupancy 322845049 # Layer occupancy (ticks) 1205system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1206system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1207system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1208system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1209system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1210system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1211system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1212system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1213system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1214system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1215system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1216system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1217system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1218system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1219system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1220system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1221system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1222system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1223system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1224system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1225system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1226system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1227system.cpu1.dtb.inst_hits 0 # ITB inst hits 1228system.cpu1.dtb.inst_misses 0 # ITB inst misses 1229system.cpu1.dtb.read_hits 81769828 # DTB read hits 1230system.cpu1.dtb.read_misses 79673 # DTB read misses 1231system.cpu1.dtb.write_hits 74311746 # DTB write hits 1232system.cpu1.dtb.write_misses 27355 # DTB write misses 1233system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1234system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1235system.cpu1.dtb.flush_tlb_mva_asid 41884 # Number of times TLB was flushed by MVA & ASID 1236system.cpu1.dtb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID 1237system.cpu1.dtb.flush_entries 41105 # Number of entries that have been flushed from TLB 1238system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 1239system.cpu1.dtb.prefetch_faults 4547 # Number of TLB faults due to prefetch 1240system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1241system.cpu1.dtb.perms_faults 10770 # Number of TLB faults due to permissions restrictions 1242system.cpu1.dtb.read_accesses 81849501 # DTB read accesses 1243system.cpu1.dtb.write_accesses 74339101 # DTB write accesses 1244system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1245system.cpu1.dtb.hits 156081574 # DTB hits 1246system.cpu1.dtb.misses 107028 # DTB misses 1247system.cpu1.dtb.accesses 156188602 # DTB accesses 1248system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1249system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1250system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1251system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1252system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1253system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1254system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1255system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1256system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1257system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1258system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1259system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1260system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1261system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1262system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1263system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1264system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1265system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1266system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1267system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1268system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1269system.cpu1.itb.inst_hits 434473512 # ITB inst hits 1270system.cpu1.itb.inst_misses 57336 # ITB inst misses 1271system.cpu1.itb.read_hits 0 # DTB read hits 1272system.cpu1.itb.read_misses 0 # DTB read misses 1273system.cpu1.itb.write_hits 0 # DTB write hits 1274system.cpu1.itb.write_misses 0 # DTB write misses 1275system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1276system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1277system.cpu1.itb.flush_tlb_mva_asid 41884 # Number of times TLB was flushed by MVA & ASID 1278system.cpu1.itb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID 1279system.cpu1.itb.flush_entries 28749 # Number of entries that have been flushed from TLB 1280system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1281system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1282system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1283system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1284system.cpu1.itb.read_accesses 0 # DTB read accesses 1285system.cpu1.itb.write_accesses 0 # DTB write accesses 1286system.cpu1.itb.inst_accesses 434530848 # ITB inst accesses 1287system.cpu1.itb.hits 434473512 # DTB hits 1288system.cpu1.itb.misses 57336 # DTB misses 1289system.cpu1.itb.accesses 434530848 # DTB accesses 1290system.cpu1.numCycles 95132031696 # number of cpu cycles simulated 1291system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1292system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1293system.cpu1.committedInsts 434160856 # Number of instructions committed 1294system.cpu1.committedOps 511722288 # Number of ops (including micro ops) committed 1295system.cpu1.num_int_alu_accesses 470175639 # Number of integer alu accesses 1296system.cpu1.num_fp_alu_accesses 456535 # Number of float alu accesses 1297system.cpu1.num_func_calls 26230713 # number of times a function call or return occured 1298system.cpu1.num_conditional_control_insts 66122636 # number of instructions that are conditional controls 1299system.cpu1.num_int_insts 470175639 # number of integer instructions 1300system.cpu1.num_fp_insts 456535 # number of float instructions 1301system.cpu1.num_int_register_reads 688104482 # number of times the integer registers were read 1302system.cpu1.num_int_register_writes 373632663 # number of times the integer registers were written 1303system.cpu1.num_fp_register_reads 726332 # number of times the floating registers were read 1304system.cpu1.num_fp_register_writes 408756 # number of times the floating registers were written 1305system.cpu1.num_cc_register_reads 113709240 # number of times the CC registers were read 1306system.cpu1.num_cc_register_writes 113476936 # number of times the CC registers were written 1307system.cpu1.num_mem_refs 156073929 # number of memory refs 1308system.cpu1.num_load_insts 81768358 # Number of load instructions 1309system.cpu1.num_store_insts 74305571 # Number of store instructions 1310system.cpu1.num_idle_cycles 94082707842.004028 # Number of idle cycles 1311system.cpu1.num_busy_cycles 1049323853.995978 # Number of busy cycles 1312system.cpu1.not_idle_fraction 0.011030 # Percentage of non-idle cycles 1313system.cpu1.idle_fraction 0.988970 # Percentage of idle cycles 1314system.cpu1.Branches 96877428 # Number of branches fetched 1315system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 1316system.cpu1.op_class::IntAlu 354755827 69.28% 69.28% # Class of executed instruction 1317system.cpu1.op_class::IntMult 1081291 0.21% 69.49% # Class of executed instruction 1318system.cpu1.op_class::IntDiv 57437 0.01% 69.51% # Class of executed instruction 1319system.cpu1.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction 1320system.cpu1.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction 1321system.cpu1.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction 1322system.cpu1.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction 1323system.cpu1.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction 1324system.cpu1.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction 1325system.cpu1.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction 1326system.cpu1.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction 1327system.cpu1.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction 1328system.cpu1.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction 1329system.cpu1.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction 1330system.cpu1.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction 1331system.cpu1.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction 1332system.cpu1.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction 1333system.cpu1.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction 1334system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction 1335system.cpu1.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction 1336system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.51% # Class of executed instruction 1337system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction 1338system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.51% # Class of executed instruction 1339system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.51% # Class of executed instruction 1340system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction 1341system.cpu1.op_class::SimdFloatMisc 66526 0.01% 69.52% # Class of executed instruction 1342system.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction 1343system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction 1344system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction 1345system.cpu1.op_class::MemRead 81768358 15.97% 85.49% # Class of executed instruction 1346system.cpu1.op_class::MemWrite 74305571 14.51% 100.00% # Class of executed instruction 1347system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1348system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 1349system.cpu1.op_class::total 512035053 # Class of executed instruction 1350system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1351system.cpu1.kern.inst.quiesce 13728 # number of quiesce instructions executed 1352system.cpu1.dcache.tags.replacements 5229569 # number of replacements 1353system.cpu1.dcache.tags.tagsinuse 446.555743 # Cycle average of tags in use 1354system.cpu1.dcache.tags.total_refs 150635340 # Total number of references to valid blocks. 1355system.cpu1.dcache.tags.sampled_refs 5230081 # Sample count of references to valid blocks. 1356system.cpu1.dcache.tags.avg_refs 28.801722 # Average number of references to valid blocks. 1357system.cpu1.dcache.tags.warmup_cycle 8374220312000 # Cycle when the warmup percentage was hit. 1358system.cpu1.dcache.tags.occ_blocks::cpu1.data 446.555743 # Average occupied blocks per requestor 1359system.cpu1.dcache.tags.occ_percent::cpu1.data 0.872179 # Average percentage of cache occupancy 1360system.cpu1.dcache.tags.occ_percent::total 0.872179 # Average percentage of cache occupancy 1361system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1362system.cpu1.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id 1363system.cpu1.dcache.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id 1364system.cpu1.dcache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id 1365system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1366system.cpu1.dcache.tags.tag_accesses 317363377 # Number of tag accesses 1367system.cpu1.dcache.tags.data_accesses 317363377 # Number of data accesses 1368system.cpu1.dcache.ReadReq_hits::cpu1.data 76086699 # number of ReadReq hits 1369system.cpu1.dcache.ReadReq_hits::total 76086699 # number of ReadReq hits 1370system.cpu1.dcache.WriteReq_hits::cpu1.data 70396756 # number of WriteReq hits 1371system.cpu1.dcache.WriteReq_hits::total 70396756 # number of WriteReq hits 1372system.cpu1.dcache.SoftPFReq_hits::cpu1.data 188905 # number of SoftPFReq hits 1373system.cpu1.dcache.SoftPFReq_hits::total 188905 # number of SoftPFReq hits 1374system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 685307 # number of WriteInvalidateReq hits 1375system.cpu1.dcache.WriteInvalidateReq_hits::total 685307 # number of WriteInvalidateReq hits 1376system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1701097 # number of LoadLockedReq hits 1377system.cpu1.dcache.LoadLockedReq_hits::total 1701097 # number of LoadLockedReq hits 1378system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1676869 # number of StoreCondReq hits 1379system.cpu1.dcache.StoreCondReq_hits::total 1676869 # number of StoreCondReq hits 1380system.cpu1.dcache.demand_hits::cpu1.data 146483455 # number of demand (read+write) hits 1381system.cpu1.dcache.demand_hits::total 146483455 # number of demand (read+write) hits 1382system.cpu1.dcache.overall_hits::cpu1.data 146672360 # number of overall hits 1383system.cpu1.dcache.overall_hits::total 146672360 # number of overall hits 1384system.cpu1.dcache.ReadReq_misses::cpu1.data 2949268 # number of ReadReq misses 1385system.cpu1.dcache.ReadReq_misses::total 2949268 # number of ReadReq misses 1386system.cpu1.dcache.WriteReq_misses::cpu1.data 1324938 # number of WriteReq misses 1387system.cpu1.dcache.WriteReq_misses::total 1324938 # number of WriteReq misses 1388system.cpu1.dcache.SoftPFReq_misses::cpu1.data 648778 # number of SoftPFReq misses 1389system.cpu1.dcache.SoftPFReq_misses::total 648778 # number of SoftPFReq misses 1390system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 170596 # number of LoadLockedReq misses 1391system.cpu1.dcache.LoadLockedReq_misses::total 170596 # number of LoadLockedReq misses 1392system.cpu1.dcache.StoreCondReq_misses::cpu1.data 193531 # number of StoreCondReq misses 1393system.cpu1.dcache.StoreCondReq_misses::total 193531 # number of StoreCondReq misses 1394system.cpu1.dcache.demand_misses::cpu1.data 4274206 # number of demand (read+write) misses 1395system.cpu1.dcache.demand_misses::total 4274206 # number of demand (read+write) misses 1396system.cpu1.dcache.overall_misses::cpu1.data 4922984 # number of overall misses 1397system.cpu1.dcache.overall_misses::total 4922984 # number of overall misses 1398system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 43925732439 # number of ReadReq miss cycles 1399system.cpu1.dcache.ReadReq_miss_latency::total 43925732439 # number of ReadReq miss cycles 1400system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 22816644952 # number of WriteReq miss cycles 1401system.cpu1.dcache.WriteReq_miss_latency::total 22816644952 # number of WriteReq miss cycles 1402system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2487645065 # number of LoadLockedReq miss cycles 1403system.cpu1.dcache.LoadLockedReq_miss_latency::total 2487645065 # number of LoadLockedReq miss cycles 1404system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4103865813 # number of StoreCondReq miss cycles 1405system.cpu1.dcache.StoreCondReq_miss_latency::total 4103865813 # number of StoreCondReq miss cycles 1406system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1896000 # number of StoreCondFailReq miss cycles 1407system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1896000 # number of StoreCondFailReq miss cycles 1408system.cpu1.dcache.demand_miss_latency::cpu1.data 66742377391 # number of demand (read+write) miss cycles 1409system.cpu1.dcache.demand_miss_latency::total 66742377391 # number of demand (read+write) miss cycles 1410system.cpu1.dcache.overall_miss_latency::cpu1.data 66742377391 # number of overall miss cycles 1411system.cpu1.dcache.overall_miss_latency::total 66742377391 # number of overall miss cycles 1412system.cpu1.dcache.ReadReq_accesses::cpu1.data 79035967 # number of ReadReq accesses(hits+misses) 1413system.cpu1.dcache.ReadReq_accesses::total 79035967 # number of ReadReq accesses(hits+misses) 1414system.cpu1.dcache.WriteReq_accesses::cpu1.data 71721694 # number of WriteReq accesses(hits+misses) 1415system.cpu1.dcache.WriteReq_accesses::total 71721694 # number of WriteReq accesses(hits+misses) 1416system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 837683 # number of SoftPFReq accesses(hits+misses) 1417system.cpu1.dcache.SoftPFReq_accesses::total 837683 # number of SoftPFReq accesses(hits+misses) 1418system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 685307 # number of WriteInvalidateReq accesses(hits+misses) 1419system.cpu1.dcache.WriteInvalidateReq_accesses::total 685307 # number of WriteInvalidateReq accesses(hits+misses) 1420system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1871693 # number of LoadLockedReq accesses(hits+misses) 1421system.cpu1.dcache.LoadLockedReq_accesses::total 1871693 # number of LoadLockedReq accesses(hits+misses) 1422system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1870400 # number of StoreCondReq accesses(hits+misses) 1423system.cpu1.dcache.StoreCondReq_accesses::total 1870400 # number of StoreCondReq accesses(hits+misses) 1424system.cpu1.dcache.demand_accesses::cpu1.data 150757661 # number of demand (read+write) accesses 1425system.cpu1.dcache.demand_accesses::total 150757661 # number of demand (read+write) accesses 1426system.cpu1.dcache.overall_accesses::cpu1.data 151595344 # number of overall (read+write) accesses 1427system.cpu1.dcache.overall_accesses::total 151595344 # number of overall (read+write) accesses 1428system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037316 # miss rate for ReadReq accesses 1429system.cpu1.dcache.ReadReq_miss_rate::total 0.037316 # miss rate for ReadReq accesses 1430system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018473 # miss rate for WriteReq accesses 1431system.cpu1.dcache.WriteReq_miss_rate::total 0.018473 # miss rate for WriteReq accesses 1432system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.774491 # miss rate for SoftPFReq accesses 1433system.cpu1.dcache.SoftPFReq_miss_rate::total 0.774491 # miss rate for SoftPFReq accesses 1434system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.091145 # miss rate for LoadLockedReq accesses 1435system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.091145 # miss rate for LoadLockedReq accesses 1436system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103470 # miss rate for StoreCondReq accesses 1437system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103470 # miss rate for StoreCondReq accesses 1438system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028352 # miss rate for demand accesses 1439system.cpu1.dcache.demand_miss_rate::total 0.028352 # miss rate for demand accesses 1440system.cpu1.dcache.overall_miss_rate::cpu1.data 0.032475 # miss rate for overall accesses 1441system.cpu1.dcache.overall_miss_rate::total 0.032475 # miss rate for overall accesses 1442system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14893.774468 # average ReadReq miss latency 1443system.cpu1.dcache.ReadReq_avg_miss_latency::total 14893.774468 # average ReadReq miss latency 1444system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17220.915207 # average WriteReq miss latency 1445system.cpu1.dcache.WriteReq_avg_miss_latency::total 17220.915207 # average WriteReq miss latency 1446system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14582.083197 # average LoadLockedReq miss latency 1447system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14582.083197 # average LoadLockedReq miss latency 1448system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21205.211635 # average StoreCondReq miss latency 1449system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21205.211635 # average StoreCondReq miss latency 1450system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1451system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1452system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15615.152239 # average overall miss latency 1453system.cpu1.dcache.demand_avg_miss_latency::total 15615.152239 # average overall miss latency 1454system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13557.301302 # average overall miss latency 1455system.cpu1.dcache.overall_avg_miss_latency::total 13557.301302 # average overall miss latency 1456system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1457system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1458system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1459system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1460system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1461system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1462system.cpu1.dcache.fast_writes 685307 # number of fast writes performed 1463system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1464system.cpu1.dcache.writebacks::writebacks 2978181 # number of writebacks 1465system.cpu1.dcache.writebacks::total 2978181 # number of writebacks 1466system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 23865 # number of ReadReq MSHR hits 1467system.cpu1.dcache.ReadReq_mshr_hits::total 23865 # number of ReadReq MSHR hits 1468system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 515 # number of WriteReq MSHR hits 1469system.cpu1.dcache.WriteReq_mshr_hits::total 515 # number of WriteReq MSHR hits 1470system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 45192 # number of LoadLockedReq MSHR hits 1471system.cpu1.dcache.LoadLockedReq_mshr_hits::total 45192 # number of LoadLockedReq MSHR hits 1472system.cpu1.dcache.demand_mshr_hits::cpu1.data 24380 # number of demand (read+write) MSHR hits 1473system.cpu1.dcache.demand_mshr_hits::total 24380 # number of demand (read+write) MSHR hits 1474system.cpu1.dcache.overall_mshr_hits::cpu1.data 24380 # number of overall MSHR hits 1475system.cpu1.dcache.overall_mshr_hits::total 24380 # number of overall MSHR hits 1476system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2925403 # number of ReadReq MSHR misses 1477system.cpu1.dcache.ReadReq_mshr_misses::total 2925403 # number of ReadReq MSHR misses 1478system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1324423 # number of WriteReq MSHR misses 1479system.cpu1.dcache.WriteReq_mshr_misses::total 1324423 # number of WriteReq MSHR misses 1480system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 648778 # number of SoftPFReq MSHR misses 1481system.cpu1.dcache.SoftPFReq_mshr_misses::total 648778 # number of SoftPFReq MSHR misses 1482system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 125404 # number of LoadLockedReq MSHR misses 1483system.cpu1.dcache.LoadLockedReq_mshr_misses::total 125404 # number of LoadLockedReq MSHR misses 1484system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193531 # number of StoreCondReq MSHR misses 1485system.cpu1.dcache.StoreCondReq_mshr_misses::total 193531 # number of StoreCondReq MSHR misses 1486system.cpu1.dcache.demand_mshr_misses::cpu1.data 4249826 # number of demand (read+write) MSHR misses 1487system.cpu1.dcache.demand_mshr_misses::total 4249826 # number of demand (read+write) MSHR misses 1488system.cpu1.dcache.overall_mshr_misses::cpu1.data 4898604 # number of overall MSHR misses 1489system.cpu1.dcache.overall_mshr_misses::total 4898604 # number of overall MSHR misses 1490system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 36900792539 # number of ReadReq MSHR miss cycles 1491system.cpu1.dcache.ReadReq_mshr_miss_latency::total 36900792539 # number of ReadReq MSHR miss cycles 1492system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 20082419307 # number of WriteReq MSHR miss cycles 1493system.cpu1.dcache.WriteReq_mshr_miss_latency::total 20082419307 # number of WriteReq MSHR miss cycles 1494system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13833136236 # number of SoftPFReq MSHR miss cycles 1495system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13833136236 # number of SoftPFReq MSHR miss cycles 1496system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 30583171682 # number of WriteInvalidateReq MSHR miss cycles 1497system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 30583171682 # number of WriteInvalidateReq MSHR miss cycles 1498system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1453819204 # number of LoadLockedReq MSHR miss cycles 1499system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1453819204 # number of LoadLockedReq MSHR miss cycles 1500system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3706136187 # number of StoreCondReq MSHR miss cycles 1501system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3706136187 # number of StoreCondReq MSHR miss cycles 1502system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1808000 # number of StoreCondFailReq MSHR miss cycles 1503system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1808000 # number of StoreCondFailReq MSHR miss cycles 1504system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 56983211846 # number of demand (read+write) MSHR miss cycles 1505system.cpu1.dcache.demand_mshr_miss_latency::total 56983211846 # number of demand (read+write) MSHR miss cycles 1506system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 70816348082 # number of overall MSHR miss cycles 1507system.cpu1.dcache.overall_mshr_miss_latency::total 70816348082 # number of overall MSHR miss cycles 1508system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4114514480 # number of ReadReq MSHR uncacheable cycles 1509system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4114514480 # number of ReadReq MSHR uncacheable cycles 1510system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3994198470 # number of WriteReq MSHR uncacheable cycles 1511system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3994198470 # number of WriteReq MSHR uncacheable cycles 1512system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 8108712950 # number of overall MSHR uncacheable cycles 1513system.cpu1.dcache.overall_mshr_uncacheable_latency::total 8108712950 # number of overall MSHR uncacheable cycles 1514system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037014 # mshr miss rate for ReadReq accesses 1515system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037014 # mshr miss rate for ReadReq accesses 1516system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018466 # mshr miss rate for WriteReq accesses 1517system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018466 # mshr miss rate for WriteReq accesses 1518system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.774491 # mshr miss rate for SoftPFReq accesses 1519system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.774491 # mshr miss rate for SoftPFReq accesses 1520system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067000 # mshr miss rate for LoadLockedReq accesses 1521system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067000 # mshr miss rate for LoadLockedReq accesses 1522system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103470 # mshr miss rate for StoreCondReq accesses 1523system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103470 # mshr miss rate for StoreCondReq accesses 1524system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028190 # mshr miss rate for demand accesses 1525system.cpu1.dcache.demand_mshr_miss_rate::total 0.028190 # mshr miss rate for demand accesses 1526system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032314 # mshr miss rate for overall accesses 1527system.cpu1.dcache.overall_mshr_miss_rate::total 0.032314 # mshr miss rate for overall accesses 1528system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12613.917651 # average ReadReq mshr miss latency 1529system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12613.917651 # average ReadReq mshr miss latency 1530system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15163.145994 # average WriteReq mshr miss latency 1531system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15163.145994 # average WriteReq mshr miss latency 1532system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21321.833102 # average SoftPFReq mshr miss latency 1533system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21321.833102 # average SoftPFReq mshr miss latency 1534system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency 1535system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 1536system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11593.084782 # average LoadLockedReq mshr miss latency 1537system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11593.084782 # average LoadLockedReq mshr miss latency 1538system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19150.090616 # average StoreCondReq mshr miss latency 1539system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19150.090616 # average StoreCondReq mshr miss latency 1540system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1541system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1542system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13408.363506 # average overall mshr miss latency 1543system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13408.363506 # average overall mshr miss latency 1544system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14456.434544 # average overall mshr miss latency 1545system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14456.434544 # average overall mshr miss latency 1546system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1547system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1548system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1549system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1550system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1551system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1552system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1553system.cpu1.icache.tags.replacements 4838786 # number of replacements 1554system.cpu1.icache.tags.tagsinuse 496.335132 # Cycle average of tags in use 1555system.cpu1.icache.tags.total_refs 429634209 # Total number of references to valid blocks. 1556system.cpu1.icache.tags.sampled_refs 4839298 # Sample count of references to valid blocks. 1557system.cpu1.icache.tags.avg_refs 88.780275 # Average number of references to valid blocks. 1558system.cpu1.icache.tags.warmup_cycle 8374030789000 # Cycle when the warmup percentage was hit. 1559system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.335132 # Average occupied blocks per requestor 1560system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969405 # Average percentage of cache occupancy 1561system.cpu1.icache.tags.occ_percent::total 0.969405 # Average percentage of cache occupancy 1562system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1563system.cpu1.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id 1564system.cpu1.icache.tags.age_task_id_blocks_1024::1 281 # Occupied blocks per task id 1565system.cpu1.icache.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id 1566system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id 1567system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1568system.cpu1.icache.tags.tag_accesses 873786327 # Number of tag accesses 1569system.cpu1.icache.tags.data_accesses 873786327 # Number of data accesses 1570system.cpu1.icache.ReadReq_hits::cpu1.inst 429634209 # number of ReadReq hits 1571system.cpu1.icache.ReadReq_hits::total 429634209 # number of ReadReq hits 1572system.cpu1.icache.demand_hits::cpu1.inst 429634209 # number of demand (read+write) hits 1573system.cpu1.icache.demand_hits::total 429634209 # number of demand (read+write) hits 1574system.cpu1.icache.overall_hits::cpu1.inst 429634209 # number of overall hits 1575system.cpu1.icache.overall_hits::total 429634209 # number of overall hits 1576system.cpu1.icache.ReadReq_misses::cpu1.inst 4839303 # number of ReadReq misses 1577system.cpu1.icache.ReadReq_misses::total 4839303 # number of ReadReq misses 1578system.cpu1.icache.demand_misses::cpu1.inst 4839303 # number of demand (read+write) misses 1579system.cpu1.icache.demand_misses::total 4839303 # number of demand (read+write) misses 1580system.cpu1.icache.overall_misses::cpu1.inst 4839303 # number of overall misses 1581system.cpu1.icache.overall_misses::total 4839303 # number of overall misses 1582system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 42201450669 # number of ReadReq miss cycles 1583system.cpu1.icache.ReadReq_miss_latency::total 42201450669 # number of ReadReq miss cycles 1584system.cpu1.icache.demand_miss_latency::cpu1.inst 42201450669 # number of demand (read+write) miss cycles 1585system.cpu1.icache.demand_miss_latency::total 42201450669 # number of demand (read+write) miss cycles 1586system.cpu1.icache.overall_miss_latency::cpu1.inst 42201450669 # number of overall miss cycles 1587system.cpu1.icache.overall_miss_latency::total 42201450669 # number of overall miss cycles 1588system.cpu1.icache.ReadReq_accesses::cpu1.inst 434473512 # number of ReadReq accesses(hits+misses) 1589system.cpu1.icache.ReadReq_accesses::total 434473512 # number of ReadReq accesses(hits+misses) 1590system.cpu1.icache.demand_accesses::cpu1.inst 434473512 # number of demand (read+write) accesses 1591system.cpu1.icache.demand_accesses::total 434473512 # number of demand (read+write) accesses 1592system.cpu1.icache.overall_accesses::cpu1.inst 434473512 # number of overall (read+write) accesses 1593system.cpu1.icache.overall_accesses::total 434473512 # number of overall (read+write) accesses 1594system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011138 # miss rate for ReadReq accesses 1595system.cpu1.icache.ReadReq_miss_rate::total 0.011138 # miss rate for ReadReq accesses 1596system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011138 # miss rate for demand accesses 1597system.cpu1.icache.demand_miss_rate::total 0.011138 # miss rate for demand accesses 1598system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011138 # miss rate for overall accesses 1599system.cpu1.icache.overall_miss_rate::total 0.011138 # miss rate for overall accesses 1600system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8720.563823 # average ReadReq miss latency 1601system.cpu1.icache.ReadReq_avg_miss_latency::total 8720.563823 # average ReadReq miss latency 1602system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8720.563823 # average overall miss latency 1603system.cpu1.icache.demand_avg_miss_latency::total 8720.563823 # average overall miss latency 1604system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8720.563823 # average overall miss latency 1605system.cpu1.icache.overall_avg_miss_latency::total 8720.563823 # average overall miss latency 1606system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1607system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1608system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1609system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1610system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1611system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1612system.cpu1.icache.fast_writes 0 # number of fast writes performed 1613system.cpu1.icache.cache_copies 0 # number of cache copies performed 1614system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4839303 # number of ReadReq MSHR misses 1615system.cpu1.icache.ReadReq_mshr_misses::total 4839303 # number of ReadReq MSHR misses 1616system.cpu1.icache.demand_mshr_misses::cpu1.inst 4839303 # number of demand (read+write) MSHR misses 1617system.cpu1.icache.demand_mshr_misses::total 4839303 # number of demand (read+write) MSHR misses 1618system.cpu1.icache.overall_mshr_misses::cpu1.inst 4839303 # number of overall MSHR misses 1619system.cpu1.icache.overall_mshr_misses::total 4839303 # number of overall MSHR misses 1620system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 34939638885 # number of ReadReq MSHR miss cycles 1621system.cpu1.icache.ReadReq_mshr_miss_latency::total 34939638885 # number of ReadReq MSHR miss cycles 1622system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 34939638885 # number of demand (read+write) MSHR miss cycles 1623system.cpu1.icache.demand_mshr_miss_latency::total 34939638885 # number of demand (read+write) MSHR miss cycles 1624system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 34939638885 # number of overall MSHR miss cycles 1625system.cpu1.icache.overall_mshr_miss_latency::total 34939638885 # number of overall MSHR miss cycles 1626system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8745500 # number of ReadReq MSHR uncacheable cycles 1627system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8745500 # number of ReadReq MSHR uncacheable cycles 1628system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8745500 # number of overall MSHR uncacheable cycles 1629system.cpu1.icache.overall_mshr_uncacheable_latency::total 8745500 # number of overall MSHR uncacheable cycles 1630system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011138 # mshr miss rate for ReadReq accesses 1631system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011138 # mshr miss rate for ReadReq accesses 1632system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011138 # mshr miss rate for demand accesses 1633system.cpu1.icache.demand_mshr_miss_rate::total 0.011138 # mshr miss rate for demand accesses 1634system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011138 # mshr miss rate for overall accesses 1635system.cpu1.icache.overall_mshr_miss_rate::total 0.011138 # mshr miss rate for overall accesses 1636system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7219.973390 # average ReadReq mshr miss latency 1637system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7219.973390 # average ReadReq mshr miss latency 1638system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7219.973390 # average overall mshr miss latency 1639system.cpu1.icache.demand_avg_mshr_miss_latency::total 7219.973390 # average overall mshr miss latency 1640system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7219.973390 # average overall mshr miss latency 1641system.cpu1.icache.overall_avg_mshr_miss_latency::total 7219.973390 # average overall mshr miss latency 1642system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1643system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1644system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1645system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1646system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1647system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 45129085 # number of hwpf identified 1648system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 818764 # number of hwpf that were already in mshr 1649system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 41906843 # number of hwpf that were already in the cache 1650system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 8141 # number of hwpf that were already in the prefetch queue 1651system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 1652system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 514 # number of hwpf removed because MSHR allocated 1653system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 2394823 # number of hwpf issued 1654system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 3842139 # number of hwpf spanning a virtual page 1655system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 1656system.cpu1.l2cache.tags.replacements 3029134 # number of replacements 1657system.cpu1.l2cache.tags.tagsinuse 13674.379805 # Cycle average of tags in use 1658system.cpu1.l2cache.tags.total_refs 10606046 # Total number of references to valid blocks. 1659system.cpu1.l2cache.tags.sampled_refs 3045261 # Sample count of references to valid blocks. 1660system.cpu1.l2cache.tags.avg_refs 3.482804 # Average number of references to valid blocks. 1661system.cpu1.l2cache.tags.warmup_cycle 10454752865000 # Cycle when the warmup percentage was hit. 1662system.cpu1.l2cache.tags.occ_blocks::writebacks 4179.016177 # Average occupied blocks per requestor 1663system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 54.517433 # Average occupied blocks per requestor 1664system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 70.326677 # Average occupied blocks per requestor 1665system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 591.513668 # Average occupied blocks per requestor 1666system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3188.927208 # Average occupied blocks per requestor 1667system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 5590.078642 # Average occupied blocks per requestor 1668system.cpu1.l2cache.tags.occ_percent::writebacks 0.255067 # Average percentage of cache occupancy 1669system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003327 # Average percentage of cache occupancy 1670system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004292 # Average percentage of cache occupancy 1671system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.036103 # Average percentage of cache occupancy 1672system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.194637 # Average percentage of cache occupancy 1673system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.341191 # Average percentage of cache occupancy 1674system.cpu1.l2cache.tags.occ_percent::total 0.834618 # Average percentage of cache occupancy 1675system.cpu1.l2cache.tags.occ_task_id_blocks::1022 8556 # Occupied blocks per task id 1676system.cpu1.l2cache.tags.occ_task_id_blocks::1023 61 # Occupied blocks per task id 1677system.cpu1.l2cache.tags.occ_task_id_blocks::1024 7510 # Occupied blocks per task id 1678system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 76 # Occupied blocks per task id 1679system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 438 # Occupied blocks per task id 1680system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 3359 # Occupied blocks per task id 1681system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 4072 # Occupied blocks per task id 1682system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 611 # Occupied blocks per task id 1683system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id 1684system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id 1685system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 24 # Occupied blocks per task id 1686system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 28 # Occupied blocks per task id 1687system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id 1688system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 34 # Occupied blocks per task id 1689system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 492 # Occupied blocks per task id 1690system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2836 # Occupied blocks per task id 1691system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 3841 # Occupied blocks per task id 1692system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 307 # Occupied blocks per task id 1693system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.522217 # Percentage of cache occupancy per task id 1694system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003723 # Percentage of cache occupancy per task id 1695system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.458374 # Percentage of cache occupancy per task id 1696system.cpu1.l2cache.tags.tag_accesses 230495604 # Number of tag accesses 1697system.cpu1.l2cache.tags.data_accesses 230495604 # Number of data accesses 1698system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 221576 # number of ReadReq hits 1699system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 129888 # number of ReadReq hits 1700system.cpu1.l2cache.ReadReq_hits::cpu1.inst 4667071 # number of ReadReq hits 1701system.cpu1.l2cache.ReadReq_hits::cpu1.data 2714218 # number of ReadReq hits 1702system.cpu1.l2cache.ReadReq_hits::total 7732753 # number of ReadReq hits 1703system.cpu1.l2cache.Writeback_hits::writebacks 2978176 # number of Writeback hits 1704system.cpu1.l2cache.Writeback_hits::total 2978176 # number of Writeback hits 1705system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 79936 # number of UpgradeReq hits 1706system.cpu1.l2cache.UpgradeReq_hits::total 79936 # number of UpgradeReq hits 1707system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 35720 # number of SCUpgradeReq hits 1708system.cpu1.l2cache.SCUpgradeReq_hits::total 35720 # number of SCUpgradeReq hits 1709system.cpu1.l2cache.ReadExReq_hits::cpu1.data 908771 # number of ReadExReq hits 1710system.cpu1.l2cache.ReadExReq_hits::total 908771 # number of ReadExReq hits 1711system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 221576 # number of demand (read+write) hits 1712system.cpu1.l2cache.demand_hits::cpu1.itb.walker 129888 # number of demand (read+write) hits 1713system.cpu1.l2cache.demand_hits::cpu1.inst 4667071 # number of demand (read+write) hits 1714system.cpu1.l2cache.demand_hits::cpu1.data 3622989 # number of demand (read+write) hits 1715system.cpu1.l2cache.demand_hits::total 8641524 # number of demand (read+write) hits 1716system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 221576 # number of overall hits 1717system.cpu1.l2cache.overall_hits::cpu1.itb.walker 129888 # number of overall hits 1718system.cpu1.l2cache.overall_hits::cpu1.inst 4667071 # number of overall hits 1719system.cpu1.l2cache.overall_hits::cpu1.data 3622989 # number of overall hits 1720system.cpu1.l2cache.overall_hits::total 8641524 # number of overall hits 1721system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12665 # number of ReadReq misses 1722system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 11221 # number of ReadReq misses 1723system.cpu1.l2cache.ReadReq_misses::cpu1.inst 172232 # number of ReadReq misses 1724system.cpu1.l2cache.ReadReq_misses::cpu1.data 985367 # number of ReadReq misses 1725system.cpu1.l2cache.ReadReq_misses::total 1181485 # number of ReadReq misses 1726system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 109801 # number of UpgradeReq misses 1727system.cpu1.l2cache.UpgradeReq_misses::total 109801 # number of UpgradeReq misses 1728system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 157805 # number of SCUpgradeReq misses 1729system.cpu1.l2cache.SCUpgradeReq_misses::total 157805 # number of SCUpgradeReq misses 1730system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses 1731system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses 1732system.cpu1.l2cache.ReadExReq_misses::cpu1.data 226147 # number of ReadExReq misses 1733system.cpu1.l2cache.ReadExReq_misses::total 226147 # number of ReadExReq misses 1734system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12665 # number of demand (read+write) misses 1735system.cpu1.l2cache.demand_misses::cpu1.itb.walker 11221 # number of demand (read+write) misses 1736system.cpu1.l2cache.demand_misses::cpu1.inst 172232 # number of demand (read+write) misses 1737system.cpu1.l2cache.demand_misses::cpu1.data 1211514 # number of demand (read+write) misses 1738system.cpu1.l2cache.demand_misses::total 1407632 # number of demand (read+write) misses 1739system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12665 # number of overall misses 1740system.cpu1.l2cache.overall_misses::cpu1.itb.walker 11221 # number of overall misses 1741system.cpu1.l2cache.overall_misses::cpu1.inst 172232 # number of overall misses 1742system.cpu1.l2cache.overall_misses::cpu1.data 1211514 # number of overall misses 1743system.cpu1.l2cache.overall_misses::total 1407632 # number of overall misses 1744system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 578928201 # number of ReadReq miss cycles 1745system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 733432437 # number of ReadReq miss cycles 1746system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 4494366580 # number of ReadReq miss cycles 1747system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 32191641510 # number of ReadReq miss cycles 1748system.cpu1.l2cache.ReadReq_miss_latency::total 37998368728 # number of ReadReq miss cycles 1749system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2189702140 # number of UpgradeReq miss cycles 1750system.cpu1.l2cache.UpgradeReq_miss_latency::total 2189702140 # number of UpgradeReq miss cycles 1751system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3225705678 # number of SCUpgradeReq miss cycles 1752system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3225705678 # number of SCUpgradeReq miss cycles 1753system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1763999 # number of SCUpgradeFailReq miss cycles 1754system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1763999 # number of SCUpgradeFailReq miss cycles 1755system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10153420884 # number of ReadExReq miss cycles 1756system.cpu1.l2cache.ReadExReq_miss_latency::total 10153420884 # number of ReadExReq miss cycles 1757system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 578928201 # number of demand (read+write) miss cycles 1758system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 733432437 # number of demand (read+write) miss cycles 1759system.cpu1.l2cache.demand_miss_latency::cpu1.inst 4494366580 # number of demand (read+write) miss cycles 1760system.cpu1.l2cache.demand_miss_latency::cpu1.data 42345062394 # number of demand (read+write) miss cycles 1761system.cpu1.l2cache.demand_miss_latency::total 48151789612 # number of demand (read+write) miss cycles 1762system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 578928201 # number of overall miss cycles 1763system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 733432437 # number of overall miss cycles 1764system.cpu1.l2cache.overall_miss_latency::cpu1.inst 4494366580 # number of overall miss cycles 1765system.cpu1.l2cache.overall_miss_latency::cpu1.data 42345062394 # number of overall miss cycles 1766system.cpu1.l2cache.overall_miss_latency::total 48151789612 # number of overall miss cycles 1767system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 234241 # number of ReadReq accesses(hits+misses) 1768system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 141109 # number of ReadReq accesses(hits+misses) 1769system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 4839303 # number of ReadReq accesses(hits+misses) 1770system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3699585 # number of ReadReq accesses(hits+misses) 1771system.cpu1.l2cache.ReadReq_accesses::total 8914238 # number of ReadReq accesses(hits+misses) 1772system.cpu1.l2cache.Writeback_accesses::writebacks 2978176 # number of Writeback accesses(hits+misses) 1773system.cpu1.l2cache.Writeback_accesses::total 2978176 # number of Writeback accesses(hits+misses) 1774system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 189737 # number of UpgradeReq accesses(hits+misses) 1775system.cpu1.l2cache.UpgradeReq_accesses::total 189737 # number of UpgradeReq accesses(hits+misses) 1776system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 193525 # number of SCUpgradeReq accesses(hits+misses) 1777system.cpu1.l2cache.SCUpgradeReq_accesses::total 193525 # number of SCUpgradeReq accesses(hits+misses) 1778system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses) 1779system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) 1780system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1134918 # number of ReadExReq accesses(hits+misses) 1781system.cpu1.l2cache.ReadExReq_accesses::total 1134918 # number of ReadExReq accesses(hits+misses) 1782system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 234241 # number of demand (read+write) accesses 1783system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 141109 # number of demand (read+write) accesses 1784system.cpu1.l2cache.demand_accesses::cpu1.inst 4839303 # number of demand (read+write) accesses 1785system.cpu1.l2cache.demand_accesses::cpu1.data 4834503 # number of demand (read+write) accesses 1786system.cpu1.l2cache.demand_accesses::total 10049156 # number of demand (read+write) accesses 1787system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 234241 # number of overall (read+write) accesses 1788system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 141109 # number of overall (read+write) accesses 1789system.cpu1.l2cache.overall_accesses::cpu1.inst 4839303 # number of overall (read+write) accesses 1790system.cpu1.l2cache.overall_accesses::cpu1.data 4834503 # number of overall (read+write) accesses 1791system.cpu1.l2cache.overall_accesses::total 10049156 # number of overall (read+write) accesses 1792system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.054068 # miss rate for ReadReq accesses 1793system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.079520 # miss rate for ReadReq accesses 1794system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.035590 # miss rate for ReadReq accesses 1795system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.266345 # miss rate for ReadReq accesses 1796system.cpu1.l2cache.ReadReq_miss_rate::total 0.132539 # miss rate for ReadReq accesses 1797system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.578701 # miss rate for UpgradeReq accesses 1798system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.578701 # miss rate for UpgradeReq accesses 1799system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.815424 # miss rate for SCUpgradeReq accesses 1800system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.815424 # miss rate for SCUpgradeReq accesses 1801system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 1802system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1803system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.199263 # miss rate for ReadExReq accesses 1804system.cpu1.l2cache.ReadExReq_miss_rate::total 0.199263 # miss rate for ReadExReq accesses 1805system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.054068 # miss rate for demand accesses 1806system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.079520 # miss rate for demand accesses 1807system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.035590 # miss rate for demand accesses 1808system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.250597 # miss rate for demand accesses 1809system.cpu1.l2cache.demand_miss_rate::total 0.140075 # miss rate for demand accesses 1810system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.054068 # miss rate for overall accesses 1811system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.079520 # miss rate for overall accesses 1812system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.035590 # miss rate for overall accesses 1813system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.250597 # miss rate for overall accesses 1814system.cpu1.l2cache.overall_miss_rate::total 0.140075 # miss rate for overall accesses 1815system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 45710.872562 # average ReadReq miss latency 1816system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 65362.484360 # average ReadReq miss latency 1817system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 26094.840564 # average ReadReq miss latency 1818system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 32669.697189 # average ReadReq miss latency 1819system.cpu1.l2cache.ReadReq_avg_miss_latency::total 32161.532925 # average ReadReq miss latency 1820system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19942.460815 # average UpgradeReq miss latency 1821system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19942.460815 # average UpgradeReq miss latency 1822system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20441.086645 # average SCUpgradeReq miss latency 1823system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20441.086645 # average SCUpgradeReq miss latency 1824system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 293999.833333 # average SCUpgradeFailReq miss latency 1825system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 293999.833333 # average SCUpgradeFailReq miss latency 1826system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44897.437879 # average ReadExReq miss latency 1827system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44897.437879 # average ReadExReq miss latency 1828system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 45710.872562 # average overall miss latency 1829system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 65362.484360 # average overall miss latency 1830system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 26094.840564 # average overall miss latency 1831system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34952.185773 # average overall miss latency 1832system.cpu1.l2cache.demand_avg_miss_latency::total 34207.654850 # average overall miss latency 1833system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 45710.872562 # average overall miss latency 1834system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 65362.484360 # average overall miss latency 1835system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 26094.840564 # average overall miss latency 1836system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34952.185773 # average overall miss latency 1837system.cpu1.l2cache.overall_avg_miss_latency::total 34207.654850 # average overall miss latency 1838system.cpu1.l2cache.blocked_cycles::no_mshrs 6147 # number of cycles access was blocked 1839system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1840system.cpu1.l2cache.blocked::no_mshrs 166 # number of cycles access was blocked 1841system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1842system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 37.030120 # average number of cycles each access was blocked 1843system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1844system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1845system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 1846system.cpu1.l2cache.writebacks::writebacks 960563 # number of writebacks 1847system.cpu1.l2cache.writebacks::total 960563 # number of writebacks 1848system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 26607 # number of ReadReq MSHR hits 1849system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 912 # number of ReadReq MSHR hits 1850system.cpu1.l2cache.ReadReq_mshr_hits::total 27519 # number of ReadReq MSHR hits 1851system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 6089 # number of ReadExReq MSHR hits 1852system.cpu1.l2cache.ReadExReq_mshr_hits::total 6089 # number of ReadExReq MSHR hits 1853system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 26607 # number of demand (read+write) MSHR hits 1854system.cpu1.l2cache.demand_mshr_hits::cpu1.data 7001 # number of demand (read+write) MSHR hits 1855system.cpu1.l2cache.demand_mshr_hits::total 33608 # number of demand (read+write) MSHR hits 1856system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 26607 # number of overall MSHR hits 1857system.cpu1.l2cache.overall_mshr_hits::cpu1.data 7001 # number of overall MSHR hits 1858system.cpu1.l2cache.overall_mshr_hits::total 33608 # number of overall MSHR hits 1859system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 12665 # number of ReadReq MSHR misses 1860system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 11221 # number of ReadReq MSHR misses 1861system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 145625 # number of ReadReq MSHR misses 1862system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 984455 # number of ReadReq MSHR misses 1863system.cpu1.l2cache.ReadReq_mshr_misses::total 1153966 # number of ReadReq MSHR misses 1864system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 2394712 # number of HardPFReq MSHR misses 1865system.cpu1.l2cache.HardPFReq_mshr_misses::total 2394712 # number of HardPFReq MSHR misses 1866system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 109801 # number of UpgradeReq MSHR misses 1867system.cpu1.l2cache.UpgradeReq_mshr_misses::total 109801 # number of UpgradeReq MSHR misses 1868system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 157805 # number of SCUpgradeReq MSHR misses 1869system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 157805 # number of SCUpgradeReq MSHR misses 1870system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 6 # number of SCUpgradeFailReq MSHR misses 1871system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses 1872system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 220058 # number of ReadExReq MSHR misses 1873system.cpu1.l2cache.ReadExReq_mshr_misses::total 220058 # number of ReadExReq MSHR misses 1874system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 12665 # number of demand (read+write) MSHR misses 1875system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 11221 # number of demand (read+write) MSHR misses 1876system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 145625 # number of demand (read+write) MSHR misses 1877system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1204513 # number of demand (read+write) MSHR misses 1878system.cpu1.l2cache.demand_mshr_misses::total 1374024 # number of demand (read+write) MSHR misses 1879system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 12665 # number of overall MSHR misses 1880system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 11221 # number of overall MSHR misses 1881system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 145625 # number of overall MSHR misses 1882system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1204513 # number of overall MSHR misses 1883system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 2394712 # number of overall MSHR misses 1884system.cpu1.l2cache.overall_mshr_misses::total 3768736 # number of overall MSHR misses 1885system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 489322313 # number of ReadReq MSHR miss cycles 1886system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 653538067 # number of ReadReq MSHR miss cycles 1887system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 3045903499 # number of ReadReq MSHR miss cycles 1888system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 25194010676 # number of ReadReq MSHR miss cycles 1889system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 29382774555 # number of ReadReq MSHR miss cycles 1890system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 71059948043 # number of HardPFReq MSHR miss cycles 1891system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 71059948043 # number of HardPFReq MSHR miss cycles 1892system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 25441892262 # number of WriteInvalidateReq MSHR miss cycles 1893system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 25441892262 # number of WriteInvalidateReq MSHR miss cycles 1894system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 1899234087 # number of UpgradeReq MSHR miss cycles 1895system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 1899234087 # number of UpgradeReq MSHR miss cycles 1896system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2195015270 # number of SCUpgradeReq MSHR miss cycles 1897system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2195015270 # number of SCUpgradeReq MSHR miss cycles 1898system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1455999 # number of SCUpgradeFailReq MSHR miss cycles 1899system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1455999 # number of SCUpgradeFailReq MSHR miss cycles 1900system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7950904534 # number of ReadExReq MSHR miss cycles 1901system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7950904534 # number of ReadExReq MSHR miss cycles 1902system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 489322313 # number of demand (read+write) MSHR miss cycles 1903system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 653538067 # number of demand (read+write) MSHR miss cycles 1904system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 3045903499 # number of demand (read+write) MSHR miss cycles 1905system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 33144915210 # number of demand (read+write) MSHR miss cycles 1906system.cpu1.l2cache.demand_mshr_miss_latency::total 37333679089 # number of demand (read+write) MSHR miss cycles 1907system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 489322313 # number of overall MSHR miss cycles 1908system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 653538067 # number of overall MSHR miss cycles 1909system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 3045903499 # number of overall MSHR miss cycles 1910system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 33144915210 # number of overall MSHR miss cycles 1911system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 71059948043 # number of overall MSHR miss cycles 1912system.cpu1.l2cache.overall_mshr_miss_latency::total 108393627132 # number of overall MSHR miss cycles 1913system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7884500 # number of ReadReq MSHR uncacheable cycles 1914system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3918463269 # number of ReadReq MSHR uncacheable cycles 1915system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3926347769 # number of ReadReq MSHR uncacheable cycles 1916system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 3819021030 # number of WriteReq MSHR uncacheable cycles 1917system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3819021030 # number of WriteReq MSHR uncacheable cycles 1918system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7884500 # number of overall MSHR uncacheable cycles 1919system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 7737484299 # number of overall MSHR uncacheable cycles 1920system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 7745368799 # number of overall MSHR uncacheable cycles 1921system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.054068 # mshr miss rate for ReadReq accesses 1922system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.079520 # mshr miss rate for ReadReq accesses 1923system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.030092 # mshr miss rate for ReadReq accesses 1924system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.266099 # mshr miss rate for ReadReq accesses 1925system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.129452 # mshr miss rate for ReadReq accesses 1926system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1927system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1928system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.578701 # mshr miss rate for UpgradeReq accesses 1929system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.578701 # mshr miss rate for UpgradeReq accesses 1930system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.815424 # mshr miss rate for SCUpgradeReq accesses 1931system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.815424 # mshr miss rate for SCUpgradeReq accesses 1932system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1933system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1934system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.193898 # mshr miss rate for ReadExReq accesses 1935system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.193898 # mshr miss rate for ReadExReq accesses 1936system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.054068 # mshr miss rate for demand accesses 1937system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.079520 # mshr miss rate for demand accesses 1938system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.030092 # mshr miss rate for demand accesses 1939system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.249149 # mshr miss rate for demand accesses 1940system.cpu1.l2cache.demand_mshr_miss_rate::total 0.136730 # mshr miss rate for demand accesses 1941system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.054068 # mshr miss rate for overall accesses 1942system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.079520 # mshr miss rate for overall accesses 1943system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.030092 # mshr miss rate for overall accesses 1944system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.249149 # mshr miss rate for overall accesses 1945system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 1946system.cpu1.l2cache.overall_mshr_miss_rate::total 0.375030 # mshr miss rate for overall accesses 1947system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 38635.792578 # average ReadReq mshr miss latency 1948system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 58242.408609 # average ReadReq mshr miss latency 1949system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 20916.075530 # average ReadReq mshr miss latency 1950system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 25591.835763 # average ReadReq mshr miss latency 1951system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25462.426584 # average ReadReq mshr miss latency 1952system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 29673.692721 # average HardPFReq mshr miss latency 1953system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 29673.692721 # average HardPFReq mshr miss latency 1954system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency 1955system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 1956system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17297.056375 # average UpgradeReq mshr miss latency 1957system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17297.056375 # average UpgradeReq mshr miss latency 1958system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13909.668705 # average SCUpgradeReq mshr miss latency 1959system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13909.668705 # average SCUpgradeReq mshr miss latency 1960system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 242666.500000 # average SCUpgradeFailReq mshr miss latency 1961system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 242666.500000 # average SCUpgradeFailReq mshr miss latency 1962system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36130.949722 # average ReadExReq mshr miss latency 1963system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36130.949722 # average ReadExReq mshr miss latency 1964system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 38635.792578 # average overall mshr miss latency 1965system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 58242.408609 # average overall mshr miss latency 1966system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 20916.075530 # average overall mshr miss latency 1967system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27517.274791 # average overall mshr miss latency 1968system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27171.053118 # average overall mshr miss latency 1969system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 38635.792578 # average overall mshr miss latency 1970system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 58242.408609 # average overall mshr miss latency 1971system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 20916.075530 # average overall mshr miss latency 1972system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27517.274791 # average overall mshr miss latency 1973system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 29673.692721 # average overall mshr miss latency 1974system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28761.268269 # average overall mshr miss latency 1975system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1976system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1977system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1978system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1979system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1980system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1981system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1982system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1983system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1984system.cpu1.toL2Bus.trans_dist::ReadReq 12427806 # Transaction distribution 1985system.cpu1.toL2Bus.trans_dist::ReadResp 9137324 # Transaction distribution 1986system.cpu1.toL2Bus.trans_dist::WriteReq 23353 # Transaction distribution 1987system.cpu1.toL2Bus.trans_dist::WriteResp 23353 # Transaction distribution 1988system.cpu1.toL2Bus.trans_dist::Writeback 2978176 # Transaction distribution 1989system.cpu1.toL2Bus.trans_dist::HardPFReq 3478890 # Transaction distribution 1990system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1679869 # Transaction distribution 1991system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 685307 # Transaction distribution 1992system.cpu1.toL2Bus.trans_dist::UpgradeReq 370922 # Transaction distribution 1993system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 353849 # Transaction distribution 1994system.cpu1.toL2Bus.trans_dist::UpgradeResp 446809 # Transaction distribution 1995system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 42 # Transaction distribution 1996system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 80 # Transaction distribution 1997system.cpu1.toL2Bus.trans_dist::ReadExReq 1290596 # Transaction distribution 1998system.cpu1.toL2Bus.trans_dist::ReadExResp 1141918 # Transaction distribution 1999system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9678826 # Packet count per connected master and slave (bytes) 2000system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15042396 # Packet count per connected master and slave (bytes) 2001system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 312565 # Packet count per connected master and slave (bytes) 2002system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 544877 # Packet count per connected master and slave (bytes) 2003system.cpu1.toL2Bus.pkt_count::total 25578664 # Packet count per connected master and slave (bytes) 2004system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 309715832 # Cumulative packet size per connected master and slave (bytes) 2005system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 550341480 # Cumulative packet size per connected master and slave (bytes) 2006system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1128872 # Cumulative packet size per connected master and slave (bytes) 2007system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1873928 # Cumulative packet size per connected master and slave (bytes) 2008system.cpu1.toL2Bus.pkt_size::total 863060112 # Cumulative packet size per connected master and slave (bytes) 2009system.cpu1.toL2Bus.snoops 8621982 # Total snoops (count) 2010system.cpu1.toL2Bus.snoop_fanout::samples 22555543 # Request fanout histogram 2011system.cpu1.toL2Bus.snoop_fanout::mean 5.370325 # Request fanout histogram 2012system.cpu1.toL2Bus.snoop_fanout::stdev 0.482892 # Request fanout histogram 2013system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2014system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2015system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 2016system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 2017system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 2018system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 2019system.cpu1.toL2Bus.snoop_fanout::5 14202655 62.97% 62.97% # Request fanout histogram 2020system.cpu1.toL2Bus.snoop_fanout::6 8352888 37.03% 100.00% # Request fanout histogram 2021system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2022system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 2023system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 2024system.cpu1.toL2Bus.snoop_fanout::total 22555543 # Request fanout histogram 2025system.cpu1.toL2Bus.reqLayer0.occupancy 10801104660 # Layer occupancy (ticks) 2026system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2027system.cpu1.toL2Bus.snoopLayer0.occupancy 179932994 # Layer occupancy (ticks) 2028system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2029system.cpu1.toL2Bus.respLayer0.occupancy 7260511142 # Layer occupancy (ticks) 2030system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2031system.cpu1.toL2Bus.respLayer1.occupancy 7881710673 # Layer occupancy (ticks) 2032system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2033system.cpu1.toL2Bus.respLayer2.occupancy 172097315 # Layer occupancy (ticks) 2034system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2035system.cpu1.toL2Bus.respLayer3.occupancy 311084554 # Layer occupancy (ticks) 2036system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2037system.iobus.trans_dist::ReadReq 40536 # Transaction distribution 2038system.iobus.trans_dist::ReadResp 40536 # Transaction distribution 2039system.iobus.trans_dist::WriteReq 137093 # Transaction distribution 2040system.iobus.trans_dist::WriteResp 137147 # Transaction distribution 2041system.iobus.trans_dist::WriteInvalidateReq 54 # Transaction distribution 2042system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48328 # Packet count per connected master and slave (bytes) 2043system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2044system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2045system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2046system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2047system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2048system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2049system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2050system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2051system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2052system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) 2053system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2054system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 2055system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2056system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 2057system.iobus.pkt_count_system.bridge.master::total 123470 # Packet count per connected master and slave (bytes) 2058system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231816 # Packet count per connected master and slave (bytes) 2059system.iobus.pkt_count_system.realview.ide.dma::total 231816 # Packet count per connected master and slave (bytes) 2060system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2061system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 2062system.iobus.pkt_count::total 355366 # Packet count per connected master and slave (bytes) 2063system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48348 # Cumulative packet size per connected master and slave (bytes) 2064system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2065system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2066system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2067system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2068system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2069system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2070system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2071system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2072system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2073system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) 2074system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 2075system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 2076system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 2077system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 2078system.iobus.pkt_size_system.bridge.master::total 156485 # Cumulative packet size per connected master and slave (bytes) 2079system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355616 # Cumulative packet size per connected master and slave (bytes) 2080system.iobus.pkt_size_system.realview.ide.dma::total 7355616 # Cumulative packet size per connected master and slave (bytes) 2081system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2082system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 2083system.iobus.pkt_size::total 7514187 # Cumulative packet size per connected master and slave (bytes) 2084system.iobus.reqLayer0.occupancy 36745000 # Layer occupancy (ticks) 2085system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2086system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 2087system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2088system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 2089system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2090system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 2091system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2092system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 2093system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2094system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 2095system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2096system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 2097system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2098system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 2099system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2100system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 2101system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2102system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 2103system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2104system.iobus.reqLayer23.occupancy 22142000 # Layer occupancy (ticks) 2105system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2106system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 2107system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2108system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 2109system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2110system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 2111system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 2112system.iobus.reqLayer27.occupancy 984235192 # Layer occupancy (ticks) 2113system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2114system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2115system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 2116system.iobus.respLayer0.occupancy 93310000 # Layer occupancy (ticks) 2117system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2118system.iobus.respLayer3.occupancy 179557795 # Layer occupancy (ticks) 2119system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2120system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) 2121system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 2122system.iocache.tags.replacements 115889 # number of replacements 2123system.iocache.tags.tagsinuse 11.315870 # Cycle average of tags in use 2124system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 2125system.iocache.tags.sampled_refs 115905 # Sample count of references to valid blocks. 2126system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 2127system.iocache.tags.warmup_cycle 9130394779000 # Cycle when the warmup percentage was hit. 2128system.iocache.tags.occ_blocks::realview.ethernet 3.824342 # Average occupied blocks per requestor 2129system.iocache.tags.occ_blocks::realview.ide 7.491528 # Average occupied blocks per requestor 2130system.iocache.tags.occ_percent::realview.ethernet 0.239021 # Average percentage of cache occupancy 2131system.iocache.tags.occ_percent::realview.ide 0.468221 # Average percentage of cache occupancy 2132system.iocache.tags.occ_percent::total 0.707242 # Average percentage of cache occupancy 2133system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2134system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2135system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2136system.iocache.tags.tag_accesses 1043961 # Number of tag accesses 2137system.iocache.tags.data_accesses 1043961 # Number of data accesses 2138system.iocache.WriteInvalidateReq_hits::realview.ide 106984 # number of WriteInvalidateReq hits 2139system.iocache.WriteInvalidateReq_hits::total 106984 # number of WriteInvalidateReq hits 2140system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2141system.iocache.ReadReq_misses::realview.ide 8924 # number of ReadReq misses 2142system.iocache.ReadReq_misses::total 8961 # number of ReadReq misses 2143system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2144system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2145system.iocache.WriteInvalidateReq_misses::realview.ide 54 # number of WriteInvalidateReq misses 2146system.iocache.WriteInvalidateReq_misses::total 54 # number of WriteInvalidateReq misses 2147system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 2148system.iocache.demand_misses::realview.ide 8924 # number of demand (read+write) misses 2149system.iocache.demand_misses::total 8964 # number of demand (read+write) misses 2150system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 2151system.iocache.overall_misses::realview.ide 8924 # number of overall misses 2152system.iocache.overall_misses::total 8964 # number of overall misses 2153system.iocache.ReadReq_miss_latency::realview.ethernet 5707000 # number of ReadReq miss cycles 2154system.iocache.ReadReq_miss_latency::realview.ide 1957100855 # number of ReadReq miss cycles 2155system.iocache.ReadReq_miss_latency::total 1962807855 # number of ReadReq miss cycles 2156system.iocache.WriteReq_miss_latency::realview.ethernet 357000 # number of WriteReq miss cycles 2157system.iocache.WriteReq_miss_latency::total 357000 # number of WriteReq miss cycles 2158system.iocache.demand_miss_latency::realview.ethernet 6064000 # number of demand (read+write) miss cycles 2159system.iocache.demand_miss_latency::realview.ide 1957100855 # number of demand (read+write) miss cycles 2160system.iocache.demand_miss_latency::total 1963164855 # number of demand (read+write) miss cycles 2161system.iocache.overall_miss_latency::realview.ethernet 6064000 # number of overall miss cycles 2162system.iocache.overall_miss_latency::realview.ide 1957100855 # number of overall miss cycles 2163system.iocache.overall_miss_latency::total 1963164855 # number of overall miss cycles 2164system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 2165system.iocache.ReadReq_accesses::realview.ide 8924 # number of ReadReq accesses(hits+misses) 2166system.iocache.ReadReq_accesses::total 8961 # number of ReadReq accesses(hits+misses) 2167system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2168system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2169system.iocache.WriteInvalidateReq_accesses::realview.ide 107038 # number of WriteInvalidateReq accesses(hits+misses) 2170system.iocache.WriteInvalidateReq_accesses::total 107038 # number of WriteInvalidateReq accesses(hits+misses) 2171system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 2172system.iocache.demand_accesses::realview.ide 8924 # number of demand (read+write) accesses 2173system.iocache.demand_accesses::total 8964 # number of demand (read+write) accesses 2174system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 2175system.iocache.overall_accesses::realview.ide 8924 # number of overall (read+write) accesses 2176system.iocache.overall_accesses::total 8964 # number of overall (read+write) accesses 2177system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2178system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2179system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2180system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2181system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2182system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000504 # miss rate for WriteInvalidateReq accesses 2183system.iocache.WriteInvalidateReq_miss_rate::total 0.000504 # miss rate for WriteInvalidateReq accesses 2184system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2185system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2186system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2187system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2188system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2189system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2190system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243 # average ReadReq miss latency 2191system.iocache.ReadReq_avg_miss_latency::realview.ide 219307.581242 # average ReadReq miss latency 2192system.iocache.ReadReq_avg_miss_latency::total 219038.930365 # average ReadReq miss latency 2193system.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency 2194system.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency 2195system.iocache.demand_avg_miss_latency::realview.ethernet 151600 # average overall miss latency 2196system.iocache.demand_avg_miss_latency::realview.ide 219307.581242 # average overall miss latency 2197system.iocache.demand_avg_miss_latency::total 219005.450134 # average overall miss latency 2198system.iocache.overall_avg_miss_latency::realview.ethernet 151600 # average overall miss latency 2199system.iocache.overall_avg_miss_latency::realview.ide 219307.581242 # average overall miss latency 2200system.iocache.overall_avg_miss_latency::total 219005.450134 # average overall miss latency 2201system.iocache.blocked_cycles::no_mshrs 53861 # number of cycles access was blocked 2202system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2203system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked 2204system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2205system.iocache.avg_blocked_cycles::no_mshrs 9.810747 # average number of cycles each access was blocked 2206system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2207system.iocache.fast_writes 106984 # number of fast writes performed 2208system.iocache.cache_copies 0 # number of cache copies performed 2209system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 2210system.iocache.ReadReq_mshr_misses::realview.ide 8924 # number of ReadReq MSHR misses 2211system.iocache.ReadReq_mshr_misses::total 8961 # number of ReadReq MSHR misses 2212system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2213system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2214system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 2215system.iocache.demand_mshr_misses::realview.ide 8924 # number of demand (read+write) MSHR misses 2216system.iocache.demand_mshr_misses::total 8964 # number of demand (read+write) MSHR misses 2217system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 2218system.iocache.overall_mshr_misses::realview.ide 8924 # number of overall MSHR misses 2219system.iocache.overall_mshr_misses::total 8964 # number of overall MSHR misses 2220system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3783000 # number of ReadReq MSHR miss cycles 2221system.iocache.ReadReq_mshr_miss_latency::realview.ide 1492924359 # number of ReadReq MSHR miss cycles 2222system.iocache.ReadReq_mshr_miss_latency::total 1496707359 # number of ReadReq MSHR miss cycles 2223system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 2224system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 2225system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6628374628 # number of WriteInvalidateReq MSHR miss cycles 2226system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6628374628 # number of WriteInvalidateReq MSHR miss cycles 2227system.iocache.demand_mshr_miss_latency::realview.ethernet 3984000 # number of demand (read+write) MSHR miss cycles 2228system.iocache.demand_mshr_miss_latency::realview.ide 1492924359 # number of demand (read+write) MSHR miss cycles 2229system.iocache.demand_mshr_miss_latency::total 1496908359 # number of demand (read+write) MSHR miss cycles 2230system.iocache.overall_mshr_miss_latency::realview.ethernet 3984000 # number of overall MSHR miss cycles 2231system.iocache.overall_mshr_miss_latency::realview.ide 1492924359 # number of overall MSHR miss cycles 2232system.iocache.overall_mshr_miss_latency::total 1496908359 # number of overall MSHR miss cycles 2233system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2234system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2235system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2236system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2237system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2238system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 2239system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2240system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2241system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 2242system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2243system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2244system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243 # average ReadReq mshr miss latency 2245system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 167293.182317 # average ReadReq mshr miss latency 2246system.iocache.ReadReq_avg_mshr_miss_latency::total 167024.590894 # average ReadReq mshr miss latency 2247system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 2248system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 2249system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency 2250system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 2251system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency 2252system.iocache.demand_avg_mshr_miss_latency::realview.ide 167293.182317 # average overall mshr miss latency 2253system.iocache.demand_avg_mshr_miss_latency::total 166991.115462 # average overall mshr miss latency 2254system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency 2255system.iocache.overall_avg_mshr_miss_latency::realview.ide 167293.182317 # average overall mshr miss latency 2256system.iocache.overall_avg_mshr_miss_latency::total 166991.115462 # average overall mshr miss latency 2257system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2258system.l2c.tags.replacements 1086855 # number of replacements 2259system.l2c.tags.tagsinuse 64099.647179 # Cycle average of tags in use 2260system.l2c.tags.total_refs 6672114 # Total number of references to valid blocks. 2261system.l2c.tags.sampled_refs 1148598 # Sample count of references to valid blocks. 2262system.l2c.tags.avg_refs 5.808920 # Average number of references to valid blocks. 2263system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2264system.l2c.tags.occ_blocks::writebacks 9469.927163 # Average occupied blocks per requestor 2265system.l2c.tags.occ_blocks::cpu0.dtb.walker 51.211523 # Average occupied blocks per requestor 2266system.l2c.tags.occ_blocks::cpu0.itb.walker 68.031290 # Average occupied blocks per requestor 2267system.l2c.tags.occ_blocks::cpu0.inst 696.373428 # Average occupied blocks per requestor 2268system.l2c.tags.occ_blocks::cpu0.data 3179.738420 # Average occupied blocks per requestor 2269system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 17944.005062 # Average occupied blocks per requestor 2270system.l2c.tags.occ_blocks::cpu1.dtb.walker 291.904824 # Average occupied blocks per requestor 2271system.l2c.tags.occ_blocks::cpu1.itb.walker 401.470147 # Average occupied blocks per requestor 2272system.l2c.tags.occ_blocks::cpu1.inst 563.131009 # Average occupied blocks per requestor 2273system.l2c.tags.occ_blocks::cpu1.data 10017.603756 # Average occupied blocks per requestor 2274system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 21416.250557 # Average occupied blocks per requestor 2275system.l2c.tags.occ_percent::writebacks 0.144500 # Average percentage of cache occupancy 2276system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000781 # Average percentage of cache occupancy 2277system.l2c.tags.occ_percent::cpu0.itb.walker 0.001038 # Average percentage of cache occupancy 2278system.l2c.tags.occ_percent::cpu0.inst 0.010626 # Average percentage of cache occupancy 2279system.l2c.tags.occ_percent::cpu0.data 0.048519 # Average percentage of cache occupancy 2280system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.273804 # Average percentage of cache occupancy 2281system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004454 # Average percentage of cache occupancy 2282system.l2c.tags.occ_percent::cpu1.itb.walker 0.006126 # Average percentage of cache occupancy 2283system.l2c.tags.occ_percent::cpu1.inst 0.008593 # Average percentage of cache occupancy 2284system.l2c.tags.occ_percent::cpu1.data 0.152857 # Average percentage of cache occupancy 2285system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.326786 # Average percentage of cache occupancy 2286system.l2c.tags.occ_percent::total 0.978083 # Average percentage of cache occupancy 2287system.l2c.tags.occ_task_id_blocks::1022 31587 # Occupied blocks per task id 2288system.l2c.tags.occ_task_id_blocks::1023 309 # Occupied blocks per task id 2289system.l2c.tags.occ_task_id_blocks::1024 29847 # Occupied blocks per task id 2290system.l2c.tags.age_task_id_blocks_1022::0 9 # Occupied blocks per task id 2291system.l2c.tags.age_task_id_blocks_1022::1 114 # Occupied blocks per task id 2292system.l2c.tags.age_task_id_blocks_1022::2 1585 # Occupied blocks per task id 2293system.l2c.tags.age_task_id_blocks_1022::3 4136 # Occupied blocks per task id 2294system.l2c.tags.age_task_id_blocks_1022::4 25743 # Occupied blocks per task id 2295system.l2c.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id 2296system.l2c.tags.age_task_id_blocks_1023::1 9 # Occupied blocks per task id 2297system.l2c.tags.age_task_id_blocks_1023::2 33 # Occupied blocks per task id 2298system.l2c.tags.age_task_id_blocks_1023::3 47 # Occupied blocks per task id 2299system.l2c.tags.age_task_id_blocks_1023::4 219 # Occupied blocks per task id 2300system.l2c.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id 2301system.l2c.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id 2302system.l2c.tags.age_task_id_blocks_1024::2 1360 # Occupied blocks per task id 2303system.l2c.tags.age_task_id_blocks_1024::3 9152 # Occupied blocks per task id 2304system.l2c.tags.age_task_id_blocks_1024::4 19154 # Occupied blocks per task id 2305system.l2c.tags.occ_task_id_percent::1022 0.481979 # Percentage of cache occupancy per task id 2306system.l2c.tags.occ_task_id_percent::1023 0.004715 # Percentage of cache occupancy per task id 2307system.l2c.tags.occ_task_id_percent::1024 0.455429 # Percentage of cache occupancy per task id 2308system.l2c.tags.tag_accesses 80637866 # Number of tag accesses 2309system.l2c.tags.data_accesses 80637866 # Number of data accesses 2310system.l2c.ReadReq_hits::cpu0.dtb.walker 6250 # number of ReadReq hits 2311system.l2c.ReadReq_hits::cpu0.itb.walker 4321 # number of ReadReq hits 2312system.l2c.ReadReq_hits::cpu0.inst 142068 # number of ReadReq hits 2313system.l2c.ReadReq_hits::cpu0.data 620262 # number of ReadReq hits 2314system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 1618371 # number of ReadReq hits 2315system.l2c.ReadReq_hits::cpu1.dtb.walker 6096 # number of ReadReq hits 2316system.l2c.ReadReq_hits::cpu1.itb.walker 4059 # number of ReadReq hits 2317system.l2c.ReadReq_hits::cpu1.inst 137369 # number of ReadReq hits 2318system.l2c.ReadReq_hits::cpu1.data 611754 # number of ReadReq hits 2319system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 1545913 # number of ReadReq hits 2320system.l2c.ReadReq_hits::total 4696463 # number of ReadReq hits 2321system.l2c.Writeback_hits::writebacks 1994497 # number of Writeback hits 2322system.l2c.Writeback_hits::total 1994497 # number of Writeback hits 2323system.l2c.UpgradeReq_hits::cpu0.data 23769 # number of UpgradeReq hits 2324system.l2c.UpgradeReq_hits::cpu1.data 27954 # number of UpgradeReq hits 2325system.l2c.UpgradeReq_hits::total 51723 # number of UpgradeReq hits 2326system.l2c.SCUpgradeReq_hits::cpu0.data 7971 # number of SCUpgradeReq hits 2327system.l2c.SCUpgradeReq_hits::cpu1.data 7653 # number of SCUpgradeReq hits 2328system.l2c.SCUpgradeReq_hits::total 15624 # number of SCUpgradeReq hits 2329system.l2c.ReadExReq_hits::cpu0.data 52432 # number of ReadExReq hits 2330system.l2c.ReadExReq_hits::cpu1.data 49853 # number of ReadExReq hits 2331system.l2c.ReadExReq_hits::total 102285 # number of ReadExReq hits 2332system.l2c.demand_hits::cpu0.dtb.walker 6250 # number of demand (read+write) hits 2333system.l2c.demand_hits::cpu0.itb.walker 4321 # number of demand (read+write) hits 2334system.l2c.demand_hits::cpu0.inst 142068 # number of demand (read+write) hits 2335system.l2c.demand_hits::cpu0.data 672694 # number of demand (read+write) hits 2336system.l2c.demand_hits::cpu0.l2cache.prefetcher 1618371 # number of demand (read+write) hits 2337system.l2c.demand_hits::cpu1.dtb.walker 6096 # number of demand (read+write) hits 2338system.l2c.demand_hits::cpu1.itb.walker 4059 # number of demand (read+write) hits 2339system.l2c.demand_hits::cpu1.inst 137369 # number of demand (read+write) hits 2340system.l2c.demand_hits::cpu1.data 661607 # number of demand (read+write) hits 2341system.l2c.demand_hits::cpu1.l2cache.prefetcher 1545913 # number of demand (read+write) hits 2342system.l2c.demand_hits::total 4798748 # number of demand (read+write) hits 2343system.l2c.overall_hits::cpu0.dtb.walker 6250 # number of overall hits 2344system.l2c.overall_hits::cpu0.itb.walker 4321 # number of overall hits 2345system.l2c.overall_hits::cpu0.inst 142068 # number of overall hits 2346system.l2c.overall_hits::cpu0.data 672694 # number of overall hits 2347system.l2c.overall_hits::cpu0.l2cache.prefetcher 1618371 # number of overall hits 2348system.l2c.overall_hits::cpu1.dtb.walker 6096 # number of overall hits 2349system.l2c.overall_hits::cpu1.itb.walker 4059 # number of overall hits 2350system.l2c.overall_hits::cpu1.inst 137369 # number of overall hits 2351system.l2c.overall_hits::cpu1.data 661607 # number of overall hits 2352system.l2c.overall_hits::cpu1.l2cache.prefetcher 1545913 # number of overall hits 2353system.l2c.overall_hits::total 4798748 # number of overall hits 2354system.l2c.ReadReq_misses::cpu0.dtb.walker 3647 # number of ReadReq misses 2355system.l2c.ReadReq_misses::cpu0.itb.walker 6386 # number of ReadReq misses 2356system.l2c.ReadReq_misses::cpu0.inst 8946 # number of ReadReq misses 2357system.l2c.ReadReq_misses::cpu0.data 136148 # number of ReadReq misses 2358system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 441016 # number of ReadReq misses 2359system.l2c.ReadReq_misses::cpu1.dtb.walker 4242 # number of ReadReq misses 2360system.l2c.ReadReq_misses::cpu1.itb.walker 6837 # number of ReadReq misses 2361system.l2c.ReadReq_misses::cpu1.inst 8364 # number of ReadReq misses 2362system.l2c.ReadReq_misses::cpu1.data 140626 # number of ReadReq misses 2363system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 418325 # number of ReadReq misses 2364system.l2c.ReadReq_misses::total 1174537 # number of ReadReq misses 2365system.l2c.UpgradeReq_misses::cpu0.data 34627 # number of UpgradeReq misses 2366system.l2c.UpgradeReq_misses::cpu1.data 36381 # number of UpgradeReq misses 2367system.l2c.UpgradeReq_misses::total 71008 # number of UpgradeReq misses 2368system.l2c.SCUpgradeReq_misses::cpu0.data 10699 # number of SCUpgradeReq misses 2369system.l2c.SCUpgradeReq_misses::cpu1.data 11055 # number of SCUpgradeReq misses 2370system.l2c.SCUpgradeReq_misses::total 21754 # number of SCUpgradeReq misses 2371system.l2c.ReadExReq_misses::cpu0.data 78297 # number of ReadExReq misses 2372system.l2c.ReadExReq_misses::cpu1.data 72282 # number of ReadExReq misses 2373system.l2c.ReadExReq_misses::total 150579 # number of ReadExReq misses 2374system.l2c.demand_misses::cpu0.dtb.walker 3647 # number of demand (read+write) misses 2375system.l2c.demand_misses::cpu0.itb.walker 6386 # number of demand (read+write) misses 2376system.l2c.demand_misses::cpu0.inst 8946 # number of demand (read+write) misses 2377system.l2c.demand_misses::cpu0.data 214445 # number of demand (read+write) misses 2378system.l2c.demand_misses::cpu0.l2cache.prefetcher 441016 # number of demand (read+write) misses 2379system.l2c.demand_misses::cpu1.dtb.walker 4242 # number of demand (read+write) misses 2380system.l2c.demand_misses::cpu1.itb.walker 6837 # number of demand (read+write) misses 2381system.l2c.demand_misses::cpu1.inst 8364 # number of demand (read+write) misses 2382system.l2c.demand_misses::cpu1.data 212908 # number of demand (read+write) misses 2383system.l2c.demand_misses::cpu1.l2cache.prefetcher 418325 # number of demand (read+write) misses 2384system.l2c.demand_misses::total 1325116 # number of demand (read+write) misses 2385system.l2c.overall_misses::cpu0.dtb.walker 3647 # number of overall misses 2386system.l2c.overall_misses::cpu0.itb.walker 6386 # number of overall misses 2387system.l2c.overall_misses::cpu0.inst 8946 # number of overall misses 2388system.l2c.overall_misses::cpu0.data 214445 # number of overall misses 2389system.l2c.overall_misses::cpu0.l2cache.prefetcher 441016 # number of overall misses 2390system.l2c.overall_misses::cpu1.dtb.walker 4242 # number of overall misses 2391system.l2c.overall_misses::cpu1.itb.walker 6837 # number of overall misses 2392system.l2c.overall_misses::cpu1.inst 8364 # number of overall misses 2393system.l2c.overall_misses::cpu1.data 212908 # number of overall misses 2394system.l2c.overall_misses::cpu1.l2cache.prefetcher 418325 # number of overall misses 2395system.l2c.overall_misses::total 1325116 # number of overall misses 2396system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 290095498 # number of ReadReq miss cycles 2397system.l2c.ReadReq_miss_latency::cpu0.itb.walker 510585994 # number of ReadReq miss cycles 2398system.l2c.ReadReq_miss_latency::cpu0.inst 795450996 # number of ReadReq miss cycles 2399system.l2c.ReadReq_miss_latency::cpu0.data 11077065870 # number of ReadReq miss cycles 2400system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 46140706698 # number of ReadReq miss cycles 2401system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 335992750 # number of ReadReq miss cycles 2402system.l2c.ReadReq_miss_latency::cpu1.itb.walker 542306996 # number of ReadReq miss cycles 2403system.l2c.ReadReq_miss_latency::cpu1.inst 742040494 # number of ReadReq miss cycles 2404system.l2c.ReadReq_miss_latency::cpu1.data 11432821383 # number of ReadReq miss cycles 2405system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 44423863626 # number of ReadReq miss cycles 2406system.l2c.ReadReq_miss_latency::total 116290930305 # number of ReadReq miss cycles 2407system.l2c.UpgradeReq_miss_latency::cpu0.data 147041544 # number of UpgradeReq miss cycles 2408system.l2c.UpgradeReq_miss_latency::cpu1.data 142085765 # number of UpgradeReq miss cycles 2409system.l2c.UpgradeReq_miss_latency::total 289127309 # number of UpgradeReq miss cycles 2410system.l2c.SCUpgradeReq_miss_latency::cpu0.data 51916806 # number of SCUpgradeReq miss cycles 2411system.l2c.SCUpgradeReq_miss_latency::cpu1.data 56203152 # number of SCUpgradeReq miss cycles 2412system.l2c.SCUpgradeReq_miss_latency::total 108119958 # number of SCUpgradeReq miss cycles 2413system.l2c.ReadExReq_miss_latency::cpu0.data 5726616061 # number of ReadExReq miss cycles 2414system.l2c.ReadExReq_miss_latency::cpu1.data 5297244481 # number of ReadExReq miss cycles 2415system.l2c.ReadExReq_miss_latency::total 11023860542 # number of ReadExReq miss cycles 2416system.l2c.demand_miss_latency::cpu0.dtb.walker 290095498 # number of demand (read+write) miss cycles 2417system.l2c.demand_miss_latency::cpu0.itb.walker 510585994 # number of demand (read+write) miss cycles 2418system.l2c.demand_miss_latency::cpu0.inst 795450996 # number of demand (read+write) miss cycles 2419system.l2c.demand_miss_latency::cpu0.data 16803681931 # number of demand (read+write) miss cycles 2420system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 46140706698 # number of demand (read+write) miss cycles 2421system.l2c.demand_miss_latency::cpu1.dtb.walker 335992750 # number of demand (read+write) miss cycles 2422system.l2c.demand_miss_latency::cpu1.itb.walker 542306996 # number of demand (read+write) miss cycles 2423system.l2c.demand_miss_latency::cpu1.inst 742040494 # number of demand (read+write) miss cycles 2424system.l2c.demand_miss_latency::cpu1.data 16730065864 # number of demand (read+write) miss cycles 2425system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 44423863626 # number of demand (read+write) miss cycles 2426system.l2c.demand_miss_latency::total 127314790847 # number of demand (read+write) miss cycles 2427system.l2c.overall_miss_latency::cpu0.dtb.walker 290095498 # number of overall miss cycles 2428system.l2c.overall_miss_latency::cpu0.itb.walker 510585994 # number of overall miss cycles 2429system.l2c.overall_miss_latency::cpu0.inst 795450996 # number of overall miss cycles 2430system.l2c.overall_miss_latency::cpu0.data 16803681931 # number of overall miss cycles 2431system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 46140706698 # number of overall miss cycles 2432system.l2c.overall_miss_latency::cpu1.dtb.walker 335992750 # number of overall miss cycles 2433system.l2c.overall_miss_latency::cpu1.itb.walker 542306996 # number of overall miss cycles 2434system.l2c.overall_miss_latency::cpu1.inst 742040494 # number of overall miss cycles 2435system.l2c.overall_miss_latency::cpu1.data 16730065864 # number of overall miss cycles 2436system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 44423863626 # number of overall miss cycles 2437system.l2c.overall_miss_latency::total 127314790847 # number of overall miss cycles 2438system.l2c.ReadReq_accesses::cpu0.dtb.walker 9897 # number of ReadReq accesses(hits+misses) 2439system.l2c.ReadReq_accesses::cpu0.itb.walker 10707 # number of ReadReq accesses(hits+misses) 2440system.l2c.ReadReq_accesses::cpu0.inst 151014 # number of ReadReq accesses(hits+misses) 2441system.l2c.ReadReq_accesses::cpu0.data 756410 # number of ReadReq accesses(hits+misses) 2442system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 2059387 # number of ReadReq accesses(hits+misses) 2443system.l2c.ReadReq_accesses::cpu1.dtb.walker 10338 # number of ReadReq accesses(hits+misses) 2444system.l2c.ReadReq_accesses::cpu1.itb.walker 10896 # number of ReadReq accesses(hits+misses) 2445system.l2c.ReadReq_accesses::cpu1.inst 145733 # number of ReadReq accesses(hits+misses) 2446system.l2c.ReadReq_accesses::cpu1.data 752380 # number of ReadReq accesses(hits+misses) 2447system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 1964238 # number of ReadReq accesses(hits+misses) 2448system.l2c.ReadReq_accesses::total 5871000 # number of ReadReq accesses(hits+misses) 2449system.l2c.Writeback_accesses::writebacks 1994497 # number of Writeback accesses(hits+misses) 2450system.l2c.Writeback_accesses::total 1994497 # number of Writeback accesses(hits+misses) 2451system.l2c.UpgradeReq_accesses::cpu0.data 58396 # number of UpgradeReq accesses(hits+misses) 2452system.l2c.UpgradeReq_accesses::cpu1.data 64335 # number of UpgradeReq accesses(hits+misses) 2453system.l2c.UpgradeReq_accesses::total 122731 # number of UpgradeReq accesses(hits+misses) 2454system.l2c.SCUpgradeReq_accesses::cpu0.data 18670 # number of SCUpgradeReq accesses(hits+misses) 2455system.l2c.SCUpgradeReq_accesses::cpu1.data 18708 # number of SCUpgradeReq accesses(hits+misses) 2456system.l2c.SCUpgradeReq_accesses::total 37378 # number of SCUpgradeReq accesses(hits+misses) 2457system.l2c.ReadExReq_accesses::cpu0.data 130729 # number of ReadExReq accesses(hits+misses) 2458system.l2c.ReadExReq_accesses::cpu1.data 122135 # number of ReadExReq accesses(hits+misses) 2459system.l2c.ReadExReq_accesses::total 252864 # number of ReadExReq accesses(hits+misses) 2460system.l2c.demand_accesses::cpu0.dtb.walker 9897 # number of demand (read+write) accesses 2461system.l2c.demand_accesses::cpu0.itb.walker 10707 # number of demand (read+write) accesses 2462system.l2c.demand_accesses::cpu0.inst 151014 # number of demand (read+write) accesses 2463system.l2c.demand_accesses::cpu0.data 887139 # number of demand (read+write) accesses 2464system.l2c.demand_accesses::cpu0.l2cache.prefetcher 2059387 # number of demand (read+write) accesses 2465system.l2c.demand_accesses::cpu1.dtb.walker 10338 # number of demand (read+write) accesses 2466system.l2c.demand_accesses::cpu1.itb.walker 10896 # number of demand (read+write) accesses 2467system.l2c.demand_accesses::cpu1.inst 145733 # number of demand (read+write) accesses 2468system.l2c.demand_accesses::cpu1.data 874515 # number of demand (read+write) accesses 2469system.l2c.demand_accesses::cpu1.l2cache.prefetcher 1964238 # number of demand (read+write) accesses 2470system.l2c.demand_accesses::total 6123864 # number of demand (read+write) accesses 2471system.l2c.overall_accesses::cpu0.dtb.walker 9897 # number of overall (read+write) accesses 2472system.l2c.overall_accesses::cpu0.itb.walker 10707 # number of overall (read+write) accesses 2473system.l2c.overall_accesses::cpu0.inst 151014 # number of overall (read+write) accesses 2474system.l2c.overall_accesses::cpu0.data 887139 # number of overall (read+write) accesses 2475system.l2c.overall_accesses::cpu0.l2cache.prefetcher 2059387 # number of overall (read+write) accesses 2476system.l2c.overall_accesses::cpu1.dtb.walker 10338 # number of overall (read+write) accesses 2477system.l2c.overall_accesses::cpu1.itb.walker 10896 # number of overall (read+write) accesses 2478system.l2c.overall_accesses::cpu1.inst 145733 # number of overall (read+write) accesses 2479system.l2c.overall_accesses::cpu1.data 874515 # number of overall (read+write) accesses 2480system.l2c.overall_accesses::cpu1.l2cache.prefetcher 1964238 # number of overall (read+write) accesses 2481system.l2c.overall_accesses::total 6123864 # number of overall (read+write) accesses 2482system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.368496 # miss rate for ReadReq accesses 2483system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.596432 # miss rate for ReadReq accesses 2484system.l2c.ReadReq_miss_rate::cpu0.inst 0.059240 # miss rate for ReadReq accesses 2485system.l2c.ReadReq_miss_rate::cpu0.data 0.179992 # miss rate for ReadReq accesses 2486system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.214149 # miss rate for ReadReq accesses 2487system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.410331 # miss rate for ReadReq accesses 2488system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.627478 # miss rate for ReadReq accesses 2489system.l2c.ReadReq_miss_rate::cpu1.inst 0.057393 # miss rate for ReadReq accesses 2490system.l2c.ReadReq_miss_rate::cpu1.data 0.186908 # miss rate for ReadReq accesses 2491system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.212971 # miss rate for ReadReq accesses 2492system.l2c.ReadReq_miss_rate::total 0.200057 # miss rate for ReadReq accesses 2493system.l2c.UpgradeReq_miss_rate::cpu0.data 0.592969 # miss rate for UpgradeReq accesses 2494system.l2c.UpgradeReq_miss_rate::cpu1.data 0.565493 # miss rate for UpgradeReq accesses 2495system.l2c.UpgradeReq_miss_rate::total 0.578566 # miss rate for UpgradeReq accesses 2496system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.573058 # miss rate for SCUpgradeReq accesses 2497system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.590924 # miss rate for SCUpgradeReq accesses 2498system.l2c.SCUpgradeReq_miss_rate::total 0.582000 # miss rate for SCUpgradeReq accesses 2499system.l2c.ReadExReq_miss_rate::cpu0.data 0.598926 # miss rate for ReadExReq accesses 2500system.l2c.ReadExReq_miss_rate::cpu1.data 0.591821 # miss rate for ReadExReq accesses 2501system.l2c.ReadExReq_miss_rate::total 0.595494 # miss rate for ReadExReq accesses 2502system.l2c.demand_miss_rate::cpu0.dtb.walker 0.368496 # miss rate for demand accesses 2503system.l2c.demand_miss_rate::cpu0.itb.walker 0.596432 # miss rate for demand accesses 2504system.l2c.demand_miss_rate::cpu0.inst 0.059240 # miss rate for demand accesses 2505system.l2c.demand_miss_rate::cpu0.data 0.241726 # miss rate for demand accesses 2506system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.214149 # miss rate for demand accesses 2507system.l2c.demand_miss_rate::cpu1.dtb.walker 0.410331 # miss rate for demand accesses 2508system.l2c.demand_miss_rate::cpu1.itb.walker 0.627478 # miss rate for demand accesses 2509system.l2c.demand_miss_rate::cpu1.inst 0.057393 # miss rate for demand accesses 2510system.l2c.demand_miss_rate::cpu1.data 0.243458 # miss rate for demand accesses 2511system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.212971 # miss rate for demand accesses 2512system.l2c.demand_miss_rate::total 0.216386 # miss rate for demand accesses 2513system.l2c.overall_miss_rate::cpu0.dtb.walker 0.368496 # miss rate for overall accesses 2514system.l2c.overall_miss_rate::cpu0.itb.walker 0.596432 # miss rate for overall accesses 2515system.l2c.overall_miss_rate::cpu0.inst 0.059240 # miss rate for overall accesses 2516system.l2c.overall_miss_rate::cpu0.data 0.241726 # miss rate for overall accesses 2517system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.214149 # miss rate for overall accesses 2518system.l2c.overall_miss_rate::cpu1.dtb.walker 0.410331 # miss rate for overall accesses 2519system.l2c.overall_miss_rate::cpu1.itb.walker 0.627478 # miss rate for overall accesses 2520system.l2c.overall_miss_rate::cpu1.inst 0.057393 # miss rate for overall accesses 2521system.l2c.overall_miss_rate::cpu1.data 0.243458 # miss rate for overall accesses 2522system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.212971 # miss rate for overall accesses 2523system.l2c.overall_miss_rate::total 0.216386 # miss rate for overall accesses 2524system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 79543.596929 # average ReadReq miss latency 2525system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 79953.960852 # average ReadReq miss latency 2526system.l2c.ReadReq_avg_miss_latency::cpu0.inst 88916.945674 # average ReadReq miss latency 2527system.l2c.ReadReq_avg_miss_latency::cpu0.data 81360.474410 # average ReadReq miss latency 2528system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 104623.656960 # average ReadReq miss latency 2529system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79206.211693 # average ReadReq miss latency 2530system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 79319.437765 # average ReadReq miss latency 2531system.l2c.ReadReq_avg_miss_latency::cpu1.inst 88718.375658 # average ReadReq miss latency 2532system.l2c.ReadReq_avg_miss_latency::cpu1.data 81299.485038 # average ReadReq miss latency 2533system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 106194.618122 # average ReadReq miss latency 2534system.l2c.ReadReq_avg_miss_latency::total 99010.018675 # average ReadReq miss latency 2535system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 4246.441909 # average UpgradeReq miss latency 2536system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3905.493664 # average UpgradeReq miss latency 2537system.l2c.UpgradeReq_avg_miss_latency::total 4071.756830 # average UpgradeReq miss latency 2538system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4852.491448 # average SCUpgradeReq miss latency 2539system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5083.957666 # average SCUpgradeReq miss latency 2540system.l2c.SCUpgradeReq_avg_miss_latency::total 4970.118507 # average SCUpgradeReq miss latency 2541system.l2c.ReadExReq_avg_miss_latency::cpu0.data 73139.661302 # average ReadExReq miss latency 2542system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73285.803948 # average ReadExReq miss latency 2543system.l2c.ReadExReq_avg_miss_latency::total 73209.813732 # average ReadExReq miss latency 2544system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 79543.596929 # average overall miss latency 2545system.l2c.demand_avg_miss_latency::cpu0.itb.walker 79953.960852 # average overall miss latency 2546system.l2c.demand_avg_miss_latency::cpu0.inst 88916.945674 # average overall miss latency 2547system.l2c.demand_avg_miss_latency::cpu0.data 78358.935536 # average overall miss latency 2548system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 104623.656960 # average overall miss latency 2549system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79206.211693 # average overall miss latency 2550system.l2c.demand_avg_miss_latency::cpu1.itb.walker 79319.437765 # average overall miss latency 2551system.l2c.demand_avg_miss_latency::cpu1.inst 88718.375658 # average overall miss latency 2552system.l2c.demand_avg_miss_latency::cpu1.data 78578.850320 # average overall miss latency 2553system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 106194.618122 # average overall miss latency 2554system.l2c.demand_avg_miss_latency::total 96078.223225 # average overall miss latency 2555system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 79543.596929 # average overall miss latency 2556system.l2c.overall_avg_miss_latency::cpu0.itb.walker 79953.960852 # average overall miss latency 2557system.l2c.overall_avg_miss_latency::cpu0.inst 88916.945674 # average overall miss latency 2558system.l2c.overall_avg_miss_latency::cpu0.data 78358.935536 # average overall miss latency 2559system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 104623.656960 # average overall miss latency 2560system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79206.211693 # average overall miss latency 2561system.l2c.overall_avg_miss_latency::cpu1.itb.walker 79319.437765 # average overall miss latency 2562system.l2c.overall_avg_miss_latency::cpu1.inst 88718.375658 # average overall miss latency 2563system.l2c.overall_avg_miss_latency::cpu1.data 78578.850320 # average overall miss latency 2564system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 106194.618122 # average overall miss latency 2565system.l2c.overall_avg_miss_latency::total 96078.223225 # average overall miss latency 2566system.l2c.blocked_cycles::no_mshrs 2524 # number of cycles access was blocked 2567system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2568system.l2c.blocked::no_mshrs 54 # number of cycles access was blocked 2569system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2570system.l2c.avg_blocked_cycles::no_mshrs 46.740741 # average number of cycles each access was blocked 2571system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2572system.l2c.fast_writes 0 # number of fast writes performed 2573system.l2c.cache_copies 0 # number of cache copies performed 2574system.l2c.writebacks::writebacks 686491 # number of writebacks 2575system.l2c.writebacks::total 686491 # number of writebacks 2576system.l2c.ReadReq_mshr_hits::cpu0.inst 30 # number of ReadReq MSHR hits 2577system.l2c.ReadReq_mshr_hits::cpu0.data 24 # number of ReadReq MSHR hits 2578system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 289 # number of ReadReq MSHR hits 2579system.l2c.ReadReq_mshr_hits::cpu1.inst 14 # number of ReadReq MSHR hits 2580system.l2c.ReadReq_mshr_hits::cpu1.data 12 # number of ReadReq MSHR hits 2581system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 182 # number of ReadReq MSHR hits 2582system.l2c.ReadReq_mshr_hits::total 551 # number of ReadReq MSHR hits 2583system.l2c.demand_mshr_hits::cpu0.inst 30 # number of demand (read+write) MSHR hits 2584system.l2c.demand_mshr_hits::cpu0.data 24 # number of demand (read+write) MSHR hits 2585system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 289 # number of demand (read+write) MSHR hits 2586system.l2c.demand_mshr_hits::cpu1.inst 14 # number of demand (read+write) MSHR hits 2587system.l2c.demand_mshr_hits::cpu1.data 12 # number of demand (read+write) MSHR hits 2588system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 182 # number of demand (read+write) MSHR hits 2589system.l2c.demand_mshr_hits::total 551 # number of demand (read+write) MSHR hits 2590system.l2c.overall_mshr_hits::cpu0.inst 30 # number of overall MSHR hits 2591system.l2c.overall_mshr_hits::cpu0.data 24 # number of overall MSHR hits 2592system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 289 # number of overall MSHR hits 2593system.l2c.overall_mshr_hits::cpu1.inst 14 # number of overall MSHR hits 2594system.l2c.overall_mshr_hits::cpu1.data 12 # number of overall MSHR hits 2595system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 182 # number of overall MSHR hits 2596system.l2c.overall_mshr_hits::total 551 # number of overall MSHR hits 2597system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 3647 # number of ReadReq MSHR misses 2598system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 6386 # number of ReadReq MSHR misses 2599system.l2c.ReadReq_mshr_misses::cpu0.inst 8916 # number of ReadReq MSHR misses 2600system.l2c.ReadReq_mshr_misses::cpu0.data 136124 # number of ReadReq MSHR misses 2601system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 440727 # number of ReadReq MSHR misses 2602system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4242 # number of ReadReq MSHR misses 2603system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 6837 # number of ReadReq MSHR misses 2604system.l2c.ReadReq_mshr_misses::cpu1.inst 8350 # number of ReadReq MSHR misses 2605system.l2c.ReadReq_mshr_misses::cpu1.data 140614 # number of ReadReq MSHR misses 2606system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 418143 # number of ReadReq MSHR misses 2607system.l2c.ReadReq_mshr_misses::total 1173986 # number of ReadReq MSHR misses 2608system.l2c.UpgradeReq_mshr_misses::cpu0.data 34627 # number of UpgradeReq MSHR misses 2609system.l2c.UpgradeReq_mshr_misses::cpu1.data 36381 # number of UpgradeReq MSHR misses 2610system.l2c.UpgradeReq_mshr_misses::total 71008 # number of UpgradeReq MSHR misses 2611system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 10699 # number of SCUpgradeReq MSHR misses 2612system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11055 # number of SCUpgradeReq MSHR misses 2613system.l2c.SCUpgradeReq_mshr_misses::total 21754 # number of SCUpgradeReq MSHR misses 2614system.l2c.ReadExReq_mshr_misses::cpu0.data 78297 # number of ReadExReq MSHR misses 2615system.l2c.ReadExReq_mshr_misses::cpu1.data 72282 # number of ReadExReq MSHR misses 2616system.l2c.ReadExReq_mshr_misses::total 150579 # number of ReadExReq MSHR misses 2617system.l2c.demand_mshr_misses::cpu0.dtb.walker 3647 # number of demand (read+write) MSHR misses 2618system.l2c.demand_mshr_misses::cpu0.itb.walker 6386 # number of demand (read+write) MSHR misses 2619system.l2c.demand_mshr_misses::cpu0.inst 8916 # number of demand (read+write) MSHR misses 2620system.l2c.demand_mshr_misses::cpu0.data 214421 # number of demand (read+write) MSHR misses 2621system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 440727 # number of demand (read+write) MSHR misses 2622system.l2c.demand_mshr_misses::cpu1.dtb.walker 4242 # number of demand (read+write) MSHR misses 2623system.l2c.demand_mshr_misses::cpu1.itb.walker 6837 # number of demand (read+write) MSHR misses 2624system.l2c.demand_mshr_misses::cpu1.inst 8350 # number of demand (read+write) MSHR misses 2625system.l2c.demand_mshr_misses::cpu1.data 212896 # number of demand (read+write) MSHR misses 2626system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 418143 # number of demand (read+write) MSHR misses 2627system.l2c.demand_mshr_misses::total 1324565 # number of demand (read+write) MSHR misses 2628system.l2c.overall_mshr_misses::cpu0.dtb.walker 3647 # number of overall MSHR misses 2629system.l2c.overall_mshr_misses::cpu0.itb.walker 6386 # number of overall MSHR misses 2630system.l2c.overall_mshr_misses::cpu0.inst 8916 # number of overall MSHR misses 2631system.l2c.overall_mshr_misses::cpu0.data 214421 # number of overall MSHR misses 2632system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 440727 # number of overall MSHR misses 2633system.l2c.overall_mshr_misses::cpu1.dtb.walker 4242 # number of overall MSHR misses 2634system.l2c.overall_mshr_misses::cpu1.itb.walker 6837 # number of overall MSHR misses 2635system.l2c.overall_mshr_misses::cpu1.inst 8350 # number of overall MSHR misses 2636system.l2c.overall_mshr_misses::cpu1.data 212896 # number of overall MSHR misses 2637system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 418143 # number of overall MSHR misses 2638system.l2c.overall_mshr_misses::total 1324565 # number of overall MSHR misses 2639system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 244781998 # number of ReadReq MSHR miss cycles 2640system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 431307994 # number of ReadReq MSHR miss cycles 2641system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 682060496 # number of ReadReq MSHR miss cycles 2642system.l2c.ReadReq_mshr_miss_latency::cpu0.data 9367961184 # number of ReadReq MSHR miss cycles 2643system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 40693405448 # number of ReadReq MSHR miss cycles 2644system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 283137750 # number of ReadReq MSHR miss cycles 2645system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 457339496 # number of ReadReq MSHR miss cycles 2646system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 636822998 # number of ReadReq MSHR miss cycles 2647system.l2c.ReadReq_mshr_miss_latency::cpu1.data 9667271945 # number of ReadReq MSHR miss cycles 2648system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 39253909640 # number of ReadReq MSHR miss cycles 2649system.l2c.ReadReq_mshr_miss_latency::total 101717998949 # number of ReadReq MSHR miss cycles 2650system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 17785049779 # number of WriteInvalidateReq MSHR miss cycles 2651system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 13763550872 # number of WriteInvalidateReq MSHR miss cycles 2652system.l2c.WriteInvalidateReq_mshr_miss_latency::total 31548600651 # number of WriteInvalidateReq MSHR miss cycles 2653system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 351208941 # number of UpgradeReq MSHR miss cycles 2654system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 368943627 # number of UpgradeReq MSHR miss cycles 2655system.l2c.UpgradeReq_mshr_miss_latency::total 720152568 # number of UpgradeReq MSHR miss cycles 2656system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 109133556 # number of SCUpgradeReq MSHR miss cycles 2657system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 113272386 # number of SCUpgradeReq MSHR miss cycles 2658system.l2c.SCUpgradeReq_mshr_miss_latency::total 222405942 # number of SCUpgradeReq MSHR miss cycles 2659system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4739079365 # number of ReadExReq MSHR miss cycles 2660system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4385575961 # number of ReadExReq MSHR miss cycles 2661system.l2c.ReadExReq_mshr_miss_latency::total 9124655326 # number of ReadExReq MSHR miss cycles 2662system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 244781998 # number of demand (read+write) MSHR miss cycles 2663system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 431307994 # number of demand (read+write) MSHR miss cycles 2664system.l2c.demand_mshr_miss_latency::cpu0.inst 682060496 # number of demand (read+write) MSHR miss cycles 2665system.l2c.demand_mshr_miss_latency::cpu0.data 14107040549 # number of demand (read+write) MSHR miss cycles 2666system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 40693405448 # number of demand (read+write) MSHR miss cycles 2667system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 283137750 # number of demand (read+write) MSHR miss cycles 2668system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 457339496 # number of demand (read+write) MSHR miss cycles 2669system.l2c.demand_mshr_miss_latency::cpu1.inst 636822998 # number of demand (read+write) MSHR miss cycles 2670system.l2c.demand_mshr_miss_latency::cpu1.data 14052847906 # number of demand (read+write) MSHR miss cycles 2671system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 39253909640 # number of demand (read+write) MSHR miss cycles 2672system.l2c.demand_mshr_miss_latency::total 110842654275 # number of demand (read+write) MSHR miss cycles 2673system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 244781998 # number of overall MSHR miss cycles 2674system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 431307994 # number of overall MSHR miss cycles 2675system.l2c.overall_mshr_miss_latency::cpu0.inst 682060496 # number of overall MSHR miss cycles 2676system.l2c.overall_mshr_miss_latency::cpu0.data 14107040549 # number of overall MSHR miss cycles 2677system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 40693405448 # number of overall MSHR miss cycles 2678system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 283137750 # number of overall MSHR miss cycles 2679system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 457339496 # number of overall MSHR miss cycles 2680system.l2c.overall_mshr_miss_latency::cpu1.inst 636822998 # number of overall MSHR miss cycles 2681system.l2c.overall_mshr_miss_latency::cpu1.data 14052847906 # number of overall MSHR miss cycles 2682system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 39253909640 # number of overall MSHR miss cycles 2683system.l2c.overall_mshr_miss_latency::total 110842654275 # number of overall MSHR miss cycles 2684system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2246197250 # number of ReadReq MSHR uncacheable cycles 2685system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1903247752 # number of ReadReq MSHR uncacheable cycles 2686system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5835000 # number of ReadReq MSHR uncacheable cycles 2687system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3476254750 # number of ReadReq MSHR uncacheable cycles 2688system.l2c.ReadReq_mshr_uncacheable_latency::total 7631534752 # number of ReadReq MSHR uncacheable cycles 2689system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1855610501 # number of WriteReq MSHR uncacheable cycles 2690system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 3420953000 # number of WriteReq MSHR uncacheable cycles 2691system.l2c.WriteReq_mshr_uncacheable_latency::total 5276563501 # number of WriteReq MSHR uncacheable cycles 2692system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2246197250 # number of overall MSHR uncacheable cycles 2693system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3758858253 # number of overall MSHR uncacheable cycles 2694system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5835000 # number of overall MSHR uncacheable cycles 2695system.l2c.overall_mshr_uncacheable_latency::cpu1.data 6897207750 # number of overall MSHR uncacheable cycles 2696system.l2c.overall_mshr_uncacheable_latency::total 12908098253 # number of overall MSHR uncacheable cycles 2697system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.368496 # mshr miss rate for ReadReq accesses 2698system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.596432 # mshr miss rate for ReadReq accesses 2699system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.059041 # mshr miss rate for ReadReq accesses 2700system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.179961 # mshr miss rate for ReadReq accesses 2701system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.214009 # mshr miss rate for ReadReq accesses 2702system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.410331 # mshr miss rate for ReadReq accesses 2703system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.627478 # mshr miss rate for ReadReq accesses 2704system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.057297 # mshr miss rate for ReadReq accesses 2705system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.186892 # mshr miss rate for ReadReq accesses 2706system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.212878 # mshr miss rate for ReadReq accesses 2707system.l2c.ReadReq_mshr_miss_rate::total 0.199964 # mshr miss rate for ReadReq accesses 2708system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.592969 # mshr miss rate for UpgradeReq accesses 2709system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.565493 # mshr miss rate for UpgradeReq accesses 2710system.l2c.UpgradeReq_mshr_miss_rate::total 0.578566 # mshr miss rate for UpgradeReq accesses 2711system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.573058 # mshr miss rate for SCUpgradeReq accesses 2712system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.590924 # mshr miss rate for SCUpgradeReq accesses 2713system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.582000 # mshr miss rate for SCUpgradeReq accesses 2714system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.598926 # mshr miss rate for ReadExReq accesses 2715system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.591821 # mshr miss rate for ReadExReq accesses 2716system.l2c.ReadExReq_mshr_miss_rate::total 0.595494 # mshr miss rate for ReadExReq accesses 2717system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.368496 # mshr miss rate for demand accesses 2718system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.596432 # mshr miss rate for demand accesses 2719system.l2c.demand_mshr_miss_rate::cpu0.inst 0.059041 # mshr miss rate for demand accesses 2720system.l2c.demand_mshr_miss_rate::cpu0.data 0.241699 # mshr miss rate for demand accesses 2721system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.214009 # mshr miss rate for demand accesses 2722system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.410331 # mshr miss rate for demand accesses 2723system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.627478 # mshr miss rate for demand accesses 2724system.l2c.demand_mshr_miss_rate::cpu1.inst 0.057297 # mshr miss rate for demand accesses 2725system.l2c.demand_mshr_miss_rate::cpu1.data 0.243445 # mshr miss rate for demand accesses 2726system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.212878 # mshr miss rate for demand accesses 2727system.l2c.demand_mshr_miss_rate::total 0.216296 # mshr miss rate for demand accesses 2728system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.368496 # mshr miss rate for overall accesses 2729system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.596432 # mshr miss rate for overall accesses 2730system.l2c.overall_mshr_miss_rate::cpu0.inst 0.059041 # mshr miss rate for overall accesses 2731system.l2c.overall_mshr_miss_rate::cpu0.data 0.241699 # mshr miss rate for overall accesses 2732system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.214009 # mshr miss rate for overall accesses 2733system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.410331 # mshr miss rate for overall accesses 2734system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.627478 # mshr miss rate for overall accesses 2735system.l2c.overall_mshr_miss_rate::cpu1.inst 0.057297 # mshr miss rate for overall accesses 2736system.l2c.overall_mshr_miss_rate::cpu1.data 0.243445 # mshr miss rate for overall accesses 2737system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.212878 # mshr miss rate for overall accesses 2738system.l2c.overall_mshr_miss_rate::total 0.216296 # mshr miss rate for overall accesses 2739system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67118.727173 # average ReadReq mshr miss latency 2740system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 67539.616975 # average ReadReq mshr miss latency 2741system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 76498.485419 # average ReadReq mshr miss latency 2742system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68819.320502 # average ReadReq mshr miss latency 2743system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92332.453986 # average ReadReq mshr miss latency 2744system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66746.287129 # average ReadReq mshr miss latency 2745system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 66891.837941 # average ReadReq mshr miss latency 2746system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 76266.227305 # average ReadReq mshr miss latency 2747system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 68750.422753 # average ReadReq mshr miss latency 2748system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 93876.759003 # average ReadReq mshr miss latency 2749system.l2c.ReadReq_avg_mshr_miss_latency::total 86643.281052 # average ReadReq mshr miss latency 2750system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency 2751system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency 2752system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 2753system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10142.632657 # average UpgradeReq mshr miss latency 2754system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10141.107364 # average UpgradeReq mshr miss latency 2755system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10141.851172 # average UpgradeReq mshr miss latency 2756system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10200.351061 # average SCUpgradeReq mshr miss latency 2757system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10246.258345 # average SCUpgradeReq mshr miss latency 2758system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10223.680335 # average SCUpgradeReq mshr miss latency 2759system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 60526.959717 # average ReadExReq mshr miss latency 2760system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60673.140768 # average ReadExReq mshr miss latency 2761system.l2c.ReadExReq_avg_mshr_miss_latency::total 60597.130583 # average ReadExReq mshr miss latency 2762system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67118.727173 # average overall mshr miss latency 2763system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 67539.616975 # average overall mshr miss latency 2764system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76498.485419 # average overall mshr miss latency 2765system.l2c.demand_avg_mshr_miss_latency::cpu0.data 65791.319642 # average overall mshr miss latency 2766system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92332.453986 # average overall mshr miss latency 2767system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66746.287129 # average overall mshr miss latency 2768system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 66891.837941 # average overall mshr miss latency 2769system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76266.227305 # average overall mshr miss latency 2770system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66008.041044 # average overall mshr miss latency 2771system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 93876.759003 # average overall mshr miss latency 2772system.l2c.demand_avg_mshr_miss_latency::total 83682.306474 # average overall mshr miss latency 2773system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67118.727173 # average overall mshr miss latency 2774system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 67539.616975 # average overall mshr miss latency 2775system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76498.485419 # average overall mshr miss latency 2776system.l2c.overall_avg_mshr_miss_latency::cpu0.data 65791.319642 # average overall mshr miss latency 2777system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92332.453986 # average overall mshr miss latency 2778system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66746.287129 # average overall mshr miss latency 2779system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 66891.837941 # average overall mshr miss latency 2780system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76266.227305 # average overall mshr miss latency 2781system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66008.041044 # average overall mshr miss latency 2782system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 93876.759003 # average overall mshr miss latency 2783system.l2c.overall_avg_mshr_miss_latency::total 83682.306474 # average overall mshr miss latency 2784system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 2785system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 2786system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2787system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2788system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2789system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 2790system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2791system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2792system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 2793system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 2794system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2795system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2796system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2797system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2798system.membus.trans_dist::ReadReq 1264717 # Transaction distribution 2799system.membus.trans_dist::ReadResp 1264717 # Transaction distribution 2800system.membus.trans_dist::WriteReq 38516 # Transaction distribution 2801system.membus.trans_dist::WriteResp 38516 # Transaction distribution 2802system.membus.trans_dist::Writeback 686491 # Transaction distribution 2803system.membus.trans_dist::WriteInvalidateReq 1679861 # Transaction distribution 2804system.membus.trans_dist::WriteInvalidateResp 1679861 # Transaction distribution 2805system.membus.trans_dist::UpgradeReq 316703 # Transaction distribution 2806system.membus.trans_dist::SCUpgradeReq 302467 # Transaction distribution 2807system.membus.trans_dist::UpgradeResp 96183 # Transaction distribution 2808system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution 2809system.membus.trans_dist::ReadExReq 163141 # Transaction distribution 2810system.membus.trans_dist::ReadExResp 147161 # Transaction distribution 2811system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123470 # Packet count per connected master and slave (bytes) 2812system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 2813system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25330 # Packet count per connected master and slave (bytes) 2814system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 7297543 # Packet count per connected master and slave (bytes) 2815system.membus.pkt_count_system.l2c.mem_side::total 7446435 # Packet count per connected master and slave (bytes) 2816system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 230140 # Packet count per connected master and slave (bytes) 2817system.membus.pkt_count_system.iocache.mem_side::total 230140 # Packet count per connected master and slave (bytes) 2818system.membus.pkt_count::total 7676575 # Packet count per connected master and slave (bytes) 2819system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156485 # Cumulative packet size per connected master and slave (bytes) 2820system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 2821system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50660 # Cumulative packet size per connected master and slave (bytes) 2822system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 229346740 # Cumulative packet size per connected master and slave (bytes) 2823system.membus.pkt_size_system.l2c.mem_side::total 229554089 # Cumulative packet size per connected master and slave (bytes) 2824system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7308288 # Cumulative packet size per connected master and slave (bytes) 2825system.membus.pkt_size_system.iocache.mem_side::total 7308288 # Cumulative packet size per connected master and slave (bytes) 2826system.membus.pkt_size::total 236862377 # Cumulative packet size per connected master and slave (bytes) 2827system.membus.snoops 540732 # Total snoops (count) 2828system.membus.snoop_fanout::samples 4331622 # Request fanout histogram 2829system.membus.snoop_fanout::mean 1 # Request fanout histogram 2830system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2831system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2832system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2833system.membus.snoop_fanout::1 4331622 100.00% 100.00% # Request fanout histogram 2834system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2835system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2836system.membus.snoop_fanout::min_value 1 # Request fanout histogram 2837system.membus.snoop_fanout::max_value 1 # Request fanout histogram 2838system.membus.snoop_fanout::total 4331622 # Request fanout histogram 2839system.membus.reqLayer0.occupancy 101146499 # Layer occupancy (ticks) 2840system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2841system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks) 2842system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 2843system.membus.reqLayer2.occupancy 22031996 # Layer occupancy (ticks) 2844system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 2845system.membus.reqLayer5.occupancy 23154905719 # Layer occupancy (ticks) 2846system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 2847system.membus.respLayer2.occupancy 14237686781 # Layer occupancy (ticks) 2848system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 2849system.membus.respLayer3.occupancy 187996205 # Layer occupancy (ticks) 2850system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 2851system.realview.ethernet.txBytes 966 # Bytes Transmitted 2852system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 2853system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 2854system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 2855system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 2856system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2857system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2858system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2859system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2860system.realview.ethernet.totBandwidth 162 # Total Bandwidth (bits/s) 2861system.realview.ethernet.totPackets 3 # Total Packets 2862system.realview.ethernet.totBytes 966 # Total Bytes 2863system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 2864system.realview.ethernet.txBandwidth 162 # Transmit Bandwidth (bits/s) 2865system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 2866system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2867system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 2868system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 2869system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 2870system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 2871system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 2872system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 2873system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 2874system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 2875system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 2876system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 2877system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 2878system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 2879system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 2880system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 2881system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 2882system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 2883system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 2884system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 2885system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 2886system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2887system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2888system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 2889system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2890system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 2891system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 2892system.realview.ethernet.droppedPackets 0 # number of packets dropped 2893system.toL2Bus.trans_dist::ReadReq 6727338 # Transaction distribution 2894system.toL2Bus.trans_dist::ReadResp 6719778 # Transaction distribution 2895system.toL2Bus.trans_dist::WriteReq 38516 # Transaction distribution 2896system.toL2Bus.trans_dist::WriteResp 38516 # Transaction distribution 2897system.toL2Bus.trans_dist::Writeback 1994497 # Transaction distribution 2898system.toL2Bus.trans_dist::WriteInvalidateReq 1679869 # Transaction distribution 2899system.toL2Bus.trans_dist::WriteInvalidateResp 1572877 # Transaction distribution 2900system.toL2Bus.trans_dist::UpgradeReq 365008 # Transaction distribution 2901system.toL2Bus.trans_dist::SCUpgradeReq 318091 # Transaction distribution 2902system.toL2Bus.trans_dist::UpgradeResp 683099 # Transaction distribution 2903system.toL2Bus.trans_dist::SCUpgradeFailReq 80 # Transaction distribution 2904system.toL2Bus.trans_dist::UpgradeFailResp 80 # Transaction distribution 2905system.toL2Bus.trans_dist::ReadExReq 301724 # Transaction distribution 2906system.toL2Bus.trans_dist::ReadExResp 301724 # Transaction distribution 2907system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10020344 # Packet count per connected master and slave (bytes) 2908system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 9267363 # Packet count per connected master and slave (bytes) 2909system.toL2Bus.pkt_count::total 19287707 # Packet count per connected master and slave (bytes) 2910system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 322818441 # Cumulative packet size per connected master and slave (bytes) 2911system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 297911776 # Cumulative packet size per connected master and slave (bytes) 2912system.toL2Bus.pkt_size::total 620730217 # Cumulative packet size per connected master and slave (bytes) 2913system.toL2Bus.snoops 1454894 # Total snoops (count) 2914system.toL2Bus.snoop_fanout::samples 11304872 # Request fanout histogram 2915system.toL2Bus.snoop_fanout::mean 1.010257 # Request fanout histogram 2916system.toL2Bus.snoop_fanout::stdev 0.100757 # Request fanout histogram 2917system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2918system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2919system.toL2Bus.snoop_fanout::1 11188916 98.97% 98.97% # Request fanout histogram 2920system.toL2Bus.snoop_fanout::2 115956 1.03% 100.00% # Request fanout histogram 2921system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2922system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 2923system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2924system.toL2Bus.snoop_fanout::total 11304872 # Request fanout histogram 2925system.toL2Bus.reqLayer0.occupancy 19960086799 # Layer occupancy (ticks) 2926system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2927system.toL2Bus.snoopLayer0.occupancy 6306000 # Layer occupancy (ticks) 2928system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2929system.toL2Bus.respLayer0.occupancy 16653624789 # Layer occupancy (ticks) 2930system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2931system.toL2Bus.respLayer1.occupancy 15972471023 # Layer occupancy (ticks) 2932system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2933 2934---------- End Simulation Statistics ---------- 2935