stats.txt revision 10515
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.438275 # Number of seconds simulated 4sim_ticks 47438274662000 # Number of ticks simulated 5final_tick 47438274662000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 649244 # Simulator instruction rate (inst/s) 8host_op_rate 763603 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 34889420828 # Simulator tick rate (ticks/s) 10host_mem_usage 811016 # Number of bytes of host memory used 11host_seconds 1359.68 # Real time elapsed on the host 12sim_insts 882760938 # Number of instructions simulated 13sim_ops 1038251286 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::realview.ide 477376 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.dtb.walker 221952 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 405952 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 701748 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 13046680 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 27196672 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 278976 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.itb.walker 430208 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.inst 568824 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.data 13928160 # Number of bytes read from this memory 26system.physmem.bytes_read::cpu1.l2cache.prefetcher 27822464 # Number of bytes read from this memory 27system.physmem.bytes_read::total 85079012 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 701748 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 568824 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 1270572 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 44376640 # Number of bytes written to this memory 32system.physmem.bytes_written::realview.ide 6830592 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu0.data 54965772 # Number of bytes written to this memory 34system.physmem.bytes_written::cpu1.data 45117316 # Number of bytes written to this memory 35system.physmem.bytes_written::total 151290320 # Number of bytes written to this memory 36system.physmem.num_reads::realview.ide 7459 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.dtb.walker 3468 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.itb.walker 6343 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.inst 51372 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu0.data 203876 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu0.l2cache.prefetcher 424948 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.dtb.walker 4359 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.itb.walker 6722 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.inst 8976 # Number of read requests responded to by this memory 45system.physmem.num_reads::cpu1.data 217642 # Number of read requests responded to by this memory 46system.physmem.num_reads::cpu1.l2cache.prefetcher 434726 # Number of read requests responded to by this memory 47system.physmem.num_reads::total 1369891 # Number of read requests responded to by this memory 48system.physmem.num_writes::writebacks 693385 # Number of write requests responded to by this memory 49system.physmem.num_writes::realview.ide 106728 # Number of write requests responded to by this memory 50system.physmem.num_writes::cpu0.data 861117 # Number of write requests responded to by this memory 51system.physmem.num_writes::cpu1.data 704959 # Number of write requests responded to by this memory 52system.physmem.num_writes::total 2366189 # Number of write requests responded to by this memory 53system.physmem.bw_read::realview.ide 10063 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.dtb.walker 4679 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.itb.walker 8557 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu0.inst 14793 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu0.data 275024 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu0.l2cache.prefetcher 573307 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.dtb.walker 5881 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.itb.walker 9069 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::cpu1.inst 11991 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::cpu1.data 293606 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_read::cpu1.l2cache.prefetcher 586498 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_read::total 1793468 # Total read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::cpu0.inst 14793 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_inst_read::cpu1.inst 11991 # Instruction read bandwidth from this memory (bytes/s) 67system.physmem.bw_inst_read::total 26784 # Instruction read bandwidth from this memory (bytes/s) 68system.physmem.bw_write::writebacks 935461 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::realview.ide 143989 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_write::cpu0.data 1158680 # Write bandwidth from this memory (bytes/s) 71system.physmem.bw_write::cpu1.data 951074 # Write bandwidth from this memory (bytes/s) 72system.physmem.bw_write::total 3189204 # Write bandwidth from this memory (bytes/s) 73system.physmem.bw_total::writebacks 935461 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::realview.ide 154052 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.dtb.walker 4679 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu0.itb.walker 8557 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu0.inst 14793 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu0.data 1433704 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu0.l2cache.prefetcher 573307 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.dtb.walker 5881 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::cpu1.itb.walker 9069 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::cpu1.inst 11991 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::cpu1.data 1244680 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.bw_total::cpu1.l2cache.prefetcher 586498 # Total bandwidth to/from this memory (bytes/s) 85system.physmem.bw_total::total 4982671 # Total bandwidth to/from this memory (bytes/s) 86system.physmem.readReqs 1369891 # Number of read requests accepted 87system.physmem.writeReqs 2366189 # Number of write requests accepted 88system.physmem.readBursts 1369891 # Number of DRAM read bursts, including those serviced by the write queue 89system.physmem.writeBursts 2366189 # Number of DRAM write bursts, including those merged in the write queue 90system.physmem.bytesReadDRAM 87382976 # Total number of bytes read from DRAM 91system.physmem.bytesReadWrQ 290048 # Total number of bytes read from write queue 92system.physmem.bytesWritten 145690880 # Total number of bytes written to DRAM 93system.physmem.bytesReadSys 85079012 # Total read bytes from the system interface side 94system.physmem.bytesWrittenSys 151290320 # Total written bytes from the system interface side 95system.physmem.servicedByWrQ 4532 # Number of DRAM read bursts serviced by the write queue 96system.physmem.mergedWrBursts 89741 # Number of DRAM write bursts merged with an existing one 97system.physmem.neitherReadNorWriteReqs 95337 # Number of requests that are neither read nor write 98system.physmem.perBankRdBursts::0 80179 # Per bank write bursts 99system.physmem.perBankRdBursts::1 81898 # Per bank write bursts 100system.physmem.perBankRdBursts::2 76695 # Per bank write bursts 101system.physmem.perBankRdBursts::3 88857 # Per bank write bursts 102system.physmem.perBankRdBursts::4 82614 # Per bank write bursts 103system.physmem.perBankRdBursts::5 89869 # Per bank write bursts 104system.physmem.perBankRdBursts::6 79228 # Per bank write bursts 105system.physmem.perBankRdBursts::7 87605 # Per bank write bursts 106system.physmem.perBankRdBursts::8 77754 # Per bank write bursts 107system.physmem.perBankRdBursts::9 127975 # Per bank write bursts 108system.physmem.perBankRdBursts::10 81231 # Per bank write bursts 109system.physmem.perBankRdBursts::11 85621 # Per bank write bursts 110system.physmem.perBankRdBursts::12 74411 # Per bank write bursts 111system.physmem.perBankRdBursts::13 85967 # Per bank write bursts 112system.physmem.perBankRdBursts::14 83368 # Per bank write bursts 113system.physmem.perBankRdBursts::15 82087 # Per bank write bursts 114system.physmem.perBankWrBursts::0 134695 # Per bank write bursts 115system.physmem.perBankWrBursts::1 125793 # Per bank write bursts 116system.physmem.perBankWrBursts::2 142260 # Per bank write bursts 117system.physmem.perBankWrBursts::3 126417 # Per bank write bursts 118system.physmem.perBankWrBursts::4 155026 # Per bank write bursts 119system.physmem.perBankWrBursts::5 152020 # Per bank write bursts 120system.physmem.perBankWrBursts::6 183109 # Per bank write bursts 121system.physmem.perBankWrBursts::7 140837 # Per bank write bursts 122system.physmem.perBankWrBursts::8 128222 # Per bank write bursts 123system.physmem.perBankWrBursts::9 141420 # Per bank write bursts 124system.physmem.perBankWrBursts::10 135722 # Per bank write bursts 125system.physmem.perBankWrBursts::11 146309 # Per bank write bursts 126system.physmem.perBankWrBursts::12 139215 # Per bank write bursts 127system.physmem.perBankWrBursts::13 127398 # Per bank write bursts 128system.physmem.perBankWrBursts::14 153454 # Per bank write bursts 129system.physmem.perBankWrBursts::15 144523 # Per bank write bursts 130system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 131system.physmem.numWrRetry 10 # Number of times write queue was full causing retry 132system.physmem.totGap 47438271681000 # Total gap between requests 133system.physmem.readPktSize::0 0 # Read request sizes (log2) 134system.physmem.readPktSize::1 0 # Read request sizes (log2) 135system.physmem.readPktSize::2 43195 # Read request sizes (log2) 136system.physmem.readPktSize::3 37 # Read request sizes (log2) 137system.physmem.readPktSize::4 5 # Read request sizes (log2) 138system.physmem.readPktSize::5 0 # Read request sizes (log2) 139system.physmem.readPktSize::6 1326654 # Read request sizes (log2) 140system.physmem.writePktSize::0 0 # Write request sizes (log2) 141system.physmem.writePktSize::1 0 # Write request sizes (log2) 142system.physmem.writePktSize::2 2 # Write request sizes (log2) 143system.physmem.writePktSize::3 2601 # Write request sizes (log2) 144system.physmem.writePktSize::4 0 # Write request sizes (log2) 145system.physmem.writePktSize::5 0 # Write request sizes (log2) 146system.physmem.writePktSize::6 2363586 # Write request sizes (log2) 147system.physmem.rdQLenPdf::0 850336 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::1 158236 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::2 84690 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::3 68857 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::4 51684 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::5 44428 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::6 38277 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::7 32108 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::8 25287 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::9 4479 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::10 1980 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::11 1373 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::12 1021 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::13 801 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::14 610 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::15 432 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::16 308 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::17 239 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::18 120 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::19 85 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 176system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 177system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 178system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 179system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::15 89049 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::16 97576 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::17 118285 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::18 123036 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::19 124126 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::20 148935 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::21 133751 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::22 128713 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::23 131381 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::24 133864 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::25 133437 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::26 132728 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::27 131540 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::28 133641 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::29 128245 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::30 124149 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::31 123411 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::32 120132 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::33 5326 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::34 4141 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::35 2999 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::36 1716 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::37 855 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::38 486 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::39 413 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::40 390 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::41 351 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::42 324 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::43 306 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::44 312 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::45 307 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::46 291 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::47 275 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::48 267 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::49 225 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::50 201 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::51 177 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::52 178 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::53 179 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::54 152 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::55 131 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::56 114 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::57 87 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::58 73 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::59 52 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::60 34 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::61 31 # What write queue length does an incoming req see 241system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see 242system.physmem.wrQLenPdf::63 22 # What write queue length does an incoming req see 243system.physmem.bytesPerActivate::samples 831449 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::mean 280.321107 # Bytes accessed per row activation 245system.physmem.bytesPerActivate::gmean 152.348246 # Bytes accessed per row activation 246system.physmem.bytesPerActivate::stdev 337.173071 # Bytes accessed per row activation 247system.physmem.bytesPerActivate::0-127 412387 49.60% 49.60% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::128-255 160013 19.25% 68.84% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::256-383 57469 6.91% 75.76% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::384-511 29190 3.51% 79.27% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::512-639 24961 3.00% 82.27% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::640-767 16130 1.94% 84.21% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::768-895 12424 1.49% 85.70% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::896-1023 12438 1.50% 87.20% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::1024-1151 106437 12.80% 100.00% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::total 831449 # Bytes accessed per row activation 257system.physmem.rdPerTurnAround::samples 117879 # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::mean 11.582360 # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::stdev 193.016425 # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::0-2047 117876 100.00% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::20480-22527 1 0.00% 100.00% # Reads before turning the bus around for writes 262system.physmem.rdPerTurnAround::24576-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 263system.physmem.rdPerTurnAround::57344-59391 1 0.00% 100.00% # Reads before turning the bus around for writes 264system.physmem.rdPerTurnAround::total 117879 # Reads before turning the bus around for writes 265system.physmem.wrPerTurnAround::samples 117879 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::mean 19.311497 # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::gmean 18.988433 # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::stdev 4.874271 # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::16-19 75351 63.92% 63.92% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::20-23 36700 31.13% 95.06% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::24-27 3007 2.55% 97.61% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::28-31 902 0.77% 98.37% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::32-35 786 0.67% 99.04% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::36-39 199 0.17% 99.21% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::40-43 149 0.13% 99.33% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::44-47 77 0.07% 99.40% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::48-51 81 0.07% 99.47% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::52-55 16 0.01% 99.48% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::56-59 14 0.01% 99.49% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::60-63 14 0.01% 99.51% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::64-67 396 0.34% 99.84% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::68-71 29 0.02% 99.87% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::72-75 39 0.03% 99.90% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::76-79 22 0.02% 99.92% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::80-83 47 0.04% 99.96% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::92-95 4 0.00% 99.96% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::96-99 10 0.01% 99.97% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::100-103 1 0.00% 99.97% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::104-107 4 0.00% 99.97% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::108-111 2 0.00% 99.98% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::112-115 6 0.01% 99.98% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::120-123 1 0.00% 99.98% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::124-127 1 0.00% 99.98% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::128-131 15 0.01% 99.99% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::136-139 1 0.00% 100.00% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::140-143 4 0.00% 100.00% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::168-171 1 0.00% 100.00% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::total 117879 # Writes before turning the bus around for reads 299system.physmem.totQLat 39355914512 # Total ticks spent queuing 300system.physmem.totMemAccLat 64956395762 # Total ticks spent from burst creation until serviced by the DRAM 301system.physmem.totBusLat 6826795000 # Total ticks spent in databus transfers 302system.physmem.avgQLat 28824.59 # Average queueing delay per DRAM burst 303system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 304system.physmem.avgMemAccLat 47574.59 # Average memory access latency per DRAM burst 305system.physmem.avgRdBW 1.84 # Average DRAM read bandwidth in MiByte/s 306system.physmem.avgWrBW 3.07 # Average achieved write bandwidth in MiByte/s 307system.physmem.avgRdBWSys 1.79 # Average system read bandwidth in MiByte/s 308system.physmem.avgWrBWSys 3.19 # Average system write bandwidth in MiByte/s 309system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 310system.physmem.busUtil 0.04 # Data bus utilization in percentage 311system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 312system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 313system.physmem.avgRdQLen 1.35 # Average read queue length when enqueuing 314system.physmem.avgWrQLen 26.79 # Average write queue length when enqueuing 315system.physmem.readRowHits 1064531 # Number of row buffer hits during reads 316system.physmem.writeRowHits 1745793 # Number of row buffer hits during writes 317system.physmem.readRowHitRate 77.97 # Row buffer hit rate for reads 318system.physmem.writeRowHitRate 76.69 # Row buffer hit rate for writes 319system.physmem.avgGap 12697338.30 # Average gap between requests 320system.physmem.pageHitRate 77.17 # Row buffer hit rate, read and write combined 321system.physmem.memoryStateTime::IDLE 45390521349500 # Time in different power states 322system.physmem.memoryStateTime::REF 1584068200000 # Time in different power states 323system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 324system.physmem.memoryStateTime::ACT 463683887500 # Time in different power states 325system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 326system.physmem.actEnergy::0 3148966800 # Energy for activate commands per rank (pJ) 327system.physmem.actEnergy::1 3136780080 # Energy for activate commands per rank (pJ) 328system.physmem.preEnergy::0 1718186250 # Energy for precharge commands per rank (pJ) 329system.physmem.preEnergy::1 1711536750 # Energy for precharge commands per rank (pJ) 330system.physmem.readEnergy::0 5202085200 # Energy for read commands per rank (pJ) 331system.physmem.readEnergy::1 5447566800 # Energy for read commands per rank (pJ) 332system.physmem.writeEnergy::0 7517817360 # Energy for write commands per rank (pJ) 333system.physmem.writeEnergy::1 7233384240 # Energy for write commands per rank (pJ) 334system.physmem.refreshEnergy::0 3098437399200 # Energy for refresh commands per rank (pJ) 335system.physmem.refreshEnergy::1 3098437399200 # Energy for refresh commands per rank (pJ) 336system.physmem.actBackEnergy::0 1260445205745 # Energy for active background per rank (pJ) 337system.physmem.actBackEnergy::1 1262996298315 # Energy for active background per rank (pJ) 338system.physmem.preBackEnergy::0 27357310364250 # Energy for precharge background per rank (pJ) 339system.physmem.preBackEnergy::1 27355072563750 # Energy for precharge background per rank (pJ) 340system.physmem.totalEnergy::0 31733780024805 # Total energy per rank (pJ) 341system.physmem.totalEnergy::1 31734035529135 # Total energy per rank (pJ) 342system.physmem.averagePower::0 668.948883 # Core power per rank (mW) 343system.physmem.averagePower::1 668.954269 # Core power per rank (mW) 344system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 345system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 346system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 347system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 348system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 349system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 350system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 351system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 352system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 353system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 354system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 355system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 356system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 357system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 358system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 359system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 360system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 361system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 362system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 363system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 364system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 365system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 366system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 367system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 368system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 369system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 370system.membus.trans_dist::ReadReq 1262651 # Transaction distribution 371system.membus.trans_dist::ReadResp 1262651 # Transaction distribution 372system.membus.trans_dist::WriteReq 38160 # Transaction distribution 373system.membus.trans_dist::WriteResp 38160 # Transaction distribution 374system.membus.trans_dist::Writeback 693385 # Transaction distribution 375system.membus.trans_dist::WriteInvalidateReq 1670201 # Transaction distribution 376system.membus.trans_dist::WriteInvalidateResp 1670201 # Transaction distribution 377system.membus.trans_dist::UpgradeReq 307572 # Transaction distribution 378system.membus.trans_dist::SCUpgradeReq 298715 # Transaction distribution 379system.membus.trans_dist::UpgradeResp 95343 # Transaction distribution 380system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution 381system.membus.trans_dist::ReadExReq 162530 # Transaction distribution 382system.membus.trans_dist::ReadExResp 146943 # Transaction distribution 383system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123084 # Packet count per connected master and slave (bytes) 384system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 385system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24300 # Packet count per connected master and slave (bytes) 386system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 7267614 # Packet count per connected master and slave (bytes) 387system.membus.pkt_count_system.l2c.mem_side::total 7415090 # Packet count per connected master and slave (bytes) 388system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 229896 # Packet count per connected master and slave (bytes) 389system.membus.pkt_count_system.iocache.mem_side::total 229896 # Packet count per connected master and slave (bytes) 390system.membus.pkt_count::total 7644986 # Packet count per connected master and slave (bytes) 391system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156191 # Cumulative packet size per connected master and slave (bytes) 392system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 393system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 48600 # Cumulative packet size per connected master and slave (bytes) 394system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 229061364 # Cumulative packet size per connected master and slave (bytes) 395system.membus.pkt_size_system.l2c.mem_side::total 229266359 # Cumulative packet size per connected master and slave (bytes) 396system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7307968 # Cumulative packet size per connected master and slave (bytes) 397system.membus.pkt_size_system.iocache.mem_side::total 7307968 # Cumulative packet size per connected master and slave (bytes) 398system.membus.pkt_size::total 236574327 # Cumulative packet size per connected master and slave (bytes) 399system.membus.snoops 528061 # Total snoops (count) 400system.membus.snoop_fanout::samples 4313648 # Request fanout histogram 401system.membus.snoop_fanout::mean 1 # Request fanout histogram 402system.membus.snoop_fanout::stdev 0 # Request fanout histogram 403system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 404system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 405system.membus.snoop_fanout::1 4313648 100.00% 100.00% # Request fanout histogram 406system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 407system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 408system.membus.snoop_fanout::min_value 1 # Request fanout histogram 409system.membus.snoop_fanout::max_value 1 # Request fanout histogram 410system.membus.snoop_fanout::total 4313648 # Request fanout histogram 411system.membus.reqLayer0.occupancy 100869991 # Layer occupancy (ticks) 412system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 413system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks) 414system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 415system.membus.reqLayer2.occupancy 21144997 # Layer occupancy (ticks) 416system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 417system.membus.reqLayer5.occupancy 23127462719 # Layer occupancy (ticks) 418system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 419system.membus.respLayer2.occupancy 14206266380 # Layer occupancy (ticks) 420system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 421system.membus.respLayer3.occupancy 187834022 # Layer occupancy (ticks) 422system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 423system.cpu_clk_domain.clock 500 # Clock period in ticks 424system.l2c.tags.replacements 1088949 # number of replacements 425system.l2c.tags.tagsinuse 64239.358232 # Cycle average of tags in use 426system.l2c.tags.total_refs 6591556 # Total number of references to valid blocks. 427system.l2c.tags.sampled_refs 1149786 # Sample count of references to valid blocks. 428system.l2c.tags.avg_refs 5.732855 # Average number of references to valid blocks. 429system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 430system.l2c.tags.occ_blocks::writebacks 9309.879147 # Average occupied blocks per requestor 431system.l2c.tags.occ_blocks::cpu0.dtb.walker 38.225449 # Average occupied blocks per requestor 432system.l2c.tags.occ_blocks::cpu0.itb.walker 41.200627 # Average occupied blocks per requestor 433system.l2c.tags.occ_blocks::cpu0.inst 627.976202 # Average occupied blocks per requestor 434system.l2c.tags.occ_blocks::cpu0.data 3676.898634 # Average occupied blocks per requestor 435system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 16318.952466 # Average occupied blocks per requestor 436system.l2c.tags.occ_blocks::cpu1.dtb.walker 311.035795 # Average occupied blocks per requestor 437system.l2c.tags.occ_blocks::cpu1.itb.walker 436.956601 # Average occupied blocks per requestor 438system.l2c.tags.occ_blocks::cpu1.inst 693.970644 # Average occupied blocks per requestor 439system.l2c.tags.occ_blocks::cpu1.data 9626.822610 # Average occupied blocks per requestor 440system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 23157.440058 # Average occupied blocks per requestor 441system.l2c.tags.occ_percent::writebacks 0.142057 # Average percentage of cache occupancy 442system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000583 # Average percentage of cache occupancy 443system.l2c.tags.occ_percent::cpu0.itb.walker 0.000629 # Average percentage of cache occupancy 444system.l2c.tags.occ_percent::cpu0.inst 0.009582 # Average percentage of cache occupancy 445system.l2c.tags.occ_percent::cpu0.data 0.056105 # Average percentage of cache occupancy 446system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.249007 # Average percentage of cache occupancy 447system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004746 # Average percentage of cache occupancy 448system.l2c.tags.occ_percent::cpu1.itb.walker 0.006667 # Average percentage of cache occupancy 449system.l2c.tags.occ_percent::cpu1.inst 0.010589 # Average percentage of cache occupancy 450system.l2c.tags.occ_percent::cpu1.data 0.146894 # Average percentage of cache occupancy 451system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.353354 # Average percentage of cache occupancy 452system.l2c.tags.occ_percent::total 0.980215 # Average percentage of cache occupancy 453system.l2c.tags.occ_task_id_blocks::1022 32295 # Occupied blocks per task id 454system.l2c.tags.occ_task_id_blocks::1023 314 # Occupied blocks per task id 455system.l2c.tags.occ_task_id_blocks::1024 28228 # Occupied blocks per task id 456system.l2c.tags.age_task_id_blocks_1022::0 21 # Occupied blocks per task id 457system.l2c.tags.age_task_id_blocks_1022::1 137 # Occupied blocks per task id 458system.l2c.tags.age_task_id_blocks_1022::2 836 # Occupied blocks per task id 459system.l2c.tags.age_task_id_blocks_1022::3 1678 # Occupied blocks per task id 460system.l2c.tags.age_task_id_blocks_1022::4 29623 # Occupied blocks per task id 461system.l2c.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id 462system.l2c.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id 463system.l2c.tags.age_task_id_blocks_1023::3 31 # Occupied blocks per task id 464system.l2c.tags.age_task_id_blocks_1023::4 268 # Occupied blocks per task id 465system.l2c.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id 466system.l2c.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id 467system.l2c.tags.age_task_id_blocks_1024::2 1122 # Occupied blocks per task id 468system.l2c.tags.age_task_id_blocks_1024::3 4068 # Occupied blocks per task id 469system.l2c.tags.age_task_id_blocks_1024::4 22816 # Occupied blocks per task id 470system.l2c.tags.occ_task_id_percent::1022 0.492783 # Percentage of cache occupancy per task id 471system.l2c.tags.occ_task_id_percent::1023 0.004791 # Percentage of cache occupancy per task id 472system.l2c.tags.occ_task_id_percent::1024 0.430725 # Percentage of cache occupancy per task id 473system.l2c.tags.tag_accesses 79894517 # Number of tag accesses 474system.l2c.tags.data_accesses 79894517 # Number of data accesses 475system.l2c.ReadReq_hits::cpu0.dtb.walker 5969 # number of ReadReq hits 476system.l2c.ReadReq_hits::cpu0.itb.walker 3906 # number of ReadReq hits 477system.l2c.ReadReq_hits::cpu0.inst 130836 # number of ReadReq hits 478system.l2c.ReadReq_hits::cpu0.data 569496 # number of ReadReq hits 479system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 1489116 # number of ReadReq hits 480system.l2c.ReadReq_hits::cpu1.dtb.walker 6350 # number of ReadReq hits 481system.l2c.ReadReq_hits::cpu1.itb.walker 4630 # number of ReadReq hits 482system.l2c.ReadReq_hits::cpu1.inst 144360 # number of ReadReq hits 483system.l2c.ReadReq_hits::cpu1.data 647503 # number of ReadReq hits 484system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 1630669 # number of ReadReq hits 485system.l2c.ReadReq_hits::total 4632835 # number of ReadReq hits 486system.l2c.Writeback_hits::writebacks 1982686 # number of Writeback hits 487system.l2c.Writeback_hits::total 1982686 # number of Writeback hits 488system.l2c.UpgradeReq_hits::cpu0.data 22177 # number of UpgradeReq hits 489system.l2c.UpgradeReq_hits::cpu1.data 28734 # number of UpgradeReq hits 490system.l2c.UpgradeReq_hits::total 50911 # number of UpgradeReq hits 491system.l2c.SCUpgradeReq_hits::cpu0.data 6966 # number of SCUpgradeReq hits 492system.l2c.SCUpgradeReq_hits::cpu1.data 8106 # number of SCUpgradeReq hits 493system.l2c.SCUpgradeReq_hits::total 15072 # number of SCUpgradeReq hits 494system.l2c.ReadExReq_hits::cpu0.data 48437 # number of ReadExReq hits 495system.l2c.ReadExReq_hits::cpu1.data 51237 # number of ReadExReq hits 496system.l2c.ReadExReq_hits::total 99674 # number of ReadExReq hits 497system.l2c.demand_hits::cpu0.dtb.walker 5969 # number of demand (read+write) hits 498system.l2c.demand_hits::cpu0.itb.walker 3906 # number of demand (read+write) hits 499system.l2c.demand_hits::cpu0.inst 130836 # number of demand (read+write) hits 500system.l2c.demand_hits::cpu0.data 617933 # number of demand (read+write) hits 501system.l2c.demand_hits::cpu0.l2cache.prefetcher 1489116 # number of demand (read+write) hits 502system.l2c.demand_hits::cpu1.dtb.walker 6350 # number of demand (read+write) hits 503system.l2c.demand_hits::cpu1.itb.walker 4630 # number of demand (read+write) hits 504system.l2c.demand_hits::cpu1.inst 144360 # number of demand (read+write) hits 505system.l2c.demand_hits::cpu1.data 698740 # number of demand (read+write) hits 506system.l2c.demand_hits::cpu1.l2cache.prefetcher 1630669 # number of demand (read+write) hits 507system.l2c.demand_hits::total 4732509 # number of demand (read+write) hits 508system.l2c.overall_hits::cpu0.dtb.walker 5969 # number of overall hits 509system.l2c.overall_hits::cpu0.itb.walker 3906 # number of overall hits 510system.l2c.overall_hits::cpu0.inst 130836 # number of overall hits 511system.l2c.overall_hits::cpu0.data 617933 # number of overall hits 512system.l2c.overall_hits::cpu0.l2cache.prefetcher 1489116 # number of overall hits 513system.l2c.overall_hits::cpu1.dtb.walker 6350 # number of overall hits 514system.l2c.overall_hits::cpu1.itb.walker 4630 # number of overall hits 515system.l2c.overall_hits::cpu1.inst 144360 # number of overall hits 516system.l2c.overall_hits::cpu1.data 698740 # number of overall hits 517system.l2c.overall_hits::cpu1.l2cache.prefetcher 1630669 # number of overall hits 518system.l2c.overall_hits::total 4732509 # number of overall hits 519system.l2c.ReadReq_misses::cpu0.dtb.walker 3468 # number of ReadReq misses 520system.l2c.ReadReq_misses::cpu0.itb.walker 6343 # number of ReadReq misses 521system.l2c.ReadReq_misses::cpu0.inst 8294 # number of ReadReq misses 522system.l2c.ReadReq_misses::cpu0.data 128231 # number of ReadReq misses 523system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 425212 # number of ReadReq misses 524system.l2c.ReadReq_misses::cpu1.dtb.walker 4359 # number of ReadReq misses 525system.l2c.ReadReq_misses::cpu1.itb.walker 6722 # number of ReadReq misses 526system.l2c.ReadReq_misses::cpu1.inst 8893 # number of ReadReq misses 527system.l2c.ReadReq_misses::cpu1.data 146336 # number of ReadReq misses 528system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 434855 # number of ReadReq misses 529system.l2c.ReadReq_misses::total 1172713 # number of ReadReq misses 530system.l2c.UpgradeReq_misses::cpu0.data 33912 # number of UpgradeReq misses 531system.l2c.UpgradeReq_misses::cpu1.data 36287 # number of UpgradeReq misses 532system.l2c.UpgradeReq_misses::total 70199 # number of UpgradeReq misses 533system.l2c.SCUpgradeReq_misses::cpu0.data 10020 # number of SCUpgradeReq misses 534system.l2c.SCUpgradeReq_misses::cpu1.data 11790 # number of SCUpgradeReq misses 535system.l2c.SCUpgradeReq_misses::total 21810 # number of SCUpgradeReq misses 536system.l2c.ReadExReq_misses::cpu0.data 77130 # number of ReadExReq misses 537system.l2c.ReadExReq_misses::cpu1.data 73144 # number of ReadExReq misses 538system.l2c.ReadExReq_misses::total 150274 # number of ReadExReq misses 539system.l2c.demand_misses::cpu0.dtb.walker 3468 # number of demand (read+write) misses 540system.l2c.demand_misses::cpu0.itb.walker 6343 # number of demand (read+write) misses 541system.l2c.demand_misses::cpu0.inst 8294 # number of demand (read+write) misses 542system.l2c.demand_misses::cpu0.data 205361 # number of demand (read+write) misses 543system.l2c.demand_misses::cpu0.l2cache.prefetcher 425212 # number of demand (read+write) misses 544system.l2c.demand_misses::cpu1.dtb.walker 4359 # number of demand (read+write) misses 545system.l2c.demand_misses::cpu1.itb.walker 6722 # number of demand (read+write) misses 546system.l2c.demand_misses::cpu1.inst 8893 # number of demand (read+write) misses 547system.l2c.demand_misses::cpu1.data 219480 # number of demand (read+write) misses 548system.l2c.demand_misses::cpu1.l2cache.prefetcher 434855 # number of demand (read+write) misses 549system.l2c.demand_misses::total 1322987 # number of demand (read+write) misses 550system.l2c.overall_misses::cpu0.dtb.walker 3468 # number of overall misses 551system.l2c.overall_misses::cpu0.itb.walker 6343 # number of overall misses 552system.l2c.overall_misses::cpu0.inst 8294 # number of overall misses 553system.l2c.overall_misses::cpu0.data 205361 # number of overall misses 554system.l2c.overall_misses::cpu0.l2cache.prefetcher 425212 # number of overall misses 555system.l2c.overall_misses::cpu1.dtb.walker 4359 # number of overall misses 556system.l2c.overall_misses::cpu1.itb.walker 6722 # number of overall misses 557system.l2c.overall_misses::cpu1.inst 8893 # number of overall misses 558system.l2c.overall_misses::cpu1.data 219480 # number of overall misses 559system.l2c.overall_misses::cpu1.l2cache.prefetcher 434855 # number of overall misses 560system.l2c.overall_misses::total 1322987 # number of overall misses 561system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 277093747 # number of ReadReq miss cycles 562system.l2c.ReadReq_miss_latency::cpu0.itb.walker 508086991 # number of ReadReq miss cycles 563system.l2c.ReadReq_miss_latency::cpu0.inst 728511746 # number of ReadReq miss cycles 564system.l2c.ReadReq_miss_latency::cpu0.data 10412911614 # number of ReadReq miss cycles 565system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 44677211677 # number of ReadReq miss cycles 566system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 344069994 # number of ReadReq miss cycles 567system.l2c.ReadReq_miss_latency::cpu1.itb.walker 530104242 # number of ReadReq miss cycles 568system.l2c.ReadReq_miss_latency::cpu1.inst 794513741 # number of ReadReq miss cycles 569system.l2c.ReadReq_miss_latency::cpu1.data 11896672640 # number of ReadReq miss cycles 570system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 46121255625 # number of ReadReq miss cycles 571system.l2c.ReadReq_miss_latency::total 116290432017 # number of ReadReq miss cycles 572system.l2c.UpgradeReq_miss_latency::cpu0.data 136371763 # number of UpgradeReq miss cycles 573system.l2c.UpgradeReq_miss_latency::cpu1.data 151914842 # number of UpgradeReq miss cycles 574system.l2c.UpgradeReq_miss_latency::total 288286605 # number of UpgradeReq miss cycles 575system.l2c.SCUpgradeReq_miss_latency::cpu0.data 46986513 # number of SCUpgradeReq miss cycles 576system.l2c.SCUpgradeReq_miss_latency::cpu1.data 56444140 # number of SCUpgradeReq miss cycles 577system.l2c.SCUpgradeReq_miss_latency::total 103430653 # number of SCUpgradeReq miss cycles 578system.l2c.ReadExReq_miss_latency::cpu0.data 5663882239 # number of ReadExReq miss cycles 579system.l2c.ReadExReq_miss_latency::cpu1.data 5345531625 # number of ReadExReq miss cycles 580system.l2c.ReadExReq_miss_latency::total 11009413864 # number of ReadExReq miss cycles 581system.l2c.demand_miss_latency::cpu0.dtb.walker 277093747 # number of demand (read+write) miss cycles 582system.l2c.demand_miss_latency::cpu0.itb.walker 508086991 # number of demand (read+write) miss cycles 583system.l2c.demand_miss_latency::cpu0.inst 728511746 # number of demand (read+write) miss cycles 584system.l2c.demand_miss_latency::cpu0.data 16076793853 # number of demand (read+write) miss cycles 585system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 44677211677 # number of demand (read+write) miss cycles 586system.l2c.demand_miss_latency::cpu1.dtb.walker 344069994 # number of demand (read+write) miss cycles 587system.l2c.demand_miss_latency::cpu1.itb.walker 530104242 # number of demand (read+write) miss cycles 588system.l2c.demand_miss_latency::cpu1.inst 794513741 # number of demand (read+write) miss cycles 589system.l2c.demand_miss_latency::cpu1.data 17242204265 # number of demand (read+write) miss cycles 590system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 46121255625 # number of demand (read+write) miss cycles 591system.l2c.demand_miss_latency::total 127299845881 # number of demand (read+write) miss cycles 592system.l2c.overall_miss_latency::cpu0.dtb.walker 277093747 # number of overall miss cycles 593system.l2c.overall_miss_latency::cpu0.itb.walker 508086991 # number of overall miss cycles 594system.l2c.overall_miss_latency::cpu0.inst 728511746 # number of overall miss cycles 595system.l2c.overall_miss_latency::cpu0.data 16076793853 # number of overall miss cycles 596system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 44677211677 # number of overall miss cycles 597system.l2c.overall_miss_latency::cpu1.dtb.walker 344069994 # number of overall miss cycles 598system.l2c.overall_miss_latency::cpu1.itb.walker 530104242 # number of overall miss cycles 599system.l2c.overall_miss_latency::cpu1.inst 794513741 # number of overall miss cycles 600system.l2c.overall_miss_latency::cpu1.data 17242204265 # number of overall miss cycles 601system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 46121255625 # number of overall miss cycles 602system.l2c.overall_miss_latency::total 127299845881 # number of overall miss cycles 603system.l2c.ReadReq_accesses::cpu0.dtb.walker 9437 # number of ReadReq accesses(hits+misses) 604system.l2c.ReadReq_accesses::cpu0.itb.walker 10249 # number of ReadReq accesses(hits+misses) 605system.l2c.ReadReq_accesses::cpu0.inst 139130 # number of ReadReq accesses(hits+misses) 606system.l2c.ReadReq_accesses::cpu0.data 697727 # number of ReadReq accesses(hits+misses) 607system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 1914328 # number of ReadReq accesses(hits+misses) 608system.l2c.ReadReq_accesses::cpu1.dtb.walker 10709 # number of ReadReq accesses(hits+misses) 609system.l2c.ReadReq_accesses::cpu1.itb.walker 11352 # number of ReadReq accesses(hits+misses) 610system.l2c.ReadReq_accesses::cpu1.inst 153253 # number of ReadReq accesses(hits+misses) 611system.l2c.ReadReq_accesses::cpu1.data 793839 # number of ReadReq accesses(hits+misses) 612system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 2065524 # number of ReadReq accesses(hits+misses) 613system.l2c.ReadReq_accesses::total 5805548 # number of ReadReq accesses(hits+misses) 614system.l2c.Writeback_accesses::writebacks 1982686 # number of Writeback accesses(hits+misses) 615system.l2c.Writeback_accesses::total 1982686 # number of Writeback accesses(hits+misses) 616system.l2c.UpgradeReq_accesses::cpu0.data 56089 # number of UpgradeReq accesses(hits+misses) 617system.l2c.UpgradeReq_accesses::cpu1.data 65021 # number of UpgradeReq accesses(hits+misses) 618system.l2c.UpgradeReq_accesses::total 121110 # number of UpgradeReq accesses(hits+misses) 619system.l2c.SCUpgradeReq_accesses::cpu0.data 16986 # number of SCUpgradeReq accesses(hits+misses) 620system.l2c.SCUpgradeReq_accesses::cpu1.data 19896 # number of SCUpgradeReq accesses(hits+misses) 621system.l2c.SCUpgradeReq_accesses::total 36882 # number of SCUpgradeReq accesses(hits+misses) 622system.l2c.ReadExReq_accesses::cpu0.data 125567 # number of ReadExReq accesses(hits+misses) 623system.l2c.ReadExReq_accesses::cpu1.data 124381 # number of ReadExReq accesses(hits+misses) 624system.l2c.ReadExReq_accesses::total 249948 # number of ReadExReq accesses(hits+misses) 625system.l2c.demand_accesses::cpu0.dtb.walker 9437 # number of demand (read+write) accesses 626system.l2c.demand_accesses::cpu0.itb.walker 10249 # number of demand (read+write) accesses 627system.l2c.demand_accesses::cpu0.inst 139130 # number of demand (read+write) accesses 628system.l2c.demand_accesses::cpu0.data 823294 # number of demand (read+write) accesses 629system.l2c.demand_accesses::cpu0.l2cache.prefetcher 1914328 # number of demand (read+write) accesses 630system.l2c.demand_accesses::cpu1.dtb.walker 10709 # number of demand (read+write) accesses 631system.l2c.demand_accesses::cpu1.itb.walker 11352 # number of demand (read+write) accesses 632system.l2c.demand_accesses::cpu1.inst 153253 # number of demand (read+write) accesses 633system.l2c.demand_accesses::cpu1.data 918220 # number of demand (read+write) accesses 634system.l2c.demand_accesses::cpu1.l2cache.prefetcher 2065524 # number of demand (read+write) accesses 635system.l2c.demand_accesses::total 6055496 # number of demand (read+write) accesses 636system.l2c.overall_accesses::cpu0.dtb.walker 9437 # number of overall (read+write) accesses 637system.l2c.overall_accesses::cpu0.itb.walker 10249 # number of overall (read+write) accesses 638system.l2c.overall_accesses::cpu0.inst 139130 # number of overall (read+write) accesses 639system.l2c.overall_accesses::cpu0.data 823294 # number of overall (read+write) accesses 640system.l2c.overall_accesses::cpu0.l2cache.prefetcher 1914328 # number of overall (read+write) accesses 641system.l2c.overall_accesses::cpu1.dtb.walker 10709 # number of overall (read+write) accesses 642system.l2c.overall_accesses::cpu1.itb.walker 11352 # number of overall (read+write) accesses 643system.l2c.overall_accesses::cpu1.inst 153253 # number of overall (read+write) accesses 644system.l2c.overall_accesses::cpu1.data 918220 # number of overall (read+write) accesses 645system.l2c.overall_accesses::cpu1.l2cache.prefetcher 2065524 # number of overall (read+write) accesses 646system.l2c.overall_accesses::total 6055496 # number of overall (read+write) accesses 647system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.367490 # miss rate for ReadReq accesses 648system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.618890 # miss rate for ReadReq accesses 649system.l2c.ReadReq_miss_rate::cpu0.inst 0.059613 # miss rate for ReadReq accesses 650system.l2c.ReadReq_miss_rate::cpu0.data 0.183784 # miss rate for ReadReq accesses 651system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.222121 # miss rate for ReadReq accesses 652system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.407041 # miss rate for ReadReq accesses 653system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.592142 # miss rate for ReadReq accesses 654system.l2c.ReadReq_miss_rate::cpu1.inst 0.058028 # miss rate for ReadReq accesses 655system.l2c.ReadReq_miss_rate::cpu1.data 0.184340 # miss rate for ReadReq accesses 656system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.210530 # miss rate for ReadReq accesses 657system.l2c.ReadReq_miss_rate::total 0.201999 # miss rate for ReadReq accesses 658system.l2c.UpgradeReq_miss_rate::cpu0.data 0.604611 # miss rate for UpgradeReq accesses 659system.l2c.UpgradeReq_miss_rate::cpu1.data 0.558081 # miss rate for UpgradeReq accesses 660system.l2c.UpgradeReq_miss_rate::total 0.579630 # miss rate for UpgradeReq accesses 661system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.589898 # miss rate for SCUpgradeReq accesses 662system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.592581 # miss rate for SCUpgradeReq accesses 663system.l2c.SCUpgradeReq_miss_rate::total 0.591345 # miss rate for SCUpgradeReq accesses 664system.l2c.ReadExReq_miss_rate::cpu0.data 0.614254 # miss rate for ReadExReq accesses 665system.l2c.ReadExReq_miss_rate::cpu1.data 0.588064 # miss rate for ReadExReq accesses 666system.l2c.ReadExReq_miss_rate::total 0.601221 # miss rate for ReadExReq accesses 667system.l2c.demand_miss_rate::cpu0.dtb.walker 0.367490 # miss rate for demand accesses 668system.l2c.demand_miss_rate::cpu0.itb.walker 0.618890 # miss rate for demand accesses 669system.l2c.demand_miss_rate::cpu0.inst 0.059613 # miss rate for demand accesses 670system.l2c.demand_miss_rate::cpu0.data 0.249438 # miss rate for demand accesses 671system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.222121 # miss rate for demand accesses 672system.l2c.demand_miss_rate::cpu1.dtb.walker 0.407041 # miss rate for demand accesses 673system.l2c.demand_miss_rate::cpu1.itb.walker 0.592142 # miss rate for demand accesses 674system.l2c.demand_miss_rate::cpu1.inst 0.058028 # miss rate for demand accesses 675system.l2c.demand_miss_rate::cpu1.data 0.239028 # miss rate for demand accesses 676system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.210530 # miss rate for demand accesses 677system.l2c.demand_miss_rate::total 0.218477 # miss rate for demand accesses 678system.l2c.overall_miss_rate::cpu0.dtb.walker 0.367490 # miss rate for overall accesses 679system.l2c.overall_miss_rate::cpu0.itb.walker 0.618890 # miss rate for overall accesses 680system.l2c.overall_miss_rate::cpu0.inst 0.059613 # miss rate for overall accesses 681system.l2c.overall_miss_rate::cpu0.data 0.249438 # miss rate for overall accesses 682system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.222121 # miss rate for overall accesses 683system.l2c.overall_miss_rate::cpu1.dtb.walker 0.407041 # miss rate for overall accesses 684system.l2c.overall_miss_rate::cpu1.itb.walker 0.592142 # miss rate for overall accesses 685system.l2c.overall_miss_rate::cpu1.inst 0.058028 # miss rate for overall accesses 686system.l2c.overall_miss_rate::cpu1.data 0.239028 # miss rate for overall accesses 687system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.210530 # miss rate for overall accesses 688system.l2c.overall_miss_rate::total 0.218477 # miss rate for overall accesses 689system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 79900.157728 # average ReadReq miss latency 690system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 80102.000788 # average ReadReq miss latency 691system.l2c.ReadReq_avg_miss_latency::cpu0.inst 87835.995418 # average ReadReq miss latency 692system.l2c.ReadReq_avg_miss_latency::cpu0.data 81204.323557 # average ReadReq miss latency 693system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 105070.439397 # average ReadReq miss latency 694system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 78933.240193 # average ReadReq miss latency 695system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 78861.089259 # average ReadReq miss latency 696system.l2c.ReadReq_avg_miss_latency::cpu1.inst 89341.475430 # average ReadReq miss latency 697system.l2c.ReadReq_avg_miss_latency::cpu1.data 81296.964793 # average ReadReq miss latency 698system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 106061.228743 # average ReadReq miss latency 699system.l2c.ReadReq_avg_miss_latency::total 99163.590765 # average ReadReq miss latency 700system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 4021.342386 # average UpgradeReq miss latency 701system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4186.481164 # average UpgradeReq miss latency 702system.l2c.UpgradeReq_avg_miss_latency::total 4106.705295 # average UpgradeReq miss latency 703system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4689.272754 # average SCUpgradeReq miss latency 704system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4787.458863 # average SCUpgradeReq miss latency 705system.l2c.SCUpgradeReq_avg_miss_latency::total 4742.349977 # average SCUpgradeReq miss latency 706system.l2c.ReadExReq_avg_miss_latency::cpu0.data 73432.934513 # average ReadExReq miss latency 707system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73082.298275 # average ReadExReq miss latency 708system.l2c.ReadExReq_avg_miss_latency::total 73262.266686 # average ReadExReq miss latency 709system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 79900.157728 # average overall miss latency 710system.l2c.demand_avg_miss_latency::cpu0.itb.walker 80102.000788 # average overall miss latency 711system.l2c.demand_avg_miss_latency::cpu0.inst 87835.995418 # average overall miss latency 712system.l2c.demand_avg_miss_latency::cpu0.data 78285.525747 # average overall miss latency 713system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 105070.439397 # average overall miss latency 714system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 78933.240193 # average overall miss latency 715system.l2c.demand_avg_miss_latency::cpu1.itb.walker 78861.089259 # average overall miss latency 716system.l2c.demand_avg_miss_latency::cpu1.inst 89341.475430 # average overall miss latency 717system.l2c.demand_avg_miss_latency::cpu1.data 78559.341466 # average overall miss latency 718system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 106061.228743 # average overall miss latency 719system.l2c.demand_avg_miss_latency::total 96221.539502 # average overall miss latency 720system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 79900.157728 # average overall miss latency 721system.l2c.overall_avg_miss_latency::cpu0.itb.walker 80102.000788 # average overall miss latency 722system.l2c.overall_avg_miss_latency::cpu0.inst 87835.995418 # average overall miss latency 723system.l2c.overall_avg_miss_latency::cpu0.data 78285.525747 # average overall miss latency 724system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 105070.439397 # average overall miss latency 725system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 78933.240193 # average overall miss latency 726system.l2c.overall_avg_miss_latency::cpu1.itb.walker 78861.089259 # average overall miss latency 727system.l2c.overall_avg_miss_latency::cpu1.inst 89341.475430 # average overall miss latency 728system.l2c.overall_avg_miss_latency::cpu1.data 78559.341466 # average overall miss latency 729system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 106061.228743 # average overall miss latency 730system.l2c.overall_avg_miss_latency::total 96221.539502 # average overall miss latency 731system.l2c.blocked_cycles::no_mshrs 1844 # number of cycles access was blocked 732system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 733system.l2c.blocked::no_mshrs 53 # number of cycles access was blocked 734system.l2c.blocked::no_targets 0 # number of cycles access was blocked 735system.l2c.avg_blocked_cycles::no_mshrs 34.792453 # average number of cycles each access was blocked 736system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 737system.l2c.fast_writes 0 # number of fast writes performed 738system.l2c.cache_copies 0 # number of cache copies performed 739system.l2c.writebacks::writebacks 693385 # number of writebacks 740system.l2c.writebacks::total 693385 # number of writebacks 741system.l2c.ReadReq_mshr_hits::cpu0.inst 23 # number of ReadReq MSHR hits 742system.l2c.ReadReq_mshr_hits::cpu0.data 14 # number of ReadReq MSHR hits 743system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 264 # number of ReadReq MSHR hits 744system.l2c.ReadReq_mshr_hits::cpu1.inst 11 # number of ReadReq MSHR hits 745system.l2c.ReadReq_mshr_hits::cpu1.data 17 # number of ReadReq MSHR hits 746system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 129 # number of ReadReq MSHR hits 747system.l2c.ReadReq_mshr_hits::total 458 # number of ReadReq MSHR hits 748system.l2c.demand_mshr_hits::cpu0.inst 23 # number of demand (read+write) MSHR hits 749system.l2c.demand_mshr_hits::cpu0.data 14 # number of demand (read+write) MSHR hits 750system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 264 # number of demand (read+write) MSHR hits 751system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits 752system.l2c.demand_mshr_hits::cpu1.data 17 # number of demand (read+write) MSHR hits 753system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 129 # number of demand (read+write) MSHR hits 754system.l2c.demand_mshr_hits::total 458 # number of demand (read+write) MSHR hits 755system.l2c.overall_mshr_hits::cpu0.inst 23 # number of overall MSHR hits 756system.l2c.overall_mshr_hits::cpu0.data 14 # number of overall MSHR hits 757system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 264 # number of overall MSHR hits 758system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits 759system.l2c.overall_mshr_hits::cpu1.data 17 # number of overall MSHR hits 760system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 129 # number of overall MSHR hits 761system.l2c.overall_mshr_hits::total 458 # number of overall MSHR hits 762system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 3468 # number of ReadReq MSHR misses 763system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 6343 # number of ReadReq MSHR misses 764system.l2c.ReadReq_mshr_misses::cpu0.inst 8271 # number of ReadReq MSHR misses 765system.l2c.ReadReq_mshr_misses::cpu0.data 128217 # number of ReadReq MSHR misses 766system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 424948 # number of ReadReq MSHR misses 767system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4359 # number of ReadReq MSHR misses 768system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 6722 # number of ReadReq MSHR misses 769system.l2c.ReadReq_mshr_misses::cpu1.inst 8882 # number of ReadReq MSHR misses 770system.l2c.ReadReq_mshr_misses::cpu1.data 146319 # number of ReadReq MSHR misses 771system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 434726 # number of ReadReq MSHR misses 772system.l2c.ReadReq_mshr_misses::total 1172255 # number of ReadReq MSHR misses 773system.l2c.UpgradeReq_mshr_misses::cpu0.data 33912 # number of UpgradeReq MSHR misses 774system.l2c.UpgradeReq_mshr_misses::cpu1.data 36287 # number of UpgradeReq MSHR misses 775system.l2c.UpgradeReq_mshr_misses::total 70199 # number of UpgradeReq MSHR misses 776system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 10020 # number of SCUpgradeReq MSHR misses 777system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11790 # number of SCUpgradeReq MSHR misses 778system.l2c.SCUpgradeReq_mshr_misses::total 21810 # number of SCUpgradeReq MSHR misses 779system.l2c.ReadExReq_mshr_misses::cpu0.data 77130 # number of ReadExReq MSHR misses 780system.l2c.ReadExReq_mshr_misses::cpu1.data 73144 # number of ReadExReq MSHR misses 781system.l2c.ReadExReq_mshr_misses::total 150274 # number of ReadExReq MSHR misses 782system.l2c.demand_mshr_misses::cpu0.dtb.walker 3468 # number of demand (read+write) MSHR misses 783system.l2c.demand_mshr_misses::cpu0.itb.walker 6343 # number of demand (read+write) MSHR misses 784system.l2c.demand_mshr_misses::cpu0.inst 8271 # number of demand (read+write) MSHR misses 785system.l2c.demand_mshr_misses::cpu0.data 205347 # number of demand (read+write) MSHR misses 786system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 424948 # number of demand (read+write) MSHR misses 787system.l2c.demand_mshr_misses::cpu1.dtb.walker 4359 # number of demand (read+write) MSHR misses 788system.l2c.demand_mshr_misses::cpu1.itb.walker 6722 # number of demand (read+write) MSHR misses 789system.l2c.demand_mshr_misses::cpu1.inst 8882 # number of demand (read+write) MSHR misses 790system.l2c.demand_mshr_misses::cpu1.data 219463 # number of demand (read+write) MSHR misses 791system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 434726 # number of demand (read+write) MSHR misses 792system.l2c.demand_mshr_misses::total 1322529 # number of demand (read+write) MSHR misses 793system.l2c.overall_mshr_misses::cpu0.dtb.walker 3468 # number of overall MSHR misses 794system.l2c.overall_mshr_misses::cpu0.itb.walker 6343 # number of overall MSHR misses 795system.l2c.overall_mshr_misses::cpu0.inst 8271 # number of overall MSHR misses 796system.l2c.overall_mshr_misses::cpu0.data 205347 # number of overall MSHR misses 797system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 424948 # number of overall MSHR misses 798system.l2c.overall_mshr_misses::cpu1.dtb.walker 4359 # number of overall MSHR misses 799system.l2c.overall_mshr_misses::cpu1.itb.walker 6722 # number of overall MSHR misses 800system.l2c.overall_mshr_misses::cpu1.inst 8882 # number of overall MSHR misses 801system.l2c.overall_mshr_misses::cpu1.data 219463 # number of overall MSHR misses 802system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 434726 # number of overall MSHR misses 803system.l2c.overall_mshr_misses::total 1322529 # number of overall MSHR misses 804system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 234005247 # number of ReadReq MSHR miss cycles 805system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 429405991 # number of ReadReq MSHR miss cycles 806system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 623644746 # number of ReadReq MSHR miss cycles 807system.l2c.ReadReq_mshr_miss_latency::cpu0.data 8803657420 # number of ReadReq MSHR miss cycles 808system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 39426586681 # number of ReadReq MSHR miss cycles 809system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 289785494 # number of ReadReq MSHR miss cycles 810system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 446560742 # number of ReadReq MSHR miss cycles 811system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 682991749 # number of ReadReq MSHR miss cycles 812system.l2c.ReadReq_mshr_miss_latency::cpu1.data 10059247700 # number of ReadReq MSHR miss cycles 813system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 40752439135 # number of ReadReq MSHR miss cycles 814system.l2c.ReadReq_mshr_miss_latency::total 101748324905 # number of ReadReq MSHR miss cycles 815system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 17202577789 # number of WriteInvalidateReq MSHR miss cycles 816system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 14155732856 # number of WriteInvalidateReq MSHR miss cycles 817system.l2c.WriteInvalidateReq_mshr_miss_latency::total 31358310645 # number of WriteInvalidateReq MSHR miss cycles 818system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 344397419 # number of UpgradeReq MSHR miss cycles 819system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 367876069 # number of UpgradeReq MSHR miss cycles 820system.l2c.UpgradeReq_mshr_miss_latency::total 712273488 # number of UpgradeReq MSHR miss cycles 821system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 102095388 # number of SCUpgradeReq MSHR miss cycles 822system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 120655634 # number of SCUpgradeReq MSHR miss cycles 823system.l2c.SCUpgradeReq_mshr_miss_latency::total 222751022 # number of SCUpgradeReq MSHR miss cycles 824system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4691101701 # number of ReadExReq MSHR miss cycles 825system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4422988801 # number of ReadExReq MSHR miss cycles 826system.l2c.ReadExReq_mshr_miss_latency::total 9114090502 # number of ReadExReq MSHR miss cycles 827system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 234005247 # number of demand (read+write) MSHR miss cycles 828system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 429405991 # number of demand (read+write) MSHR miss cycles 829system.l2c.demand_mshr_miss_latency::cpu0.inst 623644746 # number of demand (read+write) MSHR miss cycles 830system.l2c.demand_mshr_miss_latency::cpu0.data 13494759121 # number of demand (read+write) MSHR miss cycles 831system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 39426586681 # number of demand (read+write) MSHR miss cycles 832system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 289785494 # number of demand (read+write) MSHR miss cycles 833system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 446560742 # number of demand (read+write) MSHR miss cycles 834system.l2c.demand_mshr_miss_latency::cpu1.inst 682991749 # number of demand (read+write) MSHR miss cycles 835system.l2c.demand_mshr_miss_latency::cpu1.data 14482236501 # number of demand (read+write) MSHR miss cycles 836system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 40752439135 # number of demand (read+write) MSHR miss cycles 837system.l2c.demand_mshr_miss_latency::total 110862415407 # number of demand (read+write) MSHR miss cycles 838system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 234005247 # number of overall MSHR miss cycles 839system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 429405991 # number of overall MSHR miss cycles 840system.l2c.overall_mshr_miss_latency::cpu0.inst 623644746 # number of overall MSHR miss cycles 841system.l2c.overall_mshr_miss_latency::cpu0.data 13494759121 # number of overall MSHR miss cycles 842system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 39426586681 # number of overall MSHR miss cycles 843system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 289785494 # number of overall MSHR miss cycles 844system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 446560742 # number of overall MSHR miss cycles 845system.l2c.overall_mshr_miss_latency::cpu1.inst 682991749 # number of overall MSHR miss cycles 846system.l2c.overall_mshr_miss_latency::cpu1.data 14482236501 # number of overall MSHR miss cycles 847system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 40752439135 # number of overall MSHR miss cycles 848system.l2c.overall_mshr_miss_latency::total 110862415407 # number of overall MSHR miss cycles 849system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2246197250 # number of ReadReq MSHR uncacheable cycles 850system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1998253750 # number of ReadReq MSHR uncacheable cycles 851system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5835000 # number of ReadReq MSHR uncacheable cycles 852system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3361097750 # number of ReadReq MSHR uncacheable cycles 853system.l2c.ReadReq_mshr_uncacheable_latency::total 7611383750 # number of ReadReq MSHR uncacheable cycles 854system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2007075001 # number of WriteReq MSHR uncacheable cycles 855system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 3246096000 # number of WriteReq MSHR uncacheable cycles 856system.l2c.WriteReq_mshr_uncacheable_latency::total 5253171001 # number of WriteReq MSHR uncacheable cycles 857system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2246197250 # number of overall MSHR uncacheable cycles 858system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4005328751 # number of overall MSHR uncacheable cycles 859system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5835000 # number of overall MSHR uncacheable cycles 860system.l2c.overall_mshr_uncacheable_latency::cpu1.data 6607193750 # number of overall MSHR uncacheable cycles 861system.l2c.overall_mshr_uncacheable_latency::total 12864554751 # number of overall MSHR uncacheable cycles 862system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.367490 # mshr miss rate for ReadReq accesses 863system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.618890 # mshr miss rate for ReadReq accesses 864system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.059448 # mshr miss rate for ReadReq accesses 865system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.183764 # mshr miss rate for ReadReq accesses 866system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.221983 # mshr miss rate for ReadReq accesses 867system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.407041 # mshr miss rate for ReadReq accesses 868system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.592142 # mshr miss rate for ReadReq accesses 869system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.057956 # mshr miss rate for ReadReq accesses 870system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.184318 # mshr miss rate for ReadReq accesses 871system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.210468 # mshr miss rate for ReadReq accesses 872system.l2c.ReadReq_mshr_miss_rate::total 0.201920 # mshr miss rate for ReadReq accesses 873system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.604611 # mshr miss rate for UpgradeReq accesses 874system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.558081 # mshr miss rate for UpgradeReq accesses 875system.l2c.UpgradeReq_mshr_miss_rate::total 0.579630 # mshr miss rate for UpgradeReq accesses 876system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.589898 # mshr miss rate for SCUpgradeReq accesses 877system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.592581 # mshr miss rate for SCUpgradeReq accesses 878system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.591345 # mshr miss rate for SCUpgradeReq accesses 879system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.614254 # mshr miss rate for ReadExReq accesses 880system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.588064 # mshr miss rate for ReadExReq accesses 881system.l2c.ReadExReq_mshr_miss_rate::total 0.601221 # mshr miss rate for ReadExReq accesses 882system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.367490 # mshr miss rate for demand accesses 883system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.618890 # mshr miss rate for demand accesses 884system.l2c.demand_mshr_miss_rate::cpu0.inst 0.059448 # mshr miss rate for demand accesses 885system.l2c.demand_mshr_miss_rate::cpu0.data 0.249421 # mshr miss rate for demand accesses 886system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.221983 # mshr miss rate for demand accesses 887system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.407041 # mshr miss rate for demand accesses 888system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.592142 # mshr miss rate for demand accesses 889system.l2c.demand_mshr_miss_rate::cpu1.inst 0.057956 # mshr miss rate for demand accesses 890system.l2c.demand_mshr_miss_rate::cpu1.data 0.239009 # mshr miss rate for demand accesses 891system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.210468 # mshr miss rate for demand accesses 892system.l2c.demand_mshr_miss_rate::total 0.218401 # mshr miss rate for demand accesses 893system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.367490 # mshr miss rate for overall accesses 894system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.618890 # mshr miss rate for overall accesses 895system.l2c.overall_mshr_miss_rate::cpu0.inst 0.059448 # mshr miss rate for overall accesses 896system.l2c.overall_mshr_miss_rate::cpu0.data 0.249421 # mshr miss rate for overall accesses 897system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.221983 # mshr miss rate for overall accesses 898system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.407041 # mshr miss rate for overall accesses 899system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.592142 # mshr miss rate for overall accesses 900system.l2c.overall_mshr_miss_rate::cpu1.inst 0.057956 # mshr miss rate for overall accesses 901system.l2c.overall_mshr_miss_rate::cpu1.data 0.239009 # mshr miss rate for overall accesses 902system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.210468 # mshr miss rate for overall accesses 903system.l2c.overall_mshr_miss_rate::total 0.218401 # mshr miss rate for overall accesses 904system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67475.561419 # average ReadReq mshr miss latency 905system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 67697.618004 # average ReadReq mshr miss latency 906system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 75401.371781 # average ReadReq mshr miss latency 907system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68662.169759 # average ReadReq mshr miss latency 908system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92779.791130 # average ReadReq mshr miss latency 909system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66479.810507 # average ReadReq mshr miss latency 910system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 66432.719726 # average ReadReq mshr miss latency 911system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 76896.166291 # average ReadReq mshr miss latency 912system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 68748.745549 # average ReadReq mshr miss latency 913system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 93742.815325 # average ReadReq mshr miss latency 914system.l2c.ReadReq_avg_mshr_miss_latency::total 86797.091849 # average ReadReq mshr miss latency 915system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency 916system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency 917system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 918system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10155.620990 # average UpgradeReq mshr miss latency 919system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10137.957643 # average UpgradeReq mshr miss latency 920system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10146.490520 # average UpgradeReq mshr miss latency 921system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10189.160479 # average SCUpgradeReq mshr miss latency 922system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10233.726378 # average SCUpgradeReq mshr miss latency 923system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10213.251811 # average SCUpgradeReq mshr miss latency 924system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 60820.714391 # average ReadExReq mshr miss latency 925system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60469.605176 # average ReadExReq mshr miss latency 926system.l2c.ReadExReq_avg_mshr_miss_latency::total 60649.816349 # average ReadExReq mshr miss latency 927system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67475.561419 # average overall mshr miss latency 928system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 67697.618004 # average overall mshr miss latency 929system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75401.371781 # average overall mshr miss latency 930system.l2c.demand_avg_mshr_miss_latency::cpu0.data 65716.855474 # average overall mshr miss latency 931system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92779.791130 # average overall mshr miss latency 932system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66479.810507 # average overall mshr miss latency 933system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 66432.719726 # average overall mshr miss latency 934system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76896.166291 # average overall mshr miss latency 935system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65989.421912 # average overall mshr miss latency 936system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 93742.815325 # average overall mshr miss latency 937system.l2c.demand_avg_mshr_miss_latency::total 83826.075199 # average overall mshr miss latency 938system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67475.561419 # average overall mshr miss latency 939system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 67697.618004 # average overall mshr miss latency 940system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75401.371781 # average overall mshr miss latency 941system.l2c.overall_avg_mshr_miss_latency::cpu0.data 65716.855474 # average overall mshr miss latency 942system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92779.791130 # average overall mshr miss latency 943system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66479.810507 # average overall mshr miss latency 944system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 66432.719726 # average overall mshr miss latency 945system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76896.166291 # average overall mshr miss latency 946system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65989.421912 # average overall mshr miss latency 947system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 93742.815325 # average overall mshr miss latency 948system.l2c.overall_avg_mshr_miss_latency::total 83826.075199 # average overall mshr miss latency 949system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 950system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 951system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 952system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 953system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 954system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 955system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 956system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 957system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 958system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 959system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 960system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 961system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 962system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 963system.realview.ethernet.txBytes 966 # Bytes Transmitted 964system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 965system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 966system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 967system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 968system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 969system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 970system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 971system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 972system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 973system.realview.ethernet.totPackets 3 # Total Packets 974system.realview.ethernet.totBytes 966 # Total Bytes 975system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 976system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 977system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 978system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 979system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 980system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 981system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 982system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 983system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 984system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 985system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 986system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 987system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 988system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 989system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 990system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 991system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 992system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 993system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 994system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 995system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 996system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 997system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 998system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 999system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1000system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 1001system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1002system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1003system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1004system.realview.ethernet.droppedPackets 0 # number of packets dropped 1005system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 1006system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 1007system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 1008system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 1009system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 1010system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 1011system.toL2Bus.trans_dist::ReadReq 6645186 # Transaction distribution 1012system.toL2Bus.trans_dist::ReadResp 6637629 # Transaction distribution 1013system.toL2Bus.trans_dist::WriteReq 38160 # Transaction distribution 1014system.toL2Bus.trans_dist::WriteResp 38160 # Transaction distribution 1015system.toL2Bus.trans_dist::Writeback 1982686 # Transaction distribution 1016system.toL2Bus.trans_dist::WriteInvalidateReq 1670210 # Transaction distribution 1017system.toL2Bus.trans_dist::WriteInvalidateResp 1563473 # Transaction distribution 1018system.toL2Bus.trans_dist::UpgradeReq 355152 # Transaction distribution 1019system.toL2Bus.trans_dist::SCUpgradeReq 313787 # Transaction distribution 1020system.toL2Bus.trans_dist::UpgradeResp 668939 # Transaction distribution 1021system.toL2Bus.trans_dist::SCUpgradeFailReq 102 # Transaction distribution 1022system.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution 1023system.toL2Bus.trans_dist::ReadExReq 297718 # Transaction distribution 1024system.toL2Bus.trans_dist::ReadExResp 297718 # Transaction distribution 1025system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9432330 # Packet count per connected master and slave (bytes) 1026system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 9652916 # Packet count per connected master and slave (bytes) 1027system.toL2Bus.pkt_count::total 19085246 # Packet count per connected master and slave (bytes) 1028system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 302653655 # Cumulative packet size per connected master and slave (bytes) 1029system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 312342176 # Cumulative packet size per connected master and slave (bytes) 1030system.toL2Bus.pkt_size::total 614995831 # Cumulative packet size per connected master and slave (bytes) 1031system.toL2Bus.snoops 1425200 # Total snoops (count) 1032system.toL2Bus.snoop_fanout::samples 11183456 # Request fanout histogram 1033system.toL2Bus.snoop_fanout::mean 1.010347 # Request fanout histogram 1034system.toL2Bus.snoop_fanout::stdev 0.101194 # Request fanout histogram 1035system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1036system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1037system.toL2Bus.snoop_fanout::1 11067738 98.97% 98.97% # Request fanout histogram 1038system.toL2Bus.snoop_fanout::2 115718 1.03% 100.00% # Request fanout histogram 1039system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1040system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1041system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1042system.toL2Bus.snoop_fanout::total 11183456 # Request fanout histogram 1043system.toL2Bus.reqLayer0.occupancy 19814172733 # Layer occupancy (ticks) 1044system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 1045system.toL2Bus.snoopLayer0.occupancy 6396000 # Layer occupancy (ticks) 1046system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1047system.toL2Bus.respLayer0.occupancy 15605521398 # Layer occupancy (ticks) 1048system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1049system.toL2Bus.respLayer1.occupancy 16621378743 # Layer occupancy (ticks) 1050system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1051system.iobus.trans_dist::ReadReq 40465 # Transaction distribution 1052system.iobus.trans_dist::ReadResp 40465 # Transaction distribution 1053system.iobus.trans_dist::WriteReq 136732 # Transaction distribution 1054system.iobus.trans_dist::WriteResp 136786 # Transaction distribution 1055system.iobus.trans_dist::WriteInvalidateReq 54 # Transaction distribution 1056system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48150 # Packet count per connected master and slave (bytes) 1057system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1058system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1059system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1060system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1061system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1062system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1063system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1064system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1065system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1066system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 1067system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 1068system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 1069system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1070system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 1071system.iobus.pkt_count_system.bridge.master::total 123084 # Packet count per connected master and slave (bytes) 1072system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231338 # Packet count per connected master and slave (bytes) 1073system.iobus.pkt_count_system.realview.ide.dma::total 231338 # Packet count per connected master and slave (bytes) 1074system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1075system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 1076system.iobus.pkt_count::total 354502 # Packet count per connected master and slave (bytes) 1077system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48170 # Cumulative packet size per connected master and slave (bytes) 1078system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1079system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1080system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1081system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1082system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1083system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1084system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1085system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1086system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1087system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 1088system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 1089system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 1090system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 1091system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1092system.iobus.pkt_size_system.bridge.master::total 156191 # Cumulative packet size per connected master and slave (bytes) 1093system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339368 # Cumulative packet size per connected master and slave (bytes) 1094system.iobus.pkt_size_system.realview.ide.dma::total 7339368 # Cumulative packet size per connected master and slave (bytes) 1095system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1096system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 1097system.iobus.pkt_size::total 7497645 # Cumulative packet size per connected master and slave (bytes) 1098system.iobus.reqLayer0.occupancy 36603000 # Layer occupancy (ticks) 1099system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1100system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 1101system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1102system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 1103system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1104system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 1105system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1106system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 1107system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1108system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 1109system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1110system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 1111system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1112system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 1113system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1114system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 1115system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1116system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 1117system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1118system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks) 1119system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1120system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 1121system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1122system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 1123system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1124system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 1125system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1126system.iobus.reqLayer27.occupancy 981958721 # Layer occupancy (ticks) 1127system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1128system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1129system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1130system.iobus.respLayer0.occupancy 93029000 # Layer occupancy (ticks) 1131system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1132system.iobus.respLayer3.occupancy 179341978 # Layer occupancy (ticks) 1133system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1134system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) 1135system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 1136system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1137system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1138system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1139system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1140system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1141system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1142system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1143system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1144system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1145system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1146system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1147system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1148system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1149system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1150system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1151system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1152system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1153system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1154system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1155system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1156system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1157system.cpu0.dtb.inst_hits 0 # ITB inst hits 1158system.cpu0.dtb.inst_misses 0 # ITB inst misses 1159system.cpu0.dtb.read_hits 81279666 # DTB read hits 1160system.cpu0.dtb.read_misses 78948 # DTB read misses 1161system.cpu0.dtb.write_hits 73742535 # DTB write hits 1162system.cpu0.dtb.write_misses 27290 # DTB write misses 1163system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1164system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1165system.cpu0.dtb.flush_tlb_mva_asid 41415 # Number of times TLB was flushed by MVA & ASID 1166system.cpu0.dtb.flush_tlb_asid 1036 # Number of times TLB was flushed by ASID 1167system.cpu0.dtb.flush_entries 31886 # Number of entries that have been flushed from TLB 1168system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 1169system.cpu0.dtb.prefetch_faults 3595 # Number of TLB faults due to prefetch 1170system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1171system.cpu0.dtb.perms_faults 8523 # Number of TLB faults due to permissions restrictions 1172system.cpu0.dtb.read_accesses 81358614 # DTB read accesses 1173system.cpu0.dtb.write_accesses 73769825 # DTB write accesses 1174system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 1175system.cpu0.dtb.hits 155022201 # DTB hits 1176system.cpu0.dtb.misses 106238 # DTB misses 1177system.cpu0.dtb.accesses 155128439 # DTB accesses 1178system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1179system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1180system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1181system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1182system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1183system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1184system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1185system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1186system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1187system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1188system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1189system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1190system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1191system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1192system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1193system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1194system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1195system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1196system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1197system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1198system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1199system.cpu0.itb.inst_hits 432012599 # ITB inst hits 1200system.cpu0.itb.inst_misses 54786 # ITB inst misses 1201system.cpu0.itb.read_hits 0 # DTB read hits 1202system.cpu0.itb.read_misses 0 # DTB read misses 1203system.cpu0.itb.write_hits 0 # DTB write hits 1204system.cpu0.itb.write_misses 0 # DTB write misses 1205system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 1206system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1207system.cpu0.itb.flush_tlb_mva_asid 41415 # Number of times TLB was flushed by MVA & ASID 1208system.cpu0.itb.flush_tlb_asid 1036 # Number of times TLB was flushed by ASID 1209system.cpu0.itb.flush_entries 22623 # Number of entries that have been flushed from TLB 1210system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1211system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1212system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1213system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1214system.cpu0.itb.read_accesses 0 # DTB read accesses 1215system.cpu0.itb.write_accesses 0 # DTB write accesses 1216system.cpu0.itb.inst_accesses 432067385 # ITB inst accesses 1217system.cpu0.itb.hits 432012599 # DTB hits 1218system.cpu0.itb.misses 54786 # DTB misses 1219system.cpu0.itb.accesses 432067385 # DTB accesses 1220system.cpu0.numCycles 94876549324 # number of cpu cycles simulated 1221system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1222system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 1223system.cpu0.committedInsts 431769250 # Number of instructions committed 1224system.cpu0.committedOps 507110651 # Number of ops (including micro ops) committed 1225system.cpu0.num_int_alu_accesses 465722099 # Number of integer alu accesses 1226system.cpu0.num_fp_alu_accesses 423380 # Number of float alu accesses 1227system.cpu0.num_func_calls 25579239 # number of times a function call or return occured 1228system.cpu0.num_conditional_control_insts 65525116 # number of instructions that are conditional controls 1229system.cpu0.num_int_insts 465722099 # number of integer instructions 1230system.cpu0.num_fp_insts 423380 # number of float instructions 1231system.cpu0.num_int_register_reads 674979358 # number of times the integer registers were read 1232system.cpu0.num_int_register_writes 369311745 # number of times the integer registers were written 1233system.cpu0.num_fp_register_reads 705560 # number of times the floating registers were read 1234system.cpu0.num_fp_register_writes 308536 # number of times the floating registers were written 1235system.cpu0.num_cc_register_reads 112703400 # number of times the CC registers were read 1236system.cpu0.num_cc_register_writes 112387692 # number of times the CC registers were written 1237system.cpu0.num_mem_refs 155012297 # number of memory refs 1238system.cpu0.num_load_insts 81273219 # Number of load instructions 1239system.cpu0.num_store_insts 73739078 # Number of store instructions 1240system.cpu0.num_idle_cycles 93821929037.552032 # Number of idle cycles 1241system.cpu0.num_busy_cycles 1054620286.447978 # Number of busy cycles 1242system.cpu0.not_idle_fraction 0.011116 # Percentage of non-idle cycles 1243system.cpu0.idle_fraction 0.988884 # Percentage of idle cycles 1244system.cpu0.Branches 96363585 # Number of branches fetched 1245system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 1246system.cpu0.op_class::IntAlu 351187949 69.21% 69.21% # Class of executed instruction 1247system.cpu0.op_class::IntMult 1094457 0.22% 69.43% # Class of executed instruction 1248system.cpu0.op_class::IntDiv 58568 0.01% 69.44% # Class of executed instruction 1249system.cpu0.op_class::FloatAdd 0 0.00% 69.44% # Class of executed instruction 1250system.cpu0.op_class::FloatCmp 0 0.00% 69.44% # Class of executed instruction 1251system.cpu0.op_class::FloatCvt 0 0.00% 69.44% # Class of executed instruction 1252system.cpu0.op_class::FloatMult 0 0.00% 69.44% # Class of executed instruction 1253system.cpu0.op_class::FloatDiv 0 0.00% 69.44% # Class of executed instruction 1254system.cpu0.op_class::FloatSqrt 0 0.00% 69.44% # Class of executed instruction 1255system.cpu0.op_class::SimdAdd 0 0.00% 69.44% # Class of executed instruction 1256system.cpu0.op_class::SimdAddAcc 0 0.00% 69.44% # Class of executed instruction 1257system.cpu0.op_class::SimdAlu 0 0.00% 69.44% # Class of executed instruction 1258system.cpu0.op_class::SimdCmp 0 0.00% 69.44% # Class of executed instruction 1259system.cpu0.op_class::SimdCvt 0 0.00% 69.44% # Class of executed instruction 1260system.cpu0.op_class::SimdMisc 0 0.00% 69.44% # Class of executed instruction 1261system.cpu0.op_class::SimdMult 0 0.00% 69.44% # Class of executed instruction 1262system.cpu0.op_class::SimdMultAcc 0 0.00% 69.44% # Class of executed instruction 1263system.cpu0.op_class::SimdShift 0 0.00% 69.44% # Class of executed instruction 1264system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.44% # Class of executed instruction 1265system.cpu0.op_class::SimdSqrt 0 0.00% 69.44% # Class of executed instruction 1266system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.44% # Class of executed instruction 1267system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.44% # Class of executed instruction 1268system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.44% # Class of executed instruction 1269system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.44% # Class of executed instruction 1270system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.44% # Class of executed instruction 1271system.cpu0.op_class::SimdFloatMisc 43852 0.01% 69.45% # Class of executed instruction 1272system.cpu0.op_class::SimdFloatMult 0 0.00% 69.45% # Class of executed instruction 1273system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.45% # Class of executed instruction 1274system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.45% # Class of executed instruction 1275system.cpu0.op_class::MemRead 81273219 16.02% 85.47% # Class of executed instruction 1276system.cpu0.op_class::MemWrite 73739078 14.53% 100.00% # Class of executed instruction 1277system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1278system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 1279system.cpu0.op_class::total 507397124 # Class of executed instruction 1280system.cpu0.kern.inst.arm 0 # number of arm instructions executed 1281system.cpu0.kern.inst.quiesce 5117 # number of quiesce instructions executed 1282system.cpu0.icache.tags.replacements 4835795 # number of replacements 1283system.cpu0.icache.tags.tagsinuse 511.921057 # Cycle average of tags in use 1284system.cpu0.icache.tags.total_refs 427176292 # Total number of references to valid blocks. 1285system.cpu0.icache.tags.sampled_refs 4836307 # Sample count of references to valid blocks. 1286system.cpu0.icache.tags.avg_refs 88.326959 # Average number of references to valid blocks. 1287system.cpu0.icache.tags.warmup_cycle 24248022750 # Cycle when the warmup percentage was hit. 1288system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.921057 # Average occupied blocks per requestor 1289system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999846 # Average percentage of cache occupancy 1290system.cpu0.icache.tags.occ_percent::total 0.999846 # Average percentage of cache occupancy 1291system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1292system.cpu0.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id 1293system.cpu0.icache.tags.age_task_id_blocks_1024::1 288 # Occupied blocks per task id 1294system.cpu0.icache.tags.age_task_id_blocks_1024::2 164 # Occupied blocks per task id 1295system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1296system.cpu0.icache.tags.tag_accesses 868861505 # Number of tag accesses 1297system.cpu0.icache.tags.data_accesses 868861505 # Number of data accesses 1298system.cpu0.icache.ReadReq_hits::cpu0.inst 427176292 # number of ReadReq hits 1299system.cpu0.icache.ReadReq_hits::total 427176292 # number of ReadReq hits 1300system.cpu0.icache.demand_hits::cpu0.inst 427176292 # number of demand (read+write) hits 1301system.cpu0.icache.demand_hits::total 427176292 # number of demand (read+write) hits 1302system.cpu0.icache.overall_hits::cpu0.inst 427176292 # number of overall hits 1303system.cpu0.icache.overall_hits::total 427176292 # number of overall hits 1304system.cpu0.icache.ReadReq_misses::cpu0.inst 4836307 # number of ReadReq misses 1305system.cpu0.icache.ReadReq_misses::total 4836307 # number of ReadReq misses 1306system.cpu0.icache.demand_misses::cpu0.inst 4836307 # number of demand (read+write) misses 1307system.cpu0.icache.demand_misses::total 4836307 # number of demand (read+write) misses 1308system.cpu0.icache.overall_misses::cpu0.inst 4836307 # number of overall misses 1309system.cpu0.icache.overall_misses::total 4836307 # number of overall misses 1310system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 42021880066 # number of ReadReq miss cycles 1311system.cpu0.icache.ReadReq_miss_latency::total 42021880066 # number of ReadReq miss cycles 1312system.cpu0.icache.demand_miss_latency::cpu0.inst 42021880066 # number of demand (read+write) miss cycles 1313system.cpu0.icache.demand_miss_latency::total 42021880066 # number of demand (read+write) miss cycles 1314system.cpu0.icache.overall_miss_latency::cpu0.inst 42021880066 # number of overall miss cycles 1315system.cpu0.icache.overall_miss_latency::total 42021880066 # number of overall miss cycles 1316system.cpu0.icache.ReadReq_accesses::cpu0.inst 432012599 # number of ReadReq accesses(hits+misses) 1317system.cpu0.icache.ReadReq_accesses::total 432012599 # number of ReadReq accesses(hits+misses) 1318system.cpu0.icache.demand_accesses::cpu0.inst 432012599 # number of demand (read+write) accesses 1319system.cpu0.icache.demand_accesses::total 432012599 # number of demand (read+write) accesses 1320system.cpu0.icache.overall_accesses::cpu0.inst 432012599 # number of overall (read+write) accesses 1321system.cpu0.icache.overall_accesses::total 432012599 # number of overall (read+write) accesses 1322system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011195 # miss rate for ReadReq accesses 1323system.cpu0.icache.ReadReq_miss_rate::total 0.011195 # miss rate for ReadReq accesses 1324system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011195 # miss rate for demand accesses 1325system.cpu0.icache.demand_miss_rate::total 0.011195 # miss rate for demand accesses 1326system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011195 # miss rate for overall accesses 1327system.cpu0.icache.overall_miss_rate::total 0.011195 # miss rate for overall accesses 1328system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8688.836351 # average ReadReq miss latency 1329system.cpu0.icache.ReadReq_avg_miss_latency::total 8688.836351 # average ReadReq miss latency 1330system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8688.836351 # average overall miss latency 1331system.cpu0.icache.demand_avg_miss_latency::total 8688.836351 # average overall miss latency 1332system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8688.836351 # average overall miss latency 1333system.cpu0.icache.overall_avg_miss_latency::total 8688.836351 # average overall miss latency 1334system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1335system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1336system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1337system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1338system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1339system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1340system.cpu0.icache.fast_writes 0 # number of fast writes performed 1341system.cpu0.icache.cache_copies 0 # number of cache copies performed 1342system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4836307 # number of ReadReq MSHR misses 1343system.cpu0.icache.ReadReq_mshr_misses::total 4836307 # number of ReadReq MSHR misses 1344system.cpu0.icache.demand_mshr_misses::cpu0.inst 4836307 # number of demand (read+write) MSHR misses 1345system.cpu0.icache.demand_mshr_misses::total 4836307 # number of demand (read+write) MSHR misses 1346system.cpu0.icache.overall_mshr_misses::cpu0.inst 4836307 # number of overall MSHR misses 1347system.cpu0.icache.overall_mshr_misses::total 4836307 # number of overall MSHR misses 1348system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 34764760966 # number of ReadReq MSHR miss cycles 1349system.cpu0.icache.ReadReq_mshr_miss_latency::total 34764760966 # number of ReadReq MSHR miss cycles 1350system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 34764760966 # number of demand (read+write) MSHR miss cycles 1351system.cpu0.icache.demand_mshr_miss_latency::total 34764760966 # number of demand (read+write) MSHR miss cycles 1352system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 34764760966 # number of overall MSHR miss cycles 1353system.cpu0.icache.overall_mshr_miss_latency::total 34764760966 # number of overall MSHR miss cycles 1354system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3405609750 # number of ReadReq MSHR uncacheable cycles 1355system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3405609750 # number of ReadReq MSHR uncacheable cycles 1356system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3405609750 # number of overall MSHR uncacheable cycles 1357system.cpu0.icache.overall_mshr_uncacheable_latency::total 3405609750 # number of overall MSHR uncacheable cycles 1358system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011195 # mshr miss rate for ReadReq accesses 1359system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011195 # mshr miss rate for ReadReq accesses 1360system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011195 # mshr miss rate for demand accesses 1361system.cpu0.icache.demand_mshr_miss_rate::total 0.011195 # mshr miss rate for demand accesses 1362system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011195 # mshr miss rate for overall accesses 1363system.cpu0.icache.overall_mshr_miss_rate::total 0.011195 # mshr miss rate for overall accesses 1364system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7188.286634 # average ReadReq mshr miss latency 1365system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7188.286634 # average ReadReq mshr miss latency 1366system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7188.286634 # average overall mshr miss latency 1367system.cpu0.icache.demand_avg_mshr_miss_latency::total 7188.286634 # average overall mshr miss latency 1368system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7188.286634 # average overall mshr miss latency 1369system.cpu0.icache.overall_avg_mshr_miss_latency::total 7188.286634 # average overall mshr miss latency 1370system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1371system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1372system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1373system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1374system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1375system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 44883381 # number of hwpf identified 1376system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 769766 # number of hwpf that were already in mshr 1377system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 41733922 # number of hwpf that were already in the cache 1378system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 7731 # number of hwpf that were already in the prefetch queue 1379system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 1380system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 460 # number of hwpf removed because MSHR allocated 1381system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 2371502 # number of hwpf issued 1382system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 3699891 # number of hwpf spanning a virtual page 1383system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 1384system.cpu0.l2cache.tags.replacements 2933552 # number of replacements 1385system.cpu0.l2cache.tags.tagsinuse 16178.968525 # Cycle average of tags in use 1386system.cpu0.l2cache.tags.total_refs 10401290 # Total number of references to valid blocks. 1387system.cpu0.l2cache.tags.sampled_refs 2949711 # Sample count of references to valid blocks. 1388system.cpu0.l2cache.tags.avg_refs 3.526206 # Average number of references to valid blocks. 1389system.cpu0.l2cache.tags.warmup_cycle 20647851500 # Cycle when the warmup percentage was hit. 1390system.cpu0.l2cache.tags.occ_blocks::writebacks 3715.452521 # Average occupied blocks per requestor 1391system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 41.338628 # Average occupied blocks per requestor 1392system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 40.195819 # Average occupied blocks per requestor 1393system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 822.456727 # Average occupied blocks per requestor 1394system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3056.932991 # Average occupied blocks per requestor 1395system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 8502.591837 # Average occupied blocks per requestor 1396system.cpu0.l2cache.tags.occ_percent::writebacks 0.226773 # Average percentage of cache occupancy 1397system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002523 # Average percentage of cache occupancy 1398system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.002453 # Average percentage of cache occupancy 1399system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.050199 # Average percentage of cache occupancy 1400system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.186580 # Average percentage of cache occupancy 1401system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.518957 # Average percentage of cache occupancy 1402system.cpu0.l2cache.tags.occ_percent::total 0.987486 # Average percentage of cache occupancy 1403system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8877 # Occupied blocks per task id 1404system.cpu0.l2cache.tags.occ_task_id_blocks::1023 49 # Occupied blocks per task id 1405system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7233 # Occupied blocks per task id 1406system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 49 # Occupied blocks per task id 1407system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 502 # Occupied blocks per task id 1408system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 2719 # Occupied blocks per task id 1409system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 3687 # Occupied blocks per task id 1410system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1920 # Occupied blocks per task id 1411system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 8 # Occupied blocks per task id 1412system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 22 # Occupied blocks per task id 1413system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id 1414system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id 1415system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 1416system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 393 # Occupied blocks per task id 1417system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2913 # Occupied blocks per task id 1418system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2975 # Occupied blocks per task id 1419system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 925 # Occupied blocks per task id 1420system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.541809 # Percentage of cache occupancy per task id 1421system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.002991 # Percentage of cache occupancy per task id 1422system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.441467 # Percentage of cache occupancy per task id 1423system.cpu0.l2cache.tags.tag_accesses 228304892 # Number of tag accesses 1424system.cpu0.l2cache.tags.data_accesses 228304892 # Number of data accesses 1425system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 221810 # number of ReadReq hits 1426system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 122090 # number of ReadReq hits 1427system.cpu0.l2cache.ReadReq_hits::cpu0.inst 4672690 # number of ReadReq hits 1428system.cpu0.l2cache.ReadReq_hits::cpu0.data 2607787 # number of ReadReq hits 1429system.cpu0.l2cache.ReadReq_hits::total 7624377 # number of ReadReq hits 1430system.cpu0.l2cache.Writeback_hits::writebacks 2894821 # number of Writeback hits 1431system.cpu0.l2cache.Writeback_hits::total 2894821 # number of Writeback hits 1432system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 81724 # number of UpgradeReq hits 1433system.cpu0.l2cache.UpgradeReq_hits::total 81724 # number of UpgradeReq hits 1434system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 31053 # number of SCUpgradeReq hits 1435system.cpu0.l2cache.SCUpgradeReq_hits::total 31053 # number of SCUpgradeReq hits 1436system.cpu0.l2cache.ReadExReq_hits::cpu0.data 866415 # number of ReadExReq hits 1437system.cpu0.l2cache.ReadExReq_hits::total 866415 # number of ReadExReq hits 1438system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 221810 # number of demand (read+write) hits 1439system.cpu0.l2cache.demand_hits::cpu0.itb.walker 122090 # number of demand (read+write) hits 1440system.cpu0.l2cache.demand_hits::cpu0.inst 4672690 # number of demand (read+write) hits 1441system.cpu0.l2cache.demand_hits::cpu0.data 3474202 # number of demand (read+write) hits 1442system.cpu0.l2cache.demand_hits::total 8490792 # number of demand (read+write) hits 1443system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 221810 # number of overall hits 1444system.cpu0.l2cache.overall_hits::cpu0.itb.walker 122090 # number of overall hits 1445system.cpu0.l2cache.overall_hits::cpu0.inst 4672690 # number of overall hits 1446system.cpu0.l2cache.overall_hits::cpu0.data 3474202 # number of overall hits 1447system.cpu0.l2cache.overall_hits::total 8490792 # number of overall hits 1448system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12355 # number of ReadReq misses 1449system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10686 # number of ReadReq misses 1450system.cpu0.l2cache.ReadReq_misses::cpu0.inst 163617 # number of ReadReq misses 1451system.cpu0.l2cache.ReadReq_misses::cpu0.data 944935 # number of ReadReq misses 1452system.cpu0.l2cache.ReadReq_misses::total 1131593 # number of ReadReq misses 1453system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 105877 # number of UpgradeReq misses 1454system.cpu0.l2cache.UpgradeReq_misses::total 105877 # number of UpgradeReq misses 1455system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 154791 # number of SCUpgradeReq misses 1456system.cpu0.l2cache.SCUpgradeReq_misses::total 154791 # number of SCUpgradeReq misses 1457system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 6 # number of SCUpgradeFailReq misses 1458system.cpu0.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses 1459system.cpu0.l2cache.ReadExReq_misses::cpu0.data 220288 # number of ReadExReq misses 1460system.cpu0.l2cache.ReadExReq_misses::total 220288 # number of ReadExReq misses 1461system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12355 # number of demand (read+write) misses 1462system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10686 # number of demand (read+write) misses 1463system.cpu0.l2cache.demand_misses::cpu0.inst 163617 # number of demand (read+write) misses 1464system.cpu0.l2cache.demand_misses::cpu0.data 1165223 # number of demand (read+write) misses 1465system.cpu0.l2cache.demand_misses::total 1351881 # number of demand (read+write) misses 1466system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12355 # number of overall misses 1467system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10686 # number of overall misses 1468system.cpu0.l2cache.overall_misses::cpu0.inst 163617 # number of overall misses 1469system.cpu0.l2cache.overall_misses::cpu0.data 1165223 # number of overall misses 1470system.cpu0.l2cache.overall_misses::total 1351881 # number of overall misses 1471system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 518388959 # number of ReadReq miss cycles 1472system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 691109452 # number of ReadReq miss cycles 1473system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 4288633088 # number of ReadReq miss cycles 1474system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 30316279776 # number of ReadReq miss cycles 1475system.cpu0.l2cache.ReadReq_miss_latency::total 35814411275 # number of ReadReq miss cycles 1476system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2067273148 # number of UpgradeReq miss cycles 1477system.cpu0.l2cache.UpgradeReq_miss_latency::total 2067273148 # number of UpgradeReq miss cycles 1478system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3132681305 # number of SCUpgradeReq miss cycles 1479system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3132681305 # number of SCUpgradeReq miss cycles 1480system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1841998 # number of SCUpgradeFailReq miss cycles 1481system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1841998 # number of SCUpgradeFailReq miss cycles 1482system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 10252738120 # number of ReadExReq miss cycles 1483system.cpu0.l2cache.ReadExReq_miss_latency::total 10252738120 # number of ReadExReq miss cycles 1484system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 518388959 # number of demand (read+write) miss cycles 1485system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 691109452 # number of demand (read+write) miss cycles 1486system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4288633088 # number of demand (read+write) miss cycles 1487system.cpu0.l2cache.demand_miss_latency::cpu0.data 40569017896 # number of demand (read+write) miss cycles 1488system.cpu0.l2cache.demand_miss_latency::total 46067149395 # number of demand (read+write) miss cycles 1489system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 518388959 # number of overall miss cycles 1490system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 691109452 # number of overall miss cycles 1491system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4288633088 # number of overall miss cycles 1492system.cpu0.l2cache.overall_miss_latency::cpu0.data 40569017896 # number of overall miss cycles 1493system.cpu0.l2cache.overall_miss_latency::total 46067149395 # number of overall miss cycles 1494system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 234165 # number of ReadReq accesses(hits+misses) 1495system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 132776 # number of ReadReq accesses(hits+misses) 1496system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 4836307 # number of ReadReq accesses(hits+misses) 1497system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3552722 # number of ReadReq accesses(hits+misses) 1498system.cpu0.l2cache.ReadReq_accesses::total 8755970 # number of ReadReq accesses(hits+misses) 1499system.cpu0.l2cache.Writeback_accesses::writebacks 2894821 # number of Writeback accesses(hits+misses) 1500system.cpu0.l2cache.Writeback_accesses::total 2894821 # number of Writeback accesses(hits+misses) 1501system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 187601 # number of UpgradeReq accesses(hits+misses) 1502system.cpu0.l2cache.UpgradeReq_accesses::total 187601 # number of UpgradeReq accesses(hits+misses) 1503system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 185844 # number of SCUpgradeReq accesses(hits+misses) 1504system.cpu0.l2cache.SCUpgradeReq_accesses::total 185844 # number of SCUpgradeReq accesses(hits+misses) 1505system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 6 # number of SCUpgradeFailReq accesses(hits+misses) 1506system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) 1507system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1086703 # number of ReadExReq accesses(hits+misses) 1508system.cpu0.l2cache.ReadExReq_accesses::total 1086703 # number of ReadExReq accesses(hits+misses) 1509system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 234165 # number of demand (read+write) accesses 1510system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 132776 # number of demand (read+write) accesses 1511system.cpu0.l2cache.demand_accesses::cpu0.inst 4836307 # number of demand (read+write) accesses 1512system.cpu0.l2cache.demand_accesses::cpu0.data 4639425 # number of demand (read+write) accesses 1513system.cpu0.l2cache.demand_accesses::total 9842673 # number of demand (read+write) accesses 1514system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 234165 # number of overall (read+write) accesses 1515system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 132776 # number of overall (read+write) accesses 1516system.cpu0.l2cache.overall_accesses::cpu0.inst 4836307 # number of overall (read+write) accesses 1517system.cpu0.l2cache.overall_accesses::cpu0.data 4639425 # number of overall (read+write) accesses 1518system.cpu0.l2cache.overall_accesses::total 9842673 # number of overall (read+write) accesses 1519system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.052762 # miss rate for ReadReq accesses 1520system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.080481 # miss rate for ReadReq accesses 1521system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.033831 # miss rate for ReadReq accesses 1522system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.265975 # miss rate for ReadReq accesses 1523system.cpu0.l2cache.ReadReq_miss_rate::total 0.129237 # miss rate for ReadReq accesses 1524system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.564373 # miss rate for UpgradeReq accesses 1525system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.564373 # miss rate for UpgradeReq accesses 1526system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.832908 # miss rate for SCUpgradeReq accesses 1527system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.832908 # miss rate for SCUpgradeReq accesses 1528system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1529system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1530system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.202712 # miss rate for ReadExReq accesses 1531system.cpu0.l2cache.ReadExReq_miss_rate::total 0.202712 # miss rate for ReadExReq accesses 1532system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.052762 # miss rate for demand accesses 1533system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.080481 # miss rate for demand accesses 1534system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.033831 # miss rate for demand accesses 1535system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.251157 # miss rate for demand accesses 1536system.cpu0.l2cache.demand_miss_rate::total 0.137349 # miss rate for demand accesses 1537system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.052762 # miss rate for overall accesses 1538system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.080481 # miss rate for overall accesses 1539system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.033831 # miss rate for overall accesses 1540system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.251157 # miss rate for overall accesses 1541system.cpu0.l2cache.overall_miss_rate::total 0.137349 # miss rate for overall accesses 1542system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 41957.827519 # average ReadReq miss latency 1543system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 64674.288976 # average ReadReq miss latency 1544system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 26211.415000 # average ReadReq miss latency 1545system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 32082.926102 # average ReadReq miss latency 1546system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31649.551804 # average ReadReq miss latency 1547system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 19525.233507 # average UpgradeReq miss latency 1548system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 19525.233507 # average UpgradeReq miss latency 1549system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20238.135970 # average SCUpgradeReq miss latency 1550system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20238.135970 # average SCUpgradeReq miss latency 1551system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 306999.666667 # average SCUpgradeFailReq miss latency 1552system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 306999.666667 # average SCUpgradeFailReq miss latency 1553system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 46542.426823 # average ReadExReq miss latency 1554system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 46542.426823 # average ReadExReq miss latency 1555system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 41957.827519 # average overall miss latency 1556system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 64674.288976 # average overall miss latency 1557system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 26211.415000 # average overall miss latency 1558system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 34816.526876 # average overall miss latency 1559system.cpu0.l2cache.demand_avg_miss_latency::total 34076.334674 # average overall miss latency 1560system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 41957.827519 # average overall miss latency 1561system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 64674.288976 # average overall miss latency 1562system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 26211.415000 # average overall miss latency 1563system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 34816.526876 # average overall miss latency 1564system.cpu0.l2cache.overall_avg_miss_latency::total 34076.334674 # average overall miss latency 1565system.cpu0.l2cache.blocked_cycles::no_mshrs 9451 # number of cycles access was blocked 1566system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1567system.cpu0.l2cache.blocked::no_mshrs 232 # number of cycles access was blocked 1568system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1569system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 40.737069 # average number of cycles each access was blocked 1570system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1571system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1572system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1573system.cpu0.l2cache.writebacks::writebacks 969387 # number of writebacks 1574system.cpu0.l2cache.writebacks::total 969387 # number of writebacks 1575system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 24596 # number of ReadReq MSHR hits 1576system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 5208 # number of ReadReq MSHR hits 1577system.cpu0.l2cache.ReadReq_mshr_hits::total 29804 # number of ReadReq MSHR hits 1578system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5052 # number of ReadExReq MSHR hits 1579system.cpu0.l2cache.ReadExReq_mshr_hits::total 5052 # number of ReadExReq MSHR hits 1580system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 24596 # number of demand (read+write) MSHR hits 1581system.cpu0.l2cache.demand_mshr_hits::cpu0.data 10260 # number of demand (read+write) MSHR hits 1582system.cpu0.l2cache.demand_mshr_hits::total 34856 # number of demand (read+write) MSHR hits 1583system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 24596 # number of overall MSHR hits 1584system.cpu0.l2cache.overall_mshr_hits::cpu0.data 10260 # number of overall MSHR hits 1585system.cpu0.l2cache.overall_mshr_hits::total 34856 # number of overall MSHR hits 1586system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 12355 # number of ReadReq MSHR misses 1587system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 10686 # number of ReadReq MSHR misses 1588system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 139021 # number of ReadReq MSHR misses 1589system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 939727 # number of ReadReq MSHR misses 1590system.cpu0.l2cache.ReadReq_mshr_misses::total 1101789 # number of ReadReq MSHR misses 1591system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 2371413 # number of HardPFReq MSHR misses 1592system.cpu0.l2cache.HardPFReq_mshr_misses::total 2371413 # number of HardPFReq MSHR misses 1593system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 105877 # number of UpgradeReq MSHR misses 1594system.cpu0.l2cache.UpgradeReq_mshr_misses::total 105877 # number of UpgradeReq MSHR misses 1595system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 154791 # number of SCUpgradeReq MSHR misses 1596system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 154791 # number of SCUpgradeReq MSHR misses 1597system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 6 # number of SCUpgradeFailReq MSHR misses 1598system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses 1599system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 215236 # number of ReadExReq MSHR misses 1600system.cpu0.l2cache.ReadExReq_mshr_misses::total 215236 # number of ReadExReq MSHR misses 1601system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 12355 # number of demand (read+write) MSHR misses 1602system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 10686 # number of demand (read+write) MSHR misses 1603system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 139021 # number of demand (read+write) MSHR misses 1604system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1154963 # number of demand (read+write) MSHR misses 1605system.cpu0.l2cache.demand_mshr_misses::total 1317025 # number of demand (read+write) MSHR misses 1606system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 12355 # number of overall MSHR misses 1607system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 10686 # number of overall MSHR misses 1608system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 139021 # number of overall MSHR misses 1609system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1154963 # number of overall MSHR misses 1610system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 2371413 # number of overall MSHR misses 1611system.cpu0.l2cache.overall_mshr_misses::total 3688438 # number of overall MSHR misses 1612system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 431221053 # number of ReadReq MSHR miss cycles 1613system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 615215054 # number of ReadReq MSHR miss cycles 1614system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2925869007 # number of ReadReq MSHR miss cycles 1615system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 23536761675 # number of ReadReq MSHR miss cycles 1616system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 27509066789 # number of ReadReq MSHR miss cycles 1617system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 70751604946 # number of HardPFReq MSHR miss cycles 1618system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 70751604946 # number of HardPFReq MSHR miss cycles 1619system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 31819773244 # number of WriteInvalidateReq MSHR miss cycles 1620system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 31819773244 # number of WriteInvalidateReq MSHR miss cycles 1621system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1812194258 # number of UpgradeReq MSHR miss cycles 1622system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1812194258 # number of UpgradeReq MSHR miss cycles 1623system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2134733797 # number of SCUpgradeReq MSHR miss cycles 1624system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2134733797 # number of SCUpgradeReq MSHR miss cycles 1625system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1512998 # number of SCUpgradeFailReq MSHR miss cycles 1626system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1512998 # number of SCUpgradeFailReq MSHR miss cycles 1627system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 8195268769 # number of ReadExReq MSHR miss cycles 1628system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 8195268769 # number of ReadExReq MSHR miss cycles 1629system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 431221053 # number of demand (read+write) MSHR miss cycles 1630system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 615215054 # number of demand (read+write) MSHR miss cycles 1631system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2925869007 # number of demand (read+write) MSHR miss cycles 1632system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 31732030444 # number of demand (read+write) MSHR miss cycles 1633system.cpu0.l2cache.demand_mshr_miss_latency::total 35704335558 # number of demand (read+write) MSHR miss cycles 1634system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 431221053 # number of overall MSHR miss cycles 1635system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 615215054 # number of overall MSHR miss cycles 1636system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2925869007 # number of overall MSHR miss cycles 1637system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 31732030444 # number of overall MSHR miss cycles 1638system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 70751604946 # number of overall MSHR miss cycles 1639system.cpu0.l2cache.overall_mshr_miss_latency::total 106455940504 # number of overall MSHR miss cycles 1640system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3061864750 # number of ReadReq MSHR uncacheable cycles 1641system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2263304784 # number of ReadReq MSHR uncacheable cycles 1642system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5325169534 # number of ReadReq MSHR uncacheable cycles 1643system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2282603541 # number of WriteReq MSHR uncacheable cycles 1644system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2282603541 # number of WriteReq MSHR uncacheable cycles 1645system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3061864750 # number of overall MSHR uncacheable cycles 1646system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4545908325 # number of overall MSHR uncacheable cycles 1647system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7607773075 # number of overall MSHR uncacheable cycles 1648system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.052762 # mshr miss rate for ReadReq accesses 1649system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.080481 # mshr miss rate for ReadReq accesses 1650system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.028745 # mshr miss rate for ReadReq accesses 1651system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.264509 # mshr miss rate for ReadReq accesses 1652system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.125833 # mshr miss rate for ReadReq accesses 1653system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1654system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1655system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.564373 # mshr miss rate for UpgradeReq accesses 1656system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.564373 # mshr miss rate for UpgradeReq accesses 1657system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.832908 # mshr miss rate for SCUpgradeReq accesses 1658system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.832908 # mshr miss rate for SCUpgradeReq accesses 1659system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1660system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1661system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.198063 # mshr miss rate for ReadExReq accesses 1662system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.198063 # mshr miss rate for ReadExReq accesses 1663system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.052762 # mshr miss rate for demand accesses 1664system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.080481 # mshr miss rate for demand accesses 1665system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.028745 # mshr miss rate for demand accesses 1666system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.248945 # mshr miss rate for demand accesses 1667system.cpu0.l2cache.demand_mshr_miss_rate::total 0.133808 # mshr miss rate for demand accesses 1668system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.052762 # mshr miss rate for overall accesses 1669system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.080481 # mshr miss rate for overall accesses 1670system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.028745 # mshr miss rate for overall accesses 1671system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.248945 # mshr miss rate for overall accesses 1672system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1673system.cpu0.l2cache.overall_mshr_miss_rate::total 0.374739 # mshr miss rate for overall accesses 1674system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 34902.553865 # average ReadReq mshr miss latency 1675system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 57572.061950 # average ReadReq mshr miss latency 1676system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 21046.237669 # average ReadReq mshr miss latency 1677system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 25046.382274 # average ReadReq mshr miss latency 1678system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24967.636080 # average ReadReq mshr miss latency 1679system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 29835.210040 # average HardPFReq mshr miss latency 1680system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 29835.210040 # average HardPFReq mshr miss latency 1681system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency 1682system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 1683system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17116.033303 # average UpgradeReq mshr miss latency 1684system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17116.033303 # average UpgradeReq mshr miss latency 1685system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13791.071813 # average SCUpgradeReq mshr miss latency 1686system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13791.071813 # average SCUpgradeReq mshr miss latency 1687system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 252166.333333 # average SCUpgradeFailReq mshr miss latency 1688system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 252166.333333 # average SCUpgradeFailReq mshr miss latency 1689system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38075.734399 # average ReadExReq mshr miss latency 1690system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38075.734399 # average ReadExReq mshr miss latency 1691system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 34902.553865 # average overall mshr miss latency 1692system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 57572.061950 # average overall mshr miss latency 1693system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 21046.237669 # average overall mshr miss latency 1694system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27474.499568 # average overall mshr miss latency 1695system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27109.838885 # average overall mshr miss latency 1696system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 34902.553865 # average overall mshr miss latency 1697system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 57572.061950 # average overall mshr miss latency 1698system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 21046.237669 # average overall mshr miss latency 1699system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27474.499568 # average overall mshr miss latency 1700system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 29835.210040 # average overall mshr miss latency 1701system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 28862.065867 # average overall mshr miss latency 1702system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1703system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1704system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1705system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1706system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1707system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1708system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1709system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1710system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1711system.cpu0.dcache.tags.replacements 5282593 # number of replacements 1712system.cpu0.dcache.tags.tagsinuse 478.557100 # Cycle average of tags in use 1713system.cpu0.dcache.tags.total_refs 149517101 # Total number of references to valid blocks. 1714system.cpu0.dcache.tags.sampled_refs 5283105 # Sample count of references to valid blocks. 1715system.cpu0.dcache.tags.avg_refs 28.300990 # Average number of references to valid blocks. 1716system.cpu0.dcache.tags.warmup_cycle 3644536500 # Cycle when the warmup percentage was hit. 1717system.cpu0.dcache.tags.occ_blocks::cpu0.data 478.557100 # Average occupied blocks per requestor 1718system.cpu0.dcache.tags.occ_percent::cpu0.data 0.934682 # Average percentage of cache occupancy 1719system.cpu0.dcache.tags.occ_percent::total 0.934682 # Average percentage of cache occupancy 1720system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1721system.cpu0.dcache.tags.age_task_id_blocks_1024::0 34 # Occupied blocks per task id 1722system.cpu0.dcache.tags.age_task_id_blocks_1024::1 411 # Occupied blocks per task id 1723system.cpu0.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id 1724system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1725system.cpu0.dcache.tags.tag_accesses 315346998 # Number of tag accesses 1726system.cpu0.dcache.tags.data_accesses 315346998 # Number of data accesses 1727system.cpu0.dcache.ReadReq_hits::cpu0.data 75666916 # number of ReadReq hits 1728system.cpu0.dcache.ReadReq_hits::total 75666916 # number of ReadReq hits 1729system.cpu0.dcache.WriteReq_hits::cpu0.data 69634196 # number of WriteReq hits 1730system.cpu0.dcache.WriteReq_hits::total 69634196 # number of WriteReq hits 1731system.cpu0.dcache.SoftPFReq_hits::cpu0.data 181888 # number of SoftPFReq hits 1732system.cpu0.dcache.SoftPFReq_hits::total 181888 # number of SoftPFReq hits 1733system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 858515 # number of WriteInvalidateReq hits 1734system.cpu0.dcache.WriteInvalidateReq_hits::total 858515 # number of WriteInvalidateReq hits 1735system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1792597 # number of LoadLockedReq hits 1736system.cpu0.dcache.LoadLockedReq_hits::total 1792597 # number of LoadLockedReq hits 1737system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1751129 # number of StoreCondReq hits 1738system.cpu0.dcache.StoreCondReq_hits::total 1751129 # number of StoreCondReq hits 1739system.cpu0.dcache.demand_hits::cpu0.data 145301112 # number of demand (read+write) hits 1740system.cpu0.dcache.demand_hits::total 145301112 # number of demand (read+write) hits 1741system.cpu0.dcache.overall_hits::cpu0.data 145483000 # number of overall hits 1742system.cpu0.dcache.overall_hits::total 145483000 # number of overall hits 1743system.cpu0.dcache.ReadReq_misses::cpu0.data 2868190 # number of ReadReq misses 1744system.cpu0.dcache.ReadReq_misses::total 2868190 # number of ReadReq misses 1745system.cpu0.dcache.WriteReq_misses::cpu0.data 1290634 # number of WriteReq misses 1746system.cpu0.dcache.WriteReq_misses::total 1290634 # number of WriteReq misses 1747system.cpu0.dcache.SoftPFReq_misses::cpu0.data 609921 # number of SoftPFReq misses 1748system.cpu0.dcache.SoftPFReq_misses::total 609921 # number of SoftPFReq misses 1749system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 145533 # number of LoadLockedReq misses 1750system.cpu0.dcache.LoadLockedReq_misses::total 145533 # number of LoadLockedReq misses 1751system.cpu0.dcache.StoreCondReq_misses::cpu0.data 185941 # number of StoreCondReq misses 1752system.cpu0.dcache.StoreCondReq_misses::total 185941 # number of StoreCondReq misses 1753system.cpu0.dcache.demand_misses::cpu0.data 4158824 # number of demand (read+write) misses 1754system.cpu0.dcache.demand_misses::total 4158824 # number of demand (read+write) misses 1755system.cpu0.dcache.overall_misses::cpu0.data 4768745 # number of overall misses 1756system.cpu0.dcache.overall_misses::total 4768745 # number of overall misses 1757system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41686378389 # number of ReadReq miss cycles 1758system.cpu0.dcache.ReadReq_miss_latency::total 41686378389 # number of ReadReq miss cycles 1759system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 22767469365 # number of WriteReq miss cycles 1760system.cpu0.dcache.WriteReq_miss_latency::total 22767469365 # number of WriteReq miss cycles 1761system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2114986821 # number of LoadLockedReq miss cycles 1762system.cpu0.dcache.LoadLockedReq_miss_latency::total 2114986821 # number of LoadLockedReq miss cycles 1763system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3970270831 # number of StoreCondReq miss cycles 1764system.cpu0.dcache.StoreCondReq_miss_latency::total 3970270831 # number of StoreCondReq miss cycles 1765system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1983000 # number of StoreCondFailReq miss cycles 1766system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1983000 # number of StoreCondFailReq miss cycles 1767system.cpu0.dcache.demand_miss_latency::cpu0.data 64453847754 # number of demand (read+write) miss cycles 1768system.cpu0.dcache.demand_miss_latency::total 64453847754 # number of demand (read+write) miss cycles 1769system.cpu0.dcache.overall_miss_latency::cpu0.data 64453847754 # number of overall miss cycles 1770system.cpu0.dcache.overall_miss_latency::total 64453847754 # number of overall miss cycles 1771system.cpu0.dcache.ReadReq_accesses::cpu0.data 78535106 # number of ReadReq accesses(hits+misses) 1772system.cpu0.dcache.ReadReq_accesses::total 78535106 # number of ReadReq accesses(hits+misses) 1773system.cpu0.dcache.WriteReq_accesses::cpu0.data 70924830 # number of WriteReq accesses(hits+misses) 1774system.cpu0.dcache.WriteReq_accesses::total 70924830 # number of WriteReq accesses(hits+misses) 1775system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 791809 # number of SoftPFReq accesses(hits+misses) 1776system.cpu0.dcache.SoftPFReq_accesses::total 791809 # number of SoftPFReq accesses(hits+misses) 1777system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 858515 # number of WriteInvalidateReq accesses(hits+misses) 1778system.cpu0.dcache.WriteInvalidateReq_accesses::total 858515 # number of WriteInvalidateReq accesses(hits+misses) 1779system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1938130 # number of LoadLockedReq accesses(hits+misses) 1780system.cpu0.dcache.LoadLockedReq_accesses::total 1938130 # number of LoadLockedReq accesses(hits+misses) 1781system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1937070 # number of StoreCondReq accesses(hits+misses) 1782system.cpu0.dcache.StoreCondReq_accesses::total 1937070 # number of StoreCondReq accesses(hits+misses) 1783system.cpu0.dcache.demand_accesses::cpu0.data 149459936 # number of demand (read+write) accesses 1784system.cpu0.dcache.demand_accesses::total 149459936 # number of demand (read+write) accesses 1785system.cpu0.dcache.overall_accesses::cpu0.data 150251745 # number of overall (read+write) accesses 1786system.cpu0.dcache.overall_accesses::total 150251745 # number of overall (read+write) accesses 1787system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036521 # miss rate for ReadReq accesses 1788system.cpu0.dcache.ReadReq_miss_rate::total 0.036521 # miss rate for ReadReq accesses 1789system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018197 # miss rate for WriteReq accesses 1790system.cpu0.dcache.WriteReq_miss_rate::total 0.018197 # miss rate for WriteReq accesses 1791system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.770288 # miss rate for SoftPFReq accesses 1792system.cpu0.dcache.SoftPFReq_miss_rate::total 0.770288 # miss rate for SoftPFReq accesses 1793system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.075089 # miss rate for LoadLockedReq accesses 1794system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.075089 # miss rate for LoadLockedReq accesses 1795system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095991 # miss rate for StoreCondReq accesses 1796system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095991 # miss rate for StoreCondReq accesses 1797system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027826 # miss rate for demand accesses 1798system.cpu0.dcache.demand_miss_rate::total 0.027826 # miss rate for demand accesses 1799system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031738 # miss rate for overall accesses 1800system.cpu0.dcache.overall_miss_rate::total 0.031738 # miss rate for overall accesses 1801system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14534.036584 # average ReadReq miss latency 1802system.cpu0.dcache.ReadReq_avg_miss_latency::total 14534.036584 # average ReadReq miss latency 1803system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17640.531216 # average WriteReq miss latency 1804system.cpu0.dcache.WriteReq_avg_miss_latency::total 17640.531216 # average WriteReq miss latency 1805system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14532.695822 # average LoadLockedReq miss latency 1806system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14532.695822 # average LoadLockedReq miss latency 1807system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21352.315148 # average StoreCondReq miss latency 1808system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21352.315148 # average StoreCondReq miss latency 1809system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 1810system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1811system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15498.094595 # average overall miss latency 1812system.cpu0.dcache.demand_avg_miss_latency::total 15498.094595 # average overall miss latency 1813system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13515.893124 # average overall miss latency 1814system.cpu0.dcache.overall_avg_miss_latency::total 13515.893124 # average overall miss latency 1815system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1816system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1817system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1818system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 1819system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1820system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1821system.cpu0.dcache.fast_writes 858515 # number of fast writes performed 1822system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1823system.cpu0.dcache.writebacks::writebacks 2894821 # number of writebacks 1824system.cpu0.dcache.writebacks::total 2894821 # number of writebacks 1825system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 28163 # number of ReadReq MSHR hits 1826system.cpu0.dcache.ReadReq_mshr_hits::total 28163 # number of ReadReq MSHR hits 1827system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21327 # number of WriteReq MSHR hits 1828system.cpu0.dcache.WriteReq_mshr_hits::total 21327 # number of WriteReq MSHR hits 1829system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 41518 # number of LoadLockedReq MSHR hits 1830system.cpu0.dcache.LoadLockedReq_mshr_hits::total 41518 # number of LoadLockedReq MSHR hits 1831system.cpu0.dcache.demand_mshr_hits::cpu0.data 49490 # number of demand (read+write) MSHR hits 1832system.cpu0.dcache.demand_mshr_hits::total 49490 # number of demand (read+write) MSHR hits 1833system.cpu0.dcache.overall_mshr_hits::cpu0.data 49490 # number of overall MSHR hits 1834system.cpu0.dcache.overall_mshr_hits::total 49490 # number of overall MSHR hits 1835system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2840027 # number of ReadReq MSHR misses 1836system.cpu0.dcache.ReadReq_mshr_misses::total 2840027 # number of ReadReq MSHR misses 1837system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1269307 # number of WriteReq MSHR misses 1838system.cpu0.dcache.WriteReq_mshr_misses::total 1269307 # number of WriteReq MSHR misses 1839system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 608681 # number of SoftPFReq MSHR misses 1840system.cpu0.dcache.SoftPFReq_mshr_misses::total 608681 # number of SoftPFReq MSHR misses 1841system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 104015 # number of LoadLockedReq MSHR misses 1842system.cpu0.dcache.LoadLockedReq_mshr_misses::total 104015 # number of LoadLockedReq MSHR misses 1843system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 185850 # number of StoreCondReq MSHR misses 1844system.cpu0.dcache.StoreCondReq_mshr_misses::total 185850 # number of StoreCondReq MSHR misses 1845system.cpu0.dcache.demand_mshr_misses::cpu0.data 4109334 # number of demand (read+write) MSHR misses 1846system.cpu0.dcache.demand_mshr_misses::total 4109334 # number of demand (read+write) MSHR misses 1847system.cpu0.dcache.overall_mshr_misses::cpu0.data 4718015 # number of overall MSHR misses 1848system.cpu0.dcache.overall_mshr_misses::total 4718015 # number of overall MSHR misses 1849system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 34673571058 # number of ReadReq MSHR miss cycles 1850system.cpu0.dcache.ReadReq_mshr_miss_latency::total 34673571058 # number of ReadReq MSHR miss cycles 1851system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 19854321886 # number of WriteReq MSHR miss cycles 1852system.cpu0.dcache.WriteReq_mshr_miss_latency::total 19854321886 # number of WriteReq MSHR miss cycles 1853system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13611528726 # number of SoftPFReq MSHR miss cycles 1854system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13611528726 # number of SoftPFReq MSHR miss cycles 1855system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 38259906745 # number of WriteInvalidateReq MSHR miss cycles 1856system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 38259906745 # number of WriteInvalidateReq MSHR miss cycles 1857system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1241876461 # number of LoadLockedReq MSHR miss cycles 1858system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1241876461 # number of LoadLockedReq MSHR miss cycles 1859system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3588911169 # number of StoreCondReq MSHR miss cycles 1860system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3588911169 # number of StoreCondReq MSHR miss cycles 1861system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1889000 # number of StoreCondFailReq MSHR miss cycles 1862system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1889000 # number of StoreCondFailReq MSHR miss cycles 1863system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 54527892944 # number of demand (read+write) MSHR miss cycles 1864system.cpu0.dcache.demand_mshr_miss_latency::total 54527892944 # number of demand (read+write) MSHR miss cycles 1865system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 68139421670 # number of overall MSHR miss cycles 1866system.cpu0.dcache.overall_mshr_miss_latency::total 68139421670 # number of overall MSHR miss cycles 1867system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2380477468 # number of ReadReq MSHR uncacheable cycles 1868system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2380477468 # number of ReadReq MSHR uncacheable cycles 1869system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2403593708 # number of WriteReq MSHR uncacheable cycles 1870system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2403593708 # number of WriteReq MSHR uncacheable cycles 1871system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4784071176 # number of overall MSHR uncacheable cycles 1872system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4784071176 # number of overall MSHR uncacheable cycles 1873system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036163 # mshr miss rate for ReadReq accesses 1874system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036163 # mshr miss rate for ReadReq accesses 1875system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017897 # mshr miss rate for WriteReq accesses 1876system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017897 # mshr miss rate for WriteReq accesses 1877system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.768722 # mshr miss rate for SoftPFReq accesses 1878system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.768722 # mshr miss rate for SoftPFReq accesses 1879system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.053668 # mshr miss rate for LoadLockedReq accesses 1880system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.053668 # mshr miss rate for LoadLockedReq accesses 1881system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095944 # mshr miss rate for StoreCondReq accesses 1882system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095944 # mshr miss rate for StoreCondReq accesses 1883system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027495 # mshr miss rate for demand accesses 1884system.cpu0.dcache.demand_mshr_miss_rate::total 0.027495 # mshr miss rate for demand accesses 1885system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031401 # mshr miss rate for overall accesses 1886system.cpu0.dcache.overall_mshr_miss_rate::total 0.031401 # mshr miss rate for overall accesses 1887system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12208.887823 # average ReadReq mshr miss latency 1888system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12208.887823 # average ReadReq mshr miss latency 1889system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15641.859602 # average WriteReq mshr miss latency 1890system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15641.859602 # average WriteReq mshr miss latency 1891system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22362.335486 # average SoftPFReq mshr miss latency 1892system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22362.335486 # average SoftPFReq mshr miss latency 1893system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency 1894system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 1895system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11939.397789 # average LoadLockedReq mshr miss latency 1896system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11939.397789 # average LoadLockedReq mshr miss latency 1897system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19310.794560 # average StoreCondReq mshr miss latency 1898system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19310.794560 # average StoreCondReq mshr miss latency 1899system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1900system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1901system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13269.277441 # average overall mshr miss latency 1902system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13269.277441 # average overall mshr miss latency 1903system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14442.391911 # average overall mshr miss latency 1904system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14442.391911 # average overall mshr miss latency 1905system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1906system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1907system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1908system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1909system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1910system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1911system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1912system.cpu0.toL2Bus.trans_dist::ReadReq 12330313 # Transaction distribution 1913system.cpu0.toL2Bus.trans_dist::ReadResp 9009509 # Transaction distribution 1914system.cpu0.toL2Bus.trans_dist::WriteReq 16126 # Transaction distribution 1915system.cpu0.toL2Bus.trans_dist::WriteResp 16126 # Transaction distribution 1916system.cpu0.toL2Bus.trans_dist::Writeback 2894821 # Transaction distribution 1917system.cpu0.toL2Bus.trans_dist::HardPFReq 3465295 # Transaction distribution 1918system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1670210 # Transaction distribution 1919system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 858515 # Transaction distribution 1920system.cpu0.toL2Bus.trans_dist::UpgradeReq 371533 # Transaction distribution 1921system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 344881 # Transaction distribution 1922system.cpu0.toL2Bus.trans_dist::UpgradeResp 439023 # Transaction distribution 1923system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution 1924system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution 1925system.cpu0.toL2Bus.trans_dist::ReadExReq 1234519 # Transaction distribution 1926system.cpu0.toL2Bus.trans_dist::ReadExResp 1094177 # Transaction distribution 1927system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 9758864 # Packet count per connected master and slave (bytes) 1928system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 14862906 # Packet count per connected master and slave (bytes) 1929system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 296442 # Packet count per connected master and slave (bytes) 1930system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 542592 # Packet count per connected master and slave (bytes) 1931system.cpu0.toL2Bus.pkt_count::total 25460804 # Packet count per connected master and slave (bytes) 1932system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 309696148 # Cumulative packet size per connected master and slave (bytes) 1933system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 543504195 # Cumulative packet size per connected master and slave (bytes) 1934system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1062208 # Cumulative packet size per connected master and slave (bytes) 1935system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1873320 # Cumulative packet size per connected master and slave (bytes) 1936system.cpu0.toL2Bus.pkt_size::total 856135871 # Cumulative packet size per connected master and slave (bytes) 1937system.cpu0.toL2Bus.snoops 8448176 # Total snoops (count) 1938system.cpu0.toL2Bus.snoop_fanout::samples 22253887 # Request fanout histogram 1939system.cpu0.toL2Bus.snoop_fanout::mean 5.367543 # Request fanout histogram 1940system.cpu0.toL2Bus.snoop_fanout::stdev 0.482136 # Request fanout histogram 1941system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1942system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1943system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1944system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1945system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1946system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1947system.cpu0.toL2Bus.snoop_fanout::5 14074632 63.25% 63.25% # Request fanout histogram 1948system.cpu0.toL2Bus.snoop_fanout::6 8179255 36.75% 100.00% # Request fanout histogram 1949system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1950system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1951system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1952system.cpu0.toL2Bus.snoop_fanout::total 22253887 # Request fanout histogram 1953system.cpu0.toL2Bus.reqLayer0.occupancy 10836211781 # Layer occupancy (ticks) 1954system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 1955system.cpu0.toL2Bus.snoopLayer0.occupancy 180026995 # Layer occupancy (ticks) 1956system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1957system.cpu0.toL2Bus.respLayer0.occupancy 7309068550 # Layer occupancy (ticks) 1958system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1959system.cpu0.toL2Bus.respLayer1.occupancy 7654516797 # Layer occupancy (ticks) 1960system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1961system.cpu0.toL2Bus.respLayer2.occupancy 164187799 # Layer occupancy (ticks) 1962system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1963system.cpu0.toL2Bus.respLayer3.occupancy 308745047 # Layer occupancy (ticks) 1964system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1965system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1966system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1967system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1968system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1969system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1970system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1971system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1972system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1973system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1974system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1975system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1976system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1977system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1978system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1979system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1980system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1981system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1982system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1983system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1984system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1985system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1986system.cpu1.dtb.inst_hits 0 # ITB inst hits 1987system.cpu1.dtb.inst_misses 0 # ITB inst misses 1988system.cpu1.dtb.read_hits 85169560 # DTB read hits 1989system.cpu1.dtb.read_misses 81568 # DTB read misses 1990system.cpu1.dtb.write_hits 77252621 # DTB write hits 1991system.cpu1.dtb.write_misses 28177 # DTB write misses 1992system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1993system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1994system.cpu1.dtb.flush_tlb_mva_asid 41415 # Number of times TLB was flushed by MVA & ASID 1995system.cpu1.dtb.flush_tlb_asid 1036 # Number of times TLB was flushed by ASID 1996system.cpu1.dtb.flush_entries 42405 # Number of entries that have been flushed from TLB 1997system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 1998system.cpu1.dtb.prefetch_faults 4822 # Number of TLB faults due to prefetch 1999system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 2000system.cpu1.dtb.perms_faults 11145 # Number of TLB faults due to permissions restrictions 2001system.cpu1.dtb.read_accesses 85251128 # DTB read accesses 2002system.cpu1.dtb.write_accesses 77280798 # DTB write accesses 2003system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 2004system.cpu1.dtb.hits 162422181 # DTB hits 2005system.cpu1.dtb.misses 109745 # DTB misses 2006system.cpu1.dtb.accesses 162531926 # DTB accesses 2007system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 2008system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 2009system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 2010system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 2011system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 2012system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 2013system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 2014system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2015system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 2016system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 2017system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 2018system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 2019system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 2020system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 2021system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 2022system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 2023system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 2024system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 2025system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 2026system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 2027system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 2028system.cpu1.itb.inst_hits 451299133 # ITB inst hits 2029system.cpu1.itb.inst_misses 60868 # ITB inst misses 2030system.cpu1.itb.read_hits 0 # DTB read hits 2031system.cpu1.itb.read_misses 0 # DTB read misses 2032system.cpu1.itb.write_hits 0 # DTB write hits 2033system.cpu1.itb.write_misses 0 # DTB write misses 2034system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 2035system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2036system.cpu1.itb.flush_tlb_mva_asid 41415 # Number of times TLB was flushed by MVA & ASID 2037system.cpu1.itb.flush_tlb_asid 1036 # Number of times TLB was flushed by ASID 2038system.cpu1.itb.flush_entries 29689 # Number of entries that have been flushed from TLB 2039system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 2040system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 2041system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 2042system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 2043system.cpu1.itb.read_accesses 0 # DTB read accesses 2044system.cpu1.itb.write_accesses 0 # DTB write accesses 2045system.cpu1.itb.inst_accesses 451360001 # ITB inst accesses 2046system.cpu1.itb.hits 451299133 # DTB hits 2047system.cpu1.itb.misses 60868 # DTB misses 2048system.cpu1.itb.accesses 451360001 # DTB accesses 2049system.cpu1.numCycles 94876549324 # number of cpu cycles simulated 2050system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 2051system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 2052system.cpu1.committedInsts 450991688 # Number of instructions committed 2053system.cpu1.committedOps 531140635 # Number of ops (including micro ops) committed 2054system.cpu1.num_int_alu_accesses 488008709 # Number of integer alu accesses 2055system.cpu1.num_fp_alu_accesses 470535 # Number of float alu accesses 2056system.cpu1.num_func_calls 27052635 # number of times a function call or return occured 2057system.cpu1.num_conditional_control_insts 68722135 # number of instructions that are conditional controls 2058system.cpu1.num_int_insts 488008709 # number of integer instructions 2059system.cpu1.num_fp_insts 470535 # number of float instructions 2060system.cpu1.num_int_register_reads 711965253 # number of times the integer registers were read 2061system.cpu1.num_int_register_writes 387496587 # number of times the integer registers were written 2062system.cpu1.num_fp_register_reads 748074 # number of times the floating registers were read 2063system.cpu1.num_fp_register_writes 424948 # number of times the floating registers were written 2064system.cpu1.num_cc_register_reads 118082190 # number of times the CC registers were read 2065system.cpu1.num_cc_register_writes 117761356 # number of times the CC registers were written 2066system.cpu1.num_mem_refs 162414438 # number of memory refs 2067system.cpu1.num_load_insts 85168501 # Number of load instructions 2068system.cpu1.num_store_insts 77245937 # Number of store instructions 2069system.cpu1.num_idle_cycles 93789094629.720032 # Number of idle cycles 2070system.cpu1.num_busy_cycles 1087454694.279977 # Number of busy cycles 2071system.cpu1.not_idle_fraction 0.011462 # Percentage of non-idle cycles 2072system.cpu1.idle_fraction 0.988538 # Percentage of idle cycles 2073system.cpu1.Branches 100614893 # Number of branches fetched 2074system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 2075system.cpu1.op_class::IntAlu 367777606 69.20% 69.20% # Class of executed instruction 2076system.cpu1.op_class::IntMult 1128259 0.21% 69.42% # Class of executed instruction 2077system.cpu1.op_class::IntDiv 59926 0.01% 69.43% # Class of executed instruction 2078system.cpu1.op_class::FloatAdd 0 0.00% 69.43% # Class of executed instruction 2079system.cpu1.op_class::FloatCmp 0 0.00% 69.43% # Class of executed instruction 2080system.cpu1.op_class::FloatCvt 0 0.00% 69.43% # Class of executed instruction 2081system.cpu1.op_class::FloatMult 0 0.00% 69.43% # Class of executed instruction 2082system.cpu1.op_class::FloatDiv 0 0.00% 69.43% # Class of executed instruction 2083system.cpu1.op_class::FloatSqrt 0 0.00% 69.43% # Class of executed instruction 2084system.cpu1.op_class::SimdAdd 0 0.00% 69.43% # Class of executed instruction 2085system.cpu1.op_class::SimdAddAcc 0 0.00% 69.43% # Class of executed instruction 2086system.cpu1.op_class::SimdAlu 0 0.00% 69.43% # Class of executed instruction 2087system.cpu1.op_class::SimdCmp 0 0.00% 69.43% # Class of executed instruction 2088system.cpu1.op_class::SimdCvt 0 0.00% 69.43% # Class of executed instruction 2089system.cpu1.op_class::SimdMisc 0 0.00% 69.43% # Class of executed instruction 2090system.cpu1.op_class::SimdMult 0 0.00% 69.43% # Class of executed instruction 2091system.cpu1.op_class::SimdMultAcc 0 0.00% 69.43% # Class of executed instruction 2092system.cpu1.op_class::SimdShift 0 0.00% 69.43% # Class of executed instruction 2093system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.43% # Class of executed instruction 2094system.cpu1.op_class::SimdSqrt 0 0.00% 69.43% # Class of executed instruction 2095system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.43% # Class of executed instruction 2096system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.43% # Class of executed instruction 2097system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.43% # Class of executed instruction 2098system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.43% # Class of executed instruction 2099system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.43% # Class of executed instruction 2100system.cpu1.op_class::SimdFloatMisc 67918 0.01% 69.44% # Class of executed instruction 2101system.cpu1.op_class::SimdFloatMult 0 0.00% 69.44% # Class of executed instruction 2102system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.44% # Class of executed instruction 2103system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.44% # Class of executed instruction 2104system.cpu1.op_class::MemRead 85168501 16.03% 85.47% # Class of executed instruction 2105system.cpu1.op_class::MemWrite 77245937 14.53% 100.00% # Class of executed instruction 2106system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 2107system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 2108system.cpu1.op_class::total 531448189 # Class of executed instruction 2109system.cpu1.kern.inst.arm 0 # number of arm instructions executed 2110system.cpu1.kern.inst.quiesce 13727 # number of quiesce instructions executed 2111system.cpu1.icache.tags.replacements 5018265 # number of replacements 2112system.cpu1.icache.tags.tagsinuse 496.292950 # Cycle average of tags in use 2113system.cpu1.icache.tags.total_refs 446280351 # Total number of references to valid blocks. 2114system.cpu1.icache.tags.sampled_refs 5018777 # Sample count of references to valid blocks. 2115system.cpu1.icache.tags.avg_refs 88.922132 # Average number of references to valid blocks. 2116system.cpu1.icache.tags.warmup_cycle 8374030789000 # Cycle when the warmup percentage was hit. 2117system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.292950 # Average occupied blocks per requestor 2118system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969322 # Average percentage of cache occupancy 2119system.cpu1.icache.tags.occ_percent::total 0.969322 # Average percentage of cache occupancy 2120system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2121system.cpu1.icache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id 2122system.cpu1.icache.tags.age_task_id_blocks_1024::1 272 # Occupied blocks per task id 2123system.cpu1.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id 2124system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id 2125system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2126system.cpu1.icache.tags.tag_accesses 907617048 # Number of tag accesses 2127system.cpu1.icache.tags.data_accesses 907617048 # Number of data accesses 2128system.cpu1.icache.ReadReq_hits::cpu1.inst 446280351 # number of ReadReq hits 2129system.cpu1.icache.ReadReq_hits::total 446280351 # number of ReadReq hits 2130system.cpu1.icache.demand_hits::cpu1.inst 446280351 # number of demand (read+write) hits 2131system.cpu1.icache.demand_hits::total 446280351 # number of demand (read+write) hits 2132system.cpu1.icache.overall_hits::cpu1.inst 446280351 # number of overall hits 2133system.cpu1.icache.overall_hits::total 446280351 # number of overall hits 2134system.cpu1.icache.ReadReq_misses::cpu1.inst 5018782 # number of ReadReq misses 2135system.cpu1.icache.ReadReq_misses::total 5018782 # number of ReadReq misses 2136system.cpu1.icache.demand_misses::cpu1.inst 5018782 # number of demand (read+write) misses 2137system.cpu1.icache.demand_misses::total 5018782 # number of demand (read+write) misses 2138system.cpu1.icache.overall_misses::cpu1.inst 5018782 # number of overall misses 2139system.cpu1.icache.overall_misses::total 5018782 # number of overall misses 2140system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 43828213410 # number of ReadReq miss cycles 2141system.cpu1.icache.ReadReq_miss_latency::total 43828213410 # number of ReadReq miss cycles 2142system.cpu1.icache.demand_miss_latency::cpu1.inst 43828213410 # number of demand (read+write) miss cycles 2143system.cpu1.icache.demand_miss_latency::total 43828213410 # number of demand (read+write) miss cycles 2144system.cpu1.icache.overall_miss_latency::cpu1.inst 43828213410 # number of overall miss cycles 2145system.cpu1.icache.overall_miss_latency::total 43828213410 # number of overall miss cycles 2146system.cpu1.icache.ReadReq_accesses::cpu1.inst 451299133 # number of ReadReq accesses(hits+misses) 2147system.cpu1.icache.ReadReq_accesses::total 451299133 # number of ReadReq accesses(hits+misses) 2148system.cpu1.icache.demand_accesses::cpu1.inst 451299133 # number of demand (read+write) accesses 2149system.cpu1.icache.demand_accesses::total 451299133 # number of demand (read+write) accesses 2150system.cpu1.icache.overall_accesses::cpu1.inst 451299133 # number of overall (read+write) accesses 2151system.cpu1.icache.overall_accesses::total 451299133 # number of overall (read+write) accesses 2152system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011121 # miss rate for ReadReq accesses 2153system.cpu1.icache.ReadReq_miss_rate::total 0.011121 # miss rate for ReadReq accesses 2154system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011121 # miss rate for demand accesses 2155system.cpu1.icache.demand_miss_rate::total 0.011121 # miss rate for demand accesses 2156system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011121 # miss rate for overall accesses 2157system.cpu1.icache.overall_miss_rate::total 0.011121 # miss rate for overall accesses 2158system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8732.838647 # average ReadReq miss latency 2159system.cpu1.icache.ReadReq_avg_miss_latency::total 8732.838647 # average ReadReq miss latency 2160system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8732.838647 # average overall miss latency 2161system.cpu1.icache.demand_avg_miss_latency::total 8732.838647 # average overall miss latency 2162system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8732.838647 # average overall miss latency 2163system.cpu1.icache.overall_avg_miss_latency::total 8732.838647 # average overall miss latency 2164system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2165system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2166system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 2167system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 2168system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2169system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2170system.cpu1.icache.fast_writes 0 # number of fast writes performed 2171system.cpu1.icache.cache_copies 0 # number of cache copies performed 2172system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5018782 # number of ReadReq MSHR misses 2173system.cpu1.icache.ReadReq_mshr_misses::total 5018782 # number of ReadReq MSHR misses 2174system.cpu1.icache.demand_mshr_misses::cpu1.inst 5018782 # number of demand (read+write) MSHR misses 2175system.cpu1.icache.demand_mshr_misses::total 5018782 # number of demand (read+write) MSHR misses 2176system.cpu1.icache.overall_mshr_misses::cpu1.inst 5018782 # number of overall MSHR misses 2177system.cpu1.icache.overall_mshr_misses::total 5018782 # number of overall MSHR misses 2178system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 36297023628 # number of ReadReq MSHR miss cycles 2179system.cpu1.icache.ReadReq_mshr_miss_latency::total 36297023628 # number of ReadReq MSHR miss cycles 2180system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 36297023628 # number of demand (read+write) MSHR miss cycles 2181system.cpu1.icache.demand_mshr_miss_latency::total 36297023628 # number of demand (read+write) MSHR miss cycles 2182system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 36297023628 # number of overall MSHR miss cycles 2183system.cpu1.icache.overall_mshr_miss_latency::total 36297023628 # number of overall MSHR miss cycles 2184system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8745500 # number of ReadReq MSHR uncacheable cycles 2185system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8745500 # number of ReadReq MSHR uncacheable cycles 2186system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8745500 # number of overall MSHR uncacheable cycles 2187system.cpu1.icache.overall_mshr_uncacheable_latency::total 8745500 # number of overall MSHR uncacheable cycles 2188system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011121 # mshr miss rate for ReadReq accesses 2189system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011121 # mshr miss rate for ReadReq accesses 2190system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011121 # mshr miss rate for demand accesses 2191system.cpu1.icache.demand_mshr_miss_rate::total 0.011121 # mshr miss rate for demand accesses 2192system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011121 # mshr miss rate for overall accesses 2193system.cpu1.icache.overall_mshr_miss_rate::total 0.011121 # mshr miss rate for overall accesses 2194system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7232.237548 # average ReadReq mshr miss latency 2195system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7232.237548 # average ReadReq mshr miss latency 2196system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7232.237548 # average overall mshr miss latency 2197system.cpu1.icache.demand_avg_mshr_miss_latency::total 7232.237548 # average overall mshr miss latency 2198system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7232.237548 # average overall mshr miss latency 2199system.cpu1.icache.overall_avg_mshr_miss_latency::total 7232.237548 # average overall mshr miss latency 2200system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2201system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2202system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2203system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2204system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2205system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 46849798 # number of hwpf identified 2206system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 849083 # number of hwpf that were already in mshr 2207system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 43478767 # number of hwpf that were already in the cache 2208system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 8509 # number of hwpf that were already in the prefetch queue 2209system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 2210system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 498 # number of hwpf removed because MSHR allocated 2211system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 2512941 # number of hwpf issued 2212system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 4003522 # number of hwpf spanning a virtual page 2213system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 2214system.cpu1.l2cache.tags.replacements 3186327 # number of replacements 2215system.cpu1.l2cache.tags.tagsinuse 13749.059276 # Cycle average of tags in use 2216system.cpu1.l2cache.tags.total_refs 10995274 # Total number of references to valid blocks. 2217system.cpu1.l2cache.tags.sampled_refs 3202540 # Sample count of references to valid blocks. 2218system.cpu1.l2cache.tags.avg_refs 3.433298 # Average number of references to valid blocks. 2219system.cpu1.l2cache.tags.warmup_cycle 10289671385000 # Cycle when the warmup percentage was hit. 2220system.cpu1.l2cache.tags.occ_blocks::writebacks 3719.678025 # Average occupied blocks per requestor 2221system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 60.787845 # Average occupied blocks per requestor 2222system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 70.255948 # Average occupied blocks per requestor 2223system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 738.115958 # Average occupied blocks per requestor 2224system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2404.101650 # Average occupied blocks per requestor 2225system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6756.119849 # Average occupied blocks per requestor 2226system.cpu1.l2cache.tags.occ_percent::writebacks 0.227031 # Average percentage of cache occupancy 2227system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003710 # Average percentage of cache occupancy 2228system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004288 # Average percentage of cache occupancy 2229system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.045051 # Average percentage of cache occupancy 2230system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.146735 # Average percentage of cache occupancy 2231system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.412361 # Average percentage of cache occupancy 2232system.cpu1.l2cache.tags.occ_percent::total 0.839176 # Average percentage of cache occupancy 2233system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9826 # Occupied blocks per task id 2234system.cpu1.l2cache.tags.occ_task_id_blocks::1023 113 # Occupied blocks per task id 2235system.cpu1.l2cache.tags.occ_task_id_blocks::1024 6274 # Occupied blocks per task id 2236system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 142 # Occupied blocks per task id 2237system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 1008 # Occupied blocks per task id 2238system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2026 # Occupied blocks per task id 2239system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 4347 # Occupied blocks per task id 2240system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 2303 # Occupied blocks per task id 2241system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 5 # Occupied blocks per task id 2242system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 31 # Occupied blocks per task id 2243system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id 2244system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 61 # Occupied blocks per task id 2245system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id 2246system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id 2247system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 496 # Occupied blocks per task id 2248system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1278 # Occupied blocks per task id 2249system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 3095 # Occupied blocks per task id 2250system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1333 # Occupied blocks per task id 2251system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.599731 # Percentage of cache occupancy per task id 2252system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006897 # Percentage of cache occupancy per task id 2253system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.382935 # Percentage of cache occupancy per task id 2254system.cpu1.l2cache.tags.tag_accesses 238490090 # Number of tag accesses 2255system.cpu1.l2cache.tags.data_accesses 238490090 # Number of data accesses 2256system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 228775 # number of ReadReq hits 2257system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 138969 # number of ReadReq hits 2258system.cpu1.l2cache.ReadReq_hits::cpu1.inst 4837723 # number of ReadReq hits 2259system.cpu1.l2cache.ReadReq_hits::cpu1.data 2811594 # number of ReadReq hits 2260system.cpu1.l2cache.ReadReq_hits::total 8017061 # number of ReadReq hits 2261system.cpu1.l2cache.Writeback_hits::writebacks 3078590 # number of Writeback hits 2262system.cpu1.l2cache.Writeback_hits::total 3078590 # number of Writeback hits 2263system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 84508 # number of UpgradeReq hits 2264system.cpu1.l2cache.UpgradeReq_hits::total 84508 # number of UpgradeReq hits 2265system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 36910 # number of SCUpgradeReq hits 2266system.cpu1.l2cache.SCUpgradeReq_hits::total 36910 # number of SCUpgradeReq hits 2267system.cpu1.l2cache.ReadExReq_hits::cpu1.data 942789 # number of ReadExReq hits 2268system.cpu1.l2cache.ReadExReq_hits::total 942789 # number of ReadExReq hits 2269system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 228775 # number of demand (read+write) hits 2270system.cpu1.l2cache.demand_hits::cpu1.itb.walker 138969 # number of demand (read+write) hits 2271system.cpu1.l2cache.demand_hits::cpu1.inst 4837723 # number of demand (read+write) hits 2272system.cpu1.l2cache.demand_hits::cpu1.data 3754383 # number of demand (read+write) hits 2273system.cpu1.l2cache.demand_hits::total 8959850 # number of demand (read+write) hits 2274system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 228775 # number of overall hits 2275system.cpu1.l2cache.overall_hits::cpu1.itb.walker 138969 # number of overall hits 2276system.cpu1.l2cache.overall_hits::cpu1.inst 4837723 # number of overall hits 2277system.cpu1.l2cache.overall_hits::cpu1.data 3754383 # number of overall hits 2278system.cpu1.l2cache.overall_hits::total 8959850 # number of overall hits 2279system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12809 # number of ReadReq misses 2280system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 11666 # number of ReadReq misses 2281system.cpu1.l2cache.ReadReq_misses::cpu1.inst 181059 # number of ReadReq misses 2282system.cpu1.l2cache.ReadReq_misses::cpu1.data 1016624 # number of ReadReq misses 2283system.cpu1.l2cache.ReadReq_misses::total 1222158 # number of ReadReq misses 2284system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 110012 # number of UpgradeReq misses 2285system.cpu1.l2cache.UpgradeReq_misses::total 110012 # number of UpgradeReq misses 2286system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 159084 # number of SCUpgradeReq misses 2287system.cpu1.l2cache.SCUpgradeReq_misses::total 159084 # number of SCUpgradeReq misses 2288system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 8 # number of SCUpgradeFailReq misses 2289system.cpu1.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses 2290system.cpu1.l2cache.ReadExReq_misses::cpu1.data 227840 # number of ReadExReq misses 2291system.cpu1.l2cache.ReadExReq_misses::total 227840 # number of ReadExReq misses 2292system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12809 # number of demand (read+write) misses 2293system.cpu1.l2cache.demand_misses::cpu1.itb.walker 11666 # number of demand (read+write) misses 2294system.cpu1.l2cache.demand_misses::cpu1.inst 181059 # number of demand (read+write) misses 2295system.cpu1.l2cache.demand_misses::cpu1.data 1244464 # number of demand (read+write) misses 2296system.cpu1.l2cache.demand_misses::total 1449998 # number of demand (read+write) misses 2297system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12809 # number of overall misses 2298system.cpu1.l2cache.overall_misses::cpu1.itb.walker 11666 # number of overall misses 2299system.cpu1.l2cache.overall_misses::cpu1.inst 181059 # number of overall misses 2300system.cpu1.l2cache.overall_misses::cpu1.data 1244464 # number of overall misses 2301system.cpu1.l2cache.overall_misses::total 1449998 # number of overall misses 2302system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 589793966 # number of ReadReq miss cycles 2303system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 732581953 # number of ReadReq miss cycles 2304system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 4736583796 # number of ReadReq miss cycles 2305system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 33373068876 # number of ReadReq miss cycles 2306system.cpu1.l2cache.ReadReq_miss_latency::total 39432028591 # number of ReadReq miss cycles 2307system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2203650350 # number of UpgradeReq miss cycles 2308system.cpu1.l2cache.UpgradeReq_miss_latency::total 2203650350 # number of UpgradeReq miss cycles 2309system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3257454308 # number of SCUpgradeReq miss cycles 2310system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3257454308 # number of SCUpgradeReq miss cycles 2311system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2221500 # number of SCUpgradeFailReq miss cycles 2312system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2221500 # number of SCUpgradeFailReq miss cycles 2313system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10235414817 # number of ReadExReq miss cycles 2314system.cpu1.l2cache.ReadExReq_miss_latency::total 10235414817 # number of ReadExReq miss cycles 2315system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 589793966 # number of demand (read+write) miss cycles 2316system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 732581953 # number of demand (read+write) miss cycles 2317system.cpu1.l2cache.demand_miss_latency::cpu1.inst 4736583796 # number of demand (read+write) miss cycles 2318system.cpu1.l2cache.demand_miss_latency::cpu1.data 43608483693 # number of demand (read+write) miss cycles 2319system.cpu1.l2cache.demand_miss_latency::total 49667443408 # number of demand (read+write) miss cycles 2320system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 589793966 # number of overall miss cycles 2321system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 732581953 # number of overall miss cycles 2322system.cpu1.l2cache.overall_miss_latency::cpu1.inst 4736583796 # number of overall miss cycles 2323system.cpu1.l2cache.overall_miss_latency::cpu1.data 43608483693 # number of overall miss cycles 2324system.cpu1.l2cache.overall_miss_latency::total 49667443408 # number of overall miss cycles 2325system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 241584 # number of ReadReq accesses(hits+misses) 2326system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 150635 # number of ReadReq accesses(hits+misses) 2327system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 5018782 # number of ReadReq accesses(hits+misses) 2328system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3828218 # number of ReadReq accesses(hits+misses) 2329system.cpu1.l2cache.ReadReq_accesses::total 9239219 # number of ReadReq accesses(hits+misses) 2330system.cpu1.l2cache.Writeback_accesses::writebacks 3078590 # number of Writeback accesses(hits+misses) 2331system.cpu1.l2cache.Writeback_accesses::total 3078590 # number of Writeback accesses(hits+misses) 2332system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 194520 # number of UpgradeReq accesses(hits+misses) 2333system.cpu1.l2cache.UpgradeReq_accesses::total 194520 # number of UpgradeReq accesses(hits+misses) 2334system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 195994 # number of SCUpgradeReq accesses(hits+misses) 2335system.cpu1.l2cache.SCUpgradeReq_accesses::total 195994 # number of SCUpgradeReq accesses(hits+misses) 2336system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 8 # number of SCUpgradeFailReq accesses(hits+misses) 2337system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses) 2338system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1170629 # number of ReadExReq accesses(hits+misses) 2339system.cpu1.l2cache.ReadExReq_accesses::total 1170629 # number of ReadExReq accesses(hits+misses) 2340system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 241584 # number of demand (read+write) accesses 2341system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 150635 # number of demand (read+write) accesses 2342system.cpu1.l2cache.demand_accesses::cpu1.inst 5018782 # number of demand (read+write) accesses 2343system.cpu1.l2cache.demand_accesses::cpu1.data 4998847 # number of demand (read+write) accesses 2344system.cpu1.l2cache.demand_accesses::total 10409848 # number of demand (read+write) accesses 2345system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 241584 # number of overall (read+write) accesses 2346system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 150635 # number of overall (read+write) accesses 2347system.cpu1.l2cache.overall_accesses::cpu1.inst 5018782 # number of overall (read+write) accesses 2348system.cpu1.l2cache.overall_accesses::cpu1.data 4998847 # number of overall (read+write) accesses 2349system.cpu1.l2cache.overall_accesses::total 10409848 # number of overall (read+write) accesses 2350system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.053021 # miss rate for ReadReq accesses 2351system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.077445 # miss rate for ReadReq accesses 2352system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.036076 # miss rate for ReadReq accesses 2353system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.265561 # miss rate for ReadReq accesses 2354system.cpu1.l2cache.ReadReq_miss_rate::total 0.132279 # miss rate for ReadReq accesses 2355system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.565556 # miss rate for UpgradeReq accesses 2356system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.565556 # miss rate for UpgradeReq accesses 2357system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.811678 # miss rate for SCUpgradeReq accesses 2358system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.811678 # miss rate for SCUpgradeReq accesses 2359system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2360system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2361system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.194630 # miss rate for ReadExReq accesses 2362system.cpu1.l2cache.ReadExReq_miss_rate::total 0.194630 # miss rate for ReadExReq accesses 2363system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.053021 # miss rate for demand accesses 2364system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.077445 # miss rate for demand accesses 2365system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.036076 # miss rate for demand accesses 2366system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.248950 # miss rate for demand accesses 2367system.cpu1.l2cache.demand_miss_rate::total 0.139291 # miss rate for demand accesses 2368system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.053021 # miss rate for overall accesses 2369system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.077445 # miss rate for overall accesses 2370system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.036076 # miss rate for overall accesses 2371system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.248950 # miss rate for overall accesses 2372system.cpu1.l2cache.overall_miss_rate::total 0.139291 # miss rate for overall accesses 2373system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 46045.278008 # average ReadReq miss latency 2374system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 62796.327190 # average ReadReq miss latency 2375system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 26160.443811 # average ReadReq miss latency 2376system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 32827.347058 # average ReadReq miss latency 2377system.cpu1.l2cache.ReadReq_avg_miss_latency::total 32264.264188 # average ReadReq miss latency 2378system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 20030.999800 # average UpgradeReq miss latency 2379system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 20030.999800 # average UpgradeReq miss latency 2380system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20476.316336 # average SCUpgradeReq miss latency 2381system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20476.316336 # average SCUpgradeReq miss latency 2382system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 277687.500000 # average SCUpgradeFailReq miss latency 2383system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 277687.500000 # average SCUpgradeFailReq miss latency 2384system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44923.695650 # average ReadExReq miss latency 2385system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44923.695650 # average ReadExReq miss latency 2386system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 46045.278008 # average overall miss latency 2387system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 62796.327190 # average overall miss latency 2388system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 26160.443811 # average overall miss latency 2389system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 35041.980879 # average overall miss latency 2390system.cpu1.l2cache.demand_avg_miss_latency::total 34253.456493 # average overall miss latency 2391system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 46045.278008 # average overall miss latency 2392system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 62796.327190 # average overall miss latency 2393system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 26160.443811 # average overall miss latency 2394system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 35041.980879 # average overall miss latency 2395system.cpu1.l2cache.overall_avg_miss_latency::total 34253.456493 # average overall miss latency 2396system.cpu1.l2cache.blocked_cycles::no_mshrs 7768 # number of cycles access was blocked 2397system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2398system.cpu1.l2cache.blocked::no_mshrs 221 # number of cycles access was blocked 2399system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2400system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 35.149321 # average number of cycles each access was blocked 2401system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2402system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2403system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 2404system.cpu1.l2cache.writebacks::writebacks 1013300 # number of writebacks 2405system.cpu1.l2cache.writebacks::total 1013300 # number of writebacks 2406system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 27917 # number of ReadReq MSHR hits 2407system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 1038 # number of ReadReq MSHR hits 2408system.cpu1.l2cache.ReadReq_mshr_hits::total 28955 # number of ReadReq MSHR hits 2409system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 6115 # number of ReadExReq MSHR hits 2410system.cpu1.l2cache.ReadExReq_mshr_hits::total 6115 # number of ReadExReq MSHR hits 2411system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 27917 # number of demand (read+write) MSHR hits 2412system.cpu1.l2cache.demand_mshr_hits::cpu1.data 7153 # number of demand (read+write) MSHR hits 2413system.cpu1.l2cache.demand_mshr_hits::total 35070 # number of demand (read+write) MSHR hits 2414system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 27917 # number of overall MSHR hits 2415system.cpu1.l2cache.overall_mshr_hits::cpu1.data 7153 # number of overall MSHR hits 2416system.cpu1.l2cache.overall_mshr_hits::total 35070 # number of overall MSHR hits 2417system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 12809 # number of ReadReq MSHR misses 2418system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 11666 # number of ReadReq MSHR misses 2419system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 153142 # number of ReadReq MSHR misses 2420system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 1015586 # number of ReadReq MSHR misses 2421system.cpu1.l2cache.ReadReq_mshr_misses::total 1193203 # number of ReadReq MSHR misses 2422system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 2512812 # number of HardPFReq MSHR misses 2423system.cpu1.l2cache.HardPFReq_mshr_misses::total 2512812 # number of HardPFReq MSHR misses 2424system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 110012 # number of UpgradeReq MSHR misses 2425system.cpu1.l2cache.UpgradeReq_mshr_misses::total 110012 # number of UpgradeReq MSHR misses 2426system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 159084 # number of SCUpgradeReq MSHR misses 2427system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 159084 # number of SCUpgradeReq MSHR misses 2428system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 8 # number of SCUpgradeFailReq MSHR misses 2429system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses 2430system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 221725 # number of ReadExReq MSHR misses 2431system.cpu1.l2cache.ReadExReq_mshr_misses::total 221725 # number of ReadExReq MSHR misses 2432system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 12809 # number of demand (read+write) MSHR misses 2433system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 11666 # number of demand (read+write) MSHR misses 2434system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 153142 # number of demand (read+write) MSHR misses 2435system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1237311 # number of demand (read+write) MSHR misses 2436system.cpu1.l2cache.demand_mshr_misses::total 1414928 # number of demand (read+write) MSHR misses 2437system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 12809 # number of overall MSHR misses 2438system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 11666 # number of overall MSHR misses 2439system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 153142 # number of overall MSHR misses 2440system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1237311 # number of overall MSHR misses 2441system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 2512812 # number of overall MSHR misses 2442system.cpu1.l2cache.overall_mshr_misses::total 3927740 # number of overall MSHR misses 2443system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 499166550 # number of ReadReq MSHR miss cycles 2444system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 649598551 # number of ReadReq MSHR miss cycles 2445system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 3217080793 # number of ReadReq MSHR miss cycles 2446system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 26145933834 # number of ReadReq MSHR miss cycles 2447system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 30511779728 # number of ReadReq MSHR miss cycles 2448system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 74093026830 # number of HardPFReq MSHR miss cycles 2449system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 74093026830 # number of HardPFReq MSHR miss cycles 2450system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 26166697651 # number of WriteInvalidateReq MSHR miss cycles 2451system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 26166697651 # number of WriteInvalidateReq MSHR miss cycles 2452system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 1898740270 # number of UpgradeReq MSHR miss cycles 2453system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 1898740270 # number of UpgradeReq MSHR miss cycles 2454system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2221301592 # number of SCUpgradeReq MSHR miss cycles 2455system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2221301592 # number of SCUpgradeReq MSHR miss cycles 2456system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1836500 # number of SCUpgradeFailReq MSHR miss cycles 2457system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1836500 # number of SCUpgradeFailReq MSHR miss cycles 2458system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8021601600 # number of ReadExReq MSHR miss cycles 2459system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8021601600 # number of ReadExReq MSHR miss cycles 2460system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 499166550 # number of demand (read+write) MSHR miss cycles 2461system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 649598551 # number of demand (read+write) MSHR miss cycles 2462system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 3217080793 # number of demand (read+write) MSHR miss cycles 2463system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 34167535434 # number of demand (read+write) MSHR miss cycles 2464system.cpu1.l2cache.demand_mshr_miss_latency::total 38533381328 # number of demand (read+write) MSHR miss cycles 2465system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 499166550 # number of overall MSHR miss cycles 2466system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 649598551 # number of overall MSHR miss cycles 2467system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 3217080793 # number of overall MSHR miss cycles 2468system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 34167535434 # number of overall MSHR miss cycles 2469system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 74093026830 # number of overall MSHR miss cycles 2470system.cpu1.l2cache.overall_mshr_miss_latency::total 112626408158 # number of overall MSHR miss cycles 2471system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7884500 # number of ReadReq MSHR uncacheable cycles 2472system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3785923263 # number of ReadReq MSHR uncacheable cycles 2473system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3793807763 # number of ReadReq MSHR uncacheable cycles 2474system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 3621697529 # number of WriteReq MSHR uncacheable cycles 2475system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3621697529 # number of WriteReq MSHR uncacheable cycles 2476system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7884500 # number of overall MSHR uncacheable cycles 2477system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 7407620792 # number of overall MSHR uncacheable cycles 2478system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 7415505292 # number of overall MSHR uncacheable cycles 2479system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.053021 # mshr miss rate for ReadReq accesses 2480system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.077445 # mshr miss rate for ReadReq accesses 2481system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.030514 # mshr miss rate for ReadReq accesses 2482system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.265289 # mshr miss rate for ReadReq accesses 2483system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.129145 # mshr miss rate for ReadReq accesses 2484system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2485system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2486system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.565556 # mshr miss rate for UpgradeReq accesses 2487system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.565556 # mshr miss rate for UpgradeReq accesses 2488system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.811678 # mshr miss rate for SCUpgradeReq accesses 2489system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.811678 # mshr miss rate for SCUpgradeReq accesses 2490system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2491system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2492system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.189407 # mshr miss rate for ReadExReq accesses 2493system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.189407 # mshr miss rate for ReadExReq accesses 2494system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.053021 # mshr miss rate for demand accesses 2495system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.077445 # mshr miss rate for demand accesses 2496system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.030514 # mshr miss rate for demand accesses 2497system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.247519 # mshr miss rate for demand accesses 2498system.cpu1.l2cache.demand_mshr_miss_rate::total 0.135922 # mshr miss rate for demand accesses 2499system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.053021 # mshr miss rate for overall accesses 2500system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.077445 # mshr miss rate for overall accesses 2501system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.030514 # mshr miss rate for overall accesses 2502system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.247519 # mshr miss rate for overall accesses 2503system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2504system.cpu1.l2cache.overall_mshr_miss_rate::total 0.377310 # mshr miss rate for overall accesses 2505system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 38969.985947 # average ReadReq mshr miss latency 2506system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 55683.057689 # average ReadReq mshr miss latency 2507system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21007.174994 # average ReadReq mshr miss latency 2508system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 25744.677294 # average ReadReq mshr miss latency 2509system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25571.323344 # average ReadReq mshr miss latency 2510system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 29486.100365 # average HardPFReq mshr miss latency 2511system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 29486.100365 # average HardPFReq mshr miss latency 2512system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency 2513system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 2514system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17259.392339 # average UpgradeReq mshr miss latency 2515system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17259.392339 # average UpgradeReq mshr miss latency 2516system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13963.073546 # average SCUpgradeReq mshr miss latency 2517system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13963.073546 # average SCUpgradeReq mshr miss latency 2518system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 229562.500000 # average SCUpgradeFailReq mshr miss latency 2519system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 229562.500000 # average SCUpgradeFailReq mshr miss latency 2520system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36178.155824 # average ReadExReq mshr miss latency 2521system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36178.155824 # average ReadExReq mshr miss latency 2522system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 38969.985947 # average overall mshr miss latency 2523system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 55683.057689 # average overall mshr miss latency 2524system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21007.174994 # average overall mshr miss latency 2525system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27614.347108 # average overall mshr miss latency 2526system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27233.457341 # average overall mshr miss latency 2527system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 38969.985947 # average overall mshr miss latency 2528system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 55683.057689 # average overall mshr miss latency 2529system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21007.174994 # average overall mshr miss latency 2530system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27614.347108 # average overall mshr miss latency 2531system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 29486.100365 # average overall mshr miss latency 2532system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28674.608848 # average overall mshr miss latency 2533system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2534system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2535system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2536system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2537system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2538system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2539system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2540system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2541system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2542system.cpu1.dcache.tags.replacements 5412769 # number of replacements 2543system.cpu1.dcache.tags.tagsinuse 455.628997 # Cycle average of tags in use 2544system.cpu1.dcache.tags.total_refs 156797756 # Total number of references to valid blocks. 2545system.cpu1.dcache.tags.sampled_refs 5413278 # Sample count of references to valid blocks. 2546system.cpu1.dcache.tags.avg_refs 28.965399 # Average number of references to valid blocks. 2547system.cpu1.dcache.tags.warmup_cycle 8374220312000 # Cycle when the warmup percentage was hit. 2548system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.628997 # Average occupied blocks per requestor 2549system.cpu1.dcache.tags.occ_percent::cpu1.data 0.889900 # Average percentage of cache occupancy 2550system.cpu1.dcache.tags.occ_percent::total 0.889900 # Average percentage of cache occupancy 2551system.cpu1.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id 2552system.cpu1.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id 2553system.cpu1.dcache.tags.age_task_id_blocks_1024::1 353 # Occupied blocks per task id 2554system.cpu1.dcache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id 2555system.cpu1.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id 2556system.cpu1.dcache.tags.tag_accesses 330228848 # Number of tag accesses 2557system.cpu1.dcache.tags.data_accesses 330228848 # Number of data accesses 2558system.cpu1.dcache.ReadReq_hits::cpu1.data 79329783 # number of ReadReq hits 2559system.cpu1.dcache.ReadReq_hits::total 79329783 # number of ReadReq hits 2560system.cpu1.dcache.WriteReq_hits::cpu1.data 73242746 # number of WriteReq hits 2561system.cpu1.dcache.WriteReq_hits::total 73242746 # number of WriteReq hits 2562system.cpu1.dcache.SoftPFReq_hits::cpu1.data 190572 # number of SoftPFReq hits 2563system.cpu1.dcache.SoftPFReq_hits::total 190572 # number of SoftPFReq hits 2564system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 704958 # number of WriteInvalidateReq hits 2565system.cpu1.dcache.WriteInvalidateReq_hits::total 704958 # number of WriteInvalidateReq hits 2566system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1728485 # number of LoadLockedReq hits 2567system.cpu1.dcache.LoadLockedReq_hits::total 1728485 # number of LoadLockedReq hits 2568system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1710118 # number of StoreCondReq hits 2569system.cpu1.dcache.StoreCondReq_hits::total 1710118 # number of StoreCondReq hits 2570system.cpu1.dcache.demand_hits::cpu1.data 152572529 # number of demand (read+write) hits 2571system.cpu1.dcache.demand_hits::total 152572529 # number of demand (read+write) hits 2572system.cpu1.dcache.overall_hits::cpu1.data 152763101 # number of overall hits 2573system.cpu1.dcache.overall_hits::total 152763101 # number of overall hits 2574system.cpu1.dcache.ReadReq_misses::cpu1.data 3054941 # number of ReadReq misses 2575system.cpu1.dcache.ReadReq_misses::total 3054941 # number of ReadReq misses 2576system.cpu1.dcache.WriteReq_misses::cpu1.data 1365411 # number of WriteReq misses 2577system.cpu1.dcache.WriteReq_misses::total 1365411 # number of WriteReq misses 2578system.cpu1.dcache.SoftPFReq_misses::cpu1.data 663261 # number of SoftPFReq misses 2579system.cpu1.dcache.SoftPFReq_misses::total 663261 # number of SoftPFReq misses 2580system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 178994 # number of LoadLockedReq misses 2581system.cpu1.dcache.LoadLockedReq_misses::total 178994 # number of LoadLockedReq misses 2582system.cpu1.dcache.StoreCondReq_misses::cpu1.data 196091 # number of StoreCondReq misses 2583system.cpu1.dcache.StoreCondReq_misses::total 196091 # number of StoreCondReq misses 2584system.cpu1.dcache.demand_misses::cpu1.data 4420352 # number of demand (read+write) misses 2585system.cpu1.dcache.demand_misses::total 4420352 # number of demand (read+write) misses 2586system.cpu1.dcache.overall_misses::cpu1.data 5083613 # number of overall misses 2587system.cpu1.dcache.overall_misses::total 5083613 # number of overall misses 2588system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 45633904603 # number of ReadReq miss cycles 2589system.cpu1.dcache.ReadReq_miss_latency::total 45633904603 # number of ReadReq miss cycles 2590system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 23251947701 # number of WriteReq miss cycles 2591system.cpu1.dcache.WriteReq_miss_latency::total 23251947701 # number of WriteReq miss cycles 2592system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2574333319 # number of LoadLockedReq miss cycles 2593system.cpu1.dcache.LoadLockedReq_miss_latency::total 2574333319 # number of LoadLockedReq miss cycles 2594system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4154245626 # number of StoreCondReq miss cycles 2595system.cpu1.dcache.StoreCondReq_miss_latency::total 4154245626 # number of StoreCondReq miss cycles 2596system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2386500 # number of StoreCondFailReq miss cycles 2597system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2386500 # number of StoreCondFailReq miss cycles 2598system.cpu1.dcache.demand_miss_latency::cpu1.data 68885852304 # number of demand (read+write) miss cycles 2599system.cpu1.dcache.demand_miss_latency::total 68885852304 # number of demand (read+write) miss cycles 2600system.cpu1.dcache.overall_miss_latency::cpu1.data 68885852304 # number of overall miss cycles 2601system.cpu1.dcache.overall_miss_latency::total 68885852304 # number of overall miss cycles 2602system.cpu1.dcache.ReadReq_accesses::cpu1.data 82384724 # number of ReadReq accesses(hits+misses) 2603system.cpu1.dcache.ReadReq_accesses::total 82384724 # number of ReadReq accesses(hits+misses) 2604system.cpu1.dcache.WriteReq_accesses::cpu1.data 74608157 # number of WriteReq accesses(hits+misses) 2605system.cpu1.dcache.WriteReq_accesses::total 74608157 # number of WriteReq accesses(hits+misses) 2606system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 853833 # number of SoftPFReq accesses(hits+misses) 2607system.cpu1.dcache.SoftPFReq_accesses::total 853833 # number of SoftPFReq accesses(hits+misses) 2608system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 704958 # number of WriteInvalidateReq accesses(hits+misses) 2609system.cpu1.dcache.WriteInvalidateReq_accesses::total 704958 # number of WriteInvalidateReq accesses(hits+misses) 2610system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1907479 # number of LoadLockedReq accesses(hits+misses) 2611system.cpu1.dcache.LoadLockedReq_accesses::total 1907479 # number of LoadLockedReq accesses(hits+misses) 2612system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1906209 # number of StoreCondReq accesses(hits+misses) 2613system.cpu1.dcache.StoreCondReq_accesses::total 1906209 # number of StoreCondReq accesses(hits+misses) 2614system.cpu1.dcache.demand_accesses::cpu1.data 156992881 # number of demand (read+write) accesses 2615system.cpu1.dcache.demand_accesses::total 156992881 # number of demand (read+write) accesses 2616system.cpu1.dcache.overall_accesses::cpu1.data 157846714 # number of overall (read+write) accesses 2617system.cpu1.dcache.overall_accesses::total 157846714 # number of overall (read+write) accesses 2618system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037081 # miss rate for ReadReq accesses 2619system.cpu1.dcache.ReadReq_miss_rate::total 0.037081 # miss rate for ReadReq accesses 2620system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018301 # miss rate for WriteReq accesses 2621system.cpu1.dcache.WriteReq_miss_rate::total 0.018301 # miss rate for WriteReq accesses 2622system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.776804 # miss rate for SoftPFReq accesses 2623system.cpu1.dcache.SoftPFReq_miss_rate::total 0.776804 # miss rate for SoftPFReq accesses 2624system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.093838 # miss rate for LoadLockedReq accesses 2625system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.093838 # miss rate for LoadLockedReq accesses 2626system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.102870 # miss rate for StoreCondReq accesses 2627system.cpu1.dcache.StoreCondReq_miss_rate::total 0.102870 # miss rate for StoreCondReq accesses 2628system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028156 # miss rate for demand accesses 2629system.cpu1.dcache.demand_miss_rate::total 0.028156 # miss rate for demand accesses 2630system.cpu1.dcache.overall_miss_rate::cpu1.data 0.032206 # miss rate for overall accesses 2631system.cpu1.dcache.overall_miss_rate::total 0.032206 # miss rate for overall accesses 2632system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14937.736802 # average ReadReq miss latency 2633system.cpu1.dcache.ReadReq_avg_miss_latency::total 14937.736802 # average ReadReq miss latency 2634system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17029.266427 # average WriteReq miss latency 2635system.cpu1.dcache.WriteReq_avg_miss_latency::total 17029.266427 # average WriteReq miss latency 2636system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14382.232471 # average LoadLockedReq miss latency 2637system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14382.232471 # average LoadLockedReq miss latency 2638system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21185.294715 # average StoreCondReq miss latency 2639system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21185.294715 # average StoreCondReq miss latency 2640system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 2641system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 2642system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15583.793396 # average overall miss latency 2643system.cpu1.dcache.demand_avg_miss_latency::total 15583.793396 # average overall miss latency 2644system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13550.569704 # average overall miss latency 2645system.cpu1.dcache.overall_avg_miss_latency::total 13550.569704 # average overall miss latency 2646system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2647system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2648system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2649system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 2650system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2651system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2652system.cpu1.dcache.fast_writes 704958 # number of fast writes performed 2653system.cpu1.dcache.cache_copies 0 # number of cache copies performed 2654system.cpu1.dcache.writebacks::writebacks 3078594 # number of writebacks 2655system.cpu1.dcache.writebacks::total 3078594 # number of writebacks 2656system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 23839 # number of ReadReq MSHR hits 2657system.cpu1.dcache.ReadReq_mshr_hits::total 23839 # number of ReadReq MSHR hits 2658system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 436 # number of WriteReq MSHR hits 2659system.cpu1.dcache.WriteReq_mshr_hits::total 436 # number of WriteReq MSHR hits 2660system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 45139 # number of LoadLockedReq MSHR hits 2661system.cpu1.dcache.LoadLockedReq_mshr_hits::total 45139 # number of LoadLockedReq MSHR hits 2662system.cpu1.dcache.demand_mshr_hits::cpu1.data 24275 # number of demand (read+write) MSHR hits 2663system.cpu1.dcache.demand_mshr_hits::total 24275 # number of demand (read+write) MSHR hits 2664system.cpu1.dcache.overall_mshr_hits::cpu1.data 24275 # number of overall MSHR hits 2665system.cpu1.dcache.overall_mshr_hits::total 24275 # number of overall MSHR hits 2666system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3031102 # number of ReadReq MSHR misses 2667system.cpu1.dcache.ReadReq_mshr_misses::total 3031102 # number of ReadReq MSHR misses 2668system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1364975 # number of WriteReq MSHR misses 2669system.cpu1.dcache.WriteReq_mshr_misses::total 1364975 # number of WriteReq MSHR misses 2670system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 663261 # number of SoftPFReq MSHR misses 2671system.cpu1.dcache.SoftPFReq_mshr_misses::total 663261 # number of SoftPFReq MSHR misses 2672system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 133855 # number of LoadLockedReq MSHR misses 2673system.cpu1.dcache.LoadLockedReq_mshr_misses::total 133855 # number of LoadLockedReq MSHR misses 2674system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 196002 # number of StoreCondReq MSHR misses 2675system.cpu1.dcache.StoreCondReq_mshr_misses::total 196002 # number of StoreCondReq MSHR misses 2676system.cpu1.dcache.demand_mshr_misses::cpu1.data 4396077 # number of demand (read+write) MSHR misses 2677system.cpu1.dcache.demand_mshr_misses::total 4396077 # number of demand (read+write) MSHR misses 2678system.cpu1.dcache.overall_mshr_misses::cpu1.data 5059338 # number of overall MSHR misses 2679system.cpu1.dcache.overall_mshr_misses::total 5059338 # number of overall MSHR misses 2680system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38375786357 # number of ReadReq MSHR miss cycles 2681system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38375786357 # number of ReadReq MSHR miss cycles 2682system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 20437608309 # number of WriteReq MSHR miss cycles 2683system.cpu1.dcache.WriteReq_mshr_miss_latency::total 20437608309 # number of WriteReq MSHR miss cycles 2684system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14184435008 # number of SoftPFReq MSHR miss cycles 2685system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14184435008 # number of SoftPFReq MSHR miss cycles 2686system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 31455228300 # number of WriteInvalidateReq MSHR miss cycles 2687system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 31455228300 # number of WriteInvalidateReq MSHR miss cycles 2688system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1522508206 # number of LoadLockedReq MSHR miss cycles 2689system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1522508206 # number of LoadLockedReq MSHR miss cycles 2690system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3750879374 # number of StoreCondReq MSHR miss cycles 2691system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3750879374 # number of StoreCondReq MSHR miss cycles 2692system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2276500 # number of StoreCondFailReq MSHR miss cycles 2693system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2276500 # number of StoreCondFailReq MSHR miss cycles 2694system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 58813394666 # number of demand (read+write) MSHR miss cycles 2695system.cpu1.dcache.demand_mshr_miss_latency::total 58813394666 # number of demand (read+write) MSHR miss cycles 2696system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 72997829674 # number of overall MSHR miss cycles 2697system.cpu1.dcache.overall_mshr_miss_latency::total 72997829674 # number of overall MSHR miss cycles 2698system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3974280487 # number of ReadReq MSHR uncacheable cycles 2699system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3974280487 # number of ReadReq MSHR uncacheable cycles 2700system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3786981721 # number of WriteReq MSHR uncacheable cycles 2701system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3786981721 # number of WriteReq MSHR uncacheable cycles 2702system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 7761262208 # number of overall MSHR uncacheable cycles 2703system.cpu1.dcache.overall_mshr_uncacheable_latency::total 7761262208 # number of overall MSHR uncacheable cycles 2704system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036792 # mshr miss rate for ReadReq accesses 2705system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036792 # mshr miss rate for ReadReq accesses 2706system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018295 # mshr miss rate for WriteReq accesses 2707system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018295 # mshr miss rate for WriteReq accesses 2708system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.776804 # mshr miss rate for SoftPFReq accesses 2709system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.776804 # mshr miss rate for SoftPFReq accesses 2710system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.070174 # mshr miss rate for LoadLockedReq accesses 2711system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.070174 # mshr miss rate for LoadLockedReq accesses 2712system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.102823 # mshr miss rate for StoreCondReq accesses 2713system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.102823 # mshr miss rate for StoreCondReq accesses 2714system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028002 # mshr miss rate for demand accesses 2715system.cpu1.dcache.demand_mshr_miss_rate::total 0.028002 # mshr miss rate for demand accesses 2716system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032052 # mshr miss rate for overall accesses 2717system.cpu1.dcache.overall_mshr_miss_rate::total 0.032052 # mshr miss rate for overall accesses 2718system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12660.671385 # average ReadReq mshr miss latency 2719system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12660.671385 # average ReadReq mshr miss latency 2720system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14972.881048 # average WriteReq mshr miss latency 2721system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14972.881048 # average WriteReq mshr miss latency 2722system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21385.902394 # average SoftPFReq mshr miss latency 2723system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21385.902394 # average SoftPFReq mshr miss latency 2724system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency 2725system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 2726system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11374.309559 # average LoadLockedReq mshr miss latency 2727system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11374.309559 # average LoadLockedReq mshr miss latency 2728system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19136.944388 # average StoreCondReq mshr miss latency 2729system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19136.944388 # average StoreCondReq mshr miss latency 2730system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2731system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 2732system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13378.608852 # average overall mshr miss latency 2733system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13378.608852 # average overall mshr miss latency 2734system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14428.336212 # average overall mshr miss latency 2735system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14428.336212 # average overall mshr miss latency 2736system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2737system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2738system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2739system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2740system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2741system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2742system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2743system.cpu1.toL2Bus.trans_dist::ReadReq 12531191 # Transaction distribution 2744system.cpu1.toL2Bus.trans_dist::ReadResp 9460246 # Transaction distribution 2745system.cpu1.toL2Bus.trans_dist::WriteReq 22034 # Transaction distribution 2746system.cpu1.toL2Bus.trans_dist::WriteResp 22034 # Transaction distribution 2747system.cpu1.toL2Bus.trans_dist::Writeback 3078590 # Transaction distribution 2748system.cpu1.toL2Bus.trans_dist::HardPFReq 3649719 # Transaction distribution 2749system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1670210 # Transaction distribution 2750system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 704958 # Transaction distribution 2751system.cpu1.toL2Bus.trans_dist::UpgradeReq 365743 # Transaction distribution 2752system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 350744 # Transaction distribution 2753system.cpu1.toL2Bus.trans_dist::UpgradeResp 452026 # Transaction distribution 2754system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 55 # Transaction distribution 2755system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution 2756system.cpu1.toL2Bus.trans_dist::ReadExReq 1320531 # Transaction distribution 2757system.cpu1.toL2Bus.trans_dist::ReadExResp 1177447 # Transaction distribution 2758system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 10037784 # Packet count per connected master and slave (bytes) 2759system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15516501 # Packet count per connected master and slave (bytes) 2760system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 332477 # Packet count per connected master and slave (bytes) 2761system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 559655 # Packet count per connected master and slave (bytes) 2762system.cpu1.toL2Bus.pkt_count::total 26446417 # Packet count per connected master and slave (bytes) 2763system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 321202488 # Cumulative packet size per connected master and slave (bytes) 2764system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 568398888 # Cumulative packet size per connected master and slave (bytes) 2765system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1205080 # Cumulative packet size per connected master and slave (bytes) 2766system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1932672 # Cumulative packet size per connected master and slave (bytes) 2767system.cpu1.toL2Bus.pkt_size::total 892739128 # Cumulative packet size per connected master and slave (bytes) 2768system.cpu1.toL2Bus.snoops 8517318 # Total snoops (count) 2769system.cpu1.toL2Bus.snoop_fanout::samples 22943145 # Request fanout histogram 2770system.cpu1.toL2Bus.snoop_fanout::mean 5.359651 # Request fanout histogram 2771system.cpu1.toL2Bus.snoop_fanout::stdev 0.479898 # Request fanout histogram 2772system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2773system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2774system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 2775system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 2776system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 2777system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 2778system.cpu1.toL2Bus.snoop_fanout::5 14691626 64.03% 64.03% # Request fanout histogram 2779system.cpu1.toL2Bus.snoop_fanout::6 8251519 35.97% 100.00% # Request fanout histogram 2780system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2781system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 2782system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 2783system.cpu1.toL2Bus.snoop_fanout::total 22943145 # Request fanout histogram 2784system.cpu1.toL2Bus.reqLayer0.occupancy 11163844442 # Layer occupancy (ticks) 2785system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2786system.cpu1.toL2Bus.snoopLayer0.occupancy 175587993 # Layer occupancy (ticks) 2787system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2788system.cpu1.toL2Bus.respLayer0.occupancy 7529809391 # Layer occupancy (ticks) 2789system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2790system.cpu1.toL2Bus.respLayer1.occupancy 8141370258 # Layer occupancy (ticks) 2791system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2792system.cpu1.toL2Bus.respLayer2.occupancy 182479297 # Layer occupancy (ticks) 2793system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2794system.cpu1.toL2Bus.respLayer3.occupancy 318532791 # Layer occupancy (ticks) 2795system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2796system.iocache.tags.replacements 115665 # number of replacements 2797system.iocache.tags.tagsinuse 11.304646 # Cycle average of tags in use 2798system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 2799system.iocache.tags.sampled_refs 115681 # Sample count of references to valid blocks. 2800system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 2801system.iocache.tags.warmup_cycle 9130394779000 # Cycle when the warmup percentage was hit. 2802system.iocache.tags.occ_blocks::realview.ethernet 7.406620 # Average occupied blocks per requestor 2803system.iocache.tags.occ_blocks::realview.ide 3.898026 # Average occupied blocks per requestor 2804system.iocache.tags.occ_percent::realview.ethernet 0.462914 # Average percentage of cache occupancy 2805system.iocache.tags.occ_percent::realview.ide 0.243627 # Average percentage of cache occupancy 2806system.iocache.tags.occ_percent::total 0.706540 # Average percentage of cache occupancy 2807system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2808system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2809system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2810system.iocache.tags.tag_accesses 1041810 # Number of tag accesses 2811system.iocache.tags.data_accesses 1041810 # Number of data accesses 2812system.iocache.WriteInvalidateReq_hits::realview.ide 106728 # number of WriteInvalidateReq hits 2813system.iocache.WriteInvalidateReq_hits::total 106728 # number of WriteInvalidateReq hits 2814system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2815system.iocache.ReadReq_misses::realview.ide 8941 # number of ReadReq misses 2816system.iocache.ReadReq_misses::total 8978 # number of ReadReq misses 2817system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2818system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2819system.iocache.WriteInvalidateReq_misses::realview.ide 54 # number of WriteInvalidateReq misses 2820system.iocache.WriteInvalidateReq_misses::total 54 # number of WriteInvalidateReq misses 2821system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 2822system.iocache.demand_misses::realview.ide 8941 # number of demand (read+write) misses 2823system.iocache.demand_misses::total 8981 # number of demand (read+write) misses 2824system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 2825system.iocache.overall_misses::realview.ide 8941 # number of overall misses 2826system.iocache.overall_misses::total 8981 # number of overall misses 2827system.iocache.ReadReq_miss_latency::realview.ethernet 5707000 # number of ReadReq miss cycles 2828system.iocache.ReadReq_miss_latency::realview.ide 1994628595 # number of ReadReq miss cycles 2829system.iocache.ReadReq_miss_latency::total 2000335595 # number of ReadReq miss cycles 2830system.iocache.WriteReq_miss_latency::realview.ethernet 357000 # number of WriteReq miss cycles 2831system.iocache.WriteReq_miss_latency::total 357000 # number of WriteReq miss cycles 2832system.iocache.demand_miss_latency::realview.ethernet 6064000 # number of demand (read+write) miss cycles 2833system.iocache.demand_miss_latency::realview.ide 1994628595 # number of demand (read+write) miss cycles 2834system.iocache.demand_miss_latency::total 2000692595 # number of demand (read+write) miss cycles 2835system.iocache.overall_miss_latency::realview.ethernet 6064000 # number of overall miss cycles 2836system.iocache.overall_miss_latency::realview.ide 1994628595 # number of overall miss cycles 2837system.iocache.overall_miss_latency::total 2000692595 # number of overall miss cycles 2838system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 2839system.iocache.ReadReq_accesses::realview.ide 8941 # number of ReadReq accesses(hits+misses) 2840system.iocache.ReadReq_accesses::total 8978 # number of ReadReq accesses(hits+misses) 2841system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2842system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2843system.iocache.WriteInvalidateReq_accesses::realview.ide 106782 # number of WriteInvalidateReq accesses(hits+misses) 2844system.iocache.WriteInvalidateReq_accesses::total 106782 # number of WriteInvalidateReq accesses(hits+misses) 2845system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 2846system.iocache.demand_accesses::realview.ide 8941 # number of demand (read+write) accesses 2847system.iocache.demand_accesses::total 8981 # number of demand (read+write) accesses 2848system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 2849system.iocache.overall_accesses::realview.ide 8941 # number of overall (read+write) accesses 2850system.iocache.overall_accesses::total 8981 # number of overall (read+write) accesses 2851system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2852system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2853system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2854system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2855system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2856system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000506 # miss rate for WriteInvalidateReq accesses 2857system.iocache.WriteInvalidateReq_miss_rate::total 0.000506 # miss rate for WriteInvalidateReq accesses 2858system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2859system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2860system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2861system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2862system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2863system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2864system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243 # average ReadReq miss latency 2865system.iocache.ReadReq_avg_miss_latency::realview.ide 223087.864333 # average ReadReq miss latency 2866system.iocache.ReadReq_avg_miss_latency::total 222804.142905 # average ReadReq miss latency 2867system.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency 2868system.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency 2869system.iocache.demand_avg_miss_latency::realview.ethernet 151600 # average overall miss latency 2870system.iocache.demand_avg_miss_latency::realview.ide 223087.864333 # average overall miss latency 2871system.iocache.demand_avg_miss_latency::total 222769.468322 # average overall miss latency 2872system.iocache.overall_avg_miss_latency::realview.ethernet 151600 # average overall miss latency 2873system.iocache.overall_avg_miss_latency::realview.ide 223087.864333 # average overall miss latency 2874system.iocache.overall_avg_miss_latency::total 222769.468322 # average overall miss latency 2875system.iocache.blocked_cycles::no_mshrs 55195 # number of cycles access was blocked 2876system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2877system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked 2878system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2879system.iocache.avg_blocked_cycles::no_mshrs 10.053734 # average number of cycles each access was blocked 2880system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2881system.iocache.fast_writes 106728 # number of fast writes performed 2882system.iocache.cache_copies 0 # number of cache copies performed 2883system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 2884system.iocache.ReadReq_mshr_misses::realview.ide 8941 # number of ReadReq MSHR misses 2885system.iocache.ReadReq_mshr_misses::total 8978 # number of ReadReq MSHR misses 2886system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2887system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2888system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 2889system.iocache.demand_mshr_misses::realview.ide 8941 # number of demand (read+write) MSHR misses 2890system.iocache.demand_mshr_misses::total 8981 # number of demand (read+write) MSHR misses 2891system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 2892system.iocache.overall_mshr_misses::realview.ide 8941 # number of overall MSHR misses 2893system.iocache.overall_mshr_misses::total 8981 # number of overall MSHR misses 2894system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3783000 # number of ReadReq MSHR miss cycles 2895system.iocache.ReadReq_mshr_miss_latency::realview.ide 1529539613 # number of ReadReq MSHR miss cycles 2896system.iocache.ReadReq_mshr_miss_latency::total 1533322613 # number of ReadReq MSHR miss cycles 2897system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 2898system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 2899system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6584739086 # number of WriteInvalidateReq MSHR miss cycles 2900system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6584739086 # number of WriteInvalidateReq MSHR miss cycles 2901system.iocache.demand_mshr_miss_latency::realview.ethernet 3984000 # number of demand (read+write) MSHR miss cycles 2902system.iocache.demand_mshr_miss_latency::realview.ide 1529539613 # number of demand (read+write) MSHR miss cycles 2903system.iocache.demand_mshr_miss_latency::total 1533523613 # number of demand (read+write) MSHR miss cycles 2904system.iocache.overall_mshr_miss_latency::realview.ethernet 3984000 # number of overall MSHR miss cycles 2905system.iocache.overall_mshr_miss_latency::realview.ide 1529539613 # number of overall MSHR miss cycles 2906system.iocache.overall_mshr_miss_latency::total 1533523613 # number of overall MSHR miss cycles 2907system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2908system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2909system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2910system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2911system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2912system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 2913system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2914system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2915system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 2916system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2917system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2918system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243 # average ReadReq mshr miss latency 2919system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 171070.306789 # average ReadReq mshr miss latency 2920system.iocache.ReadReq_avg_mshr_miss_latency::total 170786.657719 # average ReadReq mshr miss latency 2921system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 2922system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 2923system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency 2924system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 2925system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency 2926system.iocache.demand_avg_mshr_miss_latency::realview.ide 171070.306789 # average overall mshr miss latency 2927system.iocache.demand_avg_mshr_miss_latency::total 170751.988977 # average overall mshr miss latency 2928system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency 2929system.iocache.overall_avg_mshr_miss_latency::realview.ide 171070.306789 # average overall mshr miss latency 2930system.iocache.overall_avg_mshr_miss_latency::total 170751.988977 # average overall mshr miss latency 2931system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2932 2933---------- End Simulation Statistics ---------- 2934