stats.txt revision 10752:62b24818c8c6
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.111153 # Number of seconds simulated 4sim_ticks 51111152682000 # Number of ticks simulated 5final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1276359 # Simulator instruction rate (inst/s) 8host_op_rate 1499931 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 66258489115 # Simulator tick rate (ticks/s) 10host_mem_usage 712024 # Number of bytes of host memory used 11host_seconds 771.39 # Real time elapsed on the host 12sim_insts 984570519 # Number of instructions simulated 13sim_ops 1157031967 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 412352 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 376512 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 5562740 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 74833672 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 441792 # Number of bytes read from this memory 21system.physmem.bytes_read::total 81627068 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 5562740 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 5562740 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 103042944 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory 26system.physmem.bytes_written::total 103063524 # Number of bytes written to this memory 27system.physmem.num_reads::cpu.dtb.walker 6443 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 5883 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 127325 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 1169289 # Number of read requests responded to by this memory 31system.physmem.num_reads::realview.ide 6903 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 1315843 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 1610046 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 1612619 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu.dtb.walker 8068 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 7367 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.inst 108836 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 1464136 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::realview.ide 8644 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 1597050 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 108836 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 108836 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 2016056 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 2016459 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 2016056 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 8068 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 7367 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 108836 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 1464539 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::realview.ide 8644 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 3613509 # Total bandwidth to/from this memory (bytes/s) 54system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory 55system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 56system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory 57system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory 58system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory 59system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory 60system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 61system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory 62system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s) 63system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 64system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s) 65system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s) 66system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s) 67system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) 68system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 69system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) 70system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 71system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 72system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 73system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 74system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 75system.cf0.dma_write_txs 1669 # Number of DMA write transactions. 76system.cpu_clk_domain.clock 500 # Clock period in ticks 77system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 78system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 79system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 80system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 81system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 82system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 83system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 84system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 85system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 86system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 87system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 88system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 89system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 90system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 91system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 92system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 93system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 94system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 95system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 96system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 97system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 98system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 99system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 100system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 101system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 102system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 103system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 104system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 105system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 106system.cpu.dtb.walker.walks 265715 # Table walker walks requested 107system.cpu.dtb.walker.walksLong 265715 # Table walker walks initiated with long descriptors 108system.cpu.dtb.walker.walkWaitTime::samples 265715 # Table walker wait (enqueue to first request) latency 109system.cpu.dtb.walker.walkWaitTime::0 265715 100.00% 100.00% # Table walker wait (enqueue to first request) latency 110system.cpu.dtb.walker.walkWaitTime::total 265715 # Table walker wait (enqueue to first request) latency 111system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution 112system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution 113system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution 114system.cpu.dtb.walker.walkPageSizes::4K 204282 89.47% 89.47% # Table walker page sizes translated 115system.cpu.dtb.walker.walkPageSizes::2M 24037 10.53% 100.00% # Table walker page sizes translated 116system.cpu.dtb.walker.walkPageSizes::total 228319 # Table walker page sizes translated 117system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 265715 # Table walker requests started/completed, data/inst 118system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 119system.cpu.dtb.walker.walkRequestOrigin_Requested::total 265715 # Table walker requests started/completed, data/inst 120system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 228319 # Table walker requests started/completed, data/inst 121system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 122system.cpu.dtb.walker.walkRequestOrigin_Completed::total 228319 # Table walker requests started/completed, data/inst 123system.cpu.dtb.walker.walkRequestOrigin::total 494034 # Table walker requests started/completed, data/inst 124system.cpu.dtb.inst_hits 0 # ITB inst hits 125system.cpu.dtb.inst_misses 0 # ITB inst misses 126system.cpu.dtb.read_hits 184014035 # DTB read hits 127system.cpu.dtb.read_misses 194198 # DTB read misses 128system.cpu.dtb.write_hits 168232768 # DTB write hits 129system.cpu.dtb.write_misses 71517 # DTB write misses 130system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 131system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 132system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID 133system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID 134system.cpu.dtb.flush_entries 82353 # Number of entries that have been flushed from TLB 135system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 136system.cpu.dtb.prefetch_faults 9303 # Number of TLB faults due to prefetch 137system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 138system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions 139system.cpu.dtb.read_accesses 184208233 # DTB read accesses 140system.cpu.dtb.write_accesses 168304285 # DTB write accesses 141system.cpu.dtb.inst_accesses 0 # ITB inst accesses 142system.cpu.dtb.hits 352246803 # DTB hits 143system.cpu.dtb.misses 265715 # DTB misses 144system.cpu.dtb.accesses 352512518 # DTB accesses 145system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 146system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 147system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 148system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 149system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 150system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 151system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 152system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 153system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 154system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 155system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 156system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 157system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 158system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 159system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 160system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 161system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 162system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 163system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 164system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 165system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 166system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 167system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 168system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 169system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 170system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 171system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 172system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 173system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 174system.cpu.itb.walker.walks 126837 # Table walker walks requested 175system.cpu.itb.walker.walksLong 126837 # Table walker walks initiated with long descriptors 176system.cpu.itb.walker.walkWaitTime::samples 126837 # Table walker wait (enqueue to first request) latency 177system.cpu.itb.walker.walkWaitTime::0 126837 100.00% 100.00% # Table walker wait (enqueue to first request) latency 178system.cpu.itb.walker.walkWaitTime::total 126837 # Table walker wait (enqueue to first request) latency 179system.cpu.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution 180system.cpu.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution 181system.cpu.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution 182system.cpu.itb.walker.walkPageSizes::4K 113576 99.02% 99.02% # Table walker page sizes translated 183system.cpu.itb.walker.walkPageSizes::2M 1123 0.98% 100.00% # Table walker page sizes translated 184system.cpu.itb.walker.walkPageSizes::total 114699 # Table walker page sizes translated 185system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 186system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126837 # Table walker requests started/completed, data/inst 187system.cpu.itb.walker.walkRequestOrigin_Requested::total 126837 # Table walker requests started/completed, data/inst 188system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 189system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114699 # Table walker requests started/completed, data/inst 190system.cpu.itb.walker.walkRequestOrigin_Completed::total 114699 # Table walker requests started/completed, data/inst 191system.cpu.itb.walker.walkRequestOrigin::total 241536 # Table walker requests started/completed, data/inst 192system.cpu.itb.inst_hits 985047321 # ITB inst hits 193system.cpu.itb.inst_misses 126837 # ITB inst misses 194system.cpu.itb.read_hits 0 # DTB read hits 195system.cpu.itb.read_misses 0 # DTB read misses 196system.cpu.itb.write_hits 0 # DTB write hits 197system.cpu.itb.write_misses 0 # DTB write misses 198system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 199system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 200system.cpu.itb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID 201system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID 202system.cpu.itb.flush_entries 58174 # Number of entries that have been flushed from TLB 203system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 204system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 205system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 206system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 207system.cpu.itb.read_accesses 0 # DTB read accesses 208system.cpu.itb.write_accesses 0 # DTB write accesses 209system.cpu.itb.inst_accesses 985174158 # ITB inst accesses 210system.cpu.itb.hits 985047321 # DTB hits 211system.cpu.itb.misses 126837 # DTB misses 212system.cpu.itb.accesses 985174158 # DTB accesses 213system.cpu.numCycles 102222322140 # number of cpu cycles simulated 214system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 215system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 216system.cpu.committedInsts 984570519 # Number of instructions committed 217system.cpu.committedOps 1157031967 # Number of ops (including micro ops) committed 218system.cpu.num_int_alu_accesses 1060455466 # Number of integer alu accesses 219system.cpu.num_fp_alu_accesses 880805 # Number of float alu accesses 220system.cpu.num_func_calls 57056367 # number of times a function call or return occured 221system.cpu.num_conditional_control_insts 151940834 # number of instructions that are conditional controls 222system.cpu.num_int_insts 1060455466 # number of integer instructions 223system.cpu.num_fp_insts 880805 # number of float instructions 224system.cpu.num_int_register_reads 1564002170 # number of times the integer registers were read 225system.cpu.num_int_register_writes 842444791 # number of times the integer registers were written 226system.cpu.num_fp_register_reads 1418999 # number of times the floating registers were read 227system.cpu.num_fp_register_writes 747920 # number of times the floating registers were written 228system.cpu.num_cc_register_reads 264407058 # number of times the CC registers were read 229system.cpu.num_cc_register_writes 263829403 # number of times the CC registers were written 230system.cpu.num_mem_refs 352465606 # number of memory refs 231system.cpu.num_load_insts 184180431 # Number of load instructions 232system.cpu.num_store_insts 168285175 # Number of store instructions 233system.cpu.num_idle_cycles 101064643603.520065 # Number of idle cycles 234system.cpu.num_busy_cycles 1157678536.479939 # Number of busy cycles 235system.cpu.not_idle_fraction 0.011325 # Percentage of non-idle cycles 236system.cpu.idle_fraction 0.988675 # Percentage of idle cycles 237system.cpu.Branches 220088562 # Number of branches fetched 238system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 239system.cpu.op_class::IntAlu 802636616 69.33% 69.33% # Class of executed instruction 240system.cpu.op_class::IntMult 2354747 0.20% 69.54% # Class of executed instruction 241system.cpu.op_class::IntDiv 101759 0.01% 69.54% # Class of executed instruction 242system.cpu.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction 243system.cpu.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction 244system.cpu.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction 245system.cpu.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction 246system.cpu.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction 247system.cpu.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction 248system.cpu.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction 249system.cpu.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction 250system.cpu.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction 251system.cpu.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction 252system.cpu.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction 253system.cpu.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction 254system.cpu.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction 255system.cpu.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction 256system.cpu.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction 257system.cpu.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction 258system.cpu.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction 259system.cpu.op_class::SimdFloatAdd 8 0.00% 69.54% # Class of executed instruction 260system.cpu.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction 261system.cpu.op_class::SimdFloatCmp 13 0.00% 69.54% # Class of executed instruction 262system.cpu.op_class::SimdFloatCvt 21 0.00% 69.54% # Class of executed instruction 263system.cpu.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction 264system.cpu.op_class::SimdFloatMisc 107822 0.01% 69.55% # Class of executed instruction 265system.cpu.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction 266system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction 267system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction 268system.cpu.op_class::MemRead 184180431 15.91% 85.46% # Class of executed instruction 269system.cpu.op_class::MemWrite 168285175 14.54% 100.00% # Class of executed instruction 270system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 271system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 272system.cpu.op_class::total 1157666593 # Class of executed instruction 273system.cpu.kern.inst.arm 0 # number of arm instructions executed 274system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed 275system.cpu.dcache.tags.replacements 11612141 # number of replacements 276system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use 277system.cpu.dcache.tags.total_refs 340776008 # Total number of references to valid blocks. 278system.cpu.dcache.tags.sampled_refs 11612653 # Sample count of references to valid blocks. 279system.cpu.dcache.tags.avg_refs 29.345233 # Average number of references to valid blocks. 280system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. 281system.cpu.dcache.tags.occ_blocks::cpu.data 511.999719 # Average occupied blocks per requestor 282system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy 283system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy 284system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 285system.cpu.dcache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id 286system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id 287system.cpu.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id 288system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 289system.cpu.dcache.tags.tag_accesses 1421167352 # Number of tag accesses 290system.cpu.dcache.tags.data_accesses 1421167352 # Number of data accesses 291system.cpu.dcache.ReadReq_hits::cpu.data 171567259 # number of ReadReq hits 292system.cpu.dcache.ReadReq_hits::total 171567259 # number of ReadReq hits 293system.cpu.dcache.WriteReq_hits::cpu.data 159522870 # number of WriteReq hits 294system.cpu.dcache.WriteReq_hits::total 159522870 # number of WriteReq hits 295system.cpu.dcache.SoftPFReq_hits::cpu.data 424020 # number of SoftPFReq hits 296system.cpu.dcache.SoftPFReq_hits::total 424020 # number of SoftPFReq hits 297system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 337709 # number of WriteInvalidateReq hits 298system.cpu.dcache.WriteInvalidateReq_hits::total 337709 # number of WriteInvalidateReq hits 299system.cpu.dcache.LoadLockedReq_hits::cpu.data 4310545 # number of LoadLockedReq hits 300system.cpu.dcache.LoadLockedReq_hits::total 4310545 # number of LoadLockedReq hits 301system.cpu.dcache.StoreCondReq_hits::cpu.data 4562464 # number of StoreCondReq hits 302system.cpu.dcache.StoreCondReq_hits::total 4562464 # number of StoreCondReq hits 303system.cpu.dcache.demand_hits::cpu.data 331090129 # number of demand (read+write) hits 304system.cpu.dcache.demand_hits::total 331090129 # number of demand (read+write) hits 305system.cpu.dcache.overall_hits::cpu.data 331514149 # number of overall hits 306system.cpu.dcache.overall_hits::total 331514149 # number of overall hits 307system.cpu.dcache.ReadReq_misses::cpu.data 6010080 # number of ReadReq misses 308system.cpu.dcache.ReadReq_misses::total 6010080 # number of ReadReq misses 309system.cpu.dcache.WriteReq_misses::cpu.data 2570257 # number of WriteReq misses 310system.cpu.dcache.WriteReq_misses::total 2570257 # number of WriteReq misses 311system.cpu.dcache.SoftPFReq_misses::cpu.data 1584397 # number of SoftPFReq misses 312system.cpu.dcache.SoftPFReq_misses::total 1584397 # number of SoftPFReq misses 313system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1245349 # number of WriteInvalidateReq misses 314system.cpu.dcache.WriteInvalidateReq_misses::total 1245349 # number of WriteInvalidateReq misses 315system.cpu.dcache.LoadLockedReq_misses::cpu.data 253721 # number of LoadLockedReq misses 316system.cpu.dcache.LoadLockedReq_misses::total 253721 # number of LoadLockedReq misses 317system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses 318system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses 319system.cpu.dcache.demand_misses::cpu.data 8580337 # number of demand (read+write) misses 320system.cpu.dcache.demand_misses::total 8580337 # number of demand (read+write) misses 321system.cpu.dcache.overall_misses::cpu.data 10164734 # number of overall misses 322system.cpu.dcache.overall_misses::total 10164734 # number of overall misses 323system.cpu.dcache.ReadReq_accesses::cpu.data 177577339 # number of ReadReq accesses(hits+misses) 324system.cpu.dcache.ReadReq_accesses::total 177577339 # number of ReadReq accesses(hits+misses) 325system.cpu.dcache.WriteReq_accesses::cpu.data 162093127 # number of WriteReq accesses(hits+misses) 326system.cpu.dcache.WriteReq_accesses::total 162093127 # number of WriteReq accesses(hits+misses) 327system.cpu.dcache.SoftPFReq_accesses::cpu.data 2008417 # number of SoftPFReq accesses(hits+misses) 328system.cpu.dcache.SoftPFReq_accesses::total 2008417 # number of SoftPFReq accesses(hits+misses) 329system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1583058 # number of WriteInvalidateReq accesses(hits+misses) 330system.cpu.dcache.WriteInvalidateReq_accesses::total 1583058 # number of WriteInvalidateReq accesses(hits+misses) 331system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4564266 # number of LoadLockedReq accesses(hits+misses) 332system.cpu.dcache.LoadLockedReq_accesses::total 4564266 # number of LoadLockedReq accesses(hits+misses) 333system.cpu.dcache.StoreCondReq_accesses::cpu.data 4562465 # number of StoreCondReq accesses(hits+misses) 334system.cpu.dcache.StoreCondReq_accesses::total 4562465 # number of StoreCondReq accesses(hits+misses) 335system.cpu.dcache.demand_accesses::cpu.data 339670466 # number of demand (read+write) accesses 336system.cpu.dcache.demand_accesses::total 339670466 # number of demand (read+write) accesses 337system.cpu.dcache.overall_accesses::cpu.data 341678883 # number of overall (read+write) accesses 338system.cpu.dcache.overall_accesses::total 341678883 # number of overall (read+write) accesses 339system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033845 # miss rate for ReadReq accesses 340system.cpu.dcache.ReadReq_miss_rate::total 0.033845 # miss rate for ReadReq accesses 341system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015857 # miss rate for WriteReq accesses 342system.cpu.dcache.WriteReq_miss_rate::total 0.015857 # miss rate for WriteReq accesses 343system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788879 # miss rate for SoftPFReq accesses 344system.cpu.dcache.SoftPFReq_miss_rate::total 0.788879 # miss rate for SoftPFReq accesses 345system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.786673 # miss rate for WriteInvalidateReq accesses 346system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.786673 # miss rate for WriteInvalidateReq accesses 347system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055589 # miss rate for LoadLockedReq accesses 348system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055589 # miss rate for LoadLockedReq accesses 349system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses 350system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses 351system.cpu.dcache.demand_miss_rate::cpu.data 0.025261 # miss rate for demand accesses 352system.cpu.dcache.demand_miss_rate::total 0.025261 # miss rate for demand accesses 353system.cpu.dcache.overall_miss_rate::cpu.data 0.029749 # miss rate for overall accesses 354system.cpu.dcache.overall_miss_rate::total 0.029749 # miss rate for overall accesses 355system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 356system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 357system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 358system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 359system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 360system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 361system.cpu.dcache.fast_writes 0 # number of fast writes performed 362system.cpu.dcache.cache_copies 0 # number of cache copies performed 363system.cpu.dcache.writebacks::writebacks 8921315 # number of writebacks 364system.cpu.dcache.writebacks::total 8921315 # number of writebacks 365system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 366system.cpu.icache.tags.replacements 14295641 # number of replacements 367system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use 368system.cpu.icache.tags.total_refs 970865862 # Total number of references to valid blocks. 369system.cpu.icache.tags.sampled_refs 14296153 # Sample count of references to valid blocks. 370system.cpu.icache.tags.avg_refs 67.910987 # Average number of references to valid blocks. 371system.cpu.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit. 372system.cpu.icache.tags.occ_blocks::cpu.inst 511.984599 # Average occupied blocks per requestor 373system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy 374system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy 375system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 376system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id 377system.cpu.icache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id 378system.cpu.icache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id 379system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 380system.cpu.icache.tags.tag_accesses 999458178 # Number of tag accesses 381system.cpu.icache.tags.data_accesses 999458178 # Number of data accesses 382system.cpu.icache.ReadReq_hits::cpu.inst 970865862 # number of ReadReq hits 383system.cpu.icache.ReadReq_hits::total 970865862 # number of ReadReq hits 384system.cpu.icache.demand_hits::cpu.inst 970865862 # number of demand (read+write) hits 385system.cpu.icache.demand_hits::total 970865862 # number of demand (read+write) hits 386system.cpu.icache.overall_hits::cpu.inst 970865862 # number of overall hits 387system.cpu.icache.overall_hits::total 970865862 # number of overall hits 388system.cpu.icache.ReadReq_misses::cpu.inst 14296158 # number of ReadReq misses 389system.cpu.icache.ReadReq_misses::total 14296158 # number of ReadReq misses 390system.cpu.icache.demand_misses::cpu.inst 14296158 # number of demand (read+write) misses 391system.cpu.icache.demand_misses::total 14296158 # number of demand (read+write) misses 392system.cpu.icache.overall_misses::cpu.inst 14296158 # number of overall misses 393system.cpu.icache.overall_misses::total 14296158 # number of overall misses 394system.cpu.icache.ReadReq_accesses::cpu.inst 985162020 # number of ReadReq accesses(hits+misses) 395system.cpu.icache.ReadReq_accesses::total 985162020 # number of ReadReq accesses(hits+misses) 396system.cpu.icache.demand_accesses::cpu.inst 985162020 # number of demand (read+write) accesses 397system.cpu.icache.demand_accesses::total 985162020 # number of demand (read+write) accesses 398system.cpu.icache.overall_accesses::cpu.inst 985162020 # number of overall (read+write) accesses 399system.cpu.icache.overall_accesses::total 985162020 # number of overall (read+write) accesses 400system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014511 # miss rate for ReadReq accesses 401system.cpu.icache.ReadReq_miss_rate::total 0.014511 # miss rate for ReadReq accesses 402system.cpu.icache.demand_miss_rate::cpu.inst 0.014511 # miss rate for demand accesses 403system.cpu.icache.demand_miss_rate::total 0.014511 # miss rate for demand accesses 404system.cpu.icache.overall_miss_rate::cpu.inst 0.014511 # miss rate for overall accesses 405system.cpu.icache.overall_miss_rate::total 0.014511 # miss rate for overall accesses 406system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 407system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 408system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 409system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 410system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 411system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 412system.cpu.icache.fast_writes 0 # number of fast writes performed 413system.cpu.icache.cache_copies 0 # number of cache copies performed 414system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 415system.cpu.l2cache.tags.replacements 1722692 # number of replacements 416system.cpu.l2cache.tags.tagsinuse 65341.862502 # Cycle average of tags in use 417system.cpu.l2cache.tags.total_refs 29983424 # Total number of references to valid blocks. 418system.cpu.l2cache.tags.sampled_refs 1785989 # Sample count of references to valid blocks. 419system.cpu.l2cache.tags.avg_refs 16.788135 # Average number of references to valid blocks. 420system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. 421system.cpu.l2cache.tags.occ_blocks::writebacks 37141.715219 # Average occupied blocks per requestor 422system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 310.196824 # Average occupied blocks per requestor 423system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 443.735041 # Average occupied blocks per requestor 424system.cpu.l2cache.tags.occ_blocks::cpu.inst 6261.263092 # Average occupied blocks per requestor 425system.cpu.l2cache.tags.occ_blocks::cpu.data 21184.952326 # Average occupied blocks per requestor 426system.cpu.l2cache.tags.occ_percent::writebacks 0.566738 # Average percentage of cache occupancy 427system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004733 # Average percentage of cache occupancy 428system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006771 # Average percentage of cache occupancy 429system.cpu.l2cache.tags.occ_percent::cpu.inst 0.095539 # Average percentage of cache occupancy 430system.cpu.l2cache.tags.occ_percent::cpu.data 0.323257 # Average percentage of cache occupancy 431system.cpu.l2cache.tags.occ_percent::total 0.997038 # Average percentage of cache occupancy 432system.cpu.l2cache.tags.occ_task_id_blocks::1023 278 # Occupied blocks per task id 433system.cpu.l2cache.tags.occ_task_id_blocks::1024 63019 # Occupied blocks per task id 434system.cpu.l2cache.tags.age_task_id_blocks_1023::4 278 # Occupied blocks per task id 435system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id 436system.cpu.l2cache.tags.age_task_id_blocks_1024::1 588 # Occupied blocks per task id 437system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2715 # Occupied blocks per task id 438system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4911 # Occupied blocks per task id 439system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54669 # Occupied blocks per task id 440system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004242 # Percentage of cache occupancy per task id 441system.cpu.l2cache.tags.occ_task_id_percent::1024 0.961594 # Percentage of cache occupancy per task id 442system.cpu.l2cache.tags.tag_accesses 290307620 # Number of tag accesses 443system.cpu.l2cache.tags.data_accesses 290307620 # Number of data accesses 444system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 506612 # number of ReadReq hits 445system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255623 # number of ReadReq hits 446system.cpu.l2cache.ReadReq_hits::cpu.inst 14211921 # number of ReadReq hits 447system.cpu.l2cache.ReadReq_hits::cpu.data 7504232 # number of ReadReq hits 448system.cpu.l2cache.ReadReq_hits::total 22478388 # number of ReadReq hits 449system.cpu.l2cache.Writeback_hits::writebacks 8921315 # number of Writeback hits 450system.cpu.l2cache.Writeback_hits::total 8921315 # number of Writeback hits 451system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 694333 # number of WriteInvalidateReq hits 452system.cpu.l2cache.WriteInvalidateReq_hits::total 694333 # number of WriteInvalidateReq hits 453system.cpu.l2cache.UpgradeReq_hits::cpu.data 11223 # number of UpgradeReq hits 454system.cpu.l2cache.UpgradeReq_hits::total 11223 # number of UpgradeReq hits 455system.cpu.l2cache.ReadExReq_hits::cpu.data 1692610 # number of ReadExReq hits 456system.cpu.l2cache.ReadExReq_hits::total 1692610 # number of ReadExReq hits 457system.cpu.l2cache.demand_hits::cpu.dtb.walker 506612 # number of demand (read+write) hits 458system.cpu.l2cache.demand_hits::cpu.itb.walker 255623 # number of demand (read+write) hits 459system.cpu.l2cache.demand_hits::cpu.inst 14211921 # number of demand (read+write) hits 460system.cpu.l2cache.demand_hits::cpu.data 9196842 # number of demand (read+write) hits 461system.cpu.l2cache.demand_hits::total 24170998 # number of demand (read+write) hits 462system.cpu.l2cache.overall_hits::cpu.dtb.walker 506612 # number of overall hits 463system.cpu.l2cache.overall_hits::cpu.itb.walker 255623 # number of overall hits 464system.cpu.l2cache.overall_hits::cpu.inst 14211921 # number of overall hits 465system.cpu.l2cache.overall_hits::cpu.data 9196842 # number of overall hits 466system.cpu.l2cache.overall_hits::total 24170998 # number of overall hits 467system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6443 # number of ReadReq misses 468system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5883 # number of ReadReq misses 469system.cpu.l2cache.ReadReq_misses::cpu.inst 84237 # number of ReadReq misses 470system.cpu.l2cache.ReadReq_misses::cpu.data 343966 # number of ReadReq misses 471system.cpu.l2cache.ReadReq_misses::total 440529 # number of ReadReq misses 472system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 551016 # number of WriteInvalidateReq misses 473system.cpu.l2cache.WriteInvalidateReq_misses::total 551016 # number of WriteInvalidateReq misses 474system.cpu.l2cache.UpgradeReq_misses::cpu.data 39917 # number of UpgradeReq misses 475system.cpu.l2cache.UpgradeReq_misses::total 39917 # number of UpgradeReq misses 476system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses 477system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses 478system.cpu.l2cache.ReadExReq_misses::cpu.data 826507 # number of ReadExReq misses 479system.cpu.l2cache.ReadExReq_misses::total 826507 # number of ReadExReq misses 480system.cpu.l2cache.demand_misses::cpu.dtb.walker 6443 # number of demand (read+write) misses 481system.cpu.l2cache.demand_misses::cpu.itb.walker 5883 # number of demand (read+write) misses 482system.cpu.l2cache.demand_misses::cpu.inst 84237 # number of demand (read+write) misses 483system.cpu.l2cache.demand_misses::cpu.data 1170473 # number of demand (read+write) misses 484system.cpu.l2cache.demand_misses::total 1267036 # number of demand (read+write) misses 485system.cpu.l2cache.overall_misses::cpu.dtb.walker 6443 # number of overall misses 486system.cpu.l2cache.overall_misses::cpu.itb.walker 5883 # number of overall misses 487system.cpu.l2cache.overall_misses::cpu.inst 84237 # number of overall misses 488system.cpu.l2cache.overall_misses::cpu.data 1170473 # number of overall misses 489system.cpu.l2cache.overall_misses::total 1267036 # number of overall misses 490system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 513055 # number of ReadReq accesses(hits+misses) 491system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 261506 # number of ReadReq accesses(hits+misses) 492system.cpu.l2cache.ReadReq_accesses::cpu.inst 14296158 # number of ReadReq accesses(hits+misses) 493system.cpu.l2cache.ReadReq_accesses::cpu.data 7848198 # number of ReadReq accesses(hits+misses) 494system.cpu.l2cache.ReadReq_accesses::total 22918917 # number of ReadReq accesses(hits+misses) 495system.cpu.l2cache.Writeback_accesses::writebacks 8921315 # number of Writeback accesses(hits+misses) 496system.cpu.l2cache.Writeback_accesses::total 8921315 # number of Writeback accesses(hits+misses) 497system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1245349 # number of WriteInvalidateReq accesses(hits+misses) 498system.cpu.l2cache.WriteInvalidateReq_accesses::total 1245349 # number of WriteInvalidateReq accesses(hits+misses) 499system.cpu.l2cache.UpgradeReq_accesses::cpu.data 51140 # number of UpgradeReq accesses(hits+misses) 500system.cpu.l2cache.UpgradeReq_accesses::total 51140 # number of UpgradeReq accesses(hits+misses) 501system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) 502system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) 503system.cpu.l2cache.ReadExReq_accesses::cpu.data 2519117 # number of ReadExReq accesses(hits+misses) 504system.cpu.l2cache.ReadExReq_accesses::total 2519117 # number of ReadExReq accesses(hits+misses) 505system.cpu.l2cache.demand_accesses::cpu.dtb.walker 513055 # number of demand (read+write) accesses 506system.cpu.l2cache.demand_accesses::cpu.itb.walker 261506 # number of demand (read+write) accesses 507system.cpu.l2cache.demand_accesses::cpu.inst 14296158 # number of demand (read+write) accesses 508system.cpu.l2cache.demand_accesses::cpu.data 10367315 # number of demand (read+write) accesses 509system.cpu.l2cache.demand_accesses::total 25438034 # number of demand (read+write) accesses 510system.cpu.l2cache.overall_accesses::cpu.dtb.walker 513055 # number of overall (read+write) accesses 511system.cpu.l2cache.overall_accesses::cpu.itb.walker 261506 # number of overall (read+write) accesses 512system.cpu.l2cache.overall_accesses::cpu.inst 14296158 # number of overall (read+write) accesses 513system.cpu.l2cache.overall_accesses::cpu.data 10367315 # number of overall (read+write) accesses 514system.cpu.l2cache.overall_accesses::total 25438034 # number of overall (read+write) accesses 515system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012558 # miss rate for ReadReq accesses 516system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022497 # miss rate for ReadReq accesses 517system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005892 # miss rate for ReadReq accesses 518system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.043827 # miss rate for ReadReq accesses 519system.cpu.l2cache.ReadReq_miss_rate::total 0.019221 # miss rate for ReadReq accesses 520system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.442459 # miss rate for WriteInvalidateReq accesses 521system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.442459 # miss rate for WriteInvalidateReq accesses 522system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780544 # miss rate for UpgradeReq accesses 523system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780544 # miss rate for UpgradeReq accesses 524system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 525system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 526system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328094 # miss rate for ReadExReq accesses 527system.cpu.l2cache.ReadExReq_miss_rate::total 0.328094 # miss rate for ReadExReq accesses 528system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012558 # miss rate for demand accesses 529system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022497 # miss rate for demand accesses 530system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005892 # miss rate for demand accesses 531system.cpu.l2cache.demand_miss_rate::cpu.data 0.112900 # miss rate for demand accesses 532system.cpu.l2cache.demand_miss_rate::total 0.049809 # miss rate for demand accesses 533system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012558 # miss rate for overall accesses 534system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022497 # miss rate for overall accesses 535system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005892 # miss rate for overall accesses 536system.cpu.l2cache.overall_miss_rate::cpu.data 0.112900 # miss rate for overall accesses 537system.cpu.l2cache.overall_miss_rate::total 0.049809 # miss rate for overall accesses 538system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 539system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 540system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 541system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 542system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 543system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 544system.cpu.l2cache.fast_writes 0 # number of fast writes performed 545system.cpu.l2cache.cache_copies 0 # number of cache copies performed 546system.cpu.l2cache.writebacks::writebacks 1503415 # number of writebacks 547system.cpu.l2cache.writebacks::total 1503415 # number of writebacks 548system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 549system.cpu.toL2Bus.trans_dist::ReadReq 23372119 # Transaction distribution 550system.cpu.toL2Bus.trans_dist::ReadResp 23372119 # Transaction distribution 551system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution 552system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution 553system.cpu.toL2Bus.trans_dist::Writeback 8921315 # Transaction distribution 554system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1245349 # Transaction distribution 555system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1245349 # Transaction distribution 556system.cpu.toL2Bus.trans_dist::UpgradeReq 51140 # Transaction distribution 557system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution 558system.cpu.toL2Bus.trans_dist::UpgradeResp 51141 # Transaction distribution 559system.cpu.toL2Bus.trans_dist::ReadExReq 2519117 # Transaction distribution 560system.cpu.toL2Bus.trans_dist::ReadExResp 2519117 # Transaction distribution 561system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 28678566 # Packet count per connected master and slave (bytes) 562system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32383245 # Packet count per connected master and slave (bytes) 563system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758224 # Packet count per connected master and slave (bytes) 564system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1543944 # Packet count per connected master and slave (bytes) 565system.cpu.toL2Bus.pkt_count::total 63363979 # Packet count per connected master and slave (bytes) 566system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 915126612 # Cumulative packet size per connected master and slave (bytes) 567system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1314364326 # Cumulative packet size per connected master and slave (bytes) 568system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032896 # Cumulative packet size per connected master and slave (bytes) 569system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6175776 # Cumulative packet size per connected master and slave (bytes) 570system.cpu.toL2Bus.pkt_size::total 2238699610 # Cumulative packet size per connected master and slave (bytes) 571system.cpu.toL2Bus.snoops 116338 # Total snoops (count) 572system.cpu.toL2Bus.snoop_fanout::samples 36147883 # Request fanout histogram 573system.cpu.toL2Bus.snoop_fanout::mean 3.003196 # Request fanout histogram 574system.cpu.toL2Bus.snoop_fanout::stdev 0.056441 # Request fanout histogram 575system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 576system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 577system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 578system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 579system.cpu.toL2Bus.snoop_fanout::3 36032362 99.68% 99.68% # Request fanout histogram 580system.cpu.toL2Bus.snoop_fanout::4 115521 0.32% 100.00% # Request fanout histogram 581system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 582system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 583system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 584system.cpu.toL2Bus.snoop_fanout::total 36147883 # Request fanout histogram 585system.iobus.trans_dist::ReadReq 40246 # Transaction distribution 586system.iobus.trans_dist::ReadResp 40246 # Transaction distribution 587system.iobus.trans_dist::WriteReq 136515 # Transaction distribution 588system.iobus.trans_dist::WriteResp 29851 # Transaction distribution 589system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution 590system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes) 591system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 592system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 593system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 594system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 595system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 596system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 597system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 598system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 599system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 600system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 601system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 602system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 603system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 604system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 605system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes) 606system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230962 # Packet count per connected master and slave (bytes) 607system.iobus.pkt_count_system.realview.ide.dma::total 230962 # Packet count per connected master and slave (bytes) 608system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 609system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 610system.iobus.pkt_count::total 353522 # Packet count per connected master and slave (bytes) 611system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes) 612system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 613system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 614system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 615system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 616system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 617system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 618system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 619system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 620system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 621system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 622system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 623system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 624system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 625system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 626system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes) 627system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334280 # Cumulative packet size per connected master and slave (bytes) 628system.iobus.pkt_size_system.realview.ide.dma::total 7334280 # Cumulative packet size per connected master and slave (bytes) 629system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 630system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 631system.iobus.pkt_size::total 7491976 # Cumulative packet size per connected master and slave (bytes) 632system.iocache.tags.replacements 115463 # number of replacements 633system.iocache.tags.tagsinuse 10.407109 # Cycle average of tags in use 634system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 635system.iocache.tags.sampled_refs 115479 # Sample count of references to valid blocks. 636system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 637system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit. 638system.iocache.tags.occ_blocks::realview.ethernet 3.554599 # Average occupied blocks per requestor 639system.iocache.tags.occ_blocks::realview.ide 6.852510 # Average occupied blocks per requestor 640system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy 641system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy 642system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy 643system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 644system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 645system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 646system.iocache.tags.tag_accesses 1039686 # Number of tag accesses 647system.iocache.tags.data_accesses 1039686 # Number of data accesses 648system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 649system.iocache.ReadReq_misses::realview.ide 8817 # number of ReadReq misses 650system.iocache.ReadReq_misses::total 8854 # number of ReadReq misses 651system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 652system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 653system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses 654system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses 655system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 656system.iocache.demand_misses::realview.ide 8817 # number of demand (read+write) misses 657system.iocache.demand_misses::total 8857 # number of demand (read+write) misses 658system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 659system.iocache.overall_misses::realview.ide 8817 # number of overall misses 660system.iocache.overall_misses::total 8857 # number of overall misses 661system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 662system.iocache.ReadReq_accesses::realview.ide 8817 # number of ReadReq accesses(hits+misses) 663system.iocache.ReadReq_accesses::total 8854 # number of ReadReq accesses(hits+misses) 664system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 665system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 666system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) 667system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) 668system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 669system.iocache.demand_accesses::realview.ide 8817 # number of demand (read+write) accesses 670system.iocache.demand_accesses::total 8857 # number of demand (read+write) accesses 671system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 672system.iocache.overall_accesses::realview.ide 8817 # number of overall (read+write) accesses 673system.iocache.overall_accesses::total 8857 # number of overall (read+write) accesses 674system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 675system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 676system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 677system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 678system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 679system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 680system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 681system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 682system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 683system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 684system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 685system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 686system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 687system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 688system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 689system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 690system.iocache.blocked::no_targets 0 # number of cycles access was blocked 691system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 692system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 693system.iocache.fast_writes 0 # number of fast writes performed 694system.iocache.cache_copies 0 # number of cache copies performed 695system.iocache.writebacks::writebacks 106631 # number of writebacks 696system.iocache.writebacks::total 106631 # number of writebacks 697system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 698system.membus.trans_dist::ReadReq 526062 # Transaction distribution 699system.membus.trans_dist::ReadResp 526062 # Transaction distribution 700system.membus.trans_dist::WriteReq 33606 # Transaction distribution 701system.membus.trans_dist::WriteResp 33606 # Transaction distribution 702system.membus.trans_dist::Writeback 1610046 # Transaction distribution 703system.membus.trans_dist::WriteInvalidateReq 657675 # Transaction distribution 704system.membus.trans_dist::WriteInvalidateResp 657675 # Transaction distribution 705system.membus.trans_dist::UpgradeReq 40484 # Transaction distribution 706system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution 707system.membus.trans_dist::UpgradeResp 40485 # Transaction distribution 708system.membus.trans_dist::ReadExReq 825948 # Transaction distribution 709system.membus.trans_dist::ReadExResp 825948 # Transaction distribution 710system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) 711system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) 712system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) 713system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5310733 # Packet count per connected master and slave (bytes) 714system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5439925 # Packet count per connected master and slave (bytes) 715system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337673 # Packet count per connected master and slave (bytes) 716system.membus.pkt_count_system.iocache.mem_side::total 337673 # Packet count per connected master and slave (bytes) 717system.membus.pkt_count::total 5777598 # Packet count per connected master and slave (bytes) 718system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) 719system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) 720system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) 721system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 212730912 # Cumulative packet size per connected master and slave (bytes) 722system.membus.pkt_size_system.cpu.l2cache.mem_side::total 212899962 # Cumulative packet size per connected master and slave (bytes) 723system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217536 # Cumulative packet size per connected master and slave (bytes) 724system.membus.pkt_size_system.iocache.mem_side::total 14217536 # Cumulative packet size per connected master and slave (bytes) 725system.membus.pkt_size::total 227117498 # Cumulative packet size per connected master and slave (bytes) 726system.membus.snoops 0 # Total snoops (count) 727system.membus.snoop_fanout::samples 3583537 # Request fanout histogram 728system.membus.snoop_fanout::mean 1 # Request fanout histogram 729system.membus.snoop_fanout::stdev 0 # Request fanout histogram 730system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 731system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 732system.membus.snoop_fanout::1 3583537 100.00% 100.00% # Request fanout histogram 733system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 734system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 735system.membus.snoop_fanout::min_value 1 # Request fanout histogram 736system.membus.snoop_fanout::max_value 1 # Request fanout histogram 737system.membus.snoop_fanout::total 3583537 # Request fanout histogram 738system.realview.ethernet.txBytes 966 # Bytes Transmitted 739system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 740system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 741system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 742system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 743system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 744system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 745system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 746system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 747system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) 748system.realview.ethernet.totPackets 3 # Total Packets 749system.realview.ethernet.totBytes 966 # Total Bytes 750system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 751system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) 752system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 753system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 754system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 755system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 756system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 757system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 758system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 759system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 760system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 761system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 762system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 763system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 764system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 765system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 766system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 767system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 768system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 769system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 770system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 771system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 772system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 773system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 774system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 775system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 776system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 777system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 778system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 779system.realview.ethernet.droppedPackets 0 # number of packets dropped 780 781---------- End Simulation Statistics ---------- 782