110515SN/A 210515SN/A---------- Begin Simulation Statistics ---------- 311860Sandreas.hansson@arm.comsim_seconds 51.071102 # Number of seconds simulated 411860Sandreas.hansson@arm.comsim_ticks 51071102402000 # Number of ticks simulated 511860Sandreas.hansson@arm.comfinal_tick 51071102402000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711860Sandreas.hansson@arm.comhost_inst_rate 1747137 # Simulator instruction rate (inst/s) 811860Sandreas.hansson@arm.comhost_op_rate 2084338 # Simulator op (including micro ops) rate (op/s) 911860Sandreas.hansson@arm.comhost_tick_rate 95484785421 # Simulator tick rate (ticks/s) 1011860Sandreas.hansson@arm.comhost_mem_usage 679432 # Number of bytes of host memory used 1111860Sandreas.hansson@arm.comhost_seconds 534.86 # Real time elapsed on the host 1211860Sandreas.hansson@arm.comsim_insts 934475925 # Number of instructions simulated 1311860Sandreas.hansson@arm.comsim_ops 1114831373 # Number of ops (including micro ops) simulated 1410515SN/Asystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SN/Asystem.clk_domain.clock 1000 # Clock period in ticks 1611860Sandreas.hansson@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 1711860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.dtb.walker 487168 # Number of bytes read from this memory 1811860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.itb.walker 439168 # Number of bytes read from this memory 1911860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 5588020 # Number of bytes read from this memory 2011860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 87025992 # Number of bytes read from this memory 2111860Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 439360 # Number of bytes read from this memory 2211860Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 93979708 # Number of bytes read from this memory 2311860Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 5588020 # Number of instructions bytes read from this memory 2411860Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 5588020 # Number of instructions bytes read from this memory 2511860Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 115462912 # Number of bytes written to this memory 2610585SN/Asystem.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory 2711860Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 115483492 # Number of bytes written to this memory 2811860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.dtb.walker 7612 # Number of read requests responded to by this memory 2911860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.itb.walker 6862 # Number of read requests responded to by this memory 3011860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 91720 # Number of read requests responded to by this memory 3111860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 1359794 # Number of read requests responded to by this memory 3211860Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 6865 # Number of read requests responded to by this memory 3311860Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1472853 # Number of read requests responded to by this memory 3411860Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 1804108 # Number of write requests responded to by this memory 3510585SN/Asystem.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory 3611860Sandreas.hansson@arm.comsystem.physmem.num_writes::total 1806681 # Number of write requests responded to by this memory 3711860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.dtb.walker 9539 # Total read bandwidth from this memory (bytes/s) 3811860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.itb.walker 8599 # Total read bandwidth from this memory (bytes/s) 3911860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 109416 # Total read bandwidth from this memory (bytes/s) 4011860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 1704016 # Total read bandwidth from this memory (bytes/s) 4111860Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 8603 # Total read bandwidth from this memory (bytes/s) 4211860Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1840174 # Total read bandwidth from this memory (bytes/s) 4311860Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 109416 # Instruction read bandwidth from this memory (bytes/s) 4411860Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 109416 # Instruction read bandwidth from this memory (bytes/s) 4511860Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 2260827 # Write bandwidth from this memory (bytes/s) 4611860Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s) 4711860Sandreas.hansson@arm.comsystem.physmem.bw_write::total 2261230 # Write bandwidth from this memory (bytes/s) 4811860Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 2260827 # Total bandwidth to/from this memory (bytes/s) 4911860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.dtb.walker 9539 # Total bandwidth to/from this memory (bytes/s) 5011860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.itb.walker 8599 # Total bandwidth to/from this memory (bytes/s) 5111860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 109416 # Total bandwidth to/from this memory (bytes/s) 5211860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 1704419 # Total bandwidth to/from this memory (bytes/s) 5311860Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 8603 # Total bandwidth to/from this memory (bytes/s) 5411860Sandreas.hansson@arm.comsystem.physmem.bw_total::total 4101404 # Total bandwidth to/from this memory (bytes/s) 5511860Sandreas.hansson@arm.comsystem.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 5610515SN/Asystem.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory 5710515SN/Asystem.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 5810515SN/Asystem.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory 5910515SN/Asystem.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory 6010515SN/Asystem.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory 6110515SN/Asystem.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory 6210515SN/Asystem.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 6310515SN/Asystem.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory 6410515SN/Asystem.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s) 6510515SN/Asystem.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 6610515SN/Asystem.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s) 6710515SN/Asystem.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s) 6810515SN/Asystem.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s) 6910515SN/Asystem.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) 7010515SN/Asystem.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 7110515SN/Asystem.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) 7211860Sandreas.hansson@arm.comsystem.realview.vram.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 7311860Sandreas.hansson@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 7411860Sandreas.hansson@arm.comsystem.bridge.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 7510585SN/Asystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 7610585SN/Asystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 7710585SN/Asystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 7810585SN/Asystem.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 7910585SN/Asystem.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 8010585SN/Asystem.cf0.dma_write_txs 1669 # Number of DMA write transactions. 8110585SN/Asystem.cpu_clk_domain.clock 500 # Clock period in ticks 8211860Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 8310628SN/Asystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 8410628SN/Asystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 8510628SN/Asystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 8610628SN/Asystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 8710628SN/Asystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 8810628SN/Asystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 8910628SN/Asystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 9010628SN/Asystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 9110585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 9210585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 9310585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 9410585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 9510585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 9610585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 9710585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 9810585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 9910585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 10010585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 10110585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 10210585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 10310585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 10410585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 10510585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 10610585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 10710585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 10810585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 10910585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 11010585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 11110585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 11211860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 11311860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walks 297729 # Table walker walks requested 11411860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksLong 297729 # Table walker walks initiated with long descriptors 11511860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::samples 297729 # Table walker wait (enqueue to first request) latency 11611860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::0 297729 100.00% 100.00% # Table walker wait (enqueue to first request) latency 11711860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::total 297729 # Table walker wait (enqueue to first request) latency 11811860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::samples 3646000 # Table walker pending requests distribution 11911860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::0 3646000 100.00% 100.00% # Table walker pending requests distribution 12011860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::total 3646000 # Table walker pending requests distribution 12111860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkPageSizes::4K 228847 88.79% 88.79% # Table walker page sizes translated 12211860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkPageSizes::2M 28897 11.21% 100.00% # Table walker page sizes translated 12311860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkPageSizes::total 257744 # Table walker page sizes translated 12411860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 297729 # Table walker requests started/completed, data/inst 12510628SN/Asystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 12611860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 297729 # Table walker requests started/completed, data/inst 12711860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 257744 # Table walker requests started/completed, data/inst 12810628SN/Asystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 12911860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 257744 # Table walker requests started/completed, data/inst 13011860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 555473 # Table walker requests started/completed, data/inst 13110585SN/Asystem.cpu.dtb.inst_hits 0 # ITB inst hits 13210585SN/Asystem.cpu.dtb.inst_misses 0 # ITB inst misses 13311860Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 192113611 # DTB read hits 13411860Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses 218086 # DTB read misses 13511860Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 176013555 # DTB write hits 13611860Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 79643 # DTB write misses 13710585SN/Asystem.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 13810585SN/Asystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 13911860Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 53573 # Number of times TLB was flushed by MVA & ASID 14011860Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_asid 1171 # Number of times TLB was flushed by ASID 14111860Sandreas.hansson@arm.comsystem.cpu.dtb.flush_entries 85167 # Number of entries that have been flushed from TLB 14210585SN/Asystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 14311860Sandreas.hansson@arm.comsystem.cpu.dtb.prefetch_faults 10256 # Number of TLB faults due to prefetch 14410585SN/Asystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 14511860Sandreas.hansson@arm.comsystem.cpu.dtb.perms_faults 22356 # Number of TLB faults due to permissions restrictions 14611860Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 192331697 # DTB read accesses 14711860Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 176093198 # DTB write accesses 14810585SN/Asystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 14911860Sandreas.hansson@arm.comsystem.cpu.dtb.hits 368127166 # DTB hits 15011860Sandreas.hansson@arm.comsystem.cpu.dtb.misses 297729 # DTB misses 15111860Sandreas.hansson@arm.comsystem.cpu.dtb.accesses 368424895 # DTB accesses 15211860Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 15310628SN/Asystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 15410628SN/Asystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 15510628SN/Asystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 15610628SN/Asystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 15710628SN/Asystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 15810628SN/Asystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 15910628SN/Asystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 16010628SN/Asystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 16110585SN/Asystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 16210585SN/Asystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 16310585SN/Asystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 16410585SN/Asystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 16510585SN/Asystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 16610585SN/Asystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 16710585SN/Asystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 16810585SN/Asystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 16910585SN/Asystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 17010585SN/Asystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 17110585SN/Asystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 17210585SN/Asystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 17310585SN/Asystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 17410585SN/Asystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 17510585SN/Asystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 17610585SN/Asystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 17710585SN/Asystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 17810585SN/Asystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 17910585SN/Asystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 18010585SN/Asystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 18110585SN/Asystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 18211860Sandreas.hansson@arm.comsystem.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 18311860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walks 128928 # Table walker walks requested 18411860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksLong 128928 # Table walker walks initiated with long descriptors 18511860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::samples 128928 # Table walker wait (enqueue to first request) latency 18611860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::0 128928 100.00% 100.00% # Table walker wait (enqueue to first request) latency 18711860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::total 128928 # Table walker wait (enqueue to first request) latency 18811860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::samples 3644500 # Table walker pending requests distribution 18911860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::0 3644500 100.00% 100.00% # Table walker pending requests distribution 19011860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::total 3644500 # Table walker pending requests distribution 19111860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkPageSizes::4K 115252 99.04% 99.04% # Table walker page sizes translated 19211860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkPageSizes::2M 1122 0.96% 100.00% # Table walker page sizes translated 19311860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkPageSizes::total 116374 # Table walker page sizes translated 19410628SN/Asystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 19511860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 128928 # Table walker requests started/completed, data/inst 19611860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 128928 # Table walker requests started/completed, data/inst 19710628SN/Asystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 19811860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 116374 # Table walker requests started/completed, data/inst 19911860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 116374 # Table walker requests started/completed, data/inst 20011860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 245302 # Table walker requests started/completed, data/inst 20111860Sandreas.hansson@arm.comsystem.cpu.itb.inst_hits 935011975 # ITB inst hits 20211860Sandreas.hansson@arm.comsystem.cpu.itb.inst_misses 128928 # ITB inst misses 20310585SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 20410585SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 20510585SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 20610585SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 20710585SN/Asystem.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 20810585SN/Asystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 20911860Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_mva_asid 53573 # Number of times TLB was flushed by MVA & ASID 21011860Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_asid 1171 # Number of times TLB was flushed by ASID 21111860Sandreas.hansson@arm.comsystem.cpu.itb.flush_entries 59711 # Number of entries that have been flushed from TLB 21210585SN/Asystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 21310585SN/Asystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 21410585SN/Asystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 21510585SN/Asystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 21610585SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 21710585SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 21811860Sandreas.hansson@arm.comsystem.cpu.itb.inst_accesses 935140903 # ITB inst accesses 21911860Sandreas.hansson@arm.comsystem.cpu.itb.hits 935011975 # DTB hits 22011860Sandreas.hansson@arm.comsystem.cpu.itb.misses 128928 # DTB misses 22111860Sandreas.hansson@arm.comsystem.cpu.itb.accesses 935140903 # DTB accesses 22211860Sandreas.hansson@arm.comsystem.cpu.numPwrStateTransitions 33906 # Number of power state transitions 22311860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::samples 16953 # Distribution of time spent in the clock gated state 22411860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::mean 2979611399.652038 # Distribution of time spent in the clock gated state 22511860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::stdev 59761128093.250465 # Distribution of time spent in the clock gated state 22611860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::underflows 7631 45.01% 45.01% # Distribution of time spent in the clock gated state 22711860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::1000-5e+10 9287 54.78% 99.79% # Distribution of time spent in the clock gated state 22811530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::5e+10-1e+11 4 0.02% 99.82% # Distribution of time spent in the clock gated state 22911530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.84% # Distribution of time spent in the clock gated state 23011530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state 23111530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state 23211860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::2.5e+11-3e+11 3 0.02% 99.88% # Distribution of time spent in the clock gated state 23311860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 23411530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 23511860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 23611530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state 23711570SCurtis.Dunham@arm.comsystem.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 23811860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::max_value 1988782908468 # Distribution of time spent in the clock gated state 23911860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::total 16953 # Distribution of time spent in the clock gated state 24011860Sandreas.hansson@arm.comsystem.cpu.pwrStateResidencyTicks::ON 557750343699 # Cumulative time (in ticks) in various power states 24111860Sandreas.hansson@arm.comsystem.cpu.pwrStateResidencyTicks::CLK_GATED 50513352058301 # Cumulative time (in ticks) in various power states 24211860Sandreas.hansson@arm.comsystem.cpu.numCycles 102142221758 # number of cpu cycles simulated 24310585SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 24410585SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 24511167Sjthestness@gmail.comsystem.cpu.kern.inst.arm 0 # number of arm instructions executed 24611860Sandreas.hansson@arm.comsystem.cpu.kern.inst.quiesce 16953 # number of quiesce instructions executed 24711860Sandreas.hansson@arm.comsystem.cpu.committedInsts 934475925 # Number of instructions committed 24811860Sandreas.hansson@arm.comsystem.cpu.committedOps 1114831373 # Number of ops (including micro ops) committed 24911860Sandreas.hansson@arm.comsystem.cpu.num_int_alu_accesses 1036744712 # Number of integer alu accesses 25011860Sandreas.hansson@arm.comsystem.cpu.num_fp_alu_accesses 878021 # Number of float alu accesses 25111860Sandreas.hansson@arm.comsystem.cpu.num_func_calls 59056085 # number of times a function call or return occured 25211860Sandreas.hansson@arm.comsystem.cpu.num_conditional_control_insts 135851428 # number of instructions that are conditional controls 25311860Sandreas.hansson@arm.comsystem.cpu.num_int_insts 1036744712 # number of integer instructions 25411860Sandreas.hansson@arm.comsystem.cpu.num_fp_insts 878021 # number of float instructions 25511860Sandreas.hansson@arm.comsystem.cpu.num_int_register_reads 1380118426 # number of times the integer registers were read 25611860Sandreas.hansson@arm.comsystem.cpu.num_int_register_writes 809399347 # number of times the integer registers were written 25711860Sandreas.hansson@arm.comsystem.cpu.num_fp_register_reads 1413239 # number of times the floating registers were read 25811860Sandreas.hansson@arm.comsystem.cpu.num_fp_register_writes 747664 # number of times the floating registers were written 25911860Sandreas.hansson@arm.comsystem.cpu.num_cc_register_reads 207723168 # number of times the CC registers were read 26011860Sandreas.hansson@arm.comsystem.cpu.num_cc_register_writes 207152857 # number of times the CC registers were written 26111860Sandreas.hansson@arm.comsystem.cpu.num_mem_refs 368379179 # number of memory refs 26211860Sandreas.hansson@arm.comsystem.cpu.num_load_insts 192305014 # Number of load instructions 26311860Sandreas.hansson@arm.comsystem.cpu.num_store_insts 176074165 # Number of store instructions 26411860Sandreas.hansson@arm.comsystem.cpu.num_idle_cycles 101026720885.444443 # Number of idle cycles 26511860Sandreas.hansson@arm.comsystem.cpu.num_busy_cycles 1115500872.555553 # Number of busy cycles 26611860Sandreas.hansson@arm.comsystem.cpu.not_idle_fraction 0.010921 # Percentage of non-idle cycles 26711860Sandreas.hansson@arm.comsystem.cpu.idle_fraction 0.989079 # Percentage of idle cycles 26811860Sandreas.hansson@arm.comsystem.cpu.Branches 206489174 # Number of branches fetched 26910585SN/Asystem.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 27011860Sandreas.hansson@arm.comsystem.cpu.op_class::IntAlu 744480688 66.74% 66.74% # Class of executed instruction 27111860Sandreas.hansson@arm.comsystem.cpu.op_class::IntMult 2418794 0.22% 66.96% # Class of executed instruction 27211860Sandreas.hansson@arm.comsystem.cpu.op_class::IntDiv 103036 0.01% 66.97% # Class of executed instruction 27311860Sandreas.hansson@arm.comsystem.cpu.op_class::FloatAdd 8 0.00% 66.97% # Class of executed instruction 27411860Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCmp 13 0.00% 66.97% # Class of executed instruction 27511860Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCvt 21 0.00% 66.97% # Class of executed instruction 27611860Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMult 0 0.00% 66.97% # Class of executed instruction 27711860Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMultAcc 0 0.00% 66.97% # Class of executed instruction 27811860Sandreas.hansson@arm.comsystem.cpu.op_class::FloatDiv 0 0.00% 66.97% # Class of executed instruction 27911860Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMisc 106782 0.01% 66.98% # Class of executed instruction 28011860Sandreas.hansson@arm.comsystem.cpu.op_class::FloatSqrt 0 0.00% 66.98% # Class of executed instruction 28111860Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAdd 0 0.00% 66.98% # Class of executed instruction 28211860Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAddAcc 0 0.00% 66.98% # Class of executed instruction 28311860Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAlu 0 0.00% 66.98% # Class of executed instruction 28411860Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCmp 0 0.00% 66.98% # Class of executed instruction 28511860Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCvt 0 0.00% 66.98% # Class of executed instruction 28611860Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMisc 0 0.00% 66.98% # Class of executed instruction 28711860Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMult 0 0.00% 66.98% # Class of executed instruction 28811860Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMultAcc 0 0.00% 66.98% # Class of executed instruction 28911860Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShift 0 0.00% 66.98% # Class of executed instruction 29011860Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShiftAcc 0 0.00% 66.98% # Class of executed instruction 29111860Sandreas.hansson@arm.comsystem.cpu.op_class::SimdSqrt 0 0.00% 66.98% # Class of executed instruction 29211860Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAdd 0 0.00% 66.98% # Class of executed instruction 29311860Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAlu 0 0.00% 66.98% # Class of executed instruction 29411860Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCmp 0 0.00% 66.98% # Class of executed instruction 29511860Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCvt 0 0.00% 66.98% # Class of executed instruction 29611860Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatDiv 0 0.00% 66.98% # Class of executed instruction 29711860Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMisc 0 0.00% 66.98% # Class of executed instruction 29811860Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMult 0 0.00% 66.98% # Class of executed instruction 29911860Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 66.98% # Class of executed instruction 30011860Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatSqrt 0 0.00% 66.98% # Class of executed instruction 30111860Sandreas.hansson@arm.comsystem.cpu.op_class::MemRead 192192210 17.23% 84.21% # Class of executed instruction 30211860Sandreas.hansson@arm.comsystem.cpu.op_class::MemWrite 175415772 15.73% 99.93% # Class of executed instruction 30311860Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMemRead 112804 0.01% 99.94% # Class of executed instruction 30411860Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMemWrite 658393 0.06% 100.00% # Class of executed instruction 30510585SN/Asystem.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 30610585SN/Asystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 30711860Sandreas.hansson@arm.comsystem.cpu.op_class::total 1115488522 # Class of executed instruction 30811860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 30911860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 12292096 # number of replacements 31011860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 511.999911 # Cycle average of tags in use 31111860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 356005277 # Total number of references to valid blocks. 31211860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 12292608 # Sample count of references to valid blocks. 31311860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 28.960923 # Average number of references to valid blocks. 31411860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 13850500 # Cycle when the warmup percentage was hit. 31511860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.999911 # Average occupied blocks per requestor 31611860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 1.000000 # Average percentage of cache occupancy 31711860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 1.000000 # Average percentage of cache occupancy 31810585SN/Asystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 31911860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 203 # Occupied blocks per task id 32011860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 292 # Occupied blocks per task id 32111860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id 32210585SN/Asystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 32311860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 1485484203 # Number of tag accesses 32411860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 1485484203 # Number of data accesses 32511860Sandreas.hansson@arm.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 32611860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 178905891 # number of ReadReq hits 32711860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 178905891 # number of ReadReq hits 32811860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 166844782 # number of WriteReq hits 32911860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 166844782 # number of WriteReq hits 33011860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 437201 # number of SoftPFReq hits 33111860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 437201 # number of SoftPFReq hits 33211860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_hits::cpu.data 338801 # number of WriteLineReq hits 33311860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_hits::total 338801 # number of WriteLineReq hits 33411860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 4589501 # number of LoadLockedReq hits 33511860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 4589501 # number of LoadLockedReq hits 33611860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 4852460 # number of StoreCondReq hits 33711860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 4852460 # number of StoreCondReq hits 33811860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 346089474 # number of demand (read+write) hits 33911860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 346089474 # number of demand (read+write) hits 34011860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 346526675 # number of overall hits 34111860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 346526675 # number of overall hits 34211860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 6353340 # number of ReadReq misses 34311860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 6353340 # number of ReadReq misses 34411860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 2735988 # number of WriteReq misses 34511860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 2735988 # number of WriteReq misses 34611860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 1721890 # number of SoftPFReq misses 34711860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 1721890 # number of SoftPFReq misses 34811860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_misses::cpu.data 1253245 # number of WriteLineReq misses 34911860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_misses::total 1253245 # number of WriteLineReq misses 35011860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 264796 # number of LoadLockedReq misses 35111860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 264796 # number of LoadLockedReq misses 35210585SN/Asystem.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses 35310585SN/Asystem.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses 35411860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 10342573 # number of demand (read+write) misses 35511860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 10342573 # number of demand (read+write) misses 35611860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 12064463 # number of overall misses 35711860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 12064463 # number of overall misses 35811860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 185259231 # number of ReadReq accesses(hits+misses) 35911860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 185259231 # number of ReadReq accesses(hits+misses) 36011860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 169580770 # number of WriteReq accesses(hits+misses) 36111860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 169580770 # number of WriteReq accesses(hits+misses) 36211860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 2159091 # number of SoftPFReq accesses(hits+misses) 36311860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 2159091 # number of SoftPFReq accesses(hits+misses) 36411860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_accesses::cpu.data 1592046 # number of WriteLineReq accesses(hits+misses) 36511860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_accesses::total 1592046 # number of WriteLineReq accesses(hits+misses) 36611860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 4854297 # number of LoadLockedReq accesses(hits+misses) 36711860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 4854297 # number of LoadLockedReq accesses(hits+misses) 36811860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 4852461 # number of StoreCondReq accesses(hits+misses) 36911860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 4852461 # number of StoreCondReq accesses(hits+misses) 37011860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 356432047 # number of demand (read+write) accesses 37111860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 356432047 # number of demand (read+write) accesses 37211860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 358591138 # number of overall (read+write) accesses 37311860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 358591138 # number of overall (read+write) accesses 37411860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.034294 # miss rate for ReadReq accesses 37511860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.034294 # miss rate for ReadReq accesses 37611860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.016134 # miss rate for WriteReq accesses 37711860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.016134 # miss rate for WriteReq accesses 37811860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.797507 # miss rate for SoftPFReq accesses 37911860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.797507 # miss rate for SoftPFReq accesses 38011860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787191 # miss rate for WriteLineReq accesses 38111860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_miss_rate::total 0.787191 # miss rate for WriteLineReq accesses 38211860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.054549 # miss rate for LoadLockedReq accesses 38311860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.054549 # miss rate for LoadLockedReq accesses 38410585SN/Asystem.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses 38510585SN/Asystem.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses 38611860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.029017 # miss rate for demand accesses 38711860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.029017 # miss rate for demand accesses 38811860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.033644 # miss rate for overall accesses 38911860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.033644 # miss rate for overall accesses 39010585SN/Asystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 39110585SN/Asystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 39210585SN/Asystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 39310585SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 39410585SN/Asystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 39510585SN/Asystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 39611860Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 9441403 # number of writebacks 39711860Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 9441403 # number of writebacks 39811860Sandreas.hansson@arm.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 39911860Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 14554443 # number of replacements 40011860Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 511.984790 # Cycle average of tags in use 40111860Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 920573389 # Total number of references to valid blocks. 40211860Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 14554955 # Sample count of references to valid blocks. 40311860Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 63.248110 # Average number of references to valid blocks. 40411860Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 6040365000 # Cycle when the warmup percentage was hit. 40511860Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 511.984790 # Average occupied blocks per requestor 40610585SN/Asystem.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy 40710585SN/Asystem.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy 40810585SN/Asystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 40911860Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 190 # Occupied blocks per task id 41011860Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id 41111860Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id 41210585SN/Asystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 41311860Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 949683309 # Number of tag accesses 41411860Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 949683309 # Number of data accesses 41511860Sandreas.hansson@arm.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 41611860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 920573389 # number of ReadReq hits 41711860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 920573389 # number of ReadReq hits 41811860Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 920573389 # number of demand (read+write) hits 41911860Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 920573389 # number of demand (read+write) hits 42011860Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 920573389 # number of overall hits 42111860Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 920573389 # number of overall hits 42211860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 14554960 # number of ReadReq misses 42311860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 14554960 # number of ReadReq misses 42411860Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 14554960 # number of demand (read+write) misses 42511860Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 14554960 # number of demand (read+write) misses 42611860Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 14554960 # number of overall misses 42711860Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 14554960 # number of overall misses 42811860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 935128349 # number of ReadReq accesses(hits+misses) 42911860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 935128349 # number of ReadReq accesses(hits+misses) 43011860Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 935128349 # number of demand (read+write) accesses 43111860Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 935128349 # number of demand (read+write) accesses 43211860Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 935128349 # number of overall (read+write) accesses 43311860Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 935128349 # number of overall (read+write) accesses 43411860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015565 # miss rate for ReadReq accesses 43511860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.015565 # miss rate for ReadReq accesses 43611860Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.015565 # miss rate for demand accesses 43711860Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.015565 # miss rate for demand accesses 43811860Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.015565 # miss rate for overall accesses 43911860Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.015565 # miss rate for overall accesses 44010585SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 44110585SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 44210585SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 44310585SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 44410585SN/Asystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 44510585SN/Asystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 44611860Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::writebacks 14554443 # number of writebacks 44711860Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::total 14554443 # number of writebacks 44811860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 44911860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 1939529 # number of replacements 45011860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 65410.509732 # Cycle average of tags in use 45111860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 51207751 # Total number of references to valid blocks. 45211860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 2002275 # Sample count of references to valid blocks. 45311860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 25.574784 # Average number of references to valid blocks. 45411860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 373950000 # Cycle when the warmup percentage was hit. 45511860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 9607.000136 # Average occupied blocks per requestor 45611860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 373.212421 # Average occupied blocks per requestor 45711860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 441.072045 # Average occupied blocks per requestor 45811860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 6073.861347 # Average occupied blocks per requestor 45911860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 48915.363784 # Average occupied blocks per requestor 46011860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.146591 # Average percentage of cache occupancy 46111860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005695 # Average percentage of cache occupancy 46211860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006730 # Average percentage of cache occupancy 46311860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.092680 # Average percentage of cache occupancy 46411860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.746389 # Average percentage of cache occupancy 46511860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.998085 # Average percentage of cache occupancy 46611860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1023 323 # Occupied blocks per task id 46711860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 62423 # Occupied blocks per task id 46811860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1023::4 323 # Occupied blocks per task id 46911860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id 47011860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 336 # Occupied blocks per task id 47111860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 1416 # Occupied blocks per task id 47211860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 5058 # Occupied blocks per task id 47311860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 55500 # Occupied blocks per task id 47411860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1023 0.004929 # Percentage of cache occupancy per task id 47511860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.952499 # Percentage of cache occupancy per task id 47611860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 439130926 # Number of tag accesses 47711860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 439130926 # Number of data accesses 47811860Sandreas.hansson@arm.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 47911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 564464 # number of ReadReq hits 48011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.itb.walker 243894 # number of ReadReq hits 48111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 808358 # number of ReadReq hits 48211860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 9441403 # number of WritebackDirty hits 48311860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 9441403 # number of WritebackDirty hits 48411860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 14552867 # number of WritebackClean hits 48511860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 14552867 # number of WritebackClean hits 48611860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 32762 # number of UpgradeReq hits 48711860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 32762 # number of UpgradeReq hits 48811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 1717134 # number of ReadExReq hits 48911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 1717134 # number of ReadExReq hits 49011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14467928 # number of ReadCleanReq hits 49111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 14467928 # number of ReadCleanReq hits 49211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 7961263 # number of ReadSharedReq hits 49311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 7961263 # number of ReadSharedReq hits 49411860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_hits::cpu.data 682418 # number of InvalidateReq hits 49511860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_hits::total 682418 # number of InvalidateReq hits 49611860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.dtb.walker 564464 # number of demand (read+write) hits 49711860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.itb.walker 243894 # number of demand (read+write) hits 49811860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 14467928 # number of demand (read+write) hits 49911860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 9678397 # number of demand (read+write) hits 50011860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 24954683 # number of demand (read+write) hits 50111860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.dtb.walker 564464 # number of overall hits 50211860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.itb.walker 243894 # number of overall hits 50311860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 14467928 # number of overall hits 50411860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 9678397 # number of overall hits 50511860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 24954683 # number of overall hits 50611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7612 # number of ReadReq misses 50711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6862 # number of ReadReq misses 50811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 14474 # number of ReadReq misses 50911860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 3878 # number of UpgradeReq misses 51011860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 3878 # number of UpgradeReq misses 51110585SN/Asystem.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses 51210585SN/Asystem.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses 51311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 982214 # number of ReadExReq misses 51411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 982214 # number of ReadExReq misses 51511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 87032 # number of ReadCleanReq misses 51611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 87032 # number of ReadCleanReq misses 51711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 378763 # number of ReadSharedReq misses 51811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 378763 # number of ReadSharedReq misses 51911860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_misses::cpu.data 570827 # number of InvalidateReq misses 52011860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_misses::total 570827 # number of InvalidateReq misses 52111860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.dtb.walker 7612 # number of demand (read+write) misses 52211860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.itb.walker 6862 # number of demand (read+write) misses 52311860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 87032 # number of demand (read+write) misses 52411860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 1360977 # number of demand (read+write) misses 52511860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 1462483 # number of demand (read+write) misses 52611860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.dtb.walker 7612 # number of overall misses 52711860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.itb.walker 6862 # number of overall misses 52811860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 87032 # number of overall misses 52911860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 1360977 # number of overall misses 53011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 1462483 # number of overall misses 53111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 572076 # number of ReadReq accesses(hits+misses) 53211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 250756 # number of ReadReq accesses(hits+misses) 53311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 822832 # number of ReadReq accesses(hits+misses) 53411860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 9441403 # number of WritebackDirty accesses(hits+misses) 53511860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 9441403 # number of WritebackDirty accesses(hits+misses) 53611860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 14552867 # number of WritebackClean accesses(hits+misses) 53711860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 14552867 # number of WritebackClean accesses(hits+misses) 53811860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 36640 # number of UpgradeReq accesses(hits+misses) 53911860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 36640 # number of UpgradeReq accesses(hits+misses) 54010585SN/Asystem.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) 54110585SN/Asystem.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) 54211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 2699348 # number of ReadExReq accesses(hits+misses) 54311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 2699348 # number of ReadExReq accesses(hits+misses) 54411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14554960 # number of ReadCleanReq accesses(hits+misses) 54511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 14554960 # number of ReadCleanReq accesses(hits+misses) 54611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 8340026 # number of ReadSharedReq accesses(hits+misses) 54711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 8340026 # number of ReadSharedReq accesses(hits+misses) 54811860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_accesses::cpu.data 1253245 # number of InvalidateReq accesses(hits+misses) 54911860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_accesses::total 1253245 # number of InvalidateReq accesses(hits+misses) 55011860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.dtb.walker 572076 # number of demand (read+write) accesses 55111860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.itb.walker 250756 # number of demand (read+write) accesses 55211860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 14554960 # number of demand (read+write) accesses 55311860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 11039374 # number of demand (read+write) accesses 55411860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 26417166 # number of demand (read+write) accesses 55511860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.dtb.walker 572076 # number of overall (read+write) accesses 55611860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.itb.walker 250756 # number of overall (read+write) accesses 55711860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 14554960 # number of overall (read+write) accesses 55811860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 11039374 # number of overall (read+write) accesses 55911860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 26417166 # number of overall (read+write) accesses 56011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.013306 # miss rate for ReadReq accesses 56111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.027365 # miss rate for ReadReq accesses 56211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.017590 # miss rate for ReadReq accesses 56311860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.105841 # miss rate for UpgradeReq accesses 56411860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.105841 # miss rate for UpgradeReq accesses 56510585SN/Asystem.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 56610585SN/Asystem.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 56711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.363871 # miss rate for ReadExReq accesses 56811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.363871 # miss rate for ReadExReq accesses 56911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005980 # miss rate for ReadCleanReq accesses 57011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005980 # miss rate for ReadCleanReq accesses 57111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.045415 # miss rate for ReadSharedReq accesses 57211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.045415 # miss rate for ReadSharedReq accesses 57311860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.455479 # miss rate for InvalidateReq accesses 57411860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_miss_rate::total 0.455479 # miss rate for InvalidateReq accesses 57511860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.013306 # miss rate for demand accesses 57611860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.027365 # miss rate for demand accesses 57711860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.005980 # miss rate for demand accesses 57811860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.123284 # miss rate for demand accesses 57911860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.055361 # miss rate for demand accesses 58011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.013306 # miss rate for overall accesses 58111860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.027365 # miss rate for overall accesses 58211860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.005980 # miss rate for overall accesses 58311860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.123284 # miss rate for overall accesses 58411860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.055361 # miss rate for overall accesses 58510585SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 58610585SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 58710585SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 58810585SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 58910585SN/Asystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 59010585SN/Asystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 59111860Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 1697477 # number of writebacks 59211860Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 1697477 # number of writebacks 59311860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 54350593 # Total number of requests made to the snoop filter. 59411860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 27503016 # Number of requests hitting in the snoop filter with a single holder of the requested data. 59511860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 1759 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 59611860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 2697 # Total number of snoops made to the snoop filter. 59711860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 2697 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 59811138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 59911860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 60011860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 1286731 # Transaction distribution 60111860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 24181717 # Transaction distribution 60211860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteReq 33519 # Transaction distribution 60311860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteResp 33519 # Transaction distribution 60411860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 9441403 # Transaction distribution 60511860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 14554443 # Transaction distribution 60611860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 2850693 # Transaction distribution 60711860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 36640 # Transaction distribution 60810585SN/Asystem.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution 60911860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 36641 # Transaction distribution 61011860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 2699348 # Transaction distribution 61111860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 2699348 # Transaction distribution 61211860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 14554960 # Transaction distribution 61311860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 8340026 # Transaction distribution 61411860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::InvalidateReq 1253245 # Transaction distribution 61511860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::InvalidateResp 1253245 # Transaction distribution 61611860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43673813 # Packet count per connected master and slave (bytes) 61711860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 37084586 # Packet count per connected master and slave (bytes) 61811860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 770772 # Packet count per connected master and slave (bytes) 61911860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1726308 # Packet count per connected master and slave (bytes) 62011860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 83255479 # Packet count per connected master and slave (bytes) 62111860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1863020692 # Cumulative packet size per connected master and slave (bytes) 62211860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1310959042 # Cumulative packet size per connected master and slave (bytes) 62311860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3083088 # Cumulative packet size per connected master and slave (bytes) 62411860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6905232 # Cumulative packet size per connected master and slave (bytes) 62511860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 3183968054 # Cumulative packet size per connected master and slave (bytes) 62611860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 1977015 # Total snoops (count) 62711860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopTraffic 108689536 # Total snoop traffic (bytes) 62811860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 57027218 # Request fanout histogram 62911860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.010978 # Request fanout histogram 63011860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.104200 # Request fanout histogram 63110585SN/Asystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 63211860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 56401167 98.90% 98.90% # Request fanout histogram 63311860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 626051 1.10% 100.00% # Request fanout histogram 63411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 63510585SN/Asystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 63611138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 63711138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 63811860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 57027218 # Request fanout histogram 63911860Sandreas.hansson@arm.comsystem.iobus.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 64011860Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 40168 # Transaction distribution 64111860Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 40168 # Transaction distribution 64211860Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 136429 # Transaction distribution 64311860Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 136429 # Transaction distribution 64411860Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47254 # Packet count per connected master and slave (bytes) 64510585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 64611245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 64710585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 64810585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 64910585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 65010585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 65110585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 65210585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 65310585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 65410585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 65510585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 65610585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 65711860Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122136 # Packet count per connected master and slave (bytes) 65811860Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230978 # Packet count per connected master and slave (bytes) 65911860Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 230978 # Packet count per connected master and slave (bytes) 66010585SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 66110585SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 66211860Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 353194 # Packet count per connected master and slave (bytes) 66311860Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47274 # Cumulative packet size per connected master and slave (bytes) 66410585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 66511245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 66610585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 66710585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 66810585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 66910585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 67010585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 67110585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 67210585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 67310585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 67410585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 67510585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 67611860Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 155266 # Cumulative packet size per connected master and slave (bytes) 67711860Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334344 # Cumulative packet size per connected master and slave (bytes) 67811860Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7334344 # Cumulative packet size per connected master and slave (bytes) 67910585SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 68010585SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 68111860Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 7491696 # Cumulative packet size per connected master and slave (bytes) 68211860Sandreas.hansson@arm.comsystem.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 68311860Sandreas.hansson@arm.comsystem.iocache.tags.replacements 115471 # number of replacements 68411860Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 10.402763 # Cycle average of tags in use 68510585SN/Asystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 68611860Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 115487 # Sample count of references to valid blocks. 68710585SN/Asystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 68811860Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 13082091783509 # Cycle when the warmup percentage was hit. 68911860Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 3.557357 # Average occupied blocks per requestor 69011860Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 6.845405 # Average occupied blocks per requestor 69111860Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.222335 # Average percentage of cache occupancy 69211860Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.427838 # Average percentage of cache occupancy 69311860Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.650173 # Average percentage of cache occupancy 69410585SN/Asystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 69510585SN/Asystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 69610585SN/Asystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 69711860Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 1039758 # Number of tag accesses 69811860Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 1039758 # Number of data accesses 69911860Sandreas.hansson@arm.comsystem.iocache.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 70010585SN/Asystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 70111860Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ide 8825 # number of ReadReq misses 70211860Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 8862 # number of ReadReq misses 70310585SN/Asystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 70410585SN/Asystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 70510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 70610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 70710585SN/Asystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 70811860Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ide 115489 # number of demand (read+write) misses 70911860Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 115529 # number of demand (read+write) misses 71010585SN/Asystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 71111860Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ide 115489 # number of overall misses 71211860Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 115529 # number of overall misses 71310585SN/Asystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 71411860Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8825 # number of ReadReq accesses(hits+misses) 71511860Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 8862 # number of ReadReq accesses(hits+misses) 71610585SN/Asystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 71710585SN/Asystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 71810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 71910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 72010585SN/Asystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 72111860Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ide 115489 # number of demand (read+write) accesses 72211860Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 115529 # number of demand (read+write) accesses 72310585SN/Asystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 72411860Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 115489 # number of overall (read+write) accesses 72511860Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 115529 # number of overall (read+write) accesses 72610585SN/Asystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 72710585SN/Asystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 72810585SN/Asystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 72910585SN/Asystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 73010585SN/Asystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 73110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 73210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 73310585SN/Asystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 73410585SN/Asystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 73510585SN/Asystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 73610585SN/Asystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 73710585SN/Asystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 73810585SN/Asystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 73910585SN/Asystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 74010585SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 74110585SN/Asystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 74210585SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 74310585SN/Asystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 74410585SN/Asystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 74510585SN/Asystem.iocache.writebacks::writebacks 106631 # number of writebacks 74610585SN/Asystem.iocache.writebacks::total 106631 # number of writebacks 74711860Sandreas.hansson@arm.comsystem.membus.snoop_filter.tot_requests 4206457 # Total number of requests made to the snoop filter. 74811860Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_single_requests 2089632 # Number of requests hitting in the snoop filter with a single holder of the requested data. 74911860Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_multi_requests 3012 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 75011606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 75111606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 75211606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 75311860Sandreas.hansson@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 75411860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 38191 # Transaction distribution 75511860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 527322 # Transaction distribution 75611860Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 33519 # Transaction distribution 75711860Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 33519 # Transaction distribution 75811860Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty 1804108 # Transaction distribution 75911860Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 249631 # Transaction distribution 76011860Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 4439 # Transaction distribution 76110515SN/Asystem.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution 76211860Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 4440 # Transaction distribution 76311860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 981656 # Transaction distribution 76411860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 981656 # Transaction distribution 76511860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 489131 # Transaction distribution 76611860Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 677491 # Transaction distribution 76711860Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 677491 # Transaction distribution 76811860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122136 # Packet count per connected master and slave (bytes) 76910515SN/Asystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) 77011860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6648 # Packet count per connected master and slave (bytes) 77111860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6027224 # Packet count per connected master and slave (bytes) 77211860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 6156066 # Packet count per connected master and slave (bytes) 77311860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346529 # Packet count per connected master and slave (bytes) 77411860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 346529 # Packet count per connected master and slave (bytes) 77511860Sandreas.hansson@arm.comsystem.membus.pkt_count::total 6502595 # Packet count per connected master and slave (bytes) 77611860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155266 # Cumulative packet size per connected master and slave (bytes) 77710515SN/Asystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) 77811860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13296 # Cumulative packet size per connected master and slave (bytes) 77911860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 202241248 # Cumulative packet size per connected master and slave (bytes) 78011860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 202409942 # Cumulative packet size per connected master and slave (bytes) 78111860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7391552 # Cumulative packet size per connected master and slave (bytes) 78211860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7391552 # Cumulative packet size per connected master and slave (bytes) 78311860Sandreas.hansson@arm.comsystem.membus.pkt_size::total 209801494 # Cumulative packet size per connected master and slave (bytes) 78410515SN/Asystem.membus.snoops 0 # Total snoops (count) 78511570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 78611860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 4278167 # Request fanout histogram 78711860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0.008735 # Request fanout histogram 78811860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0.093051 # Request fanout histogram 78910515SN/Asystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 79011860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 4240798 99.13% 99.13% # Request fanout histogram 79111860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 37369 0.87% 100.00% # Request fanout histogram 79210515SN/Asystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 79310515SN/Asystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 79411606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 79510515SN/Asystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 79611860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 4278167 # Request fanout histogram 79711860Sandreas.hansson@arm.comsystem.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 79811860Sandreas.hansson@arm.comsystem.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 79911860Sandreas.hansson@arm.comsystem.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 80011860Sandreas.hansson@arm.comsystem.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 80111860Sandreas.hansson@arm.comsystem.realview.gic.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 80211860Sandreas.hansson@arm.comsystem.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 80311860Sandreas.hansson@arm.comsystem.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 80411239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 80511239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 80611239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 80711239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 80811239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 80911239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 81011860Sandreas.hansson@arm.comsystem.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 81111860Sandreas.hansson@arm.comsystem.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 81210515SN/Asystem.realview.ethernet.txBytes 966 # Bytes Transmitted 81310515SN/Asystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 81410515SN/Asystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 81510515SN/Asystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 81610515SN/Asystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 81710515SN/Asystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 81810515SN/Asystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 81910515SN/Asystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 82010515SN/Asystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 82111860Sandreas.hansson@arm.comsystem.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) 82210515SN/Asystem.realview.ethernet.totPackets 3 # Total Packets 82310515SN/Asystem.realview.ethernet.totBytes 966 # Total Bytes 82410515SN/Asystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 82511860Sandreas.hansson@arm.comsystem.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) 82610515SN/Asystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 82710515SN/Asystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 82810515SN/Asystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 82910515SN/Asystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 83010515SN/Asystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 83110515SN/Asystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 83210515SN/Asystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 83310515SN/Asystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 83410515SN/Asystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 83510515SN/Asystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 83610515SN/Asystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 83710515SN/Asystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 83810515SN/Asystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 83910515SN/Asystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 84010515SN/Asystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 84110515SN/Asystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 84210515SN/Asystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 84310515SN/Asystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 84410515SN/Asystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 84510515SN/Asystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 84610515SN/Asystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 84710515SN/Asystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 84810515SN/Asystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 84910515SN/Asystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 85010515SN/Asystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 85110515SN/Asystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 85210515SN/Asystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 85310515SN/Asystem.realview.ethernet.droppedPackets 0 # number of packets dropped 85411860Sandreas.hansson@arm.comsystem.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 85511860Sandreas.hansson@arm.comsystem.realview.ide.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 85611860Sandreas.hansson@arm.comsystem.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 85711860Sandreas.hansson@arm.comsystem.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 85811860Sandreas.hansson@arm.comsystem.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 85911860Sandreas.hansson@arm.comsystem.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 86011860Sandreas.hansson@arm.comsystem.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 86111239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 86211239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 86311239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 86411239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 86511860Sandreas.hansson@arm.comsystem.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 86611860Sandreas.hansson@arm.comsystem.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 86711860Sandreas.hansson@arm.comsystem.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 86811860Sandreas.hansson@arm.comsystem.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 86911860Sandreas.hansson@arm.comsystem.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 87011860Sandreas.hansson@arm.comsystem.realview.uart.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 87111860Sandreas.hansson@arm.comsystem.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 87211860Sandreas.hansson@arm.comsystem.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 87311860Sandreas.hansson@arm.comsystem.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 87411860Sandreas.hansson@arm.comsystem.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 87511860Sandreas.hansson@arm.comsystem.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 87611860Sandreas.hansson@arm.comsystem.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states 87710515SN/A 87810515SN/A---------- End Simulation Statistics ---------- 879