stats.txt revision 11606
110515SN/A 210515SN/A---------- Begin Simulation Statistics ---------- 311570SCurtis.Dunham@arm.comsim_seconds 47.296282 # Number of seconds simulated 411570SCurtis.Dunham@arm.comsim_ticks 47296281748500 # Number of ticks simulated 511570SCurtis.Dunham@arm.comfinal_tick 47296281748500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711606Sandreas.sandberg@arm.comhost_inst_rate 890958 # Simulator instruction rate (inst/s) 811606Sandreas.sandberg@arm.comhost_op_rate 1048084 # Simulator op (including micro ops) rate (op/s) 911606Sandreas.sandberg@arm.comhost_tick_rate 43128593002 # Simulator tick rate (ticks/s) 1011606Sandreas.sandberg@arm.comhost_mem_usage 697472 # Number of bytes of host memory used 1111606Sandreas.sandberg@arm.comhost_seconds 1096.63 # Real time elapsed on the host 1211570SCurtis.Dunham@arm.comsim_insts 977055082 # Number of instructions simulated 1311570SCurtis.Dunham@arm.comsim_ops 1149364510 # Number of ops (including micro ops) simulated 1410515SN/Asystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SN/Asystem.clk_domain.clock 1000 # Clock period in ticks 1611570SCurtis.Dunham@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1711606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 154816 # Number of bytes read from this memory 1811606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 128128 # Number of bytes read from this memory 1911606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu0.inst 4238644 # Number of bytes read from this memory 2011606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu0.data 35981768 # Number of bytes read from this memory 2111606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 224128 # Number of bytes read from this memory 2211606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu1.itb.walker 222976 # Number of bytes read from this memory 2311606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu1.inst 3009416 # Number of bytes read from this memory 2411606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu1.data 39414640 # Number of bytes read from this memory 2511606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::realview.ide 402560 # Number of bytes read from this memory 2611606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::total 83777076 # Number of bytes read from this memory 2711606Sandreas.sandberg@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 4238644 # Number of instructions bytes read from this memory 2811606Sandreas.sandberg@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 3009416 # Number of instructions bytes read from this memory 2911606Sandreas.sandberg@arm.comsystem.physmem.bytes_inst_read::total 7248060 # Number of instructions bytes read from this memory 3011606Sandreas.sandberg@arm.comsystem.physmem.bytes_written::writebacks 102370496 # Number of bytes written to this memory 3110827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 3210585SN/Asystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3311606Sandreas.sandberg@arm.comsystem.physmem.bytes_written::total 102391080 # Number of bytes written to this memory 3411606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 2419 # Number of read requests responded to by this memory 3511606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu0.itb.walker 2002 # Number of read requests responded to by this memory 3611606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu0.inst 106636 # Number of read requests responded to by this memory 3711606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu0.data 562228 # Number of read requests responded to by this memory 3811606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 3502 # Number of read requests responded to by this memory 3911606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu1.itb.walker 3484 # Number of read requests responded to by this memory 4011606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu1.inst 47129 # Number of read requests responded to by this memory 4111606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu1.data 615870 # Number of read requests responded to by this memory 4211606Sandreas.sandberg@arm.comsystem.physmem.num_reads::realview.ide 6290 # Number of read requests responded to by this memory 4311606Sandreas.sandberg@arm.comsystem.physmem.num_reads::total 1349560 # Number of read requests responded to by this memory 4411606Sandreas.sandberg@arm.comsystem.physmem.num_writes::writebacks 1599539 # Number of write requests responded to by this memory 4510827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 4610585SN/Asystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 4711606Sandreas.sandberg@arm.comsystem.physmem.num_writes::total 1602113 # Number of write requests responded to by this memory 4811606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 3273 # Total read bandwidth from this memory (bytes/s) 4911606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu0.itb.walker 2709 # Total read bandwidth from this memory (bytes/s) 5011606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu0.inst 89619 # Total read bandwidth from this memory (bytes/s) 5111606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu0.data 760774 # Total read bandwidth from this memory (bytes/s) 5211606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 4739 # Total read bandwidth from this memory (bytes/s) 5311606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu1.itb.walker 4714 # Total read bandwidth from this memory (bytes/s) 5411606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu1.inst 63629 # Total read bandwidth from this memory (bytes/s) 5511606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu1.data 833356 # Total read bandwidth from this memory (bytes/s) 5611606Sandreas.sandberg@arm.comsystem.physmem.bw_read::realview.ide 8511 # Total read bandwidth from this memory (bytes/s) 5711606Sandreas.sandberg@arm.comsystem.physmem.bw_read::total 1771325 # Total read bandwidth from this memory (bytes/s) 5811606Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::cpu0.inst 89619 # Instruction read bandwidth from this memory (bytes/s) 5911606Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::cpu1.inst 63629 # Instruction read bandwidth from this memory (bytes/s) 6011606Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::total 153248 # Instruction read bandwidth from this memory (bytes/s) 6111606Sandreas.sandberg@arm.comsystem.physmem.bw_write::writebacks 2164451 # Write bandwidth from this memory (bytes/s) 6211570SCurtis.Dunham@arm.comsystem.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) 6310585SN/Asystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 6411606Sandreas.sandberg@arm.comsystem.physmem.bw_write::total 2164886 # Write bandwidth from this memory (bytes/s) 6511606Sandreas.sandberg@arm.comsystem.physmem.bw_total::writebacks 2164451 # Total bandwidth to/from this memory (bytes/s) 6611606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 3273 # Total bandwidth to/from this memory (bytes/s) 6711606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu0.itb.walker 2709 # Total bandwidth to/from this memory (bytes/s) 6811606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu0.inst 89619 # Total bandwidth to/from this memory (bytes/s) 6911606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu0.data 761209 # Total bandwidth to/from this memory (bytes/s) 7011606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 4739 # Total bandwidth to/from this memory (bytes/s) 7111606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu1.itb.walker 4714 # Total bandwidth to/from this memory (bytes/s) 7211606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu1.inst 63629 # Total bandwidth to/from this memory (bytes/s) 7311606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu1.data 833356 # Total bandwidth to/from this memory (bytes/s) 7411606Sandreas.sandberg@arm.comsystem.physmem.bw_total::realview.ide 8511 # Total bandwidth to/from this memory (bytes/s) 7511606Sandreas.sandberg@arm.comsystem.physmem.bw_total::total 3936211 # Total bandwidth to/from this memory (bytes/s) 7611570SCurtis.Dunham@arm.comsystem.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 7710515SN/Asystem.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 7810515SN/Asystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 7910515SN/Asystem.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 8010515SN/Asystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 8110515SN/Asystem.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 8210515SN/Asystem.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 8310515SN/Asystem.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 8410515SN/Asystem.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 8510515SN/Asystem.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 8610515SN/Asystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 8710515SN/Asystem.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 8810515SN/Asystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 8910515SN/Asystem.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 9010515SN/Asystem.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 9110515SN/Asystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 9210515SN/Asystem.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 9310515SN/Asystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 9410515SN/Asystem.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 9510515SN/Asystem.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 9610515SN/Asystem.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 9710515SN/Asystem.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 9810515SN/Asystem.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 9910515SN/Asystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 10010515SN/Asystem.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 10110515SN/Asystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 10210515SN/Asystem.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 10311570SCurtis.Dunham@arm.comsystem.realview.vram.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 10411570SCurtis.Dunham@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 10511570SCurtis.Dunham@arm.comsystem.bridge.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 10610585SN/Asystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 10710585SN/Asystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 10810585SN/Asystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 10910585SN/Asystem.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 11010585SN/Asystem.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 11110585SN/Asystem.cf0.dma_write_txs 1670 # Number of DMA write transactions. 11210515SN/Asystem.cpu_clk_domain.clock 500 # Clock period in ticks 11311570SCurtis.Dunham@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 11410628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 11510628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 11610628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 11710628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 11810628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 11910628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 12010628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 12110628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 12210585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 12310585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 12410585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 12510585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 12610585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 12710585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 12810585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 12910585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 13010585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 13110585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 13210585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 13310585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 13410585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 13510585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 13610585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 13710585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 13810585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 13910585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 14010585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 14110585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 14210585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 14311570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 14411570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walks 125159 # Table walker walks requested 14511570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksLong 125159 # Table walker walks initiated with long descriptors 14611570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 125159 # Table walker wait (enqueue to first request) latency 14711570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0 125159 100.00% 100.00% # Table walker wait (enqueue to first request) latency 14811570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 125159 # Table walker wait (enqueue to first request) latency 14910628SN/Asystem.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution 15010628SN/Asystem.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution 15110628SN/Asystem.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution 15211570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 96412 89.79% 89.79% # Table walker page sizes translated 15311570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkPageSizes::2M 10963 10.21% 100.00% # Table walker page sizes translated 15411570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 107375 # Table walker page sizes translated 15511570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 125159 # Table walker requests started/completed, data/inst 15610628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 15711570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 125159 # Table walker requests started/completed, data/inst 15811570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107375 # Table walker requests started/completed, data/inst 15910628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 16011570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107375 # Table walker requests started/completed, data/inst 16111570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 232534 # Table walker requests started/completed, data/inst 16210585SN/Asystem.cpu0.dtb.inst_hits 0 # ITB inst hits 16310585SN/Asystem.cpu0.dtb.inst_misses 0 # ITB inst misses 16411570SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_hits 92471463 # DTB read hits 16511570SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_misses 88826 # DTB read misses 16611570SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_hits 85455153 # DTB write hits 16711570SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_misses 36333 # DTB write misses 16810585SN/Asystem.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed 16910585SN/Asystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 17011570SCurtis.Dunham@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 49425 # Number of times TLB was flushed by MVA & ASID 17110585SN/Asystem.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 17211570SCurtis.Dunham@arm.comsystem.cpu0.dtb.flush_entries 36431 # Number of entries that have been flushed from TLB 17310585SN/Asystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 17411570SCurtis.Dunham@arm.comsystem.cpu0.dtb.prefetch_faults 4810 # Number of TLB faults due to prefetch 17510585SN/Asystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 17611570SCurtis.Dunham@arm.comsystem.cpu0.dtb.perms_faults 10399 # Number of TLB faults due to permissions restrictions 17711570SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_accesses 92560289 # DTB read accesses 17811570SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_accesses 85491486 # DTB write accesses 17910585SN/Asystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 18011570SCurtis.Dunham@arm.comsystem.cpu0.dtb.hits 177926616 # DTB hits 18111570SCurtis.Dunham@arm.comsystem.cpu0.dtb.misses 125159 # DTB misses 18211570SCurtis.Dunham@arm.comsystem.cpu0.dtb.accesses 178051775 # DTB accesses 18311570SCurtis.Dunham@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 18410628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 18510628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 18610628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 18710628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 18810628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 18910628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 19010628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 19110628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 19210585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 19310585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 19410585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 19510585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 19610585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 19710585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 19810585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 19910585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 20010585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 20110585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 20210585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 20310585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 20410585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 20510585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 20610585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 20710585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 20810585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 20910585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 21010585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 21110585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 21210585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 21311570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 21411570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walks 61082 # Table walker walks requested 21511570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksLong 61082 # Table walker walks initiated with long descriptors 21611570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 61082 # Table walker wait (enqueue to first request) latency 21711570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkWaitTime::0 61082 100.00% 100.00% # Table walker wait (enqueue to first request) latency 21811570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 61082 # Table walker wait (enqueue to first request) latency 21910628SN/Asystem.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution 22010628SN/Asystem.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution 22110628SN/Asystem.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution 22211570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 54995 98.82% 98.82% # Table walker page sizes translated 22311570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkPageSizes::2M 656 1.18% 100.00% # Table walker page sizes translated 22411570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 55651 # Table walker page sizes translated 22510628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 22611570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61082 # Table walker requests started/completed, data/inst 22711570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 61082 # Table walker requests started/completed, data/inst 22810628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 22911570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55651 # Table walker requests started/completed, data/inst 23011570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 55651 # Table walker requests started/completed, data/inst 23111570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 116733 # Table walker requests started/completed, data/inst 23211570SCurtis.Dunham@arm.comsystem.cpu0.itb.inst_hits 496679820 # ITB inst hits 23311570SCurtis.Dunham@arm.comsystem.cpu0.itb.inst_misses 61082 # ITB inst misses 23410585SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 23510585SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 23610585SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 23710585SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 23810585SN/Asystem.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed 23910585SN/Asystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 24011570SCurtis.Dunham@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 49425 # Number of times TLB was flushed by MVA & ASID 24110585SN/Asystem.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 24211570SCurtis.Dunham@arm.comsystem.cpu0.itb.flush_entries 25177 # Number of entries that have been flushed from TLB 24310585SN/Asystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 24410585SN/Asystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 24510585SN/Asystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 24610585SN/Asystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 24710585SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 24810585SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 24911570SCurtis.Dunham@arm.comsystem.cpu0.itb.inst_accesses 496740902 # ITB inst accesses 25011570SCurtis.Dunham@arm.comsystem.cpu0.itb.hits 496679820 # DTB hits 25111570SCurtis.Dunham@arm.comsystem.cpu0.itb.misses 61082 # DTB misses 25211570SCurtis.Dunham@arm.comsystem.cpu0.itb.accesses 496740902 # DTB accesses 25311570SCurtis.Dunham@arm.comsystem.cpu0.numPwrStateTransitions 26445 # Number of power state transitions 25411570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::samples 13222 # Distribution of time spent in the clock gated state 25511570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::mean 3555001605.490697 # Distribution of time spent in the clock gated state 25611570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::stdev 88683028869.484894 # Distribution of time spent in the clock gated state 25711570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::underflows 3170 23.98% 23.98% # Distribution of time spent in the clock gated state 25811570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::1000-5e+10 10025 75.82% 99.80% # Distribution of time spent in the clock gated state 25911530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.82% # Distribution of time spent in the clock gated state 26011530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 2 0.02% 99.83% # Distribution of time spent in the clock gated state 26111530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state 26211570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state 26311570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state 26411570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 2 0.02% 99.89% # Distribution of time spent in the clock gated state 26511570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 26611530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::overflows 14 0.11% 100.00% # Distribution of time spent in the clock gated state 26711570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state 26811570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::max_value 7351153278004 # Distribution of time spent in the clock gated state 26911570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::total 13222 # Distribution of time spent in the clock gated state 27011570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateResidencyTicks::ON 292050520702 # Cumulative time (in ticks) in various power states 27111570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateResidencyTicks::CLK_GATED 47004231227798 # Cumulative time (in ticks) in various power states 27211570SCurtis.Dunham@arm.comsystem.cpu0.numCycles 94592576721 # number of cpu cycles simulated 27310585SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 27410585SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 27511167Sjthestness@gmail.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 27611570SCurtis.Dunham@arm.comsystem.cpu0.kern.inst.quiesce 13223 # number of quiesce instructions executed 27711570SCurtis.Dunham@arm.comsystem.cpu0.committedInsts 496443686 # Number of instructions committed 27811570SCurtis.Dunham@arm.comsystem.cpu0.committedOps 583761680 # Number of ops (including micro ops) committed 27911570SCurtis.Dunham@arm.comsystem.cpu0.num_int_alu_accesses 535025290 # Number of integer alu accesses 28011570SCurtis.Dunham@arm.comsystem.cpu0.num_fp_alu_accesses 524584 # Number of float alu accesses 28111570SCurtis.Dunham@arm.comsystem.cpu0.num_func_calls 28899937 # number of times a function call or return occured 28211570SCurtis.Dunham@arm.comsystem.cpu0.num_conditional_control_insts 76311856 # number of instructions that are conditional controls 28311570SCurtis.Dunham@arm.comsystem.cpu0.num_int_insts 535025290 # number of integer instructions 28411570SCurtis.Dunham@arm.comsystem.cpu0.num_fp_insts 524584 # number of float instructions 28511570SCurtis.Dunham@arm.comsystem.cpu0.num_int_register_reads 783282318 # number of times the integer registers were read 28611570SCurtis.Dunham@arm.comsystem.cpu0.num_int_register_writes 424505870 # number of times the integer registers were written 28711570SCurtis.Dunham@arm.comsystem.cpu0.num_fp_register_reads 845921 # number of times the floating registers were read 28811570SCurtis.Dunham@arm.comsystem.cpu0.num_fp_register_writes 445948 # number of times the floating registers were written 28911570SCurtis.Dunham@arm.comsystem.cpu0.num_cc_register_reads 133408683 # number of times the CC registers were read 29011570SCurtis.Dunham@arm.comsystem.cpu0.num_cc_register_writes 133073326 # number of times the CC registers were written 29111570SCurtis.Dunham@arm.comsystem.cpu0.num_mem_refs 178027643 # number of memory refs 29211570SCurtis.Dunham@arm.comsystem.cpu0.num_load_insts 92545018 # Number of load instructions 29311570SCurtis.Dunham@arm.comsystem.cpu0.num_store_insts 85482625 # Number of store instructions 29411570SCurtis.Dunham@arm.comsystem.cpu0.num_idle_cycles 94008475597.936935 # Number of idle cycles 29511570SCurtis.Dunham@arm.comsystem.cpu0.num_busy_cycles 584101123.063064 # Number of busy cycles 29611570SCurtis.Dunham@arm.comsystem.cpu0.not_idle_fraction 0.006175 # Percentage of non-idle cycles 29711570SCurtis.Dunham@arm.comsystem.cpu0.idle_fraction 0.993825 # Percentage of idle cycles 29811570SCurtis.Dunham@arm.comsystem.cpu0.Branches 111093071 # Number of branches fetched 29910585SN/Asystem.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 30011570SCurtis.Dunham@arm.comsystem.cpu0.op_class::IntAlu 404699186 69.29% 69.29% # Class of executed instruction 30111570SCurtis.Dunham@arm.comsystem.cpu0.op_class::IntMult 1236587 0.21% 69.50% # Class of executed instruction 30211570SCurtis.Dunham@arm.comsystem.cpu0.op_class::IntDiv 60193 0.01% 69.51% # Class of executed instruction 30311570SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction 30411570SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction 30511570SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction 30611570SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction 30711570SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction 30811570SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction 30911570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction 31011570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction 31111570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction 31211570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction 31311570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction 31411570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction 31511570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction 31611570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction 31711570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction 31811570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction 31911570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction 32011570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatAdd 8 0.00% 69.51% # Class of executed instruction 32111570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction 32211570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatCmp 13 0.00% 69.51% # Class of executed instruction 32311570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatCvt 21 0.00% 69.51% # Class of executed instruction 32411570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction 32511570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatMisc 72938 0.01% 69.52% # Class of executed instruction 32611570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction 32711570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction 32811570SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction 32911570SCurtis.Dunham@arm.comsystem.cpu0.op_class::MemRead 92545018 15.84% 85.36% # Class of executed instruction 33011570SCurtis.Dunham@arm.comsystem.cpu0.op_class::MemWrite 85482625 14.64% 100.00% # Class of executed instruction 33110585SN/Asystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 33210585SN/Asystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 33311570SCurtis.Dunham@arm.comsystem.cpu0.op_class::total 584096590 # Class of executed instruction 33411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 33511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.replacements 6248914 # number of replacements 33611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.tagsinuse 501.980044 # Cycle average of tags in use 33711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.total_refs 171607957 # Total number of references to valid blocks. 33811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.sampled_refs 6249426 # Sample count of references to valid blocks. 33911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.avg_refs 27.459795 # Average number of references to valid blocks. 34010827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. 34111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 501.980044 # Average occupied blocks per requestor 34211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.980430 # Average percentage of cache occupancy 34311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.980430 # Average percentage of cache occupancy 34410585SN/Asystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 34511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id 34611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id 34711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id 34810585SN/Asystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 34911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.tag_accesses 362271539 # Number of tag accesses 35011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.data_accesses 362271539 # Number of data accesses 35111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 35211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 86024172 # number of ReadReq hits 35311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_hits::total 86024172 # number of ReadReq hits 35411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 80674063 # number of WriteReq hits 35511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_hits::total 80674063 # number of WriteReq hits 35611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 216269 # number of SoftPFReq hits 35711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 216269 # number of SoftPFReq hits 35811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_hits::cpu0.data 261006 # number of WriteLineReq hits 35911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_hits::total 261006 # number of WriteLineReq hits 36011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2087975 # number of LoadLockedReq hits 36111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 2087975 # number of LoadLockedReq hits 36211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 2051823 # number of StoreCondReq hits 36311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 2051823 # number of StoreCondReq hits 36411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 166959241 # number of demand (read+write) hits 36511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_hits::total 166959241 # number of demand (read+write) hits 36611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 167175510 # number of overall hits 36711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_hits::total 167175510 # number of overall hits 36811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 3298422 # number of ReadReq misses 36911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_misses::total 3298422 # number of ReadReq misses 37011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 1477781 # number of WriteReq misses 37111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_misses::total 1477781 # number of WriteReq misses 37211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 769563 # number of SoftPFReq misses 37311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 769563 # number of SoftPFReq misses 37411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_misses::cpu0.data 824193 # number of WriteLineReq misses 37511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_misses::total 824193 # number of WriteLineReq misses 37611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119751 # number of LoadLockedReq misses 37711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 119751 # number of LoadLockedReq misses 37811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 154814 # number of StoreCondReq misses 37911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 154814 # number of StoreCondReq misses 38011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 5600396 # number of demand (read+write) misses 38111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_misses::total 5600396 # number of demand (read+write) misses 38211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 6369959 # number of overall misses 38311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_misses::total 6369959 # number of overall misses 38411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 89322594 # number of ReadReq accesses(hits+misses) 38511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 89322594 # number of ReadReq accesses(hits+misses) 38611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 82151844 # number of WriteReq accesses(hits+misses) 38711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 82151844 # number of WriteReq accesses(hits+misses) 38811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 985832 # number of SoftPFReq accesses(hits+misses) 38911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 985832 # number of SoftPFReq accesses(hits+misses) 39011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1085199 # number of WriteLineReq accesses(hits+misses) 39111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::total 1085199 # number of WriteLineReq accesses(hits+misses) 39211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2207726 # number of LoadLockedReq accesses(hits+misses) 39311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 2207726 # number of LoadLockedReq accesses(hits+misses) 39411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2206637 # number of StoreCondReq accesses(hits+misses) 39511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 2206637 # number of StoreCondReq accesses(hits+misses) 39611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 172559637 # number of demand (read+write) accesses 39711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_accesses::total 172559637 # number of demand (read+write) accesses 39811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 173545469 # number of overall (read+write) accesses 39911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_accesses::total 173545469 # number of overall (read+write) accesses 40011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036927 # miss rate for ReadReq accesses 40111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.036927 # miss rate for ReadReq accesses 40211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017988 # miss rate for WriteReq accesses 40311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.017988 # miss rate for WriteReq accesses 40411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.780623 # miss rate for SoftPFReq accesses 40511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.780623 # miss rate for SoftPFReq accesses 40611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.759486 # miss rate for WriteLineReq accesses 40711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::total 0.759486 # miss rate for WriteLineReq accesses 40811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054242 # miss rate for LoadLockedReq accesses 40911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054242 # miss rate for LoadLockedReq accesses 41011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.070158 # miss rate for StoreCondReq accesses 41111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.070158 # miss rate for StoreCondReq accesses 41211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.032455 # miss rate for demand accesses 41311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.032455 # miss rate for demand accesses 41411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.036705 # miss rate for overall accesses 41511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.036705 # miss rate for overall accesses 41610585SN/Asystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 41710585SN/Asystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 41810585SN/Asystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 41910585SN/Asystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 42010585SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 42110585SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 42211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.writebacks::writebacks 6248914 # number of writebacks 42311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.writebacks::total 6248914 # number of writebacks 42411570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 42511606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.replacements 5509624 # number of replacements 42611570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.tagsinuse 511.989024 # Cycle average of tags in use 42711606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.total_refs 491225330 # Total number of references to valid blocks. 42811606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.sampled_refs 5510136 # Sample count of references to valid blocks. 42911606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.avg_refs 89.149402 # Average number of references to valid blocks. 43011570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.warmup_cycle 5759898000 # Cycle when the warmup percentage was hit. 43111570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989024 # Average occupied blocks per requestor 43210585SN/Asystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy 43310585SN/Asystem.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy 43410585SN/Asystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 43511570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id 43611570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id 43711570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id 43811570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 43910585SN/Asystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 44011606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.tag_accesses 998981083 # Number of tag accesses 44111606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.data_accesses 998981083 # Number of data accesses 44211570SCurtis.Dunham@arm.comsystem.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 44311606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 491225330 # number of ReadReq hits 44411606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_hits::total 491225330 # number of ReadReq hits 44511606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 491225330 # number of demand (read+write) hits 44611606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_hits::total 491225330 # number of demand (read+write) hits 44711606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 491225330 # number of overall hits 44811606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_hits::total 491225330 # number of overall hits 44911606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 5510141 # number of ReadReq misses 45011606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_misses::total 5510141 # number of ReadReq misses 45111606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 5510141 # number of demand (read+write) misses 45211606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_misses::total 5510141 # number of demand (read+write) misses 45311606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 5510141 # number of overall misses 45411606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_misses::total 5510141 # number of overall misses 45511570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 496735471 # number of ReadReq accesses(hits+misses) 45611570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_accesses::total 496735471 # number of ReadReq accesses(hits+misses) 45711570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 496735471 # number of demand (read+write) accesses 45811570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_accesses::total 496735471 # number of demand (read+write) accesses 45911570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 496735471 # number of overall (read+write) accesses 46011570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_accesses::total 496735471 # number of overall (read+write) accesses 46111570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011093 # miss rate for ReadReq accesses 46211570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.011093 # miss rate for ReadReq accesses 46311570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.011093 # miss rate for demand accesses 46411570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.011093 # miss rate for demand accesses 46511570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.011093 # miss rate for overall accesses 46611570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.011093 # miss rate for overall accesses 46710585SN/Asystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 46810585SN/Asystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 46910585SN/Asystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 47010585SN/Asystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 47110585SN/Asystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 47210585SN/Asystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 47311606Sandreas.sandberg@arm.comsystem.cpu0.icache.writebacks::writebacks 5509624 # number of writebacks 47411606Sandreas.sandberg@arm.comsystem.cpu0.icache.writebacks::total 5509624 # number of writebacks 47511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 47610628SN/Asystem.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 47710628SN/Asystem.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 47810628SN/Asystem.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 47910628SN/Asystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 48010628SN/Asystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 48110628SN/Asystem.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 48211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 48311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.replacements 2567589 # number of replacements 48411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.tagsinuse 15706.944975 # Cycle average of tags in use 48511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.total_refs 9429067 # Total number of references to valid blocks. 48611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.sampled_refs 2583246 # Sample count of references to valid blocks. 48711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.avg_refs 3.650085 # Average number of references to valid blocks. 48810585SN/Asystem.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. 48911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 15656.940594 # Average occupied blocks per requestor 49011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 27.364617 # Average occupied blocks per requestor 49111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 22.639763 # Average occupied blocks per requestor 49211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.955624 # Average percentage of cache occupancy 49311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001670 # Average percentage of cache occupancy 49411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001382 # Average percentage of cache occupancy 49511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.958676 # Average percentage of cache occupancy 49611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 57 # Occupied blocks per task id 49711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 15600 # Occupied blocks per task id 49811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id 49911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 41 # Occupied blocks per task id 50011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id 50111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id 50211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 421 # Occupied blocks per task id 50311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 2091 # Occupied blocks per task id 50411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5339 # Occupied blocks per task id 50511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5411 # Occupied blocks per task id 50611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2338 # Occupied blocks per task id 50711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003479 # Percentage of cache occupancy per task id 50811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.952148 # Percentage of cache occupancy per task id 50911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.tag_accesses 401859473 # Number of tag accesses 51011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.data_accesses 401859473 # Number of data accesses 51111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 51211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 287369 # number of ReadReq hits 51311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 155522 # number of ReadReq hits 51411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 442891 # number of ReadReq hits 51511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::writebacks 4441046 # number of WritebackDirty hits 51611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::total 4441046 # number of WritebackDirty hits 51711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackClean_hits::writebacks 7316094 # number of WritebackClean hits 51811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackClean_hits::total 7316094 # number of WritebackClean hits 51911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 640560 # number of ReadExReq hits 52011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 640560 # number of ReadExReq hits 52111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5011469 # number of ReadCleanReq hits 52211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 5011469 # number of ReadCleanReq hits 52311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2961462 # number of ReadSharedReq hits 52411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 2961462 # number of ReadSharedReq hits 52511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::cpu0.data 222733 # number of InvalidateReq hits 52611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::total 222733 # number of InvalidateReq hits 52711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 287369 # number of demand (read+write) hits 52811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 155522 # number of demand (read+write) hits 52911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 5011469 # number of demand (read+write) hits 53011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 3602022 # number of demand (read+write) hits 53111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_hits::total 9056382 # number of demand (read+write) hits 53211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 287369 # number of overall hits 53311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 155522 # number of overall hits 53411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 5011469 # number of overall hits 53511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 3602022 # number of overall hits 53611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_hits::total 9056382 # number of overall hits 53711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 20057 # number of ReadReq misses 53811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9858 # number of ReadReq misses 53911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 29915 # number of ReadReq misses 54011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 137835 # number of UpgradeReq misses 54111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 137835 # number of UpgradeReq misses 54211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 154814 # number of SCUpgradeReq misses 54311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 154814 # number of SCUpgradeReq misses 54411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 699738 # number of ReadExReq misses 54511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 699738 # number of ReadExReq misses 54611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 498672 # number of ReadCleanReq misses 54711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 498672 # number of ReadCleanReq misses 54811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1226274 # number of ReadSharedReq misses 54911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 1226274 # number of ReadSharedReq misses 55011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::cpu0.data 601108 # number of InvalidateReq misses 55111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::total 601108 # number of InvalidateReq misses 55211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 20057 # number of demand (read+write) misses 55311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 9858 # number of demand (read+write) misses 55411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 498672 # number of demand (read+write) misses 55511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 1926012 # number of demand (read+write) misses 55611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_misses::total 2454599 # number of demand (read+write) misses 55711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 20057 # number of overall misses 55811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 9858 # number of overall misses 55911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 498672 # number of overall misses 56011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 1926012 # number of overall misses 56111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_misses::total 2454599 # number of overall misses 56211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 307426 # number of ReadReq accesses(hits+misses) 56311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 165380 # number of ReadReq accesses(hits+misses) 56411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 472806 # number of ReadReq accesses(hits+misses) 56511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::writebacks 4441046 # number of WritebackDirty accesses(hits+misses) 56611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::total 4441046 # number of WritebackDirty accesses(hits+misses) 56711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::writebacks 7316094 # number of WritebackClean accesses(hits+misses) 56811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::total 7316094 # number of WritebackClean accesses(hits+misses) 56911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 137835 # number of UpgradeReq accesses(hits+misses) 57011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 137835 # number of UpgradeReq accesses(hits+misses) 57111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 154814 # number of SCUpgradeReq accesses(hits+misses) 57211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 154814 # number of SCUpgradeReq accesses(hits+misses) 57311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1340298 # number of ReadExReq accesses(hits+misses) 57411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1340298 # number of ReadExReq accesses(hits+misses) 57511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5510141 # number of ReadCleanReq accesses(hits+misses) 57611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 5510141 # number of ReadCleanReq accesses(hits+misses) 57711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4187736 # number of ReadSharedReq accesses(hits+misses) 57811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 4187736 # number of ReadSharedReq accesses(hits+misses) 57911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 823841 # number of InvalidateReq accesses(hits+misses) 58011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::total 823841 # number of InvalidateReq accesses(hits+misses) 58111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 307426 # number of demand (read+write) accesses 58211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 165380 # number of demand (read+write) accesses 58311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 5510141 # number of demand (read+write) accesses 58411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 5528034 # number of demand (read+write) accesses 58511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_accesses::total 11510981 # number of demand (read+write) accesses 58611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 307426 # number of overall (read+write) accesses 58711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 165380 # number of overall (read+write) accesses 58811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 5510141 # number of overall (read+write) accesses 58911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 5528034 # number of overall (read+write) accesses 59011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_accesses::total 11510981 # number of overall (read+write) accesses 59111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.065242 # miss rate for ReadReq accesses 59211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.059608 # miss rate for ReadReq accesses 59311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.063271 # miss rate for ReadReq accesses 59411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 59511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 59610585SN/Asystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 59710585SN/Asystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 59811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.522076 # miss rate for ReadExReq accesses 59911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.522076 # miss rate for ReadExReq accesses 60011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.090501 # miss rate for ReadCleanReq accesses 60111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.090501 # miss rate for ReadCleanReq accesses 60211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.292825 # miss rate for ReadSharedReq accesses 60311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.292825 # miss rate for ReadSharedReq accesses 60411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.729641 # miss rate for InvalidateReq accesses 60511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::total 0.729641 # miss rate for InvalidateReq accesses 60611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.065242 # miss rate for demand accesses 60711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.059608 # miss rate for demand accesses 60811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.090501 # miss rate for demand accesses 60911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.348408 # miss rate for demand accesses 61011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.213240 # miss rate for demand accesses 61111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.065242 # miss rate for overall accesses 61211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.059608 # miss rate for overall accesses 61311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.090501 # miss rate for overall accesses 61411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.348408 # miss rate for overall accesses 61511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.213240 # miss rate for overall accesses 61610585SN/Asystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 61710585SN/Asystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 61810585SN/Asystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 61910585SN/Asystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 62010585SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 62110585SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 62211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.writebacks::writebacks 1552940 # number of writebacks 62311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.writebacks::total 1552940 # number of writebacks 62411606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_requests 24175638 # Total number of requests made to the snoop filter. 62511606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_requests 12313629 # Number of requests hitting in the snoop filter with a single holder of the requested data. 62611570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1398 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 62711606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_snoops 303605 # Total number of snoops made to the snoop filter. 62811606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_snoops 303605 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 62911606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 63011570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 63111570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 622617 # Transaction distribution 63211606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 10320494 # Transaction distribution 63311570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 33234 # Transaction distribution 63411570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 33234 # Transaction distribution 63511606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackDirty 4441046 # Transaction distribution 63611606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackClean 7317492 # Transaction distribution 63711606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 137835 # Transaction distribution 63811606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 154814 # Transaction distribution 63911606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 292649 # Transaction distribution 64011570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1340298 # Transaction distribution 64111570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1340298 # Transaction distribution 64211606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 5510141 # Transaction distribution 64311606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 4187736 # Transaction distribution 64411570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateReq 823841 # Transaction distribution 64511570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateResp 823841 # Transaction distribution 64611606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16616156 # Packet count per connected master and slave (bytes) 64711606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19670562 # Packet count per connected master and slave (bytes) 64811570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 364916 # Packet count per connected master and slave (bytes) 64911570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 727936 # Packet count per connected master and slave (bytes) 65011606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_count::total 37379570 # Packet count per connected master and slave (bytes) 65111606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 705437460 # Cumulative packet size per connected master and slave (bytes) 65211606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 753923068 # Cumulative packet size per connected master and slave (bytes) 65311570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1459664 # Cumulative packet size per connected master and slave (bytes) 65411570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2911744 # Cumulative packet size per connected master and slave (bytes) 65511606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_size::total 1463731936 # Cumulative packet size per connected master and slave (bytes) 65611606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoops 4670427 # Total snoops (count) 65711606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoopTraffic 101174852 # Total snoop traffic (bytes) 65811606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 29058250 # Request fanout histogram 65911606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 0.019576 # Request fanout histogram 66011606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.138538 # Request fanout histogram 66110585SN/Asystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 66211606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 28489407 98.04% 98.04% # Request fanout histogram 66311606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 568843 1.96% 100.00% # Request fanout histogram 66411606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 66510585SN/Asystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 66611138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 66711606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 66811606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 29058250 # Request fanout histogram 66911570SCurtis.Dunham@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 67010628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 67110628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 67210628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 67310628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 67410628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 67510628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 67610628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 67710628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 67810585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 67910585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 68010585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 68110585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 68210585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 68310585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 68410585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 68510585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 68610585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 68710585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 68810585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 68910585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 69010585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 69110585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 69210585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 69310585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 69410585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 69510585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 69610585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 69710585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 69810585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 69911570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 70011570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walks 144363 # Table walker walks requested 70111570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksLong 144363 # Table walker walks initiated with long descriptors 70211570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 144363 # Table walker wait (enqueue to first request) latency 70311570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0 144363 100.00% 100.00% # Table walker wait (enqueue to first request) latency 70411570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 144363 # Table walker wait (enqueue to first request) latency 70511570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksPending::samples -274399872 # Table walker pending requests distribution 70611570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksPending::0 -274399872 100.00% 100.00% # Table walker pending requests distribution 70711570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksPending::total -274399872 # Table walker pending requests distribution 70811570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 111796 88.76% 88.76% # Table walker page sizes translated 70911570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkPageSizes::2M 14154 11.24% 100.00% # Table walker page sizes translated 71011570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 125950 # Table walker page sizes translated 71111570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144363 # Table walker requests started/completed, data/inst 71210628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 71311570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144363 # Table walker requests started/completed, data/inst 71411570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 125950 # Table walker requests started/completed, data/inst 71510628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 71611570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 125950 # Table walker requests started/completed, data/inst 71711570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 270313 # Table walker requests started/completed, data/inst 71810585SN/Asystem.cpu1.dtb.inst_hits 0 # ITB inst hits 71910585SN/Asystem.cpu1.dtb.inst_misses 0 # ITB inst misses 72011570SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_hits 90656208 # DTB read hits 72111570SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_misses 111973 # DTB read misses 72211570SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_hits 81688076 # DTB write hits 72311570SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_misses 32390 # DTB write misses 72410585SN/Asystem.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed 72510585SN/Asystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 72611570SCurtis.Dunham@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 49425 # Number of times TLB was flushed by MVA & ASID 72710585SN/Asystem.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 72811570SCurtis.Dunham@arm.comsystem.cpu1.dtb.flush_entries 44622 # Number of entries that have been flushed from TLB 72910585SN/Asystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 73011570SCurtis.Dunham@arm.comsystem.cpu1.dtb.prefetch_faults 4399 # Number of TLB faults due to prefetch 73110585SN/Asystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 73211570SCurtis.Dunham@arm.comsystem.cpu1.dtb.perms_faults 11479 # Number of TLB faults due to permissions restrictions 73311570SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_accesses 90768181 # DTB read accesses 73411570SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_accesses 81720466 # DTB write accesses 73510585SN/Asystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 73611570SCurtis.Dunham@arm.comsystem.cpu1.dtb.hits 172344284 # DTB hits 73711570SCurtis.Dunham@arm.comsystem.cpu1.dtb.misses 144363 # DTB misses 73811570SCurtis.Dunham@arm.comsystem.cpu1.dtb.accesses 172488647 # DTB accesses 73911570SCurtis.Dunham@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 74010628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 74110628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 74210628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 74310628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 74410628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 74510628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 74610628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 74710628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 74810585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 74910585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 75010585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 75110585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 75210585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 75310585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 75410585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 75510585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 75610585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 75710585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 75810585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 75910585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 76010585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 76110585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 76210585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 76310585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 76410585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 76510585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 76610585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 76710585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 76810585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 76911570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 77011570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walks 61351 # Table walker walks requested 77111570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksLong 61351 # Table walker walks initiated with long descriptors 77211570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 61351 # Table walker wait (enqueue to first request) latency 77311570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkWaitTime::0 61351 100.00% 100.00% # Table walker wait (enqueue to first request) latency 77411570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 61351 # Table walker wait (enqueue to first request) latency 77511570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksPending::samples -274400872 # Table walker pending requests distribution 77611570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksPending::0 -274400872 100.00% 100.00% # Table walker pending requests distribution 77711570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksPending::total -274400872 # Table walker pending requests distribution 77811570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 54387 99.05% 99.05% # Table walker page sizes translated 77911570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkPageSizes::2M 524 0.95% 100.00% # Table walker page sizes translated 78011570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 54911 # Table walker page sizes translated 78110628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 78211570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61351 # Table walker requests started/completed, data/inst 78311570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 61351 # Table walker requests started/completed, data/inst 78410628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 78511570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 54911 # Table walker requests started/completed, data/inst 78611570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 54911 # Table walker requests started/completed, data/inst 78711570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 116262 # Table walker requests started/completed, data/inst 78811570SCurtis.Dunham@arm.comsystem.cpu1.itb.inst_hits 480862179 # ITB inst hits 78911570SCurtis.Dunham@arm.comsystem.cpu1.itb.inst_misses 61351 # ITB inst misses 79010585SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 79110585SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 79210585SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 79310585SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 79410585SN/Asystem.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed 79510585SN/Asystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 79611570SCurtis.Dunham@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 49425 # Number of times TLB was flushed by MVA & ASID 79710585SN/Asystem.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 79811570SCurtis.Dunham@arm.comsystem.cpu1.itb.flush_entries 31395 # Number of entries that have been flushed from TLB 79910585SN/Asystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 80010585SN/Asystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 80110585SN/Asystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 80210585SN/Asystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 80310585SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 80410585SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 80511570SCurtis.Dunham@arm.comsystem.cpu1.itb.inst_accesses 480923530 # ITB inst accesses 80611570SCurtis.Dunham@arm.comsystem.cpu1.itb.hits 480862179 # DTB hits 80711570SCurtis.Dunham@arm.comsystem.cpu1.itb.misses 61351 # DTB misses 80811570SCurtis.Dunham@arm.comsystem.cpu1.itb.accesses 480923530 # DTB accesses 80911570SCurtis.Dunham@arm.comsystem.cpu1.numPwrStateTransitions 12248 # Number of power state transitions 81011570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::samples 6124 # Distribution of time spent in the clock gated state 81111570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::mean 7676898273.449706 # Distribution of time spent in the clock gated state 81211570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::stdev 188572680414.552032 # Distribution of time spent in the clock gated state 81311570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::underflows 4459 72.81% 72.81% # Distribution of time spent in the clock gated state 81411570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::1000-5e+10 1644 26.85% 99.66% # Distribution of time spent in the clock gated state 81511570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.08% 99.74% # Distribution of time spent in the clock gated state 81611570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.76% # Distribution of time spent in the clock gated state 81711570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.77% # Distribution of time spent in the clock gated state 81811570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.03% 99.80% # Distribution of time spent in the clock gated state 81911530Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.82% # Distribution of time spent in the clock gated state 82011570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.02% 99.84% # Distribution of time spent in the clock gated state 82111530Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::overflows 10 0.16% 100.00% # Distribution of time spent in the clock gated state 82211570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state 82311570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::max_value 11813542452500 # Distribution of time spent in the clock gated state 82411570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::total 6124 # Distribution of time spent in the clock gated state 82511570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateResidencyTicks::ON 282956721894 # Cumulative time (in ticks) in various power states 82611570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateResidencyTicks::CLK_GATED 47013325026606 # Cumulative time (in ticks) in various power states 82711570SCurtis.Dunham@arm.comsystem.cpu1.numCycles 94592569622 # number of cpu cycles simulated 82810585SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 82910585SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 83011167Sjthestness@gmail.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 83111570SCurtis.Dunham@arm.comsystem.cpu1.kern.inst.quiesce 6124 # number of quiesce instructions executed 83211570SCurtis.Dunham@arm.comsystem.cpu1.committedInsts 480611396 # Number of instructions committed 83311570SCurtis.Dunham@arm.comsystem.cpu1.committedOps 565602830 # Number of ops (including micro ops) committed 83411570SCurtis.Dunham@arm.comsystem.cpu1.num_int_alu_accesses 519092247 # Number of integer alu accesses 83511570SCurtis.Dunham@arm.comsystem.cpu1.num_fp_alu_accesses 374666 # Number of float alu accesses 83611570SCurtis.Dunham@arm.comsystem.cpu1.num_func_calls 28363152 # number of times a function call or return occured 83711570SCurtis.Dunham@arm.comsystem.cpu1.num_conditional_control_insts 73579507 # number of instructions that are conditional controls 83811570SCurtis.Dunham@arm.comsystem.cpu1.num_int_insts 519092247 # number of integer instructions 83911570SCurtis.Dunham@arm.comsystem.cpu1.num_fp_insts 374666 # number of float instructions 84011570SCurtis.Dunham@arm.comsystem.cpu1.num_int_register_reads 766987939 # number of times the integer registers were read 84111570SCurtis.Dunham@arm.comsystem.cpu1.num_int_register_writes 413187755 # number of times the integer registers were written 84211570SCurtis.Dunham@arm.comsystem.cpu1.num_fp_register_reads 609913 # number of times the floating registers were read 84311570SCurtis.Dunham@arm.comsystem.cpu1.num_fp_register_writes 303136 # number of times the floating registers were written 84411570SCurtis.Dunham@arm.comsystem.cpu1.num_cc_register_reads 127077975 # number of times the CC registers were read 84511570SCurtis.Dunham@arm.comsystem.cpu1.num_cc_register_writes 126798720 # number of times the CC registers were written 84611570SCurtis.Dunham@arm.comsystem.cpu1.num_mem_refs 172465256 # number of memory refs 84711570SCurtis.Dunham@arm.comsystem.cpu1.num_load_insts 90755131 # Number of load instructions 84811570SCurtis.Dunham@arm.comsystem.cpu1.num_store_insts 81710125 # Number of store instructions 84911570SCurtis.Dunham@arm.comsystem.cpu1.num_idle_cycles 94026656141.566330 # Number of idle cycles 85011570SCurtis.Dunham@arm.comsystem.cpu1.num_busy_cycles 565913480.433670 # Number of busy cycles 85111570SCurtis.Dunham@arm.comsystem.cpu1.not_idle_fraction 0.005983 # Percentage of non-idle cycles 85211570SCurtis.Dunham@arm.comsystem.cpu1.idle_fraction 0.994017 # Percentage of idle cycles 85311570SCurtis.Dunham@arm.comsystem.cpu1.Branches 107067845 # Number of branches fetched 85410585SN/Asystem.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 85511570SCurtis.Dunham@arm.comsystem.cpu1.op_class::IntAlu 392212619 69.31% 69.31% # Class of executed instruction 85611570SCurtis.Dunham@arm.comsystem.cpu1.op_class::IntMult 1132978 0.20% 69.51% # Class of executed instruction 85711570SCurtis.Dunham@arm.comsystem.cpu1.op_class::IntDiv 61173 0.01% 69.52% # Class of executed instruction 85811570SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction 85911570SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction 86011570SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction 86111570SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction 86211570SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction 86311570SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction 86411570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction 86511570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction 86611570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction 86711570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction 86811570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction 86911570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction 87011570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction 87111570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction 87211570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction 87311570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction 87411570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction 87511570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatAdd 0 0.00% 69.52% # Class of executed instruction 87611570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction 87711570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatCmp 0 0.00% 69.52% # Class of executed instruction 87811570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatCvt 0 0.00% 69.52% # Class of executed instruction 87911570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction 88011570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatMisc 36628 0.01% 69.52% # Class of executed instruction 88111336Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction 88211336Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction 88311336Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction 88411570SCurtis.Dunham@arm.comsystem.cpu1.op_class::MemRead 90755131 16.04% 85.56% # Class of executed instruction 88511570SCurtis.Dunham@arm.comsystem.cpu1.op_class::MemWrite 81710125 14.44% 100.00% # Class of executed instruction 88610585SN/Asystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 88710585SN/Asystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 88811570SCurtis.Dunham@arm.comsystem.cpu1.op_class::total 565908654 # Class of executed instruction 88911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 89011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.replacements 5970884 # number of replacements 89111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.tagsinuse 423.354804 # Cycle average of tags in use 89211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.total_refs 166384448 # Total number of references to valid blocks. 89311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.sampled_refs 5971395 # Sample count of references to valid blocks. 89411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.avg_refs 27.863581 # Average number of references to valid blocks. 89511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.warmup_cycle 8470277781000 # Cycle when the warmup percentage was hit. 89611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 423.354804 # Average occupied blocks per requestor 89711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.826865 # Average percentage of cache occupancy 89811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.826865 # Average percentage of cache occupancy 89911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 90011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id 90111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 330 # Occupied blocks per task id 90211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id 90311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 90411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.tag_accesses 350957211 # Number of tag accesses 90511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.data_accesses 350957211 # Number of data accesses 90611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 90711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 84198598 # number of ReadReq hits 90811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_hits::total 84198598 # number of ReadReq hits 90911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 77531561 # number of WriteReq hits 91011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_hits::total 77531561 # number of WriteReq hits 91111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 187263 # number of SoftPFReq hits 91211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 187263 # number of SoftPFReq hits 91311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_hits::cpu1.data 64886 # number of WriteLineReq hits 91411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_hits::total 64886 # number of WriteLineReq hits 91511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2055500 # number of LoadLockedReq hits 91611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 2055500 # number of LoadLockedReq hits 91711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 2044725 # number of StoreCondReq hits 91811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 2044725 # number of StoreCondReq hits 91911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 161795045 # number of demand (read+write) hits 92011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_hits::total 161795045 # number of demand (read+write) hits 92111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 161982308 # number of overall hits 92211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_hits::total 161982308 # number of overall hits 92311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 3367290 # number of ReadReq misses 92411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_misses::total 3367290 # number of ReadReq misses 92511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 1466124 # number of WriteReq misses 92611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_misses::total 1466124 # number of WriteReq misses 92711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 793623 # number of SoftPFReq misses 92811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 793623 # number of SoftPFReq misses 92911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_misses::cpu1.data 433871 # number of WriteLineReq misses 93011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_misses::total 433871 # number of WriteLineReq misses 93111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 147105 # number of LoadLockedReq misses 93211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 147105 # number of LoadLockedReq misses 93311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 156674 # number of StoreCondReq misses 93411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 156674 # number of StoreCondReq misses 93511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 5267285 # number of demand (read+write) misses 93611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_misses::total 5267285 # number of demand (read+write) misses 93711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 6060908 # number of overall misses 93811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_misses::total 6060908 # number of overall misses 93911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 87565888 # number of ReadReq accesses(hits+misses) 94011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 87565888 # number of ReadReq accesses(hits+misses) 94111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 78997685 # number of WriteReq accesses(hits+misses) 94211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 78997685 # number of WriteReq accesses(hits+misses) 94311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 980886 # number of SoftPFReq accesses(hits+misses) 94411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 980886 # number of SoftPFReq accesses(hits+misses) 94511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::cpu1.data 498757 # number of WriteLineReq accesses(hits+misses) 94611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::total 498757 # number of WriteLineReq accesses(hits+misses) 94711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2202605 # number of LoadLockedReq accesses(hits+misses) 94811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 2202605 # number of LoadLockedReq accesses(hits+misses) 94911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2201399 # number of StoreCondReq accesses(hits+misses) 95011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 2201399 # number of StoreCondReq accesses(hits+misses) 95111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 167062330 # number of demand (read+write) accesses 95211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_accesses::total 167062330 # number of demand (read+write) accesses 95311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 168043216 # number of overall (read+write) accesses 95411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_accesses::total 168043216 # number of overall (read+write) accesses 95511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038454 # miss rate for ReadReq accesses 95611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.038454 # miss rate for ReadReq accesses 95711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018559 # miss rate for WriteReq accesses 95811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.018559 # miss rate for WriteReq accesses 95911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.809088 # miss rate for SoftPFReq accesses 96011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.809088 # miss rate for SoftPFReq accesses 96111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.869905 # miss rate for WriteLineReq accesses 96211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::total 0.869905 # miss rate for WriteLineReq accesses 96311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066787 # miss rate for LoadLockedReq accesses 96411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066787 # miss rate for LoadLockedReq accesses 96511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071170 # miss rate for StoreCondReq accesses 96611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.071170 # miss rate for StoreCondReq accesses 96711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.031529 # miss rate for demand accesses 96811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.031529 # miss rate for demand accesses 96911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.036068 # miss rate for overall accesses 97011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.036068 # miss rate for overall accesses 97110585SN/Asystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 97210585SN/Asystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 97310585SN/Asystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 97410585SN/Asystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 97510585SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 97610585SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 97711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.writebacks::writebacks 5970884 # number of writebacks 97811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.writebacks::total 5970884 # number of writebacks 97911570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 98011570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.replacements 4768482 # number of replacements 98111570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.tagsinuse 496.452247 # Cycle average of tags in use 98211570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.total_refs 476148096 # Total number of references to valid blocks. 98311570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.sampled_refs 4768994 # Sample count of references to valid blocks. 98411570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.avg_refs 99.842461 # Average number of references to valid blocks. 98511570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.warmup_cycle 8470205818500 # Cycle when the warmup percentage was hit. 98611570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 496.452247 # Average occupied blocks per requestor 98711570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.969633 # Average percentage of cache occupancy 98811570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.969633 # Average percentage of cache occupancy 98910585SN/Asystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 99011570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 99111502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id 99211570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 146 # Occupied blocks per task id 99310585SN/Asystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 99411570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.tag_accesses 966603174 # Number of tag accesses 99511570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.data_accesses 966603174 # Number of data accesses 99611570SCurtis.Dunham@arm.comsystem.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 99711570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 476148096 # number of ReadReq hits 99811570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_hits::total 476148096 # number of ReadReq hits 99911570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 476148096 # number of demand (read+write) hits 100011570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_hits::total 476148096 # number of demand (read+write) hits 100111570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 476148096 # number of overall hits 100211570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_hits::total 476148096 # number of overall hits 100311570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 4768994 # number of ReadReq misses 100411570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_misses::total 4768994 # number of ReadReq misses 100511570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 4768994 # number of demand (read+write) misses 100611570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_misses::total 4768994 # number of demand (read+write) misses 100711570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 4768994 # number of overall misses 100811570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_misses::total 4768994 # number of overall misses 100911570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 480917090 # number of ReadReq accesses(hits+misses) 101011570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_accesses::total 480917090 # number of ReadReq accesses(hits+misses) 101111570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 480917090 # number of demand (read+write) accesses 101211570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_accesses::total 480917090 # number of demand (read+write) accesses 101311570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 480917090 # number of overall (read+write) accesses 101411570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_accesses::total 480917090 # number of overall (read+write) accesses 101511570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009916 # miss rate for ReadReq accesses 101611570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.009916 # miss rate for ReadReq accesses 101711570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.009916 # miss rate for demand accesses 101811570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.009916 # miss rate for demand accesses 101911570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.009916 # miss rate for overall accesses 102011570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.009916 # miss rate for overall accesses 102110585SN/Asystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 102210585SN/Asystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 102310585SN/Asystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 102410585SN/Asystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 102510585SN/Asystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 102610585SN/Asystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 102711570SCurtis.Dunham@arm.comsystem.cpu1.icache.writebacks::writebacks 4768482 # number of writebacks 102811570SCurtis.Dunham@arm.comsystem.cpu1.icache.writebacks::total 4768482 # number of writebacks 102911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 103010628SN/Asystem.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 103110628SN/Asystem.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 103210628SN/Asystem.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 103310628SN/Asystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 103410628SN/Asystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 103510628SN/Asystem.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 103611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 103711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.replacements 2174770 # number of replacements 103811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.tagsinuse 13105.960937 # Cycle average of tags in use 103911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.total_refs 8815603 # Total number of references to valid blocks. 104011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.sampled_refs 2190453 # Sample count of references to valid blocks. 104111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.avg_refs 4.024557 # Average number of references to valid blocks. 104211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 104311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 13068.855777 # Average occupied blocks per requestor 104411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 21.863128 # Average occupied blocks per requestor 104511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 15.242032 # Average occupied blocks per requestor 104611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.797660 # Average percentage of cache occupancy 104711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001334 # Average percentage of cache occupancy 104811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000930 # Average percentage of cache occupancy 104911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.799924 # Average percentage of cache occupancy 105011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 90 # Occupied blocks per task id 105111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 15593 # Occupied blocks per task id 105211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 57 # Occupied blocks per task id 105311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id 105411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id 105511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 246 # Occupied blocks per task id 105611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 2414 # Occupied blocks per task id 105711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 7618 # Occupied blocks per task id 105811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 3564 # Occupied blocks per task id 105911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1751 # Occupied blocks per task id 106011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005493 # Percentage of cache occupancy per task id 106111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.951721 # Percentage of cache occupancy per task id 106211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.tag_accesses 369059783 # Number of tag accesses 106311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.data_accesses 369059783 # Number of data accesses 106411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 106511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 338101 # number of ReadReq hits 106611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 153667 # number of ReadReq hits 106711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 491768 # number of ReadReq hits 106811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::writebacks 4061526 # number of WritebackDirty hits 106911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::total 4061526 # number of WritebackDirty hits 107011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackClean_hits::writebacks 6677473 # number of WritebackClean hits 107111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackClean_hits::total 6677473 # number of WritebackClean hits 107211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 614785 # number of ReadExReq hits 107311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 614785 # number of ReadExReq hits 107411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4308825 # number of ReadCleanReq hits 107511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 4308825 # number of ReadCleanReq hits 107611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3093892 # number of ReadSharedReq hits 107711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 3093892 # number of ReadSharedReq hits 107811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::cpu1.data 164960 # number of InvalidateReq hits 107911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::total 164960 # number of InvalidateReq hits 108011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 338101 # number of demand (read+write) hits 108111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 153667 # number of demand (read+write) hits 108211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 4308825 # number of demand (read+write) hits 108311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 3708677 # number of demand (read+write) hits 108411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_hits::total 8509270 # number of demand (read+write) hits 108511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 338101 # number of overall hits 108611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 153667 # number of overall hits 108711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 4308825 # number of overall hits 108811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 3708677 # number of overall hits 108911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_hits::total 8509270 # number of overall hits 109011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 22355 # number of ReadReq misses 109111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10972 # number of ReadReq misses 109211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 33327 # number of ReadReq misses 109311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 145242 # number of UpgradeReq misses 109411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 145242 # number of UpgradeReq misses 109511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 156674 # number of SCUpgradeReq misses 109611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 156674 # number of SCUpgradeReq misses 109711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 706301 # number of ReadExReq misses 109811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 706301 # number of ReadExReq misses 109911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 460169 # number of ReadCleanReq misses 110011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 460169 # number of ReadCleanReq misses 110111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1214126 # number of ReadSharedReq misses 110211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 1214126 # number of ReadSharedReq misses 110311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::cpu1.data 268707 # number of InvalidateReq misses 110411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::total 268707 # number of InvalidateReq misses 110511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 22355 # number of demand (read+write) misses 110611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 10972 # number of demand (read+write) misses 110711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 460169 # number of demand (read+write) misses 110811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 1920427 # number of demand (read+write) misses 110911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_misses::total 2413923 # number of demand (read+write) misses 111011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 22355 # number of overall misses 111111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 10972 # number of overall misses 111211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 460169 # number of overall misses 111311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 1920427 # number of overall misses 111411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_misses::total 2413923 # number of overall misses 111511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 360456 # number of ReadReq accesses(hits+misses) 111611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 164639 # number of ReadReq accesses(hits+misses) 111711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 525095 # number of ReadReq accesses(hits+misses) 111811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::writebacks 4061526 # number of WritebackDirty accesses(hits+misses) 111911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::total 4061526 # number of WritebackDirty accesses(hits+misses) 112011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::writebacks 6677473 # number of WritebackClean accesses(hits+misses) 112111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::total 6677473 # number of WritebackClean accesses(hits+misses) 112211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 145242 # number of UpgradeReq accesses(hits+misses) 112311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 145242 # number of UpgradeReq accesses(hits+misses) 112411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 156674 # number of SCUpgradeReq accesses(hits+misses) 112511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 156674 # number of SCUpgradeReq accesses(hits+misses) 112611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1321086 # number of ReadExReq accesses(hits+misses) 112711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 1321086 # number of ReadExReq accesses(hits+misses) 112811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4768994 # number of ReadCleanReq accesses(hits+misses) 112911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 4768994 # number of ReadCleanReq accesses(hits+misses) 113011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4308018 # number of ReadSharedReq accesses(hits+misses) 113111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 4308018 # number of ReadSharedReq accesses(hits+misses) 113211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 433667 # number of InvalidateReq accesses(hits+misses) 113311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::total 433667 # number of InvalidateReq accesses(hits+misses) 113411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 360456 # number of demand (read+write) accesses 113511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 164639 # number of demand (read+write) accesses 113611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 4768994 # number of demand (read+write) accesses 113711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 5629104 # number of demand (read+write) accesses 113811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_accesses::total 10923193 # number of demand (read+write) accesses 113911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 360456 # number of overall (read+write) accesses 114011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 164639 # number of overall (read+write) accesses 114111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 4768994 # number of overall (read+write) accesses 114211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 5629104 # number of overall (read+write) accesses 114311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_accesses::total 10923193 # number of overall (read+write) accesses 114411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.062019 # miss rate for ReadReq accesses 114511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.066643 # miss rate for ReadReq accesses 114611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.063469 # miss rate for ReadReq accesses 114711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 114811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 114910585SN/Asystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 115010585SN/Asystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 115111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.534637 # miss rate for ReadExReq accesses 115211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.534637 # miss rate for ReadExReq accesses 115311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.096492 # miss rate for ReadCleanReq accesses 115411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.096492 # miss rate for ReadCleanReq accesses 115511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.281829 # miss rate for ReadSharedReq accesses 115611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.281829 # miss rate for ReadSharedReq accesses 115711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.619616 # miss rate for InvalidateReq accesses 115811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::total 0.619616 # miss rate for InvalidateReq accesses 115911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.062019 # miss rate for demand accesses 116011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.066643 # miss rate for demand accesses 116111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.096492 # miss rate for demand accesses 116211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.341160 # miss rate for demand accesses 116311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.220991 # miss rate for demand accesses 116411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.062019 # miss rate for overall accesses 116511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.066643 # miss rate for overall accesses 116611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.096492 # miss rate for overall accesses 116711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.341160 # miss rate for overall accesses 116811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.220991 # miss rate for overall accesses 116910585SN/Asystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 117010585SN/Asystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 117110585SN/Asystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 117210585SN/Asystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 117310585SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 117410585SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 117511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.writebacks::writebacks 1197912 # number of writebacks 117611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.writebacks::total 1197912 # number of writebacks 117711606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_requests 22146544 # Total number of requests made to the snoop filter. 117811606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_requests 11314780 # Number of requests hitting in the snoop filter with a single holder of the requested data. 117911570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_requests 367 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 118011606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_snoops 285761 # Total number of snoops made to the snoop filter. 118111606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_snoops 285759 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 118211606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 118311570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 118411570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 607661 # Transaction distribution 118511606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 9684673 # Transaction distribution 118611570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 5564 # Transaction distribution 118711570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 5564 # Transaction distribution 118811606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackDirty 4061526 # Transaction distribution 118911606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackClean 6677840 # Transaction distribution 119011606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 145242 # Transaction distribution 119111606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 156674 # Transaction distribution 119211606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 301916 # Transaction distribution 119311570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 1321086 # Transaction distribution 119411570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 1321086 # Transaction distribution 119511570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 4768994 # Transaction distribution 119611606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 4308018 # Transaction distribution 119711570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateReq 433667 # Transaction distribution 119811570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateResp 433667 # Transaction distribution 119911570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14306730 # Packet count per connected master and slave (bytes) 120011606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18723008 # Packet count per connected master and slave (bytes) 120111570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 366766 # Packet count per connected master and slave (bytes) 120211570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 836674 # Packet count per connected master and slave (bytes) 120311606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_count::total 34233178 # Packet count per connected master and slave (bytes) 120411570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 610398984 # Cumulative packet size per connected master and slave (bytes) 120511606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 742432559 # Cumulative packet size per connected master and slave (bytes) 120611570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1467064 # Cumulative packet size per connected master and slave (bytes) 120711570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3346696 # Cumulative packet size per connected master and slave (bytes) 120811606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_size::total 1357645303 # Cumulative packet size per connected master and slave (bytes) 120911606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoops 4277162 # Total snoops (count) 121011606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoopTraffic 79243712 # Total snoop traffic (bytes) 121111606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 26604267 # Request fanout histogram 121211606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 0.021049 # Request fanout histogram 121311606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.143548 # Request fanout histogram 121410585SN/Asystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 121511606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 26044274 97.90% 97.90% # Request fanout histogram 121611606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 559991 2.10% 100.00% # Request fanout histogram 121711606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 2 0.00% 100.00% # Request fanout histogram 121810585SN/Asystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 121911138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 122010827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 122111606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 26604267 # Request fanout histogram 122211570SCurtis.Dunham@arm.comsystem.iobus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 122311502SCurtis.Dunham@arm.comsystem.iobus.trans_dist::ReadReq 40301 # Transaction distribution 122411502SCurtis.Dunham@arm.comsystem.iobus.trans_dist::ReadResp 40301 # Transaction distribution 122511336Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 136636 # Transaction distribution 122611336Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 136636 # Transaction distribution 122711502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47642 # Packet count per connected master and slave (bytes) 122810585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 122911245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 123010585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 123110585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 123210585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 123310585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 123410585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 123510585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 123610585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 123710585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 123810585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 123910585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 124011502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122576 # Packet count per connected master and slave (bytes) 124111502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231218 # Packet count per connected master and slave (bytes) 124211502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231218 # Packet count per connected master and slave (bytes) 124310585SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 124410585SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 124511502SCurtis.Dunham@arm.comsystem.iobus.pkt_count::total 353874 # Packet count per connected master and slave (bytes) 124611502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47662 # Cumulative packet size per connected master and slave (bytes) 124710585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 124811245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 124910585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 125010585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 125110585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 125210585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 125310585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 125410585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 125510585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 125610585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 125710585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 125810585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 125911502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::total 155683 # Cumulative packet size per connected master and slave (bytes) 126011502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338888 # Cumulative packet size per connected master and slave (bytes) 126111502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7338888 # Cumulative packet size per connected master and slave (bytes) 126210585SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 126310585SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 126411502SCurtis.Dunham@arm.comsystem.iobus.pkt_size::total 7496657 # Cumulative packet size per connected master and slave (bytes) 126511570SCurtis.Dunham@arm.comsystem.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 126611502SCurtis.Dunham@arm.comsystem.iocache.tags.replacements 115590 # number of replacements 126711570SCurtis.Dunham@arm.comsystem.iocache.tags.tagsinuse 11.298808 # Cycle average of tags in use 126810585SN/Asystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 126911502SCurtis.Dunham@arm.comsystem.iocache.tags.sampled_refs 115606 # Sample count of references to valid blocks. 127010585SN/Asystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 127111570SCurtis.Dunham@arm.comsystem.iocache.tags.warmup_cycle 9107772860509 # Cycle when the warmup percentage was hit. 127211570SCurtis.Dunham@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 3.845510 # Average occupied blocks per requestor 127311570SCurtis.Dunham@arm.comsystem.iocache.tags.occ_blocks::realview.ide 7.453298 # Average occupied blocks per requestor 127411570SCurtis.Dunham@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.240344 # Average percentage of cache occupancy 127511570SCurtis.Dunham@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.465831 # Average percentage of cache occupancy 127611570SCurtis.Dunham@arm.comsystem.iocache.tags.occ_percent::total 0.706176 # Average percentage of cache occupancy 127710585SN/Asystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 127810585SN/Asystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 127910585SN/Asystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 128011502SCurtis.Dunham@arm.comsystem.iocache.tags.tag_accesses 1040838 # Number of tag accesses 128111502SCurtis.Dunham@arm.comsystem.iocache.tags.data_accesses 1040838 # Number of data accesses 128211570SCurtis.Dunham@arm.comsystem.iocache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 128310585SN/Asystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 128411502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_misses::realview.ide 8881 # number of ReadReq misses 128511502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_misses::total 8918 # number of ReadReq misses 128610585SN/Asystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 128710585SN/Asystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 128810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 128910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 129010585SN/Asystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 129111502SCurtis.Dunham@arm.comsystem.iocache.demand_misses::realview.ide 115609 # number of demand (read+write) misses 129211502SCurtis.Dunham@arm.comsystem.iocache.demand_misses::total 115649 # number of demand (read+write) misses 129310585SN/Asystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 129411502SCurtis.Dunham@arm.comsystem.iocache.overall_misses::realview.ide 115609 # number of overall misses 129511502SCurtis.Dunham@arm.comsystem.iocache.overall_misses::total 115649 # number of overall misses 129610585SN/Asystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 129711502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8881 # number of ReadReq accesses(hits+misses) 129811502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_accesses::total 8918 # number of ReadReq accesses(hits+misses) 129910585SN/Asystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 130010585SN/Asystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 130110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 130210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 130310585SN/Asystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 130411502SCurtis.Dunham@arm.comsystem.iocache.demand_accesses::realview.ide 115609 # number of demand (read+write) accesses 130511502SCurtis.Dunham@arm.comsystem.iocache.demand_accesses::total 115649 # number of demand (read+write) accesses 130610585SN/Asystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 130711502SCurtis.Dunham@arm.comsystem.iocache.overall_accesses::realview.ide 115609 # number of overall (read+write) accesses 130811502SCurtis.Dunham@arm.comsystem.iocache.overall_accesses::total 115649 # number of overall (read+write) accesses 130910585SN/Asystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 131010585SN/Asystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 131110585SN/Asystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 131210585SN/Asystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 131310585SN/Asystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 131410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 131510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 131610585SN/Asystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 131710585SN/Asystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 131810585SN/Asystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 131910585SN/Asystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 132010585SN/Asystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 132110585SN/Asystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 132210585SN/Asystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 132310585SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 132410585SN/Asystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 132510585SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 132610585SN/Asystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 132710585SN/Asystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 132810585SN/Asystem.iocache.writebacks::writebacks 106694 # number of writebacks 132910585SN/Asystem.iocache.writebacks::total 106694 # number of writebacks 133011570SCurtis.Dunham@arm.comsystem.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 133111606Sandreas.sandberg@arm.comsystem.l2c.tags.replacements 1924793 # number of replacements 133211606Sandreas.sandberg@arm.comsystem.l2c.tags.tagsinuse 65250.197909 # Cycle average of tags in use 133311606Sandreas.sandberg@arm.comsystem.l2c.tags.total_refs 5713780 # Total number of references to valid blocks. 133411606Sandreas.sandberg@arm.comsystem.l2c.tags.sampled_refs 1986359 # Sample count of references to valid blocks. 133511606Sandreas.sandberg@arm.comsystem.l2c.tags.avg_refs 2.876509 # Average number of references to valid blocks. 133611606Sandreas.sandberg@arm.comsystem.l2c.tags.warmup_cycle 477350500 # Cycle when the warmup percentage was hit. 133711606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::writebacks 10662.392220 # Average occupied blocks per requestor 133811606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 41.728586 # Average occupied blocks per requestor 133911606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 44.787257 # Average occupied blocks per requestor 134011606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 3175.849688 # Average occupied blocks per requestor 134111606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 15990.343630 # Average occupied blocks per requestor 134211606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 362.595804 # Average occupied blocks per requestor 134311606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 421.087250 # Average occupied blocks per requestor 134411606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 2804.760651 # Average occupied blocks per requestor 134511606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 31746.652822 # Average occupied blocks per requestor 134611606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::writebacks 0.162695 # Average percentage of cache occupancy 134711606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.000637 # Average percentage of cache occupancy 134811606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.000683 # Average percentage of cache occupancy 134911606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.048460 # Average percentage of cache occupancy 135011606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.243993 # Average percentage of cache occupancy 135111606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.005533 # Average percentage of cache occupancy 135211606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.006425 # Average percentage of cache occupancy 135311606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.042797 # Average percentage of cache occupancy 135411606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.484415 # Average percentage of cache occupancy 135511606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::total 0.995639 # Average percentage of cache occupancy 135611606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 224 # Occupied blocks per task id 135711606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 61342 # Occupied blocks per task id 135811570SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 135911606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 223 # Occupied blocks per task id 136011606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id 136111606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id 136211606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 3566 # Occupied blocks per task id 136311606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 4579 # Occupied blocks per task id 136411606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 52911 # Occupied blocks per task id 136511606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.003418 # Percentage of cache occupancy per task id 136611606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.936005 # Percentage of cache occupancy per task id 136711606Sandreas.sandberg@arm.comsystem.l2c.tags.tag_accesses 71904156 # Number of tag accesses 136811606Sandreas.sandberg@arm.comsystem.l2c.tags.data_accesses 71904156 # Number of data accesses 136911570SCurtis.Dunham@arm.comsystem.l2c.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 137011606Sandreas.sandberg@arm.comsystem.l2c.WritebackDirty_hits::writebacks 2750852 # number of WritebackDirty hits 137111606Sandreas.sandberg@arm.comsystem.l2c.WritebackDirty_hits::total 2750852 # number of WritebackDirty hits 137211606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 60132 # number of UpgradeReq hits 137311606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 51539 # number of UpgradeReq hits 137411606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_hits::total 111671 # number of UpgradeReq hits 137511606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 8500 # number of SCUpgradeReq hits 137611606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 7695 # number of SCUpgradeReq hits 137711606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_hits::total 16195 # number of SCUpgradeReq hits 137811606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 199510 # number of ReadExReq hits 137911606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 176557 # number of ReadExReq hits 138011606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_hits::total 376067 # number of ReadExReq hits 138111606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 12368 # number of ReadSharedReq hits 138211606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 5246 # number of ReadSharedReq hits 138311606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 435137 # number of ReadSharedReq hits 138411606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 707607 # number of ReadSharedReq hits 138511606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 12105 # number of ReadSharedReq hits 138611606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 4097 # number of ReadSharedReq hits 138711606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 413141 # number of ReadSharedReq hits 138811606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 664483 # number of ReadSharedReq hits 138911606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::total 2254184 # number of ReadSharedReq hits 139011606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_hits::cpu0.data 130356 # number of InvalidateReq hits 139111606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_hits::cpu1.data 113567 # number of InvalidateReq hits 139211606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_hits::total 243923 # number of InvalidateReq hits 139311606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 12368 # number of demand (read+write) hits 139411606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 5246 # number of demand (read+write) hits 139511606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu0.inst 435137 # number of demand (read+write) hits 139611606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu0.data 907117 # number of demand (read+write) hits 139711606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 12105 # number of demand (read+write) hits 139811606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 4097 # number of demand (read+write) hits 139911606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu1.inst 413141 # number of demand (read+write) hits 140011606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu1.data 841040 # number of demand (read+write) hits 140111606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::total 2630251 # number of demand (read+write) hits 140211606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 12368 # number of overall hits 140311606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 5246 # number of overall hits 140411606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu0.inst 435137 # number of overall hits 140511606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu0.data 907117 # number of overall hits 140611606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 12105 # number of overall hits 140711606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 4097 # number of overall hits 140811606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu1.inst 413141 # number of overall hits 140911606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu1.data 841040 # number of overall hits 141011606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::total 2630251 # number of overall hits 141111606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 21889 # number of UpgradeReq misses 141211606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 25427 # number of UpgradeReq misses 141311606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_misses::total 47316 # number of UpgradeReq misses 141411606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 415 # number of SCUpgradeReq misses 141511606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 794 # number of SCUpgradeReq misses 141611606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_misses::total 1209 # number of SCUpgradeReq misses 141711606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 372583 # number of ReadExReq misses 141811606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 420111 # number of ReadExReq misses 141911606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_misses::total 792694 # number of ReadExReq misses 142011606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2419 # number of ReadSharedReq misses 142111606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 2002 # number of ReadSharedReq misses 142211606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 63535 # number of ReadSharedReq misses 142311606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 191729 # number of ReadSharedReq misses 142411606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3502 # number of ReadSharedReq misses 142511606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.itb.walker 3484 # number of ReadSharedReq misses 142611606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 47028 # number of ReadSharedReq misses 142711606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 197713 # number of ReadSharedReq misses 142811606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::total 511412 # number of ReadSharedReq misses 142911606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_misses::cpu0.data 462716 # number of InvalidateReq misses 143011606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_misses::cpu1.data 149158 # number of InvalidateReq misses 143111606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_misses::total 611874 # number of InvalidateReq misses 143211606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 2419 # number of demand (read+write) misses 143311606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 2002 # number of demand (read+write) misses 143411606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu0.inst 63535 # number of demand (read+write) misses 143511606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu0.data 564312 # number of demand (read+write) misses 143611606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 3502 # number of demand (read+write) misses 143711606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu1.itb.walker 3484 # number of demand (read+write) misses 143811606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu1.inst 47028 # number of demand (read+write) misses 143911606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu1.data 617824 # number of demand (read+write) misses 144011606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::total 1304106 # number of demand (read+write) misses 144111606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 2419 # number of overall misses 144211606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 2002 # number of overall misses 144311606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu0.inst 63535 # number of overall misses 144411606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu0.data 564312 # number of overall misses 144511606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 3502 # number of overall misses 144611606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu1.itb.walker 3484 # number of overall misses 144711606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu1.inst 47028 # number of overall misses 144811606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu1.data 617824 # number of overall misses 144911606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::total 1304106 # number of overall misses 145011606Sandreas.sandberg@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 2750852 # number of WritebackDirty accesses(hits+misses) 145111606Sandreas.sandberg@arm.comsystem.l2c.WritebackDirty_accesses::total 2750852 # number of WritebackDirty accesses(hits+misses) 145211606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 82021 # number of UpgradeReq accesses(hits+misses) 145311606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 76966 # number of UpgradeReq accesses(hits+misses) 145411606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_accesses::total 158987 # number of UpgradeReq accesses(hits+misses) 145511606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 8915 # number of SCUpgradeReq accesses(hits+misses) 145611606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 8489 # number of SCUpgradeReq accesses(hits+misses) 145711606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_accesses::total 17404 # number of SCUpgradeReq accesses(hits+misses) 145811606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 572093 # number of ReadExReq accesses(hits+misses) 145911606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 596668 # number of ReadExReq accesses(hits+misses) 146011606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_accesses::total 1168761 # number of ReadExReq accesses(hits+misses) 146111606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 14787 # number of ReadSharedReq accesses(hits+misses) 146211606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7248 # number of ReadSharedReq accesses(hits+misses) 146311606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 498672 # number of ReadSharedReq accesses(hits+misses) 146411606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 899336 # number of ReadSharedReq accesses(hits+misses) 146511606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 15607 # number of ReadSharedReq accesses(hits+misses) 146611606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7581 # number of ReadSharedReq accesses(hits+misses) 146711606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 460169 # number of ReadSharedReq accesses(hits+misses) 146811606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 862196 # number of ReadSharedReq accesses(hits+misses) 146911606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::total 2765596 # number of ReadSharedReq accesses(hits+misses) 147011606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_accesses::cpu0.data 593072 # number of InvalidateReq accesses(hits+misses) 147111606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_accesses::cpu1.data 262725 # number of InvalidateReq accesses(hits+misses) 147211606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_accesses::total 855797 # number of InvalidateReq accesses(hits+misses) 147311606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 14787 # number of demand (read+write) accesses 147411606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 7248 # number of demand (read+write) accesses 147511606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu0.inst 498672 # number of demand (read+write) accesses 147611606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu0.data 1471429 # number of demand (read+write) accesses 147711606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 15607 # number of demand (read+write) accesses 147811606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 7581 # number of demand (read+write) accesses 147911606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu1.inst 460169 # number of demand (read+write) accesses 148011606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu1.data 1458864 # number of demand (read+write) accesses 148111606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::total 3934357 # number of demand (read+write) accesses 148211606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 14787 # number of overall (read+write) accesses 148311606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 7248 # number of overall (read+write) accesses 148411606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu0.inst 498672 # number of overall (read+write) accesses 148511606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu0.data 1471429 # number of overall (read+write) accesses 148611606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 15607 # number of overall (read+write) accesses 148711606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 7581 # number of overall (read+write) accesses 148811606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu1.inst 460169 # number of overall (read+write) accesses 148911606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu1.data 1458864 # number of overall (read+write) accesses 149011606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::total 3934357 # number of overall (read+write) accesses 149111606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.266871 # miss rate for UpgradeReq accesses 149211606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.330367 # miss rate for UpgradeReq accesses 149311606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.297609 # miss rate for UpgradeReq accesses 149411606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.046551 # miss rate for SCUpgradeReq accesses 149511606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.093533 # miss rate for SCUpgradeReq accesses 149611606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.069467 # miss rate for SCUpgradeReq accesses 149711606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.651263 # miss rate for ReadExReq accesses 149811606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.704095 # miss rate for ReadExReq accesses 149911606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.678234 # miss rate for ReadExReq accesses 150011606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.163590 # miss rate for ReadSharedReq accesses 150111606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.276214 # miss rate for ReadSharedReq accesses 150211606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.127408 # miss rate for ReadSharedReq accesses 150311606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.213190 # miss rate for ReadSharedReq accesses 150411606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.224386 # miss rate for ReadSharedReq accesses 150511606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.459570 # miss rate for ReadSharedReq accesses 150611606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.102197 # miss rate for ReadSharedReq accesses 150711606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.229313 # miss rate for ReadSharedReq accesses 150811606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.184919 # miss rate for ReadSharedReq accesses 150911606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu0.data 0.780202 # miss rate for InvalidateReq accesses 151011606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu1.data 0.567734 # miss rate for InvalidateReq accesses 151111606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_miss_rate::total 0.714976 # miss rate for InvalidateReq accesses 151211606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.163590 # miss rate for demand accesses 151311606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.276214 # miss rate for demand accesses 151411606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.127408 # miss rate for demand accesses 151511606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.383513 # miss rate for demand accesses 151611606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.224386 # miss rate for demand accesses 151711606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.459570 # miss rate for demand accesses 151811606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.102197 # miss rate for demand accesses 151911606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.423497 # miss rate for demand accesses 152011606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::total 0.331466 # miss rate for demand accesses 152111606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.163590 # miss rate for overall accesses 152211606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.276214 # miss rate for overall accesses 152311606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.127408 # miss rate for overall accesses 152411606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.383513 # miss rate for overall accesses 152511606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.224386 # miss rate for overall accesses 152611606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.459570 # miss rate for overall accesses 152711606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.102197 # miss rate for overall accesses 152811606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.423497 # miss rate for overall accesses 152911606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::total 0.331466 # miss rate for overall accesses 153010515SN/Asystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 153110515SN/Asystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 153210515SN/Asystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 153310515SN/Asystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 153410515SN/Asystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 153510515SN/Asystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 153611606Sandreas.sandberg@arm.comsystem.l2c.writebacks::writebacks 1492845 # number of writebacks 153711606Sandreas.sandberg@arm.comsystem.l2c.writebacks::total 1492845 # number of writebacks 153811606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_requests 4436915 # Total number of requests made to the snoop filter. 153911606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_requests 2508187 # Number of requests hitting in the snoop filter with a single holder of the requested data. 154011606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_requests 3478 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 154111502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 154211502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 154311502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 154411570SCurtis.Dunham@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 154511570SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadReq 82130 # Transaction distribution 154611606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadResp 602460 # Transaction distribution 154711570SCurtis.Dunham@arm.comsystem.membus.trans_dist::WriteReq 38798 # Transaction distribution 154811570SCurtis.Dunham@arm.comsystem.membus.trans_dist::WriteResp 38798 # Transaction distribution 154911606Sandreas.sandberg@arm.comsystem.membus.trans_dist::WritebackDirty 1599539 # Transaction distribution 155011606Sandreas.sandberg@arm.comsystem.membus.trans_dist::CleanEvict 267122 # Transaction distribution 155111606Sandreas.sandberg@arm.comsystem.membus.trans_dist::UpgradeReq 245150 # Transaction distribution 155211606Sandreas.sandberg@arm.comsystem.membus.trans_dist::SCUpgradeReq 295293 # Transaction distribution 155311606Sandreas.sandberg@arm.comsystem.membus.trans_dist::UpgradeResp 53835 # Transaction distribution 155411606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadExReq 792754 # Transaction distribution 155511606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadExResp 789263 # Transaction distribution 155611606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadSharedReq 520330 # Transaction distribution 155711606Sandreas.sandberg@arm.comsystem.membus.trans_dist::InvalidateReq 716726 # Transaction distribution 155811606Sandreas.sandberg@arm.comsystem.membus.trans_dist::InvalidateResp 716726 # Transaction distribution 155911502SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122576 # Packet count per connected master and slave (bytes) 156010585SN/Asystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 156111570SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27542 # Packet count per connected master and slave (bytes) 156211606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6261826 # Packet count per connected master and slave (bytes) 156311606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 6412036 # Packet count per connected master and slave (bytes) 156411502SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346888 # Packet count per connected master and slave (bytes) 156511502SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 346888 # Packet count per connected master and slave (bytes) 156611606Sandreas.sandberg@arm.comsystem.membus.pkt_count::total 6758924 # Packet count per connected master and slave (bytes) 156711502SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155683 # Cumulative packet size per connected master and slave (bytes) 156810585SN/Asystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 156911570SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55084 # Cumulative packet size per connected master and slave (bytes) 157011606Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 178979036 # Cumulative packet size per connected master and slave (bytes) 157111606Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 179190007 # Cumulative packet size per connected master and slave (bytes) 157211502SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7399168 # Cumulative packet size per connected master and slave (bytes) 157311502SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7399168 # Cumulative packet size per connected master and slave (bytes) 157411606Sandreas.sandberg@arm.comsystem.membus.pkt_size::total 186589175 # Cumulative packet size per connected master and slave (bytes) 157510585SN/Asystem.membus.snoops 0 # Total snoops (count) 157611570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 157711606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::samples 4557842 # Request fanout histogram 157811606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::mean 0.007340 # Request fanout histogram 157911606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::stdev 0.085359 # Request fanout histogram 158010585SN/Asystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 158111606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::0 4524387 99.27% 99.27% # Request fanout histogram 158211606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::1 33455 0.73% 100.00% # Request fanout histogram 158310585SN/Asystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 158410585SN/Asystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 158511502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 158610585SN/Asystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 158711606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::total 4557842 # Request fanout histogram 158811570SCurtis.Dunham@arm.comsystem.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 158911570SCurtis.Dunham@arm.comsystem.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 159011570SCurtis.Dunham@arm.comsystem.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 159111570SCurtis.Dunham@arm.comsystem.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 159211570SCurtis.Dunham@arm.comsystem.realview.gic.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 159311570SCurtis.Dunham@arm.comsystem.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 159411570SCurtis.Dunham@arm.comsystem.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 159511239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 159611239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 159711239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 159811239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 159911239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 160011239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 160111570SCurtis.Dunham@arm.comsystem.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 160211570SCurtis.Dunham@arm.comsystem.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 160310515SN/Asystem.realview.ethernet.txBytes 966 # Bytes Transmitted 160410515SN/Asystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 160510515SN/Asystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 160610515SN/Asystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 160710515SN/Asystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 160810515SN/Asystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 160910515SN/Asystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 161010515SN/Asystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 161110515SN/Asystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 161211570SCurtis.Dunham@arm.comsystem.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 161310515SN/Asystem.realview.ethernet.totPackets 3 # Total Packets 161410515SN/Asystem.realview.ethernet.totBytes 966 # Total Bytes 161510515SN/Asystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 161611570SCurtis.Dunham@arm.comsystem.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 161710515SN/Asystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 161810515SN/Asystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 161910515SN/Asystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 162010515SN/Asystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 162110515SN/Asystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 162210515SN/Asystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 162310515SN/Asystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 162410515SN/Asystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 162510515SN/Asystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 162610515SN/Asystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 162710515SN/Asystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 162810515SN/Asystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 162910515SN/Asystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 163010515SN/Asystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 163110515SN/Asystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 163210515SN/Asystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 163310515SN/Asystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 163410515SN/Asystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 163510515SN/Asystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 163610515SN/Asystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 163710515SN/Asystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 163810515SN/Asystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 163910515SN/Asystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 164010515SN/Asystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 164110515SN/Asystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 164210515SN/Asystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 164310515SN/Asystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 164410515SN/Asystem.realview.ethernet.droppedPackets 0 # number of packets dropped 164511570SCurtis.Dunham@arm.comsystem.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 164611570SCurtis.Dunham@arm.comsystem.realview.ide.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 164711570SCurtis.Dunham@arm.comsystem.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 164811570SCurtis.Dunham@arm.comsystem.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 164911570SCurtis.Dunham@arm.comsystem.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 165011570SCurtis.Dunham@arm.comsystem.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 165111570SCurtis.Dunham@arm.comsystem.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 165211239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 165311239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 165411239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 165511239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 165611570SCurtis.Dunham@arm.comsystem.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 165711570SCurtis.Dunham@arm.comsystem.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 165811570SCurtis.Dunham@arm.comsystem.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 165911570SCurtis.Dunham@arm.comsystem.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 166011570SCurtis.Dunham@arm.comsystem.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 166111570SCurtis.Dunham@arm.comsystem.realview.uart.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 166211570SCurtis.Dunham@arm.comsystem.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 166311570SCurtis.Dunham@arm.comsystem.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 166411570SCurtis.Dunham@arm.comsystem.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 166511570SCurtis.Dunham@arm.comsystem.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 166611570SCurtis.Dunham@arm.comsystem.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 166711570SCurtis.Dunham@arm.comsystem.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 166811606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_filter.tot_requests 11075061 # Total number of requests made to the snoop filter. 166911606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 5706480 # Number of requests hitting in the snoop filter with a single holder of the requested data. 167011606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 1648775 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 167111606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 269190 # Total number of snoops made to the snoop filter. 167211606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 248390 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 167311606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 20800 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 167411570SCurtis.Dunham@arm.comsystem.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 167511570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadReq 82132 # Transaction distribution 167611606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::ReadResp 3544615 # Transaction distribution 167711570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WriteReq 38798 # Transaction distribution 167811570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WriteResp 38798 # Transaction distribution 167911606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 2750852 # Transaction distribution 168011606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::CleanEvict 1991304 # Transaction distribution 168111606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 351511 # Transaction distribution 168211606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 311488 # Transaction distribution 168311606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 662999 # Transaction distribution 168411606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::ReadExReq 1351623 # Transaction distribution 168511606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::ReadExResp 1351623 # Transaction distribution 168611606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 3462483 # Transaction distribution 168711606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::InvalidateReq 855797 # Transaction distribution 168811606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::InvalidateResp 855797 # Transaction distribution 168911606Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9483041 # Packet count per connected master and slave (bytes) 169011606Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8166779 # Packet count per connected master and slave (bytes) 169111606Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_count::total 17649820 # Packet count per connected master and slave (bytes) 169211606Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 254997904 # Cumulative packet size per connected master and slave (bytes) 169311606Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 229564151 # Cumulative packet size per connected master and slave (bytes) 169411606Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_size::total 484562055 # Cumulative packet size per connected master and slave (bytes) 169511606Sandreas.sandberg@arm.comsystem.toL2Bus.snoops 1959256 # Total snoops (count) 169611606Sandreas.sandberg@arm.comsystem.toL2Bus.snoopTraffic 95582592 # Total snoop traffic (bytes) 169711606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::samples 13153559 # Request fanout histogram 169811606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::mean 0.293824 # Request fanout histogram 169911606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.458971 # Request fanout histogram 170010515SN/Asystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 170111606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::0 9309527 70.78% 70.78% # Request fanout histogram 170211606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::1 3823232 29.07% 99.84% # Request fanout histogram 170311606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::2 20800 0.16% 100.00% # Request fanout histogram 170410515SN/Asystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 170511138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 170610515SN/Asystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 170711606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::total 13153559 # Request fanout histogram 170810515SN/A 170910515SN/A---------- End Simulation Statistics ---------- 1710