stats.txt revision 11530
110515SN/A 210515SN/A---------- Begin Simulation Statistics ---------- 311502SCurtis.Dunham@arm.comsim_seconds 47.216815 # Number of seconds simulated 411502SCurtis.Dunham@arm.comsim_ticks 47216814802000 # Number of ticks simulated 511502SCurtis.Dunham@arm.comfinal_tick 47216814802000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711530Sandreas.sandberg@arm.comhost_inst_rate 1563637 # Simulator instruction rate (inst/s) 811530Sandreas.sandberg@arm.comhost_op_rate 1839381 # Simulator op (including micro ops) rate (op/s) 911530Sandreas.sandberg@arm.comhost_tick_rate 75563871924 # Simulator tick rate (ticks/s) 1011530Sandreas.sandberg@arm.comhost_mem_usage 737620 # Number of bytes of host memory used 1111530Sandreas.sandberg@arm.comhost_seconds 624.86 # Real time elapsed on the host 1211502SCurtis.Dunham@arm.comsim_insts 977053655 # Number of instructions simulated 1311502SCurtis.Dunham@arm.comsim_ops 1149354696 # Number of ops (including micro ops) simulated 1410515SN/Asystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SN/Asystem.clk_domain.clock 1000 # Clock period in ticks 1611530Sandreas.sandberg@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 1711502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 150336 # Number of bytes read from this memory 1811502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 124416 # Number of bytes read from this memory 1911502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.inst 3895860 # Number of bytes read from this memory 2011502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.data 34948936 # Number of bytes read from this memory 2111502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 222016 # Number of bytes read from this memory 2211502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.itb.walker 222656 # Number of bytes read from this memory 2311502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.inst 2668232 # Number of bytes read from this memory 2411502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.data 38725552 # Number of bytes read from this memory 2511502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::realview.ide 417728 # Number of bytes read from this memory 2611502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 81375732 # Number of bytes read from this memory 2711502SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 3895860 # Number of instructions bytes read from this memory 2811502SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 2668232 # Number of instructions bytes read from this memory 2911502SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 6564092 # Number of instructions bytes read from this memory 3011502SCurtis.Dunham@arm.comsystem.physmem.bytes_written::writebacks 101375872 # Number of bytes written to this memory 3110827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 3210585SN/Asystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3311502SCurtis.Dunham@arm.comsystem.physmem.bytes_written::total 101396456 # Number of bytes written to this memory 3411502SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 2349 # Number of read requests responded to by this memory 3511502SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.itb.walker 1944 # Number of read requests responded to by this memory 3611502SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.inst 101280 # Number of read requests responded to by this memory 3711502SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.data 546090 # Number of read requests responded to by this memory 3811502SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 3469 # Number of read requests responded to by this memory 3911502SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.itb.walker 3479 # Number of read requests responded to by this memory 4011502SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.inst 41798 # Number of read requests responded to by this memory 4111502SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.data 605103 # Number of read requests responded to by this memory 4211502SCurtis.Dunham@arm.comsystem.physmem.num_reads::realview.ide 6527 # Number of read requests responded to by this memory 4311502SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 1312039 # Number of read requests responded to by this memory 4411502SCurtis.Dunham@arm.comsystem.physmem.num_writes::writebacks 1583998 # Number of write requests responded to by this memory 4510827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 4610585SN/Asystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 4711502SCurtis.Dunham@arm.comsystem.physmem.num_writes::total 1586572 # Number of write requests responded to by this memory 4811502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 3184 # Total read bandwidth from this memory (bytes/s) 4911502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.itb.walker 2635 # Total read bandwidth from this memory (bytes/s) 5011502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.inst 82510 # Total read bandwidth from this memory (bytes/s) 5111502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.data 740180 # Total read bandwidth from this memory (bytes/s) 5211502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 4702 # Total read bandwidth from this memory (bytes/s) 5311502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.itb.walker 4716 # Total read bandwidth from this memory (bytes/s) 5411502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.inst 56510 # Total read bandwidth from this memory (bytes/s) 5511502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.data 820164 # Total read bandwidth from this memory (bytes/s) 5611502SCurtis.Dunham@arm.comsystem.physmem.bw_read::realview.ide 8847 # Total read bandwidth from this memory (bytes/s) 5711502SCurtis.Dunham@arm.comsystem.physmem.bw_read::total 1723448 # Total read bandwidth from this memory (bytes/s) 5811502SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu0.inst 82510 # Instruction read bandwidth from this memory (bytes/s) 5911502SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu1.inst 56510 # Instruction read bandwidth from this memory (bytes/s) 6011502SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::total 139020 # Instruction read bandwidth from this memory (bytes/s) 6111502SCurtis.Dunham@arm.comsystem.physmem.bw_write::writebacks 2147029 # Write bandwidth from this memory (bytes/s) 6211502SCurtis.Dunham@arm.comsystem.physmem.bw_write::cpu0.data 436 # Write bandwidth from this memory (bytes/s) 6310585SN/Asystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 6411502SCurtis.Dunham@arm.comsystem.physmem.bw_write::total 2147465 # Write bandwidth from this memory (bytes/s) 6511502SCurtis.Dunham@arm.comsystem.physmem.bw_total::writebacks 2147029 # Total bandwidth to/from this memory (bytes/s) 6611502SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 3184 # Total bandwidth to/from this memory (bytes/s) 6711502SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.itb.walker 2635 # Total bandwidth to/from this memory (bytes/s) 6811502SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.inst 82510 # Total bandwidth to/from this memory (bytes/s) 6911502SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.data 740616 # Total bandwidth to/from this memory (bytes/s) 7011502SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 4702 # Total bandwidth to/from this memory (bytes/s) 7111502SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.itb.walker 4716 # Total bandwidth to/from this memory (bytes/s) 7211502SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.inst 56510 # Total bandwidth to/from this memory (bytes/s) 7311502SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.data 820165 # Total bandwidth to/from this memory (bytes/s) 7411502SCurtis.Dunham@arm.comsystem.physmem.bw_total::realview.ide 8847 # Total bandwidth to/from this memory (bytes/s) 7511502SCurtis.Dunham@arm.comsystem.physmem.bw_total::total 3870913 # Total bandwidth to/from this memory (bytes/s) 7611530Sandreas.sandberg@arm.comsystem.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 7710515SN/Asystem.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 7810515SN/Asystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 7910515SN/Asystem.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 8010515SN/Asystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 8110515SN/Asystem.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 8210515SN/Asystem.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 8310515SN/Asystem.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 8410515SN/Asystem.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 8510515SN/Asystem.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 8610515SN/Asystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 8710515SN/Asystem.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 8810515SN/Asystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 8910515SN/Asystem.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 9010515SN/Asystem.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 9110515SN/Asystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 9210515SN/Asystem.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 9310515SN/Asystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 9410515SN/Asystem.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 9510515SN/Asystem.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 9610515SN/Asystem.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 9710515SN/Asystem.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 9810515SN/Asystem.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 9910515SN/Asystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 10010515SN/Asystem.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 10110515SN/Asystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 10210515SN/Asystem.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 10311530Sandreas.sandberg@arm.comsystem.realview.vram.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 10411530Sandreas.sandberg@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 10511530Sandreas.sandberg@arm.comsystem.bridge.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 10610585SN/Asystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 10710585SN/Asystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 10810585SN/Asystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 10910585SN/Asystem.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 11010585SN/Asystem.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 11110585SN/Asystem.cf0.dma_write_txs 1670 # Number of DMA write transactions. 11210515SN/Asystem.cpu_clk_domain.clock 500 # Clock period in ticks 11311530Sandreas.sandberg@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 11410628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 11510628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 11610628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 11710628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 11810628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 11910628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 12010628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 12110628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 12210585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 12310585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 12410585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 12510585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 12610585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 12710585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 12810585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 12910585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 13010585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 13110585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 13210585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 13310585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 13410585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 13510585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 13610585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 13710585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 13810585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 13910585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 14010585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 14110585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 14210585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 14311530Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 14411502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walks 124420 # Table walker walks requested 14511502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksLong 124420 # Table walker walks initiated with long descriptors 14611502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 124420 # Table walker wait (enqueue to first request) latency 14711502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0 124420 100.00% 100.00% # Table walker wait (enqueue to first request) latency 14811502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 124420 # Table walker wait (enqueue to first request) latency 14910628SN/Asystem.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution 15010628SN/Asystem.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution 15110628SN/Asystem.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution 15211502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 95857 89.92% 89.92% # Table walker page sizes translated 15311502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkPageSizes::2M 10751 10.08% 100.00% # Table walker page sizes translated 15411502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 106608 # Table walker page sizes translated 15511502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 124420 # Table walker requests started/completed, data/inst 15610628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 15711502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 124420 # Table walker requests started/completed, data/inst 15811502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106608 # Table walker requests started/completed, data/inst 15910628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 16011502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106608 # Table walker requests started/completed, data/inst 16111502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 231028 # Table walker requests started/completed, data/inst 16210585SN/Asystem.cpu0.dtb.inst_hits 0 # ITB inst hits 16310585SN/Asystem.cpu0.dtb.inst_misses 0 # ITB inst misses 16411502SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_hits 91801710 # DTB read hits 16511502SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_misses 88193 # DTB read misses 16611502SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_hits 84999619 # DTB write hits 16711502SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_misses 36227 # DTB write misses 16810585SN/Asystem.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed 16910585SN/Asystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 17011502SCurtis.Dunham@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID 17110585SN/Asystem.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 17211502SCurtis.Dunham@arm.comsystem.cpu0.dtb.flush_entries 36369 # Number of entries that have been flushed from TLB 17310585SN/Asystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 17411502SCurtis.Dunham@arm.comsystem.cpu0.dtb.prefetch_faults 5198 # Number of TLB faults due to prefetch 17510585SN/Asystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 17611502SCurtis.Dunham@arm.comsystem.cpu0.dtb.perms_faults 10393 # Number of TLB faults due to permissions restrictions 17711502SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_accesses 91889903 # DTB read accesses 17811502SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_accesses 85035846 # DTB write accesses 17910585SN/Asystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 18011502SCurtis.Dunham@arm.comsystem.cpu0.dtb.hits 176801329 # DTB hits 18111502SCurtis.Dunham@arm.comsystem.cpu0.dtb.misses 124420 # DTB misses 18211502SCurtis.Dunham@arm.comsystem.cpu0.dtb.accesses 176925749 # DTB accesses 18311530Sandreas.sandberg@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 18410628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 18510628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 18610628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 18710628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 18810628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 18910628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 19010628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 19110628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 19210585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 19310585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 19410585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 19510585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 19610585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 19710585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 19810585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 19910585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 20010585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 20110585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 20210585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 20310585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 20410585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 20510585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 20610585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 20710585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 20810585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 20910585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 21010585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 21110585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 21210585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 21311530Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 21411502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walks 60852 # Table walker walks requested 21511502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksLong 60852 # Table walker walks initiated with long descriptors 21611502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 60852 # Table walker wait (enqueue to first request) latency 21711502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkWaitTime::0 60852 100.00% 100.00% # Table walker wait (enqueue to first request) latency 21811502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 60852 # Table walker wait (enqueue to first request) latency 21910628SN/Asystem.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution 22010628SN/Asystem.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution 22110628SN/Asystem.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution 22211502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 54793 98.83% 98.83% # Table walker page sizes translated 22311502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkPageSizes::2M 650 1.17% 100.00% # Table walker page sizes translated 22411502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 55443 # Table walker page sizes translated 22510628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 22611502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60852 # Table walker requests started/completed, data/inst 22711502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 60852 # Table walker requests started/completed, data/inst 22810628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 22911502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55443 # Table walker requests started/completed, data/inst 23011502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 55443 # Table walker requests started/completed, data/inst 23111502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 116295 # Table walker requests started/completed, data/inst 23211502SCurtis.Dunham@arm.comsystem.cpu0.itb.inst_hits 493637993 # ITB inst hits 23311502SCurtis.Dunham@arm.comsystem.cpu0.itb.inst_misses 60852 # ITB inst misses 23410585SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 23510585SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 23610585SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 23710585SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 23810585SN/Asystem.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed 23910585SN/Asystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 24011502SCurtis.Dunham@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID 24110585SN/Asystem.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 24211502SCurtis.Dunham@arm.comsystem.cpu0.itb.flush_entries 25117 # Number of entries that have been flushed from TLB 24310585SN/Asystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 24410585SN/Asystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 24510585SN/Asystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 24610585SN/Asystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 24710585SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 24810585SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 24911502SCurtis.Dunham@arm.comsystem.cpu0.itb.inst_accesses 493698845 # ITB inst accesses 25011502SCurtis.Dunham@arm.comsystem.cpu0.itb.hits 493637993 # DTB hits 25111502SCurtis.Dunham@arm.comsystem.cpu0.itb.misses 60852 # DTB misses 25211502SCurtis.Dunham@arm.comsystem.cpu0.itb.accesses 493698845 # DTB accesses 25311530Sandreas.sandberg@arm.comsystem.cpu0.numPwrStateTransitions 26456 # Number of power state transitions 25411530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::samples 13226 # Distribution of time spent in the clock gated state 25511530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::mean 3548051502.510434 # Distribution of time spent in the clock gated state 25611530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::stdev 89670925641.729767 # Distribution of time spent in the clock gated state 25711530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::underflows 3168 23.95% 23.95% # Distribution of time spent in the clock gated state 25811530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::1000-5e+10 10031 75.84% 99.80% # Distribution of time spent in the clock gated state 25911530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.82% # Distribution of time spent in the clock gated state 26011530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 2 0.02% 99.83% # Distribution of time spent in the clock gated state 26111530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state 26211530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state 26311530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state 26411530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 2 0.02% 99.89% # Distribution of time spent in the clock gated state 26511530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 26611530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::overflows 14 0.11% 100.00% # Distribution of time spent in the clock gated state 26711530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 26811530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::max_value 7470356053852 # Distribution of time spent in the clock gated state 26911530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::total 13226 # Distribution of time spent in the clock gated state 27011530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateResidencyTicks::ON 290285629797 # Cumulative time (in ticks) in various power states 27111530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateResidencyTicks::CLK_GATED 46926529172203 # Cumulative time (in ticks) in various power states 27211502SCurtis.Dunham@arm.comsystem.cpu0.numCycles 94433642835 # number of cpu cycles simulated 27310585SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 27410585SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 27511167Sjthestness@gmail.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 27611502SCurtis.Dunham@arm.comsystem.cpu0.kern.inst.quiesce 13230 # number of quiesce instructions executed 27711502SCurtis.Dunham@arm.comsystem.cpu0.committedInsts 493402150 # Number of instructions committed 27811502SCurtis.Dunham@arm.comsystem.cpu0.committedOps 580232432 # Number of ops (including micro ops) committed 27911502SCurtis.Dunham@arm.comsystem.cpu0.num_int_alu_accesses 531778274 # Number of integer alu accesses 28011502SCurtis.Dunham@arm.comsystem.cpu0.num_fp_alu_accesses 521057 # Number of float alu accesses 28111502SCurtis.Dunham@arm.comsystem.cpu0.num_func_calls 28738017 # number of times a function call or return occured 28211502SCurtis.Dunham@arm.comsystem.cpu0.num_conditional_control_insts 75812609 # number of instructions that are conditional controls 28311502SCurtis.Dunham@arm.comsystem.cpu0.num_int_insts 531778274 # number of integer instructions 28411502SCurtis.Dunham@arm.comsystem.cpu0.num_fp_insts 521057 # number of float instructions 28511502SCurtis.Dunham@arm.comsystem.cpu0.num_int_register_reads 778807297 # number of times the integer registers were read 28611502SCurtis.Dunham@arm.comsystem.cpu0.num_int_register_writes 421918818 # number of times the integer registers were written 28711502SCurtis.Dunham@arm.comsystem.cpu0.num_fp_register_reads 841474 # number of times the floating registers were read 28811502SCurtis.Dunham@arm.comsystem.cpu0.num_fp_register_writes 439940 # number of times the floating registers were written 28911502SCurtis.Dunham@arm.comsystem.cpu0.num_cc_register_reads 132610797 # number of times the CC registers were read 29011502SCurtis.Dunham@arm.comsystem.cpu0.num_cc_register_writes 132275173 # number of times the CC registers were written 29111502SCurtis.Dunham@arm.comsystem.cpu0.num_mem_refs 176902115 # number of memory refs 29211502SCurtis.Dunham@arm.comsystem.cpu0.num_load_insts 91875039 # Number of load instructions 29311502SCurtis.Dunham@arm.comsystem.cpu0.num_store_insts 85027076 # Number of store instructions 29411502SCurtis.Dunham@arm.comsystem.cpu0.num_idle_cycles 93853071494.060760 # Number of idle cycles 29511502SCurtis.Dunham@arm.comsystem.cpu0.num_busy_cycles 580571340.939238 # Number of busy cycles 29611502SCurtis.Dunham@arm.comsystem.cpu0.not_idle_fraction 0.006148 # Percentage of non-idle cycles 29711502SCurtis.Dunham@arm.comsystem.cpu0.idle_fraction 0.993852 # Percentage of idle cycles 29811502SCurtis.Dunham@arm.comsystem.cpu0.Branches 110403926 # Number of branches fetched 29910585SN/Asystem.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 30011502SCurtis.Dunham@arm.comsystem.cpu0.op_class::IntAlu 402310075 69.30% 69.30% # Class of executed instruction 30111502SCurtis.Dunham@arm.comsystem.cpu0.op_class::IntMult 1222689 0.21% 69.51% # Class of executed instruction 30211502SCurtis.Dunham@arm.comsystem.cpu0.op_class::IntDiv 59704 0.01% 69.52% # Class of executed instruction 30311336Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction 30411336Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction 30511336Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction 30611336Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction 30711336Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction 30811336Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction 30911336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction 31011336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction 31111336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction 31211336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction 31311336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction 31411336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction 31511336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction 31611336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction 31711336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction 31811336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction 31911336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction 32011336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAdd 8 0.00% 69.52% # Class of executed instruction 32111336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction 32211336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCmp 13 0.00% 69.52% # Class of executed instruction 32311336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCvt 21 0.00% 69.52% # Class of executed instruction 32411336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction 32511502SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatMisc 72217 0.01% 69.53% # Class of executed instruction 32611336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 69.53% # Class of executed instruction 32711336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.53% # Class of executed instruction 32811336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.53% # Class of executed instruction 32911502SCurtis.Dunham@arm.comsystem.cpu0.op_class::MemRead 91875039 15.83% 85.35% # Class of executed instruction 33011502SCurtis.Dunham@arm.comsystem.cpu0.op_class::MemWrite 85027076 14.65% 100.00% # Class of executed instruction 33110585SN/Asystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 33210585SN/Asystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 33311502SCurtis.Dunham@arm.comsystem.cpu0.op_class::total 580566843 # Class of executed instruction 33411530Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 33511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.replacements 6218107 # number of replacements 33611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.tagsinuse 503.352532 # Cycle average of tags in use 33711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.total_refs 170512705 # Total number of references to valid blocks. 33811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.sampled_refs 6218619 # Sample count of references to valid blocks. 33911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.avg_refs 27.419706 # Average number of references to valid blocks. 34010827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. 34111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 503.352532 # Average occupied blocks per requestor 34211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.983110 # Average percentage of cache occupancy 34311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.983110 # Average percentage of cache occupancy 34410585SN/Asystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 34511336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id 34611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id 34711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id 34810585SN/Asystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 34911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.tag_accesses 359988587 # Number of tag accesses 35011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.data_accesses 359988587 # Number of data accesses 35111530Sandreas.sandberg@arm.comsystem.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 35211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 85387960 # number of ReadReq hits 35311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_hits::total 85387960 # number of ReadReq hits 35411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 80242803 # number of WriteReq hits 35511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_hits::total 80242803 # number of WriteReq hits 35611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 214677 # number of SoftPFReq hits 35711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 214677 # number of SoftPFReq hits 35811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_hits::cpu0.data 260385 # number of WriteLineReq hits 35911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_hits::total 260385 # number of WriteLineReq hits 36011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2076595 # number of LoadLockedReq hits 36111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 2076595 # number of LoadLockedReq hits 36211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 2038168 # number of StoreCondReq hits 36311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 2038168 # number of StoreCondReq hits 36411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 165891148 # number of demand (read+write) hits 36511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_hits::total 165891148 # number of demand (read+write) hits 36611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 166105825 # number of overall hits 36711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_hits::total 166105825 # number of overall hits 36811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 3280646 # number of ReadReq misses 36911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_misses::total 3280646 # number of ReadReq misses 37011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 1472125 # number of WriteReq misses 37111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_misses::total 1472125 # number of WriteReq misses 37211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 768471 # number of SoftPFReq misses 37311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 768471 # number of SoftPFReq misses 37411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_misses::cpu0.data 819890 # number of WriteLineReq misses 37511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_misses::total 819890 # number of WriteLineReq misses 37611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 117360 # number of LoadLockedReq misses 37711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 117360 # number of LoadLockedReq misses 37811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 154684 # number of StoreCondReq misses 37911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 154684 # number of StoreCondReq misses 38011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 5572661 # number of demand (read+write) misses 38111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_misses::total 5572661 # number of demand (read+write) misses 38211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 6341132 # number of overall misses 38311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_misses::total 6341132 # number of overall misses 38411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 88668606 # number of ReadReq accesses(hits+misses) 38511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 88668606 # number of ReadReq accesses(hits+misses) 38611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 81714928 # number of WriteReq accesses(hits+misses) 38711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 81714928 # number of WriteReq accesses(hits+misses) 38811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 983148 # number of SoftPFReq accesses(hits+misses) 38911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 983148 # number of SoftPFReq accesses(hits+misses) 39011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1080275 # number of WriteLineReq accesses(hits+misses) 39111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::total 1080275 # number of WriteLineReq accesses(hits+misses) 39211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2193955 # number of LoadLockedReq accesses(hits+misses) 39311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 2193955 # number of LoadLockedReq accesses(hits+misses) 39411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2192852 # number of StoreCondReq accesses(hits+misses) 39511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 2192852 # number of StoreCondReq accesses(hits+misses) 39611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 171463809 # number of demand (read+write) accesses 39711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_accesses::total 171463809 # number of demand (read+write) accesses 39811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 172446957 # number of overall (read+write) accesses 39911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_accesses::total 172446957 # number of overall (read+write) accesses 40011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036999 # miss rate for ReadReq accesses 40111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.036999 # miss rate for ReadReq accesses 40211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018015 # miss rate for WriteReq accesses 40311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.018015 # miss rate for WriteReq accesses 40411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781643 # miss rate for SoftPFReq accesses 40511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.781643 # miss rate for SoftPFReq accesses 40611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.758964 # miss rate for WriteLineReq accesses 40711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::total 0.758964 # miss rate for WriteLineReq accesses 40811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053492 # miss rate for LoadLockedReq accesses 40911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053492 # miss rate for LoadLockedReq accesses 41011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.070540 # miss rate for StoreCondReq accesses 41111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.070540 # miss rate for StoreCondReq accesses 41211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.032501 # miss rate for demand accesses 41311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.032501 # miss rate for demand accesses 41411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.036771 # miss rate for overall accesses 41511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.036771 # miss rate for overall accesses 41610585SN/Asystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 41710585SN/Asystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 41810585SN/Asystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 41910585SN/Asystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 42010585SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 42110585SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 42211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.writebacks::writebacks 6218107 # number of writebacks 42311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.writebacks::total 6218107 # number of writebacks 42411530Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 42511502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.replacements 5488502 # number of replacements 42611502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.tagsinuse 511.989005 # Cycle average of tags in use 42711502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.total_refs 488204417 # Total number of references to valid blocks. 42811502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.sampled_refs 5489014 # Sample count of references to valid blocks. 42911502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.avg_refs 88.942097 # Average number of references to valid blocks. 43010585SN/Asystem.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit. 43111502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989005 # Average occupied blocks per requestor 43210585SN/Asystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy 43310585SN/Asystem.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy 43410585SN/Asystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 43511502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id 43611502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id 43711502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id 43811502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 43910585SN/Asystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 44011502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.tag_accesses 992875891 # Number of tag accesses 44111502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.data_accesses 992875891 # Number of data accesses 44211530Sandreas.sandberg@arm.comsystem.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 44311502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 488204417 # number of ReadReq hits 44411502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_hits::total 488204417 # number of ReadReq hits 44511502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 488204417 # number of demand (read+write) hits 44611502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_hits::total 488204417 # number of demand (read+write) hits 44711502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 488204417 # number of overall hits 44811502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_hits::total 488204417 # number of overall hits 44911502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 5489019 # number of ReadReq misses 45011502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_misses::total 5489019 # number of ReadReq misses 45111502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 5489019 # number of demand (read+write) misses 45211502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_misses::total 5489019 # number of demand (read+write) misses 45311502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 5489019 # number of overall misses 45411502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_misses::total 5489019 # number of overall misses 45511502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 493693436 # number of ReadReq accesses(hits+misses) 45611502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_accesses::total 493693436 # number of ReadReq accesses(hits+misses) 45711502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 493693436 # number of demand (read+write) accesses 45811502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_accesses::total 493693436 # number of demand (read+write) accesses 45911502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 493693436 # number of overall (read+write) accesses 46011502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_accesses::total 493693436 # number of overall (read+write) accesses 46111502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011118 # miss rate for ReadReq accesses 46211502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.011118 # miss rate for ReadReq accesses 46311502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.011118 # miss rate for demand accesses 46411502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.011118 # miss rate for demand accesses 46511502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.011118 # miss rate for overall accesses 46611502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.011118 # miss rate for overall accesses 46710585SN/Asystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 46810585SN/Asystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 46910585SN/Asystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 47010585SN/Asystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 47110585SN/Asystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 47210585SN/Asystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 47311502SCurtis.Dunham@arm.comsystem.cpu0.icache.writebacks::writebacks 5488502 # number of writebacks 47411502SCurtis.Dunham@arm.comsystem.cpu0.icache.writebacks::total 5488502 # number of writebacks 47511530Sandreas.sandberg@arm.comsystem.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 47610628SN/Asystem.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 47710628SN/Asystem.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 47810628SN/Asystem.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 47910628SN/Asystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 48010628SN/Asystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 48110628SN/Asystem.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 48211530Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 48311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.replacements 2643580 # number of replacements 48411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.tagsinuse 16147.870386 # Cycle average of tags in use 48511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.total_refs 15444293 # Total number of references to valid blocks. 48611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.sampled_refs 2659582 # Sample count of references to valid blocks. 48711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.avg_refs 5.807038 # Average number of references to valid blocks. 48810585SN/Asystem.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. 48911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 16070.787170 # Average occupied blocks per requestor 49011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 39.567916 # Average occupied blocks per requestor 49111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 37.515300 # Average occupied blocks per requestor 49211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.980883 # Average percentage of cache occupancy 49311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002415 # Average percentage of cache occupancy 49411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.002290 # Average percentage of cache occupancy 49511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.985588 # Average percentage of cache occupancy 49611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 53 # Occupied blocks per task id 49711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 15949 # Occupied blocks per task id 49811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 39 # Occupied blocks per task id 49911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id 50011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id 50111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id 50211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1503 # Occupied blocks per task id 50311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4323 # Occupied blocks per task id 50411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5407 # Occupied blocks per task id 50511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4485 # Occupied blocks per task id 50611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003235 # Percentage of cache occupancy per task id 50711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.973450 # Percentage of cache occupancy per task id 50811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.tag_accesses 394033422 # Number of tag accesses 50911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.data_accesses 394033422 # Number of data accesses 51011530Sandreas.sandberg@arm.comsystem.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 51111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 293436 # number of ReadReq hits 51211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 155846 # number of ReadReq hits 51311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 449282 # number of ReadReq hits 51411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::writebacks 4423360 # number of WritebackDirty hits 51511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::total 4423360 # number of WritebackDirty hits 51611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_hits::writebacks 7281875 # number of WritebackClean hits 51711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_hits::total 7281875 # number of WritebackClean hits 51811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::cpu0.data 738 # number of UpgradeReq hits 51911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::total 738 # number of UpgradeReq hits 52011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 633298 # number of ReadExReq hits 52111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 633298 # number of ReadExReq hits 52211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4991790 # number of ReadCleanReq hits 52311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 4991790 # number of ReadCleanReq hits 52411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2937635 # number of ReadSharedReq hits 52511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 2937635 # number of ReadSharedReq hits 52611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::cpu0.data 218374 # number of InvalidateReq hits 52711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::total 218374 # number of InvalidateReq hits 52811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 293436 # number of demand (read+write) hits 52911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 155846 # number of demand (read+write) hits 53011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 4991790 # number of demand (read+write) hits 53111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 3570933 # number of demand (read+write) hits 53211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::total 9012005 # number of demand (read+write) hits 53311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 293436 # number of overall hits 53411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 155846 # number of overall hits 53511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 4991790 # number of overall hits 53611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 3570933 # number of overall hits 53711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::total 9012005 # number of overall hits 53811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11306 # number of ReadReq misses 53911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8709 # number of ReadReq misses 54011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 20015 # number of ReadReq misses 54111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 136695 # number of UpgradeReq misses 54211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 136695 # number of UpgradeReq misses 54311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 154684 # number of SCUpgradeReq misses 54411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 154684 # number of SCUpgradeReq misses 54511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 701772 # number of ReadExReq misses 54611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 701772 # number of ReadExReq misses 54711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 497229 # number of ReadCleanReq misses 54811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 497229 # number of ReadCleanReq misses 54911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1228842 # number of ReadSharedReq misses 55011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 1228842 # number of ReadSharedReq misses 55111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::cpu0.data 601138 # number of InvalidateReq misses 55211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::total 601138 # number of InvalidateReq misses 55311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11306 # number of demand (read+write) misses 55411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 8709 # number of demand (read+write) misses 55511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 497229 # number of demand (read+write) misses 55611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 1930614 # number of demand (read+write) misses 55711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::total 2447858 # number of demand (read+write) misses 55811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11306 # number of overall misses 55911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 8709 # number of overall misses 56011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 497229 # number of overall misses 56111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 1930614 # number of overall misses 56211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::total 2447858 # number of overall misses 56311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 304742 # number of ReadReq accesses(hits+misses) 56411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 164555 # number of ReadReq accesses(hits+misses) 56511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 469297 # number of ReadReq accesses(hits+misses) 56611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::writebacks 4423360 # number of WritebackDirty accesses(hits+misses) 56711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::total 4423360 # number of WritebackDirty accesses(hits+misses) 56811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::writebacks 7281875 # number of WritebackClean accesses(hits+misses) 56911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::total 7281875 # number of WritebackClean accesses(hits+misses) 57011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 137433 # number of UpgradeReq accesses(hits+misses) 57111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 137433 # number of UpgradeReq accesses(hits+misses) 57211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 154684 # number of SCUpgradeReq accesses(hits+misses) 57311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 154684 # number of SCUpgradeReq accesses(hits+misses) 57411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1335070 # number of ReadExReq accesses(hits+misses) 57511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1335070 # number of ReadExReq accesses(hits+misses) 57611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5489019 # number of ReadCleanReq accesses(hits+misses) 57711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 5489019 # number of ReadCleanReq accesses(hits+misses) 57811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4166477 # number of ReadSharedReq accesses(hits+misses) 57911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 4166477 # number of ReadSharedReq accesses(hits+misses) 58011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 819512 # number of InvalidateReq accesses(hits+misses) 58111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::total 819512 # number of InvalidateReq accesses(hits+misses) 58211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 304742 # number of demand (read+write) accesses 58311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 164555 # number of demand (read+write) accesses 58411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 5489019 # number of demand (read+write) accesses 58511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 5501547 # number of demand (read+write) accesses 58611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::total 11459863 # number of demand (read+write) accesses 58711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 304742 # number of overall (read+write) accesses 58811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 164555 # number of overall (read+write) accesses 58911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 5489019 # number of overall (read+write) accesses 59011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 5501547 # number of overall (read+write) accesses 59111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::total 11459863 # number of overall (read+write) accesses 59211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.037100 # miss rate for ReadReq accesses 59311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052925 # miss rate for ReadReq accesses 59411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.042649 # miss rate for ReadReq accesses 59511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.994630 # miss rate for UpgradeReq accesses 59611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 0.994630 # miss rate for UpgradeReq accesses 59710585SN/Asystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 59810585SN/Asystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 59911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.525644 # miss rate for ReadExReq accesses 60011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.525644 # miss rate for ReadExReq accesses 60111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.090586 # miss rate for ReadCleanReq accesses 60211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.090586 # miss rate for ReadCleanReq accesses 60311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.294936 # miss rate for ReadSharedReq accesses 60411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.294936 # miss rate for ReadSharedReq accesses 60511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.733532 # miss rate for InvalidateReq accesses 60611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::total 0.733532 # miss rate for InvalidateReq accesses 60711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.037100 # miss rate for demand accesses 60811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052925 # miss rate for demand accesses 60911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.090586 # miss rate for demand accesses 61011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.350922 # miss rate for demand accesses 61111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.213603 # miss rate for demand accesses 61211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.037100 # miss rate for overall accesses 61311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052925 # miss rate for overall accesses 61411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.090586 # miss rate for overall accesses 61511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.350922 # miss rate for overall accesses 61611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.213603 # miss rate for overall accesses 61710585SN/Asystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 61810585SN/Asystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 61910585SN/Asystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 62010585SN/Asystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 62110585SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 62210585SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 62311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.writebacks::writebacks 1554149 # number of writebacks 62411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.writebacks::total 1554149 # number of writebacks 62511502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_requests 24067586 # Total number of requests made to the snoop filter. 62611502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_requests 12257514 # Number of requests hitting in the snoop filter with a single holder of the requested data. 62711502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1374 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 62811502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_snoops 1770017 # Total number of snoops made to the snoop filter. 62911502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1769681 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 63011502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 336 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 63111530Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 63211502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 619965 # Transaction distribution 63311502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 10275461 # Transaction distribution 63411502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 33238 # Transaction distribution 63511502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 33238 # Transaction distribution 63611502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackDirty 4423360 # Transaction distribution 63711502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackClean 7283249 # Transaction distribution 63811502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 137433 # Transaction distribution 63911502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 154684 # Transaction distribution 64011502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 292117 # Transaction distribution 64111502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1335070 # Transaction distribution 64211502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1335070 # Transaction distribution 64311502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 5489019 # Transaction distribution 64411502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 4166477 # Transaction distribution 64511502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateReq 819512 # Transaction distribution 64611502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateResp 819512 # Transaction distribution 64711502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16552790 # Packet count per connected master and slave (bytes) 64811502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19577101 # Packet count per connected master and slave (bytes) 64911502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 363556 # Packet count per connected master and slave (bytes) 65011502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 723958 # Packet count per connected master and slave (bytes) 65111502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count::total 37217405 # Packet count per connected master and slave (bytes) 65211502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 702733844 # Cumulative packet size per connected master and slave (bytes) 65311502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 750256336 # Cumulative packet size per connected master and slave (bytes) 65411502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1454224 # Cumulative packet size per connected master and slave (bytes) 65511502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2895832 # Cumulative packet size per connected master and slave (bytes) 65611502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size::total 1457340236 # Cumulative packet size per connected master and slave (bytes) 65711502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoops 6073545 # Total snoops (count) 65811502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 30354370 # Request fanout histogram 65911502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 0.066939 # Request fanout histogram 66011502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.249960 # Request fanout histogram 66110585SN/Asystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 66211502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 28322817 93.31% 93.31% # Request fanout histogram 66311502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 2031217 6.69% 100.00% # Request fanout histogram 66411502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 336 0.00% 100.00% # Request fanout histogram 66510585SN/Asystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 66611138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 66710827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 66811502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 30354370 # Request fanout histogram 66911530Sandreas.sandberg@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 67010628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 67110628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 67210628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 67310628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 67410628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 67510628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 67610628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 67710628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 67810585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 67910585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 68010585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 68110585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 68210585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 68310585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 68410585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 68510585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 68610585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 68710585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 68810585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 68910585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 69010585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 69110585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 69210585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 69310585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 69410585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 69510585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 69610585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 69710585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 69810585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 69911530Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 70011502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walks 144355 # Table walker walks requested 70111502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksLong 144355 # Table walker walks initiated with long descriptors 70211502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 144355 # Table walker wait (enqueue to first request) latency 70311502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0 144355 100.00% 100.00% # Table walker wait (enqueue to first request) latency 70411502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 144355 # Table walker wait (enqueue to first request) latency 70510628SN/Asystem.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution 70610628SN/Asystem.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution 70710628SN/Asystem.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution 70811502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 111959 88.88% 88.88% # Table walker page sizes translated 70911502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkPageSizes::2M 14012 11.12% 100.00% # Table walker page sizes translated 71011502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 125971 # Table walker page sizes translated 71111502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144355 # Table walker requests started/completed, data/inst 71210628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 71311502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144355 # Table walker requests started/completed, data/inst 71411502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 125971 # Table walker requests started/completed, data/inst 71510628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 71611502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 125971 # Table walker requests started/completed, data/inst 71711502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 270326 # Table walker requests started/completed, data/inst 71810585SN/Asystem.cpu1.dtb.inst_hits 0 # ITB inst hits 71910585SN/Asystem.cpu1.dtb.inst_misses 0 # ITB inst misses 72011502SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_hits 91325952 # DTB read hits 72111502SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_misses 111931 # DTB read misses 72211502SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_hits 82141676 # DTB write hits 72311502SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_misses 32424 # DTB write misses 72410585SN/Asystem.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed 72510585SN/Asystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 72611502SCurtis.Dunham@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID 72710585SN/Asystem.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 72811502SCurtis.Dunham@arm.comsystem.cpu1.dtb.flush_entries 44858 # Number of entries that have been flushed from TLB 72910585SN/Asystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 73011502SCurtis.Dunham@arm.comsystem.cpu1.dtb.prefetch_faults 4450 # Number of TLB faults due to prefetch 73110585SN/Asystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 73211502SCurtis.Dunham@arm.comsystem.cpu1.dtb.perms_faults 11485 # Number of TLB faults due to permissions restrictions 73311502SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_accesses 91437883 # DTB read accesses 73411502SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_accesses 82174100 # DTB write accesses 73510585SN/Asystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 73611502SCurtis.Dunham@arm.comsystem.cpu1.dtb.hits 173467628 # DTB hits 73711502SCurtis.Dunham@arm.comsystem.cpu1.dtb.misses 144355 # DTB misses 73811502SCurtis.Dunham@arm.comsystem.cpu1.dtb.accesses 173611983 # DTB accesses 73911530Sandreas.sandberg@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 74010628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 74110628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 74210628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 74310628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 74410628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 74510628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 74610628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 74710628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 74810585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 74910585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 75010585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 75110585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 75210585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 75310585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 75410585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 75510585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 75610585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 75710585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 75810585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 75910585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 76010585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 76110585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 76210585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 76310585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 76410585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 76510585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 76610585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 76710585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 76810585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 76911530Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 77011502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walks 61638 # Table walker walks requested 77111502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksLong 61638 # Table walker walks initiated with long descriptors 77211502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 61638 # Table walker wait (enqueue to first request) latency 77311502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkWaitTime::0 61638 100.00% 100.00% # Table walker wait (enqueue to first request) latency 77411502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 61638 # Table walker wait (enqueue to first request) latency 77510628SN/Asystem.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution 77610628SN/Asystem.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution 77710628SN/Asystem.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution 77811502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 54650 99.05% 99.05% # Table walker page sizes translated 77911502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkPageSizes::2M 526 0.95% 100.00% # Table walker page sizes translated 78011502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 55176 # Table walker page sizes translated 78110628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 78211502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61638 # Table walker requests started/completed, data/inst 78311502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 61638 # Table walker requests started/completed, data/inst 78410628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 78511502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55176 # Table walker requests started/completed, data/inst 78611502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 55176 # Table walker requests started/completed, data/inst 78711502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 116814 # Table walker requests started/completed, data/inst 78811502SCurtis.Dunham@arm.comsystem.cpu1.itb.inst_hits 483902380 # ITB inst hits 78911502SCurtis.Dunham@arm.comsystem.cpu1.itb.inst_misses 61638 # ITB inst misses 79010585SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 79110585SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 79210585SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 79310585SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 79410585SN/Asystem.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed 79510585SN/Asystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 79611502SCurtis.Dunham@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID 79710585SN/Asystem.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 79811502SCurtis.Dunham@arm.comsystem.cpu1.itb.flush_entries 31512 # Number of entries that have been flushed from TLB 79910585SN/Asystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 80010585SN/Asystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 80110585SN/Asystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 80210585SN/Asystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 80310585SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 80410585SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 80511502SCurtis.Dunham@arm.comsystem.cpu1.itb.inst_accesses 483964018 # ITB inst accesses 80611502SCurtis.Dunham@arm.comsystem.cpu1.itb.hits 483902380 # DTB hits 80711502SCurtis.Dunham@arm.comsystem.cpu1.itb.misses 61638 # DTB misses 80811502SCurtis.Dunham@arm.comsystem.cpu1.itb.accesses 483964018 # DTB accesses 80911530Sandreas.sandberg@arm.comsystem.cpu1.numPwrStateTransitions 12326 # Number of power state transitions 81011530Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::samples 6163 # Distribution of time spent in the clock gated state 81111530Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::mean 7615138435.844394 # Distribution of time spent in the clock gated state 81211530Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::stdev 188025849317.388916 # Distribution of time spent in the clock gated state 81311530Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::underflows 4489 72.84% 72.84% # Distribution of time spent in the clock gated state 81411530Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::1000-5e+10 1652 26.81% 99.64% # Distribution of time spent in the clock gated state 81511530Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::5e+10-1e+11 6 0.10% 99.74% # Distribution of time spent in the clock gated state 81611530Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 2 0.03% 99.77% # Distribution of time spent in the clock gated state 81711530Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.03% 99.81% # Distribution of time spent in the clock gated state 81811530Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.82% # Distribution of time spent in the clock gated state 81911530Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::3.5e+11-4e+11 1 0.02% 99.84% # Distribution of time spent in the clock gated state 82011530Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::overflows 10 0.16% 100.00% # Distribution of time spent in the clock gated state 82111530Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 82211530Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::max_value 11813542449500 # Distribution of time spent in the clock gated state 82311530Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::total 6163 # Distribution of time spent in the clock gated state 82411530Sandreas.sandberg@arm.comsystem.cpu1.pwrStateResidencyTicks::ON 284716621891 # Cumulative time (in ticks) in various power states 82511530Sandreas.sandberg@arm.comsystem.cpu1.pwrStateResidencyTicks::CLK_GATED 46932098180109 # Cumulative time (in ticks) in various power states 82611502SCurtis.Dunham@arm.comsystem.cpu1.numCycles 94433635768 # number of cpu cycles simulated 82710585SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 82810585SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 82911167Sjthestness@gmail.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 83011502SCurtis.Dunham@arm.comsystem.cpu1.kern.inst.quiesce 6163 # number of quiesce instructions executed 83111502SCurtis.Dunham@arm.comsystem.cpu1.committedInsts 483651505 # Number of instructions committed 83211502SCurtis.Dunham@arm.comsystem.cpu1.committedOps 569122264 # Number of ops (including micro ops) committed 83311502SCurtis.Dunham@arm.comsystem.cpu1.num_int_alu_accesses 522328734 # Number of integer alu accesses 83411502SCurtis.Dunham@arm.comsystem.cpu1.num_fp_alu_accesses 379089 # Number of float alu accesses 83511502SCurtis.Dunham@arm.comsystem.cpu1.num_func_calls 28525698 # number of times a function call or return occured 83611502SCurtis.Dunham@arm.comsystem.cpu1.num_conditional_control_insts 74077236 # number of instructions that are conditional controls 83711502SCurtis.Dunham@arm.comsystem.cpu1.num_int_insts 522328734 # number of integer instructions 83811502SCurtis.Dunham@arm.comsystem.cpu1.num_fp_insts 379089 # number of float instructions 83911502SCurtis.Dunham@arm.comsystem.cpu1.num_int_register_reads 771436981 # number of times the integer registers were read 84011502SCurtis.Dunham@arm.comsystem.cpu1.num_int_register_writes 415765246 # number of times the integer registers were written 84111502SCurtis.Dunham@arm.comsystem.cpu1.num_fp_register_reads 615128 # number of times the floating registers were read 84211502SCurtis.Dunham@arm.comsystem.cpu1.num_fp_register_writes 311192 # number of times the floating registers were written 84311502SCurtis.Dunham@arm.comsystem.cpu1.num_cc_register_reads 127876698 # number of times the CC registers were read 84411502SCurtis.Dunham@arm.comsystem.cpu1.num_cc_register_writes 127597836 # number of times the CC registers were written 84511502SCurtis.Dunham@arm.comsystem.cpu1.num_mem_refs 173588529 # number of memory refs 84611502SCurtis.Dunham@arm.comsystem.cpu1.num_load_insts 91424864 # Number of load instructions 84711502SCurtis.Dunham@arm.comsystem.cpu1.num_store_insts 82163665 # Number of store instructions 84811502SCurtis.Dunham@arm.comsystem.cpu1.num_idle_cycles 93864202487.047195 # Number of idle cycles 84911502SCurtis.Dunham@arm.comsystem.cpu1.num_busy_cycles 569433280.952807 # Number of busy cycles 85011502SCurtis.Dunham@arm.comsystem.cpu1.not_idle_fraction 0.006030 # Percentage of non-idle cycles 85111502SCurtis.Dunham@arm.comsystem.cpu1.idle_fraction 0.993970 # Percentage of idle cycles 85211502SCurtis.Dunham@arm.comsystem.cpu1.Branches 107756231 # Number of branches fetched 85310585SN/Asystem.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 85411502SCurtis.Dunham@arm.comsystem.cpu1.op_class::IntAlu 394594292 69.30% 69.30% # Class of executed instruction 85511502SCurtis.Dunham@arm.comsystem.cpu1.op_class::IntMult 1146816 0.20% 69.50% # Class of executed instruction 85611502SCurtis.Dunham@arm.comsystem.cpu1.op_class::IntDiv 61459 0.01% 69.51% # Class of executed instruction 85711502SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction 85811502SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction 85911502SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction 86011502SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction 86111502SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction 86211502SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction 86311502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction 86411502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction 86511502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction 86611502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction 86711502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction 86811502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction 86911502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction 87011502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction 87111502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction 87211502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction 87311502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction 87411502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatAdd 0 0.00% 69.51% # Class of executed instruction 87511502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction 87611502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatCmp 0 0.00% 69.51% # Class of executed instruction 87711502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatCvt 0 0.00% 69.51% # Class of executed instruction 87811502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction 87911502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatMisc 37349 0.01% 69.52% # Class of executed instruction 88011336Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction 88111336Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction 88211336Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction 88311502SCurtis.Dunham@arm.comsystem.cpu1.op_class::MemRead 91424864 16.06% 85.57% # Class of executed instruction 88411502SCurtis.Dunham@arm.comsystem.cpu1.op_class::MemWrite 82163665 14.43% 100.00% # Class of executed instruction 88510585SN/Asystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 88610585SN/Asystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 88711502SCurtis.Dunham@arm.comsystem.cpu1.op_class::total 569428445 # Class of executed instruction 88811530Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 88911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.replacements 6003966 # number of replacements 89011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.tagsinuse 423.687505 # Cycle average of tags in use 89111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.total_refs 167475451 # Total number of references to valid blocks. 89211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.sampled_refs 6004478 # Sample count of references to valid blocks. 89311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.avg_refs 27.891759 # Average number of references to valid blocks. 89410585SN/Asystem.cpu1.dcache.tags.warmup_cycle 8470277778500 # Cycle when the warmup percentage was hit. 89511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 423.687505 # Average occupied blocks per requestor 89611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.827515 # Average percentage of cache occupancy 89711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.827515 # Average percentage of cache occupancy 89810726SN/Asystem.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 89911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 248 # Occupied blocks per task id 90011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 264 # Occupied blocks per task id 90110726SN/Asystem.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 90211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.tag_accesses 353236361 # Number of tag accesses 90311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.data_accesses 353236361 # Number of data accesses 90411530Sandreas.sandberg@arm.comsystem.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 90511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 84832048 # number of ReadReq hits 90611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_hits::total 84832048 # number of ReadReq hits 90711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 77963660 # number of WriteReq hits 90811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_hits::total 77963660 # number of WriteReq hits 90911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 187526 # number of SoftPFReq hits 91011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 187526 # number of SoftPFReq hits 91111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_hits::cpu1.data 65427 # number of WriteLineReq hits 91211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_hits::total 65427 # number of WriteLineReq hits 91311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2067288 # number of LoadLockedReq hits 91411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 2067288 # number of LoadLockedReq hits 91511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 2056969 # number of StoreCondReq hits 91611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 2056969 # number of StoreCondReq hits 91711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 162861135 # number of demand (read+write) hits 91811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_hits::total 162861135 # number of demand (read+write) hits 91911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 163048661 # number of overall hits 92011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_hits::total 163048661 # number of overall hits 92111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 3388721 # number of ReadReq misses 92211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_misses::total 3388721 # number of ReadReq misses 92311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 1469364 # number of WriteReq misses 92411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_misses::total 1469364 # number of WriteReq misses 92511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 795051 # number of SoftPFReq misses 92611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 795051 # number of SoftPFReq misses 92711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_misses::cpu1.data 438458 # number of WriteLineReq misses 92811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_misses::total 438458 # number of WriteLineReq misses 92911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 148516 # number of LoadLockedReq misses 93011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 148516 # number of LoadLockedReq misses 93111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 157576 # number of StoreCondReq misses 93211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 157576 # number of StoreCondReq misses 93311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 5296543 # number of demand (read+write) misses 93411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_misses::total 5296543 # number of demand (read+write) misses 93511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 6091594 # number of overall misses 93611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_misses::total 6091594 # number of overall misses 93711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 88220769 # number of ReadReq accesses(hits+misses) 93811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 88220769 # number of ReadReq accesses(hits+misses) 93911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 79433024 # number of WriteReq accesses(hits+misses) 94011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 79433024 # number of WriteReq accesses(hits+misses) 94111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 982577 # number of SoftPFReq accesses(hits+misses) 94211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 982577 # number of SoftPFReq accesses(hits+misses) 94311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::cpu1.data 503885 # number of WriteLineReq accesses(hits+misses) 94411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::total 503885 # number of WriteLineReq accesses(hits+misses) 94511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2215804 # number of LoadLockedReq accesses(hits+misses) 94611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 2215804 # number of LoadLockedReq accesses(hits+misses) 94711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2214545 # number of StoreCondReq accesses(hits+misses) 94811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 2214545 # number of StoreCondReq accesses(hits+misses) 94911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 168157678 # number of demand (read+write) accesses 95011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_accesses::total 168157678 # number of demand (read+write) accesses 95111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 169140255 # number of overall (read+write) accesses 95211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_accesses::total 169140255 # number of overall (read+write) accesses 95311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038412 # miss rate for ReadReq accesses 95411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.038412 # miss rate for ReadReq accesses 95511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018498 # miss rate for WriteReq accesses 95611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.018498 # miss rate for WriteReq accesses 95711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.809149 # miss rate for SoftPFReq accesses 95811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.809149 # miss rate for SoftPFReq accesses 95911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870155 # miss rate for WriteLineReq accesses 96011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::total 0.870155 # miss rate for WriteLineReq accesses 96111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.067026 # miss rate for LoadLockedReq accesses 96211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.067026 # miss rate for LoadLockedReq accesses 96311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071155 # miss rate for StoreCondReq accesses 96411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.071155 # miss rate for StoreCondReq accesses 96511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.031497 # miss rate for demand accesses 96611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.031497 # miss rate for demand accesses 96711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.036015 # miss rate for overall accesses 96811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.036015 # miss rate for overall accesses 96910585SN/Asystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 97010585SN/Asystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 97110585SN/Asystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 97210585SN/Asystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 97310585SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 97410585SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 97511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.writebacks::writebacks 6003966 # number of writebacks 97611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.writebacks::total 6003966 # number of writebacks 97711530Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 97811502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.replacements 4799154 # number of replacements 97911502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.tagsinuse 496.426080 # Cycle average of tags in use 98011502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.total_refs 479157890 # Total number of references to valid blocks. 98111502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.sampled_refs 4799666 # Sample count of references to valid blocks. 98211502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.avg_refs 99.831507 # Average number of references to valid blocks. 98310585SN/Asystem.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit. 98411502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 496.426080 # Average occupied blocks per requestor 98511502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.969582 # Average percentage of cache occupancy 98611502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.969582 # Average percentage of cache occupancy 98710585SN/Asystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 98811502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 98911502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id 99011502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 147 # Occupied blocks per task id 99110585SN/Asystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 99211502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.tag_accesses 972714778 # Number of tag accesses 99311502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.data_accesses 972714778 # Number of data accesses 99411530Sandreas.sandberg@arm.comsystem.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 99511502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 479157890 # number of ReadReq hits 99611502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_hits::total 479157890 # number of ReadReq hits 99711502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 479157890 # number of demand (read+write) hits 99811502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_hits::total 479157890 # number of demand (read+write) hits 99911502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 479157890 # number of overall hits 100011502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_hits::total 479157890 # number of overall hits 100111502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 4799666 # number of ReadReq misses 100211502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_misses::total 4799666 # number of ReadReq misses 100311502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 4799666 # number of demand (read+write) misses 100411502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_misses::total 4799666 # number of demand (read+write) misses 100511502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 4799666 # number of overall misses 100611502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_misses::total 4799666 # number of overall misses 100711502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 483957556 # number of ReadReq accesses(hits+misses) 100811502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_accesses::total 483957556 # number of ReadReq accesses(hits+misses) 100911502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 483957556 # number of demand (read+write) accesses 101011502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_accesses::total 483957556 # number of demand (read+write) accesses 101111502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 483957556 # number of overall (read+write) accesses 101211502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_accesses::total 483957556 # number of overall (read+write) accesses 101311502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009918 # miss rate for ReadReq accesses 101411502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.009918 # miss rate for ReadReq accesses 101511502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.009918 # miss rate for demand accesses 101611502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.009918 # miss rate for demand accesses 101711502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.009918 # miss rate for overall accesses 101811502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.009918 # miss rate for overall accesses 101910585SN/Asystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 102010585SN/Asystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 102110585SN/Asystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 102210585SN/Asystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 102310585SN/Asystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 102410585SN/Asystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 102511502SCurtis.Dunham@arm.comsystem.cpu1.icache.writebacks::writebacks 4799154 # number of writebacks 102611502SCurtis.Dunham@arm.comsystem.cpu1.icache.writebacks::total 4799154 # number of writebacks 102711530Sandreas.sandberg@arm.comsystem.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 102810628SN/Asystem.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 102910628SN/Asystem.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 103010628SN/Asystem.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 103110628SN/Asystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 103210628SN/Asystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 103310628SN/Asystem.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 103411530Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 103511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.replacements 2283161 # number of replacements 103611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.tagsinuse 13345.955021 # Cycle average of tags in use 103711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.total_refs 14389871 # Total number of references to valid blocks. 103811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.sampled_refs 2299207 # Sample count of references to valid blocks. 103911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.avg_refs 6.258624 # Average number of references to valid blocks. 104011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 10262240501000 # Cycle when the warmup percentage was hit. 104111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 13228.741418 # Average occupied blocks per requestor 104211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 51.265537 # Average occupied blocks per requestor 104311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 65.948066 # Average occupied blocks per requestor 104411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.807418 # Average percentage of cache occupancy 104511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003129 # Average percentage of cache occupancy 104611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004025 # Average percentage of cache occupancy 104711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.814572 # Average percentage of cache occupancy 104811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 89 # Occupied blocks per task id 104911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 15957 # Occupied blocks per task id 105011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 105111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 53 # Occupied blocks per task id 105211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 15 # Occupied blocks per task id 105311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id 105411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 211 # Occupied blocks per task id 105511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1511 # Occupied blocks per task id 105611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6067 # Occupied blocks per task id 105711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4384 # Occupied blocks per task id 105811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3784 # Occupied blocks per task id 105911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005432 # Percentage of cache occupancy per task id 106011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.973938 # Percentage of cache occupancy per task id 106111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.tag_accesses 365657601 # Number of tag accesses 106211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.data_accesses 365657601 # Number of data accesses 106311530Sandreas.sandberg@arm.comsystem.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 106411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 347777 # number of ReadReq hits 106511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155733 # number of ReadReq hits 106611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 503510 # number of ReadReq hits 106711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::writebacks 4070389 # number of WritebackDirty hits 106811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::total 4070389 # number of WritebackDirty hits 106911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_hits::writebacks 6732353 # number of WritebackClean hits 107011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_hits::total 6732353 # number of WritebackClean hits 107111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1054 # number of UpgradeReq hits 107211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::total 1054 # number of UpgradeReq hits 107311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 615614 # number of ReadExReq hits 107411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 615614 # number of ReadExReq hits 107511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4333068 # number of ReadCleanReq hits 107611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 4333068 # number of ReadCleanReq hits 107711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3106952 # number of ReadSharedReq hits 107811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 3106952 # number of ReadSharedReq hits 107911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::cpu1.data 166128 # number of InvalidateReq hits 108011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::total 166128 # number of InvalidateReq hits 108111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 347777 # number of demand (read+write) hits 108211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 155733 # number of demand (read+write) hits 108311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 4333068 # number of demand (read+write) hits 108411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 3722566 # number of demand (read+write) hits 108511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::total 8559144 # number of demand (read+write) hits 108611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 347777 # number of overall hits 108711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 155733 # number of overall hits 108811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 4333068 # number of overall hits 108911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 3722566 # number of overall hits 109011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::total 8559144 # number of overall hits 109111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12333 # number of ReadReq misses 109211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9620 # number of ReadReq misses 109311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 21953 # number of ReadReq misses 109411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 143903 # number of UpgradeReq misses 109511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 143903 # number of UpgradeReq misses 109611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 157576 # number of SCUpgradeReq misses 109711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 157576 # number of SCUpgradeReq misses 109811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 709038 # number of ReadExReq misses 109911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 709038 # number of ReadExReq misses 110011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 466598 # number of ReadCleanReq misses 110111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 466598 # number of ReadCleanReq misses 110211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1225336 # number of ReadSharedReq misses 110311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 1225336 # number of ReadSharedReq misses 110411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::cpu1.data 272085 # number of InvalidateReq misses 110511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::total 272085 # number of InvalidateReq misses 110611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12333 # number of demand (read+write) misses 110711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 9620 # number of demand (read+write) misses 110811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 466598 # number of demand (read+write) misses 110911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 1934374 # number of demand (read+write) misses 111011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::total 2422925 # number of demand (read+write) misses 111111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12333 # number of overall misses 111211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 9620 # number of overall misses 111311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 466598 # number of overall misses 111411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 1934374 # number of overall misses 111511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::total 2422925 # number of overall misses 111611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 360110 # number of ReadReq accesses(hits+misses) 111711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 165353 # number of ReadReq accesses(hits+misses) 111811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 525463 # number of ReadReq accesses(hits+misses) 111911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::writebacks 4070389 # number of WritebackDirty accesses(hits+misses) 112011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::total 4070389 # number of WritebackDirty accesses(hits+misses) 112111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::writebacks 6732353 # number of WritebackClean accesses(hits+misses) 112211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::total 6732353 # number of WritebackClean accesses(hits+misses) 112311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 144957 # number of UpgradeReq accesses(hits+misses) 112411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 144957 # number of UpgradeReq accesses(hits+misses) 112511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 157576 # number of SCUpgradeReq accesses(hits+misses) 112611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 157576 # number of SCUpgradeReq accesses(hits+misses) 112711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1324652 # number of ReadExReq accesses(hits+misses) 112811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 1324652 # number of ReadExReq accesses(hits+misses) 112911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4799666 # number of ReadCleanReq accesses(hits+misses) 113011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 4799666 # number of ReadCleanReq accesses(hits+misses) 113111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4332288 # number of ReadSharedReq accesses(hits+misses) 113211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 4332288 # number of ReadSharedReq accesses(hits+misses) 113311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 438213 # number of InvalidateReq accesses(hits+misses) 113411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::total 438213 # number of InvalidateReq accesses(hits+misses) 113511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 360110 # number of demand (read+write) accesses 113611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 165353 # number of demand (read+write) accesses 113711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 4799666 # number of demand (read+write) accesses 113811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 5656940 # number of demand (read+write) accesses 113911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::total 10982069 # number of demand (read+write) accesses 114011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 360110 # number of overall (read+write) accesses 114111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 165353 # number of overall (read+write) accesses 114211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 4799666 # number of overall (read+write) accesses 114311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 5656940 # number of overall (read+write) accesses 114411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::total 10982069 # number of overall (read+write) accesses 114511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.034248 # miss rate for ReadReq accesses 114611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.058179 # miss rate for ReadReq accesses 114711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.041778 # miss rate for ReadReq accesses 114811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.992729 # miss rate for UpgradeReq accesses 114911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 0.992729 # miss rate for UpgradeReq accesses 115010585SN/Asystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 115110585SN/Asystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 115211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.535264 # miss rate for ReadExReq accesses 115311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.535264 # miss rate for ReadExReq accesses 115411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.097215 # miss rate for ReadCleanReq accesses 115511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.097215 # miss rate for ReadCleanReq accesses 115611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.282838 # miss rate for ReadSharedReq accesses 115711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.282838 # miss rate for ReadSharedReq accesses 115811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.620897 # miss rate for InvalidateReq accesses 115911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::total 0.620897 # miss rate for InvalidateReq accesses 116011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.034248 # miss rate for demand accesses 116111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.058179 # miss rate for demand accesses 116211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.097215 # miss rate for demand accesses 116311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.341947 # miss rate for demand accesses 116411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.220626 # miss rate for demand accesses 116511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.034248 # miss rate for overall accesses 116611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.058179 # miss rate for overall accesses 116711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.097215 # miss rate for overall accesses 116811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.341947 # miss rate for overall accesses 116911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.220626 # miss rate for overall accesses 117010585SN/Asystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 117110585SN/Asystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 117210585SN/Asystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 117310585SN/Asystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 117410585SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 117510585SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 117611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.writebacks::writebacks 1211269 # number of writebacks 117711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.writebacks::total 1211269 # number of writebacks 117811502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_requests 22276444 # Total number of requests made to the snoop filter. 117911502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_requests 11381625 # Number of requests hitting in the snoop filter with a single holder of the requested data. 118011502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_requests 378 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 118111502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_snoops 1756231 # Total number of snoops made to the snoop filter. 118211502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1756065 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 118311502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 166 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 118411530Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 118511502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 608590 # Transaction distribution 118611502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 9740544 # Transaction distribution 118711502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 5562 # Transaction distribution 118811502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 5562 # Transaction distribution 118911502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackDirty 4070389 # Transaction distribution 119011502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackClean 6732731 # Transaction distribution 119111502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 144957 # Transaction distribution 119211502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 157576 # Transaction distribution 119311502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 302533 # Transaction distribution 119411502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 1324652 # Transaction distribution 119511502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 1324652 # Transaction distribution 119611502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 4799666 # Transaction distribution 119711502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 4332288 # Transaction distribution 119811502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateReq 438213 # Transaction distribution 119911502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateResp 438213 # Transaction distribution 120011502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14398746 # Packet count per connected master and slave (bytes) 120111502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18822028 # Packet count per connected master and slave (bytes) 120211502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 368476 # Packet count per connected master and slave (bytes) 120311502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 836878 # Packet count per connected master and slave (bytes) 120411502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count::total 34426128 # Packet count per connected master and slave (bytes) 120511502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 614325000 # Cumulative packet size per connected master and slave (bytes) 120611502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 746331191 # Cumulative packet size per connected master and slave (bytes) 120711502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1473904 # Cumulative packet size per connected master and slave (bytes) 120811502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3347512 # Cumulative packet size per connected master and slave (bytes) 120911502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size::total 1365477607 # Cumulative packet size per connected master and slave (bytes) 121011502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoops 5687998 # Total snoops (count) 121111502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 28144557 # Request fanout histogram 121211502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 0.072239 # Request fanout histogram 121311502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.258905 # Request fanout histogram 121410585SN/Asystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 121511502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 26111598 92.78% 92.78% # Request fanout histogram 121611502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 2032793 7.22% 100.00% # Request fanout histogram 121711502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 166 0.00% 100.00% # Request fanout histogram 121810585SN/Asystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 121911138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 122010827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 122111502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 28144557 # Request fanout histogram 122211530Sandreas.sandberg@arm.comsystem.iobus.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 122311502SCurtis.Dunham@arm.comsystem.iobus.trans_dist::ReadReq 40301 # Transaction distribution 122411502SCurtis.Dunham@arm.comsystem.iobus.trans_dist::ReadResp 40301 # Transaction distribution 122511336Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 136636 # Transaction distribution 122611336Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 136636 # Transaction distribution 122711502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47642 # Packet count per connected master and slave (bytes) 122810585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 122911245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 123010585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 123110585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 123210585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 123310585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 123410585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 123510585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 123610585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 123710585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 123810585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 123910585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 124011502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122576 # Packet count per connected master and slave (bytes) 124111502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231218 # Packet count per connected master and slave (bytes) 124211502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231218 # Packet count per connected master and slave (bytes) 124310585SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 124410585SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 124511502SCurtis.Dunham@arm.comsystem.iobus.pkt_count::total 353874 # Packet count per connected master and slave (bytes) 124611502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47662 # Cumulative packet size per connected master and slave (bytes) 124710585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 124811245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 124910585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 125010585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 125110585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 125210585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 125310585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 125410585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 125510585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 125610585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 125710585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 125810585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 125911502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::total 155683 # Cumulative packet size per connected master and slave (bytes) 126011502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338888 # Cumulative packet size per connected master and slave (bytes) 126111502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7338888 # Cumulative packet size per connected master and slave (bytes) 126210585SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 126310585SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 126411502SCurtis.Dunham@arm.comsystem.iobus.pkt_size::total 7496657 # Cumulative packet size per connected master and slave (bytes) 126511530Sandreas.sandberg@arm.comsystem.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 126611502SCurtis.Dunham@arm.comsystem.iocache.tags.replacements 115590 # number of replacements 126711502SCurtis.Dunham@arm.comsystem.iocache.tags.tagsinuse 11.289214 # Cycle average of tags in use 126810585SN/Asystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 126911502SCurtis.Dunham@arm.comsystem.iocache.tags.sampled_refs 115606 # Sample count of references to valid blocks. 127010585SN/Asystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 127111502SCurtis.Dunham@arm.comsystem.iocache.tags.warmup_cycle 9107775784009 # Cycle when the warmup percentage was hit. 127211502SCurtis.Dunham@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 3.856196 # Average occupied blocks per requestor 127311502SCurtis.Dunham@arm.comsystem.iocache.tags.occ_blocks::realview.ide 7.433018 # Average occupied blocks per requestor 127411502SCurtis.Dunham@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.241012 # Average percentage of cache occupancy 127511502SCurtis.Dunham@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.464564 # Average percentage of cache occupancy 127611502SCurtis.Dunham@arm.comsystem.iocache.tags.occ_percent::total 0.705576 # Average percentage of cache occupancy 127710585SN/Asystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 127810585SN/Asystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 127910585SN/Asystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 128011502SCurtis.Dunham@arm.comsystem.iocache.tags.tag_accesses 1040838 # Number of tag accesses 128111502SCurtis.Dunham@arm.comsystem.iocache.tags.data_accesses 1040838 # Number of data accesses 128211530Sandreas.sandberg@arm.comsystem.iocache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 128310585SN/Asystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 128411502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_misses::realview.ide 8881 # number of ReadReq misses 128511502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_misses::total 8918 # number of ReadReq misses 128610585SN/Asystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 128710585SN/Asystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 128810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 128910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 129010585SN/Asystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 129111502SCurtis.Dunham@arm.comsystem.iocache.demand_misses::realview.ide 115609 # number of demand (read+write) misses 129211502SCurtis.Dunham@arm.comsystem.iocache.demand_misses::total 115649 # number of demand (read+write) misses 129310585SN/Asystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 129411502SCurtis.Dunham@arm.comsystem.iocache.overall_misses::realview.ide 115609 # number of overall misses 129511502SCurtis.Dunham@arm.comsystem.iocache.overall_misses::total 115649 # number of overall misses 129610585SN/Asystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 129711502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8881 # number of ReadReq accesses(hits+misses) 129811502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_accesses::total 8918 # number of ReadReq accesses(hits+misses) 129910585SN/Asystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 130010585SN/Asystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 130110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 130210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 130310585SN/Asystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 130411502SCurtis.Dunham@arm.comsystem.iocache.demand_accesses::realview.ide 115609 # number of demand (read+write) accesses 130511502SCurtis.Dunham@arm.comsystem.iocache.demand_accesses::total 115649 # number of demand (read+write) accesses 130610585SN/Asystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 130711502SCurtis.Dunham@arm.comsystem.iocache.overall_accesses::realview.ide 115609 # number of overall (read+write) accesses 130811502SCurtis.Dunham@arm.comsystem.iocache.overall_accesses::total 115649 # number of overall (read+write) accesses 130910585SN/Asystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 131010585SN/Asystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 131110585SN/Asystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 131210585SN/Asystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 131310585SN/Asystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 131410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 131510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 131610585SN/Asystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 131710585SN/Asystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 131810585SN/Asystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 131910585SN/Asystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 132010585SN/Asystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 132110585SN/Asystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 132210585SN/Asystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 132310585SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 132410585SN/Asystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 132510585SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 132610585SN/Asystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 132710585SN/Asystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 132810585SN/Asystem.iocache.writebacks::writebacks 106694 # number of writebacks 132910585SN/Asystem.iocache.writebacks::total 106694 # number of writebacks 133011530Sandreas.sandberg@arm.comsystem.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 133111502SCurtis.Dunham@arm.comsystem.l2c.tags.replacements 1772279 # number of replacements 133211502SCurtis.Dunham@arm.comsystem.l2c.tags.tagsinuse 63191.056766 # Cycle average of tags in use 133311502SCurtis.Dunham@arm.comsystem.l2c.tags.total_refs 4630026 # Total number of references to valid blocks. 133411502SCurtis.Dunham@arm.comsystem.l2c.tags.sampled_refs 1831889 # Sample count of references to valid blocks. 133511502SCurtis.Dunham@arm.comsystem.l2c.tags.avg_refs 2.527460 # Average number of references to valid blocks. 133611353Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 514828500 # Cycle when the warmup percentage was hit. 133711502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::writebacks 34852.259954 # Average occupied blocks per requestor 133811502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 35.728290 # Average occupied blocks per requestor 133911502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 43.277467 # Average occupied blocks per requestor 134011502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 3264.617227 # Average occupied blocks per requestor 134111502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 6940.607740 # Average occupied blocks per requestor 134211502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 274.307726 # Average occupied blocks per requestor 134311502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 426.439632 # Average occupied blocks per requestor 134411502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 2871.138387 # Average occupied blocks per requestor 134511502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 14482.680343 # Average occupied blocks per requestor 134611502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::writebacks 0.531803 # Average percentage of cache occupancy 134711502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.000545 # Average percentage of cache occupancy 134811502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.000660 # Average percentage of cache occupancy 134911502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.049814 # Average percentage of cache occupancy 135011502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.105905 # Average percentage of cache occupancy 135111502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.004186 # Average percentage of cache occupancy 135211502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.006507 # Average percentage of cache occupancy 135311502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.043810 # Average percentage of cache occupancy 135411502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.220988 # Average percentage of cache occupancy 135511502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::total 0.964219 # Average percentage of cache occupancy 135611502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 206 # Occupied blocks per task id 135711502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 59404 # Occupied blocks per task id 135811502SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id 135911502SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 204 # Occupied blocks per task id 136011502SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id 136111502SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 483 # Occupied blocks per task id 136211502SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 3390 # Occupied blocks per task id 136311502SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 5782 # Occupied blocks per task id 136411502SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 49679 # Occupied blocks per task id 136511502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.003143 # Percentage of cache occupancy per task id 136611502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.906433 # Percentage of cache occupancy per task id 136711502SCurtis.Dunham@arm.comsystem.l2c.tags.tag_accesses 73419992 # Number of tag accesses 136811502SCurtis.Dunham@arm.comsystem.l2c.tags.data_accesses 73419992 # Number of data accesses 136911530Sandreas.sandberg@arm.comsystem.l2c.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 137011502SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_hits::writebacks 2765418 # number of WritebackDirty hits 137111502SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_hits::total 2765418 # number of WritebackDirty hits 137211502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 17779 # number of UpgradeReq hits 137311502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 15575 # number of UpgradeReq hits 137411502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::total 33354 # number of UpgradeReq hits 137511502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 2588 # number of SCUpgradeReq hits 137611502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 2404 # number of SCUpgradeReq hits 137711502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_hits::total 4992 # number of SCUpgradeReq hits 137811502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 200286 # number of ReadExReq hits 137911502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 176214 # number of ReadExReq hits 138011502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_hits::total 376500 # number of ReadExReq hits 138111502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6410 # number of ReadSharedReq hits 138211502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 4846 # number of ReadSharedReq hits 138311502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 439050 # number of ReadSharedReq hits 138411502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 727042 # number of ReadSharedReq hits 138511502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5703 # number of ReadSharedReq hits 138611502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 3689 # number of ReadSharedReq hits 138711502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 424901 # number of ReadSharedReq hits 138811502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 685160 # number of ReadSharedReq hits 138911502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::total 2296801 # number of ReadSharedReq hits 139011502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_hits::cpu0.data 115689 # number of InvalidateReq hits 139111502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_hits::cpu1.data 102800 # number of InvalidateReq hits 139211502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_hits::total 218489 # number of InvalidateReq hits 139311502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 6410 # number of demand (read+write) hits 139411502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 4846 # number of demand (read+write) hits 139511502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.inst 439050 # number of demand (read+write) hits 139611502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.data 927328 # number of demand (read+write) hits 139711502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 5703 # number of demand (read+write) hits 139811502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 3689 # number of demand (read+write) hits 139911502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.inst 424901 # number of demand (read+write) hits 140011502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.data 861374 # number of demand (read+write) hits 140111502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::total 2673301 # number of demand (read+write) hits 140211502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 6410 # number of overall hits 140311502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 4846 # number of overall hits 140411502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.inst 439050 # number of overall hits 140511502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.data 927328 # number of overall hits 140611502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 5703 # number of overall hits 140711502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 3689 # number of overall hits 140811502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.inst 424901 # number of overall hits 140911502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.data 861374 # number of overall hits 141011502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::total 2673301 # number of overall hits 141111502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 64906 # number of UpgradeReq misses 141211502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 60031 # number of UpgradeReq misses 141311502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::total 124937 # number of UpgradeReq misses 141411502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 6479 # number of SCUpgradeReq misses 141511502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 6386 # number of SCUpgradeReq misses 141611502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_misses::total 12865 # number of SCUpgradeReq misses 141711502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 376689 # number of ReadExReq misses 141811502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 423433 # number of ReadExReq misses 141911502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::total 800122 # number of ReadExReq misses 142011502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2349 # number of ReadSharedReq misses 142111502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 1944 # number of ReadSharedReq misses 142211502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 58179 # number of ReadSharedReq misses 142311502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 178934 # number of ReadSharedReq misses 142411502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3469 # number of ReadSharedReq misses 142511502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.itb.walker 3479 # number of ReadSharedReq misses 142611502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 41697 # number of ReadSharedReq misses 142711502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 188396 # number of ReadSharedReq misses 142811502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::total 478447 # number of ReadSharedReq misses 142911502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_misses::cpu0.data 477304 # number of InvalidateReq misses 143011502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_misses::cpu1.data 163191 # number of InvalidateReq misses 143111502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_misses::total 640495 # number of InvalidateReq misses 143211502SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 2349 # number of demand (read+write) misses 143311502SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 1944 # number of demand (read+write) misses 143411502SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.inst 58179 # number of demand (read+write) misses 143511502SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.data 555623 # number of demand (read+write) misses 143611502SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 3469 # number of demand (read+write) misses 143711502SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.itb.walker 3479 # number of demand (read+write) misses 143811502SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.inst 41697 # number of demand (read+write) misses 143911502SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.data 611829 # number of demand (read+write) misses 144011502SCurtis.Dunham@arm.comsystem.l2c.demand_misses::total 1278569 # number of demand (read+write) misses 144111502SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 2349 # number of overall misses 144211502SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 1944 # number of overall misses 144311502SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.inst 58179 # number of overall misses 144411502SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.data 555623 # number of overall misses 144511502SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 3469 # number of overall misses 144611502SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.itb.walker 3479 # number of overall misses 144711502SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.inst 41697 # number of overall misses 144811502SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.data 611829 # number of overall misses 144911502SCurtis.Dunham@arm.comsystem.l2c.overall_misses::total 1278569 # number of overall misses 145011502SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 2765418 # number of WritebackDirty accesses(hits+misses) 145111502SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_accesses::total 2765418 # number of WritebackDirty accesses(hits+misses) 145211502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 82685 # number of UpgradeReq accesses(hits+misses) 145311502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 75606 # number of UpgradeReq accesses(hits+misses) 145411502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::total 158291 # number of UpgradeReq accesses(hits+misses) 145511502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 9067 # number of SCUpgradeReq accesses(hits+misses) 145611502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 8790 # number of SCUpgradeReq accesses(hits+misses) 145711502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_accesses::total 17857 # number of SCUpgradeReq accesses(hits+misses) 145811502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 576975 # number of ReadExReq accesses(hits+misses) 145911502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 599647 # number of ReadExReq accesses(hits+misses) 146011502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::total 1176622 # number of ReadExReq accesses(hits+misses) 146111502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8759 # number of ReadSharedReq accesses(hits+misses) 146211502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6790 # number of ReadSharedReq accesses(hits+misses) 146311502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 497229 # number of ReadSharedReq accesses(hits+misses) 146411502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 905976 # number of ReadSharedReq accesses(hits+misses) 146511502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 9172 # number of ReadSharedReq accesses(hits+misses) 146611502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7168 # number of ReadSharedReq accesses(hits+misses) 146711502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 466598 # number of ReadSharedReq accesses(hits+misses) 146811502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 873556 # number of ReadSharedReq accesses(hits+misses) 146911502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::total 2775248 # number of ReadSharedReq accesses(hits+misses) 147011502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_accesses::cpu0.data 592993 # number of InvalidateReq accesses(hits+misses) 147111502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_accesses::cpu1.data 265991 # number of InvalidateReq accesses(hits+misses) 147211502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_accesses::total 858984 # number of InvalidateReq accesses(hits+misses) 147311502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 8759 # number of demand (read+write) accesses 147411502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 6790 # number of demand (read+write) accesses 147511502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.inst 497229 # number of demand (read+write) accesses 147611502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.data 1482951 # number of demand (read+write) accesses 147711502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 9172 # number of demand (read+write) accesses 147811502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 7168 # number of demand (read+write) accesses 147911502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.inst 466598 # number of demand (read+write) accesses 148011502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.data 1473203 # number of demand (read+write) accesses 148111502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::total 3951870 # number of demand (read+write) accesses 148211502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 8759 # number of overall (read+write) accesses 148311502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 6790 # number of overall (read+write) accesses 148411502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.inst 497229 # number of overall (read+write) accesses 148511502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.data 1482951 # number of overall (read+write) accesses 148611502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 9172 # number of overall (read+write) accesses 148711502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 7168 # number of overall (read+write) accesses 148811502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.inst 466598 # number of overall (read+write) accesses 148911502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.data 1473203 # number of overall (read+write) accesses 149011502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::total 3951870 # number of overall (read+write) accesses 149111502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.784979 # miss rate for UpgradeReq accesses 149211502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.793998 # miss rate for UpgradeReq accesses 149311502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.789287 # miss rate for UpgradeReq accesses 149411502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.714569 # miss rate for SCUpgradeReq accesses 149511502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.726507 # miss rate for SCUpgradeReq accesses 149611502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.720446 # miss rate for SCUpgradeReq accesses 149711502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.652869 # miss rate for ReadExReq accesses 149811502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.706137 # miss rate for ReadExReq accesses 149911502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.680016 # miss rate for ReadExReq accesses 150011502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.268181 # miss rate for ReadSharedReq accesses 150111502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.286303 # miss rate for ReadSharedReq accesses 150211502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.117006 # miss rate for ReadSharedReq accesses 150311502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.197504 # miss rate for ReadSharedReq accesses 150411502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.378216 # miss rate for ReadSharedReq accesses 150511502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.485352 # miss rate for ReadSharedReq accesses 150611502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.089364 # miss rate for ReadSharedReq accesses 150711502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.215666 # miss rate for ReadSharedReq accesses 150811502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.172398 # miss rate for ReadSharedReq accesses 150911502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu0.data 0.804907 # miss rate for InvalidateReq accesses 151011502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu1.data 0.613521 # miss rate for InvalidateReq accesses 151111502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_rate::total 0.745643 # miss rate for InvalidateReq accesses 151211502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.268181 # miss rate for demand accesses 151311502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.286303 # miss rate for demand accesses 151411502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.117006 # miss rate for demand accesses 151511502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.374674 # miss rate for demand accesses 151611502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.378216 # miss rate for demand accesses 151711502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.485352 # miss rate for demand accesses 151811502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.089364 # miss rate for demand accesses 151911502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.415305 # miss rate for demand accesses 152011502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::total 0.323535 # miss rate for demand accesses 152111502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.268181 # miss rate for overall accesses 152211502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.286303 # miss rate for overall accesses 152311502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.117006 # miss rate for overall accesses 152411502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.374674 # miss rate for overall accesses 152511502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.378216 # miss rate for overall accesses 152611502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.485352 # miss rate for overall accesses 152711502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.089364 # miss rate for overall accesses 152811502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.415305 # miss rate for overall accesses 152911502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::total 0.323535 # miss rate for overall accesses 153010515SN/Asystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 153110515SN/Asystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 153210515SN/Asystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 153310515SN/Asystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 153410515SN/Asystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 153510515SN/Asystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 153611502SCurtis.Dunham@arm.comsystem.l2c.writebacks::writebacks 1477304 # number of writebacks 153711502SCurtis.Dunham@arm.comsystem.l2c.writebacks::total 1477304 # number of writebacks 153811502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_requests 4491425 # Total number of requests made to the snoop filter. 153911502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_requests 2595543 # Number of requests hitting in the snoop filter with a single holder of the requested data. 154011502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_requests 3224 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 154111502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 154211502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 154311502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 154411530Sandreas.sandberg@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 154511502SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadReq 82119 # Transaction distribution 154611502SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 569484 # Transaction distribution 154711502SCurtis.Dunham@arm.comsystem.membus.trans_dist::WriteReq 38800 # Transaction distribution 154811502SCurtis.Dunham@arm.comsystem.membus.trans_dist::WriteResp 38800 # Transaction distribution 154911502SCurtis.Dunham@arm.comsystem.membus.trans_dist::WritebackDirty 1583998 # Transaction distribution 155011502SCurtis.Dunham@arm.comsystem.membus.trans_dist::CleanEvict 246737 # Transaction distribution 155111502SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeReq 335468 # Transaction distribution 155211502SCurtis.Dunham@arm.comsystem.membus.trans_dist::SCUpgradeReq 307268 # Transaction distribution 155311502SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeResp 157952 # Transaction distribution 155411502SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExReq 787861 # Transaction distribution 155511502SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExResp 784470 # Transaction distribution 155611502SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 487365 # Transaction distribution 155711502SCurtis.Dunham@arm.comsystem.membus.trans_dist::InvalidateReq 742728 # Transaction distribution 155811502SCurtis.Dunham@arm.comsystem.membus.trans_dist::InvalidateResp 742728 # Transaction distribution 155911502SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122576 # Packet count per connected master and slave (bytes) 156010585SN/Asystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 156111502SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27524 # Packet count per connected master and slave (bytes) 156211502SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6408698 # Packet count per connected master and slave (bytes) 156311502SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 6558890 # Packet count per connected master and slave (bytes) 156411502SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346888 # Packet count per connected master and slave (bytes) 156511502SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 346888 # Packet count per connected master and slave (bytes) 156611502SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 6905778 # Packet count per connected master and slave (bytes) 156711502SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155683 # Cumulative packet size per connected master and slave (bytes) 156810585SN/Asystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 156911502SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55048 # Cumulative packet size per connected master and slave (bytes) 157011502SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 175567900 # Cumulative packet size per connected master and slave (bytes) 157111502SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 175778835 # Cumulative packet size per connected master and slave (bytes) 157211502SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7399168 # Cumulative packet size per connected master and slave (bytes) 157311502SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7399168 # Cumulative packet size per connected master and slave (bytes) 157411502SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 183178003 # Cumulative packet size per connected master and slave (bytes) 157510585SN/Asystem.membus.snoops 0 # Total snoops (count) 157611502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 4612344 # Request fanout histogram 157711502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0.007156 # Request fanout histogram 157811502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0.084293 # Request fanout histogram 157910585SN/Asystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 158011502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 4579336 99.28% 99.28% # Request fanout histogram 158111502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 33008 0.72% 100.00% # Request fanout histogram 158210585SN/Asystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 158310585SN/Asystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 158411502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 158510585SN/Asystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 158611502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 4612344 # Request fanout histogram 158711530Sandreas.sandberg@arm.comsystem.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 158811530Sandreas.sandberg@arm.comsystem.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 158911530Sandreas.sandberg@arm.comsystem.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 159011530Sandreas.sandberg@arm.comsystem.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 159111530Sandreas.sandberg@arm.comsystem.realview.gic.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 159211530Sandreas.sandberg@arm.comsystem.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 159311530Sandreas.sandberg@arm.comsystem.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 159411239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 159511239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 159611239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 159711239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 159811239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 159911239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 160011530Sandreas.sandberg@arm.comsystem.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 160111530Sandreas.sandberg@arm.comsystem.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 160210515SN/Asystem.realview.ethernet.txBytes 966 # Bytes Transmitted 160310515SN/Asystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 160410515SN/Asystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 160510515SN/Asystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 160610515SN/Asystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 160710515SN/Asystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 160810515SN/Asystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 160910515SN/Asystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 161010515SN/Asystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 161110515SN/Asystem.realview.ethernet.totBandwidth 164 # Total Bandwidth (bits/s) 161210515SN/Asystem.realview.ethernet.totPackets 3 # Total Packets 161310515SN/Asystem.realview.ethernet.totBytes 966 # Total Bytes 161410515SN/Asystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 161510515SN/Asystem.realview.ethernet.txBandwidth 164 # Transmit Bandwidth (bits/s) 161610515SN/Asystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 161710515SN/Asystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 161810515SN/Asystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 161910515SN/Asystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 162010515SN/Asystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 162110515SN/Asystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 162210515SN/Asystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 162310515SN/Asystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 162410515SN/Asystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 162510515SN/Asystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 162610515SN/Asystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 162710515SN/Asystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 162810515SN/Asystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 162910515SN/Asystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 163010515SN/Asystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 163110515SN/Asystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 163210515SN/Asystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 163310515SN/Asystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 163410515SN/Asystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 163510515SN/Asystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 163610515SN/Asystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 163710515SN/Asystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 163810515SN/Asystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 163910515SN/Asystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 164010515SN/Asystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 164110515SN/Asystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 164210515SN/Asystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 164310515SN/Asystem.realview.ethernet.droppedPackets 0 # number of packets dropped 164411530Sandreas.sandberg@arm.comsystem.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 164511530Sandreas.sandberg@arm.comsystem.realview.ide.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 164611530Sandreas.sandberg@arm.comsystem.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 164711530Sandreas.sandberg@arm.comsystem.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 164811530Sandreas.sandberg@arm.comsystem.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 164911530Sandreas.sandberg@arm.comsystem.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 165011530Sandreas.sandberg@arm.comsystem.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 165111239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 165211239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 165311239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 165411239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 165511530Sandreas.sandberg@arm.comsystem.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 165611530Sandreas.sandberg@arm.comsystem.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 165711530Sandreas.sandberg@arm.comsystem.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 165811530Sandreas.sandberg@arm.comsystem.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 165911530Sandreas.sandberg@arm.comsystem.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 166011530Sandreas.sandberg@arm.comsystem.realview.uart.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 166111530Sandreas.sandberg@arm.comsystem.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 166211530Sandreas.sandberg@arm.comsystem.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 166311530Sandreas.sandberg@arm.comsystem.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 166411530Sandreas.sandberg@arm.comsystem.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 166511530Sandreas.sandberg@arm.comsystem.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 166611530Sandreas.sandberg@arm.comsystem.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 166711502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.tot_requests 11113814 # Total number of requests made to the snoop filter. 166811502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 5721773 # Number of requests hitting in the snoop filter with a single holder of the requested data. 166911502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 1636305 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 167011502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 133991 # Total number of snoops made to the snoop filter. 167111502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 120343 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 167211502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 13648 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 167311530Sandreas.sandberg@arm.comsystem.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 167411502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadReq 82121 # Transaction distribution 167511502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadResp 3542094 # Transaction distribution 167611502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WriteReq 38800 # Transaction distribution 167711502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WriteResp 38800 # Transaction distribution 167811502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 2765418 # Transaction distribution 167911502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::CleanEvict 2011530 # Transaction distribution 168011502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 348672 # Transaction distribution 168111502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 312260 # Transaction distribution 168211502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 660932 # Transaction distribution 168311502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadExReq 1356975 # Transaction distribution 168411502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadExResp 1356975 # Transaction distribution 168511502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 3459973 # Transaction distribution 168611502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::InvalidateReq 858984 # Transaction distribution 168711502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::InvalidateResp 858984 # Transaction distribution 168811502SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9470177 # Packet count per connected master and slave (bytes) 168911502SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8222341 # Packet count per connected master and slave (bytes) 169011502SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count::total 17692518 # Packet count per connected master and slave (bytes) 169111502SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 254644772 # Cumulative packet size per connected master and slave (bytes) 169211502SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 231031359 # Cumulative packet size per connected master and slave (bytes) 169311502SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size::total 485676131 # Cumulative packet size per connected master and slave (bytes) 169411502SCurtis.Dunham@arm.comsystem.toL2Bus.snoops 1806287 # Total snoops (count) 169511502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::samples 13039342 # Request fanout histogram 169611502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::mean 0.283997 # Request fanout histogram 169711502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.453251 # Request fanout histogram 169810515SN/Asystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 169911502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::0 9349855 71.70% 71.70% # Request fanout histogram 170011502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::1 3675839 28.19% 99.90% # Request fanout histogram 170111502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::2 13648 0.10% 100.00% # Request fanout histogram 170210515SN/Asystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 170311138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 170410515SN/Asystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 170511502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::total 13039342 # Request fanout histogram 170610515SN/A 170710515SN/A---------- End Simulation Statistics ---------- 1708