stats.txt revision 11502
110515SN/A 210515SN/A---------- Begin Simulation Statistics ---------- 311502SCurtis.Dunham@arm.comsim_seconds 47.216815 # Number of seconds simulated 411502SCurtis.Dunham@arm.comsim_ticks 47216814802000 # Number of ticks simulated 511502SCurtis.Dunham@arm.comfinal_tick 47216814802000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711502SCurtis.Dunham@arm.comhost_inst_rate 1112312 # Simulator instruction rate (inst/s) 811502SCurtis.Dunham@arm.comhost_op_rate 1308465 # Simulator op (including micro ops) rate (op/s) 911502SCurtis.Dunham@arm.comhost_tick_rate 53753255119 # Simulator tick rate (ticks/s) 1011502SCurtis.Dunham@arm.comhost_mem_usage 687512 # Number of bytes of host memory used 1111502SCurtis.Dunham@arm.comhost_seconds 878.40 # Real time elapsed on the host 1211502SCurtis.Dunham@arm.comsim_insts 977053655 # Number of instructions simulated 1311502SCurtis.Dunham@arm.comsim_ops 1149354696 # Number of ops (including micro ops) simulated 1410515SN/Asystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SN/Asystem.clk_domain.clock 1000 # Clock period in ticks 1611502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 150336 # Number of bytes read from this memory 1711502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 124416 # Number of bytes read from this memory 1811502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.inst 3895860 # Number of bytes read from this memory 1911502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.data 34948936 # Number of bytes read from this memory 2011502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 222016 # Number of bytes read from this memory 2111502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.itb.walker 222656 # Number of bytes read from this memory 2211502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.inst 2668232 # Number of bytes read from this memory 2311502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.data 38725552 # Number of bytes read from this memory 2411502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::realview.ide 417728 # Number of bytes read from this memory 2511502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 81375732 # Number of bytes read from this memory 2611502SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 3895860 # Number of instructions bytes read from this memory 2711502SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 2668232 # Number of instructions bytes read from this memory 2811502SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 6564092 # Number of instructions bytes read from this memory 2911502SCurtis.Dunham@arm.comsystem.physmem.bytes_written::writebacks 101375872 # Number of bytes written to this memory 3010827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 3110585SN/Asystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3211502SCurtis.Dunham@arm.comsystem.physmem.bytes_written::total 101396456 # Number of bytes written to this memory 3311502SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 2349 # Number of read requests responded to by this memory 3411502SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.itb.walker 1944 # Number of read requests responded to by this memory 3511502SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.inst 101280 # Number of read requests responded to by this memory 3611502SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.data 546090 # Number of read requests responded to by this memory 3711502SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 3469 # Number of read requests responded to by this memory 3811502SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.itb.walker 3479 # Number of read requests responded to by this memory 3911502SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.inst 41798 # Number of read requests responded to by this memory 4011502SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.data 605103 # Number of read requests responded to by this memory 4111502SCurtis.Dunham@arm.comsystem.physmem.num_reads::realview.ide 6527 # Number of read requests responded to by this memory 4211502SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 1312039 # Number of read requests responded to by this memory 4311502SCurtis.Dunham@arm.comsystem.physmem.num_writes::writebacks 1583998 # Number of write requests responded to by this memory 4410827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 4510585SN/Asystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 4611502SCurtis.Dunham@arm.comsystem.physmem.num_writes::total 1586572 # Number of write requests responded to by this memory 4711502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 3184 # Total read bandwidth from this memory (bytes/s) 4811502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.itb.walker 2635 # Total read bandwidth from this memory (bytes/s) 4911502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.inst 82510 # Total read bandwidth from this memory (bytes/s) 5011502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.data 740180 # Total read bandwidth from this memory (bytes/s) 5111502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 4702 # Total read bandwidth from this memory (bytes/s) 5211502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.itb.walker 4716 # Total read bandwidth from this memory (bytes/s) 5311502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.inst 56510 # Total read bandwidth from this memory (bytes/s) 5411502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.data 820164 # Total read bandwidth from this memory (bytes/s) 5511502SCurtis.Dunham@arm.comsystem.physmem.bw_read::realview.ide 8847 # Total read bandwidth from this memory (bytes/s) 5611502SCurtis.Dunham@arm.comsystem.physmem.bw_read::total 1723448 # Total read bandwidth from this memory (bytes/s) 5711502SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu0.inst 82510 # Instruction read bandwidth from this memory (bytes/s) 5811502SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu1.inst 56510 # Instruction read bandwidth from this memory (bytes/s) 5911502SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::total 139020 # Instruction read bandwidth from this memory (bytes/s) 6011502SCurtis.Dunham@arm.comsystem.physmem.bw_write::writebacks 2147029 # Write bandwidth from this memory (bytes/s) 6111502SCurtis.Dunham@arm.comsystem.physmem.bw_write::cpu0.data 436 # Write bandwidth from this memory (bytes/s) 6210585SN/Asystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 6311502SCurtis.Dunham@arm.comsystem.physmem.bw_write::total 2147465 # Write bandwidth from this memory (bytes/s) 6411502SCurtis.Dunham@arm.comsystem.physmem.bw_total::writebacks 2147029 # Total bandwidth to/from this memory (bytes/s) 6511502SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 3184 # Total bandwidth to/from this memory (bytes/s) 6611502SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.itb.walker 2635 # Total bandwidth to/from this memory (bytes/s) 6711502SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.inst 82510 # Total bandwidth to/from this memory (bytes/s) 6811502SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.data 740616 # Total bandwidth to/from this memory (bytes/s) 6911502SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 4702 # Total bandwidth to/from this memory (bytes/s) 7011502SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.itb.walker 4716 # Total bandwidth to/from this memory (bytes/s) 7111502SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.inst 56510 # Total bandwidth to/from this memory (bytes/s) 7211502SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.data 820165 # Total bandwidth to/from this memory (bytes/s) 7311502SCurtis.Dunham@arm.comsystem.physmem.bw_total::realview.ide 8847 # Total bandwidth to/from this memory (bytes/s) 7411502SCurtis.Dunham@arm.comsystem.physmem.bw_total::total 3870913 # Total bandwidth to/from this memory (bytes/s) 7510515SN/Asystem.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 7610515SN/Asystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 7710515SN/Asystem.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 7810515SN/Asystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 7910515SN/Asystem.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 8010515SN/Asystem.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 8110515SN/Asystem.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 8210515SN/Asystem.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 8310515SN/Asystem.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 8410515SN/Asystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 8510515SN/Asystem.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 8610515SN/Asystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 8710515SN/Asystem.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 8810515SN/Asystem.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 8910515SN/Asystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 9010515SN/Asystem.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 9110515SN/Asystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 9210515SN/Asystem.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 9310515SN/Asystem.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 9410515SN/Asystem.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 9510515SN/Asystem.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 9610515SN/Asystem.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 9710515SN/Asystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 9810515SN/Asystem.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 9910515SN/Asystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 10010515SN/Asystem.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 10110585SN/Asystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 10210585SN/Asystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 10310585SN/Asystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 10410585SN/Asystem.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 10510585SN/Asystem.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 10610585SN/Asystem.cf0.dma_write_txs 1670 # Number of DMA write transactions. 10710515SN/Asystem.cpu_clk_domain.clock 500 # Clock period in ticks 10810628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 10910628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 11010628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 11110628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 11210628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 11310628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 11410628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 11510628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 11610585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 11710585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 11810585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 11910585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 12010585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 12110585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 12210585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 12310585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 12410585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 12510585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 12610585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 12710585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 12810585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 12910585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 13010585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 13110585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 13210585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 13310585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 13410585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 13510585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 13610585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 13711502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walks 124420 # Table walker walks requested 13811502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksLong 124420 # Table walker walks initiated with long descriptors 13911502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 124420 # Table walker wait (enqueue to first request) latency 14011502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0 124420 100.00% 100.00% # Table walker wait (enqueue to first request) latency 14111502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 124420 # Table walker wait (enqueue to first request) latency 14210628SN/Asystem.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution 14310628SN/Asystem.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution 14410628SN/Asystem.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution 14511502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 95857 89.92% 89.92% # Table walker page sizes translated 14611502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkPageSizes::2M 10751 10.08% 100.00% # Table walker page sizes translated 14711502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 106608 # Table walker page sizes translated 14811502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 124420 # Table walker requests started/completed, data/inst 14910628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 15011502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 124420 # Table walker requests started/completed, data/inst 15111502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106608 # Table walker requests started/completed, data/inst 15210628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 15311502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106608 # Table walker requests started/completed, data/inst 15411502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 231028 # Table walker requests started/completed, data/inst 15510585SN/Asystem.cpu0.dtb.inst_hits 0 # ITB inst hits 15610585SN/Asystem.cpu0.dtb.inst_misses 0 # ITB inst misses 15711502SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_hits 91801710 # DTB read hits 15811502SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_misses 88193 # DTB read misses 15911502SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_hits 84999619 # DTB write hits 16011502SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_misses 36227 # DTB write misses 16110585SN/Asystem.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed 16210585SN/Asystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 16311502SCurtis.Dunham@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID 16410585SN/Asystem.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 16511502SCurtis.Dunham@arm.comsystem.cpu0.dtb.flush_entries 36369 # Number of entries that have been flushed from TLB 16610585SN/Asystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 16711502SCurtis.Dunham@arm.comsystem.cpu0.dtb.prefetch_faults 5198 # Number of TLB faults due to prefetch 16810585SN/Asystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 16911502SCurtis.Dunham@arm.comsystem.cpu0.dtb.perms_faults 10393 # Number of TLB faults due to permissions restrictions 17011502SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_accesses 91889903 # DTB read accesses 17111502SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_accesses 85035846 # DTB write accesses 17210585SN/Asystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 17311502SCurtis.Dunham@arm.comsystem.cpu0.dtb.hits 176801329 # DTB hits 17411502SCurtis.Dunham@arm.comsystem.cpu0.dtb.misses 124420 # DTB misses 17511502SCurtis.Dunham@arm.comsystem.cpu0.dtb.accesses 176925749 # DTB accesses 17610628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 17710628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 17810628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 17910628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 18010628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 18110628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 18210628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 18310628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 18410585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 18510585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 18610585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 18710585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 18810585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 18910585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 19010585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 19110585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 19210585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 19310585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 19410585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 19510585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 19610585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 19710585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 19810585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 19910585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 20010585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 20110585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 20210585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 20310585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 20410585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 20511502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walks 60852 # Table walker walks requested 20611502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksLong 60852 # Table walker walks initiated with long descriptors 20711502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 60852 # Table walker wait (enqueue to first request) latency 20811502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkWaitTime::0 60852 100.00% 100.00% # Table walker wait (enqueue to first request) latency 20911502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 60852 # Table walker wait (enqueue to first request) latency 21010628SN/Asystem.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution 21110628SN/Asystem.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution 21210628SN/Asystem.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution 21311502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 54793 98.83% 98.83% # Table walker page sizes translated 21411502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkPageSizes::2M 650 1.17% 100.00% # Table walker page sizes translated 21511502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 55443 # Table walker page sizes translated 21610628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 21711502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60852 # Table walker requests started/completed, data/inst 21811502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 60852 # Table walker requests started/completed, data/inst 21910628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 22011502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55443 # Table walker requests started/completed, data/inst 22111502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 55443 # Table walker requests started/completed, data/inst 22211502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 116295 # Table walker requests started/completed, data/inst 22311502SCurtis.Dunham@arm.comsystem.cpu0.itb.inst_hits 493637993 # ITB inst hits 22411502SCurtis.Dunham@arm.comsystem.cpu0.itb.inst_misses 60852 # ITB inst misses 22510585SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 22610585SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 22710585SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 22810585SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 22910585SN/Asystem.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed 23010585SN/Asystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 23111502SCurtis.Dunham@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID 23210585SN/Asystem.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 23311502SCurtis.Dunham@arm.comsystem.cpu0.itb.flush_entries 25117 # Number of entries that have been flushed from TLB 23410585SN/Asystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 23510585SN/Asystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 23610585SN/Asystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 23710585SN/Asystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 23810585SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 23910585SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 24011502SCurtis.Dunham@arm.comsystem.cpu0.itb.inst_accesses 493698845 # ITB inst accesses 24111502SCurtis.Dunham@arm.comsystem.cpu0.itb.hits 493637993 # DTB hits 24211502SCurtis.Dunham@arm.comsystem.cpu0.itb.misses 60852 # DTB misses 24311502SCurtis.Dunham@arm.comsystem.cpu0.itb.accesses 493698845 # DTB accesses 24411502SCurtis.Dunham@arm.comsystem.cpu0.numCycles 94433642835 # number of cpu cycles simulated 24510585SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 24610585SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 24711167Sjthestness@gmail.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 24811502SCurtis.Dunham@arm.comsystem.cpu0.kern.inst.quiesce 13230 # number of quiesce instructions executed 24911502SCurtis.Dunham@arm.comsystem.cpu0.committedInsts 493402150 # Number of instructions committed 25011502SCurtis.Dunham@arm.comsystem.cpu0.committedOps 580232432 # Number of ops (including micro ops) committed 25111502SCurtis.Dunham@arm.comsystem.cpu0.num_int_alu_accesses 531778274 # Number of integer alu accesses 25211502SCurtis.Dunham@arm.comsystem.cpu0.num_fp_alu_accesses 521057 # Number of float alu accesses 25311502SCurtis.Dunham@arm.comsystem.cpu0.num_func_calls 28738017 # number of times a function call or return occured 25411502SCurtis.Dunham@arm.comsystem.cpu0.num_conditional_control_insts 75812609 # number of instructions that are conditional controls 25511502SCurtis.Dunham@arm.comsystem.cpu0.num_int_insts 531778274 # number of integer instructions 25611502SCurtis.Dunham@arm.comsystem.cpu0.num_fp_insts 521057 # number of float instructions 25711502SCurtis.Dunham@arm.comsystem.cpu0.num_int_register_reads 778807297 # number of times the integer registers were read 25811502SCurtis.Dunham@arm.comsystem.cpu0.num_int_register_writes 421918818 # number of times the integer registers were written 25911502SCurtis.Dunham@arm.comsystem.cpu0.num_fp_register_reads 841474 # number of times the floating registers were read 26011502SCurtis.Dunham@arm.comsystem.cpu0.num_fp_register_writes 439940 # number of times the floating registers were written 26111502SCurtis.Dunham@arm.comsystem.cpu0.num_cc_register_reads 132610797 # number of times the CC registers were read 26211502SCurtis.Dunham@arm.comsystem.cpu0.num_cc_register_writes 132275173 # number of times the CC registers were written 26311502SCurtis.Dunham@arm.comsystem.cpu0.num_mem_refs 176902115 # number of memory refs 26411502SCurtis.Dunham@arm.comsystem.cpu0.num_load_insts 91875039 # Number of load instructions 26511502SCurtis.Dunham@arm.comsystem.cpu0.num_store_insts 85027076 # Number of store instructions 26611502SCurtis.Dunham@arm.comsystem.cpu0.num_idle_cycles 93853071494.060760 # Number of idle cycles 26711502SCurtis.Dunham@arm.comsystem.cpu0.num_busy_cycles 580571340.939238 # Number of busy cycles 26811502SCurtis.Dunham@arm.comsystem.cpu0.not_idle_fraction 0.006148 # Percentage of non-idle cycles 26911502SCurtis.Dunham@arm.comsystem.cpu0.idle_fraction 0.993852 # Percentage of idle cycles 27011502SCurtis.Dunham@arm.comsystem.cpu0.Branches 110403926 # Number of branches fetched 27110585SN/Asystem.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 27211502SCurtis.Dunham@arm.comsystem.cpu0.op_class::IntAlu 402310075 69.30% 69.30% # Class of executed instruction 27311502SCurtis.Dunham@arm.comsystem.cpu0.op_class::IntMult 1222689 0.21% 69.51% # Class of executed instruction 27411502SCurtis.Dunham@arm.comsystem.cpu0.op_class::IntDiv 59704 0.01% 69.52% # Class of executed instruction 27511336Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction 27611336Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction 27711336Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction 27811336Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction 27911336Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction 28011336Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction 28111336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction 28211336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction 28311336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction 28411336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction 28511336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction 28611336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction 28711336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction 28811336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction 28911336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction 29011336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction 29111336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction 29211336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAdd 8 0.00% 69.52% # Class of executed instruction 29311336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction 29411336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCmp 13 0.00% 69.52% # Class of executed instruction 29511336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCvt 21 0.00% 69.52% # Class of executed instruction 29611336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction 29711502SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatMisc 72217 0.01% 69.53% # Class of executed instruction 29811336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 69.53% # Class of executed instruction 29911336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.53% # Class of executed instruction 30011336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.53% # Class of executed instruction 30111502SCurtis.Dunham@arm.comsystem.cpu0.op_class::MemRead 91875039 15.83% 85.35% # Class of executed instruction 30211502SCurtis.Dunham@arm.comsystem.cpu0.op_class::MemWrite 85027076 14.65% 100.00% # Class of executed instruction 30310585SN/Asystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 30410585SN/Asystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 30511502SCurtis.Dunham@arm.comsystem.cpu0.op_class::total 580566843 # Class of executed instruction 30611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.replacements 6218107 # number of replacements 30711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.tagsinuse 503.352532 # Cycle average of tags in use 30811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.total_refs 170512705 # Total number of references to valid blocks. 30911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.sampled_refs 6218619 # Sample count of references to valid blocks. 31011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.avg_refs 27.419706 # Average number of references to valid blocks. 31110827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. 31211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 503.352532 # Average occupied blocks per requestor 31311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.983110 # Average percentage of cache occupancy 31411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.983110 # Average percentage of cache occupancy 31510585SN/Asystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 31611336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id 31711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id 31811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id 31910585SN/Asystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 32011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.tag_accesses 359988587 # Number of tag accesses 32111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.data_accesses 359988587 # Number of data accesses 32211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 85387960 # number of ReadReq hits 32311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_hits::total 85387960 # number of ReadReq hits 32411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 80242803 # number of WriteReq hits 32511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_hits::total 80242803 # number of WriteReq hits 32611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 214677 # number of SoftPFReq hits 32711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 214677 # number of SoftPFReq hits 32811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_hits::cpu0.data 260385 # number of WriteLineReq hits 32911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_hits::total 260385 # number of WriteLineReq hits 33011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2076595 # number of LoadLockedReq hits 33111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 2076595 # number of LoadLockedReq hits 33211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 2038168 # number of StoreCondReq hits 33311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 2038168 # number of StoreCondReq hits 33411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 165891148 # number of demand (read+write) hits 33511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_hits::total 165891148 # number of demand (read+write) hits 33611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 166105825 # number of overall hits 33711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_hits::total 166105825 # number of overall hits 33811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 3280646 # number of ReadReq misses 33911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_misses::total 3280646 # number of ReadReq misses 34011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 1472125 # number of WriteReq misses 34111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_misses::total 1472125 # number of WriteReq misses 34211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 768471 # number of SoftPFReq misses 34311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 768471 # number of SoftPFReq misses 34411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_misses::cpu0.data 819890 # number of WriteLineReq misses 34511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_misses::total 819890 # number of WriteLineReq misses 34611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 117360 # number of LoadLockedReq misses 34711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 117360 # number of LoadLockedReq misses 34811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 154684 # number of StoreCondReq misses 34911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 154684 # number of StoreCondReq misses 35011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 5572661 # number of demand (read+write) misses 35111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_misses::total 5572661 # number of demand (read+write) misses 35211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 6341132 # number of overall misses 35311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_misses::total 6341132 # number of overall misses 35411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 88668606 # number of ReadReq accesses(hits+misses) 35511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 88668606 # number of ReadReq accesses(hits+misses) 35611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 81714928 # number of WriteReq accesses(hits+misses) 35711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 81714928 # number of WriteReq accesses(hits+misses) 35811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 983148 # number of SoftPFReq accesses(hits+misses) 35911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 983148 # number of SoftPFReq accesses(hits+misses) 36011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1080275 # number of WriteLineReq accesses(hits+misses) 36111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::total 1080275 # number of WriteLineReq accesses(hits+misses) 36211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2193955 # number of LoadLockedReq accesses(hits+misses) 36311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 2193955 # number of LoadLockedReq accesses(hits+misses) 36411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2192852 # number of StoreCondReq accesses(hits+misses) 36511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 2192852 # number of StoreCondReq accesses(hits+misses) 36611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 171463809 # number of demand (read+write) accesses 36711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_accesses::total 171463809 # number of demand (read+write) accesses 36811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 172446957 # number of overall (read+write) accesses 36911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_accesses::total 172446957 # number of overall (read+write) accesses 37011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036999 # miss rate for ReadReq accesses 37111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.036999 # miss rate for ReadReq accesses 37211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018015 # miss rate for WriteReq accesses 37311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.018015 # miss rate for WriteReq accesses 37411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781643 # miss rate for SoftPFReq accesses 37511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.781643 # miss rate for SoftPFReq accesses 37611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.758964 # miss rate for WriteLineReq accesses 37711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::total 0.758964 # miss rate for WriteLineReq accesses 37811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053492 # miss rate for LoadLockedReq accesses 37911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053492 # miss rate for LoadLockedReq accesses 38011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.070540 # miss rate for StoreCondReq accesses 38111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.070540 # miss rate for StoreCondReq accesses 38211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.032501 # miss rate for demand accesses 38311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.032501 # miss rate for demand accesses 38411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.036771 # miss rate for overall accesses 38511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.036771 # miss rate for overall accesses 38610585SN/Asystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 38710585SN/Asystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 38810585SN/Asystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 38910585SN/Asystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 39010585SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 39110585SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 39211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.writebacks::writebacks 6218107 # number of writebacks 39311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.writebacks::total 6218107 # number of writebacks 39411502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.replacements 5488502 # number of replacements 39511502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.tagsinuse 511.989005 # Cycle average of tags in use 39611502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.total_refs 488204417 # Total number of references to valid blocks. 39711502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.sampled_refs 5489014 # Sample count of references to valid blocks. 39811502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.avg_refs 88.942097 # Average number of references to valid blocks. 39910585SN/Asystem.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit. 40011502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989005 # Average occupied blocks per requestor 40110585SN/Asystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy 40210585SN/Asystem.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy 40310585SN/Asystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 40411502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id 40511502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id 40611502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id 40711502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 40810585SN/Asystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 40911502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.tag_accesses 992875891 # Number of tag accesses 41011502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.data_accesses 992875891 # Number of data accesses 41111502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 488204417 # number of ReadReq hits 41211502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_hits::total 488204417 # number of ReadReq hits 41311502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 488204417 # number of demand (read+write) hits 41411502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_hits::total 488204417 # number of demand (read+write) hits 41511502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 488204417 # number of overall hits 41611502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_hits::total 488204417 # number of overall hits 41711502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 5489019 # number of ReadReq misses 41811502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_misses::total 5489019 # number of ReadReq misses 41911502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 5489019 # number of demand (read+write) misses 42011502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_misses::total 5489019 # number of demand (read+write) misses 42111502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 5489019 # number of overall misses 42211502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_misses::total 5489019 # number of overall misses 42311502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 493693436 # number of ReadReq accesses(hits+misses) 42411502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_accesses::total 493693436 # number of ReadReq accesses(hits+misses) 42511502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 493693436 # number of demand (read+write) accesses 42611502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_accesses::total 493693436 # number of demand (read+write) accesses 42711502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 493693436 # number of overall (read+write) accesses 42811502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_accesses::total 493693436 # number of overall (read+write) accesses 42911502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011118 # miss rate for ReadReq accesses 43011502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.011118 # miss rate for ReadReq accesses 43111502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.011118 # miss rate for demand accesses 43211502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.011118 # miss rate for demand accesses 43311502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.011118 # miss rate for overall accesses 43411502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.011118 # miss rate for overall accesses 43510585SN/Asystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 43610585SN/Asystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 43710585SN/Asystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 43810585SN/Asystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 43910585SN/Asystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 44010585SN/Asystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 44111502SCurtis.Dunham@arm.comsystem.cpu0.icache.writebacks::writebacks 5488502 # number of writebacks 44211502SCurtis.Dunham@arm.comsystem.cpu0.icache.writebacks::total 5488502 # number of writebacks 44310628SN/Asystem.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 44410628SN/Asystem.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 44510628SN/Asystem.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 44610628SN/Asystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 44710628SN/Asystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 44810628SN/Asystem.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 44911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.replacements 2643580 # number of replacements 45011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.tagsinuse 16147.870386 # Cycle average of tags in use 45111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.total_refs 15444293 # Total number of references to valid blocks. 45211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.sampled_refs 2659582 # Sample count of references to valid blocks. 45311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.avg_refs 5.807038 # Average number of references to valid blocks. 45410585SN/Asystem.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. 45511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 16070.787170 # Average occupied blocks per requestor 45611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 39.567916 # Average occupied blocks per requestor 45711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 37.515300 # Average occupied blocks per requestor 45811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.980883 # Average percentage of cache occupancy 45911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002415 # Average percentage of cache occupancy 46011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.002290 # Average percentage of cache occupancy 46111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.985588 # Average percentage of cache occupancy 46211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 53 # Occupied blocks per task id 46311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 15949 # Occupied blocks per task id 46411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 39 # Occupied blocks per task id 46511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id 46611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id 46711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id 46811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1503 # Occupied blocks per task id 46911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4323 # Occupied blocks per task id 47011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5407 # Occupied blocks per task id 47111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4485 # Occupied blocks per task id 47211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003235 # Percentage of cache occupancy per task id 47311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.973450 # Percentage of cache occupancy per task id 47411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.tag_accesses 394033422 # Number of tag accesses 47511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.data_accesses 394033422 # Number of data accesses 47611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 293436 # number of ReadReq hits 47711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 155846 # number of ReadReq hits 47811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 449282 # number of ReadReq hits 47911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::writebacks 4423360 # number of WritebackDirty hits 48011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::total 4423360 # number of WritebackDirty hits 48111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_hits::writebacks 7281875 # number of WritebackClean hits 48211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_hits::total 7281875 # number of WritebackClean hits 48311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::cpu0.data 738 # number of UpgradeReq hits 48411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::total 738 # number of UpgradeReq hits 48511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 633298 # number of ReadExReq hits 48611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 633298 # number of ReadExReq hits 48711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4991790 # number of ReadCleanReq hits 48811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 4991790 # number of ReadCleanReq hits 48911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2937635 # number of ReadSharedReq hits 49011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 2937635 # number of ReadSharedReq hits 49111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::cpu0.data 218374 # number of InvalidateReq hits 49211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::total 218374 # number of InvalidateReq hits 49311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 293436 # number of demand (read+write) hits 49411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 155846 # number of demand (read+write) hits 49511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 4991790 # number of demand (read+write) hits 49611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 3570933 # number of demand (read+write) hits 49711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::total 9012005 # number of demand (read+write) hits 49811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 293436 # number of overall hits 49911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 155846 # number of overall hits 50011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 4991790 # number of overall hits 50111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 3570933 # number of overall hits 50211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::total 9012005 # number of overall hits 50311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11306 # number of ReadReq misses 50411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8709 # number of ReadReq misses 50511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 20015 # number of ReadReq misses 50611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 136695 # number of UpgradeReq misses 50711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 136695 # number of UpgradeReq misses 50811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 154684 # number of SCUpgradeReq misses 50911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 154684 # number of SCUpgradeReq misses 51011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 701772 # number of ReadExReq misses 51111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 701772 # number of ReadExReq misses 51211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 497229 # number of ReadCleanReq misses 51311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 497229 # number of ReadCleanReq misses 51411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1228842 # number of ReadSharedReq misses 51511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 1228842 # number of ReadSharedReq misses 51611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::cpu0.data 601138 # number of InvalidateReq misses 51711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::total 601138 # number of InvalidateReq misses 51811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11306 # number of demand (read+write) misses 51911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 8709 # number of demand (read+write) misses 52011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 497229 # number of demand (read+write) misses 52111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 1930614 # number of demand (read+write) misses 52211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::total 2447858 # number of demand (read+write) misses 52311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11306 # number of overall misses 52411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 8709 # number of overall misses 52511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 497229 # number of overall misses 52611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 1930614 # number of overall misses 52711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::total 2447858 # number of overall misses 52811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 304742 # number of ReadReq accesses(hits+misses) 52911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 164555 # number of ReadReq accesses(hits+misses) 53011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 469297 # number of ReadReq accesses(hits+misses) 53111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::writebacks 4423360 # number of WritebackDirty accesses(hits+misses) 53211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::total 4423360 # number of WritebackDirty accesses(hits+misses) 53311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::writebacks 7281875 # number of WritebackClean accesses(hits+misses) 53411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::total 7281875 # number of WritebackClean accesses(hits+misses) 53511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 137433 # number of UpgradeReq accesses(hits+misses) 53611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 137433 # number of UpgradeReq accesses(hits+misses) 53711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 154684 # number of SCUpgradeReq accesses(hits+misses) 53811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 154684 # number of SCUpgradeReq accesses(hits+misses) 53911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1335070 # number of ReadExReq accesses(hits+misses) 54011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1335070 # number of ReadExReq accesses(hits+misses) 54111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5489019 # number of ReadCleanReq accesses(hits+misses) 54211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 5489019 # number of ReadCleanReq accesses(hits+misses) 54311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4166477 # number of ReadSharedReq accesses(hits+misses) 54411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 4166477 # number of ReadSharedReq accesses(hits+misses) 54511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 819512 # number of InvalidateReq accesses(hits+misses) 54611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::total 819512 # number of InvalidateReq accesses(hits+misses) 54711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 304742 # number of demand (read+write) accesses 54811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 164555 # number of demand (read+write) accesses 54911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 5489019 # number of demand (read+write) accesses 55011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 5501547 # number of demand (read+write) accesses 55111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::total 11459863 # number of demand (read+write) accesses 55211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 304742 # number of overall (read+write) accesses 55311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 164555 # number of overall (read+write) accesses 55411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 5489019 # number of overall (read+write) accesses 55511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 5501547 # number of overall (read+write) accesses 55611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::total 11459863 # number of overall (read+write) accesses 55711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.037100 # miss rate for ReadReq accesses 55811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052925 # miss rate for ReadReq accesses 55911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.042649 # miss rate for ReadReq accesses 56011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.994630 # miss rate for UpgradeReq accesses 56111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 0.994630 # miss rate for UpgradeReq accesses 56210585SN/Asystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 56310585SN/Asystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 56411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.525644 # miss rate for ReadExReq accesses 56511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.525644 # miss rate for ReadExReq accesses 56611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.090586 # miss rate for ReadCleanReq accesses 56711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.090586 # miss rate for ReadCleanReq accesses 56811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.294936 # miss rate for ReadSharedReq accesses 56911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.294936 # miss rate for ReadSharedReq accesses 57011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.733532 # miss rate for InvalidateReq accesses 57111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::total 0.733532 # miss rate for InvalidateReq accesses 57211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.037100 # miss rate for demand accesses 57311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052925 # miss rate for demand accesses 57411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.090586 # miss rate for demand accesses 57511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.350922 # miss rate for demand accesses 57611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.213603 # miss rate for demand accesses 57711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.037100 # miss rate for overall accesses 57811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052925 # miss rate for overall accesses 57911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.090586 # miss rate for overall accesses 58011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.350922 # miss rate for overall accesses 58111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.213603 # miss rate for overall accesses 58210585SN/Asystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 58310585SN/Asystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 58410585SN/Asystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 58510585SN/Asystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 58610585SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 58710585SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 58811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.writebacks::writebacks 1554149 # number of writebacks 58911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.writebacks::total 1554149 # number of writebacks 59011502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_requests 24067586 # Total number of requests made to the snoop filter. 59111502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_requests 12257514 # Number of requests hitting in the snoop filter with a single holder of the requested data. 59211502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1374 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 59311502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_snoops 1770017 # Total number of snoops made to the snoop filter. 59411502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1769681 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 59511502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 336 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 59611502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 619965 # Transaction distribution 59711502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 10275461 # Transaction distribution 59811502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 33238 # Transaction distribution 59911502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 33238 # Transaction distribution 60011502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackDirty 4423360 # Transaction distribution 60111502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackClean 7283249 # Transaction distribution 60211502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 137433 # Transaction distribution 60311502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 154684 # Transaction distribution 60411502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 292117 # Transaction distribution 60511502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1335070 # Transaction distribution 60611502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1335070 # Transaction distribution 60711502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 5489019 # Transaction distribution 60811502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 4166477 # Transaction distribution 60911502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateReq 819512 # Transaction distribution 61011502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateResp 819512 # Transaction distribution 61111502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16552790 # Packet count per connected master and slave (bytes) 61211502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19577101 # Packet count per connected master and slave (bytes) 61311502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 363556 # Packet count per connected master and slave (bytes) 61411502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 723958 # Packet count per connected master and slave (bytes) 61511502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count::total 37217405 # Packet count per connected master and slave (bytes) 61611502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 702733844 # Cumulative packet size per connected master and slave (bytes) 61711502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 750256336 # Cumulative packet size per connected master and slave (bytes) 61811502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1454224 # Cumulative packet size per connected master and slave (bytes) 61911502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2895832 # Cumulative packet size per connected master and slave (bytes) 62011502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size::total 1457340236 # Cumulative packet size per connected master and slave (bytes) 62111502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoops 6073545 # Total snoops (count) 62211502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 30354370 # Request fanout histogram 62311502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 0.066939 # Request fanout histogram 62411502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.249960 # Request fanout histogram 62510585SN/Asystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 62611502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 28322817 93.31% 93.31% # Request fanout histogram 62711502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 2031217 6.69% 100.00% # Request fanout histogram 62811502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 336 0.00% 100.00% # Request fanout histogram 62910585SN/Asystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 63011138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 63110827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 63211502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 30354370 # Request fanout histogram 63310628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 63410628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 63510628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 63610628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 63710628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 63810628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 63910628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 64010628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 64110585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 64210585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 64310585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 64410585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 64510585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 64610585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 64710585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 64810585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 64910585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 65010585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 65110585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 65210585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 65310585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 65410585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 65510585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 65610585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 65710585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 65810585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 65910585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 66010585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 66110585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 66211502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walks 144355 # Table walker walks requested 66311502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksLong 144355 # Table walker walks initiated with long descriptors 66411502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 144355 # Table walker wait (enqueue to first request) latency 66511502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0 144355 100.00% 100.00% # Table walker wait (enqueue to first request) latency 66611502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 144355 # Table walker wait (enqueue to first request) latency 66710628SN/Asystem.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution 66810628SN/Asystem.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution 66910628SN/Asystem.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution 67011502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 111959 88.88% 88.88% # Table walker page sizes translated 67111502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkPageSizes::2M 14012 11.12% 100.00% # Table walker page sizes translated 67211502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 125971 # Table walker page sizes translated 67311502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144355 # Table walker requests started/completed, data/inst 67410628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 67511502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144355 # Table walker requests started/completed, data/inst 67611502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 125971 # Table walker requests started/completed, data/inst 67710628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 67811502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 125971 # Table walker requests started/completed, data/inst 67911502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 270326 # Table walker requests started/completed, data/inst 68010585SN/Asystem.cpu1.dtb.inst_hits 0 # ITB inst hits 68110585SN/Asystem.cpu1.dtb.inst_misses 0 # ITB inst misses 68211502SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_hits 91325952 # DTB read hits 68311502SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_misses 111931 # DTB read misses 68411502SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_hits 82141676 # DTB write hits 68511502SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_misses 32424 # DTB write misses 68610585SN/Asystem.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed 68710585SN/Asystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 68811502SCurtis.Dunham@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID 68910585SN/Asystem.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 69011502SCurtis.Dunham@arm.comsystem.cpu1.dtb.flush_entries 44858 # Number of entries that have been flushed from TLB 69110585SN/Asystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 69211502SCurtis.Dunham@arm.comsystem.cpu1.dtb.prefetch_faults 4450 # Number of TLB faults due to prefetch 69310585SN/Asystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 69411502SCurtis.Dunham@arm.comsystem.cpu1.dtb.perms_faults 11485 # Number of TLB faults due to permissions restrictions 69511502SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_accesses 91437883 # DTB read accesses 69611502SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_accesses 82174100 # DTB write accesses 69710585SN/Asystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 69811502SCurtis.Dunham@arm.comsystem.cpu1.dtb.hits 173467628 # DTB hits 69911502SCurtis.Dunham@arm.comsystem.cpu1.dtb.misses 144355 # DTB misses 70011502SCurtis.Dunham@arm.comsystem.cpu1.dtb.accesses 173611983 # DTB accesses 70110628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 70210628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 70310628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 70410628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 70510628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 70610628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 70710628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 70810628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 70910585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 71010585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 71110585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 71210585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 71310585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 71410585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 71510585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 71610585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 71710585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 71810585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 71910585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 72010585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 72110585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 72210585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 72310585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 72410585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 72510585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 72610585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 72710585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 72810585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 72910585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 73011502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walks 61638 # Table walker walks requested 73111502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksLong 61638 # Table walker walks initiated with long descriptors 73211502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 61638 # Table walker wait (enqueue to first request) latency 73311502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkWaitTime::0 61638 100.00% 100.00% # Table walker wait (enqueue to first request) latency 73411502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 61638 # Table walker wait (enqueue to first request) latency 73510628SN/Asystem.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution 73610628SN/Asystem.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution 73710628SN/Asystem.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution 73811502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 54650 99.05% 99.05% # Table walker page sizes translated 73911502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkPageSizes::2M 526 0.95% 100.00% # Table walker page sizes translated 74011502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 55176 # Table walker page sizes translated 74110628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 74211502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61638 # Table walker requests started/completed, data/inst 74311502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 61638 # Table walker requests started/completed, data/inst 74410628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 74511502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55176 # Table walker requests started/completed, data/inst 74611502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 55176 # Table walker requests started/completed, data/inst 74711502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 116814 # Table walker requests started/completed, data/inst 74811502SCurtis.Dunham@arm.comsystem.cpu1.itb.inst_hits 483902380 # ITB inst hits 74911502SCurtis.Dunham@arm.comsystem.cpu1.itb.inst_misses 61638 # ITB inst misses 75010585SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 75110585SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 75210585SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 75310585SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 75410585SN/Asystem.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed 75510585SN/Asystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 75611502SCurtis.Dunham@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID 75710585SN/Asystem.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 75811502SCurtis.Dunham@arm.comsystem.cpu1.itb.flush_entries 31512 # Number of entries that have been flushed from TLB 75910585SN/Asystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 76010585SN/Asystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 76110585SN/Asystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 76210585SN/Asystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 76310585SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 76410585SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 76511502SCurtis.Dunham@arm.comsystem.cpu1.itb.inst_accesses 483964018 # ITB inst accesses 76611502SCurtis.Dunham@arm.comsystem.cpu1.itb.hits 483902380 # DTB hits 76711502SCurtis.Dunham@arm.comsystem.cpu1.itb.misses 61638 # DTB misses 76811502SCurtis.Dunham@arm.comsystem.cpu1.itb.accesses 483964018 # DTB accesses 76911502SCurtis.Dunham@arm.comsystem.cpu1.numCycles 94433635768 # number of cpu cycles simulated 77010585SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 77110585SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 77211167Sjthestness@gmail.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 77311502SCurtis.Dunham@arm.comsystem.cpu1.kern.inst.quiesce 6163 # number of quiesce instructions executed 77411502SCurtis.Dunham@arm.comsystem.cpu1.committedInsts 483651505 # Number of instructions committed 77511502SCurtis.Dunham@arm.comsystem.cpu1.committedOps 569122264 # Number of ops (including micro ops) committed 77611502SCurtis.Dunham@arm.comsystem.cpu1.num_int_alu_accesses 522328734 # Number of integer alu accesses 77711502SCurtis.Dunham@arm.comsystem.cpu1.num_fp_alu_accesses 379089 # Number of float alu accesses 77811502SCurtis.Dunham@arm.comsystem.cpu1.num_func_calls 28525698 # number of times a function call or return occured 77911502SCurtis.Dunham@arm.comsystem.cpu1.num_conditional_control_insts 74077236 # number of instructions that are conditional controls 78011502SCurtis.Dunham@arm.comsystem.cpu1.num_int_insts 522328734 # number of integer instructions 78111502SCurtis.Dunham@arm.comsystem.cpu1.num_fp_insts 379089 # number of float instructions 78211502SCurtis.Dunham@arm.comsystem.cpu1.num_int_register_reads 771436981 # number of times the integer registers were read 78311502SCurtis.Dunham@arm.comsystem.cpu1.num_int_register_writes 415765246 # number of times the integer registers were written 78411502SCurtis.Dunham@arm.comsystem.cpu1.num_fp_register_reads 615128 # number of times the floating registers were read 78511502SCurtis.Dunham@arm.comsystem.cpu1.num_fp_register_writes 311192 # number of times the floating registers were written 78611502SCurtis.Dunham@arm.comsystem.cpu1.num_cc_register_reads 127876698 # number of times the CC registers were read 78711502SCurtis.Dunham@arm.comsystem.cpu1.num_cc_register_writes 127597836 # number of times the CC registers were written 78811502SCurtis.Dunham@arm.comsystem.cpu1.num_mem_refs 173588529 # number of memory refs 78911502SCurtis.Dunham@arm.comsystem.cpu1.num_load_insts 91424864 # Number of load instructions 79011502SCurtis.Dunham@arm.comsystem.cpu1.num_store_insts 82163665 # Number of store instructions 79111502SCurtis.Dunham@arm.comsystem.cpu1.num_idle_cycles 93864202487.047195 # Number of idle cycles 79211502SCurtis.Dunham@arm.comsystem.cpu1.num_busy_cycles 569433280.952807 # Number of busy cycles 79311502SCurtis.Dunham@arm.comsystem.cpu1.not_idle_fraction 0.006030 # Percentage of non-idle cycles 79411502SCurtis.Dunham@arm.comsystem.cpu1.idle_fraction 0.993970 # Percentage of idle cycles 79511502SCurtis.Dunham@arm.comsystem.cpu1.Branches 107756231 # Number of branches fetched 79610585SN/Asystem.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 79711502SCurtis.Dunham@arm.comsystem.cpu1.op_class::IntAlu 394594292 69.30% 69.30% # Class of executed instruction 79811502SCurtis.Dunham@arm.comsystem.cpu1.op_class::IntMult 1146816 0.20% 69.50% # Class of executed instruction 79911502SCurtis.Dunham@arm.comsystem.cpu1.op_class::IntDiv 61459 0.01% 69.51% # Class of executed instruction 80011502SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction 80111502SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction 80211502SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction 80311502SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction 80411502SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction 80511502SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction 80611502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction 80711502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction 80811502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction 80911502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction 81011502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction 81111502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction 81211502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction 81311502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction 81411502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction 81511502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction 81611502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction 81711502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatAdd 0 0.00% 69.51% # Class of executed instruction 81811502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction 81911502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatCmp 0 0.00% 69.51% # Class of executed instruction 82011502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatCvt 0 0.00% 69.51% # Class of executed instruction 82111502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction 82211502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatMisc 37349 0.01% 69.52% # Class of executed instruction 82311336Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction 82411336Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction 82511336Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction 82611502SCurtis.Dunham@arm.comsystem.cpu1.op_class::MemRead 91424864 16.06% 85.57% # Class of executed instruction 82711502SCurtis.Dunham@arm.comsystem.cpu1.op_class::MemWrite 82163665 14.43% 100.00% # Class of executed instruction 82810585SN/Asystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 82910585SN/Asystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 83011502SCurtis.Dunham@arm.comsystem.cpu1.op_class::total 569428445 # Class of executed instruction 83111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.replacements 6003966 # number of replacements 83211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.tagsinuse 423.687505 # Cycle average of tags in use 83311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.total_refs 167475451 # Total number of references to valid blocks. 83411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.sampled_refs 6004478 # Sample count of references to valid blocks. 83511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.avg_refs 27.891759 # Average number of references to valid blocks. 83610585SN/Asystem.cpu1.dcache.tags.warmup_cycle 8470277778500 # Cycle when the warmup percentage was hit. 83711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 423.687505 # Average occupied blocks per requestor 83811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.827515 # Average percentage of cache occupancy 83911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.827515 # Average percentage of cache occupancy 84010726SN/Asystem.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 84111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 248 # Occupied blocks per task id 84211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 264 # Occupied blocks per task id 84310726SN/Asystem.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 84411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.tag_accesses 353236361 # Number of tag accesses 84511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.data_accesses 353236361 # Number of data accesses 84611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 84832048 # number of ReadReq hits 84711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_hits::total 84832048 # number of ReadReq hits 84811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 77963660 # number of WriteReq hits 84911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_hits::total 77963660 # number of WriteReq hits 85011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 187526 # number of SoftPFReq hits 85111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 187526 # number of SoftPFReq hits 85211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_hits::cpu1.data 65427 # number of WriteLineReq hits 85311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_hits::total 65427 # number of WriteLineReq hits 85411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2067288 # number of LoadLockedReq hits 85511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 2067288 # number of LoadLockedReq hits 85611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 2056969 # number of StoreCondReq hits 85711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 2056969 # number of StoreCondReq hits 85811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 162861135 # number of demand (read+write) hits 85911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_hits::total 162861135 # number of demand (read+write) hits 86011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 163048661 # number of overall hits 86111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_hits::total 163048661 # number of overall hits 86211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 3388721 # number of ReadReq misses 86311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_misses::total 3388721 # number of ReadReq misses 86411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 1469364 # number of WriteReq misses 86511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_misses::total 1469364 # number of WriteReq misses 86611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 795051 # number of SoftPFReq misses 86711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 795051 # number of SoftPFReq misses 86811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_misses::cpu1.data 438458 # number of WriteLineReq misses 86911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_misses::total 438458 # number of WriteLineReq misses 87011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 148516 # number of LoadLockedReq misses 87111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 148516 # number of LoadLockedReq misses 87211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 157576 # number of StoreCondReq misses 87311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 157576 # number of StoreCondReq misses 87411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 5296543 # number of demand (read+write) misses 87511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_misses::total 5296543 # number of demand (read+write) misses 87611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 6091594 # number of overall misses 87711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_misses::total 6091594 # number of overall misses 87811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 88220769 # number of ReadReq accesses(hits+misses) 87911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 88220769 # number of ReadReq accesses(hits+misses) 88011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 79433024 # number of WriteReq accesses(hits+misses) 88111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 79433024 # number of WriteReq accesses(hits+misses) 88211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 982577 # number of SoftPFReq accesses(hits+misses) 88311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 982577 # number of SoftPFReq accesses(hits+misses) 88411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::cpu1.data 503885 # number of WriteLineReq accesses(hits+misses) 88511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::total 503885 # number of WriteLineReq accesses(hits+misses) 88611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2215804 # number of LoadLockedReq accesses(hits+misses) 88711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 2215804 # number of LoadLockedReq accesses(hits+misses) 88811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2214545 # number of StoreCondReq accesses(hits+misses) 88911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 2214545 # number of StoreCondReq accesses(hits+misses) 89011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 168157678 # number of demand (read+write) accesses 89111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_accesses::total 168157678 # number of demand (read+write) accesses 89211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 169140255 # number of overall (read+write) accesses 89311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_accesses::total 169140255 # number of overall (read+write) accesses 89411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038412 # miss rate for ReadReq accesses 89511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.038412 # miss rate for ReadReq accesses 89611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018498 # miss rate for WriteReq accesses 89711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.018498 # miss rate for WriteReq accesses 89811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.809149 # miss rate for SoftPFReq accesses 89911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.809149 # miss rate for SoftPFReq accesses 90011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870155 # miss rate for WriteLineReq accesses 90111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::total 0.870155 # miss rate for WriteLineReq accesses 90211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.067026 # miss rate for LoadLockedReq accesses 90311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.067026 # miss rate for LoadLockedReq accesses 90411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071155 # miss rate for StoreCondReq accesses 90511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.071155 # miss rate for StoreCondReq accesses 90611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.031497 # miss rate for demand accesses 90711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.031497 # miss rate for demand accesses 90811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.036015 # miss rate for overall accesses 90911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.036015 # miss rate for overall accesses 91010585SN/Asystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 91110585SN/Asystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 91210585SN/Asystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 91310585SN/Asystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 91410585SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 91510585SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 91611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.writebacks::writebacks 6003966 # number of writebacks 91711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.writebacks::total 6003966 # number of writebacks 91811502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.replacements 4799154 # number of replacements 91911502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.tagsinuse 496.426080 # Cycle average of tags in use 92011502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.total_refs 479157890 # Total number of references to valid blocks. 92111502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.sampled_refs 4799666 # Sample count of references to valid blocks. 92211502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.avg_refs 99.831507 # Average number of references to valid blocks. 92310585SN/Asystem.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit. 92411502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 496.426080 # Average occupied blocks per requestor 92511502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.969582 # Average percentage of cache occupancy 92611502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.969582 # Average percentage of cache occupancy 92710585SN/Asystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 92811502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 92911502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id 93011502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 147 # Occupied blocks per task id 93110585SN/Asystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 93211502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.tag_accesses 972714778 # Number of tag accesses 93311502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.data_accesses 972714778 # Number of data accesses 93411502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 479157890 # number of ReadReq hits 93511502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_hits::total 479157890 # number of ReadReq hits 93611502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 479157890 # number of demand (read+write) hits 93711502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_hits::total 479157890 # number of demand (read+write) hits 93811502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 479157890 # number of overall hits 93911502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_hits::total 479157890 # number of overall hits 94011502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 4799666 # number of ReadReq misses 94111502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_misses::total 4799666 # number of ReadReq misses 94211502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 4799666 # number of demand (read+write) misses 94311502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_misses::total 4799666 # number of demand (read+write) misses 94411502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 4799666 # number of overall misses 94511502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_misses::total 4799666 # number of overall misses 94611502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 483957556 # number of ReadReq accesses(hits+misses) 94711502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_accesses::total 483957556 # number of ReadReq accesses(hits+misses) 94811502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 483957556 # number of demand (read+write) accesses 94911502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_accesses::total 483957556 # number of demand (read+write) accesses 95011502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 483957556 # number of overall (read+write) accesses 95111502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_accesses::total 483957556 # number of overall (read+write) accesses 95211502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009918 # miss rate for ReadReq accesses 95311502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.009918 # miss rate for ReadReq accesses 95411502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.009918 # miss rate for demand accesses 95511502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.009918 # miss rate for demand accesses 95611502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.009918 # miss rate for overall accesses 95711502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.009918 # miss rate for overall accesses 95810585SN/Asystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 95910585SN/Asystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 96010585SN/Asystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 96110585SN/Asystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 96210585SN/Asystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 96310585SN/Asystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 96411502SCurtis.Dunham@arm.comsystem.cpu1.icache.writebacks::writebacks 4799154 # number of writebacks 96511502SCurtis.Dunham@arm.comsystem.cpu1.icache.writebacks::total 4799154 # number of writebacks 96610628SN/Asystem.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 96710628SN/Asystem.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 96810628SN/Asystem.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 96910628SN/Asystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 97010628SN/Asystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 97110628SN/Asystem.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 97211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.replacements 2283161 # number of replacements 97311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.tagsinuse 13345.955021 # Cycle average of tags in use 97411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.total_refs 14389871 # Total number of references to valid blocks. 97511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.sampled_refs 2299207 # Sample count of references to valid blocks. 97611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.avg_refs 6.258624 # Average number of references to valid blocks. 97711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 10262240501000 # Cycle when the warmup percentage was hit. 97811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 13228.741418 # Average occupied blocks per requestor 97911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 51.265537 # Average occupied blocks per requestor 98011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 65.948066 # Average occupied blocks per requestor 98111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.807418 # Average percentage of cache occupancy 98211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003129 # Average percentage of cache occupancy 98311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004025 # Average percentage of cache occupancy 98411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.814572 # Average percentage of cache occupancy 98511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 89 # Occupied blocks per task id 98611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 15957 # Occupied blocks per task id 98711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 98811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 53 # Occupied blocks per task id 98911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 15 # Occupied blocks per task id 99011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id 99111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 211 # Occupied blocks per task id 99211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1511 # Occupied blocks per task id 99311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6067 # Occupied blocks per task id 99411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4384 # Occupied blocks per task id 99511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3784 # Occupied blocks per task id 99611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005432 # Percentage of cache occupancy per task id 99711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.973938 # Percentage of cache occupancy per task id 99811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.tag_accesses 365657601 # Number of tag accesses 99911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.data_accesses 365657601 # Number of data accesses 100011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 347777 # number of ReadReq hits 100111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155733 # number of ReadReq hits 100211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 503510 # number of ReadReq hits 100311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::writebacks 4070389 # number of WritebackDirty hits 100411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::total 4070389 # number of WritebackDirty hits 100511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_hits::writebacks 6732353 # number of WritebackClean hits 100611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_hits::total 6732353 # number of WritebackClean hits 100711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1054 # number of UpgradeReq hits 100811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::total 1054 # number of UpgradeReq hits 100911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 615614 # number of ReadExReq hits 101011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 615614 # number of ReadExReq hits 101111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4333068 # number of ReadCleanReq hits 101211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 4333068 # number of ReadCleanReq hits 101311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3106952 # number of ReadSharedReq hits 101411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 3106952 # number of ReadSharedReq hits 101511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::cpu1.data 166128 # number of InvalidateReq hits 101611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::total 166128 # number of InvalidateReq hits 101711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 347777 # number of demand (read+write) hits 101811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 155733 # number of demand (read+write) hits 101911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 4333068 # number of demand (read+write) hits 102011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 3722566 # number of demand (read+write) hits 102111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::total 8559144 # number of demand (read+write) hits 102211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 347777 # number of overall hits 102311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 155733 # number of overall hits 102411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 4333068 # number of overall hits 102511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 3722566 # number of overall hits 102611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::total 8559144 # number of overall hits 102711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12333 # number of ReadReq misses 102811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9620 # number of ReadReq misses 102911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 21953 # number of ReadReq misses 103011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 143903 # number of UpgradeReq misses 103111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 143903 # number of UpgradeReq misses 103211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 157576 # number of SCUpgradeReq misses 103311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 157576 # number of SCUpgradeReq misses 103411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 709038 # number of ReadExReq misses 103511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 709038 # number of ReadExReq misses 103611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 466598 # number of ReadCleanReq misses 103711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 466598 # number of ReadCleanReq misses 103811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1225336 # number of ReadSharedReq misses 103911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 1225336 # number of ReadSharedReq misses 104011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::cpu1.data 272085 # number of InvalidateReq misses 104111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::total 272085 # number of InvalidateReq misses 104211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12333 # number of demand (read+write) misses 104311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 9620 # number of demand (read+write) misses 104411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 466598 # number of demand (read+write) misses 104511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 1934374 # number of demand (read+write) misses 104611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::total 2422925 # number of demand (read+write) misses 104711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12333 # number of overall misses 104811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 9620 # number of overall misses 104911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 466598 # number of overall misses 105011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 1934374 # number of overall misses 105111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::total 2422925 # number of overall misses 105211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 360110 # number of ReadReq accesses(hits+misses) 105311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 165353 # number of ReadReq accesses(hits+misses) 105411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 525463 # number of ReadReq accesses(hits+misses) 105511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::writebacks 4070389 # number of WritebackDirty accesses(hits+misses) 105611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::total 4070389 # number of WritebackDirty accesses(hits+misses) 105711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::writebacks 6732353 # number of WritebackClean accesses(hits+misses) 105811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::total 6732353 # number of WritebackClean accesses(hits+misses) 105911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 144957 # number of UpgradeReq accesses(hits+misses) 106011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 144957 # number of UpgradeReq accesses(hits+misses) 106111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 157576 # number of SCUpgradeReq accesses(hits+misses) 106211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 157576 # number of SCUpgradeReq accesses(hits+misses) 106311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1324652 # number of ReadExReq accesses(hits+misses) 106411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 1324652 # number of ReadExReq accesses(hits+misses) 106511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4799666 # number of ReadCleanReq accesses(hits+misses) 106611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 4799666 # number of ReadCleanReq accesses(hits+misses) 106711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4332288 # number of ReadSharedReq accesses(hits+misses) 106811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 4332288 # number of ReadSharedReq accesses(hits+misses) 106911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 438213 # number of InvalidateReq accesses(hits+misses) 107011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::total 438213 # number of InvalidateReq accesses(hits+misses) 107111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 360110 # number of demand (read+write) accesses 107211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 165353 # number of demand (read+write) accesses 107311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 4799666 # number of demand (read+write) accesses 107411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 5656940 # number of demand (read+write) accesses 107511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::total 10982069 # number of demand (read+write) accesses 107611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 360110 # number of overall (read+write) accesses 107711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 165353 # number of overall (read+write) accesses 107811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 4799666 # number of overall (read+write) accesses 107911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 5656940 # number of overall (read+write) accesses 108011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::total 10982069 # number of overall (read+write) accesses 108111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.034248 # miss rate for ReadReq accesses 108211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.058179 # miss rate for ReadReq accesses 108311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.041778 # miss rate for ReadReq accesses 108411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.992729 # miss rate for UpgradeReq accesses 108511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 0.992729 # miss rate for UpgradeReq accesses 108610585SN/Asystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 108710585SN/Asystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 108811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.535264 # miss rate for ReadExReq accesses 108911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.535264 # miss rate for ReadExReq accesses 109011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.097215 # miss rate for ReadCleanReq accesses 109111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.097215 # miss rate for ReadCleanReq accesses 109211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.282838 # miss rate for ReadSharedReq accesses 109311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.282838 # miss rate for ReadSharedReq accesses 109411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.620897 # miss rate for InvalidateReq accesses 109511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::total 0.620897 # miss rate for InvalidateReq accesses 109611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.034248 # miss rate for demand accesses 109711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.058179 # miss rate for demand accesses 109811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.097215 # miss rate for demand accesses 109911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.341947 # miss rate for demand accesses 110011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.220626 # miss rate for demand accesses 110111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.034248 # miss rate for overall accesses 110211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.058179 # miss rate for overall accesses 110311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.097215 # miss rate for overall accesses 110411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.341947 # miss rate for overall accesses 110511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.220626 # miss rate for overall accesses 110610585SN/Asystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 110710585SN/Asystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 110810585SN/Asystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 110910585SN/Asystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 111010585SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 111110585SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 111211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.writebacks::writebacks 1211269 # number of writebacks 111311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.writebacks::total 1211269 # number of writebacks 111411502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_requests 22276444 # Total number of requests made to the snoop filter. 111511502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_requests 11381625 # Number of requests hitting in the snoop filter with a single holder of the requested data. 111611502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_requests 378 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 111711502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_snoops 1756231 # Total number of snoops made to the snoop filter. 111811502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1756065 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 111911502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 166 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 112011502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 608590 # Transaction distribution 112111502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 9740544 # Transaction distribution 112211502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 5562 # Transaction distribution 112311502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 5562 # Transaction distribution 112411502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackDirty 4070389 # Transaction distribution 112511502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackClean 6732731 # Transaction distribution 112611502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 144957 # Transaction distribution 112711502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 157576 # Transaction distribution 112811502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 302533 # Transaction distribution 112911502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 1324652 # Transaction distribution 113011502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 1324652 # Transaction distribution 113111502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 4799666 # Transaction distribution 113211502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 4332288 # Transaction distribution 113311502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateReq 438213 # Transaction distribution 113411502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateResp 438213 # Transaction distribution 113511502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14398746 # Packet count per connected master and slave (bytes) 113611502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18822028 # Packet count per connected master and slave (bytes) 113711502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 368476 # Packet count per connected master and slave (bytes) 113811502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 836878 # Packet count per connected master and slave (bytes) 113911502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count::total 34426128 # Packet count per connected master and slave (bytes) 114011502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 614325000 # Cumulative packet size per connected master and slave (bytes) 114111502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 746331191 # Cumulative packet size per connected master and slave (bytes) 114211502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1473904 # Cumulative packet size per connected master and slave (bytes) 114311502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3347512 # Cumulative packet size per connected master and slave (bytes) 114411502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size::total 1365477607 # Cumulative packet size per connected master and slave (bytes) 114511502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoops 5687998 # Total snoops (count) 114611502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 28144557 # Request fanout histogram 114711502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 0.072239 # Request fanout histogram 114811502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.258905 # Request fanout histogram 114910585SN/Asystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 115011502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 26111598 92.78% 92.78% # Request fanout histogram 115111502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 2032793 7.22% 100.00% # Request fanout histogram 115211502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 166 0.00% 100.00% # Request fanout histogram 115310585SN/Asystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 115411138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 115510827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 115611502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 28144557 # Request fanout histogram 115711502SCurtis.Dunham@arm.comsystem.iobus.trans_dist::ReadReq 40301 # Transaction distribution 115811502SCurtis.Dunham@arm.comsystem.iobus.trans_dist::ReadResp 40301 # Transaction distribution 115911336Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 136636 # Transaction distribution 116011336Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 136636 # Transaction distribution 116111502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47642 # Packet count per connected master and slave (bytes) 116210585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 116311245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 116410585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 116510585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 116610585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 116710585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 116810585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 116910585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 117010585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 117110585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 117210585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 117310585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 117411502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122576 # Packet count per connected master and slave (bytes) 117511502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231218 # Packet count per connected master and slave (bytes) 117611502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231218 # Packet count per connected master and slave (bytes) 117710585SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 117810585SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 117911502SCurtis.Dunham@arm.comsystem.iobus.pkt_count::total 353874 # Packet count per connected master and slave (bytes) 118011502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47662 # Cumulative packet size per connected master and slave (bytes) 118110585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 118211245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 118310585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 118410585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 118510585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 118610585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 118710585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 118810585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 118910585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 119010585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 119110585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 119210585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 119311502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::total 155683 # Cumulative packet size per connected master and slave (bytes) 119411502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338888 # Cumulative packet size per connected master and slave (bytes) 119511502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7338888 # Cumulative packet size per connected master and slave (bytes) 119610585SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 119710585SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 119811502SCurtis.Dunham@arm.comsystem.iobus.pkt_size::total 7496657 # Cumulative packet size per connected master and slave (bytes) 119911502SCurtis.Dunham@arm.comsystem.iocache.tags.replacements 115590 # number of replacements 120011502SCurtis.Dunham@arm.comsystem.iocache.tags.tagsinuse 11.289214 # Cycle average of tags in use 120110585SN/Asystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 120211502SCurtis.Dunham@arm.comsystem.iocache.tags.sampled_refs 115606 # Sample count of references to valid blocks. 120310585SN/Asystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 120411502SCurtis.Dunham@arm.comsystem.iocache.tags.warmup_cycle 9107775784009 # Cycle when the warmup percentage was hit. 120511502SCurtis.Dunham@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 3.856196 # Average occupied blocks per requestor 120611502SCurtis.Dunham@arm.comsystem.iocache.tags.occ_blocks::realview.ide 7.433018 # Average occupied blocks per requestor 120711502SCurtis.Dunham@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.241012 # Average percentage of cache occupancy 120811502SCurtis.Dunham@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.464564 # Average percentage of cache occupancy 120911502SCurtis.Dunham@arm.comsystem.iocache.tags.occ_percent::total 0.705576 # Average percentage of cache occupancy 121010585SN/Asystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 121110585SN/Asystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 121210585SN/Asystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 121311502SCurtis.Dunham@arm.comsystem.iocache.tags.tag_accesses 1040838 # Number of tag accesses 121411502SCurtis.Dunham@arm.comsystem.iocache.tags.data_accesses 1040838 # Number of data accesses 121510585SN/Asystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 121611502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_misses::realview.ide 8881 # number of ReadReq misses 121711502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_misses::total 8918 # number of ReadReq misses 121810585SN/Asystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 121910585SN/Asystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 122010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 122110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 122210585SN/Asystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 122311502SCurtis.Dunham@arm.comsystem.iocache.demand_misses::realview.ide 115609 # number of demand (read+write) misses 122411502SCurtis.Dunham@arm.comsystem.iocache.demand_misses::total 115649 # number of demand (read+write) misses 122510585SN/Asystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 122611502SCurtis.Dunham@arm.comsystem.iocache.overall_misses::realview.ide 115609 # number of overall misses 122711502SCurtis.Dunham@arm.comsystem.iocache.overall_misses::total 115649 # number of overall misses 122810585SN/Asystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 122911502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8881 # number of ReadReq accesses(hits+misses) 123011502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_accesses::total 8918 # number of ReadReq accesses(hits+misses) 123110585SN/Asystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 123210585SN/Asystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 123310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 123410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 123510585SN/Asystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 123611502SCurtis.Dunham@arm.comsystem.iocache.demand_accesses::realview.ide 115609 # number of demand (read+write) accesses 123711502SCurtis.Dunham@arm.comsystem.iocache.demand_accesses::total 115649 # number of demand (read+write) accesses 123810585SN/Asystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 123911502SCurtis.Dunham@arm.comsystem.iocache.overall_accesses::realview.ide 115609 # number of overall (read+write) accesses 124011502SCurtis.Dunham@arm.comsystem.iocache.overall_accesses::total 115649 # number of overall (read+write) accesses 124110585SN/Asystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 124210585SN/Asystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 124310585SN/Asystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 124410585SN/Asystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 124510585SN/Asystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 124610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 124710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 124810585SN/Asystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 124910585SN/Asystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 125010585SN/Asystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 125110585SN/Asystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 125210585SN/Asystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 125310585SN/Asystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 125410585SN/Asystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 125510585SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 125610585SN/Asystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 125710585SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 125810585SN/Asystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 125910585SN/Asystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 126010585SN/Asystem.iocache.writebacks::writebacks 106694 # number of writebacks 126110585SN/Asystem.iocache.writebacks::total 106694 # number of writebacks 126211502SCurtis.Dunham@arm.comsystem.l2c.tags.replacements 1772279 # number of replacements 126311502SCurtis.Dunham@arm.comsystem.l2c.tags.tagsinuse 63191.056766 # Cycle average of tags in use 126411502SCurtis.Dunham@arm.comsystem.l2c.tags.total_refs 4630026 # Total number of references to valid blocks. 126511502SCurtis.Dunham@arm.comsystem.l2c.tags.sampled_refs 1831889 # Sample count of references to valid blocks. 126611502SCurtis.Dunham@arm.comsystem.l2c.tags.avg_refs 2.527460 # Average number of references to valid blocks. 126711353Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 514828500 # Cycle when the warmup percentage was hit. 126811502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::writebacks 34852.259954 # Average occupied blocks per requestor 126911502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 35.728290 # Average occupied blocks per requestor 127011502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 43.277467 # Average occupied blocks per requestor 127111502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 3264.617227 # Average occupied blocks per requestor 127211502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 6940.607740 # Average occupied blocks per requestor 127311502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 274.307726 # Average occupied blocks per requestor 127411502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 426.439632 # Average occupied blocks per requestor 127511502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 2871.138387 # Average occupied blocks per requestor 127611502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 14482.680343 # Average occupied blocks per requestor 127711502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::writebacks 0.531803 # Average percentage of cache occupancy 127811502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.000545 # Average percentage of cache occupancy 127911502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.000660 # Average percentage of cache occupancy 128011502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.049814 # Average percentage of cache occupancy 128111502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.105905 # Average percentage of cache occupancy 128211502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.004186 # Average percentage of cache occupancy 128311502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.006507 # Average percentage of cache occupancy 128411502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.043810 # Average percentage of cache occupancy 128511502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.220988 # Average percentage of cache occupancy 128611502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::total 0.964219 # Average percentage of cache occupancy 128711502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 206 # Occupied blocks per task id 128811502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 59404 # Occupied blocks per task id 128911502SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id 129011502SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 204 # Occupied blocks per task id 129111502SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id 129211502SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 483 # Occupied blocks per task id 129311502SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 3390 # Occupied blocks per task id 129411502SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 5782 # Occupied blocks per task id 129511502SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 49679 # Occupied blocks per task id 129611502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.003143 # Percentage of cache occupancy per task id 129711502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.906433 # Percentage of cache occupancy per task id 129811502SCurtis.Dunham@arm.comsystem.l2c.tags.tag_accesses 73419992 # Number of tag accesses 129911502SCurtis.Dunham@arm.comsystem.l2c.tags.data_accesses 73419992 # Number of data accesses 130011502SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_hits::writebacks 2765418 # number of WritebackDirty hits 130111502SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_hits::total 2765418 # number of WritebackDirty hits 130211502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 17779 # number of UpgradeReq hits 130311502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 15575 # number of UpgradeReq hits 130411502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::total 33354 # number of UpgradeReq hits 130511502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 2588 # number of SCUpgradeReq hits 130611502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 2404 # number of SCUpgradeReq hits 130711502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_hits::total 4992 # number of SCUpgradeReq hits 130811502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 200286 # number of ReadExReq hits 130911502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 176214 # number of ReadExReq hits 131011502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_hits::total 376500 # number of ReadExReq hits 131111502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6410 # number of ReadSharedReq hits 131211502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 4846 # number of ReadSharedReq hits 131311502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 439050 # number of ReadSharedReq hits 131411502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 727042 # number of ReadSharedReq hits 131511502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5703 # number of ReadSharedReq hits 131611502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 3689 # number of ReadSharedReq hits 131711502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 424901 # number of ReadSharedReq hits 131811502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 685160 # number of ReadSharedReq hits 131911502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::total 2296801 # number of ReadSharedReq hits 132011502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_hits::cpu0.data 115689 # number of InvalidateReq hits 132111502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_hits::cpu1.data 102800 # number of InvalidateReq hits 132211502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_hits::total 218489 # number of InvalidateReq hits 132311502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 6410 # number of demand (read+write) hits 132411502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 4846 # number of demand (read+write) hits 132511502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.inst 439050 # number of demand (read+write) hits 132611502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.data 927328 # number of demand (read+write) hits 132711502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 5703 # number of demand (read+write) hits 132811502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 3689 # number of demand (read+write) hits 132911502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.inst 424901 # number of demand (read+write) hits 133011502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.data 861374 # number of demand (read+write) hits 133111502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::total 2673301 # number of demand (read+write) hits 133211502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 6410 # number of overall hits 133311502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 4846 # number of overall hits 133411502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.inst 439050 # number of overall hits 133511502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.data 927328 # number of overall hits 133611502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 5703 # number of overall hits 133711502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 3689 # number of overall hits 133811502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.inst 424901 # number of overall hits 133911502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.data 861374 # number of overall hits 134011502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::total 2673301 # number of overall hits 134111502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 64906 # number of UpgradeReq misses 134211502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 60031 # number of UpgradeReq misses 134311502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::total 124937 # number of UpgradeReq misses 134411502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 6479 # number of SCUpgradeReq misses 134511502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 6386 # number of SCUpgradeReq misses 134611502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_misses::total 12865 # number of SCUpgradeReq misses 134711502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 376689 # number of ReadExReq misses 134811502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 423433 # number of ReadExReq misses 134911502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::total 800122 # number of ReadExReq misses 135011502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2349 # number of ReadSharedReq misses 135111502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 1944 # number of ReadSharedReq misses 135211502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 58179 # number of ReadSharedReq misses 135311502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 178934 # number of ReadSharedReq misses 135411502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3469 # number of ReadSharedReq misses 135511502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.itb.walker 3479 # number of ReadSharedReq misses 135611502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 41697 # number of ReadSharedReq misses 135711502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 188396 # number of ReadSharedReq misses 135811502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::total 478447 # number of ReadSharedReq misses 135911502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_misses::cpu0.data 477304 # number of InvalidateReq misses 136011502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_misses::cpu1.data 163191 # number of InvalidateReq misses 136111502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_misses::total 640495 # number of InvalidateReq misses 136211502SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 2349 # number of demand (read+write) misses 136311502SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 1944 # number of demand (read+write) misses 136411502SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.inst 58179 # number of demand (read+write) misses 136511502SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.data 555623 # number of demand (read+write) misses 136611502SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 3469 # number of demand (read+write) misses 136711502SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.itb.walker 3479 # number of demand (read+write) misses 136811502SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.inst 41697 # number of demand (read+write) misses 136911502SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.data 611829 # number of demand (read+write) misses 137011502SCurtis.Dunham@arm.comsystem.l2c.demand_misses::total 1278569 # number of demand (read+write) misses 137111502SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 2349 # number of overall misses 137211502SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 1944 # number of overall misses 137311502SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.inst 58179 # number of overall misses 137411502SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.data 555623 # number of overall misses 137511502SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 3469 # number of overall misses 137611502SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.itb.walker 3479 # number of overall misses 137711502SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.inst 41697 # number of overall misses 137811502SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.data 611829 # number of overall misses 137911502SCurtis.Dunham@arm.comsystem.l2c.overall_misses::total 1278569 # number of overall misses 138011502SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 2765418 # number of WritebackDirty accesses(hits+misses) 138111502SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_accesses::total 2765418 # number of WritebackDirty accesses(hits+misses) 138211502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 82685 # number of UpgradeReq accesses(hits+misses) 138311502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 75606 # number of UpgradeReq accesses(hits+misses) 138411502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::total 158291 # number of UpgradeReq accesses(hits+misses) 138511502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 9067 # number of SCUpgradeReq accesses(hits+misses) 138611502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 8790 # number of SCUpgradeReq accesses(hits+misses) 138711502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_accesses::total 17857 # number of SCUpgradeReq accesses(hits+misses) 138811502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 576975 # number of ReadExReq accesses(hits+misses) 138911502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 599647 # number of ReadExReq accesses(hits+misses) 139011502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::total 1176622 # number of ReadExReq accesses(hits+misses) 139111502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8759 # number of ReadSharedReq accesses(hits+misses) 139211502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6790 # number of ReadSharedReq accesses(hits+misses) 139311502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 497229 # number of ReadSharedReq accesses(hits+misses) 139411502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 905976 # number of ReadSharedReq accesses(hits+misses) 139511502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 9172 # number of ReadSharedReq accesses(hits+misses) 139611502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7168 # number of ReadSharedReq accesses(hits+misses) 139711502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 466598 # number of ReadSharedReq accesses(hits+misses) 139811502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 873556 # number of ReadSharedReq accesses(hits+misses) 139911502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::total 2775248 # number of ReadSharedReq accesses(hits+misses) 140011502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_accesses::cpu0.data 592993 # number of InvalidateReq accesses(hits+misses) 140111502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_accesses::cpu1.data 265991 # number of InvalidateReq accesses(hits+misses) 140211502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_accesses::total 858984 # number of InvalidateReq accesses(hits+misses) 140311502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 8759 # number of demand (read+write) accesses 140411502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 6790 # number of demand (read+write) accesses 140511502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.inst 497229 # number of demand (read+write) accesses 140611502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.data 1482951 # number of demand (read+write) accesses 140711502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 9172 # number of demand (read+write) accesses 140811502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 7168 # number of demand (read+write) accesses 140911502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.inst 466598 # number of demand (read+write) accesses 141011502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.data 1473203 # number of demand (read+write) accesses 141111502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::total 3951870 # number of demand (read+write) accesses 141211502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 8759 # number of overall (read+write) accesses 141311502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 6790 # number of overall (read+write) accesses 141411502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.inst 497229 # number of overall (read+write) accesses 141511502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.data 1482951 # number of overall (read+write) accesses 141611502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 9172 # number of overall (read+write) accesses 141711502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 7168 # number of overall (read+write) accesses 141811502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.inst 466598 # number of overall (read+write) accesses 141911502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.data 1473203 # number of overall (read+write) accesses 142011502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::total 3951870 # number of overall (read+write) accesses 142111502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.784979 # miss rate for UpgradeReq accesses 142211502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.793998 # miss rate for UpgradeReq accesses 142311502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.789287 # miss rate for UpgradeReq accesses 142411502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.714569 # miss rate for SCUpgradeReq accesses 142511502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.726507 # miss rate for SCUpgradeReq accesses 142611502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.720446 # miss rate for SCUpgradeReq accesses 142711502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.652869 # miss rate for ReadExReq accesses 142811502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.706137 # miss rate for ReadExReq accesses 142911502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.680016 # miss rate for ReadExReq accesses 143011502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.268181 # miss rate for ReadSharedReq accesses 143111502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.286303 # miss rate for ReadSharedReq accesses 143211502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.117006 # miss rate for ReadSharedReq accesses 143311502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.197504 # miss rate for ReadSharedReq accesses 143411502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.378216 # miss rate for ReadSharedReq accesses 143511502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.485352 # miss rate for ReadSharedReq accesses 143611502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.089364 # miss rate for ReadSharedReq accesses 143711502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.215666 # miss rate for ReadSharedReq accesses 143811502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.172398 # miss rate for ReadSharedReq accesses 143911502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu0.data 0.804907 # miss rate for InvalidateReq accesses 144011502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu1.data 0.613521 # miss rate for InvalidateReq accesses 144111502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_rate::total 0.745643 # miss rate for InvalidateReq accesses 144211502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.268181 # miss rate for demand accesses 144311502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.286303 # miss rate for demand accesses 144411502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.117006 # miss rate for demand accesses 144511502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.374674 # miss rate for demand accesses 144611502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.378216 # miss rate for demand accesses 144711502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.485352 # miss rate for demand accesses 144811502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.089364 # miss rate for demand accesses 144911502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.415305 # miss rate for demand accesses 145011502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::total 0.323535 # miss rate for demand accesses 145111502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.268181 # miss rate for overall accesses 145211502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.286303 # miss rate for overall accesses 145311502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.117006 # miss rate for overall accesses 145411502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.374674 # miss rate for overall accesses 145511502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.378216 # miss rate for overall accesses 145611502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.485352 # miss rate for overall accesses 145711502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.089364 # miss rate for overall accesses 145811502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.415305 # miss rate for overall accesses 145911502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::total 0.323535 # miss rate for overall accesses 146010515SN/Asystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 146110515SN/Asystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 146210515SN/Asystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 146310515SN/Asystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 146410515SN/Asystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 146510515SN/Asystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 146611502SCurtis.Dunham@arm.comsystem.l2c.writebacks::writebacks 1477304 # number of writebacks 146711502SCurtis.Dunham@arm.comsystem.l2c.writebacks::total 1477304 # number of writebacks 146811502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_requests 4491425 # Total number of requests made to the snoop filter. 146911502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_requests 2595543 # Number of requests hitting in the snoop filter with a single holder of the requested data. 147011502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_requests 3224 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 147111502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 147211502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 147311502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 147411502SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadReq 82119 # Transaction distribution 147511502SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 569484 # Transaction distribution 147611502SCurtis.Dunham@arm.comsystem.membus.trans_dist::WriteReq 38800 # Transaction distribution 147711502SCurtis.Dunham@arm.comsystem.membus.trans_dist::WriteResp 38800 # Transaction distribution 147811502SCurtis.Dunham@arm.comsystem.membus.trans_dist::WritebackDirty 1583998 # Transaction distribution 147911502SCurtis.Dunham@arm.comsystem.membus.trans_dist::CleanEvict 246737 # Transaction distribution 148011502SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeReq 335468 # Transaction distribution 148111502SCurtis.Dunham@arm.comsystem.membus.trans_dist::SCUpgradeReq 307268 # Transaction distribution 148211502SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeResp 157952 # Transaction distribution 148311502SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExReq 787861 # Transaction distribution 148411502SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExResp 784470 # Transaction distribution 148511502SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 487365 # Transaction distribution 148611502SCurtis.Dunham@arm.comsystem.membus.trans_dist::InvalidateReq 742728 # Transaction distribution 148711502SCurtis.Dunham@arm.comsystem.membus.trans_dist::InvalidateResp 742728 # Transaction distribution 148811502SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122576 # Packet count per connected master and slave (bytes) 148910585SN/Asystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 149011502SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27524 # Packet count per connected master and slave (bytes) 149111502SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6408698 # Packet count per connected master and slave (bytes) 149211502SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 6558890 # Packet count per connected master and slave (bytes) 149311502SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346888 # Packet count per connected master and slave (bytes) 149411502SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 346888 # Packet count per connected master and slave (bytes) 149511502SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 6905778 # Packet count per connected master and slave (bytes) 149611502SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155683 # Cumulative packet size per connected master and slave (bytes) 149710585SN/Asystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 149811502SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55048 # Cumulative packet size per connected master and slave (bytes) 149911502SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 175567900 # Cumulative packet size per connected master and slave (bytes) 150011502SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 175778835 # Cumulative packet size per connected master and slave (bytes) 150111502SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7399168 # Cumulative packet size per connected master and slave (bytes) 150211502SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7399168 # Cumulative packet size per connected master and slave (bytes) 150311502SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 183178003 # Cumulative packet size per connected master and slave (bytes) 150410585SN/Asystem.membus.snoops 0 # Total snoops (count) 150511502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 4612344 # Request fanout histogram 150611502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0.007156 # Request fanout histogram 150711502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0.084293 # Request fanout histogram 150810585SN/Asystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 150911502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 4579336 99.28% 99.28% # Request fanout histogram 151011502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 33008 0.72% 100.00% # Request fanout histogram 151110585SN/Asystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 151210585SN/Asystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 151311502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 151410585SN/Asystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 151511502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 4612344 # Request fanout histogram 151611239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 151711239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 151811239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 151911239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 152011239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 152111239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 152210515SN/Asystem.realview.ethernet.txBytes 966 # Bytes Transmitted 152310515SN/Asystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 152410515SN/Asystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 152510515SN/Asystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 152610515SN/Asystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 152710515SN/Asystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 152810515SN/Asystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 152910515SN/Asystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 153010515SN/Asystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 153110515SN/Asystem.realview.ethernet.totBandwidth 164 # Total Bandwidth (bits/s) 153210515SN/Asystem.realview.ethernet.totPackets 3 # Total Packets 153310515SN/Asystem.realview.ethernet.totBytes 966 # Total Bytes 153410515SN/Asystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 153510515SN/Asystem.realview.ethernet.txBandwidth 164 # Transmit Bandwidth (bits/s) 153610515SN/Asystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 153710515SN/Asystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 153810515SN/Asystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 153910515SN/Asystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 154010515SN/Asystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 154110515SN/Asystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 154210515SN/Asystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 154310515SN/Asystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 154410515SN/Asystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 154510515SN/Asystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 154610515SN/Asystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 154710515SN/Asystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 154810515SN/Asystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 154910515SN/Asystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 155010515SN/Asystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 155110515SN/Asystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 155210515SN/Asystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 155310515SN/Asystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 155410515SN/Asystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 155510515SN/Asystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 155610515SN/Asystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 155710515SN/Asystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 155810515SN/Asystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 155910515SN/Asystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 156010515SN/Asystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 156110515SN/Asystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 156210515SN/Asystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 156310515SN/Asystem.realview.ethernet.droppedPackets 0 # number of packets dropped 156411239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 156511239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 156611239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 156711239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 156811502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.tot_requests 11113814 # Total number of requests made to the snoop filter. 156911502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 5721773 # Number of requests hitting in the snoop filter with a single holder of the requested data. 157011502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 1636305 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 157111502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 133991 # Total number of snoops made to the snoop filter. 157211502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 120343 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 157311502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 13648 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 157411502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadReq 82121 # Transaction distribution 157511502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadResp 3542094 # Transaction distribution 157611502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WriteReq 38800 # Transaction distribution 157711502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WriteResp 38800 # Transaction distribution 157811502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 2765418 # Transaction distribution 157911502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::CleanEvict 2011530 # Transaction distribution 158011502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 348672 # Transaction distribution 158111502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 312260 # Transaction distribution 158211502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 660932 # Transaction distribution 158311502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadExReq 1356975 # Transaction distribution 158411502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadExResp 1356975 # Transaction distribution 158511502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 3459973 # Transaction distribution 158611502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::InvalidateReq 858984 # Transaction distribution 158711502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::InvalidateResp 858984 # Transaction distribution 158811502SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9470177 # Packet count per connected master and slave (bytes) 158911502SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8222341 # Packet count per connected master and slave (bytes) 159011502SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count::total 17692518 # Packet count per connected master and slave (bytes) 159111502SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 254644772 # Cumulative packet size per connected master and slave (bytes) 159211502SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 231031359 # Cumulative packet size per connected master and slave (bytes) 159311502SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size::total 485676131 # Cumulative packet size per connected master and slave (bytes) 159411502SCurtis.Dunham@arm.comsystem.toL2Bus.snoops 1806287 # Total snoops (count) 159511502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::samples 13039342 # Request fanout histogram 159611502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::mean 0.283997 # Request fanout histogram 159711502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.453251 # Request fanout histogram 159810515SN/Asystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 159911502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::0 9349855 71.70% 71.70% # Request fanout histogram 160011502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::1 3675839 28.19% 99.90% # Request fanout histogram 160111502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::2 13648 0.10% 100.00% # Request fanout histogram 160210515SN/Asystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 160311138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 160410515SN/Asystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 160511502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::total 13039342 # Request fanout histogram 160610515SN/A 160710515SN/A---------- End Simulation Statistics ---------- 1608