stats.txt revision 11353
110515SN/A 210515SN/A---------- Begin Simulation Statistics ---------- 311336Sandreas.hansson@arm.comsim_seconds 47.256536 # Number of seconds simulated 411336Sandreas.hansson@arm.comsim_ticks 47256535705500 # Number of ticks simulated 511336Sandreas.hansson@arm.comfinal_tick 47256535705500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711353Sandreas.hansson@arm.comhost_inst_rate 1671940 # Simulator instruction rate (inst/s) 811353Sandreas.hansson@arm.comhost_op_rate 1966949 # Simulator op (including micro ops) rate (op/s) 911353Sandreas.hansson@arm.comhost_tick_rate 80984002716 # Simulator tick rate (ticks/s) 1011353Sandreas.hansson@arm.comhost_mem_usage 693668 # Number of bytes of host memory used 1111353Sandreas.hansson@arm.comhost_seconds 583.53 # Real time elapsed on the host 1211336Sandreas.hansson@arm.comsim_insts 975625723 # Number of instructions simulated 1311336Sandreas.hansson@arm.comsim_ops 1147772483 # Number of ops (including micro ops) simulated 1410515SN/Asystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SN/Asystem.clk_domain.clock 1000 # Clock period in ticks 1611353Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 156864 # Number of bytes read from this memory 1711336Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 131392 # Number of bytes read from this memory 1811353Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 3883124 # Number of bytes read from this memory 1911353Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 35607176 # Number of bytes read from this memory 2011353Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 217792 # Number of bytes read from this memory 2111353Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.itb.walker 214080 # Number of bytes read from this memory 2211353Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 2613000 # Number of bytes read from this memory 2311353Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 38038064 # Number of bytes read from this memory 2411353Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 430464 # Number of bytes read from this memory 2511353Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 81291956 # Number of bytes read from this memory 2611353Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 3883124 # Number of instructions bytes read from this memory 2711353Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 2613000 # Number of instructions bytes read from this memory 2811353Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 6496124 # Number of instructions bytes read from this memory 2911353Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 101151552 # Number of bytes written to this memory 3010827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 3110585SN/Asystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3211353Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 101172136 # Number of bytes written to this memory 3311353Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 2451 # Number of read requests responded to by this memory 3411336Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.itb.walker 2053 # Number of read requests responded to by this memory 3511353Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 101081 # Number of read requests responded to by this memory 3611353Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 556375 # Number of read requests responded to by this memory 3711353Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 3403 # Number of read requests responded to by this memory 3811353Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.itb.walker 3345 # Number of read requests responded to by this memory 3911353Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 40935 # Number of read requests responded to by this memory 4011353Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 594361 # Number of read requests responded to by this memory 4111353Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 6726 # Number of read requests responded to by this memory 4211353Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1310730 # Number of read requests responded to by this memory 4311353Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 1580493 # Number of write requests responded to by this memory 4410827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 4510585SN/Asystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 4611353Sandreas.hansson@arm.comsystem.physmem.num_writes::total 1583067 # Number of write requests responded to by this memory 4711353Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 3319 # Total read bandwidth from this memory (bytes/s) 4811336Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.itb.walker 2780 # Total read bandwidth from this memory (bytes/s) 4911353Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 82171 # Total read bandwidth from this memory (bytes/s) 5011353Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 753487 # Total read bandwidth from this memory (bytes/s) 5111353Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 4609 # Total read bandwidth from this memory (bytes/s) 5211353Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.itb.walker 4530 # Total read bandwidth from this memory (bytes/s) 5311353Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 55294 # Total read bandwidth from this memory (bytes/s) 5411353Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 804927 # Total read bandwidth from this memory (bytes/s) 5511353Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 9109 # Total read bandwidth from this memory (bytes/s) 5611353Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1720227 # Total read bandwidth from this memory (bytes/s) 5711353Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 82171 # Instruction read bandwidth from this memory (bytes/s) 5811353Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 55294 # Instruction read bandwidth from this memory (bytes/s) 5911353Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 137465 # Instruction read bandwidth from this memory (bytes/s) 6011353Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 2140478 # Write bandwidth from this memory (bytes/s) 6111336Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) 6210585SN/Asystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 6311353Sandreas.hansson@arm.comsystem.physmem.bw_write::total 2140913 # Write bandwidth from this memory (bytes/s) 6411353Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 2140478 # Total bandwidth to/from this memory (bytes/s) 6511353Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 3319 # Total bandwidth to/from this memory (bytes/s) 6611336Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.itb.walker 2780 # Total bandwidth to/from this memory (bytes/s) 6711353Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 82171 # Total bandwidth to/from this memory (bytes/s) 6811353Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 753922 # Total bandwidth to/from this memory (bytes/s) 6911353Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 4609 # Total bandwidth to/from this memory (bytes/s) 7011353Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.itb.walker 4530 # Total bandwidth to/from this memory (bytes/s) 7111353Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 55294 # Total bandwidth to/from this memory (bytes/s) 7211353Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 804927 # Total bandwidth to/from this memory (bytes/s) 7311353Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 9109 # Total bandwidth to/from this memory (bytes/s) 7411353Sandreas.hansson@arm.comsystem.physmem.bw_total::total 3861140 # Total bandwidth to/from this memory (bytes/s) 7510515SN/Asystem.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 7610515SN/Asystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 7710515SN/Asystem.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 7810515SN/Asystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 7910515SN/Asystem.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 8010515SN/Asystem.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 8110515SN/Asystem.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 8210515SN/Asystem.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 8310515SN/Asystem.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 8410515SN/Asystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 8510515SN/Asystem.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 8610515SN/Asystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 8710515SN/Asystem.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 8810515SN/Asystem.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 8910515SN/Asystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 9010515SN/Asystem.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 9110515SN/Asystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 9210515SN/Asystem.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 9310515SN/Asystem.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 9410515SN/Asystem.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 9510515SN/Asystem.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 9610515SN/Asystem.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 9710515SN/Asystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 9810515SN/Asystem.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 9910515SN/Asystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 10010515SN/Asystem.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 10110585SN/Asystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 10210585SN/Asystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 10310585SN/Asystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 10410585SN/Asystem.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 10510585SN/Asystem.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 10610585SN/Asystem.cf0.dma_write_txs 1670 # Number of DMA write transactions. 10710515SN/Asystem.cpu_clk_domain.clock 500 # Clock period in ticks 10810628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 10910628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 11010628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 11110628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 11210628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 11310628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 11410628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 11510628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 11610585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 11710585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 11810585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 11910585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 12010585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 12110585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 12210585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 12310585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 12410585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 12510585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 12610585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 12710585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 12810585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 12910585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 13010585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 13110585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 13210585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 13310585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 13410585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 13510585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 13610585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 13711336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walks 124170 # Table walker walks requested 13811336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLong 124170 # Table walker walks initiated with long descriptors 13911336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 124170 # Table walker wait (enqueue to first request) latency 14011336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0 124170 100.00% 100.00% # Table walker wait (enqueue to first request) latency 14111336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 124170 # Table walker wait (enqueue to first request) latency 14210628SN/Asystem.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution 14310628SN/Asystem.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution 14410628SN/Asystem.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution 14511336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 95903 89.91% 89.91% # Table walker page sizes translated 14611336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::2M 10758 10.09% 100.00% # Table walker page sizes translated 14711336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 106661 # Table walker page sizes translated 14811336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 124170 # Table walker requests started/completed, data/inst 14910628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 15011336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 124170 # Table walker requests started/completed, data/inst 15111336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106661 # Table walker requests started/completed, data/inst 15210628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 15311336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106661 # Table walker requests started/completed, data/inst 15411336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 230831 # Table walker requests started/completed, data/inst 15510585SN/Asystem.cpu0.dtb.inst_hits 0 # ITB inst hits 15610585SN/Asystem.cpu0.dtb.inst_misses 0 # ITB inst misses 15711336Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 91996645 # DTB read hits 15811336Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 87944 # DTB read misses 15911336Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 85085804 # DTB write hits 16011336Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 36226 # DTB write misses 16110585SN/Asystem.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed 16210585SN/Asystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 16311336Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID 16410585SN/Asystem.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 16511336Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_entries 36305 # Number of entries that have been flushed from TLB 16610585SN/Asystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 16711336Sandreas.hansson@arm.comsystem.cpu0.dtb.prefetch_faults 5760 # Number of TLB faults due to prefetch 16810585SN/Asystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 16911336Sandreas.hansson@arm.comsystem.cpu0.dtb.perms_faults 10368 # Number of TLB faults due to permissions restrictions 17011336Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 92084589 # DTB read accesses 17111336Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 85122030 # DTB write accesses 17210585SN/Asystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 17311336Sandreas.hansson@arm.comsystem.cpu0.dtb.hits 177082449 # DTB hits 17411336Sandreas.hansson@arm.comsystem.cpu0.dtb.misses 124170 # DTB misses 17511336Sandreas.hansson@arm.comsystem.cpu0.dtb.accesses 177206619 # DTB accesses 17610628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 17710628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 17810628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 17910628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 18010628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 18110628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 18210628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 18310628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 18410585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 18510585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 18610585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 18710585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 18810585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 18910585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 19010585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 19110585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 19210585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 19310585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 19410585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 19510585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 19610585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 19710585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 19810585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 19910585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 20010585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 20110585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 20210585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 20310585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 20410585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 20511336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walks 60706 # Table walker walks requested 20611336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLong 60706 # Table walker walks initiated with long descriptors 20711336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 60706 # Table walker wait (enqueue to first request) latency 20811336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::0 60706 100.00% 100.00% # Table walker wait (enqueue to first request) latency 20911336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 60706 # Table walker wait (enqueue to first request) latency 21010628SN/Asystem.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution 21110628SN/Asystem.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution 21210628SN/Asystem.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution 21311336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 54677 98.81% 98.81% # Table walker page sizes translated 21411336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::2M 656 1.19% 100.00% # Table walker page sizes translated 21511336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 55333 # Table walker page sizes translated 21610628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 21711336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60706 # Table walker requests started/completed, data/inst 21811336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 60706 # Table walker requests started/completed, data/inst 21910628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 22011336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55333 # Table walker requests started/completed, data/inst 22111336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 55333 # Table walker requests started/completed, data/inst 22211336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 116039 # Table walker requests started/completed, data/inst 22311336Sandreas.hansson@arm.comsystem.cpu0.itb.inst_hits 494456191 # ITB inst hits 22411336Sandreas.hansson@arm.comsystem.cpu0.itb.inst_misses 60706 # ITB inst misses 22510585SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 22610585SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 22710585SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 22810585SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 22910585SN/Asystem.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed 23010585SN/Asystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 23111336Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID 23210585SN/Asystem.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 23311336Sandreas.hansson@arm.comsystem.cpu0.itb.flush_entries 25125 # Number of entries that have been flushed from TLB 23410585SN/Asystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 23510585SN/Asystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 23610585SN/Asystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 23710585SN/Asystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 23810585SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 23910585SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 24011336Sandreas.hansson@arm.comsystem.cpu0.itb.inst_accesses 494516897 # ITB inst accesses 24111336Sandreas.hansson@arm.comsystem.cpu0.itb.hits 494456191 # DTB hits 24211336Sandreas.hansson@arm.comsystem.cpu0.itb.misses 60706 # DTB misses 24311336Sandreas.hansson@arm.comsystem.cpu0.itb.accesses 494516897 # DTB accesses 24411336Sandreas.hansson@arm.comsystem.cpu0.numCycles 94513084765 # number of cpu cycles simulated 24510585SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 24610585SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 24711167Sjthestness@gmail.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 24811336Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 13353 # number of quiesce instructions executed 24911336Sandreas.hansson@arm.comsystem.cpu0.committedInsts 494222683 # Number of instructions committed 25011336Sandreas.hansson@arm.comsystem.cpu0.committedOps 581244792 # Number of ops (including micro ops) committed 25111336Sandreas.hansson@arm.comsystem.cpu0.num_int_alu_accesses 532690974 # Number of integer alu accesses 25211336Sandreas.hansson@arm.comsystem.cpu0.num_fp_alu_accesses 523276 # Number of float alu accesses 25311336Sandreas.hansson@arm.comsystem.cpu0.num_func_calls 28754621 # number of times a function call or return occured 25411336Sandreas.hansson@arm.comsystem.cpu0.num_conditional_control_insts 75975087 # number of instructions that are conditional controls 25511336Sandreas.hansson@arm.comsystem.cpu0.num_int_insts 532690974 # number of integer instructions 25611336Sandreas.hansson@arm.comsystem.cpu0.num_fp_insts 523276 # number of float instructions 25711336Sandreas.hansson@arm.comsystem.cpu0.num_int_register_reads 780604880 # number of times the integer registers were read 25811336Sandreas.hansson@arm.comsystem.cpu0.num_int_register_writes 422748329 # number of times the integer registers were written 25911336Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_reads 843639 # number of times the floating registers were read 26011336Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_writes 445096 # number of times the floating registers were written 26111336Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_reads 132982449 # number of times the CC registers were read 26211336Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_writes 132652363 # number of times the CC registers were written 26311336Sandreas.hansson@arm.comsystem.cpu0.num_mem_refs 177183712 # number of memory refs 26411336Sandreas.hansson@arm.comsystem.cpu0.num_load_insts 92070454 # Number of load instructions 26511336Sandreas.hansson@arm.comsystem.cpu0.num_store_insts 85113258 # Number of store instructions 26611336Sandreas.hansson@arm.comsystem.cpu0.num_idle_cycles 93931503589.334885 # Number of idle cycles 26711336Sandreas.hansson@arm.comsystem.cpu0.num_busy_cycles 581581175.665107 # Number of busy cycles 26811336Sandreas.hansson@arm.comsystem.cpu0.not_idle_fraction 0.006153 # Percentage of non-idle cycles 26911336Sandreas.hansson@arm.comsystem.cpu0.idle_fraction 0.993847 # Percentage of idle cycles 27011336Sandreas.hansson@arm.comsystem.cpu0.Branches 110567658 # Number of branches fetched 27110585SN/Asystem.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 27211336Sandreas.hansson@arm.comsystem.cpu0.op_class::IntAlu 403027649 69.30% 69.30% # Class of executed instruction 27311336Sandreas.hansson@arm.comsystem.cpu0.op_class::IntMult 1232673 0.21% 69.51% # Class of executed instruction 27411336Sandreas.hansson@arm.comsystem.cpu0.op_class::IntDiv 59610 0.01% 69.52% # Class of executed instruction 27511336Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction 27611336Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction 27711336Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction 27811336Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction 27911336Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction 28011336Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction 28111336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction 28211336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction 28311336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction 28411336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction 28511336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction 28611336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction 28711336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction 28811336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction 28911336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction 29011336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction 29111336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction 29211336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAdd 8 0.00% 69.52% # Class of executed instruction 29311336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction 29411336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCmp 13 0.00% 69.52% # Class of executed instruction 29511336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCvt 21 0.00% 69.52% # Class of executed instruction 29611336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction 29711336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMisc 73071 0.01% 69.53% # Class of executed instruction 29811336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 69.53% # Class of executed instruction 29911336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.53% # Class of executed instruction 30011336Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.53% # Class of executed instruction 30111336Sandreas.hansson@arm.comsystem.cpu0.op_class::MemRead 92070454 15.83% 85.37% # Class of executed instruction 30211336Sandreas.hansson@arm.comsystem.cpu0.op_class::MemWrite 85113258 14.63% 100.00% # Class of executed instruction 30310585SN/Asystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 30410585SN/Asystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 30511336Sandreas.hansson@arm.comsystem.cpu0.op_class::total 581576758 # Class of executed instruction 30611336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 6248192 # number of replacements 30711336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 500.818994 # Cycle average of tags in use 30811336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 170762721 # Total number of references to valid blocks. 30911336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 6248704 # Sample count of references to valid blocks. 31011336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 27.327702 # Average number of references to valid blocks. 31110827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. 31211336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 500.818994 # Average occupied blocks per requestor 31311336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.978162 # Average percentage of cache occupancy 31411336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.978162 # Average percentage of cache occupancy 31510585SN/Asystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 31611336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id 31711336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id 31811336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id 31910585SN/Asystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 32011336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 360582168 # Number of tag accesses 32111336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 360582168 # Number of data accesses 32211336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 85561344 # number of ReadReq hits 32311336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 85561344 # number of ReadReq hits 32411353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 80310144 # number of WriteReq hits 32511353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 80310144 # number of WriteReq hits 32611336Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 214412 # number of SoftPFReq hits 32711336Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 214412 # number of SoftPFReq hits 32811353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::cpu0.data 259689 # number of WriteLineReq hits 32911353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::total 259689 # number of WriteLineReq hits 33011336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2079285 # number of LoadLockedReq hits 33111336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 2079285 # number of LoadLockedReq hits 33211353Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 2039805 # number of StoreCondReq hits 33311353Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 2039805 # number of StoreCondReq hits 33411353Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 165871488 # number of demand (read+write) hits 33511353Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 165871488 # number of demand (read+write) hits 33611353Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 166085900 # number of overall hits 33711353Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 166085900 # number of overall hits 33811336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 3292661 # number of ReadReq misses 33911336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 3292661 # number of ReadReq misses 34011353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 1484857 # number of WriteReq misses 34111353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 1484857 # number of WriteReq misses 34211336Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 774558 # number of SoftPFReq misses 34311336Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 774558 # number of SoftPFReq misses 34411353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::cpu0.data 823193 # number of WriteLineReq misses 34511353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::total 823193 # number of WriteLineReq misses 34611336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 118361 # number of LoadLockedReq misses 34711336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 118361 # number of LoadLockedReq misses 34811353Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 156654 # number of StoreCondReq misses 34911353Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 156654 # number of StoreCondReq misses 35011353Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 4777518 # number of demand (read+write) misses 35111353Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 4777518 # number of demand (read+write) misses 35211353Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 5552076 # number of overall misses 35311353Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 5552076 # number of overall misses 35411336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 88854005 # number of ReadReq accesses(hits+misses) 35511336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 88854005 # number of ReadReq accesses(hits+misses) 35611336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 81795001 # number of WriteReq accesses(hits+misses) 35711336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 81795001 # number of WriteReq accesses(hits+misses) 35811336Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 988970 # number of SoftPFReq accesses(hits+misses) 35911336Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 988970 # number of SoftPFReq accesses(hits+misses) 36011336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1082882 # number of WriteLineReq accesses(hits+misses) 36111336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::total 1082882 # number of WriteLineReq accesses(hits+misses) 36211336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2197646 # number of LoadLockedReq accesses(hits+misses) 36311336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 2197646 # number of LoadLockedReq accesses(hits+misses) 36411336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2196459 # number of StoreCondReq accesses(hits+misses) 36511336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 2196459 # number of StoreCondReq accesses(hits+misses) 36611336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 170649006 # number of demand (read+write) accesses 36711336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 170649006 # number of demand (read+write) accesses 36811336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 171637976 # number of overall (read+write) accesses 36911336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 171637976 # number of overall (read+write) accesses 37011336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037057 # miss rate for ReadReq accesses 37111336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.037057 # miss rate for ReadReq accesses 37211336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018153 # miss rate for WriteReq accesses 37311336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.018153 # miss rate for WriteReq accesses 37411336Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.783197 # miss rate for SoftPFReq accesses 37511336Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.783197 # miss rate for SoftPFReq accesses 37611353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760187 # miss rate for WriteLineReq accesses 37711353Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::total 0.760187 # miss rate for WriteLineReq accesses 37811336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053858 # miss rate for LoadLockedReq accesses 37911336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053858 # miss rate for LoadLockedReq accesses 38011353Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.071321 # miss rate for StoreCondReq accesses 38111353Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.071321 # miss rate for StoreCondReq accesses 38211336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.027996 # miss rate for demand accesses 38311336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.027996 # miss rate for demand accesses 38411353Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.032348 # miss rate for overall accesses 38511353Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.032348 # miss rate for overall accesses 38610585SN/Asystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 38710585SN/Asystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 38810585SN/Asystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 38910585SN/Asystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 39010585SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 39110585SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 39210585SN/Asystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 39310585SN/Asystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 39411336Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 6248192 # number of writebacks 39511336Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 6248192 # number of writebacks 39610585SN/Asystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 39711336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 5479450 # number of replacements 39811336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.989014 # Cycle average of tags in use 39911336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 489031557 # Total number of references to valid blocks. 40011336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 5479962 # Sample count of references to valid blocks. 40111336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 89.239954 # Average number of references to valid blocks. 40210585SN/Asystem.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit. 40311336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989014 # Average occupied blocks per requestor 40410585SN/Asystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy 40510585SN/Asystem.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy 40610585SN/Asystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 40711336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id 40811336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id 40911336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id 41010585SN/Asystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 41111336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 994503015 # Number of tag accesses 41211336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 994503015 # Number of data accesses 41311336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 489031557 # number of ReadReq hits 41411336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 489031557 # number of ReadReq hits 41511336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 489031557 # number of demand (read+write) hits 41611336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 489031557 # number of demand (read+write) hits 41711336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 489031557 # number of overall hits 41811336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 489031557 # number of overall hits 41911336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 5479967 # number of ReadReq misses 42011336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 5479967 # number of ReadReq misses 42111336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 5479967 # number of demand (read+write) misses 42211336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 5479967 # number of demand (read+write) misses 42311336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 5479967 # number of overall misses 42411336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 5479967 # number of overall misses 42511336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 494511524 # number of ReadReq accesses(hits+misses) 42611336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 494511524 # number of ReadReq accesses(hits+misses) 42711336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 494511524 # number of demand (read+write) accesses 42811336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 494511524 # number of demand (read+write) accesses 42911336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 494511524 # number of overall (read+write) accesses 43011336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 494511524 # number of overall (read+write) accesses 43111336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011082 # miss rate for ReadReq accesses 43211336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.011082 # miss rate for ReadReq accesses 43311336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.011082 # miss rate for demand accesses 43411336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.011082 # miss rate for demand accesses 43511336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.011082 # miss rate for overall accesses 43611336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.011082 # miss rate for overall accesses 43710585SN/Asystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 43810585SN/Asystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 43910585SN/Asystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 44010585SN/Asystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 44110585SN/Asystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 44210585SN/Asystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 44310585SN/Asystem.cpu0.icache.fast_writes 0 # number of fast writes performed 44410585SN/Asystem.cpu0.icache.cache_copies 0 # number of cache copies performed 44511336Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::writebacks 5479450 # number of writebacks 44611336Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::total 5479450 # number of writebacks 44710585SN/Asystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 44810628SN/Asystem.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 44910628SN/Asystem.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 45010628SN/Asystem.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 45110628SN/Asystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 45210628SN/Asystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 45310628SN/Asystem.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 45411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.replacements 2651590 # number of replacements 45511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tagsinuse 16092.484650 # Cycle average of tags in use 45611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.total_refs 15457113 # Total number of references to valid blocks. 45711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.sampled_refs 2667587 # Sample count of references to valid blocks. 45811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.avg_refs 5.794418 # Average number of references to valid blocks. 45910585SN/Asystem.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. 46011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 15991.608429 # Average occupied blocks per requestor 46111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 49.291374 # Average occupied blocks per requestor 46211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 51.584847 # Average occupied blocks per requestor 46311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.976050 # Average percentage of cache occupancy 46411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003009 # Average percentage of cache occupancy 46511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003148 # Average percentage of cache occupancy 46611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.982207 # Average percentage of cache occupancy 46711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 77 # Occupied blocks per task id 46811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 15920 # Occupied blocks per task id 46911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 56 # Occupied blocks per task id 47011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id 47111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id 47211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 226 # Occupied blocks per task id 47311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1478 # Occupied blocks per task id 47411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4821 # Occupied blocks per task id 47511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4797 # Occupied blocks per task id 47611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4598 # Occupied blocks per task id 47711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004700 # Percentage of cache occupancy per task id 47811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.971680 # Percentage of cache occupancy per task id 47911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tag_accesses 394865177 # Number of tag accesses 48011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.data_accesses 394865177 # Number of data accesses 48111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 294372 # number of ReadReq hits 48211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 156640 # number of ReadReq hits 48311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 451012 # number of ReadReq hits 48411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::writebacks 4430802 # number of WritebackDirty hits 48511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::total 4430802 # number of WritebackDirty hits 48611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_hits::writebacks 7295441 # number of WritebackClean hits 48711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_hits::total 7295441 # number of WritebackClean hits 48811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::cpu0.data 774 # number of UpgradeReq hits 48911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::total 774 # number of UpgradeReq hits 49011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 631554 # number of ReadExReq hits 49111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 631554 # number of ReadExReq hits 49211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4983798 # number of ReadCleanReq hits 49311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 4983798 # number of ReadCleanReq hits 49411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2949332 # number of ReadSharedReq hits 49511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 2949332 # number of ReadSharedReq hits 49611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::cpu0.data 218231 # number of InvalidateReq hits 49711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::total 218231 # number of InvalidateReq hits 49811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 294372 # number of demand (read+write) hits 49911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 156640 # number of demand (read+write) hits 50011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 4983798 # number of demand (read+write) hits 50111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 3580886 # number of demand (read+write) hits 50211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::total 9015696 # number of demand (read+write) hits 50311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 294372 # number of overall hits 50411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 156640 # number of overall hits 50511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 4983798 # number of overall hits 50611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 3580886 # number of overall hits 50711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::total 9015696 # number of overall hits 50811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11531 # number of ReadReq misses 50911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8761 # number of ReadReq misses 51011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 20292 # number of ReadReq misses 51111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 140614 # number of UpgradeReq misses 51211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 140614 # number of UpgradeReq misses 51311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 156654 # number of SCUpgradeReq misses 51411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 156654 # number of SCUpgradeReq misses 51511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 712280 # number of ReadExReq misses 51611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 712280 # number of ReadExReq misses 51711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 496169 # number of ReadCleanReq misses 51811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 496169 # number of ReadCleanReq misses 51911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1236248 # number of ReadSharedReq misses 52011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 1236248 # number of ReadSharedReq misses 52111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::cpu0.data 604597 # number of InvalidateReq misses 52211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::total 604597 # number of InvalidateReq misses 52311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11531 # number of demand (read+write) misses 52411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 8761 # number of demand (read+write) misses 52511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 496169 # number of demand (read+write) misses 52611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 1948528 # number of demand (read+write) misses 52711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::total 2464989 # number of demand (read+write) misses 52811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11531 # number of overall misses 52911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 8761 # number of overall misses 53011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 496169 # number of overall misses 53111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 1948528 # number of overall misses 53211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::total 2464989 # number of overall misses 53311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 305903 # number of ReadReq accesses(hits+misses) 53411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 165401 # number of ReadReq accesses(hits+misses) 53511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 471304 # number of ReadReq accesses(hits+misses) 53611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::writebacks 4430802 # number of WritebackDirty accesses(hits+misses) 53711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::total 4430802 # number of WritebackDirty accesses(hits+misses) 53811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::writebacks 7295441 # number of WritebackClean accesses(hits+misses) 53911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::total 7295441 # number of WritebackClean accesses(hits+misses) 54011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 141388 # number of UpgradeReq accesses(hits+misses) 54111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 141388 # number of UpgradeReq accesses(hits+misses) 54211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 156654 # number of SCUpgradeReq accesses(hits+misses) 54311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 156654 # number of SCUpgradeReq accesses(hits+misses) 54411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1343834 # number of ReadExReq accesses(hits+misses) 54511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1343834 # number of ReadExReq accesses(hits+misses) 54611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5479967 # number of ReadCleanReq accesses(hits+misses) 54711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 5479967 # number of ReadCleanReq accesses(hits+misses) 54811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4185580 # number of ReadSharedReq accesses(hits+misses) 54911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 4185580 # number of ReadSharedReq accesses(hits+misses) 55011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 822828 # number of InvalidateReq accesses(hits+misses) 55111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::total 822828 # number of InvalidateReq accesses(hits+misses) 55211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 305903 # number of demand (read+write) accesses 55311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 165401 # number of demand (read+write) accesses 55411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 5479967 # number of demand (read+write) accesses 55511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 5529414 # number of demand (read+write) accesses 55611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::total 11480685 # number of demand (read+write) accesses 55711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 305903 # number of overall (read+write) accesses 55811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 165401 # number of overall (read+write) accesses 55911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 5479967 # number of overall (read+write) accesses 56011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 5529414 # number of overall (read+write) accesses 56111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::total 11480685 # number of overall (read+write) accesses 56211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.037695 # miss rate for ReadReq accesses 56311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052968 # miss rate for ReadReq accesses 56411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.043055 # miss rate for ReadReq accesses 56511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.994526 # miss rate for UpgradeReq accesses 56611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 0.994526 # miss rate for UpgradeReq accesses 56710585SN/Asystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 56810585SN/Asystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 56911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.530036 # miss rate for ReadExReq accesses 57011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.530036 # miss rate for ReadExReq accesses 57111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.090542 # miss rate for ReadCleanReq accesses 57211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.090542 # miss rate for ReadCleanReq accesses 57311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.295359 # miss rate for ReadSharedReq accesses 57411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.295359 # miss rate for ReadSharedReq accesses 57511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.734779 # miss rate for InvalidateReq accesses 57611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::total 0.734779 # miss rate for InvalidateReq accesses 57711353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.037695 # miss rate for demand accesses 57811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052968 # miss rate for demand accesses 57911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.090542 # miss rate for demand accesses 58011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.352393 # miss rate for demand accesses 58111353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.214707 # miss rate for demand accesses 58211353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.037695 # miss rate for overall accesses 58311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052968 # miss rate for overall accesses 58411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.090542 # miss rate for overall accesses 58511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.352393 # miss rate for overall accesses 58611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.214707 # miss rate for overall accesses 58710585SN/Asystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 58810585SN/Asystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 58910585SN/Asystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 59010585SN/Asystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 59110585SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 59210585SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 59310585SN/Asystem.cpu0.l2cache.fast_writes 0 # number of fast writes performed 59410585SN/Asystem.cpu0.l2cache.cache_copies 0 # number of cache copies performed 59511353Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::writebacks 1558575 # number of writebacks 59611353Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::total 1558575 # number of writebacks 59710585SN/Asystem.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 59811353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_requests 24117057 # Total number of requests made to the snoop filter. 59911353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_requests 12284855 # Number of requests hitting in the snoop filter with a single holder of the requested data. 60011138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1399 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 60111353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_snoops 1785822 # Total number of snoops made to the snoop filter. 60211353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1785488 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 60311353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 334 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 60411336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 618755 # Transaction distribution 60511336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 10284302 # Transaction distribution 60611336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 33226 # Transaction distribution 60711336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 33226 # Transaction distribution 60811353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackDirty 4430802 # Transaction distribution 60911353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackClean 7296840 # Transaction distribution 61011353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 141388 # Transaction distribution 61111353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 156654 # Transaction distribution 61211353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 298042 # Transaction distribution 61311336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1343834 # Transaction distribution 61411336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1343834 # Transaction distribution 61511336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 5479967 # Transaction distribution 61611336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 4185580 # Transaction distribution 61711336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateReq 822828 # Transaction distribution 61811336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateResp 822828 # Transaction distribution 61911336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16525634 # Packet count per connected master and slave (bytes) 62011353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19681390 # Packet count per connected master and slave (bytes) 62111336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 362662 # Packet count per connected master and slave (bytes) 62211336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 722420 # Packet count per connected master and slave (bytes) 62311353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count::total 37292106 # Packet count per connected master and slave (bytes) 62411336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 701575188 # Cumulative packet size per connected master and slave (bytes) 62511336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 753965416 # Cumulative packet size per connected master and slave (bytes) 62611336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1450648 # Cumulative packet size per connected master and slave (bytes) 62711336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2889680 # Cumulative packet size per connected master and slave (bytes) 62811336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size::total 1459880932 # Cumulative packet size per connected master and slave (bytes) 62911353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoops 6124419 # Total snoops (count) 63011353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 30450834 # Request fanout histogram 63111353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 0.067260 # Request fanout histogram 63211353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.250516 # Request fanout histogram 63310585SN/Asystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 63411353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 28403043 93.28% 93.28% # Request fanout histogram 63511353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 2047457 6.72% 100.00% # Request fanout histogram 63611353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 334 0.00% 100.00% # Request fanout histogram 63710585SN/Asystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 63811138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 63910827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 64011353Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 30450834 # Request fanout histogram 64110628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 64210628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 64310628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 64410628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 64510628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 64610628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 64710628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 64810628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 64910585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 65010585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 65110585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 65210585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 65310585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 65410585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 65510585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 65610585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 65710585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 65810585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 65910585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 66010585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 66110585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 66210585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 66310585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 66410585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 66510585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 66610585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 66710585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 66810585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 66910585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 67011336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walks 145097 # Table walker walks requested 67111336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLong 145097 # Table walker walks initiated with long descriptors 67211336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 145097 # Table walker wait (enqueue to first request) latency 67311336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0 145097 100.00% 100.00% # Table walker wait (enqueue to first request) latency 67411336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 145097 # Table walker wait (enqueue to first request) latency 67510628SN/Asystem.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution 67610628SN/Asystem.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution 67710628SN/Asystem.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution 67811336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 112288 88.82% 88.82% # Table walker page sizes translated 67911336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::2M 14132 11.18% 100.00% # Table walker page sizes translated 68011336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 126420 # Table walker page sizes translated 68111336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 145097 # Table walker requests started/completed, data/inst 68210628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 68311336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 145097 # Table walker requests started/completed, data/inst 68411336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 126420 # Table walker requests started/completed, data/inst 68510628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 68611336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 126420 # Table walker requests started/completed, data/inst 68711336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 271517 # Table walker requests started/completed, data/inst 68810585SN/Asystem.cpu1.dtb.inst_hits 0 # ITB inst hits 68910585SN/Asystem.cpu1.dtb.inst_misses 0 # ITB inst misses 69011336Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 90839106 # DTB read hits 69111336Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 112437 # DTB read misses 69211336Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 81787747 # DTB write hits 69311336Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 32660 # DTB write misses 69410585SN/Asystem.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed 69510585SN/Asystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 69611336Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID 69710585SN/Asystem.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 69811336Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_entries 44645 # Number of entries that have been flushed from TLB 69910585SN/Asystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 70011336Sandreas.hansson@arm.comsystem.cpu1.dtb.prefetch_faults 4653 # Number of TLB faults due to prefetch 70110585SN/Asystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 70211336Sandreas.hansson@arm.comsystem.cpu1.dtb.perms_faults 11499 # Number of TLB faults due to permissions restrictions 70311336Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 90951543 # DTB read accesses 70411336Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 81820407 # DTB write accesses 70510585SN/Asystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 70611336Sandreas.hansson@arm.comsystem.cpu1.dtb.hits 172626853 # DTB hits 70711336Sandreas.hansson@arm.comsystem.cpu1.dtb.misses 145097 # DTB misses 70811336Sandreas.hansson@arm.comsystem.cpu1.dtb.accesses 172771950 # DTB accesses 70910628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 71010628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 71110628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 71210628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 71310628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 71410628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 71510628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 71610628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 71710585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 71810585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 71910585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 72010585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 72110585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 72210585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 72310585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 72410585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 72510585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 72610585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 72710585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 72810585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 72910585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 73010585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 73110585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 73210585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 73310585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 73410585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 73510585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 73610585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 73710585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 73811336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walks 61573 # Table walker walks requested 73911336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLong 61573 # Table walker walks initiated with long descriptors 74011336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 61573 # Table walker wait (enqueue to first request) latency 74111336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::0 61573 100.00% 100.00% # Table walker wait (enqueue to first request) latency 74211336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 61573 # Table walker wait (enqueue to first request) latency 74310628SN/Asystem.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution 74410628SN/Asystem.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution 74510628SN/Asystem.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution 74611336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 54551 99.05% 99.05% # Table walker page sizes translated 74711336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::2M 525 0.95% 100.00% # Table walker page sizes translated 74811336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 55076 # Table walker page sizes translated 74910628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 75011336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61573 # Table walker requests started/completed, data/inst 75111336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 61573 # Table walker requests started/completed, data/inst 75210628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 75311336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55076 # Table walker requests started/completed, data/inst 75411336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 55076 # Table walker requests started/completed, data/inst 75511336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 116649 # Table walker requests started/completed, data/inst 75611336Sandreas.hansson@arm.comsystem.cpu1.itb.inst_hits 481656543 # ITB inst hits 75711336Sandreas.hansson@arm.comsystem.cpu1.itb.inst_misses 61573 # ITB inst misses 75810585SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 75910585SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 76010585SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 76110585SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 76210585SN/Asystem.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed 76310585SN/Asystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 76411336Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID 76510585SN/Asystem.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 76611336Sandreas.hansson@arm.comsystem.cpu1.itb.flush_entries 31343 # Number of entries that have been flushed from TLB 76710585SN/Asystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 76810585SN/Asystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 76910585SN/Asystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 77010585SN/Asystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 77110585SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 77210585SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 77311336Sandreas.hansson@arm.comsystem.cpu1.itb.inst_accesses 481718116 # ITB inst accesses 77411336Sandreas.hansson@arm.comsystem.cpu1.itb.hits 481656543 # DTB hits 77511336Sandreas.hansson@arm.comsystem.cpu1.itb.misses 61573 # DTB misses 77611336Sandreas.hansson@arm.comsystem.cpu1.itb.accesses 481718116 # DTB accesses 77711336Sandreas.hansson@arm.comsystem.cpu1.numCycles 94513077683 # number of cpu cycles simulated 77810585SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 77910585SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 78011167Sjthestness@gmail.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 78111336Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 6271 # number of quiesce instructions executed 78211336Sandreas.hansson@arm.comsystem.cpu1.committedInsts 481403040 # Number of instructions committed 78311336Sandreas.hansson@arm.comsystem.cpu1.committedOps 566527691 # Number of ops (including micro ops) committed 78411336Sandreas.hansson@arm.comsystem.cpu1.num_int_alu_accesses 519926686 # Number of integer alu accesses 78511336Sandreas.hansson@arm.comsystem.cpu1.num_fp_alu_accesses 376275 # Number of float alu accesses 78611336Sandreas.hansson@arm.comsystem.cpu1.num_func_calls 28379648 # number of times a function call or return occured 78711336Sandreas.hansson@arm.comsystem.cpu1.num_conditional_control_insts 73708476 # number of instructions that are conditional controls 78811336Sandreas.hansson@arm.comsystem.cpu1.num_int_insts 519926686 # number of integer instructions 78911336Sandreas.hansson@arm.comsystem.cpu1.num_fp_insts 376275 # number of float instructions 79011336Sandreas.hansson@arm.comsystem.cpu1.num_int_register_reads 767885454 # number of times the integer registers were read 79111336Sandreas.hansson@arm.comsystem.cpu1.num_int_register_writes 413863113 # number of times the integer registers were written 79211336Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_reads 612543 # number of times the floating registers were read 79311336Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_writes 304496 # number of times the floating registers were written 79411336Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_reads 127271010 # number of times the CC registers were read 79511336Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_writes 126985650 # number of times the CC registers were written 79611336Sandreas.hansson@arm.comsystem.cpu1.num_mem_refs 172748485 # number of memory refs 79711336Sandreas.hansson@arm.comsystem.cpu1.num_load_insts 90938541 # Number of load instructions 79811336Sandreas.hansson@arm.comsystem.cpu1.num_store_insts 81809944 # Number of store instructions 79911336Sandreas.hansson@arm.comsystem.cpu1.num_idle_cycles 93946236472.485764 # Number of idle cycles 80011336Sandreas.hansson@arm.comsystem.cpu1.num_busy_cycles 566841210.514243 # Number of busy cycles 80111336Sandreas.hansson@arm.comsystem.cpu1.not_idle_fraction 0.005997 # Percentage of non-idle cycles 80211336Sandreas.hansson@arm.comsystem.cpu1.idle_fraction 0.994003 # Percentage of idle cycles 80311336Sandreas.hansson@arm.comsystem.cpu1.Branches 107246711 # Number of branches fetched 80410585SN/Asystem.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 80511336Sandreas.hansson@arm.comsystem.cpu1.op_class::IntAlu 392852056 69.31% 69.31% # Class of executed instruction 80611336Sandreas.hansson@arm.comsystem.cpu1.op_class::IntMult 1138487 0.20% 69.51% # Class of executed instruction 80711336Sandreas.hansson@arm.comsystem.cpu1.op_class::IntDiv 60879 0.01% 69.52% # Class of executed instruction 80811336Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction 80911336Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction 81011336Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction 81111336Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction 81211336Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction 81311336Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction 81411336Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction 81511336Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction 81611336Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction 81711336Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction 81811336Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction 81911336Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction 82011336Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction 82111336Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction 82211336Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction 82311336Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction 82411336Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction 82511336Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAdd 0 0.00% 69.52% # Class of executed instruction 82611336Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction 82711336Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCmp 0 0.00% 69.52% # Class of executed instruction 82811336Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCvt 0 0.00% 69.52% # Class of executed instruction 82911336Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction 83011336Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMisc 36493 0.01% 69.52% # Class of executed instruction 83111336Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction 83211336Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction 83311336Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction 83411336Sandreas.hansson@arm.comsystem.cpu1.op_class::MemRead 90938541 16.04% 85.57% # Class of executed instruction 83511336Sandreas.hansson@arm.comsystem.cpu1.op_class::MemWrite 81809944 14.43% 100.00% # Class of executed instruction 83610585SN/Asystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 83710585SN/Asystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 83811336Sandreas.hansson@arm.comsystem.cpu1.op_class::total 566836400 # Class of executed instruction 83911336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 5963482 # number of replacements 84011336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 422.067067 # Cycle average of tags in use 84111336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 166672957 # Total number of references to valid blocks. 84211336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 5963994 # Sample count of references to valid blocks. 84311336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 27.946533 # Average number of references to valid blocks. 84410585SN/Asystem.cpu1.dcache.tags.warmup_cycle 8470277778500 # Cycle when the warmup percentage was hit. 84511336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 422.067067 # Average occupied blocks per requestor 84611336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.824350 # Average percentage of cache occupancy 84711336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.824350 # Average percentage of cache occupancy 84810726SN/Asystem.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 84911336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 348 # Occupied blocks per task id 85011336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id 85110726SN/Asystem.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 85211336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 351517490 # Number of tag accesses 85311336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 351517490 # Number of data accesses 85411336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 84375671 # number of ReadReq hits 85511336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 84375671 # number of ReadReq hits 85611353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 77626026 # number of WriteReq hits 85711353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 77626026 # number of WriteReq hits 85811336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 188285 # number of SoftPFReq hits 85911336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 188285 # number of SoftPFReq hits 86011353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::cpu1.data 64910 # number of WriteLineReq hits 86111353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::total 64910 # number of WriteLineReq hits 86211336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2062470 # number of LoadLockedReq hits 86311336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 2062470 # number of LoadLockedReq hits 86411353Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 2047982 # number of StoreCondReq hits 86511353Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 2047982 # number of StoreCondReq hits 86611353Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 162001697 # number of demand (read+write) hits 86711353Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 162001697 # number of demand (read+write) hits 86811353Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 162189982 # number of overall hits 86911353Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 162189982 # number of overall hits 87011336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 3369907 # number of ReadReq misses 87111336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 3369907 # number of ReadReq misses 87211353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 1463877 # number of WriteReq misses 87311353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 1463877 # number of WriteReq misses 87411336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 790298 # number of SoftPFReq misses 87511336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 790298 # number of SoftPFReq misses 87611353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::cpu1.data 435843 # number of WriteLineReq misses 87711353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::total 435843 # number of WriteLineReq misses 87811336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 145888 # number of LoadLockedReq misses 87911336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 145888 # number of LoadLockedReq misses 88011353Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 158992 # number of StoreCondReq misses 88111353Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 158992 # number of StoreCondReq misses 88211353Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 4833784 # number of demand (read+write) misses 88311353Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 4833784 # number of demand (read+write) misses 88411353Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 5624082 # number of overall misses 88511353Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 5624082 # number of overall misses 88611336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 87745578 # number of ReadReq accesses(hits+misses) 88711336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 87745578 # number of ReadReq accesses(hits+misses) 88811336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 79089903 # number of WriteReq accesses(hits+misses) 88911336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 79089903 # number of WriteReq accesses(hits+misses) 89011336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 978583 # number of SoftPFReq accesses(hits+misses) 89111336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 978583 # number of SoftPFReq accesses(hits+misses) 89211336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::cpu1.data 500753 # number of WriteLineReq accesses(hits+misses) 89311336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::total 500753 # number of WriteLineReq accesses(hits+misses) 89411336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2208358 # number of LoadLockedReq accesses(hits+misses) 89511336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 2208358 # number of LoadLockedReq accesses(hits+misses) 89611336Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2206974 # number of StoreCondReq accesses(hits+misses) 89711336Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 2206974 # number of StoreCondReq accesses(hits+misses) 89811336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 166835481 # number of demand (read+write) accesses 89911336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 166835481 # number of demand (read+write) accesses 90011336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 167814064 # number of overall (read+write) accesses 90111336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 167814064 # number of overall (read+write) accesses 90211336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038405 # miss rate for ReadReq accesses 90311336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.038405 # miss rate for ReadReq accesses 90411353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018509 # miss rate for WriteReq accesses 90511353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.018509 # miss rate for WriteReq accesses 90611336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.807594 # miss rate for SoftPFReq accesses 90711336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.807594 # miss rate for SoftPFReq accesses 90811353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870375 # miss rate for WriteLineReq accesses 90911353Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::total 0.870375 # miss rate for WriteLineReq accesses 91011336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066062 # miss rate for LoadLockedReq accesses 91111336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066062 # miss rate for LoadLockedReq accesses 91211353Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.072041 # miss rate for StoreCondReq accesses 91311353Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.072041 # miss rate for StoreCondReq accesses 91411336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.028973 # miss rate for demand accesses 91511336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.028973 # miss rate for demand accesses 91611353Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.033514 # miss rate for overall accesses 91711353Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.033514 # miss rate for overall accesses 91810585SN/Asystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 91910585SN/Asystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 92010585SN/Asystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 92110585SN/Asystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 92210585SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 92310585SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 92410585SN/Asystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 92510585SN/Asystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 92611336Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 5963482 # number of writebacks 92711336Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 5963482 # number of writebacks 92810585SN/Asystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 92911336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 4804881 # number of replacements 93011336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 496.439171 # Cycle average of tags in use 93111336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 476906226 # Total number of references to valid blocks. 93211336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 4805393 # Sample count of references to valid blocks. 93311336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 99.243959 # Average number of references to valid blocks. 93410585SN/Asystem.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit. 93511336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 496.439171 # Average occupied blocks per requestor 93611336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.969608 # Average percentage of cache occupancy 93711336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.969608 # Average percentage of cache occupancy 93810585SN/Asystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 93911336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 34 # Occupied blocks per task id 94011336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id 94111336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id 94210585SN/Asystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 94311336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 968228631 # Number of tag accesses 94411336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 968228631 # Number of data accesses 94511336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 476906226 # number of ReadReq hits 94611336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 476906226 # number of ReadReq hits 94711336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 476906226 # number of demand (read+write) hits 94811336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 476906226 # number of demand (read+write) hits 94911336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 476906226 # number of overall hits 95011336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 476906226 # number of overall hits 95111336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 4805393 # number of ReadReq misses 95211336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 4805393 # number of ReadReq misses 95311336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 4805393 # number of demand (read+write) misses 95411336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 4805393 # number of demand (read+write) misses 95511336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 4805393 # number of overall misses 95611336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 4805393 # number of overall misses 95711336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 481711619 # number of ReadReq accesses(hits+misses) 95811336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 481711619 # number of ReadReq accesses(hits+misses) 95911336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 481711619 # number of demand (read+write) accesses 96011336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 481711619 # number of demand (read+write) accesses 96111336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 481711619 # number of overall (read+write) accesses 96211336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 481711619 # number of overall (read+write) accesses 96311336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009976 # miss rate for ReadReq accesses 96411336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.009976 # miss rate for ReadReq accesses 96511336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.009976 # miss rate for demand accesses 96611336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.009976 # miss rate for demand accesses 96711336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.009976 # miss rate for overall accesses 96811336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.009976 # miss rate for overall accesses 96910585SN/Asystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 97010585SN/Asystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 97110585SN/Asystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 97210585SN/Asystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 97310585SN/Asystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 97410585SN/Asystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 97510585SN/Asystem.cpu1.icache.fast_writes 0 # number of fast writes performed 97610585SN/Asystem.cpu1.icache.cache_copies 0 # number of cache copies performed 97711336Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::writebacks 4804881 # number of writebacks 97811336Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::total 4804881 # number of writebacks 97910585SN/Asystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 98010628SN/Asystem.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 98110628SN/Asystem.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 98210628SN/Asystem.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 98310628SN/Asystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 98410628SN/Asystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 98510628SN/Asystem.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 98611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.replacements 2274505 # number of replacements 98711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tagsinuse 13370.273853 # Cycle average of tags in use 98811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.total_refs 14355408 # Total number of references to valid blocks. 98911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.sampled_refs 2290637 # Sample count of references to valid blocks. 99011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.avg_refs 6.266994 # Average number of references to valid blocks. 99111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 9713557342500 # Cycle when the warmup percentage was hit. 99211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 13266.664229 # Average occupied blocks per requestor 99311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 44.449121 # Average occupied blocks per requestor 99411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 59.160502 # Average occupied blocks per requestor 99511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.809733 # Average percentage of cache occupancy 99611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002713 # Average percentage of cache occupancy 99711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003611 # Average percentage of cache occupancy 99811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.816057 # Average percentage of cache occupancy 99911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 66 # Occupied blocks per task id 100011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 16066 # Occupied blocks per task id 100111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id 100211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 37 # Occupied blocks per task id 100311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 100411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id 100511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 307 # Occupied blocks per task id 100611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1542 # Occupied blocks per task id 100711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5867 # Occupied blocks per task id 100811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4427 # Occupied blocks per task id 100911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3923 # Occupied blocks per task id 101011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004028 # Percentage of cache occupancy per task id 101111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.980591 # Percentage of cache occupancy per task id 101211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tag_accesses 364664430 # Number of tag accesses 101311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.data_accesses 364664430 # Number of data accesses 101411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 349739 # number of ReadReq hits 101511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155441 # number of ReadReq hits 101611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 505180 # number of ReadReq hits 101711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::writebacks 4030758 # number of WritebackDirty hits 101811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::total 4030758 # number of WritebackDirty hits 101911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_hits::writebacks 6737219 # number of WritebackClean hits 102011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_hits::total 6737219 # number of WritebackClean hits 102111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1036 # number of UpgradeReq hits 102211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::total 1036 # number of UpgradeReq hits 102311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 606945 # number of ReadExReq hits 102411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 606945 # number of ReadExReq hits 102511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4338204 # number of ReadCleanReq hits 102611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 4338204 # number of ReadCleanReq hits 102711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3075973 # number of ReadSharedReq hits 102811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 3075973 # number of ReadSharedReq hits 102911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::cpu1.data 162958 # number of InvalidateReq hits 103011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::total 162958 # number of InvalidateReq hits 103111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 349739 # number of demand (read+write) hits 103211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 155441 # number of demand (read+write) hits 103311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 4338204 # number of demand (read+write) hits 103411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 3682918 # number of demand (read+write) hits 103511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::total 8526302 # number of demand (read+write) hits 103611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 349739 # number of overall hits 103711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 155441 # number of overall hits 103811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 4338204 # number of overall hits 103911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 3682918 # number of overall hits 104011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::total 8526302 # number of overall hits 104111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12351 # number of ReadReq misses 104211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9805 # number of ReadReq misses 104311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 22156 # number of ReadReq misses 104411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 147585 # number of UpgradeReq misses 104511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 147585 # number of UpgradeReq misses 104611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 158992 # number of SCUpgradeReq misses 104711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 158992 # number of SCUpgradeReq misses 104811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 708546 # number of ReadExReq misses 104911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 708546 # number of ReadExReq misses 105011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 467189 # number of ReadCleanReq misses 105111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 467189 # number of ReadCleanReq misses 105211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1230120 # number of ReadSharedReq misses 105311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 1230120 # number of ReadSharedReq misses 105411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::cpu1.data 272650 # number of InvalidateReq misses 105511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::total 272650 # number of InvalidateReq misses 105611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12351 # number of demand (read+write) misses 105711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 9805 # number of demand (read+write) misses 105811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 467189 # number of demand (read+write) misses 105911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 1938666 # number of demand (read+write) misses 106011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::total 2428011 # number of demand (read+write) misses 106111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12351 # number of overall misses 106211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 9805 # number of overall misses 106311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 467189 # number of overall misses 106411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 1938666 # number of overall misses 106511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::total 2428011 # number of overall misses 106611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 362090 # number of ReadReq accesses(hits+misses) 106711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 165246 # number of ReadReq accesses(hits+misses) 106811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 527336 # number of ReadReq accesses(hits+misses) 106911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::writebacks 4030758 # number of WritebackDirty accesses(hits+misses) 107011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::total 4030758 # number of WritebackDirty accesses(hits+misses) 107111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::writebacks 6737219 # number of WritebackClean accesses(hits+misses) 107211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::total 6737219 # number of WritebackClean accesses(hits+misses) 107311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 148621 # number of UpgradeReq accesses(hits+misses) 107411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 148621 # number of UpgradeReq accesses(hits+misses) 107511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 158992 # number of SCUpgradeReq accesses(hits+misses) 107611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 158992 # number of SCUpgradeReq accesses(hits+misses) 107711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1315491 # number of ReadExReq accesses(hits+misses) 107811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 1315491 # number of ReadExReq accesses(hits+misses) 107911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4805393 # number of ReadCleanReq accesses(hits+misses) 108011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 4805393 # number of ReadCleanReq accesses(hits+misses) 108111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4306093 # number of ReadSharedReq accesses(hits+misses) 108211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 4306093 # number of ReadSharedReq accesses(hits+misses) 108311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 435608 # number of InvalidateReq accesses(hits+misses) 108411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::total 435608 # number of InvalidateReq accesses(hits+misses) 108511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 362090 # number of demand (read+write) accesses 108611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 165246 # number of demand (read+write) accesses 108711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 4805393 # number of demand (read+write) accesses 108811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 5621584 # number of demand (read+write) accesses 108911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::total 10954313 # number of demand (read+write) accesses 109011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 362090 # number of overall (read+write) accesses 109111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 165246 # number of overall (read+write) accesses 109211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 4805393 # number of overall (read+write) accesses 109311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 5621584 # number of overall (read+write) accesses 109411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::total 10954313 # number of overall (read+write) accesses 109511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.034110 # miss rate for ReadReq accesses 109611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.059336 # miss rate for ReadReq accesses 109711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.042015 # miss rate for ReadReq accesses 109811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.993029 # miss rate for UpgradeReq accesses 109911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 0.993029 # miss rate for UpgradeReq accesses 110010585SN/Asystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 110110585SN/Asystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 110211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.538617 # miss rate for ReadExReq accesses 110311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.538617 # miss rate for ReadExReq accesses 110411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.097222 # miss rate for ReadCleanReq accesses 110511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.097222 # miss rate for ReadCleanReq accesses 110611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.285670 # miss rate for ReadSharedReq accesses 110711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.285670 # miss rate for ReadSharedReq accesses 110811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.625907 # miss rate for InvalidateReq accesses 110911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::total 0.625907 # miss rate for InvalidateReq accesses 111011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.034110 # miss rate for demand accesses 111111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.059336 # miss rate for demand accesses 111211353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.097222 # miss rate for demand accesses 111311353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.344861 # miss rate for demand accesses 111411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.221649 # miss rate for demand accesses 111511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.034110 # miss rate for overall accesses 111611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.059336 # miss rate for overall accesses 111711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.097222 # miss rate for overall accesses 111811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.344861 # miss rate for overall accesses 111911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.221649 # miss rate for overall accesses 112010585SN/Asystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 112110585SN/Asystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 112210585SN/Asystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 112310585SN/Asystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 112410585SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 112510585SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 112610585SN/Asystem.cpu1.l2cache.fast_writes 0 # number of fast writes performed 112710585SN/Asystem.cpu1.l2cache.cache_copies 0 # number of cache copies performed 112811353Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::writebacks 1199052 # number of writebacks 112911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::total 1199052 # number of writebacks 113010585SN/Asystem.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 113111353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_requests 22219600 # Total number of requests made to the snoop filter. 113211353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_requests 11357015 # Number of requests hitting in the snoop filter with a single holder of the requested data. 113311336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_requests 386 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 113411353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_snoops 1768706 # Total number of snoops made to the snoop filter. 113511353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1768522 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 113611353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 184 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 113711336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 610577 # Transaction distribution 113811336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 9722063 # Transaction distribution 113911336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 5621 # Transaction distribution 114011336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 5621 # Transaction distribution 114111353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackDirty 4030758 # Transaction distribution 114211353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackClean 6737605 # Transaction distribution 114311353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 148621 # Transaction distribution 114411353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 158992 # Transaction distribution 114511353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 307613 # Transaction distribution 114611336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 1315491 # Transaction distribution 114711336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 1315491 # Transaction distribution 114811336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 4805393 # Transaction distribution 114911336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 4306093 # Transaction distribution 115011336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateReq 435608 # Transaction distribution 115111336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateResp 435608 # Transaction distribution 115211336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14415927 # Packet count per connected master and slave (bytes) 115311353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18716020 # Packet count per connected master and slave (bytes) 115411336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 368094 # Packet count per connected master and slave (bytes) 115511336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 841114 # Packet count per connected master and slave (bytes) 115611353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count::total 34341155 # Packet count per connected master and slave (bytes) 115711336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 615058056 # Cumulative packet size per connected master and slave (bytes) 115811336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 741477723 # Cumulative packet size per connected master and slave (bytes) 115911336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1472376 # Cumulative packet size per connected master and slave (bytes) 116011336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3364456 # Cumulative packet size per connected master and slave (bytes) 116111336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size::total 1361372611 # Cumulative packet size per connected master and slave (bytes) 116211353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoops 5725702 # Total snoops (count) 116311353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 28118123 # Request fanout histogram 116411353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 0.072932 # Request fanout histogram 116511353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.260049 # Request fanout histogram 116610585SN/Asystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 116711353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 26067606 92.71% 92.71% # Request fanout histogram 116811353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 2050333 7.29% 100.00% # Request fanout histogram 116911353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 184 0.00% 100.00% # Request fanout histogram 117010585SN/Asystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 117111138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 117210827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 117311353Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 28118123 # Request fanout histogram 117411336Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 40311 # Transaction distribution 117511336Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 40311 # Transaction distribution 117611336Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 136636 # Transaction distribution 117711336Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 136636 # Transaction distribution 117811336Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47650 # Packet count per connected master and slave (bytes) 117910585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 118011245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 118110585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 118210585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 118310585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 118410585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 118510585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 118610585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 118710585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 118810585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 118910585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 119010585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 119111336Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122584 # Packet count per connected master and slave (bytes) 119211336Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231230 # Packet count per connected master and slave (bytes) 119311336Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231230 # Packet count per connected master and slave (bytes) 119410585SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 119510585SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 119611336Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 353894 # Packet count per connected master and slave (bytes) 119711336Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47670 # Cumulative packet size per connected master and slave (bytes) 119810585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 119911245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 120010585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 120110585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 120210585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 120310585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 120410585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 120510585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 120610585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 120710585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 120810585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 120910585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 121011336Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 155691 # Cumulative packet size per connected master and slave (bytes) 121111336Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338936 # Cumulative packet size per connected master and slave (bytes) 121211336Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7338936 # Cumulative packet size per connected master and slave (bytes) 121310585SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 121410585SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 121511336Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 7496713 # Cumulative packet size per connected master and slave (bytes) 121611336Sandreas.hansson@arm.comsystem.iocache.tags.replacements 115596 # number of replacements 121711336Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 11.294855 # Cycle average of tags in use 121810585SN/Asystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 121911336Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 115612 # Sample count of references to valid blocks. 122010585SN/Asystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 122110585SN/Asystem.iocache.tags.warmup_cycle 9107775783009 # Cycle when the warmup percentage was hit. 122211336Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 3.848747 # Average occupied blocks per requestor 122311336Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 7.446108 # Average occupied blocks per requestor 122411336Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.240547 # Average percentage of cache occupancy 122511336Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.465382 # Average percentage of cache occupancy 122611336Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.705928 # Average percentage of cache occupancy 122710585SN/Asystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 122810585SN/Asystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 122910585SN/Asystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 123011336Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 1040892 # Number of tag accesses 123111336Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 1040892 # Number of data accesses 123210585SN/Asystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 123311336Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ide 8887 # number of ReadReq misses 123411336Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 8924 # number of ReadReq misses 123510585SN/Asystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 123610585SN/Asystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 123710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 123810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 123910585SN/Asystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 124011336Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ide 8887 # number of demand (read+write) misses 124111336Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 8927 # number of demand (read+write) misses 124210585SN/Asystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 124311336Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ide 8887 # number of overall misses 124411336Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 8927 # number of overall misses 124510585SN/Asystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 124611336Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8887 # number of ReadReq accesses(hits+misses) 124711336Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 8924 # number of ReadReq accesses(hits+misses) 124810585SN/Asystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 124910585SN/Asystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 125010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 125110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 125210585SN/Asystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 125311336Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ide 8887 # number of demand (read+write) accesses 125411336Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 8927 # number of demand (read+write) accesses 125510585SN/Asystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 125611336Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 8887 # number of overall (read+write) accesses 125711336Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 8927 # number of overall (read+write) accesses 125810585SN/Asystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 125910585SN/Asystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 126010585SN/Asystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 126110585SN/Asystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 126210585SN/Asystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 126310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 126410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 126510585SN/Asystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 126610585SN/Asystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 126710585SN/Asystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 126810585SN/Asystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 126910585SN/Asystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 127010585SN/Asystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 127110585SN/Asystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 127210585SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 127310585SN/Asystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 127410585SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 127510585SN/Asystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 127610585SN/Asystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 127710585SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 127810585SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 127910585SN/Asystem.iocache.writebacks::writebacks 106694 # number of writebacks 128010585SN/Asystem.iocache.writebacks::total 106694 # number of writebacks 128110585SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 128211353Sandreas.hansson@arm.comsystem.l2c.tags.replacements 1766126 # number of replacements 128311353Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 63106.596515 # Cycle average of tags in use 128411353Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 4618110 # Total number of references to valid blocks. 128511353Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 1825499 # Sample count of references to valid blocks. 128611353Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 2.529780 # Average number of references to valid blocks. 128711353Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 514828500 # Cycle when the warmup percentage was hit. 128811353Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 34858.975183 # Average occupied blocks per requestor 128911353Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 68.002297 # Average occupied blocks per requestor 129011353Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 102.298868 # Average occupied blocks per requestor 129111353Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 3405.442592 # Average occupied blocks per requestor 129211353Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 8003.318713 # Average occupied blocks per requestor 129311353Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 244.723732 # Average occupied blocks per requestor 129411353Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 389.512702 # Average occupied blocks per requestor 129511353Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 2881.151775 # Average occupied blocks per requestor 129611353Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 13153.170652 # Average occupied blocks per requestor 129711353Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.531906 # Average percentage of cache occupancy 129811353Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.001038 # Average percentage of cache occupancy 129911353Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.001561 # Average percentage of cache occupancy 130011353Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.051963 # Average percentage of cache occupancy 130111353Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.122121 # Average percentage of cache occupancy 130211353Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.003734 # Average percentage of cache occupancy 130311353Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.005943 # Average percentage of cache occupancy 130411353Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.043963 # Average percentage of cache occupancy 130511353Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.200701 # Average percentage of cache occupancy 130611353Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.962930 # Average percentage of cache occupancy 130711353Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 203 # Occupied blocks per task id 130811353Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 59170 # Occupied blocks per task id 130911353Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id 131011353Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 200 # Occupied blocks per task id 131111353Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 131211353Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 472 # Occupied blocks per task id 131311353Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 3156 # Occupied blocks per task id 131411353Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 5264 # Occupied blocks per task id 131511353Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 50220 # Occupied blocks per task id 131611353Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.003098 # Percentage of cache occupancy per task id 131711353Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.902863 # Percentage of cache occupancy per task id 131811353Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 73355182 # Number of tag accesses 131911353Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 73355182 # Number of data accesses 132011353Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::writebacks 2757627 # number of WritebackDirty hits 132111353Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::total 2757627 # number of WritebackDirty hits 132211353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 19019 # number of UpgradeReq hits 132311353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 16164 # number of UpgradeReq hits 132411353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 35183 # number of UpgradeReq hits 132511353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 2641 # number of SCUpgradeReq hits 132611353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 2463 # number of SCUpgradeReq hits 132711353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 5104 # number of SCUpgradeReq hits 132811353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 198159 # number of ReadExReq hits 132911353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 177179 # number of ReadExReq hits 133011353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 375338 # number of ReadExReq hits 133111353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6315 # number of ReadSharedReq hits 133211353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 4649 # number of ReadSharedReq hits 133311353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 438189 # number of ReadSharedReq hits 133411353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 723007 # number of ReadSharedReq hits 133511353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5487 # number of ReadSharedReq hits 133611353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 3779 # number of ReadSharedReq hits 133711353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 426355 # number of ReadSharedReq hits 133811353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 685222 # number of ReadSharedReq hits 133911353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::total 2293003 # number of ReadSharedReq hits 134011353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_hits::cpu0.data 118931 # number of InvalidateReq hits 134111353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_hits::cpu1.data 103897 # number of InvalidateReq hits 134211353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_hits::total 222828 # number of InvalidateReq hits 134311353Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 6315 # number of demand (read+write) hits 134411353Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 4649 # number of demand (read+write) hits 134511353Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 438189 # number of demand (read+write) hits 134611353Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 921166 # number of demand (read+write) hits 134711353Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 5487 # number of demand (read+write) hits 134811353Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 3779 # number of demand (read+write) hits 134911353Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 426355 # number of demand (read+write) hits 135011353Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 862401 # number of demand (read+write) hits 135111353Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 2668341 # number of demand (read+write) hits 135211353Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 6315 # number of overall hits 135311353Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 4649 # number of overall hits 135411353Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 438189 # number of overall hits 135511353Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 921166 # number of overall hits 135611353Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 5487 # number of overall hits 135711353Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 3779 # number of overall hits 135811353Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 426355 # number of overall hits 135911353Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 862401 # number of overall hits 136011353Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 2668341 # number of overall hits 136111353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 65379 # number of UpgradeReq misses 136211353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 61938 # number of UpgradeReq misses 136311353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 127317 # number of UpgradeReq misses 136411353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 6666 # number of SCUpgradeReq misses 136511353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 6353 # number of SCUpgradeReq misses 136611353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 13019 # number of SCUpgradeReq misses 136711353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 385718 # number of ReadExReq misses 136811353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 415753 # number of ReadExReq misses 136911353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 801471 # number of ReadExReq misses 137011353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2451 # number of ReadSharedReq misses 137111336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 2053 # number of ReadSharedReq misses 137211353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 57980 # number of ReadSharedReq misses 137311353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 180523 # number of ReadSharedReq misses 137411353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3403 # number of ReadSharedReq misses 137511353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.itb.walker 3345 # number of ReadSharedReq misses 137611353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 40834 # number of ReadSharedReq misses 137711353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 186956 # number of ReadSharedReq misses 137811353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::total 477545 # number of ReadSharedReq misses 137911353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_misses::cpu0.data 477269 # number of InvalidateReq misses 138011353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_misses::cpu1.data 162394 # number of InvalidateReq misses 138111353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_misses::total 639663 # number of InvalidateReq misses 138211353Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 2451 # number of demand (read+write) misses 138311336Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 2053 # number of demand (read+write) misses 138411353Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 57980 # number of demand (read+write) misses 138511353Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 566241 # number of demand (read+write) misses 138611353Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 3403 # number of demand (read+write) misses 138711353Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.itb.walker 3345 # number of demand (read+write) misses 138811353Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 40834 # number of demand (read+write) misses 138911353Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 602709 # number of demand (read+write) misses 139011353Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 1279016 # number of demand (read+write) misses 139111353Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 2451 # number of overall misses 139211336Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 2053 # number of overall misses 139311353Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 57980 # number of overall misses 139411353Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 566241 # number of overall misses 139511353Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 3403 # number of overall misses 139611353Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.itb.walker 3345 # number of overall misses 139711353Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 40834 # number of overall misses 139811353Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 602709 # number of overall misses 139911353Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 1279016 # number of overall misses 140011353Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 2757627 # number of WritebackDirty accesses(hits+misses) 140111353Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::total 2757627 # number of WritebackDirty accesses(hits+misses) 140211353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 84398 # number of UpgradeReq accesses(hits+misses) 140311353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 78102 # number of UpgradeReq accesses(hits+misses) 140411353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 162500 # number of UpgradeReq accesses(hits+misses) 140511353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 9307 # number of SCUpgradeReq accesses(hits+misses) 140611353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 8816 # number of SCUpgradeReq accesses(hits+misses) 140711353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 18123 # number of SCUpgradeReq accesses(hits+misses) 140811353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 583877 # number of ReadExReq accesses(hits+misses) 140911353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 592932 # number of ReadExReq accesses(hits+misses) 141011353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 1176809 # number of ReadExReq accesses(hits+misses) 141111353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8766 # number of ReadSharedReq accesses(hits+misses) 141211353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6702 # number of ReadSharedReq accesses(hits+misses) 141311353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 496169 # number of ReadSharedReq accesses(hits+misses) 141411353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 903530 # number of ReadSharedReq accesses(hits+misses) 141511353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8890 # number of ReadSharedReq accesses(hits+misses) 141611353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7124 # number of ReadSharedReq accesses(hits+misses) 141711353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 467189 # number of ReadSharedReq accesses(hits+misses) 141811353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 872178 # number of ReadSharedReq accesses(hits+misses) 141911353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::total 2770548 # number of ReadSharedReq accesses(hits+misses) 142011353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_accesses::cpu0.data 596200 # number of InvalidateReq accesses(hits+misses) 142111353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_accesses::cpu1.data 266291 # number of InvalidateReq accesses(hits+misses) 142211353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_accesses::total 862491 # number of InvalidateReq accesses(hits+misses) 142311353Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 8766 # number of demand (read+write) accesses 142411353Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 6702 # number of demand (read+write) accesses 142511353Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 496169 # number of demand (read+write) accesses 142611353Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 1487407 # number of demand (read+write) accesses 142711353Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 8890 # number of demand (read+write) accesses 142811353Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 7124 # number of demand (read+write) accesses 142911353Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 467189 # number of demand (read+write) accesses 143011353Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 1465110 # number of demand (read+write) accesses 143111353Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 3947357 # number of demand (read+write) accesses 143211353Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 8766 # number of overall (read+write) accesses 143311353Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 6702 # number of overall (read+write) accesses 143411353Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 496169 # number of overall (read+write) accesses 143511353Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 1487407 # number of overall (read+write) accesses 143611353Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 8890 # number of overall (read+write) accesses 143711353Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 7124 # number of overall (read+write) accesses 143811353Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 467189 # number of overall (read+write) accesses 143911353Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 1465110 # number of overall (read+write) accesses 144011353Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 3947357 # number of overall (read+write) accesses 144111353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.774651 # miss rate for UpgradeReq accesses 144211353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.793040 # miss rate for UpgradeReq accesses 144311353Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.783489 # miss rate for UpgradeReq accesses 144411353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.716235 # miss rate for SCUpgradeReq accesses 144511353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.720622 # miss rate for SCUpgradeReq accesses 144611353Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.718369 # miss rate for SCUpgradeReq accesses 144711353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.660615 # miss rate for ReadExReq accesses 144811353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.701182 # miss rate for ReadExReq accesses 144911353Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.681054 # miss rate for ReadExReq accesses 145011353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.279603 # miss rate for ReadSharedReq accesses 145111353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.306326 # miss rate for ReadSharedReq accesses 145211353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.116855 # miss rate for ReadSharedReq accesses 145311353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.199797 # miss rate for ReadSharedReq accesses 145411353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.382790 # miss rate for ReadSharedReq accesses 145511353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.469540 # miss rate for ReadSharedReq accesses 145611353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.087404 # miss rate for ReadSharedReq accesses 145711353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.214355 # miss rate for ReadSharedReq accesses 145811353Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.172365 # miss rate for ReadSharedReq accesses 145911353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu0.data 0.800518 # miss rate for InvalidateReq accesses 146011353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu1.data 0.609837 # miss rate for InvalidateReq accesses 146111353Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_miss_rate::total 0.741646 # miss rate for InvalidateReq accesses 146211353Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.279603 # miss rate for demand accesses 146311353Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.306326 # miss rate for demand accesses 146411353Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.116855 # miss rate for demand accesses 146511353Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.380690 # miss rate for demand accesses 146611353Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.382790 # miss rate for demand accesses 146711353Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.469540 # miss rate for demand accesses 146811353Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.087404 # miss rate for demand accesses 146911353Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.411375 # miss rate for demand accesses 147011353Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.324018 # miss rate for demand accesses 147111353Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.279603 # miss rate for overall accesses 147211353Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.306326 # miss rate for overall accesses 147311353Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.116855 # miss rate for overall accesses 147411353Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.380690 # miss rate for overall accesses 147511353Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.382790 # miss rate for overall accesses 147611353Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.469540 # miss rate for overall accesses 147711353Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.087404 # miss rate for overall accesses 147811353Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.411375 # miss rate for overall accesses 147911353Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.324018 # miss rate for overall accesses 148010515SN/Asystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 148110515SN/Asystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 148210515SN/Asystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 148310515SN/Asystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 148410515SN/Asystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 148510515SN/Asystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 148610515SN/Asystem.l2c.fast_writes 0 # number of fast writes performed 148710515SN/Asystem.l2c.cache_copies 0 # number of cache copies performed 148811353Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 1473799 # number of writebacks 148911353Sandreas.hansson@arm.comsystem.l2c.writebacks::total 1473799 # number of writebacks 149010515SN/Asystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 149111336Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 82185 # Transaction distribution 149211353Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 568654 # Transaction distribution 149311336Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 38847 # Transaction distribution 149411336Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 38847 # Transaction distribution 149511353Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty 1580493 # Transaction distribution 149611353Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 246676 # Transaction distribution 149711353Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 346899 # Transaction distribution 149811353Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 310542 # Transaction distribution 149911353Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 162598 # Transaction distribution 150011353Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 787734 # Transaction distribution 150111353Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 783864 # Transaction distribution 150211353Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 486469 # Transaction distribution 150311353Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 741739 # Transaction distribution 150411353Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 741739 # Transaction distribution 150511336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122584 # Packet count per connected master and slave (bytes) 150610585SN/Asystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 150711336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27742 # Packet count per connected master and slave (bytes) 150811353Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6419962 # Packet count per connected master and slave (bytes) 150911353Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 6570380 # Packet count per connected master and slave (bytes) 151011336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346906 # Packet count per connected master and slave (bytes) 151111336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 346906 # Packet count per connected master and slave (bytes) 151211353Sandreas.hansson@arm.comsystem.membus.pkt_count::total 6917286 # Packet count per connected master and slave (bytes) 151311336Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155691 # Cumulative packet size per connected master and slave (bytes) 151410585SN/Asystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 151511336Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55484 # Cumulative packet size per connected master and slave (bytes) 151611353Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 175247068 # Cumulative packet size per connected master and slave (bytes) 151711353Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 175458447 # Cumulative packet size per connected master and slave (bytes) 151811336Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7399552 # Cumulative packet size per connected master and slave (bytes) 151911336Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7399552 # Cumulative packet size per connected master and slave (bytes) 152011353Sandreas.hansson@arm.comsystem.membus.pkt_size::total 182857999 # Cumulative packet size per connected master and slave (bytes) 152110585SN/Asystem.membus.snoops 0 # Total snoops (count) 152211353Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 4621584 # Request fanout histogram 152310585SN/Asystem.membus.snoop_fanout::mean 1 # Request fanout histogram 152410585SN/Asystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 152510585SN/Asystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 152610585SN/Asystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 152711353Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 4621584 100.00% 100.00% # Request fanout histogram 152810585SN/Asystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 152910585SN/Asystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 153010585SN/Asystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 153110585SN/Asystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 153211353Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 4621584 # Request fanout histogram 153311239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 153411239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 153511239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 153611239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 153711239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 153811239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 153910515SN/Asystem.realview.ethernet.txBytes 966 # Bytes Transmitted 154010515SN/Asystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 154110515SN/Asystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 154210515SN/Asystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 154310515SN/Asystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 154410515SN/Asystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 154510515SN/Asystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 154610515SN/Asystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 154710515SN/Asystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 154810515SN/Asystem.realview.ethernet.totBandwidth 164 # Total Bandwidth (bits/s) 154910515SN/Asystem.realview.ethernet.totPackets 3 # Total Packets 155010515SN/Asystem.realview.ethernet.totBytes 966 # Total Bytes 155110515SN/Asystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 155210515SN/Asystem.realview.ethernet.txBandwidth 164 # Transmit Bandwidth (bits/s) 155310515SN/Asystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 155410515SN/Asystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 155510515SN/Asystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 155610515SN/Asystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 155710515SN/Asystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 155810515SN/Asystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 155910515SN/Asystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 156010515SN/Asystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 156110515SN/Asystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 156210515SN/Asystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 156310515SN/Asystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 156410515SN/Asystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 156510515SN/Asystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 156610515SN/Asystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 156710515SN/Asystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 156810515SN/Asystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 156910515SN/Asystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 157010515SN/Asystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 157110515SN/Asystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 157210515SN/Asystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 157310515SN/Asystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 157410515SN/Asystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 157510515SN/Asystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 157610515SN/Asystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 157710515SN/Asystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 157810515SN/Asystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 157910515SN/Asystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 158010515SN/Asystem.realview.ethernet.droppedPackets 0 # number of packets dropped 158111239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 158211239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 158311239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 158411239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 158511353Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_requests 11149977 # Total number of requests made to the snoop filter. 158611353Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 5745476 # Number of requests hitting in the snoop filter with a single holder of the requested data. 158711353Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 1663139 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 158811353Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 131712 # Total number of snoops made to the snoop filter. 158911353Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 118684 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 159011353Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 13028 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 159111336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 82187 # Transaction distribution 159211353Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 3554361 # Transaction distribution 159311336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 38847 # Transaction distribution 159411336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 38847 # Transaction distribution 159511353Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 2757627 # Transaction distribution 159611353Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::CleanEvict 2018256 # Transaction distribution 159711353Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 359820 # Transaction distribution 159811353Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 315646 # Transaction distribution 159911353Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 675466 # Transaction distribution 160011353Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 1363961 # Transaction distribution 160111353Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 1363961 # Transaction distribution 160211353Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 3472174 # Transaction distribution 160311353Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::InvalidateReq 862491 # Transaction distribution 160411353Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::InvalidateResp 862491 # Transaction distribution 160511353Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9530168 # Packet count per connected master and slave (bytes) 160611353Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8235967 # Packet count per connected master and slave (bytes) 160711353Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 17766135 # Packet count per connected master and slave (bytes) 160811353Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 255951612 # Cumulative packet size per connected master and slave (bytes) 160911353Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 230454307 # Cumulative packet size per connected master and slave (bytes) 161011353Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 486405919 # Cumulative packet size per connected master and slave (bytes) 161111353Sandreas.hansson@arm.comsystem.toL2Bus.snoops 1999071 # Total snoops (count) 161211353Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 13268387 # Request fanout histogram 161311353Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 0.283691 # Request fanout histogram 161411353Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.452962 # Request fanout histogram 161510515SN/Asystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 161611353Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::0 9517290 71.73% 71.73% # Request fanout histogram 161711353Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 3738069 28.17% 99.90% # Request fanout histogram 161811353Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 13028 0.10% 100.00% # Request fanout histogram 161910515SN/Asystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 162011138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 162110515SN/Asystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 162211353Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 13268387 # Request fanout histogram 162310515SN/A 162410515SN/A---------- End Simulation Statistics ---------- 1625