stats.txt revision 11239
110515SN/A 210515SN/A---------- Begin Simulation Statistics ---------- 310726SN/Asim_seconds 47.216814 # Number of seconds simulated 410726SN/Asim_ticks 47216814145000 # Number of ticks simulated 510726SN/Afinal_tick 47216814145000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711239Sandreas.sandberg@arm.comhost_inst_rate 564335 # Simulator instruction rate (inst/s) 811239Sandreas.sandberg@arm.comhost_op_rate 663890 # Simulator op (including micro ops) rate (op/s) 911239Sandreas.sandberg@arm.comhost_tick_rate 27316522801 # Simulator tick rate (ticks/s) 1011239Sandreas.sandberg@arm.comhost_mem_usage 691236 # Number of bytes of host memory used 1111239Sandreas.sandberg@arm.comhost_seconds 1728.51 # Real time elapsed on the host 1210726SN/Asim_insts 975457230 # Number of instructions simulated 1310726SN/Asim_ops 1147538415 # Number of ops (including micro ops) simulated 1410515SN/Asystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SN/Asystem.clk_domain.clock 1000 # Clock period in ticks 1611201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 152064 # Number of bytes read from this memory 1711201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 126912 # Number of bytes read from this memory 1811201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 3862964 # Number of bytes read from this memory 1911201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 62933832 # Number of bytes read from this memory 2011201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 221952 # Number of bytes read from this memory 2111201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.itb.walker 220096 # Number of bytes read from this memory 2211201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 2661000 # Number of bytes read from this memory 2311201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 46409840 # Number of bytes read from this memory 2411201Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 419200 # Number of bytes read from this memory 2511201Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 117007860 # Number of bytes read from this memory 2611201Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 3862964 # Number of instructions bytes read from this memory 2711201Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 2661000 # Number of instructions bytes read from this memory 2811201Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 6523964 # Number of instructions bytes read from this memory 2911201Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 100926976 # Number of bytes written to this memory 3010827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 3110585SN/Asystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3211201Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 100947560 # Number of bytes written to this memory 3311201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 2376 # Number of read requests responded to by this memory 3411201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.itb.walker 1983 # Number of read requests responded to by this memory 3511201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 100766 # Number of read requests responded to by this memory 3611201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 983354 # Number of read requests responded to by this memory 3711201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 3468 # Number of read requests responded to by this memory 3811201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.itb.walker 3439 # Number of read requests responded to by this memory 3911201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 41685 # Number of read requests responded to by this memory 4011201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 725170 # Number of read requests responded to by this memory 4111201Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 6550 # Number of read requests responded to by this memory 4211201Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1868791 # Number of read requests responded to by this memory 4311201Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 1576984 # Number of write requests responded to by this memory 4410827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 4510585SN/Asystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 4611201Sandreas.hansson@arm.comsystem.physmem.num_writes::total 1579558 # Number of write requests responded to by this memory 4711201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 3221 # Total read bandwidth from this memory (bytes/s) 4811201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.itb.walker 2688 # Total read bandwidth from this memory (bytes/s) 4911201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 81813 # Total read bandwidth from this memory (bytes/s) 5011201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 1332869 # Total read bandwidth from this memory (bytes/s) 5111201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 4701 # Total read bandwidth from this memory (bytes/s) 5211201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.itb.walker 4661 # Total read bandwidth from this memory (bytes/s) 5311201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 56357 # Total read bandwidth from this memory (bytes/s) 5411201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 982909 # Total read bandwidth from this memory (bytes/s) 5511201Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 8878 # Total read bandwidth from this memory (bytes/s) 5611201Sandreas.hansson@arm.comsystem.physmem.bw_read::total 2478097 # Total read bandwidth from this memory (bytes/s) 5711201Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 81813 # Instruction read bandwidth from this memory (bytes/s) 5811201Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 56357 # Instruction read bandwidth from this memory (bytes/s) 5911201Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 138170 # Instruction read bandwidth from this memory (bytes/s) 6011201Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 2137522 # Write bandwidth from this memory (bytes/s) 6110827Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu0.data 436 # Write bandwidth from this memory (bytes/s) 6210585SN/Asystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 6311201Sandreas.hansson@arm.comsystem.physmem.bw_write::total 2137958 # Write bandwidth from this memory (bytes/s) 6411201Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 2137522 # Total bandwidth to/from this memory (bytes/s) 6511201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 3221 # Total bandwidth to/from this memory (bytes/s) 6611201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.itb.walker 2688 # Total bandwidth to/from this memory (bytes/s) 6711201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 81813 # Total bandwidth to/from this memory (bytes/s) 6811201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 1333305 # Total bandwidth to/from this memory (bytes/s) 6911201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 4701 # Total bandwidth to/from this memory (bytes/s) 7011201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.itb.walker 4661 # Total bandwidth to/from this memory (bytes/s) 7111201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 56357 # Total bandwidth to/from this memory (bytes/s) 7211201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 982909 # Total bandwidth to/from this memory (bytes/s) 7311201Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 8878 # Total bandwidth to/from this memory (bytes/s) 7411201Sandreas.hansson@arm.comsystem.physmem.bw_total::total 4616055 # Total bandwidth to/from this memory (bytes/s) 7510515SN/Asystem.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 7610515SN/Asystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 7710515SN/Asystem.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 7810515SN/Asystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 7910515SN/Asystem.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 8010515SN/Asystem.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 8110515SN/Asystem.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 8210515SN/Asystem.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 8310515SN/Asystem.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 8410515SN/Asystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 8510515SN/Asystem.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 8610515SN/Asystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 8710515SN/Asystem.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 8810515SN/Asystem.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 8910515SN/Asystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 9010515SN/Asystem.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 9110515SN/Asystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 9210515SN/Asystem.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 9310515SN/Asystem.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 9410515SN/Asystem.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 9510515SN/Asystem.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 9610515SN/Asystem.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 9710515SN/Asystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 9810515SN/Asystem.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 9910515SN/Asystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 10010515SN/Asystem.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 10110585SN/Asystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 10210585SN/Asystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 10310585SN/Asystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 10410585SN/Asystem.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 10510585SN/Asystem.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 10610585SN/Asystem.cf0.dma_write_txs 1670 # Number of DMA write transactions. 10710515SN/Asystem.cpu_clk_domain.clock 500 # Clock period in ticks 10810628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 10910628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 11010628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 11110628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 11210628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 11310628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 11410628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 11510628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 11610585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 11710585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 11810585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 11910585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 12010585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 12110585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 12210585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 12310585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 12410585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 12510585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 12610585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 12710585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 12810585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 12910585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 13010585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 13110585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 13210585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 13310585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 13410585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 13510585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 13610585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 13710726SN/Asystem.cpu0.dtb.walker.walks 125229 # Table walker walks requested 13810726SN/Asystem.cpu0.dtb.walker.walksLong 125229 # Table walker walks initiated with long descriptors 13910726SN/Asystem.cpu0.dtb.walker.walkWaitTime::samples 125229 # Table walker wait (enqueue to first request) latency 14010726SN/Asystem.cpu0.dtb.walker.walkWaitTime::0 125229 100.00% 100.00% # Table walker wait (enqueue to first request) latency 14110726SN/Asystem.cpu0.dtb.walker.walkWaitTime::total 125229 # Table walker wait (enqueue to first request) latency 14210628SN/Asystem.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution 14310628SN/Asystem.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution 14410628SN/Asystem.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution 14510726SN/Asystem.cpu0.dtb.walker.walkPageSizes::4K 96746 89.71% 89.71% # Table walker page sizes translated 14610726SN/Asystem.cpu0.dtb.walker.walkPageSizes::2M 11103 10.29% 100.00% # Table walker page sizes translated 14710726SN/Asystem.cpu0.dtb.walker.walkPageSizes::total 107849 # Table walker page sizes translated 14810726SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 125229 # Table walker requests started/completed, data/inst 14910628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 15010726SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 125229 # Table walker requests started/completed, data/inst 15110726SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107849 # Table walker requests started/completed, data/inst 15210628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 15310726SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107849 # Table walker requests started/completed, data/inst 15410726SN/Asystem.cpu0.dtb.walker.walkRequestOrigin::total 233078 # Table walker requests started/completed, data/inst 15510585SN/Asystem.cpu0.dtb.inst_hits 0 # ITB inst hits 15610585SN/Asystem.cpu0.dtb.inst_misses 0 # ITB inst misses 15710726SN/Asystem.cpu0.dtb.read_hits 92662773 # DTB read hits 15810726SN/Asystem.cpu0.dtb.read_misses 88786 # DTB read misses 15910726SN/Asystem.cpu0.dtb.write_hits 85694958 # DTB write hits 16010726SN/Asystem.cpu0.dtb.write_misses 36443 # DTB write misses 16110585SN/Asystem.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed 16210585SN/Asystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 16310726SN/Asystem.cpu0.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID 16410585SN/Asystem.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 16510726SN/Asystem.cpu0.dtb.flush_entries 36354 # Number of entries that have been flushed from TLB 16610585SN/Asystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 16710726SN/Asystem.cpu0.dtb.prefetch_faults 5600 # Number of TLB faults due to prefetch 16810585SN/Asystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 16910726SN/Asystem.cpu0.dtb.perms_faults 10503 # Number of TLB faults due to permissions restrictions 17010726SN/Asystem.cpu0.dtb.read_accesses 92751559 # DTB read accesses 17110726SN/Asystem.cpu0.dtb.write_accesses 85731401 # DTB write accesses 17210585SN/Asystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 17310726SN/Asystem.cpu0.dtb.hits 178357731 # DTB hits 17410726SN/Asystem.cpu0.dtb.misses 125229 # DTB misses 17510726SN/Asystem.cpu0.dtb.accesses 178482960 # DTB accesses 17610628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 17710628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 17810628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 17910628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 18010628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 18110628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 18210628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 18310628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 18410585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 18510585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 18610585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 18710585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 18810585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 18910585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 19010585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 19110585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 19210585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 19310585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 19410585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 19510585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 19610585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 19710585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 19810585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 19910585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 20010585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 20110585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 20210585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 20310585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 20410585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 20510726SN/Asystem.cpu0.itb.walker.walks 61377 # Table walker walks requested 20610726SN/Asystem.cpu0.itb.walker.walksLong 61377 # Table walker walks initiated with long descriptors 20710726SN/Asystem.cpu0.itb.walker.walkWaitTime::samples 61377 # Table walker wait (enqueue to first request) latency 20810726SN/Asystem.cpu0.itb.walker.walkWaitTime::0 61377 100.00% 100.00% # Table walker wait (enqueue to first request) latency 20910726SN/Asystem.cpu0.itb.walker.walkWaitTime::total 61377 # Table walker wait (enqueue to first request) latency 21010628SN/Asystem.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution 21110628SN/Asystem.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution 21210628SN/Asystem.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution 21310726SN/Asystem.cpu0.itb.walker.walkPageSizes::4K 55424 98.80% 98.80% # Table walker page sizes translated 21410726SN/Asystem.cpu0.itb.walker.walkPageSizes::2M 672 1.20% 100.00% # Table walker page sizes translated 21510726SN/Asystem.cpu0.itb.walker.walkPageSizes::total 56096 # Table walker page sizes translated 21610628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 21710726SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61377 # Table walker requests started/completed, data/inst 21810726SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 61377 # Table walker requests started/completed, data/inst 21910628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 22010726SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56096 # Table walker requests started/completed, data/inst 22110726SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 56096 # Table walker requests started/completed, data/inst 22210726SN/Asystem.cpu0.itb.walker.walkRequestOrigin::total 117473 # Table walker requests started/completed, data/inst 22310726SN/Asystem.cpu0.itb.inst_hits 497696393 # ITB inst hits 22410726SN/Asystem.cpu0.itb.inst_misses 61377 # ITB inst misses 22510585SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 22610585SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 22710585SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 22810585SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 22910585SN/Asystem.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed 23010585SN/Asystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 23110726SN/Asystem.cpu0.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID 23210585SN/Asystem.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 23310726SN/Asystem.cpu0.itb.flush_entries 25032 # Number of entries that have been flushed from TLB 23410585SN/Asystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 23510585SN/Asystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 23610585SN/Asystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 23710585SN/Asystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 23810585SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 23910585SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 24010726SN/Asystem.cpu0.itb.inst_accesses 497757770 # ITB inst accesses 24110726SN/Asystem.cpu0.itb.hits 497696393 # DTB hits 24210726SN/Asystem.cpu0.itb.misses 61377 # DTB misses 24310726SN/Asystem.cpu0.itb.accesses 497757770 # DTB accesses 24411167Sjthestness@gmail.comsystem.cpu0.numCycles 94433641544 # number of cpu cycles simulated 24510585SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 24610585SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 24711167Sjthestness@gmail.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 24811167Sjthestness@gmail.comsystem.cpu0.kern.inst.quiesce 13253 # number of quiesce instructions executed 24910726SN/Asystem.cpu0.committedInsts 497466384 # Number of instructions committed 25010726SN/Asystem.cpu0.committedOps 584970773 # Number of ops (including micro ops) committed 25110726SN/Asystem.cpu0.num_int_alu_accesses 536103359 # Number of integer alu accesses 25210726SN/Asystem.cpu0.num_fp_alu_accesses 526132 # Number of float alu accesses 25310726SN/Asystem.cpu0.num_func_calls 28869117 # number of times a function call or return occured 25410726SN/Asystem.cpu0.num_conditional_control_insts 76496594 # number of instructions that are conditional controls 25510726SN/Asystem.cpu0.num_int_insts 536103359 # number of integer instructions 25610726SN/Asystem.cpu0.num_fp_insts 526132 # number of float instructions 25710726SN/Asystem.cpu0.num_int_register_reads 784958858 # number of times the integer registers were read 25810726SN/Asystem.cpu0.num_int_register_writes 425337843 # number of times the integer registers were written 25910726SN/Asystem.cpu0.num_fp_register_reads 849923 # number of times the floating registers were read 26010726SN/Asystem.cpu0.num_fp_register_writes 443780 # number of times the floating registers were written 26110726SN/Asystem.cpu0.num_cc_register_reads 133878831 # number of times the CC registers were read 26210726SN/Asystem.cpu0.num_cc_register_writes 133531045 # number of times the CC registers were written 26310726SN/Asystem.cpu0.num_mem_refs 178459396 # number of memory refs 26410726SN/Asystem.cpu0.num_load_insts 92737001 # Number of load instructions 26510726SN/Asystem.cpu0.num_store_insts 85722395 # Number of store instructions 26611167Sjthestness@gmail.comsystem.cpu0.num_idle_cycles 93848337191.325058 # Number of idle cycles 26711167Sjthestness@gmail.comsystem.cpu0.num_busy_cycles 585304352.674931 # Number of busy cycles 26810726SN/Asystem.cpu0.not_idle_fraction 0.006198 # Percentage of non-idle cycles 26910726SN/Asystem.cpu0.idle_fraction 0.993802 # Percentage of idle cycles 27010726SN/Asystem.cpu0.Branches 111287587 # Number of branches fetched 27110585SN/Asystem.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 27210726SN/Asystem.cpu0.op_class::IntAlu 405476023 69.28% 69.28% # Class of executed instruction 27310726SN/Asystem.cpu0.op_class::IntMult 1232194 0.21% 69.49% # Class of executed instruction 27410726SN/Asystem.cpu0.op_class::IntDiv 59840 0.01% 69.50% # Class of executed instruction 27510726SN/Asystem.cpu0.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction 27610726SN/Asystem.cpu0.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction 27710726SN/Asystem.cpu0.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction 27810726SN/Asystem.cpu0.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction 27910726SN/Asystem.cpu0.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction 28010726SN/Asystem.cpu0.op_class::FloatSqrt 0 0.00% 69.50% # Class of executed instruction 28110726SN/Asystem.cpu0.op_class::SimdAdd 0 0.00% 69.50% # Class of executed instruction 28210726SN/Asystem.cpu0.op_class::SimdAddAcc 0 0.00% 69.50% # Class of executed instruction 28310726SN/Asystem.cpu0.op_class::SimdAlu 0 0.00% 69.50% # Class of executed instruction 28410726SN/Asystem.cpu0.op_class::SimdCmp 0 0.00% 69.50% # Class of executed instruction 28510726SN/Asystem.cpu0.op_class::SimdCvt 0 0.00% 69.50% # Class of executed instruction 28610726SN/Asystem.cpu0.op_class::SimdMisc 0 0.00% 69.50% # Class of executed instruction 28710726SN/Asystem.cpu0.op_class::SimdMult 0 0.00% 69.50% # Class of executed instruction 28810726SN/Asystem.cpu0.op_class::SimdMultAcc 0 0.00% 69.50% # Class of executed instruction 28910726SN/Asystem.cpu0.op_class::SimdShift 0 0.00% 69.50% # Class of executed instruction 29010726SN/Asystem.cpu0.op_class::SimdShiftAcc 0 0.00% 69.50% # Class of executed instruction 29110726SN/Asystem.cpu0.op_class::SimdSqrt 0 0.00% 69.50% # Class of executed instruction 29210726SN/Asystem.cpu0.op_class::SimdFloatAdd 8 0.00% 69.50% # Class of executed instruction 29310726SN/Asystem.cpu0.op_class::SimdFloatAlu 0 0.00% 69.50% # Class of executed instruction 29410726SN/Asystem.cpu0.op_class::SimdFloatCmp 13 0.00% 69.50% # Class of executed instruction 29510726SN/Asystem.cpu0.op_class::SimdFloatCvt 21 0.00% 69.50% # Class of executed instruction 29610726SN/Asystem.cpu0.op_class::SimdFloatDiv 0 0.00% 69.50% # Class of executed instruction 29710726SN/Asystem.cpu0.op_class::SimdFloatMisc 72507 0.01% 69.51% # Class of executed instruction 29810726SN/Asystem.cpu0.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction 29910726SN/Asystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction 30010726SN/Asystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction 30110726SN/Asystem.cpu0.op_class::MemRead 92737001 15.84% 85.35% # Class of executed instruction 30210726SN/Asystem.cpu0.op_class::MemWrite 85722395 14.65% 100.00% # Class of executed instruction 30310585SN/Asystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 30410585SN/Asystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 30510726SN/Asystem.cpu0.op_class::total 585300003 # Class of executed instruction 30611138Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 6272771 # number of replacements 30710726SN/Asystem.cpu0.dcache.tags.tagsinuse 500.885315 # Cycle average of tags in use 30811138Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 172015771 # Total number of references to valid blocks. 30911138Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 6273283 # Sample count of references to valid blocks. 31011138Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 27.420375 # Average number of references to valid blocks. 31110827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. 31210726SN/Asystem.cpu0.dcache.tags.occ_blocks::cpu0.data 500.885315 # Average occupied blocks per requestor 31310726SN/Asystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.978292 # Average percentage of cache occupancy 31410726SN/Asystem.cpu0.dcache.tags.occ_percent::total 0.978292 # Average percentage of cache occupancy 31510585SN/Asystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 31610726SN/Asystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id 31710726SN/Asystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id 31810726SN/Asystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id 31910585SN/Asystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 32011138Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 363162248 # Number of tag accesses 32111138Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 363162248 # Number of data accesses 32210892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 86214911 # number of ReadReq hits 32310892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 86214911 # number of ReadReq hits 32411201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 80912298 # number of WriteReq hits 32511201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 80912298 # number of WriteReq hits 32610827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 215654 # number of SoftPFReq hits 32710827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 215654 # number of SoftPFReq hits 32811201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::cpu0.data 262024 # number of WriteLineReq hits 32911201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::total 262024 # number of WriteLineReq hits 33010892Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2076466 # number of LoadLockedReq hits 33110892Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 2076466 # number of LoadLockedReq hits 33211201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 2036634 # number of StoreCondReq hits 33311201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 2036634 # number of StoreCondReq hits 33411201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 167127209 # number of demand (read+write) hits 33511201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 167127209 # number of demand (read+write) hits 33611201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 167342863 # number of overall hits 33711201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 167342863 # number of overall hits 33810892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 3309382 # number of ReadReq misses 33910892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 3309382 # number of ReadReq misses 34011201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 1483144 # number of WriteReq misses 34111201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 1483144 # number of WriteReq misses 34210827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 772139 # number of SoftPFReq misses 34310827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 772139 # number of SoftPFReq misses 34411201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::cpu0.data 831696 # number of WriteLineReq misses 34511201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::total 831696 # number of WriteLineReq misses 34610892Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119816 # number of LoadLockedReq misses 34710892Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 119816 # number of LoadLockedReq misses 34811201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 158509 # number of StoreCondReq misses 34911201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 158509 # number of StoreCondReq misses 35011201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 4792526 # number of demand (read+write) misses 35111201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 4792526 # number of demand (read+write) misses 35211201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 5564665 # number of overall misses 35311201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 5564665 # number of overall misses 35410827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 89524293 # number of ReadReq accesses(hits+misses) 35510827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 89524293 # number of ReadReq accesses(hits+misses) 35610827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 82395442 # number of WriteReq accesses(hits+misses) 35710827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 82395442 # number of WriteReq accesses(hits+misses) 35810726SN/Asystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 987793 # number of SoftPFReq accesses(hits+misses) 35910726SN/Asystem.cpu0.dcache.SoftPFReq_accesses::total 987793 # number of SoftPFReq accesses(hits+misses) 36010892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1093720 # number of WriteLineReq accesses(hits+misses) 36110892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::total 1093720 # number of WriteLineReq accesses(hits+misses) 36210726SN/Asystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2196282 # number of LoadLockedReq accesses(hits+misses) 36310726SN/Asystem.cpu0.dcache.LoadLockedReq_accesses::total 2196282 # number of LoadLockedReq accesses(hits+misses) 36410726SN/Asystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2195143 # number of StoreCondReq accesses(hits+misses) 36510726SN/Asystem.cpu0.dcache.StoreCondReq_accesses::total 2195143 # number of StoreCondReq accesses(hits+misses) 36610827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 171919735 # number of demand (read+write) accesses 36710827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 171919735 # number of demand (read+write) accesses 36810827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 172907528 # number of overall (read+write) accesses 36910827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 172907528 # number of overall (read+write) accesses 37010726SN/Asystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036966 # miss rate for ReadReq accesses 37110726SN/Asystem.cpu0.dcache.ReadReq_miss_rate::total 0.036966 # miss rate for ReadReq accesses 37211201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018000 # miss rate for WriteReq accesses 37311201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.018000 # miss rate for WriteReq accesses 37410827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781681 # miss rate for SoftPFReq accesses 37510827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.781681 # miss rate for SoftPFReq accesses 37611201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760429 # miss rate for WriteLineReq accesses 37711201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::total 0.760429 # miss rate for WriteLineReq accesses 37810726SN/Asystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054554 # miss rate for LoadLockedReq accesses 37910726SN/Asystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054554 # miss rate for LoadLockedReq accesses 38011201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.072209 # miss rate for StoreCondReq accesses 38111201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.072209 # miss rate for StoreCondReq accesses 38211201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.027877 # miss rate for demand accesses 38311201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.027877 # miss rate for demand accesses 38411201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.032183 # miss rate for overall accesses 38511201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.032183 # miss rate for overall accesses 38610585SN/Asystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 38710585SN/Asystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 38810585SN/Asystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 38910585SN/Asystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 39010585SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 39110585SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 39210585SN/Asystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 39310585SN/Asystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 39411201Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 6272771 # number of writebacks 39511201Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 6272771 # number of writebacks 39610585SN/Asystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 39710892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 5539081 # number of replacements 39810726SN/Asystem.cpu0.icache.tags.tagsinuse 511.989005 # Cycle average of tags in use 39910892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 492212891 # Total number of references to valid blocks. 40010892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 5539593 # Sample count of references to valid blocks. 40110892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 88.853620 # Average number of references to valid blocks. 40210585SN/Asystem.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit. 40310726SN/Asystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989005 # Average occupied blocks per requestor 40410585SN/Asystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy 40510585SN/Asystem.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy 40610585SN/Asystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 40710726SN/Asystem.cpu0.icache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id 40810726SN/Asystem.cpu0.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id 40910726SN/Asystem.cpu0.icache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id 41010585SN/Asystem.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 41110585SN/Asystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 41210892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 1001044576 # Number of tag accesses 41310892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 1001044576 # Number of data accesses 41410892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 492212891 # number of ReadReq hits 41510892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 492212891 # number of ReadReq hits 41610892Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 492212891 # number of demand (read+write) hits 41710892Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 492212891 # number of demand (read+write) hits 41810892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 492212891 # number of overall hits 41910892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 492212891 # number of overall hits 42010892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 5539598 # number of ReadReq misses 42110892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 5539598 # number of ReadReq misses 42210892Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 5539598 # number of demand (read+write) misses 42310892Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 5539598 # number of demand (read+write) misses 42410892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 5539598 # number of overall misses 42510892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 5539598 # number of overall misses 42610726SN/Asystem.cpu0.icache.ReadReq_accesses::cpu0.inst 497752489 # number of ReadReq accesses(hits+misses) 42710726SN/Asystem.cpu0.icache.ReadReq_accesses::total 497752489 # number of ReadReq accesses(hits+misses) 42810726SN/Asystem.cpu0.icache.demand_accesses::cpu0.inst 497752489 # number of demand (read+write) accesses 42910726SN/Asystem.cpu0.icache.demand_accesses::total 497752489 # number of demand (read+write) accesses 43010726SN/Asystem.cpu0.icache.overall_accesses::cpu0.inst 497752489 # number of overall (read+write) accesses 43110726SN/Asystem.cpu0.icache.overall_accesses::total 497752489 # number of overall (read+write) accesses 43210726SN/Asystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011129 # miss rate for ReadReq accesses 43310726SN/Asystem.cpu0.icache.ReadReq_miss_rate::total 0.011129 # miss rate for ReadReq accesses 43410726SN/Asystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.011129 # miss rate for demand accesses 43510726SN/Asystem.cpu0.icache.demand_miss_rate::total 0.011129 # miss rate for demand accesses 43610726SN/Asystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.011129 # miss rate for overall accesses 43710726SN/Asystem.cpu0.icache.overall_miss_rate::total 0.011129 # miss rate for overall accesses 43810585SN/Asystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 43910585SN/Asystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 44010585SN/Asystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 44110585SN/Asystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 44210585SN/Asystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 44310585SN/Asystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 44410585SN/Asystem.cpu0.icache.fast_writes 0 # number of fast writes performed 44510585SN/Asystem.cpu0.icache.cache_copies 0 # number of cache copies performed 44611201Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::writebacks 5539081 # number of writebacks 44711201Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::total 5539081 # number of writebacks 44810585SN/Asystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 44910628SN/Asystem.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 45010628SN/Asystem.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 45110628SN/Asystem.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 45210628SN/Asystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 45310628SN/Asystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 45410628SN/Asystem.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 45511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.replacements 2670833 # number of replacements 45611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tagsinuse 16144.496707 # Cycle average of tags in use 45711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.total_refs 15583793 # Total number of references to valid blocks. 45811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.sampled_refs 2686790 # Sample count of references to valid blocks. 45911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.avg_refs 5.800153 # Average number of references to valid blocks. 46010585SN/Asystem.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. 46111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 16059.102143 # Average occupied blocks per requestor 46211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 41.665572 # Average occupied blocks per requestor 46311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 43.728993 # Average occupied blocks per requestor 46411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.980170 # Average percentage of cache occupancy 46511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002543 # Average percentage of cache occupancy 46611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.002669 # Average percentage of cache occupancy 46711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.985382 # Average percentage of cache occupancy 46811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 50 # Occupied blocks per task id 46911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 15907 # Occupied blocks per task id 47011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 35 # Occupied blocks per task id 47111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id 47211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id 47311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 242 # Occupied blocks per task id 47411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1465 # Occupied blocks per task id 47511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4378 # Occupied blocks per task id 47611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5313 # Occupied blocks per task id 47711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4509 # Occupied blocks per task id 47811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003052 # Percentage of cache occupancy per task id 47911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.970886 # Percentage of cache occupancy per task id 48011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tag_accesses 397685392 # Number of tag accesses 48111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.data_accesses 397685392 # Number of data accesses 48211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 298097 # number of ReadReq hits 48311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 159313 # number of ReadReq hits 48411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 457410 # number of ReadReq hits 48511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::writebacks 4459579 # number of WritebackDirty hits 48611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::total 4459579 # number of WritebackDirty hits 48711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_hits::writebacks 7350874 # number of WritebackClean hits 48811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_hits::total 7350874 # number of WritebackClean hits 48911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::cpu0.data 760 # number of UpgradeReq hits 49011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::total 760 # number of UpgradeReq hits 49111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 635944 # number of ReadExReq hits 49211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 635944 # number of ReadExReq hits 49311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5035825 # number of ReadCleanReq hits 49411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 5035825 # number of ReadCleanReq hits 49511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2962064 # number of ReadSharedReq hits 49611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 2962064 # number of ReadSharedReq hits 49711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::cpu0.data 223971 # number of InvalidateReq hits 49811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::total 223971 # number of InvalidateReq hits 49911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 298097 # number of demand (read+write) hits 50011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 159313 # number of demand (read+write) hits 50111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 5035825 # number of demand (read+write) hits 50211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 3598008 # number of demand (read+write) hits 50311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::total 9091243 # number of demand (read+write) hits 50411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 298097 # number of overall hits 50511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 159313 # number of overall hits 50611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 5035825 # number of overall hits 50711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 3598008 # number of overall hits 50811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::total 9091243 # number of overall hits 50911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11326 # number of ReadReq misses 51011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8418 # number of ReadReq misses 51111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 19744 # number of ReadReq misses 51211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 138515 # number of UpgradeReq misses 51311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 138515 # number of UpgradeReq misses 51411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 158509 # number of SCUpgradeReq misses 51511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 158509 # number of SCUpgradeReq misses 51611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 708286 # number of ReadExReq misses 51711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 708286 # number of ReadExReq misses 51811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 503773 # number of ReadCleanReq misses 51911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 503773 # number of ReadCleanReq misses 52011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1239273 # number of ReadSharedReq misses 52111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 1239273 # number of ReadSharedReq misses 52211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::cpu0.data 607364 # number of InvalidateReq misses 52311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::total 607364 # number of InvalidateReq misses 52411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11326 # number of demand (read+write) misses 52511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 8418 # number of demand (read+write) misses 52611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 503773 # number of demand (read+write) misses 52711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 1947559 # number of demand (read+write) misses 52811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::total 2471076 # number of demand (read+write) misses 52911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11326 # number of overall misses 53011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 8418 # number of overall misses 53111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 503773 # number of overall misses 53211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 1947559 # number of overall misses 53311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::total 2471076 # number of overall misses 53411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 309423 # number of ReadReq accesses(hits+misses) 53511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 167731 # number of ReadReq accesses(hits+misses) 53611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 477154 # number of ReadReq accesses(hits+misses) 53711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::writebacks 4459579 # number of WritebackDirty accesses(hits+misses) 53811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::total 4459579 # number of WritebackDirty accesses(hits+misses) 53911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::writebacks 7350874 # number of WritebackClean accesses(hits+misses) 54011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::total 7350874 # number of WritebackClean accesses(hits+misses) 54111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 139275 # number of UpgradeReq accesses(hits+misses) 54211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 139275 # number of UpgradeReq accesses(hits+misses) 54311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 158509 # number of SCUpgradeReq accesses(hits+misses) 54411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 158509 # number of SCUpgradeReq accesses(hits+misses) 54511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1344230 # number of ReadExReq accesses(hits+misses) 54611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1344230 # number of ReadExReq accesses(hits+misses) 54710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5539598 # number of ReadCleanReq accesses(hits+misses) 54810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 5539598 # number of ReadCleanReq accesses(hits+misses) 54910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4201337 # number of ReadSharedReq accesses(hits+misses) 55010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 4201337 # number of ReadSharedReq accesses(hits+misses) 55111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 831335 # number of InvalidateReq accesses(hits+misses) 55211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::total 831335 # number of InvalidateReq accesses(hits+misses) 55311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 309423 # number of demand (read+write) accesses 55411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 167731 # number of demand (read+write) accesses 55510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 5539598 # number of demand (read+write) accesses 55611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 5545567 # number of demand (read+write) accesses 55711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::total 11562319 # number of demand (read+write) accesses 55811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 309423 # number of overall (read+write) accesses 55911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 167731 # number of overall (read+write) accesses 56010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 5539598 # number of overall (read+write) accesses 56111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 5545567 # number of overall (read+write) accesses 56211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::total 11562319 # number of overall (read+write) accesses 56311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.036604 # miss rate for ReadReq accesses 56411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.050188 # miss rate for ReadReq accesses 56511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.041379 # miss rate for ReadReq accesses 56611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.994543 # miss rate for UpgradeReq accesses 56711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 0.994543 # miss rate for UpgradeReq accesses 56810585SN/Asystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 56910585SN/Asystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 57011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.526908 # miss rate for ReadExReq accesses 57111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.526908 # miss rate for ReadExReq accesses 57211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.090940 # miss rate for ReadCleanReq accesses 57311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.090940 # miss rate for ReadCleanReq accesses 57411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.294971 # miss rate for ReadSharedReq accesses 57511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.294971 # miss rate for ReadSharedReq accesses 57611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.730589 # miss rate for InvalidateReq accesses 57711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::total 0.730589 # miss rate for InvalidateReq accesses 57811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.036604 # miss rate for demand accesses 57911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.050188 # miss rate for demand accesses 58011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.090940 # miss rate for demand accesses 58111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.351192 # miss rate for demand accesses 58211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.213718 # miss rate for demand accesses 58311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.036604 # miss rate for overall accesses 58411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.050188 # miss rate for overall accesses 58511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.090940 # miss rate for overall accesses 58611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.351192 # miss rate for overall accesses 58711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.213718 # miss rate for overall accesses 58810585SN/Asystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 58910585SN/Asystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 59010585SN/Asystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 59110585SN/Asystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 59210585SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 59310585SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 59410585SN/Asystem.cpu0.l2cache.fast_writes 0 # number of fast writes performed 59510585SN/Asystem.cpu0.l2cache.cache_copies 0 # number of cache copies performed 59611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::writebacks 1567377 # number of writebacks 59711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::total 1567377 # number of writebacks 59810585SN/Asystem.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 59911201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_requests 24282502 # Total number of requests made to the snoop filter. 60011201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_requests 12366009 # Number of requests hitting in the snoop filter with a single holder of the requested data. 60111138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1399 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 60211201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_snoops 1791227 # Total number of snoops made to the snoop filter. 60311201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1790958 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 60411201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 269 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 60510892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 623009 # Transaction distribution 60610827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 10363944 # Transaction distribution 60710827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 32419 # Transaction distribution 60810827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 32419 # Transaction distribution 60911201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackDirty 4459579 # Transaction distribution 61011201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackClean 7350874 # Transaction distribution 61111201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 139275 # Transaction distribution 61211201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 158509 # Transaction distribution 61311201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 297784 # Transaction distribution 61411138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1344230 # Transaction distribution 61511138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1344230 # Transaction distribution 61610892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 5539598 # Transaction distribution 61710892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 4201337 # Transaction distribution 61811138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateReq 831335 # Transaction distribution 61911138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateResp 831335 # Transaction distribution 62011138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16703618 # Packet count per connected master and slave (bytes) 62111201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19751529 # Packet count per connected master and slave (bytes) 62210726SN/Asystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 366654 # Packet count per connected master and slave (bytes) 62310726SN/Asystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 728076 # Packet count per connected master and slave (bytes) 62411201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count::total 37549877 # Packet count per connected master and slave (bytes) 62511201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 709149780 # Cumulative packet size per connected master and slave (bytes) 62611201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 756535625 # Cumulative packet size per connected master and slave (bytes) 62710726SN/Asystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1466616 # Cumulative packet size per connected master and slave (bytes) 62810726SN/Asystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2912304 # Cumulative packet size per connected master and slave (bytes) 62911201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size::total 1470064325 # Cumulative packet size per connected master and slave (bytes) 63011201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoops 6119333 # Total snoops (count) 63111201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 30615399 # Request fanout histogram 63211201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 0.066982 # Request fanout histogram 63311201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.250025 # Request fanout histogram 63410585SN/Asystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 63511201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 28565001 93.30% 93.30% # Request fanout histogram 63611201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 2050129 6.70% 100.00% # Request fanout histogram 63711201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 269 0.00% 100.00% # Request fanout histogram 63810585SN/Asystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 63911138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 64010827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 64111201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 30615399 # Request fanout histogram 64210628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 64310628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 64410628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 64510628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 64610628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 64710628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 64810628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 64910628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 65010585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 65110585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 65210585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 65310585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 65410585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 65510585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 65610585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 65710585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 65810585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 65910585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 66010585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 66110585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 66210585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 66310585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 66410585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 66510585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 66610585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 66710585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 66810585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 66910585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 67010585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 67110726SN/Asystem.cpu1.dtb.walker.walks 144041 # Table walker walks requested 67210726SN/Asystem.cpu1.dtb.walker.walksLong 144041 # Table walker walks initiated with long descriptors 67310726SN/Asystem.cpu1.dtb.walker.walkWaitTime::samples 144041 # Table walker wait (enqueue to first request) latency 67410726SN/Asystem.cpu1.dtb.walker.walkWaitTime::0 144041 100.00% 100.00% # Table walker wait (enqueue to first request) latency 67510726SN/Asystem.cpu1.dtb.walker.walkWaitTime::total 144041 # Table walker wait (enqueue to first request) latency 67610628SN/Asystem.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution 67710628SN/Asystem.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution 67810628SN/Asystem.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution 67910726SN/Asystem.cpu1.dtb.walker.walkPageSizes::4K 111414 88.97% 88.97% # Table walker page sizes translated 68010726SN/Asystem.cpu1.dtb.walker.walkPageSizes::2M 13807 11.03% 100.00% # Table walker page sizes translated 68110726SN/Asystem.cpu1.dtb.walker.walkPageSizes::total 125221 # Table walker page sizes translated 68210726SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144041 # Table walker requests started/completed, data/inst 68310628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 68410726SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144041 # Table walker requests started/completed, data/inst 68510726SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 125221 # Table walker requests started/completed, data/inst 68610628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 68710726SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 125221 # Table walker requests started/completed, data/inst 68810726SN/Asystem.cpu1.dtb.walker.walkRequestOrigin::total 269262 # Table walker requests started/completed, data/inst 68910585SN/Asystem.cpu1.dtb.inst_hits 0 # ITB inst hits 69010585SN/Asystem.cpu1.dtb.inst_misses 0 # ITB inst misses 69110726SN/Asystem.cpu1.dtb.read_hits 90153061 # DTB read hits 69210726SN/Asystem.cpu1.dtb.read_misses 111753 # DTB read misses 69310726SN/Asystem.cpu1.dtb.write_hits 81132787 # DTB write hits 69410726SN/Asystem.cpu1.dtb.write_misses 32288 # DTB write misses 69510585SN/Asystem.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed 69610585SN/Asystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 69710726SN/Asystem.cpu1.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID 69810585SN/Asystem.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 69910726SN/Asystem.cpu1.dtb.flush_entries 44587 # Number of entries that have been flushed from TLB 70010585SN/Asystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 70110726SN/Asystem.cpu1.dtb.prefetch_faults 4554 # Number of TLB faults due to prefetch 70210585SN/Asystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 70310726SN/Asystem.cpu1.dtb.perms_faults 11374 # Number of TLB faults due to permissions restrictions 70410726SN/Asystem.cpu1.dtb.read_accesses 90264814 # DTB read accesses 70510726SN/Asystem.cpu1.dtb.write_accesses 81165075 # DTB write accesses 70610585SN/Asystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 70710726SN/Asystem.cpu1.dtb.hits 171285848 # DTB hits 70810726SN/Asystem.cpu1.dtb.misses 144041 # DTB misses 70910726SN/Asystem.cpu1.dtb.accesses 171429889 # DTB accesses 71010628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 71110628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 71210628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 71310628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 71410628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 71510628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 71610628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 71710628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 71810585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 71910585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 72010585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 72110585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 72210585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 72310585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 72410585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 72510585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 72610585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 72710585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 72810585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 72910585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 73010585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 73110585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 73210585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 73310585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 73410585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 73510585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 73610585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 73710585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 73810585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 73910726SN/Asystem.cpu1.itb.walker.walks 60885 # Table walker walks requested 74010726SN/Asystem.cpu1.itb.walker.walksLong 60885 # Table walker walks initiated with long descriptors 74110726SN/Asystem.cpu1.itb.walker.walkWaitTime::samples 60885 # Table walker wait (enqueue to first request) latency 74210726SN/Asystem.cpu1.itb.walker.walkWaitTime::0 60885 100.00% 100.00% # Table walker wait (enqueue to first request) latency 74310726SN/Asystem.cpu1.itb.walker.walkWaitTime::total 60885 # Table walker wait (enqueue to first request) latency 74410628SN/Asystem.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution 74510628SN/Asystem.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution 74610628SN/Asystem.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution 74710726SN/Asystem.cpu1.itb.walker.walkPageSizes::4K 53790 99.07% 99.07% # Table walker page sizes translated 74810726SN/Asystem.cpu1.itb.walker.walkPageSizes::2M 505 0.93% 100.00% # Table walker page sizes translated 74910726SN/Asystem.cpu1.itb.walker.walkPageSizes::total 54295 # Table walker page sizes translated 75010628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 75110726SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60885 # Table walker requests started/completed, data/inst 75210726SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 60885 # Table walker requests started/completed, data/inst 75310628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 75410726SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 54295 # Table walker requests started/completed, data/inst 75510726SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 54295 # Table walker requests started/completed, data/inst 75610726SN/Asystem.cpu1.itb.walker.walkRequestOrigin::total 115180 # Table walker requests started/completed, data/inst 75710726SN/Asystem.cpu1.itb.inst_hits 478248118 # ITB inst hits 75810726SN/Asystem.cpu1.itb.inst_misses 60885 # ITB inst misses 75910585SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 76010585SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 76110585SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 76210585SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 76310585SN/Asystem.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed 76410585SN/Asystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 76510726SN/Asystem.cpu1.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID 76610585SN/Asystem.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 76710726SN/Asystem.cpu1.itb.flush_entries 31530 # Number of entries that have been flushed from TLB 76810585SN/Asystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 76910585SN/Asystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 77010585SN/Asystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 77110585SN/Asystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 77210585SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 77310585SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 77410726SN/Asystem.cpu1.itb.inst_accesses 478309003 # ITB inst accesses 77510726SN/Asystem.cpu1.itb.hits 478248118 # DTB hits 77610726SN/Asystem.cpu1.itb.misses 60885 # DTB misses 77710726SN/Asystem.cpu1.itb.accesses 478309003 # DTB accesses 77811167Sjthestness@gmail.comsystem.cpu1.numCycles 94433634550 # number of cpu cycles simulated 77910585SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 78010585SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 78111167Sjthestness@gmail.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 78211167Sjthestness@gmail.comsystem.cpu1.kern.inst.quiesce 6259 # number of quiesce instructions executed 78310726SN/Asystem.cpu1.committedInsts 477990846 # Number of instructions committed 78410726SN/Asystem.cpu1.committedOps 562567642 # Number of ops (including micro ops) committed 78510726SN/Asystem.cpu1.num_int_alu_accesses 516282159 # Number of integer alu accesses 78610726SN/Asystem.cpu1.num_fp_alu_accesses 374678 # Number of float alu accesses 78710726SN/Asystem.cpu1.num_func_calls 28237407 # number of times a function call or return occured 78810726SN/Asystem.cpu1.num_conditional_control_insts 73185792 # number of instructions that are conditional controls 78910726SN/Asystem.cpu1.num_int_insts 516282159 # number of integer instructions 79010726SN/Asystem.cpu1.num_fp_insts 374678 # number of float instructions 79110726SN/Asystem.cpu1.num_int_register_reads 763231058 # number of times the integer registers were read 79210726SN/Asystem.cpu1.num_int_register_writes 411079626 # number of times the integer registers were written 79310726SN/Asystem.cpu1.num_fp_register_reads 608455 # number of times the floating registers were read 79410726SN/Asystem.cpu1.num_fp_register_writes 306456 # number of times the floating registers were written 79510726SN/Asystem.cpu1.num_cc_register_reads 126379788 # number of times the CC registers were read 79610726SN/Asystem.cpu1.num_cc_register_writes 126112608 # number of times the CC registers were written 79710726SN/Asystem.cpu1.num_mem_refs 171406825 # number of memory refs 79810726SN/Asystem.cpu1.num_load_insts 90251973 # Number of load instructions 79910726SN/Asystem.cpu1.num_store_insts 81154852 # Number of store instructions 80011167Sjthestness@gmail.comsystem.cpu1.num_idle_cycles 93870750285.000458 # Number of idle cycles 80111167Sjthestness@gmail.comsystem.cpu1.num_busy_cycles 562884264.999552 # Number of busy cycles 80210726SN/Asystem.cpu1.not_idle_fraction 0.005961 # Percentage of non-idle cycles 80310726SN/Asystem.cpu1.idle_fraction 0.994039 # Percentage of idle cycles 80410726SN/Asystem.cpu1.Branches 106497601 # Number of branches fetched 80510585SN/Asystem.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 80610726SN/Asystem.cpu1.op_class::IntAlu 390236864 69.33% 69.33% # Class of executed instruction 80710726SN/Asystem.cpu1.op_class::IntMult 1137629 0.20% 69.53% # Class of executed instruction 80810726SN/Asystem.cpu1.op_class::IntDiv 60962 0.01% 69.54% # Class of executed instruction 80910726SN/Asystem.cpu1.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction 81010726SN/Asystem.cpu1.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction 81110726SN/Asystem.cpu1.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction 81210726SN/Asystem.cpu1.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction 81310726SN/Asystem.cpu1.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction 81410726SN/Asystem.cpu1.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction 81510726SN/Asystem.cpu1.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction 81610726SN/Asystem.cpu1.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction 81710726SN/Asystem.cpu1.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction 81810726SN/Asystem.cpu1.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction 81910726SN/Asystem.cpu1.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction 82010726SN/Asystem.cpu1.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction 82110726SN/Asystem.cpu1.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction 82210726SN/Asystem.cpu1.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction 82310726SN/Asystem.cpu1.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction 82410726SN/Asystem.cpu1.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction 82510726SN/Asystem.cpu1.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction 82610726SN/Asystem.cpu1.op_class::SimdFloatAdd 0 0.00% 69.54% # Class of executed instruction 82710726SN/Asystem.cpu1.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction 82810726SN/Asystem.cpu1.op_class::SimdFloatCmp 0 0.00% 69.54% # Class of executed instruction 82910726SN/Asystem.cpu1.op_class::SimdFloatCvt 0 0.00% 69.54% # Class of executed instruction 83010726SN/Asystem.cpu1.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction 83110726SN/Asystem.cpu1.op_class::SimdFloatMisc 37059 0.01% 69.55% # Class of executed instruction 83210726SN/Asystem.cpu1.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction 83310726SN/Asystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction 83410726SN/Asystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction 83510726SN/Asystem.cpu1.op_class::MemRead 90251973 16.03% 85.58% # Class of executed instruction 83610726SN/Asystem.cpu1.op_class::MemWrite 81154852 14.42% 100.00% # Class of executed instruction 83710585SN/Asystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 83810585SN/Asystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 83910726SN/Asystem.cpu1.op_class::total 562879339 # Class of executed instruction 84010726SN/Asystem.cpu1.dcache.tags.replacements 5945049 # number of replacements 84110726SN/Asystem.cpu1.dcache.tags.tagsinuse 438.290639 # Cycle average of tags in use 84210726SN/Asystem.cpu1.dcache.tags.total_refs 165346662 # Total number of references to valid blocks. 84310726SN/Asystem.cpu1.dcache.tags.sampled_refs 5945561 # Sample count of references to valid blocks. 84410726SN/Asystem.cpu1.dcache.tags.avg_refs 27.810103 # Average number of references to valid blocks. 84510585SN/Asystem.cpu1.dcache.tags.warmup_cycle 8470277778500 # Cycle when the warmup percentage was hit. 84610726SN/Asystem.cpu1.dcache.tags.occ_blocks::cpu1.data 438.290639 # Average occupied blocks per requestor 84710726SN/Asystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.856036 # Average percentage of cache occupancy 84810726SN/Asystem.cpu1.dcache.tags.occ_percent::total 0.856036 # Average percentage of cache occupancy 84910726SN/Asystem.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 85010726SN/Asystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id 85110726SN/Asystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id 85210726SN/Asystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id 85310726SN/Asystem.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 85410726SN/Asystem.cpu1.dcache.tags.tag_accesses 348813711 # Number of tag accesses 85510726SN/Asystem.cpu1.dcache.tags.data_accesses 348813711 # Number of data accesses 85610726SN/Asystem.cpu1.dcache.ReadReq_hits::cpu1.data 83697564 # number of ReadReq hits 85710726SN/Asystem.cpu1.dcache.ReadReq_hits::total 83697564 # number of ReadReq hits 85811201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 76981821 # number of WriteReq hits 85911201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 76981821 # number of WriteReq hits 86010726SN/Asystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 187854 # number of SoftPFReq hits 86110726SN/Asystem.cpu1.dcache.SoftPFReq_hits::total 187854 # number of SoftPFReq hits 86211201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::cpu1.data 63451 # number of WriteLineReq hits 86311201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::total 63451 # number of WriteLineReq hits 86410726SN/Asystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2062256 # number of LoadLockedReq hits 86510726SN/Asystem.cpu1.dcache.LoadLockedReq_hits::total 2062256 # number of LoadLockedReq hits 86611201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 2048602 # number of StoreCondReq hits 86711201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 2048602 # number of StoreCondReq hits 86811201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 160679385 # number of demand (read+write) hits 86911201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 160679385 # number of demand (read+write) hits 87011201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 160867239 # number of overall hits 87111201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 160867239 # number of overall hits 87210726SN/Asystem.cpu1.dcache.ReadReq_misses::cpu1.data 3358222 # number of ReadReq misses 87310726SN/Asystem.cpu1.dcache.ReadReq_misses::total 3358222 # number of ReadReq misses 87411201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 1461655 # number of WriteReq misses 87511201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 1461655 # number of WriteReq misses 87610726SN/Asystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 792351 # number of SoftPFReq misses 87710726SN/Asystem.cpu1.dcache.SoftPFReq_misses::total 792351 # number of SoftPFReq misses 87811201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::cpu1.data 427048 # number of WriteLineReq misses 87911201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::total 427048 # number of WriteLineReq misses 88010726SN/Asystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 146820 # number of LoadLockedReq misses 88110726SN/Asystem.cpu1.dcache.LoadLockedReq_misses::total 146820 # number of LoadLockedReq misses 88211201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 159147 # number of StoreCondReq misses 88311201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 159147 # number of StoreCondReq misses 88411201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 4819877 # number of demand (read+write) misses 88511201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 4819877 # number of demand (read+write) misses 88611201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 5612228 # number of overall misses 88711201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 5612228 # number of overall misses 88810726SN/Asystem.cpu1.dcache.ReadReq_accesses::cpu1.data 87055786 # number of ReadReq accesses(hits+misses) 88910726SN/Asystem.cpu1.dcache.ReadReq_accesses::total 87055786 # number of ReadReq accesses(hits+misses) 89010726SN/Asystem.cpu1.dcache.WriteReq_accesses::cpu1.data 78443476 # number of WriteReq accesses(hits+misses) 89110726SN/Asystem.cpu1.dcache.WriteReq_accesses::total 78443476 # number of WriteReq accesses(hits+misses) 89210726SN/Asystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 980205 # number of SoftPFReq accesses(hits+misses) 89310726SN/Asystem.cpu1.dcache.SoftPFReq_accesses::total 980205 # number of SoftPFReq accesses(hits+misses) 89410892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::cpu1.data 490499 # number of WriteLineReq accesses(hits+misses) 89510892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::total 490499 # number of WriteLineReq accesses(hits+misses) 89610726SN/Asystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2209076 # number of LoadLockedReq accesses(hits+misses) 89710726SN/Asystem.cpu1.dcache.LoadLockedReq_accesses::total 2209076 # number of LoadLockedReq accesses(hits+misses) 89810726SN/Asystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2207749 # number of StoreCondReq accesses(hits+misses) 89910726SN/Asystem.cpu1.dcache.StoreCondReq_accesses::total 2207749 # number of StoreCondReq accesses(hits+misses) 90010726SN/Asystem.cpu1.dcache.demand_accesses::cpu1.data 165499262 # number of demand (read+write) accesses 90110726SN/Asystem.cpu1.dcache.demand_accesses::total 165499262 # number of demand (read+write) accesses 90210726SN/Asystem.cpu1.dcache.overall_accesses::cpu1.data 166479467 # number of overall (read+write) accesses 90310726SN/Asystem.cpu1.dcache.overall_accesses::total 166479467 # number of overall (read+write) accesses 90410726SN/Asystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038576 # miss rate for ReadReq accesses 90510726SN/Asystem.cpu1.dcache.ReadReq_miss_rate::total 0.038576 # miss rate for ReadReq accesses 90611201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018633 # miss rate for WriteReq accesses 90711201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.018633 # miss rate for WriteReq accesses 90810726SN/Asystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808352 # miss rate for SoftPFReq accesses 90910726SN/Asystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.808352 # miss rate for SoftPFReq accesses 91011201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870640 # miss rate for WriteLineReq accesses 91111201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::total 0.870640 # miss rate for WriteLineReq accesses 91210726SN/Asystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066462 # miss rate for LoadLockedReq accesses 91310726SN/Asystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066462 # miss rate for LoadLockedReq accesses 91411201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.072086 # miss rate for StoreCondReq accesses 91511201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.072086 # miss rate for StoreCondReq accesses 91611201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.029123 # miss rate for demand accesses 91711201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.029123 # miss rate for demand accesses 91811201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.033711 # miss rate for overall accesses 91911201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.033711 # miss rate for overall accesses 92010585SN/Asystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 92110585SN/Asystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 92210585SN/Asystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 92310585SN/Asystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 92410585SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 92510585SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 92610585SN/Asystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 92710585SN/Asystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 92811201Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 5945049 # number of writebacks 92911201Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 5945049 # number of writebacks 93010585SN/Asystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 93110726SN/Asystem.cpu1.icache.tags.replacements 4741297 # number of replacements 93210726SN/Asystem.cpu1.icache.tags.tagsinuse 496.426080 # Cycle average of tags in use 93310726SN/Asystem.cpu1.icache.tags.total_refs 473560604 # Total number of references to valid blocks. 93410726SN/Asystem.cpu1.icache.tags.sampled_refs 4741809 # Sample count of references to valid blocks. 93510726SN/Asystem.cpu1.icache.tags.avg_refs 99.869186 # Average number of references to valid blocks. 93610585SN/Asystem.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit. 93710726SN/Asystem.cpu1.icache.tags.occ_blocks::cpu1.inst 496.426080 # Average occupied blocks per requestor 93810726SN/Asystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.969582 # Average percentage of cache occupancy 93910726SN/Asystem.cpu1.icache.tags.occ_percent::total 0.969582 # Average percentage of cache occupancy 94010585SN/Asystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 94110585SN/Asystem.cpu1.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 94210585SN/Asystem.cpu1.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id 94310585SN/Asystem.cpu1.icache.tags.age_task_id_blocks_1024::2 144 # Occupied blocks per task id 94410585SN/Asystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 94510726SN/Asystem.cpu1.icache.tags.tag_accesses 961346635 # Number of tag accesses 94610726SN/Asystem.cpu1.icache.tags.data_accesses 961346635 # Number of data accesses 94710726SN/Asystem.cpu1.icache.ReadReq_hits::cpu1.inst 473560604 # number of ReadReq hits 94810726SN/Asystem.cpu1.icache.ReadReq_hits::total 473560604 # number of ReadReq hits 94910726SN/Asystem.cpu1.icache.demand_hits::cpu1.inst 473560604 # number of demand (read+write) hits 95010726SN/Asystem.cpu1.icache.demand_hits::total 473560604 # number of demand (read+write) hits 95110726SN/Asystem.cpu1.icache.overall_hits::cpu1.inst 473560604 # number of overall hits 95210726SN/Asystem.cpu1.icache.overall_hits::total 473560604 # number of overall hits 95310726SN/Asystem.cpu1.icache.ReadReq_misses::cpu1.inst 4741809 # number of ReadReq misses 95410726SN/Asystem.cpu1.icache.ReadReq_misses::total 4741809 # number of ReadReq misses 95510726SN/Asystem.cpu1.icache.demand_misses::cpu1.inst 4741809 # number of demand (read+write) misses 95610726SN/Asystem.cpu1.icache.demand_misses::total 4741809 # number of demand (read+write) misses 95710726SN/Asystem.cpu1.icache.overall_misses::cpu1.inst 4741809 # number of overall misses 95810726SN/Asystem.cpu1.icache.overall_misses::total 4741809 # number of overall misses 95910726SN/Asystem.cpu1.icache.ReadReq_accesses::cpu1.inst 478302413 # number of ReadReq accesses(hits+misses) 96010726SN/Asystem.cpu1.icache.ReadReq_accesses::total 478302413 # number of ReadReq accesses(hits+misses) 96110726SN/Asystem.cpu1.icache.demand_accesses::cpu1.inst 478302413 # number of demand (read+write) accesses 96210726SN/Asystem.cpu1.icache.demand_accesses::total 478302413 # number of demand (read+write) accesses 96310726SN/Asystem.cpu1.icache.overall_accesses::cpu1.inst 478302413 # number of overall (read+write) accesses 96410726SN/Asystem.cpu1.icache.overall_accesses::total 478302413 # number of overall (read+write) accesses 96510726SN/Asystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009914 # miss rate for ReadReq accesses 96610726SN/Asystem.cpu1.icache.ReadReq_miss_rate::total 0.009914 # miss rate for ReadReq accesses 96710726SN/Asystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.009914 # miss rate for demand accesses 96810726SN/Asystem.cpu1.icache.demand_miss_rate::total 0.009914 # miss rate for demand accesses 96910726SN/Asystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.009914 # miss rate for overall accesses 97010726SN/Asystem.cpu1.icache.overall_miss_rate::total 0.009914 # miss rate for overall accesses 97110585SN/Asystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 97210585SN/Asystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 97310585SN/Asystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 97410585SN/Asystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 97510585SN/Asystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 97610585SN/Asystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 97710585SN/Asystem.cpu1.icache.fast_writes 0 # number of fast writes performed 97810585SN/Asystem.cpu1.icache.cache_copies 0 # number of cache copies performed 97911201Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::writebacks 4741297 # number of writebacks 98011201Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::total 4741297 # number of writebacks 98110585SN/Asystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 98210628SN/Asystem.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 98310628SN/Asystem.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 98410628SN/Asystem.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 98510628SN/Asystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 98610628SN/Asystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 98710628SN/Asystem.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 98811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.replacements 2235881 # number of replacements 98911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tagsinuse 13334.612647 # Cycle average of tags in use 99011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.total_refs 14249550 # Total number of references to valid blocks. 99111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.sampled_refs 2251891 # Sample count of references to valid blocks. 99211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.avg_refs 6.327815 # Average number of references to valid blocks. 99311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 9713557375000 # Cycle when the warmup percentage was hit. 99411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 13222.980748 # Average occupied blocks per requestor 99511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 46.246601 # Average occupied blocks per requestor 99611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 65.385297 # Average occupied blocks per requestor 99711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.807067 # Average percentage of cache occupancy 99811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002823 # Average percentage of cache occupancy 99911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003991 # Average percentage of cache occupancy 100011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.813880 # Average percentage of cache occupancy 100111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 89 # Occupied blocks per task id 100211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 15921 # Occupied blocks per task id 100311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 56 # Occupied blocks per task id 100411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 14 # Occupied blocks per task id 100511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 19 # Occupied blocks per task id 100611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id 100711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1627 # Occupied blocks per task id 100811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6185 # Occupied blocks per task id 100911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4247 # Occupied blocks per task id 101011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3746 # Occupied blocks per task id 101111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005432 # Percentage of cache occupancy per task id 101211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.971741 # Percentage of cache occupancy per task id 101311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tag_accesses 361919913 # Number of tag accesses 101411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.data_accesses 361919913 # Number of data accesses 101511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 346945 # number of ReadReq hits 101611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 153602 # number of ReadReq hits 101711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 500547 # number of ReadReq hits 101811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::writebacks 4020160 # number of WritebackDirty hits 101911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::total 4020160 # number of WritebackDirty hits 102011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_hits::writebacks 6665818 # number of WritebackClean hits 102111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_hits::total 6665818 # number of WritebackClean hits 102211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1056 # number of UpgradeReq hits 102311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::total 1056 # number of UpgradeReq hits 102411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 614983 # number of ReadExReq hits 102511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 614983 # number of ReadExReq hits 102611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4283593 # number of ReadCleanReq hits 102711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 4283593 # number of ReadCleanReq hits 102811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3077520 # number of ReadSharedReq hits 102911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 3077520 # number of ReadSharedReq hits 103011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::cpu1.data 161463 # number of InvalidateReq hits 103111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::total 161463 # number of InvalidateReq hits 103211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 346945 # number of demand (read+write) hits 103311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 153602 # number of demand (read+write) hits 103411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 4283593 # number of demand (read+write) hits 103511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 3692503 # number of demand (read+write) hits 103611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::total 8476643 # number of demand (read+write) hits 103711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 346945 # number of overall hits 103811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 153602 # number of overall hits 103911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 4283593 # number of overall hits 104011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 3692503 # number of overall hits 104111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::total 8476643 # number of overall hits 104211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12460 # number of ReadReq misses 104311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9763 # number of ReadReq misses 104411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 22223 # number of ReadReq misses 104511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 144911 # number of UpgradeReq misses 104611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 144911 # number of UpgradeReq misses 104711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 159147 # number of SCUpgradeReq misses 104811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 159147 # number of SCUpgradeReq misses 104911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 700907 # number of ReadExReq misses 105011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 700907 # number of ReadExReq misses 105111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 458216 # number of ReadCleanReq misses 105211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 458216 # number of ReadCleanReq misses 105311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1219873 # number of ReadSharedReq misses 105411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 1219873 # number of ReadSharedReq misses 105511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::cpu1.data 265383 # number of InvalidateReq misses 105611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::total 265383 # number of InvalidateReq misses 105711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12460 # number of demand (read+write) misses 105811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 9763 # number of demand (read+write) misses 105911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 458216 # number of demand (read+write) misses 106011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 1920780 # number of demand (read+write) misses 106111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::total 2401219 # number of demand (read+write) misses 106211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12460 # number of overall misses 106311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 9763 # number of overall misses 106411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 458216 # number of overall misses 106511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 1920780 # number of overall misses 106611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::total 2401219 # number of overall misses 106711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 359405 # number of ReadReq accesses(hits+misses) 106811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 163365 # number of ReadReq accesses(hits+misses) 106911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 522770 # number of ReadReq accesses(hits+misses) 107011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::writebacks 4020160 # number of WritebackDirty accesses(hits+misses) 107111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::total 4020160 # number of WritebackDirty accesses(hits+misses) 107211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::writebacks 6665818 # number of WritebackClean accesses(hits+misses) 107311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::total 6665818 # number of WritebackClean accesses(hits+misses) 107411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 145967 # number of UpgradeReq accesses(hits+misses) 107511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 145967 # number of UpgradeReq accesses(hits+misses) 107611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 159147 # number of SCUpgradeReq accesses(hits+misses) 107711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 159147 # number of SCUpgradeReq accesses(hits+misses) 107810726SN/Asystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1315890 # number of ReadExReq accesses(hits+misses) 107910726SN/Asystem.cpu1.l2cache.ReadExReq_accesses::total 1315890 # number of ReadExReq accesses(hits+misses) 108010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4741809 # number of ReadCleanReq accesses(hits+misses) 108110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 4741809 # number of ReadCleanReq accesses(hits+misses) 108210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4297393 # number of ReadSharedReq accesses(hits+misses) 108310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 4297393 # number of ReadSharedReq accesses(hits+misses) 108410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 426846 # number of InvalidateReq accesses(hits+misses) 108510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::total 426846 # number of InvalidateReq accesses(hits+misses) 108611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 359405 # number of demand (read+write) accesses 108711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 163365 # number of demand (read+write) accesses 108810726SN/Asystem.cpu1.l2cache.demand_accesses::cpu1.inst 4741809 # number of demand (read+write) accesses 108910726SN/Asystem.cpu1.l2cache.demand_accesses::cpu1.data 5613283 # number of demand (read+write) accesses 109011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::total 10877862 # number of demand (read+write) accesses 109111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 359405 # number of overall (read+write) accesses 109211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 163365 # number of overall (read+write) accesses 109310726SN/Asystem.cpu1.l2cache.overall_accesses::cpu1.inst 4741809 # number of overall (read+write) accesses 109410726SN/Asystem.cpu1.l2cache.overall_accesses::cpu1.data 5613283 # number of overall (read+write) accesses 109511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::total 10877862 # number of overall (read+write) accesses 109611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.034668 # miss rate for ReadReq accesses 109711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.059762 # miss rate for ReadReq accesses 109811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.042510 # miss rate for ReadReq accesses 109911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.992765 # miss rate for UpgradeReq accesses 110011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 0.992765 # miss rate for UpgradeReq accesses 110110585SN/Asystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 110210585SN/Asystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 110311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.532649 # miss rate for ReadExReq accesses 110411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.532649 # miss rate for ReadExReq accesses 110511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.096633 # miss rate for ReadCleanReq accesses 110611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.096633 # miss rate for ReadCleanReq accesses 110711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.283863 # miss rate for ReadSharedReq accesses 110811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.283863 # miss rate for ReadSharedReq accesses 110911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.621730 # miss rate for InvalidateReq accesses 111011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::total 0.621730 # miss rate for InvalidateReq accesses 111111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.034668 # miss rate for demand accesses 111211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.059762 # miss rate for demand accesses 111311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.096633 # miss rate for demand accesses 111411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.342185 # miss rate for demand accesses 111511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.220744 # miss rate for demand accesses 111611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.034668 # miss rate for overall accesses 111711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.059762 # miss rate for overall accesses 111811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.096633 # miss rate for overall accesses 111911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.342185 # miss rate for overall accesses 112011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.220744 # miss rate for overall accesses 112110585SN/Asystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 112210585SN/Asystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 112310585SN/Asystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 112410585SN/Asystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 112510585SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 112610585SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 112710585SN/Asystem.cpu1.l2cache.fast_writes 0 # number of fast writes performed 112810585SN/Asystem.cpu1.l2cache.cache_copies 0 # number of cache copies performed 112911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::writebacks 1179503 # number of writebacks 113011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::total 1179503 # number of writebacks 113110585SN/Asystem.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 113211201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_requests 22049015 # Total number of requests made to the snoop filter. 113311201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_requests 11267078 # Number of requests hitting in the snoop filter with a single holder of the requested data. 113411138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_requests 368 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 113511201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_snoops 1760820 # Total number of snoops made to the snoop filter. 113611201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1760650 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 113711201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 170 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 113810892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 606211 # Transaction distribution 113910726SN/Asystem.cpu1.toL2Bus.trans_dist::ReadResp 9645413 # Transaction distribution 114010726SN/Asystem.cpu1.toL2Bus.trans_dist::WriteReq 6383 # Transaction distribution 114110726SN/Asystem.cpu1.toL2Bus.trans_dist::WriteResp 6383 # Transaction distribution 114211201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackDirty 4020160 # Transaction distribution 114311201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackClean 6665818 # Transaction distribution 114411201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 145967 # Transaction distribution 114511201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 159147 # Transaction distribution 114611201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 305114 # Transaction distribution 114710726SN/Asystem.cpu1.toL2Bus.trans_dist::ReadExReq 1315890 # Transaction distribution 114810726SN/Asystem.cpu1.toL2Bus.trans_dist::ReadExResp 1315890 # Transaction distribution 114910892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 4741809 # Transaction distribution 115010892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 4297393 # Transaction distribution 115110892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateReq 426846 # Transaction distribution 115210892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateResp 426846 # Transaction distribution 115311138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14225112 # Packet count per connected master and slave (bytes) 115411201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18660714 # Packet count per connected master and slave (bytes) 115510726SN/Asystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 364008 # Packet count per connected master and slave (bytes) 115610726SN/Asystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 835436 # Packet count per connected master and slave (bytes) 115711201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count::total 34085270 # Packet count per connected master and slave (bytes) 115811201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 606915272 # Cumulative packet size per connected master and slave (bytes) 115911201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 739752124 # Cumulative packet size per connected master and slave (bytes) 116010726SN/Asystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1456032 # Cumulative packet size per connected master and slave (bytes) 116110726SN/Asystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3341744 # Cumulative packet size per connected master and slave (bytes) 116211201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size::total 1351465172 # Cumulative packet size per connected master and slave (bytes) 116311201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoops 5690396 # Total snoops (count) 116411201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 27910438 # Request fanout histogram 116511201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 0.072996 # Request fanout histogram 116611201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.260153 # Request fanout histogram 116710585SN/Asystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 116811201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 25873264 92.70% 92.70% # Request fanout histogram 116911201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 2037004 7.30% 100.00% # Request fanout histogram 117011201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 170 0.00% 100.00% # Request fanout histogram 117110585SN/Asystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 117211138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 117310827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 117411201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 27910438 # Request fanout histogram 117510726SN/Asystem.iobus.trans_dist::ReadReq 40295 # Transaction distribution 117610726SN/Asystem.iobus.trans_dist::ReadResp 40295 # Transaction distribution 117710726SN/Asystem.iobus.trans_dist::WriteReq 136634 # Transaction distribution 117810892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 136634 # Transaction distribution 117910726SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47636 # Packet count per connected master and slave (bytes) 118010585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 118110585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 118210585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 118310585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 118410585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 118510585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 118610585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 118710585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 118810585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 118910585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 119010585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 119110585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 119210585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 119310585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 119410726SN/Asystem.iobus.pkt_count_system.bridge.master::total 122570 # Packet count per connected master and slave (bytes) 119510726SN/Asystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231208 # Packet count per connected master and slave (bytes) 119610726SN/Asystem.iobus.pkt_count_system.realview.ide.dma::total 231208 # Packet count per connected master and slave (bytes) 119710585SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 119810585SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 119910726SN/Asystem.iobus.pkt_count::total 353858 # Packet count per connected master and slave (bytes) 120010726SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47656 # Cumulative packet size per connected master and slave (bytes) 120110585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 120210585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 120310585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 120410585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 120510585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 120610585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 120710585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 120810585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 120910585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 121010585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 121110585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 121210585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 121310585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 121410585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 121510726SN/Asystem.iobus.pkt_size_system.bridge.master::total 155677 # Cumulative packet size per connected master and slave (bytes) 121610726SN/Asystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338848 # Cumulative packet size per connected master and slave (bytes) 121710726SN/Asystem.iobus.pkt_size_system.realview.ide.dma::total 7338848 # Cumulative packet size per connected master and slave (bytes) 121810585SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 121910585SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 122010726SN/Asystem.iobus.pkt_size::total 7496611 # Cumulative packet size per connected master and slave (bytes) 122110726SN/Asystem.iocache.tags.replacements 115585 # number of replacements 122210726SN/Asystem.iocache.tags.tagsinuse 11.290896 # Cycle average of tags in use 122310585SN/Asystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 122410726SN/Asystem.iocache.tags.sampled_refs 115601 # Sample count of references to valid blocks. 122510585SN/Asystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 122610585SN/Asystem.iocache.tags.warmup_cycle 9107775783009 # Cycle when the warmup percentage was hit. 122710726SN/Asystem.iocache.tags.occ_blocks::realview.ethernet 3.851982 # Average occupied blocks per requestor 122810726SN/Asystem.iocache.tags.occ_blocks::realview.ide 7.438915 # Average occupied blocks per requestor 122910726SN/Asystem.iocache.tags.occ_percent::realview.ethernet 0.240749 # Average percentage of cache occupancy 123010726SN/Asystem.iocache.tags.occ_percent::realview.ide 0.464932 # Average percentage of cache occupancy 123110726SN/Asystem.iocache.tags.occ_percent::total 0.705681 # Average percentage of cache occupancy 123210585SN/Asystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 123310585SN/Asystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 123410585SN/Asystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 123510726SN/Asystem.iocache.tags.tag_accesses 1040793 # Number of tag accesses 123610726SN/Asystem.iocache.tags.data_accesses 1040793 # Number of data accesses 123710585SN/Asystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 123810726SN/Asystem.iocache.ReadReq_misses::realview.ide 8876 # number of ReadReq misses 123910726SN/Asystem.iocache.ReadReq_misses::total 8913 # number of ReadReq misses 124010585SN/Asystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 124110585SN/Asystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 124210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 124310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 124410585SN/Asystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 124510726SN/Asystem.iocache.demand_misses::realview.ide 8876 # number of demand (read+write) misses 124610726SN/Asystem.iocache.demand_misses::total 8916 # number of demand (read+write) misses 124710585SN/Asystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 124810726SN/Asystem.iocache.overall_misses::realview.ide 8876 # number of overall misses 124910726SN/Asystem.iocache.overall_misses::total 8916 # number of overall misses 125010585SN/Asystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 125110726SN/Asystem.iocache.ReadReq_accesses::realview.ide 8876 # number of ReadReq accesses(hits+misses) 125210726SN/Asystem.iocache.ReadReq_accesses::total 8913 # number of ReadReq accesses(hits+misses) 125310585SN/Asystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 125410585SN/Asystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 125510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 125610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 125710585SN/Asystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 125810726SN/Asystem.iocache.demand_accesses::realview.ide 8876 # number of demand (read+write) accesses 125910726SN/Asystem.iocache.demand_accesses::total 8916 # number of demand (read+write) accesses 126010585SN/Asystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 126110726SN/Asystem.iocache.overall_accesses::realview.ide 8876 # number of overall (read+write) accesses 126210726SN/Asystem.iocache.overall_accesses::total 8916 # number of overall (read+write) accesses 126310585SN/Asystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 126410585SN/Asystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 126510585SN/Asystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 126610585SN/Asystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 126710585SN/Asystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 126810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 126910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 127010585SN/Asystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 127110585SN/Asystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 127210585SN/Asystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 127310585SN/Asystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 127410585SN/Asystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 127510585SN/Asystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 127610585SN/Asystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 127710585SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 127810585SN/Asystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 127910585SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 128010585SN/Asystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 128110585SN/Asystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 128210585SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 128310585SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 128410585SN/Asystem.iocache.writebacks::writebacks 106694 # number of writebacks 128510585SN/Asystem.iocache.writebacks::total 106694 # number of writebacks 128610585SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 128711201Sandreas.hansson@arm.comsystem.l2c.tags.replacements 1759418 # number of replacements 128811201Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 62296.253449 # Cycle average of tags in use 128911201Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 4473392 # Total number of references to valid blocks. 129011201Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 1817492 # Sample count of references to valid blocks. 129111201Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 2.461299 # Average number of references to valid blocks. 129210892Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 129311201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 34373.643780 # Average occupied blocks per requestor 129411201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 42.521667 # Average occupied blocks per requestor 129511201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 58.768031 # Average occupied blocks per requestor 129611201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 3224.697109 # Average occupied blocks per requestor 129711201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 7016.159468 # Average occupied blocks per requestor 129811201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 270.222583 # Average occupied blocks per requestor 129911201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 416.861208 # Average occupied blocks per requestor 130011201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 2985.929949 # Average occupied blocks per requestor 130111201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 13907.449654 # Average occupied blocks per requestor 130211201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.524500 # Average percentage of cache occupancy 130311201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.000649 # Average percentage of cache occupancy 130411201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.000897 # Average percentage of cache occupancy 130511201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.049205 # Average percentage of cache occupancy 130611201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.107058 # Average percentage of cache occupancy 130711201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.004123 # Average percentage of cache occupancy 130811201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.006361 # Average percentage of cache occupancy 130911201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.045562 # Average percentage of cache occupancy 131011201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.212211 # Average percentage of cache occupancy 131111201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.950565 # Average percentage of cache occupancy 131211201Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 212 # Occupied blocks per task id 131311201Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 57862 # Occupied blocks per task id 131411201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 212 # Occupied blocks per task id 131511201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id 131611201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 539 # Occupied blocks per task id 131711201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 3515 # Occupied blocks per task id 131811201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 5475 # Occupied blocks per task id 131911201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 48284 # Occupied blocks per task id 132011201Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.003235 # Percentage of cache occupancy per task id 132111201Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.882904 # Percentage of cache occupancy per task id 132211201Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 73042126 # Number of tag accesses 132311201Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 73042126 # Number of data accesses 132411201Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::writebacks 2746880 # number of WritebackDirty hits 132511201Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::total 2746880 # number of WritebackDirty hits 132611201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 14674 # number of UpgradeReq hits 132711201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 12828 # number of UpgradeReq hits 132811201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 27502 # number of UpgradeReq hits 132911201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 1473 # number of SCUpgradeReq hits 133011201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 1269 # number of SCUpgradeReq hits 133111201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 2742 # number of SCUpgradeReq hits 133211201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 316195 # number of ReadExReq hits 133311201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 262623 # number of ReadExReq hits 133411201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 578818 # number of ReadExReq hits 133511201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6348 # number of ReadSharedReq hits 133611201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 4560 # number of ReadSharedReq hits 133711201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 446108 # number of ReadSharedReq hits 133811201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 731335 # number of ReadSharedReq hits 133911201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5573 # number of ReadSharedReq hits 134011201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 3622 # number of ReadSharedReq hits 134111201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 416632 # number of ReadSharedReq hits 134211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 676220 # number of ReadSharedReq hits 134311201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::total 2290398 # number of ReadSharedReq hits 134411201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 6348 # number of demand (read+write) hits 134511201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 4560 # number of demand (read+write) hits 134611201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 446108 # number of demand (read+write) hits 134711201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 1047530 # number of demand (read+write) hits 134811201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 5573 # number of demand (read+write) hits 134911201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 3622 # number of demand (read+write) hits 135011201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 416632 # number of demand (read+write) hits 135111201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 938843 # number of demand (read+write) hits 135211201Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 2869216 # number of demand (read+write) hits 135311201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 6348 # number of overall hits 135411201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 4560 # number of overall hits 135511201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 446108 # number of overall hits 135611201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 1047530 # number of overall hits 135711201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 5573 # number of overall hits 135811201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 3622 # number of overall hits 135911201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 416632 # number of overall hits 136011201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 938843 # number of overall hits 136111201Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 2869216 # number of overall hits 136211201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 68066 # number of UpgradeReq misses 136311201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 63332 # number of UpgradeReq misses 136411201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 131398 # number of UpgradeReq misses 136511201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 7840 # number of SCUpgradeReq misses 136611201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 7476 # number of SCUpgradeReq misses 136711201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 15316 # number of SCUpgradeReq misses 136811201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 815697 # number of ReadExReq misses 136911201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 546954 # number of ReadExReq misses 137011201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 1362651 # number of ReadExReq misses 137111201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2376 # number of ReadSharedReq misses 137211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 1983 # number of ReadSharedReq misses 137311201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 57665 # number of ReadSharedReq misses 137411201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 181479 # number of ReadSharedReq misses 137511201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3468 # number of ReadSharedReq misses 137611201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.itb.walker 3439 # number of ReadSharedReq misses 137711201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 41584 # number of ReadSharedReq misses 137811201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 187193 # number of ReadSharedReq misses 137911201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::total 479187 # number of ReadSharedReq misses 138011201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 2376 # number of demand (read+write) misses 138111201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 1983 # number of demand (read+write) misses 138211201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 57665 # number of demand (read+write) misses 138311201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 997176 # number of demand (read+write) misses 138411201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 3468 # number of demand (read+write) misses 138511201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.itb.walker 3439 # number of demand (read+write) misses 138611201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 41584 # number of demand (read+write) misses 138711201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 734147 # number of demand (read+write) misses 138811201Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 1841838 # number of demand (read+write) misses 138911201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 2376 # number of overall misses 139011201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 1983 # number of overall misses 139111201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 57665 # number of overall misses 139211201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 997176 # number of overall misses 139311201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 3468 # number of overall misses 139411201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.itb.walker 3439 # number of overall misses 139511201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 41584 # number of overall misses 139611201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 734147 # number of overall misses 139711201Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 1841838 # number of overall misses 139811201Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 2746880 # number of WritebackDirty accesses(hits+misses) 139911201Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::total 2746880 # number of WritebackDirty accesses(hits+misses) 140011201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 82740 # number of UpgradeReq accesses(hits+misses) 140111201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 76160 # number of UpgradeReq accesses(hits+misses) 140211201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 158900 # number of UpgradeReq accesses(hits+misses) 140311201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 9313 # number of SCUpgradeReq accesses(hits+misses) 140411201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 8745 # number of SCUpgradeReq accesses(hits+misses) 140511201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 18058 # number of SCUpgradeReq accesses(hits+misses) 140611201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 1131892 # number of ReadExReq accesses(hits+misses) 140711201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 809577 # number of ReadExReq accesses(hits+misses) 140811201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 1941469 # number of ReadExReq accesses(hits+misses) 140911201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8724 # number of ReadSharedReq accesses(hits+misses) 141011201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6543 # number of ReadSharedReq accesses(hits+misses) 141111201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 503773 # number of ReadSharedReq accesses(hits+misses) 141211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 912814 # number of ReadSharedReq accesses(hits+misses) 141311201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 9041 # number of ReadSharedReq accesses(hits+misses) 141411201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7061 # number of ReadSharedReq accesses(hits+misses) 141511201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 458216 # number of ReadSharedReq accesses(hits+misses) 141611201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 863413 # number of ReadSharedReq accesses(hits+misses) 141711201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::total 2769585 # number of ReadSharedReq accesses(hits+misses) 141811201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 8724 # number of demand (read+write) accesses 141911201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 6543 # number of demand (read+write) accesses 142011201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 503773 # number of demand (read+write) accesses 142111201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 2044706 # number of demand (read+write) accesses 142211201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 9041 # number of demand (read+write) accesses 142311201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 7061 # number of demand (read+write) accesses 142411201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 458216 # number of demand (read+write) accesses 142511201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 1672990 # number of demand (read+write) accesses 142611201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 4711054 # number of demand (read+write) accesses 142711201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 8724 # number of overall (read+write) accesses 142811201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 6543 # number of overall (read+write) accesses 142911201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 503773 # number of overall (read+write) accesses 143011201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 2044706 # number of overall (read+write) accesses 143111201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 9041 # number of overall (read+write) accesses 143211201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 7061 # number of overall (read+write) accesses 143311201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 458216 # number of overall (read+write) accesses 143411201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 1672990 # number of overall (read+write) accesses 143511201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 4711054 # number of overall (read+write) accesses 143611201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.822649 # miss rate for UpgradeReq accesses 143711201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.831565 # miss rate for UpgradeReq accesses 143811201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.826923 # miss rate for UpgradeReq accesses 143911201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.841834 # miss rate for SCUpgradeReq accesses 144011201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.854889 # miss rate for SCUpgradeReq accesses 144111201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.848156 # miss rate for SCUpgradeReq accesses 144211201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.720649 # miss rate for ReadExReq accesses 144311201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.675605 # miss rate for ReadExReq accesses 144411201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.701866 # miss rate for ReadExReq accesses 144511201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.272352 # miss rate for ReadSharedReq accesses 144611201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.303072 # miss rate for ReadSharedReq accesses 144711201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.114466 # miss rate for ReadSharedReq accesses 144811201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.198813 # miss rate for ReadSharedReq accesses 144911201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.383586 # miss rate for ReadSharedReq accesses 145011201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.487041 # miss rate for ReadSharedReq accesses 145111201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.090752 # miss rate for ReadSharedReq accesses 145211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.216806 # miss rate for ReadSharedReq accesses 145311201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.173018 # miss rate for ReadSharedReq accesses 145411201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.272352 # miss rate for demand accesses 145511201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.303072 # miss rate for demand accesses 145611201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.114466 # miss rate for demand accesses 145711201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.487687 # miss rate for demand accesses 145811201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.383586 # miss rate for demand accesses 145911201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.487041 # miss rate for demand accesses 146011201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.090752 # miss rate for demand accesses 146111201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.438823 # miss rate for demand accesses 146211201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.390961 # miss rate for demand accesses 146311201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.272352 # miss rate for overall accesses 146411201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.303072 # miss rate for overall accesses 146511201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.114466 # miss rate for overall accesses 146611201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.487687 # miss rate for overall accesses 146711201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.383586 # miss rate for overall accesses 146811201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.487041 # miss rate for overall accesses 146911201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.090752 # miss rate for overall accesses 147011201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.438823 # miss rate for overall accesses 147111201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.390961 # miss rate for overall accesses 147210515SN/Asystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 147310515SN/Asystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 147410515SN/Asystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 147510515SN/Asystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 147610515SN/Asystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 147710515SN/Asystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 147810515SN/Asystem.l2c.fast_writes 0 # number of fast writes performed 147910515SN/Asystem.l2c.cache_copies 0 # number of cache copies performed 148011201Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 1470290 # number of writebacks 148111201Sandreas.hansson@arm.comsystem.l2c.writebacks::total 1470290 # number of writebacks 148210515SN/Asystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 148310892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 82131 # Transaction distribution 148411201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 570231 # Transaction distribution 148510827Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 38802 # Transaction distribution 148610827Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 38802 # Transaction distribution 148711201Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty 1576984 # Transaction distribution 148811201Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 244820 # Transaction distribution 148911201Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 347427 # Transaction distribution 149011201Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 314914 # Transaction distribution 149111201Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 168909 # Transaction distribution 149211201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 1611622 # Transaction distribution 149311201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 1340459 # Transaction distribution 149411201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 488100 # Transaction distribution 149510892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 106728 # Transaction distribution 149610892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 106728 # Transaction distribution 149710726SN/Asystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122570 # Packet count per connected master and slave (bytes) 149810585SN/Asystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 149910726SN/Asystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27558 # Packet count per connected master and slave (bytes) 150011201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6542117 # Packet count per connected master and slave (bytes) 150111201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 6692337 # Packet count per connected master and slave (bytes) 150211201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 344320 # Packet count per connected master and slave (bytes) 150311201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 344320 # Packet count per connected master and slave (bytes) 150411201Sandreas.hansson@arm.comsystem.membus.pkt_count::total 7036657 # Packet count per connected master and slave (bytes) 150510726SN/Asystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155677 # Cumulative packet size per connected master and slave (bytes) 150610585SN/Asystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 150710726SN/Asystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55116 # Cumulative packet size per connected master and slave (bytes) 150811201Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 210749660 # Cumulative packet size per connected master and slave (bytes) 150911201Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 210960657 # Cumulative packet size per connected master and slave (bytes) 151010892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7398848 # Cumulative packet size per connected master and slave (bytes) 151110892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7398848 # Cumulative packet size per connected master and slave (bytes) 151211201Sandreas.hansson@arm.comsystem.membus.pkt_size::total 218359505 # Cumulative packet size per connected master and slave (bytes) 151310585SN/Asystem.membus.snoops 0 # Total snoops (count) 151411201Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 4814081 # Request fanout histogram 151510585SN/Asystem.membus.snoop_fanout::mean 1 # Request fanout histogram 151610585SN/Asystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 151710585SN/Asystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 151810585SN/Asystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 151911201Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 4814081 100.00% 100.00% # Request fanout histogram 152010585SN/Asystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 152110585SN/Asystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 152210585SN/Asystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 152310585SN/Asystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 152411201Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 4814081 # Request fanout histogram 152511239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 152611239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 152711239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 152811239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 152911239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 153011239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 153110515SN/Asystem.realview.ethernet.txBytes 966 # Bytes Transmitted 153210515SN/Asystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 153310515SN/Asystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 153410515SN/Asystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 153510515SN/Asystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 153610515SN/Asystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 153710515SN/Asystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 153810515SN/Asystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 153910515SN/Asystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 154010515SN/Asystem.realview.ethernet.totBandwidth 164 # Total Bandwidth (bits/s) 154110515SN/Asystem.realview.ethernet.totPackets 3 # Total Packets 154210515SN/Asystem.realview.ethernet.totBytes 966 # Total Bytes 154310515SN/Asystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 154410515SN/Asystem.realview.ethernet.txBandwidth 164 # Transmit Bandwidth (bits/s) 154510515SN/Asystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 154610515SN/Asystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 154710515SN/Asystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 154810515SN/Asystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 154910515SN/Asystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 155010515SN/Asystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 155110515SN/Asystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 155210515SN/Asystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 155310515SN/Asystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 155410515SN/Asystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 155510515SN/Asystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 155610515SN/Asystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 155710515SN/Asystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 155810515SN/Asystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 155910515SN/Asystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 156010515SN/Asystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 156110515SN/Asystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 156210515SN/Asystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 156310515SN/Asystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 156410515SN/Asystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 156510515SN/Asystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 156610515SN/Asystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 156710515SN/Asystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 156810515SN/Asystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 156910515SN/Asystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 157010515SN/Asystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 157110515SN/Asystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 157210515SN/Asystem.realview.ethernet.droppedPackets 0 # number of packets dropped 157311239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 157411239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 157511239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 157611239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 157711201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_requests 11103531 # Total number of requests made to the snoop filter. 157811201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 5720804 # Number of requests hitting in the snoop filter with a single holder of the requested data. 157911201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 1657088 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 158011201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 128474 # Total number of snoops made to the snoop filter. 158111201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 115294 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 158211201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 13180 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 158310892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 82133 # Transaction distribution 158411201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 3545235 # Transaction distribution 158510827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 38802 # Transaction distribution 158610827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 38802 # Transaction distribution 158711201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 2746880 # Transaction distribution 158811201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::CleanEvict 1000532 # Transaction distribution 158911201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 352734 # Transaction distribution 159011201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 317656 # Transaction distribution 159111201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 670390 # Transaction distribution 159211201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 2212632 # Transaction distribution 159311201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 2212632 # Transaction distribution 159411201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 3463102 # Transaction distribution 159511201Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9045879 # Packet count per connected master and slave (bytes) 159611201Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7635651 # Packet count per connected master and slave (bytes) 159711201Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 16681530 # Packet count per connected master and slave (bytes) 159811201Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 295373981 # Cumulative packet size per connected master and slave (bytes) 159911201Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 244078084 # Cumulative packet size per connected master and slave (bytes) 160011201Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 539452065 # Cumulative packet size per connected master and slave (bytes) 160111201Sandreas.hansson@arm.comsystem.toL2Bus.snoops 1992317 # Total snoops (count) 160211201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 13215112 # Request fanout histogram 160311201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 0.283607 # Request fanout histogram 160411201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.452956 # Request fanout histogram 160510515SN/Asystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 160611201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::0 9480390 71.74% 71.74% # Request fanout histogram 160711201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 3721542 28.16% 99.90% # Request fanout histogram 160811201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 13180 0.10% 100.00% # Request fanout histogram 160910515SN/Asystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 161011138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 161110515SN/Asystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 161211201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 13215112 # Request fanout histogram 161310515SN/A 161410515SN/A---------- End Simulation Statistics ---------- 1615