stats.txt revision 11138
110515SN/A 210515SN/A---------- Begin Simulation Statistics ---------- 310726SN/Asim_seconds 47.216814 # Number of seconds simulated 410726SN/Asim_ticks 47216814145000 # Number of ticks simulated 510726SN/Afinal_tick 47216814145000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711138Sandreas.hansson@arm.comhost_inst_rate 1096625 # Simulator instruction rate (inst/s) 811138Sandreas.hansson@arm.comhost_op_rate 1290081 # Simulator op (including micro ops) rate (op/s) 911138Sandreas.hansson@arm.comhost_tick_rate 53081906922 # Simulator tick rate (ticks/s) 1011138Sandreas.hansson@arm.comhost_mem_usage 734248 # Number of bytes of host memory used 1111138Sandreas.hansson@arm.comhost_seconds 889.51 # Real time elapsed on the host 1210726SN/Asim_insts 975457230 # Number of instructions simulated 1310726SN/Asim_ops 1147538415 # Number of ops (including micro ops) simulated 1410515SN/Asystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SN/Asystem.clk_domain.clock 1000 # Clock period in ticks 1611138Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 152640 # Number of bytes read from this memory 1711138Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 127168 # Number of bytes read from this memory 1811138Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 3766772 # Number of bytes read from this memory 1911138Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 62976200 # Number of bytes read from this memory 2011138Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 221312 # Number of bytes read from this memory 2111138Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.itb.walker 220864 # Number of bytes read from this memory 2211138Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 2509128 # Number of bytes read from this memory 2311138Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 46395632 # Number of bytes read from this memory 2411138Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 419264 # Number of bytes read from this memory 2511138Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 116788980 # Number of bytes read from this memory 2611138Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 3766772 # Number of instructions bytes read from this memory 2711138Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 2509128 # Number of instructions bytes read from this memory 2811138Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 6275900 # Number of instructions bytes read from this memory 2911138Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 100984448 # Number of bytes written to this memory 3010827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 3110585SN/Asystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3211138Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 101005032 # Number of bytes written to this memory 3311138Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 2385 # Number of read requests responded to by this memory 3411138Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.itb.walker 1987 # Number of read requests responded to by this memory 3511138Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 99263 # Number of read requests responded to by this memory 3611138Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 984016 # Number of read requests responded to by this memory 3711138Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 3458 # Number of read requests responded to by this memory 3811138Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.itb.walker 3451 # Number of read requests responded to by this memory 3911138Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 39312 # Number of read requests responded to by this memory 4011138Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 724948 # Number of read requests responded to by this memory 4111138Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 6551 # Number of read requests responded to by this memory 4211138Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1865371 # Number of read requests responded to by this memory 4311138Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 1577882 # Number of write requests responded to by this memory 4410827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 4510585SN/Asystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 4611138Sandreas.hansson@arm.comsystem.physmem.num_writes::total 1580456 # Number of write requests responded to by this memory 4711138Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 3233 # Total read bandwidth from this memory (bytes/s) 4811138Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.itb.walker 2693 # Total read bandwidth from this memory (bytes/s) 4911138Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 79776 # Total read bandwidth from this memory (bytes/s) 5011138Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 1333766 # Total read bandwidth from this memory (bytes/s) 5111138Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 4687 # Total read bandwidth from this memory (bytes/s) 5211138Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.itb.walker 4678 # Total read bandwidth from this memory (bytes/s) 5311138Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 53141 # Total read bandwidth from this memory (bytes/s) 5411138Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 982608 # Total read bandwidth from this memory (bytes/s) 5511138Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 8880 # Total read bandwidth from this memory (bytes/s) 5611138Sandreas.hansson@arm.comsystem.physmem.bw_read::total 2473462 # Total read bandwidth from this memory (bytes/s) 5711138Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 79776 # Instruction read bandwidth from this memory (bytes/s) 5811138Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 53141 # Instruction read bandwidth from this memory (bytes/s) 5911138Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 132917 # Instruction read bandwidth from this memory (bytes/s) 6011138Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 2138739 # Write bandwidth from this memory (bytes/s) 6110827Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu0.data 436 # Write bandwidth from this memory (bytes/s) 6210585SN/Asystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 6311138Sandreas.hansson@arm.comsystem.physmem.bw_write::total 2139175 # Write bandwidth from this memory (bytes/s) 6411138Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 2138739 # Total bandwidth to/from this memory (bytes/s) 6511138Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 3233 # Total bandwidth to/from this memory (bytes/s) 6611138Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.itb.walker 2693 # Total bandwidth to/from this memory (bytes/s) 6711138Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 79776 # Total bandwidth to/from this memory (bytes/s) 6811138Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 1334202 # Total bandwidth to/from this memory (bytes/s) 6911138Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 4687 # Total bandwidth to/from this memory (bytes/s) 7011138Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.itb.walker 4678 # Total bandwidth to/from this memory (bytes/s) 7111138Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 53141 # Total bandwidth to/from this memory (bytes/s) 7211138Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 982608 # Total bandwidth to/from this memory (bytes/s) 7311138Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 8880 # Total bandwidth to/from this memory (bytes/s) 7411138Sandreas.hansson@arm.comsystem.physmem.bw_total::total 4612637 # Total bandwidth to/from this memory (bytes/s) 7510515SN/Asystem.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 7610515SN/Asystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 7710515SN/Asystem.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 7810515SN/Asystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 7910515SN/Asystem.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 8010515SN/Asystem.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 8110515SN/Asystem.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 8210515SN/Asystem.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 8310515SN/Asystem.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 8410515SN/Asystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 8510515SN/Asystem.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 8610515SN/Asystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 8710515SN/Asystem.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 8810515SN/Asystem.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 8910515SN/Asystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 9010515SN/Asystem.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 9110515SN/Asystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 9210515SN/Asystem.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 9310515SN/Asystem.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 9410515SN/Asystem.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 9510515SN/Asystem.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 9610515SN/Asystem.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 9710515SN/Asystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 9810515SN/Asystem.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 9910515SN/Asystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 10010515SN/Asystem.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 10110585SN/Asystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 10210585SN/Asystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 10310585SN/Asystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 10410585SN/Asystem.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 10510585SN/Asystem.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 10610585SN/Asystem.cf0.dma_write_txs 1670 # Number of DMA write transactions. 10710515SN/Asystem.cpu_clk_domain.clock 500 # Clock period in ticks 10810628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 10910628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 11010628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 11110628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 11210628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 11310628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 11410628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 11510628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 11610585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 11710585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 11810585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 11910585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 12010585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 12110585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 12210585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 12310585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 12410585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 12510585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 12610585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 12710585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 12810585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 12910585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 13010585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 13110585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 13210585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 13310585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 13410585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 13510585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 13610585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 13710726SN/Asystem.cpu0.dtb.walker.walks 125229 # Table walker walks requested 13810726SN/Asystem.cpu0.dtb.walker.walksLong 125229 # Table walker walks initiated with long descriptors 13910726SN/Asystem.cpu0.dtb.walker.walkWaitTime::samples 125229 # Table walker wait (enqueue to first request) latency 14010726SN/Asystem.cpu0.dtb.walker.walkWaitTime::0 125229 100.00% 100.00% # Table walker wait (enqueue to first request) latency 14110726SN/Asystem.cpu0.dtb.walker.walkWaitTime::total 125229 # Table walker wait (enqueue to first request) latency 14210628SN/Asystem.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution 14310628SN/Asystem.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution 14410628SN/Asystem.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution 14510726SN/Asystem.cpu0.dtb.walker.walkPageSizes::4K 96746 89.71% 89.71% # Table walker page sizes translated 14610726SN/Asystem.cpu0.dtb.walker.walkPageSizes::2M 11103 10.29% 100.00% # Table walker page sizes translated 14710726SN/Asystem.cpu0.dtb.walker.walkPageSizes::total 107849 # Table walker page sizes translated 14810726SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 125229 # Table walker requests started/completed, data/inst 14910628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 15010726SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 125229 # Table walker requests started/completed, data/inst 15110726SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107849 # Table walker requests started/completed, data/inst 15210628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 15310726SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107849 # Table walker requests started/completed, data/inst 15410726SN/Asystem.cpu0.dtb.walker.walkRequestOrigin::total 233078 # Table walker requests started/completed, data/inst 15510585SN/Asystem.cpu0.dtb.inst_hits 0 # ITB inst hits 15610585SN/Asystem.cpu0.dtb.inst_misses 0 # ITB inst misses 15710726SN/Asystem.cpu0.dtb.read_hits 92662773 # DTB read hits 15810726SN/Asystem.cpu0.dtb.read_misses 88786 # DTB read misses 15910726SN/Asystem.cpu0.dtb.write_hits 85694958 # DTB write hits 16010726SN/Asystem.cpu0.dtb.write_misses 36443 # DTB write misses 16110585SN/Asystem.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed 16210585SN/Asystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 16310726SN/Asystem.cpu0.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID 16410585SN/Asystem.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 16510726SN/Asystem.cpu0.dtb.flush_entries 36354 # Number of entries that have been flushed from TLB 16610585SN/Asystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 16710726SN/Asystem.cpu0.dtb.prefetch_faults 5600 # Number of TLB faults due to prefetch 16810585SN/Asystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 16910726SN/Asystem.cpu0.dtb.perms_faults 10503 # Number of TLB faults due to permissions restrictions 17010726SN/Asystem.cpu0.dtb.read_accesses 92751559 # DTB read accesses 17110726SN/Asystem.cpu0.dtb.write_accesses 85731401 # DTB write accesses 17210585SN/Asystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 17310726SN/Asystem.cpu0.dtb.hits 178357731 # DTB hits 17410726SN/Asystem.cpu0.dtb.misses 125229 # DTB misses 17510726SN/Asystem.cpu0.dtb.accesses 178482960 # DTB accesses 17610628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 17710628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 17810628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 17910628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 18010628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 18110628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 18210628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 18310628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 18410585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 18510585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 18610585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 18710585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 18810585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 18910585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 19010585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 19110585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 19210585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 19310585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 19410585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 19510585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 19610585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 19710585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 19810585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 19910585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 20010585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 20110585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 20210585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 20310585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 20410585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 20510726SN/Asystem.cpu0.itb.walker.walks 61377 # Table walker walks requested 20610726SN/Asystem.cpu0.itb.walker.walksLong 61377 # Table walker walks initiated with long descriptors 20710726SN/Asystem.cpu0.itb.walker.walkWaitTime::samples 61377 # Table walker wait (enqueue to first request) latency 20810726SN/Asystem.cpu0.itb.walker.walkWaitTime::0 61377 100.00% 100.00% # Table walker wait (enqueue to first request) latency 20910726SN/Asystem.cpu0.itb.walker.walkWaitTime::total 61377 # Table walker wait (enqueue to first request) latency 21010628SN/Asystem.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution 21110628SN/Asystem.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution 21210628SN/Asystem.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution 21310726SN/Asystem.cpu0.itb.walker.walkPageSizes::4K 55424 98.80% 98.80% # Table walker page sizes translated 21410726SN/Asystem.cpu0.itb.walker.walkPageSizes::2M 672 1.20% 100.00% # Table walker page sizes translated 21510726SN/Asystem.cpu0.itb.walker.walkPageSizes::total 56096 # Table walker page sizes translated 21610628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 21710726SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61377 # Table walker requests started/completed, data/inst 21810726SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 61377 # Table walker requests started/completed, data/inst 21910628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 22010726SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56096 # Table walker requests started/completed, data/inst 22110726SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 56096 # Table walker requests started/completed, data/inst 22210726SN/Asystem.cpu0.itb.walker.walkRequestOrigin::total 117473 # Table walker requests started/completed, data/inst 22310726SN/Asystem.cpu0.itb.inst_hits 497696393 # ITB inst hits 22410726SN/Asystem.cpu0.itb.inst_misses 61377 # ITB inst misses 22510585SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 22610585SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 22710585SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 22810585SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 22910585SN/Asystem.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed 23010585SN/Asystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 23110726SN/Asystem.cpu0.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID 23210585SN/Asystem.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 23310726SN/Asystem.cpu0.itb.flush_entries 25032 # Number of entries that have been flushed from TLB 23410585SN/Asystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 23510585SN/Asystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 23610585SN/Asystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 23710585SN/Asystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 23810585SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 23910585SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 24010726SN/Asystem.cpu0.itb.inst_accesses 497757770 # ITB inst accesses 24110726SN/Asystem.cpu0.itb.hits 497696393 # DTB hits 24210726SN/Asystem.cpu0.itb.misses 61377 # DTB misses 24310726SN/Asystem.cpu0.itb.accesses 497757770 # DTB accesses 24411103Snilay@cs.wisc.edusystem.cpu0.numCycles 94433643486 # number of cpu cycles simulated 24510585SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 24610585SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 24710726SN/Asystem.cpu0.committedInsts 497466384 # Number of instructions committed 24810726SN/Asystem.cpu0.committedOps 584970773 # Number of ops (including micro ops) committed 24910726SN/Asystem.cpu0.num_int_alu_accesses 536103359 # Number of integer alu accesses 25010726SN/Asystem.cpu0.num_fp_alu_accesses 526132 # Number of float alu accesses 25110726SN/Asystem.cpu0.num_func_calls 28869117 # number of times a function call or return occured 25210726SN/Asystem.cpu0.num_conditional_control_insts 76496594 # number of instructions that are conditional controls 25310726SN/Asystem.cpu0.num_int_insts 536103359 # number of integer instructions 25410726SN/Asystem.cpu0.num_fp_insts 526132 # number of float instructions 25510726SN/Asystem.cpu0.num_int_register_reads 784958858 # number of times the integer registers were read 25610726SN/Asystem.cpu0.num_int_register_writes 425337843 # number of times the integer registers were written 25710726SN/Asystem.cpu0.num_fp_register_reads 849923 # number of times the floating registers were read 25810726SN/Asystem.cpu0.num_fp_register_writes 443780 # number of times the floating registers were written 25910726SN/Asystem.cpu0.num_cc_register_reads 133878831 # number of times the CC registers were read 26010726SN/Asystem.cpu0.num_cc_register_writes 133531045 # number of times the CC registers were written 26110726SN/Asystem.cpu0.num_mem_refs 178459396 # number of memory refs 26210726SN/Asystem.cpu0.num_load_insts 92737001 # Number of load instructions 26310726SN/Asystem.cpu0.num_store_insts 85722395 # Number of store instructions 26411103Snilay@cs.wisc.edusystem.cpu0.num_idle_cycles 93848339121.288452 # Number of idle cycles 26511103Snilay@cs.wisc.edusystem.cpu0.num_busy_cycles 585304364.711543 # Number of busy cycles 26610726SN/Asystem.cpu0.not_idle_fraction 0.006198 # Percentage of non-idle cycles 26710726SN/Asystem.cpu0.idle_fraction 0.993802 # Percentage of idle cycles 26810726SN/Asystem.cpu0.Branches 111287587 # Number of branches fetched 26910585SN/Asystem.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 27010726SN/Asystem.cpu0.op_class::IntAlu 405476023 69.28% 69.28% # Class of executed instruction 27110726SN/Asystem.cpu0.op_class::IntMult 1232194 0.21% 69.49% # Class of executed instruction 27210726SN/Asystem.cpu0.op_class::IntDiv 59840 0.01% 69.50% # Class of executed instruction 27310726SN/Asystem.cpu0.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction 27410726SN/Asystem.cpu0.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction 27510726SN/Asystem.cpu0.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction 27610726SN/Asystem.cpu0.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction 27710726SN/Asystem.cpu0.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction 27810726SN/Asystem.cpu0.op_class::FloatSqrt 0 0.00% 69.50% # Class of executed instruction 27910726SN/Asystem.cpu0.op_class::SimdAdd 0 0.00% 69.50% # Class of executed instruction 28010726SN/Asystem.cpu0.op_class::SimdAddAcc 0 0.00% 69.50% # Class of executed instruction 28110726SN/Asystem.cpu0.op_class::SimdAlu 0 0.00% 69.50% # Class of executed instruction 28210726SN/Asystem.cpu0.op_class::SimdCmp 0 0.00% 69.50% # Class of executed instruction 28310726SN/Asystem.cpu0.op_class::SimdCvt 0 0.00% 69.50% # Class of executed instruction 28410726SN/Asystem.cpu0.op_class::SimdMisc 0 0.00% 69.50% # Class of executed instruction 28510726SN/Asystem.cpu0.op_class::SimdMult 0 0.00% 69.50% # Class of executed instruction 28610726SN/Asystem.cpu0.op_class::SimdMultAcc 0 0.00% 69.50% # Class of executed instruction 28710726SN/Asystem.cpu0.op_class::SimdShift 0 0.00% 69.50% # Class of executed instruction 28810726SN/Asystem.cpu0.op_class::SimdShiftAcc 0 0.00% 69.50% # Class of executed instruction 28910726SN/Asystem.cpu0.op_class::SimdSqrt 0 0.00% 69.50% # Class of executed instruction 29010726SN/Asystem.cpu0.op_class::SimdFloatAdd 8 0.00% 69.50% # Class of executed instruction 29110726SN/Asystem.cpu0.op_class::SimdFloatAlu 0 0.00% 69.50% # Class of executed instruction 29210726SN/Asystem.cpu0.op_class::SimdFloatCmp 13 0.00% 69.50% # Class of executed instruction 29310726SN/Asystem.cpu0.op_class::SimdFloatCvt 21 0.00% 69.50% # Class of executed instruction 29410726SN/Asystem.cpu0.op_class::SimdFloatDiv 0 0.00% 69.50% # Class of executed instruction 29510726SN/Asystem.cpu0.op_class::SimdFloatMisc 72507 0.01% 69.51% # Class of executed instruction 29610726SN/Asystem.cpu0.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction 29710726SN/Asystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction 29810726SN/Asystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction 29910726SN/Asystem.cpu0.op_class::MemRead 92737001 15.84% 85.35% # Class of executed instruction 30010726SN/Asystem.cpu0.op_class::MemWrite 85722395 14.65% 100.00% # Class of executed instruction 30110585SN/Asystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 30210585SN/Asystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 30310726SN/Asystem.cpu0.op_class::total 585300003 # Class of executed instruction 30410585SN/Asystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 30511103Snilay@cs.wisc.edusystem.cpu0.kern.inst.quiesce 15195 # number of quiesce instructions executed 30611138Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 6272771 # number of replacements 30710726SN/Asystem.cpu0.dcache.tags.tagsinuse 500.885315 # Cycle average of tags in use 30811138Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 172015771 # Total number of references to valid blocks. 30911138Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 6273283 # Sample count of references to valid blocks. 31011138Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 27.420375 # Average number of references to valid blocks. 31110827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. 31210726SN/Asystem.cpu0.dcache.tags.occ_blocks::cpu0.data 500.885315 # Average occupied blocks per requestor 31310726SN/Asystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.978292 # Average percentage of cache occupancy 31410726SN/Asystem.cpu0.dcache.tags.occ_percent::total 0.978292 # Average percentage of cache occupancy 31510585SN/Asystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 31610726SN/Asystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id 31710726SN/Asystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id 31810726SN/Asystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id 31910585SN/Asystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 32011138Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 363162248 # Number of tag accesses 32111138Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 363162248 # Number of data accesses 32210892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 86214911 # number of ReadReq hits 32310892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 86214911 # number of ReadReq hits 32411138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 80919852 # number of WriteReq hits 32511138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 80919852 # number of WriteReq hits 32610827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 215654 # number of SoftPFReq hits 32710827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 215654 # number of SoftPFReq hits 32811138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::cpu0.data 262009 # number of WriteLineReq hits 32911138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::total 262009 # number of WriteLineReq hits 33010892Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2076466 # number of LoadLockedReq hits 33110892Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 2076466 # number of LoadLockedReq hits 33211138Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 2036568 # number of StoreCondReq hits 33311138Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 2036568 # number of StoreCondReq hits 33411138Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 167134763 # number of demand (read+write) hits 33511138Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 167134763 # number of demand (read+write) hits 33611138Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 167350417 # number of overall hits 33711138Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 167350417 # number of overall hits 33810892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 3309382 # number of ReadReq misses 33910892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 3309382 # number of ReadReq misses 34011138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 1475590 # number of WriteReq misses 34111138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 1475590 # number of WriteReq misses 34210827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 772139 # number of SoftPFReq misses 34310827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 772139 # number of SoftPFReq misses 34411138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::cpu0.data 831711 # number of WriteLineReq misses 34511138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::total 831711 # number of WriteLineReq misses 34610892Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119816 # number of LoadLockedReq misses 34710892Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 119816 # number of LoadLockedReq misses 34811138Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 158575 # number of StoreCondReq misses 34911138Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 158575 # number of StoreCondReq misses 35011138Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 4784972 # number of demand (read+write) misses 35111138Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 4784972 # number of demand (read+write) misses 35211138Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 5557111 # number of overall misses 35311138Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 5557111 # number of overall misses 35410827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 89524293 # number of ReadReq accesses(hits+misses) 35510827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 89524293 # number of ReadReq accesses(hits+misses) 35610827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 82395442 # number of WriteReq accesses(hits+misses) 35710827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 82395442 # number of WriteReq accesses(hits+misses) 35810726SN/Asystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 987793 # number of SoftPFReq accesses(hits+misses) 35910726SN/Asystem.cpu0.dcache.SoftPFReq_accesses::total 987793 # number of SoftPFReq accesses(hits+misses) 36010892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1093720 # number of WriteLineReq accesses(hits+misses) 36110892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::total 1093720 # number of WriteLineReq accesses(hits+misses) 36210726SN/Asystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2196282 # number of LoadLockedReq accesses(hits+misses) 36310726SN/Asystem.cpu0.dcache.LoadLockedReq_accesses::total 2196282 # number of LoadLockedReq accesses(hits+misses) 36410726SN/Asystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2195143 # number of StoreCondReq accesses(hits+misses) 36510726SN/Asystem.cpu0.dcache.StoreCondReq_accesses::total 2195143 # number of StoreCondReq accesses(hits+misses) 36610827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 171919735 # number of demand (read+write) accesses 36710827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 171919735 # number of demand (read+write) accesses 36810827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 172907528 # number of overall (read+write) accesses 36910827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 172907528 # number of overall (read+write) accesses 37010726SN/Asystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036966 # miss rate for ReadReq accesses 37110726SN/Asystem.cpu0.dcache.ReadReq_miss_rate::total 0.036966 # miss rate for ReadReq accesses 37210827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017909 # miss rate for WriteReq accesses 37310827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.017909 # miss rate for WriteReq accesses 37410827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781681 # miss rate for SoftPFReq accesses 37510827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.781681 # miss rate for SoftPFReq accesses 37611138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760442 # miss rate for WriteLineReq accesses 37711138Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::total 0.760442 # miss rate for WriteLineReq accesses 37810726SN/Asystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054554 # miss rate for LoadLockedReq accesses 37910726SN/Asystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054554 # miss rate for LoadLockedReq accesses 38011138Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.072239 # miss rate for StoreCondReq accesses 38111138Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.072239 # miss rate for StoreCondReq accesses 38210827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.027833 # miss rate for demand accesses 38310827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.027833 # miss rate for demand accesses 38411138Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.032139 # miss rate for overall accesses 38511138Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.032139 # miss rate for overall accesses 38610585SN/Asystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 38710585SN/Asystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 38810585SN/Asystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 38910585SN/Asystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 39010585SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 39110585SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 39210585SN/Asystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 39310585SN/Asystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 39411138Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 4465852 # number of writebacks 39511138Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 4465852 # number of writebacks 39610585SN/Asystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 39710892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 5539081 # number of replacements 39810726SN/Asystem.cpu0.icache.tags.tagsinuse 511.989005 # Cycle average of tags in use 39910892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 492212891 # Total number of references to valid blocks. 40010892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 5539593 # Sample count of references to valid blocks. 40110892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 88.853620 # Average number of references to valid blocks. 40210585SN/Asystem.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit. 40310726SN/Asystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989005 # Average occupied blocks per requestor 40410585SN/Asystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy 40510585SN/Asystem.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy 40610585SN/Asystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 40710726SN/Asystem.cpu0.icache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id 40810726SN/Asystem.cpu0.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id 40910726SN/Asystem.cpu0.icache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id 41010585SN/Asystem.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 41110585SN/Asystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 41210892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 1001044576 # Number of tag accesses 41310892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 1001044576 # Number of data accesses 41410892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 492212891 # number of ReadReq hits 41510892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 492212891 # number of ReadReq hits 41610892Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 492212891 # number of demand (read+write) hits 41710892Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 492212891 # number of demand (read+write) hits 41810892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 492212891 # number of overall hits 41910892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 492212891 # number of overall hits 42010892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 5539598 # number of ReadReq misses 42110892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 5539598 # number of ReadReq misses 42210892Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 5539598 # number of demand (read+write) misses 42310892Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 5539598 # number of demand (read+write) misses 42410892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 5539598 # number of overall misses 42510892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 5539598 # number of overall misses 42610726SN/Asystem.cpu0.icache.ReadReq_accesses::cpu0.inst 497752489 # number of ReadReq accesses(hits+misses) 42710726SN/Asystem.cpu0.icache.ReadReq_accesses::total 497752489 # number of ReadReq accesses(hits+misses) 42810726SN/Asystem.cpu0.icache.demand_accesses::cpu0.inst 497752489 # number of demand (read+write) accesses 42910726SN/Asystem.cpu0.icache.demand_accesses::total 497752489 # number of demand (read+write) accesses 43010726SN/Asystem.cpu0.icache.overall_accesses::cpu0.inst 497752489 # number of overall (read+write) accesses 43110726SN/Asystem.cpu0.icache.overall_accesses::total 497752489 # number of overall (read+write) accesses 43210726SN/Asystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011129 # miss rate for ReadReq accesses 43310726SN/Asystem.cpu0.icache.ReadReq_miss_rate::total 0.011129 # miss rate for ReadReq accesses 43410726SN/Asystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.011129 # miss rate for demand accesses 43510726SN/Asystem.cpu0.icache.demand_miss_rate::total 0.011129 # miss rate for demand accesses 43610726SN/Asystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.011129 # miss rate for overall accesses 43710726SN/Asystem.cpu0.icache.overall_miss_rate::total 0.011129 # miss rate for overall accesses 43810585SN/Asystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 43910585SN/Asystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 44010585SN/Asystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 44110585SN/Asystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 44210585SN/Asystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 44310585SN/Asystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 44410585SN/Asystem.cpu0.icache.fast_writes 0 # number of fast writes performed 44510585SN/Asystem.cpu0.icache.cache_copies 0 # number of cache copies performed 44610585SN/Asystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 44710628SN/Asystem.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 44810628SN/Asystem.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 44910628SN/Asystem.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 45010628SN/Asystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 45110628SN/Asystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 45210628SN/Asystem.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 45311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.replacements 2711851 # number of replacements 45411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tagsinuse 16210.481258 # Cycle average of tags in use 45511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.total_refs 18787660 # Total number of references to valid blocks. 45611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.sampled_refs 2727832 # Sample count of references to valid blocks. 45711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.avg_refs 6.887396 # Average number of references to valid blocks. 45810585SN/Asystem.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. 45911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 5681.130997 # Average occupied blocks per requestor 46011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 53.077110 # Average occupied blocks per requestor 46111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 57.001745 # Average occupied blocks per requestor 46211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4560.666382 # Average occupied blocks per requestor 46311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.data 5858.605025 # Average occupied blocks per requestor 46411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.346749 # Average percentage of cache occupancy 46511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003240 # Average percentage of cache occupancy 46611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003479 # Average percentage of cache occupancy 46711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.278361 # Average percentage of cache occupancy 46811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.data 0.357581 # Average percentage of cache occupancy 46911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.989409 # Average percentage of cache occupancy 47011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 46 # Occupied blocks per task id 47111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 15935 # Occupied blocks per task id 47211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 35 # Occupied blocks per task id 47310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id 47411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 47511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 229 # Occupied blocks per task id 47611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1157 # Occupied blocks per task id 47711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4616 # Occupied blocks per task id 47811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5323 # Occupied blocks per task id 47911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4610 # Occupied blocks per task id 48011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.002808 # Percentage of cache occupancy per task id 48111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.972595 # Percentage of cache occupancy per task id 48211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tag_accesses 396153496 # Number of tag accesses 48311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.data_accesses 396153496 # Number of data accesses 48411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 271024 # number of ReadReq hits 48511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 142798 # number of ReadReq hits 48611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 413822 # number of ReadReq hits 48711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_hits::writebacks 4465852 # number of Writeback hits 48811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_hits::total 4465852 # number of Writeback hits 48911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::cpu0.data 3520 # number of UpgradeReq hits 49011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::total 3520 # number of UpgradeReq hits 49111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 634528 # number of ReadExReq hits 49211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 634528 # number of ReadExReq hits 49311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4971317 # number of ReadCleanReq hits 49411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 4971317 # number of ReadCleanReq hits 49511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2943098 # number of ReadSharedReq hits 49611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 2943098 # number of ReadSharedReq hits 49711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::cpu0.data 222986 # number of InvalidateReq hits 49811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::total 222986 # number of InvalidateReq hits 49911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 271024 # number of demand (read+write) hits 50011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 142798 # number of demand (read+write) hits 50111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 4971317 # number of demand (read+write) hits 50211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 3577626 # number of demand (read+write) hits 50311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::total 8962765 # number of demand (read+write) hits 50411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 271024 # number of overall hits 50511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 142798 # number of overall hits 50611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 4971317 # number of overall hits 50711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 3577626 # number of overall hits 50811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::total 8962765 # number of overall hits 50911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11253 # number of ReadReq misses 51011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8486 # number of ReadReq misses 51111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 19739 # number of ReadReq misses 51211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 128216 # number of UpgradeReq misses 51311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 128216 # number of UpgradeReq misses 51411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 158575 # number of SCUpgradeReq misses 51511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 158575 # number of SCUpgradeReq misses 51611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 709702 # number of ReadExReq misses 51711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 709702 # number of ReadExReq misses 51811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 568281 # number of ReadCleanReq misses 51911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 568281 # number of ReadCleanReq misses 52011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1258239 # number of ReadSharedReq misses 52111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 1258239 # number of ReadSharedReq misses 52211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::cpu0.data 608349 # number of InvalidateReq misses 52311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::total 608349 # number of InvalidateReq misses 52411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11253 # number of demand (read+write) misses 52511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 8486 # number of demand (read+write) misses 52611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 568281 # number of demand (read+write) misses 52711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 1967941 # number of demand (read+write) misses 52811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::total 2555961 # number of demand (read+write) misses 52911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11253 # number of overall misses 53011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 8486 # number of overall misses 53111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 568281 # number of overall misses 53211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 1967941 # number of overall misses 53311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::total 2555961 # number of overall misses 53411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 282277 # number of ReadReq accesses(hits+misses) 53511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 151284 # number of ReadReq accesses(hits+misses) 53611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 433561 # number of ReadReq accesses(hits+misses) 53711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_accesses::writebacks 4465852 # number of Writeback accesses(hits+misses) 53811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_accesses::total 4465852 # number of Writeback accesses(hits+misses) 53911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 131736 # number of UpgradeReq accesses(hits+misses) 54011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 131736 # number of UpgradeReq accesses(hits+misses) 54111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 158575 # number of SCUpgradeReq accesses(hits+misses) 54211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 158575 # number of SCUpgradeReq accesses(hits+misses) 54311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1344230 # number of ReadExReq accesses(hits+misses) 54411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1344230 # number of ReadExReq accesses(hits+misses) 54510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5539598 # number of ReadCleanReq accesses(hits+misses) 54610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 5539598 # number of ReadCleanReq accesses(hits+misses) 54710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4201337 # number of ReadSharedReq accesses(hits+misses) 54810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 4201337 # number of ReadSharedReq accesses(hits+misses) 54911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 831335 # number of InvalidateReq accesses(hits+misses) 55011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::total 831335 # number of InvalidateReq accesses(hits+misses) 55111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 282277 # number of demand (read+write) accesses 55211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 151284 # number of demand (read+write) accesses 55310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 5539598 # number of demand (read+write) accesses 55411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 5545567 # number of demand (read+write) accesses 55511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::total 11518726 # number of demand (read+write) accesses 55611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 282277 # number of overall (read+write) accesses 55711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 151284 # number of overall (read+write) accesses 55810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 5539598 # number of overall (read+write) accesses 55911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 5545567 # number of overall (read+write) accesses 56011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::total 11518726 # number of overall (read+write) accesses 56111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.039865 # miss rate for ReadReq accesses 56211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.056093 # miss rate for ReadReq accesses 56311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.045528 # miss rate for ReadReq accesses 56411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.973280 # miss rate for UpgradeReq accesses 56511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 0.973280 # miss rate for UpgradeReq accesses 56610585SN/Asystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 56710585SN/Asystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 56811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.527962 # miss rate for ReadExReq accesses 56911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.527962 # miss rate for ReadExReq accesses 57011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.102585 # miss rate for ReadCleanReq accesses 57111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.102585 # miss rate for ReadCleanReq accesses 57211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.299485 # miss rate for ReadSharedReq accesses 57311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.299485 # miss rate for ReadSharedReq accesses 57411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.731774 # miss rate for InvalidateReq accesses 57511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::total 0.731774 # miss rate for InvalidateReq accesses 57611138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.039865 # miss rate for demand accesses 57711138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.056093 # miss rate for demand accesses 57811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.102585 # miss rate for demand accesses 57911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.354867 # miss rate for demand accesses 58011138Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.221896 # miss rate for demand accesses 58111138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.039865 # miss rate for overall accesses 58211138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.056093 # miss rate for overall accesses 58311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.102585 # miss rate for overall accesses 58411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.354867 # miss rate for overall accesses 58511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.221896 # miss rate for overall accesses 58610585SN/Asystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 58710585SN/Asystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 58810585SN/Asystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 58910585SN/Asystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 59010585SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 59110585SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 59210585SN/Asystem.cpu0.l2cache.fast_writes 0 # number of fast writes performed 59310585SN/Asystem.cpu0.l2cache.cache_copies 0 # number of cache copies performed 59411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::writebacks 1571493 # number of writebacks 59511138Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::total 1571493 # number of writebacks 59610585SN/Asystem.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 59711138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_requests 24275029 # Total number of requests made to the snoop filter. 59811138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_requests 12358536 # Number of requests hitting in the snoop filter with a single holder of the requested data. 59911138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1399 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 60011138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_snoops 471082 # Total number of snoops made to the snoop filter. 60111138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_snoops 471076 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 60211138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 60310892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 623009 # Transaction distribution 60410827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 10363944 # Transaction distribution 60510827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 32419 # Transaction distribution 60610827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 32419 # Transaction distribution 60711138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::Writeback 4465852 # Transaction distribution 60811138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::CleanEvict 7344601 # Transaction distribution 60911138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 131736 # Transaction distribution 61011138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 158575 # Transaction distribution 61111138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 290311 # Transaction distribution 61211138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1344230 # Transaction distribution 61311138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1344230 # Transaction distribution 61410892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 5539598 # Transaction distribution 61510892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 4201337 # Transaction distribution 61611138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateReq 831335 # Transaction distribution 61711138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateResp 831335 # Transaction distribution 61811138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16703618 # Packet count per connected master and slave (bytes) 61911138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19736583 # Packet count per connected master and slave (bytes) 62010726SN/Asystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 366654 # Packet count per connected master and slave (bytes) 62110726SN/Asystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 728076 # Packet count per connected master and slave (bytes) 62211138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count::total 37534931 # Packet count per connected master and slave (bytes) 62310892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 354706772 # Cumulative packet size per connected master and slave (bytes) 62411138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 640924169 # Cumulative packet size per connected master and slave (bytes) 62510726SN/Asystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1466616 # Cumulative packet size per connected master and slave (bytes) 62610726SN/Asystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2912304 # Cumulative packet size per connected master and slave (bytes) 62711138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size::total 1000009861 # Cumulative packet size per connected master and slave (bytes) 62811138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoops 4846239 # Total snoops (count) 62911138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 29334646 # Request fanout histogram 63011138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 0.024894 # Request fanout histogram 63111138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.155804 # Request fanout histogram 63210585SN/Asystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 63311138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 28604393 97.51% 97.51% # Request fanout histogram 63411138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 730247 2.49% 100.00% # Request fanout histogram 63511138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram 63610585SN/Asystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 63711138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 63810827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 63911138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 29334646 # Request fanout histogram 64010628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 64110628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 64210628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 64310628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 64410628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 64510628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 64610628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 64710628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 64810585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 64910585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 65010585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 65110585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 65210585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 65310585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 65410585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 65510585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 65610585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 65710585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 65810585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 65910585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 66010585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 66110585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 66210585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 66310585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 66410585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 66510585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 66610585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 66710585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 66810585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 66910726SN/Asystem.cpu1.dtb.walker.walks 144041 # Table walker walks requested 67010726SN/Asystem.cpu1.dtb.walker.walksLong 144041 # Table walker walks initiated with long descriptors 67110726SN/Asystem.cpu1.dtb.walker.walkWaitTime::samples 144041 # Table walker wait (enqueue to first request) latency 67210726SN/Asystem.cpu1.dtb.walker.walkWaitTime::0 144041 100.00% 100.00% # Table walker wait (enqueue to first request) latency 67310726SN/Asystem.cpu1.dtb.walker.walkWaitTime::total 144041 # Table walker wait (enqueue to first request) latency 67410628SN/Asystem.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution 67510628SN/Asystem.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution 67610628SN/Asystem.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution 67710726SN/Asystem.cpu1.dtb.walker.walkPageSizes::4K 111414 88.97% 88.97% # Table walker page sizes translated 67810726SN/Asystem.cpu1.dtb.walker.walkPageSizes::2M 13807 11.03% 100.00% # Table walker page sizes translated 67910726SN/Asystem.cpu1.dtb.walker.walkPageSizes::total 125221 # Table walker page sizes translated 68010726SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144041 # Table walker requests started/completed, data/inst 68110628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 68210726SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144041 # Table walker requests started/completed, data/inst 68310726SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 125221 # Table walker requests started/completed, data/inst 68410628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 68510726SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 125221 # Table walker requests started/completed, data/inst 68610726SN/Asystem.cpu1.dtb.walker.walkRequestOrigin::total 269262 # Table walker requests started/completed, data/inst 68710585SN/Asystem.cpu1.dtb.inst_hits 0 # ITB inst hits 68810585SN/Asystem.cpu1.dtb.inst_misses 0 # ITB inst misses 68910726SN/Asystem.cpu1.dtb.read_hits 90153061 # DTB read hits 69010726SN/Asystem.cpu1.dtb.read_misses 111753 # DTB read misses 69110726SN/Asystem.cpu1.dtb.write_hits 81132787 # DTB write hits 69210726SN/Asystem.cpu1.dtb.write_misses 32288 # DTB write misses 69310585SN/Asystem.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed 69410585SN/Asystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 69510726SN/Asystem.cpu1.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID 69610585SN/Asystem.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 69710726SN/Asystem.cpu1.dtb.flush_entries 44587 # Number of entries that have been flushed from TLB 69810585SN/Asystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 69910726SN/Asystem.cpu1.dtb.prefetch_faults 4554 # Number of TLB faults due to prefetch 70010585SN/Asystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 70110726SN/Asystem.cpu1.dtb.perms_faults 11374 # Number of TLB faults due to permissions restrictions 70210726SN/Asystem.cpu1.dtb.read_accesses 90264814 # DTB read accesses 70310726SN/Asystem.cpu1.dtb.write_accesses 81165075 # DTB write accesses 70410585SN/Asystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 70510726SN/Asystem.cpu1.dtb.hits 171285848 # DTB hits 70610726SN/Asystem.cpu1.dtb.misses 144041 # DTB misses 70710726SN/Asystem.cpu1.dtb.accesses 171429889 # DTB accesses 70810628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 70910628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 71010628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 71110628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 71210628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 71310628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 71410628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 71510628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 71610585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 71710585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 71810585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 71910585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 72010585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 72110585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 72210585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 72310585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 72410585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 72510585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 72610585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 72710585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 72810585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 72910585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 73010585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 73110585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 73210585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 73310585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 73410585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 73510585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 73610585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 73710726SN/Asystem.cpu1.itb.walker.walks 60885 # Table walker walks requested 73810726SN/Asystem.cpu1.itb.walker.walksLong 60885 # Table walker walks initiated with long descriptors 73910726SN/Asystem.cpu1.itb.walker.walkWaitTime::samples 60885 # Table walker wait (enqueue to first request) latency 74010726SN/Asystem.cpu1.itb.walker.walkWaitTime::0 60885 100.00% 100.00% # Table walker wait (enqueue to first request) latency 74110726SN/Asystem.cpu1.itb.walker.walkWaitTime::total 60885 # Table walker wait (enqueue to first request) latency 74210628SN/Asystem.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution 74310628SN/Asystem.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution 74410628SN/Asystem.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution 74510726SN/Asystem.cpu1.itb.walker.walkPageSizes::4K 53790 99.07% 99.07% # Table walker page sizes translated 74610726SN/Asystem.cpu1.itb.walker.walkPageSizes::2M 505 0.93% 100.00% # Table walker page sizes translated 74710726SN/Asystem.cpu1.itb.walker.walkPageSizes::total 54295 # Table walker page sizes translated 74810628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 74910726SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60885 # Table walker requests started/completed, data/inst 75010726SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 60885 # Table walker requests started/completed, data/inst 75110628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 75210726SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 54295 # Table walker requests started/completed, data/inst 75310726SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 54295 # Table walker requests started/completed, data/inst 75410726SN/Asystem.cpu1.itb.walker.walkRequestOrigin::total 115180 # Table walker requests started/completed, data/inst 75510726SN/Asystem.cpu1.itb.inst_hits 478248118 # ITB inst hits 75610726SN/Asystem.cpu1.itb.inst_misses 60885 # ITB inst misses 75710585SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 75810585SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 75910585SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 76010585SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 76110585SN/Asystem.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed 76210585SN/Asystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 76310726SN/Asystem.cpu1.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID 76410585SN/Asystem.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 76510726SN/Asystem.cpu1.itb.flush_entries 31530 # Number of entries that have been flushed from TLB 76610585SN/Asystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 76710585SN/Asystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 76810585SN/Asystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 76910585SN/Asystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 77010585SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 77110585SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 77210726SN/Asystem.cpu1.itb.inst_accesses 478309003 # ITB inst accesses 77310726SN/Asystem.cpu1.itb.hits 478248118 # DTB hits 77410726SN/Asystem.cpu1.itb.misses 60885 # DTB misses 77510726SN/Asystem.cpu1.itb.accesses 478309003 # DTB accesses 77611103Snilay@cs.wisc.edusystem.cpu1.numCycles 94433635490 # number of cpu cycles simulated 77710585SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 77810585SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 77910726SN/Asystem.cpu1.committedInsts 477990846 # Number of instructions committed 78010726SN/Asystem.cpu1.committedOps 562567642 # Number of ops (including micro ops) committed 78110726SN/Asystem.cpu1.num_int_alu_accesses 516282159 # Number of integer alu accesses 78210726SN/Asystem.cpu1.num_fp_alu_accesses 374678 # Number of float alu accesses 78310726SN/Asystem.cpu1.num_func_calls 28237407 # number of times a function call or return occured 78410726SN/Asystem.cpu1.num_conditional_control_insts 73185792 # number of instructions that are conditional controls 78510726SN/Asystem.cpu1.num_int_insts 516282159 # number of integer instructions 78610726SN/Asystem.cpu1.num_fp_insts 374678 # number of float instructions 78710726SN/Asystem.cpu1.num_int_register_reads 763231058 # number of times the integer registers were read 78810726SN/Asystem.cpu1.num_int_register_writes 411079626 # number of times the integer registers were written 78910726SN/Asystem.cpu1.num_fp_register_reads 608455 # number of times the floating registers were read 79010726SN/Asystem.cpu1.num_fp_register_writes 306456 # number of times the floating registers were written 79110726SN/Asystem.cpu1.num_cc_register_reads 126379788 # number of times the CC registers were read 79210726SN/Asystem.cpu1.num_cc_register_writes 126112608 # number of times the CC registers were written 79310726SN/Asystem.cpu1.num_mem_refs 171406825 # number of memory refs 79410726SN/Asystem.cpu1.num_load_insts 90251973 # Number of load instructions 79510726SN/Asystem.cpu1.num_store_insts 81154852 # Number of store instructions 79611103Snilay@cs.wisc.edusystem.cpu1.num_idle_cycles 93870751219.397461 # Number of idle cycles 79711103Snilay@cs.wisc.edusystem.cpu1.num_busy_cycles 562884270.602548 # Number of busy cycles 79810726SN/Asystem.cpu1.not_idle_fraction 0.005961 # Percentage of non-idle cycles 79910726SN/Asystem.cpu1.idle_fraction 0.994039 # Percentage of idle cycles 80010726SN/Asystem.cpu1.Branches 106497601 # Number of branches fetched 80110585SN/Asystem.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 80210726SN/Asystem.cpu1.op_class::IntAlu 390236864 69.33% 69.33% # Class of executed instruction 80310726SN/Asystem.cpu1.op_class::IntMult 1137629 0.20% 69.53% # Class of executed instruction 80410726SN/Asystem.cpu1.op_class::IntDiv 60962 0.01% 69.54% # Class of executed instruction 80510726SN/Asystem.cpu1.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction 80610726SN/Asystem.cpu1.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction 80710726SN/Asystem.cpu1.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction 80810726SN/Asystem.cpu1.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction 80910726SN/Asystem.cpu1.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction 81010726SN/Asystem.cpu1.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction 81110726SN/Asystem.cpu1.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction 81210726SN/Asystem.cpu1.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction 81310726SN/Asystem.cpu1.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction 81410726SN/Asystem.cpu1.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction 81510726SN/Asystem.cpu1.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction 81610726SN/Asystem.cpu1.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction 81710726SN/Asystem.cpu1.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction 81810726SN/Asystem.cpu1.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction 81910726SN/Asystem.cpu1.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction 82010726SN/Asystem.cpu1.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction 82110726SN/Asystem.cpu1.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction 82210726SN/Asystem.cpu1.op_class::SimdFloatAdd 0 0.00% 69.54% # Class of executed instruction 82310726SN/Asystem.cpu1.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction 82410726SN/Asystem.cpu1.op_class::SimdFloatCmp 0 0.00% 69.54% # Class of executed instruction 82510726SN/Asystem.cpu1.op_class::SimdFloatCvt 0 0.00% 69.54% # Class of executed instruction 82610726SN/Asystem.cpu1.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction 82710726SN/Asystem.cpu1.op_class::SimdFloatMisc 37059 0.01% 69.55% # Class of executed instruction 82810726SN/Asystem.cpu1.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction 82910726SN/Asystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction 83010726SN/Asystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction 83110726SN/Asystem.cpu1.op_class::MemRead 90251973 16.03% 85.58% # Class of executed instruction 83210726SN/Asystem.cpu1.op_class::MemWrite 81154852 14.42% 100.00% # Class of executed instruction 83310585SN/Asystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 83410585SN/Asystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 83510726SN/Asystem.cpu1.op_class::total 562879339 # Class of executed instruction 83610585SN/Asystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 83711103Snilay@cs.wisc.edusystem.cpu1.kern.inst.quiesce 7199 # number of quiesce instructions executed 83810726SN/Asystem.cpu1.dcache.tags.replacements 5945049 # number of replacements 83910726SN/Asystem.cpu1.dcache.tags.tagsinuse 438.290639 # Cycle average of tags in use 84010726SN/Asystem.cpu1.dcache.tags.total_refs 165346662 # Total number of references to valid blocks. 84110726SN/Asystem.cpu1.dcache.tags.sampled_refs 5945561 # Sample count of references to valid blocks. 84210726SN/Asystem.cpu1.dcache.tags.avg_refs 27.810103 # Average number of references to valid blocks. 84310585SN/Asystem.cpu1.dcache.tags.warmup_cycle 8470277778500 # Cycle when the warmup percentage was hit. 84410726SN/Asystem.cpu1.dcache.tags.occ_blocks::cpu1.data 438.290639 # Average occupied blocks per requestor 84510726SN/Asystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.856036 # Average percentage of cache occupancy 84610726SN/Asystem.cpu1.dcache.tags.occ_percent::total 0.856036 # Average percentage of cache occupancy 84710726SN/Asystem.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 84810726SN/Asystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id 84910726SN/Asystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id 85010726SN/Asystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id 85110726SN/Asystem.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 85210726SN/Asystem.cpu1.dcache.tags.tag_accesses 348813711 # Number of tag accesses 85310726SN/Asystem.cpu1.dcache.tags.data_accesses 348813711 # Number of data accesses 85410726SN/Asystem.cpu1.dcache.ReadReq_hits::cpu1.data 83697564 # number of ReadReq hits 85510726SN/Asystem.cpu1.dcache.ReadReq_hits::total 83697564 # number of ReadReq hits 85611138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 76990146 # number of WriteReq hits 85711138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 76990146 # number of WriteReq hits 85810726SN/Asystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 187854 # number of SoftPFReq hits 85910726SN/Asystem.cpu1.dcache.SoftPFReq_hits::total 187854 # number of SoftPFReq hits 86010892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::cpu1.data 63440 # number of WriteLineReq hits 86110892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::total 63440 # number of WriteLineReq hits 86210726SN/Asystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2062256 # number of LoadLockedReq hits 86310726SN/Asystem.cpu1.dcache.LoadLockedReq_hits::total 2062256 # number of LoadLockedReq hits 86411138Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 2048851 # number of StoreCondReq hits 86511138Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 2048851 # number of StoreCondReq hits 86611138Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 160687710 # number of demand (read+write) hits 86711138Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 160687710 # number of demand (read+write) hits 86811138Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 160875564 # number of overall hits 86911138Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 160875564 # number of overall hits 87010726SN/Asystem.cpu1.dcache.ReadReq_misses::cpu1.data 3358222 # number of ReadReq misses 87110726SN/Asystem.cpu1.dcache.ReadReq_misses::total 3358222 # number of ReadReq misses 87211138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 1453330 # number of WriteReq misses 87311138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 1453330 # number of WriteReq misses 87410726SN/Asystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 792351 # number of SoftPFReq misses 87510726SN/Asystem.cpu1.dcache.SoftPFReq_misses::total 792351 # number of SoftPFReq misses 87610892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::cpu1.data 427059 # number of WriteLineReq misses 87710892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::total 427059 # number of WriteLineReq misses 87810726SN/Asystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 146820 # number of LoadLockedReq misses 87910726SN/Asystem.cpu1.dcache.LoadLockedReq_misses::total 146820 # number of LoadLockedReq misses 88011138Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 158898 # number of StoreCondReq misses 88111138Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 158898 # number of StoreCondReq misses 88211138Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 4811552 # number of demand (read+write) misses 88311138Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 4811552 # number of demand (read+write) misses 88411138Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 5603903 # number of overall misses 88511138Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 5603903 # number of overall misses 88610726SN/Asystem.cpu1.dcache.ReadReq_accesses::cpu1.data 87055786 # number of ReadReq accesses(hits+misses) 88710726SN/Asystem.cpu1.dcache.ReadReq_accesses::total 87055786 # number of ReadReq accesses(hits+misses) 88810726SN/Asystem.cpu1.dcache.WriteReq_accesses::cpu1.data 78443476 # number of WriteReq accesses(hits+misses) 88910726SN/Asystem.cpu1.dcache.WriteReq_accesses::total 78443476 # number of WriteReq accesses(hits+misses) 89010726SN/Asystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 980205 # number of SoftPFReq accesses(hits+misses) 89110726SN/Asystem.cpu1.dcache.SoftPFReq_accesses::total 980205 # number of SoftPFReq accesses(hits+misses) 89210892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::cpu1.data 490499 # number of WriteLineReq accesses(hits+misses) 89310892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::total 490499 # number of WriteLineReq accesses(hits+misses) 89410726SN/Asystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2209076 # number of LoadLockedReq accesses(hits+misses) 89510726SN/Asystem.cpu1.dcache.LoadLockedReq_accesses::total 2209076 # number of LoadLockedReq accesses(hits+misses) 89610726SN/Asystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2207749 # number of StoreCondReq accesses(hits+misses) 89710726SN/Asystem.cpu1.dcache.StoreCondReq_accesses::total 2207749 # number of StoreCondReq accesses(hits+misses) 89810726SN/Asystem.cpu1.dcache.demand_accesses::cpu1.data 165499262 # number of demand (read+write) accesses 89910726SN/Asystem.cpu1.dcache.demand_accesses::total 165499262 # number of demand (read+write) accesses 90010726SN/Asystem.cpu1.dcache.overall_accesses::cpu1.data 166479467 # number of overall (read+write) accesses 90110726SN/Asystem.cpu1.dcache.overall_accesses::total 166479467 # number of overall (read+write) accesses 90210726SN/Asystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038576 # miss rate for ReadReq accesses 90310726SN/Asystem.cpu1.dcache.ReadReq_miss_rate::total 0.038576 # miss rate for ReadReq accesses 90411138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018527 # miss rate for WriteReq accesses 90511138Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.018527 # miss rate for WriteReq accesses 90610726SN/Asystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808352 # miss rate for SoftPFReq accesses 90710726SN/Asystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.808352 # miss rate for SoftPFReq accesses 90810892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870662 # miss rate for WriteLineReq accesses 90910892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::total 0.870662 # miss rate for WriteLineReq accesses 91010726SN/Asystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066462 # miss rate for LoadLockedReq accesses 91110726SN/Asystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066462 # miss rate for LoadLockedReq accesses 91211138Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071973 # miss rate for StoreCondReq accesses 91311138Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.071973 # miss rate for StoreCondReq accesses 91411138Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.029073 # miss rate for demand accesses 91511138Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.029073 # miss rate for demand accesses 91610892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.033661 # miss rate for overall accesses 91710892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.033661 # miss rate for overall accesses 91810585SN/Asystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 91910585SN/Asystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 92010585SN/Asystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 92110585SN/Asystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 92210585SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 92310585SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 92410585SN/Asystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 92510585SN/Asystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 92611138Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 4029235 # number of writebacks 92711138Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 4029235 # number of writebacks 92810585SN/Asystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 92910726SN/Asystem.cpu1.icache.tags.replacements 4741297 # number of replacements 93010726SN/Asystem.cpu1.icache.tags.tagsinuse 496.426080 # Cycle average of tags in use 93110726SN/Asystem.cpu1.icache.tags.total_refs 473560604 # Total number of references to valid blocks. 93210726SN/Asystem.cpu1.icache.tags.sampled_refs 4741809 # Sample count of references to valid blocks. 93310726SN/Asystem.cpu1.icache.tags.avg_refs 99.869186 # Average number of references to valid blocks. 93410585SN/Asystem.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit. 93510726SN/Asystem.cpu1.icache.tags.occ_blocks::cpu1.inst 496.426080 # Average occupied blocks per requestor 93610726SN/Asystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.969582 # Average percentage of cache occupancy 93710726SN/Asystem.cpu1.icache.tags.occ_percent::total 0.969582 # Average percentage of cache occupancy 93810585SN/Asystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 93910585SN/Asystem.cpu1.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 94010585SN/Asystem.cpu1.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id 94110585SN/Asystem.cpu1.icache.tags.age_task_id_blocks_1024::2 144 # Occupied blocks per task id 94210585SN/Asystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 94310726SN/Asystem.cpu1.icache.tags.tag_accesses 961346635 # Number of tag accesses 94410726SN/Asystem.cpu1.icache.tags.data_accesses 961346635 # Number of data accesses 94510726SN/Asystem.cpu1.icache.ReadReq_hits::cpu1.inst 473560604 # number of ReadReq hits 94610726SN/Asystem.cpu1.icache.ReadReq_hits::total 473560604 # number of ReadReq hits 94710726SN/Asystem.cpu1.icache.demand_hits::cpu1.inst 473560604 # number of demand (read+write) hits 94810726SN/Asystem.cpu1.icache.demand_hits::total 473560604 # number of demand (read+write) hits 94910726SN/Asystem.cpu1.icache.overall_hits::cpu1.inst 473560604 # number of overall hits 95010726SN/Asystem.cpu1.icache.overall_hits::total 473560604 # number of overall hits 95110726SN/Asystem.cpu1.icache.ReadReq_misses::cpu1.inst 4741809 # number of ReadReq misses 95210726SN/Asystem.cpu1.icache.ReadReq_misses::total 4741809 # number of ReadReq misses 95310726SN/Asystem.cpu1.icache.demand_misses::cpu1.inst 4741809 # number of demand (read+write) misses 95410726SN/Asystem.cpu1.icache.demand_misses::total 4741809 # number of demand (read+write) misses 95510726SN/Asystem.cpu1.icache.overall_misses::cpu1.inst 4741809 # number of overall misses 95610726SN/Asystem.cpu1.icache.overall_misses::total 4741809 # number of overall misses 95710726SN/Asystem.cpu1.icache.ReadReq_accesses::cpu1.inst 478302413 # number of ReadReq accesses(hits+misses) 95810726SN/Asystem.cpu1.icache.ReadReq_accesses::total 478302413 # number of ReadReq accesses(hits+misses) 95910726SN/Asystem.cpu1.icache.demand_accesses::cpu1.inst 478302413 # number of demand (read+write) accesses 96010726SN/Asystem.cpu1.icache.demand_accesses::total 478302413 # number of demand (read+write) accesses 96110726SN/Asystem.cpu1.icache.overall_accesses::cpu1.inst 478302413 # number of overall (read+write) accesses 96210726SN/Asystem.cpu1.icache.overall_accesses::total 478302413 # number of overall (read+write) accesses 96310726SN/Asystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009914 # miss rate for ReadReq accesses 96410726SN/Asystem.cpu1.icache.ReadReq_miss_rate::total 0.009914 # miss rate for ReadReq accesses 96510726SN/Asystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.009914 # miss rate for demand accesses 96610726SN/Asystem.cpu1.icache.demand_miss_rate::total 0.009914 # miss rate for demand accesses 96710726SN/Asystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.009914 # miss rate for overall accesses 96810726SN/Asystem.cpu1.icache.overall_miss_rate::total 0.009914 # miss rate for overall accesses 96910585SN/Asystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 97010585SN/Asystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 97110585SN/Asystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 97210585SN/Asystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 97310585SN/Asystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 97410585SN/Asystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 97510585SN/Asystem.cpu1.icache.fast_writes 0 # number of fast writes performed 97610585SN/Asystem.cpu1.icache.cache_copies 0 # number of cache copies performed 97710585SN/Asystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 97810628SN/Asystem.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 97910628SN/Asystem.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 98010628SN/Asystem.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 98110628SN/Asystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 98210628SN/Asystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 98310628SN/Asystem.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 98411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.replacements 2280083 # number of replacements 98511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tagsinuse 13449.950084 # Cycle average of tags in use 98611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.total_refs 17410791 # Total number of references to valid blocks. 98711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.sampled_refs 2296131 # Sample count of references to valid blocks. 98811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.avg_refs 7.582664 # Average number of references to valid blocks. 98910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 9726491516500 # Cycle when the warmup percentage was hit. 99011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 5225.723861 # Average occupied blocks per requestor 99111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 68.459971 # Average occupied blocks per requestor 99211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 87.577044 # Average occupied blocks per requestor 99311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2849.184130 # Average occupied blocks per requestor 99411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.data 5219.005079 # Average occupied blocks per requestor 99511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.318953 # Average percentage of cache occupancy 99611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004178 # Average percentage of cache occupancy 99711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005345 # Average percentage of cache occupancy 99811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.173900 # Average percentage of cache occupancy 99911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.data 0.318543 # Average percentage of cache occupancy 100011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.820920 # Average percentage of cache occupancy 100111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 105 # Occupied blocks per task id 100211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 15943 # Occupied blocks per task id 100310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id 100411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id 100511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 68 # Occupied blocks per task id 100611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 11 # Occupied blocks per task id 100711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 23 # Occupied blocks per task id 100811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id 100911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1612 # Occupied blocks per task id 101011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5944 # Occupied blocks per task id 101111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4501 # Occupied blocks per task id 101211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3801 # Occupied blocks per task id 101311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006409 # Percentage of cache occupancy per task id 101411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.973083 # Percentage of cache occupancy per task id 101511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tag_accesses 360471879 # Number of tag accesses 101611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.data_accesses 360471879 # Number of data accesses 101711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 324612 # number of ReadReq hits 101811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 139654 # number of ReadReq hits 101911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 464266 # number of ReadReq hits 102011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_hits::writebacks 4029235 # number of Writeback hits 102111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_hits::total 4029235 # number of Writeback hits 102211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::cpu1.data 3866 # number of UpgradeReq hits 102311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::total 3866 # number of UpgradeReq hits 102411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 614223 # number of ReadExReq hits 102511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 614223 # number of ReadExReq hits 102611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4216163 # number of ReadCleanReq hits 102711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 4216163 # number of ReadCleanReq hits 102811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3057520 # number of ReadSharedReq hits 102911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 3057520 # number of ReadSharedReq hits 103011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::cpu1.data 161092 # number of InvalidateReq hits 103111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::total 161092 # number of InvalidateReq hits 103211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 324612 # number of demand (read+write) hits 103311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 139654 # number of demand (read+write) hits 103411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 4216163 # number of demand (read+write) hits 103511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 3671743 # number of demand (read+write) hits 103611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::total 8352172 # number of demand (read+write) hits 103711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 324612 # number of overall hits 103811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 139654 # number of overall hits 103911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 4216163 # number of overall hits 104011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 3671743 # number of overall hits 104111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::total 8352172 # number of overall hits 104211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12357 # number of ReadReq misses 104311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9710 # number of ReadReq misses 104411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 22067 # number of ReadReq misses 104511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 133787 # number of UpgradeReq misses 104611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 133787 # number of UpgradeReq misses 104711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 158898 # number of SCUpgradeReq misses 104811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 158898 # number of SCUpgradeReq misses 104911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 701667 # number of ReadExReq misses 105011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 701667 # number of ReadExReq misses 105111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 525646 # number of ReadCleanReq misses 105211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 525646 # number of ReadCleanReq misses 105311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1239873 # number of ReadSharedReq misses 105411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 1239873 # number of ReadSharedReq misses 105511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::cpu1.data 265754 # number of InvalidateReq misses 105611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::total 265754 # number of InvalidateReq misses 105711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12357 # number of demand (read+write) misses 105811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 9710 # number of demand (read+write) misses 105911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 525646 # number of demand (read+write) misses 106011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 1941540 # number of demand (read+write) misses 106111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::total 2489253 # number of demand (read+write) misses 106211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12357 # number of overall misses 106311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 9710 # number of overall misses 106411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 525646 # number of overall misses 106511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 1941540 # number of overall misses 106611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::total 2489253 # number of overall misses 106711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 336969 # number of ReadReq accesses(hits+misses) 106811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 149364 # number of ReadReq accesses(hits+misses) 106911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 486333 # number of ReadReq accesses(hits+misses) 107011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_accesses::writebacks 4029235 # number of Writeback accesses(hits+misses) 107111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_accesses::total 4029235 # number of Writeback accesses(hits+misses) 107211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 137653 # number of UpgradeReq accesses(hits+misses) 107311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 137653 # number of UpgradeReq accesses(hits+misses) 107411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 158898 # number of SCUpgradeReq accesses(hits+misses) 107511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 158898 # number of SCUpgradeReq accesses(hits+misses) 107610726SN/Asystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1315890 # number of ReadExReq accesses(hits+misses) 107710726SN/Asystem.cpu1.l2cache.ReadExReq_accesses::total 1315890 # number of ReadExReq accesses(hits+misses) 107810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4741809 # number of ReadCleanReq accesses(hits+misses) 107910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 4741809 # number of ReadCleanReq accesses(hits+misses) 108010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4297393 # number of ReadSharedReq accesses(hits+misses) 108110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 4297393 # number of ReadSharedReq accesses(hits+misses) 108210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 426846 # number of InvalidateReq accesses(hits+misses) 108310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::total 426846 # number of InvalidateReq accesses(hits+misses) 108411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 336969 # number of demand (read+write) accesses 108511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 149364 # number of demand (read+write) accesses 108610726SN/Asystem.cpu1.l2cache.demand_accesses::cpu1.inst 4741809 # number of demand (read+write) accesses 108710726SN/Asystem.cpu1.l2cache.demand_accesses::cpu1.data 5613283 # number of demand (read+write) accesses 108811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::total 10841425 # number of demand (read+write) accesses 108911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 336969 # number of overall (read+write) accesses 109011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 149364 # number of overall (read+write) accesses 109110726SN/Asystem.cpu1.l2cache.overall_accesses::cpu1.inst 4741809 # number of overall (read+write) accesses 109210726SN/Asystem.cpu1.l2cache.overall_accesses::cpu1.data 5613283 # number of overall (read+write) accesses 109311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::total 10841425 # number of overall (read+write) accesses 109411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.036671 # miss rate for ReadReq accesses 109511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.065009 # miss rate for ReadReq accesses 109611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.045374 # miss rate for ReadReq accesses 109711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.971915 # miss rate for UpgradeReq accesses 109811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 0.971915 # miss rate for UpgradeReq accesses 109910585SN/Asystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 110010585SN/Asystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 110111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.533226 # miss rate for ReadExReq accesses 110211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.533226 # miss rate for ReadExReq accesses 110311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.110853 # miss rate for ReadCleanReq accesses 110411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.110853 # miss rate for ReadCleanReq accesses 110511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.288517 # miss rate for ReadSharedReq accesses 110611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.288517 # miss rate for ReadSharedReq accesses 110711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.622599 # miss rate for InvalidateReq accesses 110811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::total 0.622599 # miss rate for InvalidateReq accesses 110911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.036671 # miss rate for demand accesses 111011138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.065009 # miss rate for demand accesses 111111138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.110853 # miss rate for demand accesses 111211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.345883 # miss rate for demand accesses 111311138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.229606 # miss rate for demand accesses 111411138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.036671 # miss rate for overall accesses 111511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.065009 # miss rate for overall accesses 111611138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.110853 # miss rate for overall accesses 111711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.345883 # miss rate for overall accesses 111811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.229606 # miss rate for overall accesses 111910585SN/Asystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 112010585SN/Asystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 112110585SN/Asystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 112210585SN/Asystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 112310585SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 112410585SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 112510585SN/Asystem.cpu1.l2cache.fast_writes 0 # number of fast writes performed 112610585SN/Asystem.cpu1.l2cache.cache_copies 0 # number of cache copies performed 112711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::writebacks 1182496 # number of writebacks 112811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::total 1182496 # number of writebacks 112910585SN/Asystem.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 113011138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_requests 22040452 # Total number of requests made to the snoop filter. 113111138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_requests 11258515 # Number of requests hitting in the snoop filter with a single holder of the requested data. 113211138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_requests 368 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 113311138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_snoops 465210 # Total number of snoops made to the snoop filter. 113411138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_snoops 465207 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 113511138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 113610892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 606211 # Transaction distribution 113710726SN/Asystem.cpu1.toL2Bus.trans_dist::ReadResp 9645413 # Transaction distribution 113810726SN/Asystem.cpu1.toL2Bus.trans_dist::WriteReq 6383 # Transaction distribution 113910726SN/Asystem.cpu1.toL2Bus.trans_dist::WriteResp 6383 # Transaction distribution 114011138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::Writeback 4029235 # Transaction distribution 114111138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::CleanEvict 6656743 # Transaction distribution 114211138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 137653 # Transaction distribution 114311138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 158898 # Transaction distribution 114411138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 296551 # Transaction distribution 114510726SN/Asystem.cpu1.toL2Bus.trans_dist::ReadExReq 1315890 # Transaction distribution 114610726SN/Asystem.cpu1.toL2Bus.trans_dist::ReadExResp 1315890 # Transaction distribution 114710892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 4741809 # Transaction distribution 114810892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 4297393 # Transaction distribution 114910892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateReq 426846 # Transaction distribution 115010892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateResp 426846 # Transaction distribution 115111138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14225112 # Packet count per connected master and slave (bytes) 115211138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18643588 # Packet count per connected master and slave (bytes) 115310726SN/Asystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 364008 # Packet count per connected master and slave (bytes) 115410726SN/Asystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 835436 # Packet count per connected master and slave (bytes) 115511138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count::total 34068144 # Packet count per connected master and slave (bytes) 115610726SN/Asystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 303476296 # Cumulative packet size per connected master and slave (bytes) 115711138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 617159548 # Cumulative packet size per connected master and slave (bytes) 115810726SN/Asystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1456032 # Cumulative packet size per connected master and slave (bytes) 115910726SN/Asystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3341744 # Cumulative packet size per connected master and slave (bytes) 116011138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size::total 925433620 # Cumulative packet size per connected master and slave (bytes) 116111138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoops 4444908 # Total snoops (count) 116211138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 26656221 # Request fanout histogram 116311138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 0.027820 # Request fanout histogram 116411138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.164457 # Request fanout histogram 116510585SN/Asystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 116611138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 25914657 97.22% 97.22% # Request fanout histogram 116711138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 741561 2.78% 100.00% # Request fanout histogram 116811138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram 116910585SN/Asystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 117011138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 117110827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 117211138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 26656221 # Request fanout histogram 117310726SN/Asystem.iobus.trans_dist::ReadReq 40295 # Transaction distribution 117410726SN/Asystem.iobus.trans_dist::ReadResp 40295 # Transaction distribution 117510726SN/Asystem.iobus.trans_dist::WriteReq 136634 # Transaction distribution 117610892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 136634 # Transaction distribution 117710726SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47636 # Packet count per connected master and slave (bytes) 117810585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 117910585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 118010585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 118110585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 118210585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 118310585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 118410585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 118510585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 118610585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 118710585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 118810585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 118910585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 119010585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 119110585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 119210726SN/Asystem.iobus.pkt_count_system.bridge.master::total 122570 # Packet count per connected master and slave (bytes) 119310726SN/Asystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231208 # Packet count per connected master and slave (bytes) 119410726SN/Asystem.iobus.pkt_count_system.realview.ide.dma::total 231208 # Packet count per connected master and slave (bytes) 119510585SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 119610585SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 119710726SN/Asystem.iobus.pkt_count::total 353858 # Packet count per connected master and slave (bytes) 119810726SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47656 # Cumulative packet size per connected master and slave (bytes) 119910585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 120010585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 120110585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 120210585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 120310585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 120410585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 120510585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 120610585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 120710585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 120810585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 120910585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 121010585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 121110585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 121210585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 121310726SN/Asystem.iobus.pkt_size_system.bridge.master::total 155677 # Cumulative packet size per connected master and slave (bytes) 121410726SN/Asystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338848 # Cumulative packet size per connected master and slave (bytes) 121510726SN/Asystem.iobus.pkt_size_system.realview.ide.dma::total 7338848 # Cumulative packet size per connected master and slave (bytes) 121610585SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 121710585SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 121810726SN/Asystem.iobus.pkt_size::total 7496611 # Cumulative packet size per connected master and slave (bytes) 121910726SN/Asystem.iocache.tags.replacements 115585 # number of replacements 122010726SN/Asystem.iocache.tags.tagsinuse 11.290896 # Cycle average of tags in use 122110585SN/Asystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 122210726SN/Asystem.iocache.tags.sampled_refs 115601 # Sample count of references to valid blocks. 122310585SN/Asystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 122410585SN/Asystem.iocache.tags.warmup_cycle 9107775783009 # Cycle when the warmup percentage was hit. 122510726SN/Asystem.iocache.tags.occ_blocks::realview.ethernet 3.851982 # Average occupied blocks per requestor 122610726SN/Asystem.iocache.tags.occ_blocks::realview.ide 7.438915 # Average occupied blocks per requestor 122710726SN/Asystem.iocache.tags.occ_percent::realview.ethernet 0.240749 # Average percentage of cache occupancy 122810726SN/Asystem.iocache.tags.occ_percent::realview.ide 0.464932 # Average percentage of cache occupancy 122910726SN/Asystem.iocache.tags.occ_percent::total 0.705681 # Average percentage of cache occupancy 123010585SN/Asystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 123110585SN/Asystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 123210585SN/Asystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 123310726SN/Asystem.iocache.tags.tag_accesses 1040793 # Number of tag accesses 123410726SN/Asystem.iocache.tags.data_accesses 1040793 # Number of data accesses 123510585SN/Asystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 123610726SN/Asystem.iocache.ReadReq_misses::realview.ide 8876 # number of ReadReq misses 123710726SN/Asystem.iocache.ReadReq_misses::total 8913 # number of ReadReq misses 123810585SN/Asystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 123910585SN/Asystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 124010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 124110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 124210585SN/Asystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 124310726SN/Asystem.iocache.demand_misses::realview.ide 8876 # number of demand (read+write) misses 124410726SN/Asystem.iocache.demand_misses::total 8916 # number of demand (read+write) misses 124510585SN/Asystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 124610726SN/Asystem.iocache.overall_misses::realview.ide 8876 # number of overall misses 124710726SN/Asystem.iocache.overall_misses::total 8916 # number of overall misses 124810585SN/Asystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 124910726SN/Asystem.iocache.ReadReq_accesses::realview.ide 8876 # number of ReadReq accesses(hits+misses) 125010726SN/Asystem.iocache.ReadReq_accesses::total 8913 # number of ReadReq accesses(hits+misses) 125110585SN/Asystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 125210585SN/Asystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 125310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 125410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 125510585SN/Asystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 125610726SN/Asystem.iocache.demand_accesses::realview.ide 8876 # number of demand (read+write) accesses 125710726SN/Asystem.iocache.demand_accesses::total 8916 # number of demand (read+write) accesses 125810585SN/Asystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 125910726SN/Asystem.iocache.overall_accesses::realview.ide 8876 # number of overall (read+write) accesses 126010726SN/Asystem.iocache.overall_accesses::total 8916 # number of overall (read+write) accesses 126110585SN/Asystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 126210585SN/Asystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 126310585SN/Asystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 126410585SN/Asystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 126510585SN/Asystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 126610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 126710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 126810585SN/Asystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 126910585SN/Asystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 127010585SN/Asystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 127110585SN/Asystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 127210585SN/Asystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 127310585SN/Asystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 127410585SN/Asystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 127510585SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 127610585SN/Asystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 127710585SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 127810585SN/Asystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 127910585SN/Asystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 128010585SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 128110585SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 128210585SN/Asystem.iocache.writebacks::writebacks 106694 # number of writebacks 128310585SN/Asystem.iocache.writebacks::total 106694 # number of writebacks 128410585SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 128511138Sandreas.hansson@arm.comsystem.l2c.tags.replacements 1756378 # number of replacements 128611138Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 62298.874763 # Cycle average of tags in use 128711138Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 4716146 # Total number of references to valid blocks. 128811138Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 1814465 # Sample count of references to valid blocks. 128911138Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 2.599194 # Average number of references to valid blocks. 129010892Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 129111138Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 34280.883889 # Average occupied blocks per requestor 129211138Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 45.238820 # Average occupied blocks per requestor 129311138Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 58.953050 # Average occupied blocks per requestor 129411138Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 3333.891398 # Average occupied blocks per requestor 129511138Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 6982.835280 # Average occupied blocks per requestor 129611138Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 308.005625 # Average occupied blocks per requestor 129711138Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 424.754545 # Average occupied blocks per requestor 129811138Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 2990.314104 # Average occupied blocks per requestor 129911138Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 13873.998053 # Average occupied blocks per requestor 130011138Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.523085 # Average percentage of cache occupancy 130111138Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.000690 # Average percentage of cache occupancy 130211138Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.000900 # Average percentage of cache occupancy 130311138Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.050871 # Average percentage of cache occupancy 130411138Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.106550 # Average percentage of cache occupancy 130511138Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.004700 # Average percentage of cache occupancy 130611138Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.006481 # Average percentage of cache occupancy 130711138Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.045629 # Average percentage of cache occupancy 130811138Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.211700 # Average percentage of cache occupancy 130911138Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.950605 # Average percentage of cache occupancy 131011138Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 228 # Occupied blocks per task id 131111138Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 57859 # Occupied blocks per task id 131211138Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 131311138Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 227 # Occupied blocks per task id 131411138Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 131511138Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 548 # Occupied blocks per task id 131611138Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 3455 # Occupied blocks per task id 131711138Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 5562 # Occupied blocks per task id 131811138Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 48240 # Occupied blocks per task id 131911138Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.003479 # Percentage of cache occupancy per task id 132011138Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.882858 # Percentage of cache occupancy per task id 132111138Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 74820318 # Number of tag accesses 132211138Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 74820318 # Number of data accesses 132311138Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::writebacks 2753989 # number of Writeback hits 132411138Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::total 2753989 # number of Writeback hits 132511138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 13132 # number of UpgradeReq hits 132611138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 10939 # number of UpgradeReq hits 132711138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 24071 # number of UpgradeReq hits 132811138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 1512 # number of SCUpgradeReq hits 132911138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 1301 # number of SCUpgradeReq hits 133011138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 2813 # number of SCUpgradeReq hits 133111138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 319600 # number of ReadExReq hits 133211138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 264468 # number of ReadExReq hits 133311138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 584068 # number of ReadExReq hits 133411138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6283 # number of ReadSharedReq hits 133511138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 4584 # number of ReadSharedReq hits 133611138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 512119 # number of ReadSharedReq hits 133711138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 747634 # number of ReadSharedReq hits 133811138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5445 # number of ReadSharedReq hits 133911138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 3568 # number of ReadSharedReq hits 134011138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 486435 # number of ReadSharedReq hits 134111138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 695595 # number of ReadSharedReq hits 134211138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::total 2461663 # number of ReadSharedReq hits 134311138Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 6283 # number of demand (read+write) hits 134411138Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 4584 # number of demand (read+write) hits 134511138Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 512119 # number of demand (read+write) hits 134611138Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 1067234 # number of demand (read+write) hits 134711138Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 5445 # number of demand (read+write) hits 134811138Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 3568 # number of demand (read+write) hits 134911138Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 486435 # number of demand (read+write) hits 135011138Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 960063 # number of demand (read+write) hits 135111138Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 3045731 # number of demand (read+write) hits 135211138Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 6283 # number of overall hits 135311138Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 4584 # number of overall hits 135411138Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 512119 # number of overall hits 135511138Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 1067234 # number of overall hits 135611138Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 5445 # number of overall hits 135711138Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 3568 # number of overall hits 135811138Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 486435 # number of overall hits 135911138Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 960063 # number of overall hits 136011138Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 3045731 # number of overall hits 136111138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 58697 # number of UpgradeReq misses 136211138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 54120 # number of UpgradeReq misses 136311138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 112817 # number of UpgradeReq misses 136411138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 7808 # number of SCUpgradeReq misses 136511138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 7401 # number of SCUpgradeReq misses 136611138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 15209 # number of SCUpgradeReq misses 136711138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 816140 # number of ReadExReq misses 136811138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 547219 # number of ReadExReq misses 136911138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 1363359 # number of ReadExReq misses 137011138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2385 # number of ReadSharedReq misses 137111138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 1987 # number of ReadSharedReq misses 137211138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 56162 # number of ReadSharedReq misses 137311138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 181808 # number of ReadSharedReq misses 137411138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3458 # number of ReadSharedReq misses 137511138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.itb.walker 3451 # number of ReadSharedReq misses 137611138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 39211 # number of ReadSharedReq misses 137711138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 186749 # number of ReadSharedReq misses 137811138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::total 475211 # number of ReadSharedReq misses 137911138Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 2385 # number of demand (read+write) misses 138011138Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 1987 # number of demand (read+write) misses 138111138Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 56162 # number of demand (read+write) misses 138211138Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 997948 # number of demand (read+write) misses 138311138Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 3458 # number of demand (read+write) misses 138411138Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.itb.walker 3451 # number of demand (read+write) misses 138511138Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 39211 # number of demand (read+write) misses 138611138Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 733968 # number of demand (read+write) misses 138711138Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 1838570 # number of demand (read+write) misses 138811138Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 2385 # number of overall misses 138911138Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 1987 # number of overall misses 139011138Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 56162 # number of overall misses 139111138Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 997948 # number of overall misses 139211138Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 3458 # number of overall misses 139311138Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.itb.walker 3451 # number of overall misses 139411138Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 39211 # number of overall misses 139511138Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 733968 # number of overall misses 139611138Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 1838570 # number of overall misses 139711138Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::writebacks 2753989 # number of Writeback accesses(hits+misses) 139811138Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::total 2753989 # number of Writeback accesses(hits+misses) 139911138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 71829 # number of UpgradeReq accesses(hits+misses) 140011138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 65059 # number of UpgradeReq accesses(hits+misses) 140111138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 136888 # number of UpgradeReq accesses(hits+misses) 140211138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 9320 # number of SCUpgradeReq accesses(hits+misses) 140311138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 8702 # number of SCUpgradeReq accesses(hits+misses) 140411138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 18022 # number of SCUpgradeReq accesses(hits+misses) 140511138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 1135740 # number of ReadExReq accesses(hits+misses) 140611138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 811687 # number of ReadExReq accesses(hits+misses) 140711138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 1947427 # number of ReadExReq accesses(hits+misses) 140810892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8668 # number of ReadSharedReq accesses(hits+misses) 140911138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6571 # number of ReadSharedReq accesses(hits+misses) 141011138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 568281 # number of ReadSharedReq accesses(hits+misses) 141111138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 929442 # number of ReadSharedReq accesses(hits+misses) 141211138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8903 # number of ReadSharedReq accesses(hits+misses) 141311138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7019 # number of ReadSharedReq accesses(hits+misses) 141411138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 525646 # number of ReadSharedReq accesses(hits+misses) 141511138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 882344 # number of ReadSharedReq accesses(hits+misses) 141611138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::total 2936874 # number of ReadSharedReq accesses(hits+misses) 141710892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 8668 # number of demand (read+write) accesses 141811138Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 6571 # number of demand (read+write) accesses 141911138Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 568281 # number of demand (read+write) accesses 142011138Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 2065182 # number of demand (read+write) accesses 142111138Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 8903 # number of demand (read+write) accesses 142211138Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 7019 # number of demand (read+write) accesses 142311138Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 525646 # number of demand (read+write) accesses 142411138Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 1694031 # number of demand (read+write) accesses 142511138Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 4884301 # number of demand (read+write) accesses 142610892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 8668 # number of overall (read+write) accesses 142711138Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 6571 # number of overall (read+write) accesses 142811138Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 568281 # number of overall (read+write) accesses 142911138Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 2065182 # number of overall (read+write) accesses 143011138Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 8903 # number of overall (read+write) accesses 143111138Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 7019 # number of overall (read+write) accesses 143211138Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 525646 # number of overall (read+write) accesses 143311138Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 1694031 # number of overall (read+write) accesses 143411138Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 4884301 # number of overall (read+write) accesses 143511138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.817177 # miss rate for UpgradeReq accesses 143611138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.831860 # miss rate for UpgradeReq accesses 143711138Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.824156 # miss rate for UpgradeReq accesses 143811138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.837768 # miss rate for SCUpgradeReq accesses 143911138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.850494 # miss rate for SCUpgradeReq accesses 144011138Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.843913 # miss rate for SCUpgradeReq accesses 144111138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.718598 # miss rate for ReadExReq accesses 144211138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.674175 # miss rate for ReadExReq accesses 144311138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.700082 # miss rate for ReadExReq accesses 144411138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.275150 # miss rate for ReadSharedReq accesses 144511138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.302389 # miss rate for ReadSharedReq accesses 144611138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.098828 # miss rate for ReadSharedReq accesses 144711138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.195610 # miss rate for ReadSharedReq accesses 144811138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.388408 # miss rate for ReadSharedReq accesses 144911138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.491665 # miss rate for ReadSharedReq accesses 145011138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.074596 # miss rate for ReadSharedReq accesses 145111138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.211651 # miss rate for ReadSharedReq accesses 145211138Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.161808 # miss rate for ReadSharedReq accesses 145311138Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.275150 # miss rate for demand accesses 145411138Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.302389 # miss rate for demand accesses 145511138Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.098828 # miss rate for demand accesses 145611138Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.483225 # miss rate for demand accesses 145711138Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.388408 # miss rate for demand accesses 145811138Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.491665 # miss rate for demand accesses 145911138Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.074596 # miss rate for demand accesses 146011138Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.433267 # miss rate for demand accesses 146111138Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.376424 # miss rate for demand accesses 146211138Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.275150 # miss rate for overall accesses 146311138Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.302389 # miss rate for overall accesses 146411138Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.098828 # miss rate for overall accesses 146511138Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.483225 # miss rate for overall accesses 146611138Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.388408 # miss rate for overall accesses 146711138Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.491665 # miss rate for overall accesses 146811138Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.074596 # miss rate for overall accesses 146911138Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.433267 # miss rate for overall accesses 147011138Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.376424 # miss rate for overall accesses 147110515SN/Asystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 147210515SN/Asystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 147310515SN/Asystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 147410515SN/Asystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 147510515SN/Asystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 147610515SN/Asystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 147710515SN/Asystem.l2c.fast_writes 0 # number of fast writes performed 147810515SN/Asystem.l2c.cache_copies 0 # number of cache copies performed 147911138Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 1471188 # number of writebacks 148011138Sandreas.hansson@arm.comsystem.l2c.writebacks::total 1471188 # number of writebacks 148110515SN/Asystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 148210892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 82131 # Transaction distribution 148311138Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 566255 # Transaction distribution 148410827Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 38802 # Transaction distribution 148510827Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 38802 # Transaction distribution 148611138Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 1577882 # Transaction distribution 148711138Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 244930 # Transaction distribution 148811138Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 328773 # Transaction distribution 148911138Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 314660 # Transaction distribution 149011138Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 150374 # Transaction distribution 149111138Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 1610566 # Transaction distribution 149211138Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 1341014 # Transaction distribution 149311138Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 484124 # Transaction distribution 149410892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 106728 # Transaction distribution 149510892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 106728 # Transaction distribution 149610726SN/Asystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122570 # Packet count per connected master and slave (bytes) 149710585SN/Asystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 149810726SN/Asystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27558 # Packet count per connected master and slave (bytes) 149911138Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6497230 # Packet count per connected master and slave (bytes) 150011138Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 6647450 # Packet count per connected master and slave (bytes) 150111138Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 344319 # Packet count per connected master and slave (bytes) 150211138Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 344319 # Packet count per connected master and slave (bytes) 150311138Sandreas.hansson@arm.comsystem.membus.pkt_count::total 6991769 # Packet count per connected master and slave (bytes) 150410726SN/Asystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155677 # Cumulative packet size per connected master and slave (bytes) 150510585SN/Asystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 150610726SN/Asystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55116 # Cumulative packet size per connected master and slave (bytes) 150711138Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 210588188 # Cumulative packet size per connected master and slave (bytes) 150811138Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 210799185 # Cumulative packet size per connected master and slave (bytes) 150910892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7398848 # Cumulative packet size per connected master and slave (bytes) 151010892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7398848 # Cumulative packet size per connected master and slave (bytes) 151111138Sandreas.hansson@arm.comsystem.membus.pkt_size::total 218198033 # Cumulative packet size per connected master and slave (bytes) 151210585SN/Asystem.membus.snoops 0 # Total snoops (count) 151311138Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 4791150 # Request fanout histogram 151410585SN/Asystem.membus.snoop_fanout::mean 1 # Request fanout histogram 151510585SN/Asystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 151610585SN/Asystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 151710585SN/Asystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 151811138Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 4791150 100.00% 100.00% # Request fanout histogram 151910585SN/Asystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 152010585SN/Asystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 152110585SN/Asystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 152210585SN/Asystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 152311138Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 4791150 # Request fanout histogram 152410515SN/Asystem.realview.ethernet.txBytes 966 # Bytes Transmitted 152510515SN/Asystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 152610515SN/Asystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 152710515SN/Asystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 152810515SN/Asystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 152910515SN/Asystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 153010515SN/Asystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 153110515SN/Asystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 153210515SN/Asystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 153310515SN/Asystem.realview.ethernet.totBandwidth 164 # Total Bandwidth (bits/s) 153410515SN/Asystem.realview.ethernet.totPackets 3 # Total Packets 153510515SN/Asystem.realview.ethernet.totBytes 966 # Total Bytes 153610515SN/Asystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 153710515SN/Asystem.realview.ethernet.txBandwidth 164 # Transmit Bandwidth (bits/s) 153810515SN/Asystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 153910515SN/Asystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 154010515SN/Asystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 154110515SN/Asystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 154210515SN/Asystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 154310515SN/Asystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 154410515SN/Asystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 154510515SN/Asystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 154610515SN/Asystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 154710515SN/Asystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 154810515SN/Asystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 154910515SN/Asystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 155010515SN/Asystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 155110515SN/Asystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 155210515SN/Asystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 155310515SN/Asystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 155410515SN/Asystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 155510515SN/Asystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 155610515SN/Asystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 155710515SN/Asystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 155810515SN/Asystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 155910515SN/Asystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 156010515SN/Asystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 156110515SN/Asystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 156210515SN/Asystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 156310515SN/Asystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 156410515SN/Asystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 156510515SN/Asystem.realview.ethernet.droppedPackets 0 # number of packets dropped 156611103Snilay@cs.wisc.edusystem.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks 156711014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks 156811014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks 156911014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks 157011014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks 157111014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks 157211014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks 157311014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks 157411014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks 157511014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks 157611138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_requests 11435399 # Total number of requests made to the snoop filter. 157711138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 5875226 # Number of requests hitting in the snoop filter with a single holder of the requested data. 157811138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 1762842 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 157911138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 121928 # Total number of snoops made to the snoop filter. 158011138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 112531 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 158111138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 9397 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 158210892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 82133 # Transaction distribution 158311138Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 3715978 # Transaction distribution 158410827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 38802 # Transaction distribution 158510827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 38802 # Transaction distribution 158611138Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::Writeback 2753989 # Transaction distribution 158711138Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::CleanEvict 1064741 # Transaction distribution 158811138Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 330496 # Transaction distribution 158911138Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 317473 # Transaction distribution 159011138Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 647969 # Transaction distribution 159111138Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 2216979 # Transaction distribution 159211138Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 2216979 # Transaction distribution 159311138Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 3633845 # Transaction distribution 159411138Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9232436 # Packet count per connected master and slave (bytes) 159511138Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7825750 # Packet count per connected master and slave (bytes) 159611138Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 17058186 # Packet count per connected master and slave (bytes) 159711138Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 301171869 # Cumulative packet size per connected master and slave (bytes) 159811138Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 249940932 # Cumulative packet size per connected master and slave (bytes) 159911138Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 551112801 # Cumulative packet size per connected master and slave (bytes) 160011138Sandreas.hansson@arm.comsystem.toL2Bus.snoops 1989284 # Total snoops (count) 160111138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 13543939 # Request fanout histogram 160211138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 0.291452 # Request fanout histogram 160311138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.455956 # Request fanout histogram 160410515SN/Asystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 160511138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::0 9605923 70.92% 70.92% # Request fanout histogram 160611138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 3928619 29.01% 99.93% # Request fanout histogram 160711138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 9397 0.07% 100.00% # Request fanout histogram 160810515SN/Asystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 160911138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 161010515SN/Asystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 161111138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 13543939 # Request fanout histogram 161210515SN/A 161310515SN/A---------- End Simulation Statistics ---------- 1614