stats.txt revision 10944
110515SN/A 210515SN/A---------- Begin Simulation Statistics ---------- 310726SN/Asim_seconds 47.216814 # Number of seconds simulated 410726SN/Asim_ticks 47216814145000 # Number of ticks simulated 510726SN/Afinal_tick 47216814145000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710944Sandreas.hansson@arm.comhost_inst_rate 1175010 # Simulator instruction rate (inst/s) 810944Sandreas.hansson@arm.comhost_op_rate 1382295 # Simulator op (including micro ops) rate (op/s) 910944Sandreas.hansson@arm.comhost_tick_rate 56876129335 # Simulator tick rate (ticks/s) 1010944Sandreas.hansson@arm.comhost_mem_usage 728240 # Number of bytes of host memory used 1110944Sandreas.hansson@arm.comhost_seconds 830.17 # Real time elapsed on the host 1210726SN/Asim_insts 975457230 # Number of instructions simulated 1310726SN/Asim_ops 1147538415 # Number of ops (including micro ops) simulated 1410515SN/Asystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SN/Asystem.clk_domain.clock 1000 # Clock period in ticks 1610892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 152256 # Number of bytes read from this memory 1710892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 127104 # Number of bytes read from this memory 1810892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 3638260 # Number of bytes read from this memory 1910892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 62923528 # Number of bytes read from this memory 2010892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 221632 # Number of bytes read from this memory 2110892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.itb.walker 219968 # Number of bytes read from this memory 2210892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 2412168 # Number of bytes read from this memory 2310892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 46368688 # Number of bytes read from this memory 2410892Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 419904 # Number of bytes read from this memory 2510892Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 116483508 # Number of bytes read from this memory 2610892Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 3638260 # Number of instructions bytes read from this memory 2710892Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 2412168 # Number of instructions bytes read from this memory 2810892Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 6050428 # Number of instructions bytes read from this memory 2910892Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 101038848 # Number of bytes written to this memory 3010827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 3110585SN/Asystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3210892Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 101059432 # Number of bytes written to this memory 3310892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 2379 # Number of read requests responded to by this memory 3410892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.itb.walker 1986 # Number of read requests responded to by this memory 3510892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 97255 # Number of read requests responded to by this memory 3610892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 983193 # Number of read requests responded to by this memory 3710892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 3463 # Number of read requests responded to by this memory 3810892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.itb.walker 3437 # Number of read requests responded to by this memory 3910892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 37797 # Number of read requests responded to by this memory 4010892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 724527 # Number of read requests responded to by this memory 4110892Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 6561 # Number of read requests responded to by this memory 4210892Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1860598 # Number of read requests responded to by this memory 4310892Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 1578732 # Number of write requests responded to by this memory 4410827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 4510585SN/Asystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 4610892Sandreas.hansson@arm.comsystem.physmem.num_writes::total 1581306 # Number of write requests responded to by this memory 4710892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 3225 # Total read bandwidth from this memory (bytes/s) 4810892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.itb.walker 2692 # Total read bandwidth from this memory (bytes/s) 4910892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 77054 # Total read bandwidth from this memory (bytes/s) 5010892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 1332651 # Total read bandwidth from this memory (bytes/s) 5110892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 4694 # Total read bandwidth from this memory (bytes/s) 5210892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.itb.walker 4659 # Total read bandwidth from this memory (bytes/s) 5310892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 51087 # Total read bandwidth from this memory (bytes/s) 5410892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 982038 # Total read bandwidth from this memory (bytes/s) 5510892Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 8893 # Total read bandwidth from this memory (bytes/s) 5610892Sandreas.hansson@arm.comsystem.physmem.bw_read::total 2466992 # Total read bandwidth from this memory (bytes/s) 5710892Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 77054 # Instruction read bandwidth from this memory (bytes/s) 5810892Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 51087 # Instruction read bandwidth from this memory (bytes/s) 5910892Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 128141 # Instruction read bandwidth from this memory (bytes/s) 6010892Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 2139891 # Write bandwidth from this memory (bytes/s) 6110827Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu0.data 436 # Write bandwidth from this memory (bytes/s) 6210585SN/Asystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 6310892Sandreas.hansson@arm.comsystem.physmem.bw_write::total 2140327 # Write bandwidth from this memory (bytes/s) 6410892Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 2139891 # Total bandwidth to/from this memory (bytes/s) 6510892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 3225 # Total bandwidth to/from this memory (bytes/s) 6610892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.itb.walker 2692 # Total bandwidth to/from this memory (bytes/s) 6710892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 77054 # Total bandwidth to/from this memory (bytes/s) 6810892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 1333087 # Total bandwidth to/from this memory (bytes/s) 6910892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 4694 # Total bandwidth to/from this memory (bytes/s) 7010892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.itb.walker 4659 # Total bandwidth to/from this memory (bytes/s) 7110892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 51087 # Total bandwidth to/from this memory (bytes/s) 7210892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 982038 # Total bandwidth to/from this memory (bytes/s) 7310892Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 8893 # Total bandwidth to/from this memory (bytes/s) 7410892Sandreas.hansson@arm.comsystem.physmem.bw_total::total 4607319 # Total bandwidth to/from this memory (bytes/s) 7510515SN/Asystem.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 7610515SN/Asystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 7710515SN/Asystem.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 7810515SN/Asystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 7910515SN/Asystem.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 8010515SN/Asystem.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 8110515SN/Asystem.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 8210515SN/Asystem.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 8310515SN/Asystem.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 8410515SN/Asystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 8510515SN/Asystem.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 8610515SN/Asystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 8710515SN/Asystem.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 8810515SN/Asystem.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 8910515SN/Asystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 9010515SN/Asystem.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 9110515SN/Asystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 9210515SN/Asystem.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 9310515SN/Asystem.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 9410515SN/Asystem.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 9510515SN/Asystem.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 9610515SN/Asystem.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 9710515SN/Asystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 9810515SN/Asystem.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 9910515SN/Asystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 10010515SN/Asystem.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 10110585SN/Asystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 10210585SN/Asystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 10310585SN/Asystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 10410585SN/Asystem.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 10510585SN/Asystem.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 10610585SN/Asystem.cf0.dma_write_txs 1670 # Number of DMA write transactions. 10710515SN/Asystem.cpu_clk_domain.clock 500 # Clock period in ticks 10810628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 10910628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 11010628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 11110628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 11210628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 11310628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 11410628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 11510628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 11610585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 11710585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 11810585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 11910585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 12010585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 12110585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 12210585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 12310585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 12410585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 12510585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 12610585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 12710585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 12810585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 12910585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 13010585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 13110585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 13210585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 13310585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 13410585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 13510585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 13610585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 13710726SN/Asystem.cpu0.dtb.walker.walks 125229 # Table walker walks requested 13810726SN/Asystem.cpu0.dtb.walker.walksLong 125229 # Table walker walks initiated with long descriptors 13910726SN/Asystem.cpu0.dtb.walker.walkWaitTime::samples 125229 # Table walker wait (enqueue to first request) latency 14010726SN/Asystem.cpu0.dtb.walker.walkWaitTime::0 125229 100.00% 100.00% # Table walker wait (enqueue to first request) latency 14110726SN/Asystem.cpu0.dtb.walker.walkWaitTime::total 125229 # Table walker wait (enqueue to first request) latency 14210628SN/Asystem.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution 14310628SN/Asystem.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution 14410628SN/Asystem.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution 14510726SN/Asystem.cpu0.dtb.walker.walkPageSizes::4K 96746 89.71% 89.71% # Table walker page sizes translated 14610726SN/Asystem.cpu0.dtb.walker.walkPageSizes::2M 11103 10.29% 100.00% # Table walker page sizes translated 14710726SN/Asystem.cpu0.dtb.walker.walkPageSizes::total 107849 # Table walker page sizes translated 14810726SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 125229 # Table walker requests started/completed, data/inst 14910628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 15010726SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 125229 # Table walker requests started/completed, data/inst 15110726SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107849 # Table walker requests started/completed, data/inst 15210628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 15310726SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107849 # Table walker requests started/completed, data/inst 15410726SN/Asystem.cpu0.dtb.walker.walkRequestOrigin::total 233078 # Table walker requests started/completed, data/inst 15510585SN/Asystem.cpu0.dtb.inst_hits 0 # ITB inst hits 15610585SN/Asystem.cpu0.dtb.inst_misses 0 # ITB inst misses 15710726SN/Asystem.cpu0.dtb.read_hits 92662773 # DTB read hits 15810726SN/Asystem.cpu0.dtb.read_misses 88786 # DTB read misses 15910726SN/Asystem.cpu0.dtb.write_hits 85694958 # DTB write hits 16010726SN/Asystem.cpu0.dtb.write_misses 36443 # DTB write misses 16110585SN/Asystem.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed 16210585SN/Asystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 16310726SN/Asystem.cpu0.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID 16410585SN/Asystem.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 16510726SN/Asystem.cpu0.dtb.flush_entries 36354 # Number of entries that have been flushed from TLB 16610585SN/Asystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 16710726SN/Asystem.cpu0.dtb.prefetch_faults 5600 # Number of TLB faults due to prefetch 16810585SN/Asystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 16910726SN/Asystem.cpu0.dtb.perms_faults 10503 # Number of TLB faults due to permissions restrictions 17010726SN/Asystem.cpu0.dtb.read_accesses 92751559 # DTB read accesses 17110726SN/Asystem.cpu0.dtb.write_accesses 85731401 # DTB write accesses 17210585SN/Asystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 17310726SN/Asystem.cpu0.dtb.hits 178357731 # DTB hits 17410726SN/Asystem.cpu0.dtb.misses 125229 # DTB misses 17510726SN/Asystem.cpu0.dtb.accesses 178482960 # DTB accesses 17610628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 17710628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 17810628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 17910628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 18010628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 18110628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 18210628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 18310628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 18410585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 18510585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 18610585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 18710585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 18810585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 18910585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 19010585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 19110585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 19210585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 19310585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 19410585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 19510585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 19610585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 19710585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 19810585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 19910585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 20010585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 20110585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 20210585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 20310585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 20410585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 20510726SN/Asystem.cpu0.itb.walker.walks 61377 # Table walker walks requested 20610726SN/Asystem.cpu0.itb.walker.walksLong 61377 # Table walker walks initiated with long descriptors 20710726SN/Asystem.cpu0.itb.walker.walkWaitTime::samples 61377 # Table walker wait (enqueue to first request) latency 20810726SN/Asystem.cpu0.itb.walker.walkWaitTime::0 61377 100.00% 100.00% # Table walker wait (enqueue to first request) latency 20910726SN/Asystem.cpu0.itb.walker.walkWaitTime::total 61377 # Table walker wait (enqueue to first request) latency 21010628SN/Asystem.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution 21110628SN/Asystem.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution 21210628SN/Asystem.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution 21310726SN/Asystem.cpu0.itb.walker.walkPageSizes::4K 55424 98.80% 98.80% # Table walker page sizes translated 21410726SN/Asystem.cpu0.itb.walker.walkPageSizes::2M 672 1.20% 100.00% # Table walker page sizes translated 21510726SN/Asystem.cpu0.itb.walker.walkPageSizes::total 56096 # Table walker page sizes translated 21610628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 21710726SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61377 # Table walker requests started/completed, data/inst 21810726SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 61377 # Table walker requests started/completed, data/inst 21910628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 22010726SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56096 # Table walker requests started/completed, data/inst 22110726SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 56096 # Table walker requests started/completed, data/inst 22210726SN/Asystem.cpu0.itb.walker.walkRequestOrigin::total 117473 # Table walker requests started/completed, data/inst 22310726SN/Asystem.cpu0.itb.inst_hits 497696393 # ITB inst hits 22410726SN/Asystem.cpu0.itb.inst_misses 61377 # ITB inst misses 22510585SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 22610585SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 22710585SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 22810585SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 22910585SN/Asystem.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed 23010585SN/Asystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 23110726SN/Asystem.cpu0.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID 23210585SN/Asystem.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 23310726SN/Asystem.cpu0.itb.flush_entries 25032 # Number of entries that have been flushed from TLB 23410585SN/Asystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 23510585SN/Asystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 23610585SN/Asystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 23710585SN/Asystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 23810585SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 23910585SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 24010726SN/Asystem.cpu0.itb.inst_accesses 497757770 # ITB inst accesses 24110726SN/Asystem.cpu0.itb.hits 497696393 # DTB hits 24210726SN/Asystem.cpu0.itb.misses 61377 # DTB misses 24310726SN/Asystem.cpu0.itb.accesses 497757770 # DTB accesses 24410726SN/Asystem.cpu0.numCycles 94433641544 # number of cpu cycles simulated 24510585SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 24610585SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 24710726SN/Asystem.cpu0.committedInsts 497466384 # Number of instructions committed 24810726SN/Asystem.cpu0.committedOps 584970773 # Number of ops (including micro ops) committed 24910726SN/Asystem.cpu0.num_int_alu_accesses 536103359 # Number of integer alu accesses 25010726SN/Asystem.cpu0.num_fp_alu_accesses 526132 # Number of float alu accesses 25110726SN/Asystem.cpu0.num_func_calls 28869117 # number of times a function call or return occured 25210726SN/Asystem.cpu0.num_conditional_control_insts 76496594 # number of instructions that are conditional controls 25310726SN/Asystem.cpu0.num_int_insts 536103359 # number of integer instructions 25410726SN/Asystem.cpu0.num_fp_insts 526132 # number of float instructions 25510726SN/Asystem.cpu0.num_int_register_reads 784958858 # number of times the integer registers were read 25610726SN/Asystem.cpu0.num_int_register_writes 425337843 # number of times the integer registers were written 25710726SN/Asystem.cpu0.num_fp_register_reads 849923 # number of times the floating registers were read 25810726SN/Asystem.cpu0.num_fp_register_writes 443780 # number of times the floating registers were written 25910726SN/Asystem.cpu0.num_cc_register_reads 133878831 # number of times the CC registers were read 26010726SN/Asystem.cpu0.num_cc_register_writes 133531045 # number of times the CC registers were written 26110726SN/Asystem.cpu0.num_mem_refs 178459396 # number of memory refs 26210726SN/Asystem.cpu0.num_load_insts 92737001 # Number of load instructions 26310726SN/Asystem.cpu0.num_store_insts 85722395 # Number of store instructions 26410726SN/Asystem.cpu0.num_idle_cycles 93848337191.325058 # Number of idle cycles 26510726SN/Asystem.cpu0.num_busy_cycles 585304352.674931 # Number of busy cycles 26610726SN/Asystem.cpu0.not_idle_fraction 0.006198 # Percentage of non-idle cycles 26710726SN/Asystem.cpu0.idle_fraction 0.993802 # Percentage of idle cycles 26810726SN/Asystem.cpu0.Branches 111287587 # Number of branches fetched 26910585SN/Asystem.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 27010726SN/Asystem.cpu0.op_class::IntAlu 405476023 69.28% 69.28% # Class of executed instruction 27110726SN/Asystem.cpu0.op_class::IntMult 1232194 0.21% 69.49% # Class of executed instruction 27210726SN/Asystem.cpu0.op_class::IntDiv 59840 0.01% 69.50% # Class of executed instruction 27310726SN/Asystem.cpu0.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction 27410726SN/Asystem.cpu0.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction 27510726SN/Asystem.cpu0.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction 27610726SN/Asystem.cpu0.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction 27710726SN/Asystem.cpu0.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction 27810726SN/Asystem.cpu0.op_class::FloatSqrt 0 0.00% 69.50% # Class of executed instruction 27910726SN/Asystem.cpu0.op_class::SimdAdd 0 0.00% 69.50% # Class of executed instruction 28010726SN/Asystem.cpu0.op_class::SimdAddAcc 0 0.00% 69.50% # Class of executed instruction 28110726SN/Asystem.cpu0.op_class::SimdAlu 0 0.00% 69.50% # Class of executed instruction 28210726SN/Asystem.cpu0.op_class::SimdCmp 0 0.00% 69.50% # Class of executed instruction 28310726SN/Asystem.cpu0.op_class::SimdCvt 0 0.00% 69.50% # Class of executed instruction 28410726SN/Asystem.cpu0.op_class::SimdMisc 0 0.00% 69.50% # Class of executed instruction 28510726SN/Asystem.cpu0.op_class::SimdMult 0 0.00% 69.50% # Class of executed instruction 28610726SN/Asystem.cpu0.op_class::SimdMultAcc 0 0.00% 69.50% # Class of executed instruction 28710726SN/Asystem.cpu0.op_class::SimdShift 0 0.00% 69.50% # Class of executed instruction 28810726SN/Asystem.cpu0.op_class::SimdShiftAcc 0 0.00% 69.50% # Class of executed instruction 28910726SN/Asystem.cpu0.op_class::SimdSqrt 0 0.00% 69.50% # Class of executed instruction 29010726SN/Asystem.cpu0.op_class::SimdFloatAdd 8 0.00% 69.50% # Class of executed instruction 29110726SN/Asystem.cpu0.op_class::SimdFloatAlu 0 0.00% 69.50% # Class of executed instruction 29210726SN/Asystem.cpu0.op_class::SimdFloatCmp 13 0.00% 69.50% # Class of executed instruction 29310726SN/Asystem.cpu0.op_class::SimdFloatCvt 21 0.00% 69.50% # Class of executed instruction 29410726SN/Asystem.cpu0.op_class::SimdFloatDiv 0 0.00% 69.50% # Class of executed instruction 29510726SN/Asystem.cpu0.op_class::SimdFloatMisc 72507 0.01% 69.51% # Class of executed instruction 29610726SN/Asystem.cpu0.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction 29710726SN/Asystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction 29810726SN/Asystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction 29910726SN/Asystem.cpu0.op_class::MemRead 92737001 15.84% 85.35% # Class of executed instruction 30010726SN/Asystem.cpu0.op_class::MemWrite 85722395 14.65% 100.00% # Class of executed instruction 30110585SN/Asystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 30210585SN/Asystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 30310726SN/Asystem.cpu0.op_class::total 585300003 # Class of executed instruction 30410585SN/Asystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 30510726SN/Asystem.cpu0.kern.inst.quiesce 13253 # number of quiesce instructions executed 30610827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 6272773 # number of replacements 30710726SN/Asystem.cpu0.dcache.tags.tagsinuse 500.885315 # Cycle average of tags in use 30810827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 172015769 # Total number of references to valid blocks. 30910827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 6273285 # Sample count of references to valid blocks. 31010827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 27.420366 # Average number of references to valid blocks. 31110827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. 31210726SN/Asystem.cpu0.dcache.tags.occ_blocks::cpu0.data 500.885315 # Average occupied blocks per requestor 31310726SN/Asystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.978292 # Average percentage of cache occupancy 31410726SN/Asystem.cpu0.dcache.tags.occ_percent::total 0.978292 # Average percentage of cache occupancy 31510585SN/Asystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 31610726SN/Asystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id 31710726SN/Asystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id 31810726SN/Asystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id 31910585SN/Asystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 32010827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 363162250 # Number of tag accesses 32110827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 363162250 # Number of data accesses 32210892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 86214911 # number of ReadReq hits 32310892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 86214911 # number of ReadReq hits 32410892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 80919787 # number of WriteReq hits 32510892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 80919787 # number of WriteReq hits 32610827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 215654 # number of SoftPFReq hits 32710827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 215654 # number of SoftPFReq hits 32810892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::cpu0.data 262007 # number of WriteLineReq hits 32910892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::total 262007 # number of WriteLineReq hits 33010892Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2076466 # number of LoadLockedReq hits 33110892Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 2076466 # number of LoadLockedReq hits 33210892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 2036572 # number of StoreCondReq hits 33310892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 2036572 # number of StoreCondReq hits 33410892Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 167134698 # number of demand (read+write) hits 33510892Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 167134698 # number of demand (read+write) hits 33610892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 167350352 # number of overall hits 33710892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 167350352 # number of overall hits 33810892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 3309382 # number of ReadReq misses 33910892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 3309382 # number of ReadReq misses 34010892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 1475655 # number of WriteReq misses 34110892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 1475655 # number of WriteReq misses 34210827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 772139 # number of SoftPFReq misses 34310827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 772139 # number of SoftPFReq misses 34410892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::cpu0.data 831713 # number of WriteLineReq misses 34510892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::total 831713 # number of WriteLineReq misses 34610892Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119816 # number of LoadLockedReq misses 34710892Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 119816 # number of LoadLockedReq misses 34810892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 158571 # number of StoreCondReq misses 34910892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 158571 # number of StoreCondReq misses 35010892Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 4785037 # number of demand (read+write) misses 35110892Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 4785037 # number of demand (read+write) misses 35210892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 5557176 # number of overall misses 35310892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 5557176 # number of overall misses 35410827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 89524293 # number of ReadReq accesses(hits+misses) 35510827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 89524293 # number of ReadReq accesses(hits+misses) 35610827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 82395442 # number of WriteReq accesses(hits+misses) 35710827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 82395442 # number of WriteReq accesses(hits+misses) 35810726SN/Asystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 987793 # number of SoftPFReq accesses(hits+misses) 35910726SN/Asystem.cpu0.dcache.SoftPFReq_accesses::total 987793 # number of SoftPFReq accesses(hits+misses) 36010892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1093720 # number of WriteLineReq accesses(hits+misses) 36110892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::total 1093720 # number of WriteLineReq accesses(hits+misses) 36210726SN/Asystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2196282 # number of LoadLockedReq accesses(hits+misses) 36310726SN/Asystem.cpu0.dcache.LoadLockedReq_accesses::total 2196282 # number of LoadLockedReq accesses(hits+misses) 36410726SN/Asystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2195143 # number of StoreCondReq accesses(hits+misses) 36510726SN/Asystem.cpu0.dcache.StoreCondReq_accesses::total 2195143 # number of StoreCondReq accesses(hits+misses) 36610827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 171919735 # number of demand (read+write) accesses 36710827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 171919735 # number of demand (read+write) accesses 36810827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 172907528 # number of overall (read+write) accesses 36910827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 172907528 # number of overall (read+write) accesses 37010726SN/Asystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036966 # miss rate for ReadReq accesses 37110726SN/Asystem.cpu0.dcache.ReadReq_miss_rate::total 0.036966 # miss rate for ReadReq accesses 37210827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017909 # miss rate for WriteReq accesses 37310827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.017909 # miss rate for WriteReq accesses 37410827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781681 # miss rate for SoftPFReq accesses 37510827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.781681 # miss rate for SoftPFReq accesses 37610892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760444 # miss rate for WriteLineReq accesses 37710892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::total 0.760444 # miss rate for WriteLineReq accesses 37810726SN/Asystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054554 # miss rate for LoadLockedReq accesses 37910726SN/Asystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054554 # miss rate for LoadLockedReq accesses 38010892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.072237 # miss rate for StoreCondReq accesses 38110892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.072237 # miss rate for StoreCondReq accesses 38210827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.027833 # miss rate for demand accesses 38310827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.027833 # miss rate for demand accesses 38410892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.032140 # miss rate for overall accesses 38510892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.032140 # miss rate for overall accesses 38610585SN/Asystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 38710585SN/Asystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 38810585SN/Asystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 38910585SN/Asystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 39010585SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 39110585SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 39210585SN/Asystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 39310585SN/Asystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 39410892Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 4472506 # number of writebacks 39510892Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 4472506 # number of writebacks 39610585SN/Asystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 39710892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 5539081 # number of replacements 39810726SN/Asystem.cpu0.icache.tags.tagsinuse 511.989005 # Cycle average of tags in use 39910892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 492212891 # Total number of references to valid blocks. 40010892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 5539593 # Sample count of references to valid blocks. 40110892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 88.853620 # Average number of references to valid blocks. 40210585SN/Asystem.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit. 40310726SN/Asystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989005 # Average occupied blocks per requestor 40410585SN/Asystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy 40510585SN/Asystem.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy 40610585SN/Asystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 40710726SN/Asystem.cpu0.icache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id 40810726SN/Asystem.cpu0.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id 40910726SN/Asystem.cpu0.icache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id 41010585SN/Asystem.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 41110585SN/Asystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 41210892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 1001044576 # Number of tag accesses 41310892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 1001044576 # Number of data accesses 41410892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 492212891 # number of ReadReq hits 41510892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 492212891 # number of ReadReq hits 41610892Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 492212891 # number of demand (read+write) hits 41710892Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 492212891 # number of demand (read+write) hits 41810892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 492212891 # number of overall hits 41910892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 492212891 # number of overall hits 42010892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 5539598 # number of ReadReq misses 42110892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 5539598 # number of ReadReq misses 42210892Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 5539598 # number of demand (read+write) misses 42310892Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 5539598 # number of demand (read+write) misses 42410892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 5539598 # number of overall misses 42510892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 5539598 # number of overall misses 42610726SN/Asystem.cpu0.icache.ReadReq_accesses::cpu0.inst 497752489 # number of ReadReq accesses(hits+misses) 42710726SN/Asystem.cpu0.icache.ReadReq_accesses::total 497752489 # number of ReadReq accesses(hits+misses) 42810726SN/Asystem.cpu0.icache.demand_accesses::cpu0.inst 497752489 # number of demand (read+write) accesses 42910726SN/Asystem.cpu0.icache.demand_accesses::total 497752489 # number of demand (read+write) accesses 43010726SN/Asystem.cpu0.icache.overall_accesses::cpu0.inst 497752489 # number of overall (read+write) accesses 43110726SN/Asystem.cpu0.icache.overall_accesses::total 497752489 # number of overall (read+write) accesses 43210726SN/Asystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011129 # miss rate for ReadReq accesses 43310726SN/Asystem.cpu0.icache.ReadReq_miss_rate::total 0.011129 # miss rate for ReadReq accesses 43410726SN/Asystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.011129 # miss rate for demand accesses 43510726SN/Asystem.cpu0.icache.demand_miss_rate::total 0.011129 # miss rate for demand accesses 43610726SN/Asystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.011129 # miss rate for overall accesses 43710726SN/Asystem.cpu0.icache.overall_miss_rate::total 0.011129 # miss rate for overall accesses 43810585SN/Asystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 43910585SN/Asystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 44010585SN/Asystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 44110585SN/Asystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 44210585SN/Asystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 44310585SN/Asystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 44410585SN/Asystem.cpu0.icache.fast_writes 0 # number of fast writes performed 44510585SN/Asystem.cpu0.icache.cache_copies 0 # number of cache copies performed 44610585SN/Asystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 44710628SN/Asystem.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 44810628SN/Asystem.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 44910628SN/Asystem.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 45010628SN/Asystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 45110628SN/Asystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 45210628SN/Asystem.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 45310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.replacements 2713035 # number of replacements 45410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tagsinuse 16212.776574 # Cycle average of tags in use 45510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.total_refs 18780735 # Total number of references to valid blocks. 45610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.sampled_refs 2729020 # Sample count of references to valid blocks. 45710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.avg_refs 6.881861 # Average number of references to valid blocks. 45810585SN/Asystem.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. 45910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 5698.548759 # Average occupied blocks per requestor 46010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 52.293580 # Average occupied blocks per requestor 46110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 53.073220 # Average occupied blocks per requestor 46210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4549.413482 # Average occupied blocks per requestor 46310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.data 5859.447533 # Average occupied blocks per requestor 46410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.347812 # Average percentage of cache occupancy 46510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003192 # Average percentage of cache occupancy 46610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003239 # Average percentage of cache occupancy 46710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.277674 # Average percentage of cache occupancy 46810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.data 0.357632 # Average percentage of cache occupancy 46910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.989549 # Average percentage of cache occupancy 47010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 51 # Occupied blocks per task id 47110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 15934 # Occupied blocks per task id 47210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 32 # Occupied blocks per task id 47310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id 47410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id 47510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 233 # Occupied blocks per task id 47610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1169 # Occupied blocks per task id 47710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4652 # Occupied blocks per task id 47810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5280 # Occupied blocks per task id 47910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4600 # Occupied blocks per task id 48010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003113 # Percentage of cache occupancy per task id 48110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.972534 # Percentage of cache occupancy per task id 48210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tag_accesses 396071662 # Number of tag accesses 48310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.data_accesses 396071662 # Number of data accesses 48410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 267140 # number of ReadReq hits 48510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 140047 # number of ReadReq hits 48610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 407187 # number of ReadReq hits 48710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_hits::writebacks 4472506 # number of Writeback hits 48810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_hits::total 4472506 # number of Writeback hits 48910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::cpu0.data 3480 # number of UpgradeReq hits 49010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::total 3480 # number of UpgradeReq hits 49110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 634900 # number of ReadExReq hits 49210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 634900 # number of ReadExReq hits 49310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4970860 # number of ReadCleanReq hits 49410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 4970860 # number of ReadCleanReq hits 49510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2942102 # number of ReadSharedReq hits 49610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 2942102 # number of ReadSharedReq hits 49710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::cpu0.data 223126 # number of InvalidateReq hits 49810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::total 223126 # number of InvalidateReq hits 49910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 267140 # number of demand (read+write) hits 50010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 140047 # number of demand (read+write) hits 50110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 4970860 # number of demand (read+write) hits 50210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 3577002 # number of demand (read+write) hits 50310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::total 8955049 # number of demand (read+write) hits 50410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 267140 # number of overall hits 50510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 140047 # number of overall hits 50610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 4970860 # number of overall hits 50710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 3577002 # number of overall hits 50810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::total 8955049 # number of overall hits 50910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11279 # number of ReadReq misses 51010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8435 # number of ReadReq misses 51110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 19714 # number of ReadReq misses 51210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 128321 # number of UpgradeReq misses 51310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 128321 # number of UpgradeReq misses 51410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 158571 # number of SCUpgradeReq misses 51510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 158571 # number of SCUpgradeReq misses 51610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 709333 # number of ReadExReq misses 51710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 709333 # number of ReadExReq misses 51810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 568738 # number of ReadCleanReq misses 51910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 568738 # number of ReadCleanReq misses 52010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1259235 # number of ReadSharedReq misses 52110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 1259235 # number of ReadSharedReq misses 52210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::cpu0.data 608208 # number of InvalidateReq misses 52310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::total 608208 # number of InvalidateReq misses 52410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11279 # number of demand (read+write) misses 52510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 8435 # number of demand (read+write) misses 52610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 568738 # number of demand (read+write) misses 52710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 1968568 # number of demand (read+write) misses 52810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::total 2557020 # number of demand (read+write) misses 52910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11279 # number of overall misses 53010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 8435 # number of overall misses 53110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 568738 # number of overall misses 53210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 1968568 # number of overall misses 53310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::total 2557020 # number of overall misses 53410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 278419 # number of ReadReq accesses(hits+misses) 53510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 148482 # number of ReadReq accesses(hits+misses) 53610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 426901 # number of ReadReq accesses(hits+misses) 53710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_accesses::writebacks 4472506 # number of Writeback accesses(hits+misses) 53810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_accesses::total 4472506 # number of Writeback accesses(hits+misses) 53910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 131801 # number of UpgradeReq accesses(hits+misses) 54010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 131801 # number of UpgradeReq accesses(hits+misses) 54110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 158571 # number of SCUpgradeReq accesses(hits+misses) 54210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 158571 # number of SCUpgradeReq accesses(hits+misses) 54310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1344233 # number of ReadExReq accesses(hits+misses) 54410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1344233 # number of ReadExReq accesses(hits+misses) 54510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5539598 # number of ReadCleanReq accesses(hits+misses) 54610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 5539598 # number of ReadCleanReq accesses(hits+misses) 54710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4201337 # number of ReadSharedReq accesses(hits+misses) 54810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 4201337 # number of ReadSharedReq accesses(hits+misses) 54910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 831334 # number of InvalidateReq accesses(hits+misses) 55010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::total 831334 # number of InvalidateReq accesses(hits+misses) 55110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 278419 # number of demand (read+write) accesses 55210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 148482 # number of demand (read+write) accesses 55310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 5539598 # number of demand (read+write) accesses 55410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 5545570 # number of demand (read+write) accesses 55510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::total 11512069 # number of demand (read+write) accesses 55610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 278419 # number of overall (read+write) accesses 55710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 148482 # number of overall (read+write) accesses 55810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 5539598 # number of overall (read+write) accesses 55910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 5545570 # number of overall (read+write) accesses 56010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::total 11512069 # number of overall (read+write) accesses 56110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.040511 # miss rate for ReadReq accesses 56210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.056808 # miss rate for ReadReq accesses 56310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.046179 # miss rate for ReadReq accesses 56410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.973597 # miss rate for UpgradeReq accesses 56510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 0.973597 # miss rate for UpgradeReq accesses 56610585SN/Asystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 56710585SN/Asystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 56810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.527686 # miss rate for ReadExReq accesses 56910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.527686 # miss rate for ReadExReq accesses 57010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.102668 # miss rate for ReadCleanReq accesses 57110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.102668 # miss rate for ReadCleanReq accesses 57210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.299722 # miss rate for ReadSharedReq accesses 57310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.299722 # miss rate for ReadSharedReq accesses 57410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.731605 # miss rate for InvalidateReq accesses 57510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::total 0.731605 # miss rate for InvalidateReq accesses 57610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.040511 # miss rate for demand accesses 57710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.056808 # miss rate for demand accesses 57810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.102668 # miss rate for demand accesses 57910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.354980 # miss rate for demand accesses 58010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.222116 # miss rate for demand accesses 58110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.040511 # miss rate for overall accesses 58210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.056808 # miss rate for overall accesses 58310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.102668 # miss rate for overall accesses 58410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.354980 # miss rate for overall accesses 58510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.222116 # miss rate for overall accesses 58610585SN/Asystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 58710585SN/Asystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 58810585SN/Asystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 58910585SN/Asystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 59010585SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 59110585SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 59210585SN/Asystem.cpu0.l2cache.fast_writes 0 # number of fast writes performed 59310585SN/Asystem.cpu0.l2cache.cache_copies 0 # number of cache copies performed 59410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::writebacks 1573891 # number of writebacks 59510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::total 1573891 # number of writebacks 59610585SN/Asystem.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 59710892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 623009 # Transaction distribution 59810827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 10363944 # Transaction distribution 59910827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 32419 # Transaction distribution 60010827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 32419 # Transaction distribution 60110892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::Writeback 4472506 # Transaction distribution 60210892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::CleanEvict 7339348 # Transaction distribution 60310892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 131801 # Transaction distribution 60410892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 158571 # Transaction distribution 60510892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 290372 # Transaction distribution 60610892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1344233 # Transaction distribution 60710892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1344233 # Transaction distribution 60810892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 5539598 # Transaction distribution 60910892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 4201337 # Transaction distribution 61010892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateReq 831334 # Transaction distribution 61110892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateResp 831334 # Transaction distribution 61210892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16704527 # Packet count per connected master and slave (bytes) 61310892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19737201 # Packet count per connected master and slave (bytes) 61410726SN/Asystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 366654 # Packet count per connected master and slave (bytes) 61510726SN/Asystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 728076 # Packet count per connected master and slave (bytes) 61610892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count::total 37536458 # Packet count per connected master and slave (bytes) 61710892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 354706772 # Cumulative packet size per connected master and slave (bytes) 61810892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 641350217 # Cumulative packet size per connected master and slave (bytes) 61910726SN/Asystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1466616 # Cumulative packet size per connected master and slave (bytes) 62010726SN/Asystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2912304 # Cumulative packet size per connected master and slave (bytes) 62110892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size::total 1000435909 # Cumulative packet size per connected master and slave (bytes) 62210892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoops 3360861 # Total snoops (count) 62310892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 27849165 # Request fanout histogram 62410892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 1.133662 # Request fanout histogram 62510892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.340289 # Request fanout histogram 62610585SN/Asystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 62710585SN/Asystem.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 62810892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 24126791 86.63% 86.63% # Request fanout histogram 62910892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 3722374 13.37% 100.00% # Request fanout histogram 63010585SN/Asystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 63110827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 63210827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 63310892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 27849165 # Request fanout histogram 63410628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 63510628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 63610628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 63710628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 63810628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 63910628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 64010628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 64110628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 64210585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 64310585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 64410585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 64510585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 64610585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 64710585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 64810585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 64910585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 65010585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 65110585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 65210585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 65310585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 65410585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 65510585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 65610585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 65710585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 65810585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 65910585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 66010585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 66110585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 66210585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 66310726SN/Asystem.cpu1.dtb.walker.walks 144041 # Table walker walks requested 66410726SN/Asystem.cpu1.dtb.walker.walksLong 144041 # Table walker walks initiated with long descriptors 66510726SN/Asystem.cpu1.dtb.walker.walkWaitTime::samples 144041 # Table walker wait (enqueue to first request) latency 66610726SN/Asystem.cpu1.dtb.walker.walkWaitTime::0 144041 100.00% 100.00% # Table walker wait (enqueue to first request) latency 66710726SN/Asystem.cpu1.dtb.walker.walkWaitTime::total 144041 # Table walker wait (enqueue to first request) latency 66810628SN/Asystem.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution 66910628SN/Asystem.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution 67010628SN/Asystem.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution 67110726SN/Asystem.cpu1.dtb.walker.walkPageSizes::4K 111414 88.97% 88.97% # Table walker page sizes translated 67210726SN/Asystem.cpu1.dtb.walker.walkPageSizes::2M 13807 11.03% 100.00% # Table walker page sizes translated 67310726SN/Asystem.cpu1.dtb.walker.walkPageSizes::total 125221 # Table walker page sizes translated 67410726SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144041 # Table walker requests started/completed, data/inst 67510628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 67610726SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144041 # Table walker requests started/completed, data/inst 67710726SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 125221 # Table walker requests started/completed, data/inst 67810628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 67910726SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 125221 # Table walker requests started/completed, data/inst 68010726SN/Asystem.cpu1.dtb.walker.walkRequestOrigin::total 269262 # Table walker requests started/completed, data/inst 68110585SN/Asystem.cpu1.dtb.inst_hits 0 # ITB inst hits 68210585SN/Asystem.cpu1.dtb.inst_misses 0 # ITB inst misses 68310726SN/Asystem.cpu1.dtb.read_hits 90153061 # DTB read hits 68410726SN/Asystem.cpu1.dtb.read_misses 111753 # DTB read misses 68510726SN/Asystem.cpu1.dtb.write_hits 81132787 # DTB write hits 68610726SN/Asystem.cpu1.dtb.write_misses 32288 # DTB write misses 68710585SN/Asystem.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed 68810585SN/Asystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 68910726SN/Asystem.cpu1.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID 69010585SN/Asystem.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 69110726SN/Asystem.cpu1.dtb.flush_entries 44587 # Number of entries that have been flushed from TLB 69210585SN/Asystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 69310726SN/Asystem.cpu1.dtb.prefetch_faults 4554 # Number of TLB faults due to prefetch 69410585SN/Asystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 69510726SN/Asystem.cpu1.dtb.perms_faults 11374 # Number of TLB faults due to permissions restrictions 69610726SN/Asystem.cpu1.dtb.read_accesses 90264814 # DTB read accesses 69710726SN/Asystem.cpu1.dtb.write_accesses 81165075 # DTB write accesses 69810585SN/Asystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 69910726SN/Asystem.cpu1.dtb.hits 171285848 # DTB hits 70010726SN/Asystem.cpu1.dtb.misses 144041 # DTB misses 70110726SN/Asystem.cpu1.dtb.accesses 171429889 # DTB accesses 70210628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 70310628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 70410628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 70510628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 70610628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 70710628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 70810628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 70910628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 71010585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 71110585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 71210585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 71310585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 71410585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 71510585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 71610585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 71710585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 71810585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 71910585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 72010585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 72110585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 72210585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 72310585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 72410585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 72510585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 72610585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 72710585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 72810585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 72910585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 73010585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 73110726SN/Asystem.cpu1.itb.walker.walks 60885 # Table walker walks requested 73210726SN/Asystem.cpu1.itb.walker.walksLong 60885 # Table walker walks initiated with long descriptors 73310726SN/Asystem.cpu1.itb.walker.walkWaitTime::samples 60885 # Table walker wait (enqueue to first request) latency 73410726SN/Asystem.cpu1.itb.walker.walkWaitTime::0 60885 100.00% 100.00% # Table walker wait (enqueue to first request) latency 73510726SN/Asystem.cpu1.itb.walker.walkWaitTime::total 60885 # Table walker wait (enqueue to first request) latency 73610628SN/Asystem.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution 73710628SN/Asystem.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution 73810628SN/Asystem.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution 73910726SN/Asystem.cpu1.itb.walker.walkPageSizes::4K 53790 99.07% 99.07% # Table walker page sizes translated 74010726SN/Asystem.cpu1.itb.walker.walkPageSizes::2M 505 0.93% 100.00% # Table walker page sizes translated 74110726SN/Asystem.cpu1.itb.walker.walkPageSizes::total 54295 # Table walker page sizes translated 74210628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 74310726SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60885 # Table walker requests started/completed, data/inst 74410726SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 60885 # Table walker requests started/completed, data/inst 74510628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 74610726SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 54295 # Table walker requests started/completed, data/inst 74710726SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 54295 # Table walker requests started/completed, data/inst 74810726SN/Asystem.cpu1.itb.walker.walkRequestOrigin::total 115180 # Table walker requests started/completed, data/inst 74910726SN/Asystem.cpu1.itb.inst_hits 478248118 # ITB inst hits 75010726SN/Asystem.cpu1.itb.inst_misses 60885 # ITB inst misses 75110585SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 75210585SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 75310585SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 75410585SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 75510585SN/Asystem.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed 75610585SN/Asystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 75710726SN/Asystem.cpu1.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID 75810585SN/Asystem.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 75910726SN/Asystem.cpu1.itb.flush_entries 31530 # Number of entries that have been flushed from TLB 76010585SN/Asystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 76110585SN/Asystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 76210585SN/Asystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 76310585SN/Asystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 76410585SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 76510585SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 76610726SN/Asystem.cpu1.itb.inst_accesses 478309003 # ITB inst accesses 76710726SN/Asystem.cpu1.itb.hits 478248118 # DTB hits 76810726SN/Asystem.cpu1.itb.misses 60885 # DTB misses 76910726SN/Asystem.cpu1.itb.accesses 478309003 # DTB accesses 77010726SN/Asystem.cpu1.numCycles 94433634550 # number of cpu cycles simulated 77110585SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 77210585SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 77310726SN/Asystem.cpu1.committedInsts 477990846 # Number of instructions committed 77410726SN/Asystem.cpu1.committedOps 562567642 # Number of ops (including micro ops) committed 77510726SN/Asystem.cpu1.num_int_alu_accesses 516282159 # Number of integer alu accesses 77610726SN/Asystem.cpu1.num_fp_alu_accesses 374678 # Number of float alu accesses 77710726SN/Asystem.cpu1.num_func_calls 28237407 # number of times a function call or return occured 77810726SN/Asystem.cpu1.num_conditional_control_insts 73185792 # number of instructions that are conditional controls 77910726SN/Asystem.cpu1.num_int_insts 516282159 # number of integer instructions 78010726SN/Asystem.cpu1.num_fp_insts 374678 # number of float instructions 78110726SN/Asystem.cpu1.num_int_register_reads 763231058 # number of times the integer registers were read 78210726SN/Asystem.cpu1.num_int_register_writes 411079626 # number of times the integer registers were written 78310726SN/Asystem.cpu1.num_fp_register_reads 608455 # number of times the floating registers were read 78410726SN/Asystem.cpu1.num_fp_register_writes 306456 # number of times the floating registers were written 78510726SN/Asystem.cpu1.num_cc_register_reads 126379788 # number of times the CC registers were read 78610726SN/Asystem.cpu1.num_cc_register_writes 126112608 # number of times the CC registers were written 78710726SN/Asystem.cpu1.num_mem_refs 171406825 # number of memory refs 78810726SN/Asystem.cpu1.num_load_insts 90251973 # Number of load instructions 78910726SN/Asystem.cpu1.num_store_insts 81154852 # Number of store instructions 79010726SN/Asystem.cpu1.num_idle_cycles 93870750285.000458 # Number of idle cycles 79110726SN/Asystem.cpu1.num_busy_cycles 562884264.999552 # Number of busy cycles 79210726SN/Asystem.cpu1.not_idle_fraction 0.005961 # Percentage of non-idle cycles 79310726SN/Asystem.cpu1.idle_fraction 0.994039 # Percentage of idle cycles 79410726SN/Asystem.cpu1.Branches 106497601 # Number of branches fetched 79510585SN/Asystem.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 79610726SN/Asystem.cpu1.op_class::IntAlu 390236864 69.33% 69.33% # Class of executed instruction 79710726SN/Asystem.cpu1.op_class::IntMult 1137629 0.20% 69.53% # Class of executed instruction 79810726SN/Asystem.cpu1.op_class::IntDiv 60962 0.01% 69.54% # Class of executed instruction 79910726SN/Asystem.cpu1.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction 80010726SN/Asystem.cpu1.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction 80110726SN/Asystem.cpu1.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction 80210726SN/Asystem.cpu1.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction 80310726SN/Asystem.cpu1.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction 80410726SN/Asystem.cpu1.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction 80510726SN/Asystem.cpu1.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction 80610726SN/Asystem.cpu1.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction 80710726SN/Asystem.cpu1.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction 80810726SN/Asystem.cpu1.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction 80910726SN/Asystem.cpu1.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction 81010726SN/Asystem.cpu1.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction 81110726SN/Asystem.cpu1.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction 81210726SN/Asystem.cpu1.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction 81310726SN/Asystem.cpu1.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction 81410726SN/Asystem.cpu1.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction 81510726SN/Asystem.cpu1.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction 81610726SN/Asystem.cpu1.op_class::SimdFloatAdd 0 0.00% 69.54% # Class of executed instruction 81710726SN/Asystem.cpu1.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction 81810726SN/Asystem.cpu1.op_class::SimdFloatCmp 0 0.00% 69.54% # Class of executed instruction 81910726SN/Asystem.cpu1.op_class::SimdFloatCvt 0 0.00% 69.54% # Class of executed instruction 82010726SN/Asystem.cpu1.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction 82110726SN/Asystem.cpu1.op_class::SimdFloatMisc 37059 0.01% 69.55% # Class of executed instruction 82210726SN/Asystem.cpu1.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction 82310726SN/Asystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction 82410726SN/Asystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction 82510726SN/Asystem.cpu1.op_class::MemRead 90251973 16.03% 85.58% # Class of executed instruction 82610726SN/Asystem.cpu1.op_class::MemWrite 81154852 14.42% 100.00% # Class of executed instruction 82710585SN/Asystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 82810585SN/Asystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 82910726SN/Asystem.cpu1.op_class::total 562879339 # Class of executed instruction 83010585SN/Asystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 83110726SN/Asystem.cpu1.kern.inst.quiesce 6259 # number of quiesce instructions executed 83210726SN/Asystem.cpu1.dcache.tags.replacements 5945049 # number of replacements 83310726SN/Asystem.cpu1.dcache.tags.tagsinuse 438.290639 # Cycle average of tags in use 83410726SN/Asystem.cpu1.dcache.tags.total_refs 165346662 # Total number of references to valid blocks. 83510726SN/Asystem.cpu1.dcache.tags.sampled_refs 5945561 # Sample count of references to valid blocks. 83610726SN/Asystem.cpu1.dcache.tags.avg_refs 27.810103 # Average number of references to valid blocks. 83710585SN/Asystem.cpu1.dcache.tags.warmup_cycle 8470277778500 # Cycle when the warmup percentage was hit. 83810726SN/Asystem.cpu1.dcache.tags.occ_blocks::cpu1.data 438.290639 # Average occupied blocks per requestor 83910726SN/Asystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.856036 # Average percentage of cache occupancy 84010726SN/Asystem.cpu1.dcache.tags.occ_percent::total 0.856036 # Average percentage of cache occupancy 84110726SN/Asystem.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 84210726SN/Asystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id 84310726SN/Asystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id 84410726SN/Asystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id 84510726SN/Asystem.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 84610726SN/Asystem.cpu1.dcache.tags.tag_accesses 348813711 # Number of tag accesses 84710726SN/Asystem.cpu1.dcache.tags.data_accesses 348813711 # Number of data accesses 84810726SN/Asystem.cpu1.dcache.ReadReq_hits::cpu1.data 83697564 # number of ReadReq hits 84910726SN/Asystem.cpu1.dcache.ReadReq_hits::total 83697564 # number of ReadReq hits 85010892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 76990238 # number of WriteReq hits 85110892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 76990238 # number of WriteReq hits 85210726SN/Asystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 187854 # number of SoftPFReq hits 85310726SN/Asystem.cpu1.dcache.SoftPFReq_hits::total 187854 # number of SoftPFReq hits 85410892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::cpu1.data 63440 # number of WriteLineReq hits 85510892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::total 63440 # number of WriteLineReq hits 85610726SN/Asystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2062256 # number of LoadLockedReq hits 85710726SN/Asystem.cpu1.dcache.LoadLockedReq_hits::total 2062256 # number of LoadLockedReq hits 85810892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 2048840 # number of StoreCondReq hits 85910892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 2048840 # number of StoreCondReq hits 86010892Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 160687802 # number of demand (read+write) hits 86110892Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 160687802 # number of demand (read+write) hits 86210892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 160875656 # number of overall hits 86310892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 160875656 # number of overall hits 86410726SN/Asystem.cpu1.dcache.ReadReq_misses::cpu1.data 3358222 # number of ReadReq misses 86510726SN/Asystem.cpu1.dcache.ReadReq_misses::total 3358222 # number of ReadReq misses 86610892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 1453238 # number of WriteReq misses 86710892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 1453238 # number of WriteReq misses 86810726SN/Asystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 792351 # number of SoftPFReq misses 86910726SN/Asystem.cpu1.dcache.SoftPFReq_misses::total 792351 # number of SoftPFReq misses 87010892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::cpu1.data 427059 # number of WriteLineReq misses 87110892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::total 427059 # number of WriteLineReq misses 87210726SN/Asystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 146820 # number of LoadLockedReq misses 87310726SN/Asystem.cpu1.dcache.LoadLockedReq_misses::total 146820 # number of LoadLockedReq misses 87410892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 158909 # number of StoreCondReq misses 87510892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 158909 # number of StoreCondReq misses 87610892Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 4811460 # number of demand (read+write) misses 87710892Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 4811460 # number of demand (read+write) misses 87810892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 5603811 # number of overall misses 87910892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 5603811 # number of overall misses 88010726SN/Asystem.cpu1.dcache.ReadReq_accesses::cpu1.data 87055786 # number of ReadReq accesses(hits+misses) 88110726SN/Asystem.cpu1.dcache.ReadReq_accesses::total 87055786 # number of ReadReq accesses(hits+misses) 88210726SN/Asystem.cpu1.dcache.WriteReq_accesses::cpu1.data 78443476 # number of WriteReq accesses(hits+misses) 88310726SN/Asystem.cpu1.dcache.WriteReq_accesses::total 78443476 # number of WriteReq accesses(hits+misses) 88410726SN/Asystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 980205 # number of SoftPFReq accesses(hits+misses) 88510726SN/Asystem.cpu1.dcache.SoftPFReq_accesses::total 980205 # number of SoftPFReq accesses(hits+misses) 88610892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::cpu1.data 490499 # number of WriteLineReq accesses(hits+misses) 88710892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::total 490499 # number of WriteLineReq accesses(hits+misses) 88810726SN/Asystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2209076 # number of LoadLockedReq accesses(hits+misses) 88910726SN/Asystem.cpu1.dcache.LoadLockedReq_accesses::total 2209076 # number of LoadLockedReq accesses(hits+misses) 89010726SN/Asystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2207749 # number of StoreCondReq accesses(hits+misses) 89110726SN/Asystem.cpu1.dcache.StoreCondReq_accesses::total 2207749 # number of StoreCondReq accesses(hits+misses) 89210726SN/Asystem.cpu1.dcache.demand_accesses::cpu1.data 165499262 # number of demand (read+write) accesses 89310726SN/Asystem.cpu1.dcache.demand_accesses::total 165499262 # number of demand (read+write) accesses 89410726SN/Asystem.cpu1.dcache.overall_accesses::cpu1.data 166479467 # number of overall (read+write) accesses 89510726SN/Asystem.cpu1.dcache.overall_accesses::total 166479467 # number of overall (read+write) accesses 89610726SN/Asystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038576 # miss rate for ReadReq accesses 89710726SN/Asystem.cpu1.dcache.ReadReq_miss_rate::total 0.038576 # miss rate for ReadReq accesses 89810892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018526 # miss rate for WriteReq accesses 89910892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.018526 # miss rate for WriteReq accesses 90010726SN/Asystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808352 # miss rate for SoftPFReq accesses 90110726SN/Asystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.808352 # miss rate for SoftPFReq accesses 90210892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870662 # miss rate for WriteLineReq accesses 90310892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::total 0.870662 # miss rate for WriteLineReq accesses 90410726SN/Asystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066462 # miss rate for LoadLockedReq accesses 90510726SN/Asystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066462 # miss rate for LoadLockedReq accesses 90610892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071978 # miss rate for StoreCondReq accesses 90710892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.071978 # miss rate for StoreCondReq accesses 90810726SN/Asystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.029072 # miss rate for demand accesses 90910726SN/Asystem.cpu1.dcache.demand_miss_rate::total 0.029072 # miss rate for demand accesses 91010892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.033661 # miss rate for overall accesses 91110892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.033661 # miss rate for overall accesses 91210585SN/Asystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 91310585SN/Asystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 91410585SN/Asystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 91510585SN/Asystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 91610585SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 91710585SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 91810585SN/Asystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 91910585SN/Asystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 92010892Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 4032489 # number of writebacks 92110892Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 4032489 # number of writebacks 92210585SN/Asystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 92310726SN/Asystem.cpu1.icache.tags.replacements 4741297 # number of replacements 92410726SN/Asystem.cpu1.icache.tags.tagsinuse 496.426080 # Cycle average of tags in use 92510726SN/Asystem.cpu1.icache.tags.total_refs 473560604 # Total number of references to valid blocks. 92610726SN/Asystem.cpu1.icache.tags.sampled_refs 4741809 # Sample count of references to valid blocks. 92710726SN/Asystem.cpu1.icache.tags.avg_refs 99.869186 # Average number of references to valid blocks. 92810585SN/Asystem.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit. 92910726SN/Asystem.cpu1.icache.tags.occ_blocks::cpu1.inst 496.426080 # Average occupied blocks per requestor 93010726SN/Asystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.969582 # Average percentage of cache occupancy 93110726SN/Asystem.cpu1.icache.tags.occ_percent::total 0.969582 # Average percentage of cache occupancy 93210585SN/Asystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 93310585SN/Asystem.cpu1.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 93410585SN/Asystem.cpu1.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id 93510585SN/Asystem.cpu1.icache.tags.age_task_id_blocks_1024::2 144 # Occupied blocks per task id 93610585SN/Asystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 93710726SN/Asystem.cpu1.icache.tags.tag_accesses 961346635 # Number of tag accesses 93810726SN/Asystem.cpu1.icache.tags.data_accesses 961346635 # Number of data accesses 93910726SN/Asystem.cpu1.icache.ReadReq_hits::cpu1.inst 473560604 # number of ReadReq hits 94010726SN/Asystem.cpu1.icache.ReadReq_hits::total 473560604 # number of ReadReq hits 94110726SN/Asystem.cpu1.icache.demand_hits::cpu1.inst 473560604 # number of demand (read+write) hits 94210726SN/Asystem.cpu1.icache.demand_hits::total 473560604 # number of demand (read+write) hits 94310726SN/Asystem.cpu1.icache.overall_hits::cpu1.inst 473560604 # number of overall hits 94410726SN/Asystem.cpu1.icache.overall_hits::total 473560604 # number of overall hits 94510726SN/Asystem.cpu1.icache.ReadReq_misses::cpu1.inst 4741809 # number of ReadReq misses 94610726SN/Asystem.cpu1.icache.ReadReq_misses::total 4741809 # number of ReadReq misses 94710726SN/Asystem.cpu1.icache.demand_misses::cpu1.inst 4741809 # number of demand (read+write) misses 94810726SN/Asystem.cpu1.icache.demand_misses::total 4741809 # number of demand (read+write) misses 94910726SN/Asystem.cpu1.icache.overall_misses::cpu1.inst 4741809 # number of overall misses 95010726SN/Asystem.cpu1.icache.overall_misses::total 4741809 # number of overall misses 95110726SN/Asystem.cpu1.icache.ReadReq_accesses::cpu1.inst 478302413 # number of ReadReq accesses(hits+misses) 95210726SN/Asystem.cpu1.icache.ReadReq_accesses::total 478302413 # number of ReadReq accesses(hits+misses) 95310726SN/Asystem.cpu1.icache.demand_accesses::cpu1.inst 478302413 # number of demand (read+write) accesses 95410726SN/Asystem.cpu1.icache.demand_accesses::total 478302413 # number of demand (read+write) accesses 95510726SN/Asystem.cpu1.icache.overall_accesses::cpu1.inst 478302413 # number of overall (read+write) accesses 95610726SN/Asystem.cpu1.icache.overall_accesses::total 478302413 # number of overall (read+write) accesses 95710726SN/Asystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009914 # miss rate for ReadReq accesses 95810726SN/Asystem.cpu1.icache.ReadReq_miss_rate::total 0.009914 # miss rate for ReadReq accesses 95910726SN/Asystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.009914 # miss rate for demand accesses 96010726SN/Asystem.cpu1.icache.demand_miss_rate::total 0.009914 # miss rate for demand accesses 96110726SN/Asystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.009914 # miss rate for overall accesses 96210726SN/Asystem.cpu1.icache.overall_miss_rate::total 0.009914 # miss rate for overall accesses 96310585SN/Asystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 96410585SN/Asystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 96510585SN/Asystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 96610585SN/Asystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 96710585SN/Asystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 96810585SN/Asystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 96910585SN/Asystem.cpu1.icache.fast_writes 0 # number of fast writes performed 97010585SN/Asystem.cpu1.icache.cache_copies 0 # number of cache copies performed 97110585SN/Asystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 97210628SN/Asystem.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 97310628SN/Asystem.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 97410628SN/Asystem.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 97510628SN/Asystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 97610628SN/Asystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 97710628SN/Asystem.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 97810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.replacements 2278625 # number of replacements 97910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tagsinuse 13455.366056 # Cycle average of tags in use 98010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.total_refs 17413486 # Total number of references to valid blocks. 98110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.sampled_refs 2294680 # Sample count of references to valid blocks. 98210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.avg_refs 7.588634 # Average number of references to valid blocks. 98310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 9726491516500 # Cycle when the warmup percentage was hit. 98410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 5192.867159 # Average occupied blocks per requestor 98510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 66.806245 # Average occupied blocks per requestor 98610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 99.441300 # Average occupied blocks per requestor 98710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2834.629918 # Average occupied blocks per requestor 98810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.data 5261.621433 # Average occupied blocks per requestor 98910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.316947 # Average percentage of cache occupancy 99010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004078 # Average percentage of cache occupancy 99110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.006069 # Average percentage of cache occupancy 99210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.173012 # Average percentage of cache occupancy 99310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.data 0.321144 # Average percentage of cache occupancy 99410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.821250 # Average percentage of cache occupancy 99510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 98 # Occupied blocks per task id 99610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 15957 # Occupied blocks per task id 99710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id 99810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 99910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 49 # Occupied blocks per task id 100010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id 100110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 34 # Occupied blocks per task id 100210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id 100310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1614 # Occupied blocks per task id 100410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5923 # Occupied blocks per task id 100510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4524 # Occupied blocks per task id 100610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3815 # Occupied blocks per task id 100710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005981 # Percentage of cache occupancy per task id 100810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.973938 # Percentage of cache occupancy per task id 100910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tag_accesses 360485676 # Number of tag accesses 101010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.data_accesses 360485676 # Number of data accesses 101110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 324846 # number of ReadReq hits 101210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 140054 # number of ReadReq hits 101310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 464900 # number of ReadReq hits 101410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_hits::writebacks 4032489 # number of Writeback hits 101510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_hits::total 4032489 # number of Writeback hits 101610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::cpu1.data 3822 # number of UpgradeReq hits 101710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::total 3822 # number of UpgradeReq hits 101810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 614016 # number of ReadExReq hits 101910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 614016 # number of ReadExReq hits 102010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4217303 # number of ReadCleanReq hits 102110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 4217303 # number of ReadCleanReq hits 102210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3057649 # number of ReadSharedReq hits 102310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 3057649 # number of ReadSharedReq hits 102410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::cpu1.data 161208 # number of InvalidateReq hits 102510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::total 161208 # number of InvalidateReq hits 102610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 324846 # number of demand (read+write) hits 102710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 140054 # number of demand (read+write) hits 102810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 4217303 # number of demand (read+write) hits 102910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 3671665 # number of demand (read+write) hits 103010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::total 8353868 # number of demand (read+write) hits 103110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 324846 # number of overall hits 103210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 140054 # number of overall hits 103310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 4217303 # number of overall hits 103410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 3671665 # number of overall hits 103510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::total 8353868 # number of overall hits 103610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12306 # number of ReadReq misses 103710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9777 # number of ReadReq misses 103810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 22083 # number of ReadReq misses 103910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 133739 # number of UpgradeReq misses 104010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 133739 # number of UpgradeReq misses 104110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 158909 # number of SCUpgradeReq misses 104210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 158909 # number of SCUpgradeReq misses 104310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 701874 # number of ReadExReq misses 104410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 701874 # number of ReadExReq misses 104510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 524506 # number of ReadCleanReq misses 104610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 524506 # number of ReadCleanReq misses 104710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1239744 # number of ReadSharedReq misses 104810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 1239744 # number of ReadSharedReq misses 104910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::cpu1.data 265638 # number of InvalidateReq misses 105010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::total 265638 # number of InvalidateReq misses 105110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12306 # number of demand (read+write) misses 105210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 9777 # number of demand (read+write) misses 105310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 524506 # number of demand (read+write) misses 105410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 1941618 # number of demand (read+write) misses 105510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::total 2488207 # number of demand (read+write) misses 105610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12306 # number of overall misses 105710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 9777 # number of overall misses 105810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 524506 # number of overall misses 105910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 1941618 # number of overall misses 106010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::total 2488207 # number of overall misses 106110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 337152 # number of ReadReq accesses(hits+misses) 106210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 149831 # number of ReadReq accesses(hits+misses) 106310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 486983 # number of ReadReq accesses(hits+misses) 106410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_accesses::writebacks 4032489 # number of Writeback accesses(hits+misses) 106510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_accesses::total 4032489 # number of Writeback accesses(hits+misses) 106610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 137561 # number of UpgradeReq accesses(hits+misses) 106710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 137561 # number of UpgradeReq accesses(hits+misses) 106810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 158909 # number of SCUpgradeReq accesses(hits+misses) 106910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 158909 # number of SCUpgradeReq accesses(hits+misses) 107010726SN/Asystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1315890 # number of ReadExReq accesses(hits+misses) 107110726SN/Asystem.cpu1.l2cache.ReadExReq_accesses::total 1315890 # number of ReadExReq accesses(hits+misses) 107210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4741809 # number of ReadCleanReq accesses(hits+misses) 107310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 4741809 # number of ReadCleanReq accesses(hits+misses) 107410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4297393 # number of ReadSharedReq accesses(hits+misses) 107510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 4297393 # number of ReadSharedReq accesses(hits+misses) 107610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 426846 # number of InvalidateReq accesses(hits+misses) 107710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::total 426846 # number of InvalidateReq accesses(hits+misses) 107810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 337152 # number of demand (read+write) accesses 107910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 149831 # number of demand (read+write) accesses 108010726SN/Asystem.cpu1.l2cache.demand_accesses::cpu1.inst 4741809 # number of demand (read+write) accesses 108110726SN/Asystem.cpu1.l2cache.demand_accesses::cpu1.data 5613283 # number of demand (read+write) accesses 108210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::total 10842075 # number of demand (read+write) accesses 108310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 337152 # number of overall (read+write) accesses 108410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 149831 # number of overall (read+write) accesses 108510726SN/Asystem.cpu1.l2cache.overall_accesses::cpu1.inst 4741809 # number of overall (read+write) accesses 108610726SN/Asystem.cpu1.l2cache.overall_accesses::cpu1.data 5613283 # number of overall (read+write) accesses 108710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::total 10842075 # number of overall (read+write) accesses 108810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.036500 # miss rate for ReadReq accesses 108910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.065254 # miss rate for ReadReq accesses 109010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.045347 # miss rate for ReadReq accesses 109110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.972216 # miss rate for UpgradeReq accesses 109210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 0.972216 # miss rate for UpgradeReq accesses 109310585SN/Asystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 109410585SN/Asystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 109510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.533383 # miss rate for ReadExReq accesses 109610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.533383 # miss rate for ReadExReq accesses 109710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.110613 # miss rate for ReadCleanReq accesses 109810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.110613 # miss rate for ReadCleanReq accesses 109910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.288487 # miss rate for ReadSharedReq accesses 110010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.288487 # miss rate for ReadSharedReq accesses 110110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.622327 # miss rate for InvalidateReq accesses 110210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::total 0.622327 # miss rate for InvalidateReq accesses 110310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.036500 # miss rate for demand accesses 110410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.065254 # miss rate for demand accesses 110510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.110613 # miss rate for demand accesses 110610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.345897 # miss rate for demand accesses 110710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.229495 # miss rate for demand accesses 110810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.036500 # miss rate for overall accesses 110910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.065254 # miss rate for overall accesses 111010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.110613 # miss rate for overall accesses 111110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.345897 # miss rate for overall accesses 111210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.229495 # miss rate for overall accesses 111310585SN/Asystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 111410585SN/Asystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 111510585SN/Asystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 111610585SN/Asystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 111710585SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 111810585SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 111910585SN/Asystem.cpu1.l2cache.fast_writes 0 # number of fast writes performed 112010585SN/Asystem.cpu1.l2cache.cache_copies 0 # number of cache copies performed 112110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::writebacks 1184748 # number of writebacks 112210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::total 1184748 # number of writebacks 112310585SN/Asystem.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 112410892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 606211 # Transaction distribution 112510726SN/Asystem.cpu1.toL2Bus.trans_dist::ReadResp 9645413 # Transaction distribution 112610726SN/Asystem.cpu1.toL2Bus.trans_dist::WriteReq 6383 # Transaction distribution 112710726SN/Asystem.cpu1.toL2Bus.trans_dist::WriteResp 6383 # Transaction distribution 112810892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::Writeback 4032489 # Transaction distribution 112910892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::CleanEvict 6653857 # Transaction distribution 113010892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 137561 # Transaction distribution 113110892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 158909 # Transaction distribution 113210892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 296470 # Transaction distribution 113310726SN/Asystem.cpu1.toL2Bus.trans_dist::ReadExReq 1315890 # Transaction distribution 113410726SN/Asystem.cpu1.toL2Bus.trans_dist::ReadExResp 1315890 # Transaction distribution 113510892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 4741809 # Transaction distribution 113610892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 4297393 # Transaction distribution 113710892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateReq 426846 # Transaction distribution 113810892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateResp 426846 # Transaction distribution 113910892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14225175 # Packet count per connected master and slave (bytes) 114010892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18643731 # Packet count per connected master and slave (bytes) 114110726SN/Asystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 364008 # Packet count per connected master and slave (bytes) 114210726SN/Asystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 835436 # Packet count per connected master and slave (bytes) 114310892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count::total 34068350 # Packet count per connected master and slave (bytes) 114410726SN/Asystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 303476296 # Cumulative packet size per connected master and slave (bytes) 114510892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 617367804 # Cumulative packet size per connected master and slave (bytes) 114610726SN/Asystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1456032 # Cumulative packet size per connected master and slave (bytes) 114710726SN/Asystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3341744 # Cumulative packet size per connected master and slave (bytes) 114810892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size::total 925641876 # Cumulative packet size per connected master and slave (bytes) 114910892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoops 3842126 # Total snoops (count) 115010892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 26053175 # Request fanout histogram 115110892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 1.164109 # Request fanout histogram 115210892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.370374 # Request fanout histogram 115310585SN/Asystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 115410585SN/Asystem.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 115510892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 21777626 83.59% 83.59% # Request fanout histogram 115610892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 4275549 16.41% 100.00% # Request fanout histogram 115710585SN/Asystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 115810827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 115910827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 116010892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 26053175 # Request fanout histogram 116110726SN/Asystem.iobus.trans_dist::ReadReq 40295 # Transaction distribution 116210726SN/Asystem.iobus.trans_dist::ReadResp 40295 # Transaction distribution 116310726SN/Asystem.iobus.trans_dist::WriteReq 136634 # Transaction distribution 116410892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 136634 # Transaction distribution 116510726SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47636 # Packet count per connected master and slave (bytes) 116610585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 116710585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 116810585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 116910585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 117010585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 117110585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 117210585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 117310585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 117410585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 117510585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 117610585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 117710585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 117810585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 117910585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 118010726SN/Asystem.iobus.pkt_count_system.bridge.master::total 122570 # Packet count per connected master and slave (bytes) 118110726SN/Asystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231208 # Packet count per connected master and slave (bytes) 118210726SN/Asystem.iobus.pkt_count_system.realview.ide.dma::total 231208 # Packet count per connected master and slave (bytes) 118310585SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 118410585SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 118510726SN/Asystem.iobus.pkt_count::total 353858 # Packet count per connected master and slave (bytes) 118610726SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47656 # Cumulative packet size per connected master and slave (bytes) 118710585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 118810585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 118910585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 119010585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 119110585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 119210585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 119310585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 119410585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 119510585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 119610585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 119710585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 119810585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 119910585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 120010585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 120110726SN/Asystem.iobus.pkt_size_system.bridge.master::total 155677 # Cumulative packet size per connected master and slave (bytes) 120210726SN/Asystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338848 # Cumulative packet size per connected master and slave (bytes) 120310726SN/Asystem.iobus.pkt_size_system.realview.ide.dma::total 7338848 # Cumulative packet size per connected master and slave (bytes) 120410585SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 120510585SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 120610726SN/Asystem.iobus.pkt_size::total 7496611 # Cumulative packet size per connected master and slave (bytes) 120710726SN/Asystem.iocache.tags.replacements 115585 # number of replacements 120810726SN/Asystem.iocache.tags.tagsinuse 11.290896 # Cycle average of tags in use 120910585SN/Asystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 121010726SN/Asystem.iocache.tags.sampled_refs 115601 # Sample count of references to valid blocks. 121110585SN/Asystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 121210585SN/Asystem.iocache.tags.warmup_cycle 9107775783009 # Cycle when the warmup percentage was hit. 121310726SN/Asystem.iocache.tags.occ_blocks::realview.ethernet 3.851982 # Average occupied blocks per requestor 121410726SN/Asystem.iocache.tags.occ_blocks::realview.ide 7.438915 # Average occupied blocks per requestor 121510726SN/Asystem.iocache.tags.occ_percent::realview.ethernet 0.240749 # Average percentage of cache occupancy 121610726SN/Asystem.iocache.tags.occ_percent::realview.ide 0.464932 # Average percentage of cache occupancy 121710726SN/Asystem.iocache.tags.occ_percent::total 0.705681 # Average percentage of cache occupancy 121810585SN/Asystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 121910585SN/Asystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 122010585SN/Asystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 122110726SN/Asystem.iocache.tags.tag_accesses 1040793 # Number of tag accesses 122210726SN/Asystem.iocache.tags.data_accesses 1040793 # Number of data accesses 122310585SN/Asystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 122410726SN/Asystem.iocache.ReadReq_misses::realview.ide 8876 # number of ReadReq misses 122510726SN/Asystem.iocache.ReadReq_misses::total 8913 # number of ReadReq misses 122610585SN/Asystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 122710585SN/Asystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 122810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 122910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 123010585SN/Asystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 123110726SN/Asystem.iocache.demand_misses::realview.ide 8876 # number of demand (read+write) misses 123210726SN/Asystem.iocache.demand_misses::total 8916 # number of demand (read+write) misses 123310585SN/Asystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 123410726SN/Asystem.iocache.overall_misses::realview.ide 8876 # number of overall misses 123510726SN/Asystem.iocache.overall_misses::total 8916 # number of overall misses 123610585SN/Asystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 123710726SN/Asystem.iocache.ReadReq_accesses::realview.ide 8876 # number of ReadReq accesses(hits+misses) 123810726SN/Asystem.iocache.ReadReq_accesses::total 8913 # number of ReadReq accesses(hits+misses) 123910585SN/Asystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 124010585SN/Asystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 124110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 124210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 124310585SN/Asystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 124410726SN/Asystem.iocache.demand_accesses::realview.ide 8876 # number of demand (read+write) accesses 124510726SN/Asystem.iocache.demand_accesses::total 8916 # number of demand (read+write) accesses 124610585SN/Asystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 124710726SN/Asystem.iocache.overall_accesses::realview.ide 8876 # number of overall (read+write) accesses 124810726SN/Asystem.iocache.overall_accesses::total 8916 # number of overall (read+write) accesses 124910585SN/Asystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 125010585SN/Asystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 125110585SN/Asystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 125210585SN/Asystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 125310585SN/Asystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 125410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 125510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 125610585SN/Asystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 125710585SN/Asystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 125810585SN/Asystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 125910585SN/Asystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 126010585SN/Asystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 126110585SN/Asystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 126210585SN/Asystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 126310585SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 126410585SN/Asystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 126510585SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 126610585SN/Asystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 126710585SN/Asystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 126810585SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 126910585SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 127010585SN/Asystem.iocache.writebacks::writebacks 106694 # number of writebacks 127110585SN/Asystem.iocache.writebacks::total 106694 # number of writebacks 127210585SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 127310892Sandreas.hansson@arm.comsystem.l2c.tags.replacements 1751385 # number of replacements 127410892Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 62313.380560 # Cycle average of tags in use 127510892Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 6017106 # Total number of references to valid blocks. 127610892Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 1809468 # Sample count of references to valid blocks. 127710892Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 3.325345 # Average number of references to valid blocks. 127810892Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 127910892Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 34286.931814 # Average occupied blocks per requestor 128010892Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 47.043983 # Average occupied blocks per requestor 128110892Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 59.106418 # Average occupied blocks per requestor 128210892Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 3327.548165 # Average occupied blocks per requestor 128310892Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 6997.138223 # Average occupied blocks per requestor 128410892Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 309.986034 # Average occupied blocks per requestor 128510892Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 428.835942 # Average occupied blocks per requestor 128610892Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 3021.438473 # Average occupied blocks per requestor 128710892Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 13835.351509 # Average occupied blocks per requestor 128810892Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.523177 # Average percentage of cache occupancy 128910892Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.000718 # Average percentage of cache occupancy 129010892Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.000902 # Average percentage of cache occupancy 129110892Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.050774 # Average percentage of cache occupancy 129210892Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.106768 # Average percentage of cache occupancy 129310892Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.004730 # Average percentage of cache occupancy 129410892Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.006544 # Average percentage of cache occupancy 129510892Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.046103 # Average percentage of cache occupancy 129610892Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.211111 # Average percentage of cache occupancy 129710892Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.950827 # Average percentage of cache occupancy 129810892Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 220 # Occupied blocks per task id 129910892Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 57863 # Occupied blocks per task id 130010892Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id 130110892Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 218 # Occupied blocks per task id 130210892Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id 130310892Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 545 # Occupied blocks per task id 130410892Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 3434 # Occupied blocks per task id 130510892Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 5577 # Occupied blocks per task id 130610892Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 48241 # Occupied blocks per task id 130710892Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.003357 # Percentage of cache occupancy per task id 130810892Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.882919 # Percentage of cache occupancy per task id 130910892Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 85814440 # Number of tag accesses 131010892Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 85814440 # Number of data accesses 131110892Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::writebacks 2758639 # number of Writeback hits 131210892Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::total 2758639 # number of Writeback hits 131310892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 13259 # number of UpgradeReq hits 131410892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 10916 # number of UpgradeReq hits 131510892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 24175 # number of UpgradeReq hits 131610892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 1481 # number of SCUpgradeReq hits 131710892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 1240 # number of SCUpgradeReq hits 131810892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 2721 # number of SCUpgradeReq hits 131910892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 318588 # number of ReadExReq hits 132010892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 264415 # number of ReadExReq hits 132110892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 583003 # number of ReadExReq hits 132210892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6289 # number of ReadSharedReq hits 132310892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 4561 # number of ReadSharedReq hits 132410892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 514584 # number of ReadSharedReq hits 132510892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 748348 # number of ReadSharedReq hits 132610892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5382 # number of ReadSharedReq hits 132710892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 3638 # number of ReadSharedReq hits 132810892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 486810 # number of ReadSharedReq hits 132910892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 695012 # number of ReadSharedReq hits 133010892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::total 2464624 # number of ReadSharedReq hits 133110892Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 6289 # number of demand (read+write) hits 133210892Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 4561 # number of demand (read+write) hits 133310892Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 514584 # number of demand (read+write) hits 133410892Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 1066936 # number of demand (read+write) hits 133510892Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 5382 # number of demand (read+write) hits 133610892Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 3638 # number of demand (read+write) hits 133710892Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 486810 # number of demand (read+write) hits 133810892Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 959427 # number of demand (read+write) hits 133910892Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 3047627 # number of demand (read+write) hits 134010892Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 6289 # number of overall hits 134110892Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 4561 # number of overall hits 134210892Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 514584 # number of overall hits 134310892Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 1066936 # number of overall hits 134410892Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 5382 # number of overall hits 134510892Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 3638 # number of overall hits 134610892Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 486810 # number of overall hits 134710892Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 959427 # number of overall hits 134810892Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 3047627 # number of overall hits 134910892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 58599 # number of UpgradeReq misses 135010892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 54084 # number of UpgradeReq misses 135110892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 112683 # number of UpgradeReq misses 135210892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 7811 # number of SCUpgradeReq misses 135310892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 7438 # number of SCUpgradeReq misses 135410892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 15249 # number of SCUpgradeReq misses 135510892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 816245 # number of ReadExReq misses 135610892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 547345 # number of ReadExReq misses 135710892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 1363590 # number of ReadExReq misses 135810892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2379 # number of ReadSharedReq misses 135910892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 1986 # number of ReadSharedReq misses 136010892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 54154 # number of ReadSharedReq misses 136110892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 180703 # number of ReadSharedReq misses 136210892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3463 # number of ReadSharedReq misses 136310892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.itb.walker 3437 # number of ReadSharedReq misses 136410892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 37696 # number of ReadSharedReq misses 136510892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 186059 # number of ReadSharedReq misses 136610892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::total 469877 # number of ReadSharedReq misses 136710892Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 2379 # number of demand (read+write) misses 136810892Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 1986 # number of demand (read+write) misses 136910892Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 54154 # number of demand (read+write) misses 137010892Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 996948 # number of demand (read+write) misses 137110892Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 3463 # number of demand (read+write) misses 137210892Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.itb.walker 3437 # number of demand (read+write) misses 137310892Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 37696 # number of demand (read+write) misses 137410892Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 733404 # number of demand (read+write) misses 137510892Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 1833467 # number of demand (read+write) misses 137610892Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 2379 # number of overall misses 137710892Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 1986 # number of overall misses 137810892Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 54154 # number of overall misses 137910892Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 996948 # number of overall misses 138010892Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 3463 # number of overall misses 138110892Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.itb.walker 3437 # number of overall misses 138210892Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 37696 # number of overall misses 138310892Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 733404 # number of overall misses 138410892Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 1833467 # number of overall misses 138510892Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::writebacks 2758639 # number of Writeback accesses(hits+misses) 138610892Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::total 2758639 # number of Writeback accesses(hits+misses) 138710892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 71858 # number of UpgradeReq accesses(hits+misses) 138810892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 65000 # number of UpgradeReq accesses(hits+misses) 138910892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 136858 # number of UpgradeReq accesses(hits+misses) 139010892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 9292 # number of SCUpgradeReq accesses(hits+misses) 139110892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 8678 # number of SCUpgradeReq accesses(hits+misses) 139210892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 17970 # number of SCUpgradeReq accesses(hits+misses) 139310892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 1134833 # number of ReadExReq accesses(hits+misses) 139410892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 811760 # number of ReadExReq accesses(hits+misses) 139510892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 1946593 # number of ReadExReq accesses(hits+misses) 139610892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8668 # number of ReadSharedReq accesses(hits+misses) 139710892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6547 # number of ReadSharedReq accesses(hits+misses) 139810892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 568738 # number of ReadSharedReq accesses(hits+misses) 139910892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 929051 # number of ReadSharedReq accesses(hits+misses) 140010892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8845 # number of ReadSharedReq accesses(hits+misses) 140110892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7075 # number of ReadSharedReq accesses(hits+misses) 140210892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 524506 # number of ReadSharedReq accesses(hits+misses) 140310892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 881071 # number of ReadSharedReq accesses(hits+misses) 140410892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::total 2934501 # number of ReadSharedReq accesses(hits+misses) 140510892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 8668 # number of demand (read+write) accesses 140610892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 6547 # number of demand (read+write) accesses 140710892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 568738 # number of demand (read+write) accesses 140810892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 2063884 # number of demand (read+write) accesses 140910892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 8845 # number of demand (read+write) accesses 141010892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 7075 # number of demand (read+write) accesses 141110892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 524506 # number of demand (read+write) accesses 141210892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 1692831 # number of demand (read+write) accesses 141310892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 4881094 # number of demand (read+write) accesses 141410892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 8668 # number of overall (read+write) accesses 141510892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 6547 # number of overall (read+write) accesses 141610892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 568738 # number of overall (read+write) accesses 141710892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 2063884 # number of overall (read+write) accesses 141810892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 8845 # number of overall (read+write) accesses 141910892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 7075 # number of overall (read+write) accesses 142010892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 524506 # number of overall (read+write) accesses 142110892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 1692831 # number of overall (read+write) accesses 142210892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 4881094 # number of overall (read+write) accesses 142310892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.815483 # miss rate for UpgradeReq accesses 142410892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.832062 # miss rate for UpgradeReq accesses 142510892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.823357 # miss rate for UpgradeReq accesses 142610892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.840616 # miss rate for SCUpgradeReq accesses 142710892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.857110 # miss rate for SCUpgradeReq accesses 142810892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.848581 # miss rate for SCUpgradeReq accesses 142910892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.719264 # miss rate for ReadExReq accesses 143010892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.674269 # miss rate for ReadExReq accesses 143110892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.700501 # miss rate for ReadExReq accesses 143210892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.274458 # miss rate for ReadSharedReq accesses 143310892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.303345 # miss rate for ReadSharedReq accesses 143410892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.095218 # miss rate for ReadSharedReq accesses 143510892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.194503 # miss rate for ReadSharedReq accesses 143610892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.391521 # miss rate for ReadSharedReq accesses 143710892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.485795 # miss rate for ReadSharedReq accesses 143810892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.071870 # miss rate for ReadSharedReq accesses 143910892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.211174 # miss rate for ReadSharedReq accesses 144010892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.160122 # miss rate for ReadSharedReq accesses 144110892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.274458 # miss rate for demand accesses 144210892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.303345 # miss rate for demand accesses 144310892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.095218 # miss rate for demand accesses 144410892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.483045 # miss rate for demand accesses 144510892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.391521 # miss rate for demand accesses 144610892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.485795 # miss rate for demand accesses 144710892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.071870 # miss rate for demand accesses 144810892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.433241 # miss rate for demand accesses 144910892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.375626 # miss rate for demand accesses 145010892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.274458 # miss rate for overall accesses 145110892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.303345 # miss rate for overall accesses 145210892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.095218 # miss rate for overall accesses 145310892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.483045 # miss rate for overall accesses 145410892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.391521 # miss rate for overall accesses 145510892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.485795 # miss rate for overall accesses 145610892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.071870 # miss rate for overall accesses 145710892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.433241 # miss rate for overall accesses 145810892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.375626 # miss rate for overall accesses 145910515SN/Asystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 146010515SN/Asystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 146110515SN/Asystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 146210515SN/Asystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 146310515SN/Asystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 146410515SN/Asystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 146510515SN/Asystem.l2c.fast_writes 0 # number of fast writes performed 146610515SN/Asystem.l2c.cache_copies 0 # number of cache copies performed 146710892Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 1472038 # number of writebacks 146810892Sandreas.hansson@arm.comsystem.l2c.writebacks::total 1472038 # number of writebacks 146910515SN/Asystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 147010892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 82131 # Transaction distribution 147110892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 560921 # Transaction distribution 147210827Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 38802 # Transaction distribution 147310827Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 38802 # Transaction distribution 147410892Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 1578732 # Transaction distribution 147510944Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 418759 # Transaction distribution 147610892Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 328366 # Transaction distribution 147710892Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 314759 # Transaction distribution 147810892Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 149960 # Transaction distribution 147910892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 1611572 # Transaction distribution 148010892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 1341565 # Transaction distribution 148110892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 478790 # Transaction distribution 148210892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 106728 # Transaction distribution 148310892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 106728 # Transaction distribution 148410726SN/Asystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122570 # Packet count per connected master and slave (bytes) 148510585SN/Asystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 148610726SN/Asystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27558 # Packet count per connected master and slave (bytes) 148710944Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6659522 # Packet count per connected master and slave (bytes) 148810944Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 6809742 # Packet count per connected master and slave (bytes) 148910892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346873 # Packet count per connected master and slave (bytes) 149010892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 346873 # Packet count per connected master and slave (bytes) 149110944Sandreas.hansson@arm.comsystem.membus.pkt_count::total 7156615 # Packet count per connected master and slave (bytes) 149210726SN/Asystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155677 # Cumulative packet size per connected master and slave (bytes) 149310585SN/Asystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 149410726SN/Asystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55116 # Cumulative packet size per connected master and slave (bytes) 149510892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 210336476 # Cumulative packet size per connected master and slave (bytes) 149610892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 210547473 # Cumulative packet size per connected master and slave (bytes) 149710892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7398848 # Cumulative packet size per connected master and slave (bytes) 149810892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7398848 # Cumulative packet size per connected master and slave (bytes) 149910892Sandreas.hansson@arm.comsystem.membus.pkt_size::total 217946321 # Cumulative packet size per connected master and slave (bytes) 150010585SN/Asystem.membus.snoops 0 # Total snoops (count) 150110944Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 4958639 # Request fanout histogram 150210585SN/Asystem.membus.snoop_fanout::mean 1 # Request fanout histogram 150310585SN/Asystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 150410585SN/Asystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 150510585SN/Asystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 150610944Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 4958639 100.00% 100.00% # Request fanout histogram 150710585SN/Asystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 150810585SN/Asystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 150910585SN/Asystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 151010585SN/Asystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 151110944Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 4958639 # Request fanout histogram 151210515SN/Asystem.realview.ethernet.txBytes 966 # Bytes Transmitted 151310515SN/Asystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 151410515SN/Asystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 151510515SN/Asystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 151610515SN/Asystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 151710515SN/Asystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 151810515SN/Asystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 151910515SN/Asystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 152010515SN/Asystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 152110515SN/Asystem.realview.ethernet.totBandwidth 164 # Total Bandwidth (bits/s) 152210515SN/Asystem.realview.ethernet.totPackets 3 # Total Packets 152310515SN/Asystem.realview.ethernet.totBytes 966 # Total Bytes 152410515SN/Asystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 152510515SN/Asystem.realview.ethernet.txBandwidth 164 # Transmit Bandwidth (bits/s) 152610515SN/Asystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 152710515SN/Asystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 152810515SN/Asystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 152910515SN/Asystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 153010515SN/Asystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 153110515SN/Asystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 153210515SN/Asystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 153310515SN/Asystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 153410515SN/Asystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 153510515SN/Asystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 153610515SN/Asystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 153710515SN/Asystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 153810515SN/Asystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 153910515SN/Asystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 154010515SN/Asystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 154110515SN/Asystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 154210515SN/Asystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 154310515SN/Asystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 154410515SN/Asystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 154510515SN/Asystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 154610515SN/Asystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 154710515SN/Asystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 154810515SN/Asystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 154910515SN/Asystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 155010515SN/Asystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 155110515SN/Asystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 155210515SN/Asystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 155310515SN/Asystem.realview.ethernet.droppedPackets 0 # number of packets dropped 155410892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 82133 # Transaction distribution 155510892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 3716153 # Transaction distribution 155610827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 38802 # Transaction distribution 155710827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 38802 # Transaction distribution 155810892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::Writeback 2758639 # Transaction distribution 155910892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::CleanEvict 2438361 # Transaction distribution 156010892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 330513 # Transaction distribution 156110892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 317480 # Transaction distribution 156210892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 647993 # Transaction distribution 156310892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 2216600 # Transaction distribution 156410892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 2216600 # Transaction distribution 156510892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 3634020 # Transaction distribution 156610892Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9937165 # Packet count per connected master and slave (bytes) 156710892Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8498931 # Packet count per connected master and slave (bytes) 156810892Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 18436096 # Packet count per connected master and slave (bytes) 156910892Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 301383709 # Cumulative packet size per connected master and slave (bytes) 157010892Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 250013636 # Cumulative packet size per connected master and slave (bytes) 157110892Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 551397345 # Cumulative packet size per connected master and slave (bytes) 157210892Sandreas.hansson@arm.comsystem.toL2Bus.snoops 117333 # Total snoops (count) 157310892Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 11932192 # Request fanout histogram 157410892Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 1.009692 # Request fanout histogram 157510892Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.097969 # Request fanout histogram 157610515SN/Asystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 157710515SN/Asystem.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 157810892Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 11816548 99.03% 99.03% # Request fanout histogram 157910892Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 115644 0.97% 100.00% # Request fanout histogram 158010515SN/Asystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 158110515SN/Asystem.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 158210515SN/Asystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 158310892Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 11932192 # Request fanout histogram 158410515SN/A 158510515SN/A---------- End Simulation Statistics ---------- 1586