xref: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 47.177080                       # Number of seconds simulated
sim_ticks                                47177080006500                       # Number of ticks simulated
final_tick                               47177080006500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1049876                       # Simulator instruction rate (inst/s)
host_op_rate                                  1235062                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            50706899360                       # Simulator tick rate (ticks/s)
host_mem_usage                                 670076                       # Number of bytes of host memory used
host_seconds                                   930.39                       # Real time elapsed on the host
sim_insts                                   976792036                       # Number of instructions simulated
sim_ops                                    1149086878                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker       149696                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       124032                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          3867700                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         35125336                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       224640                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       222848                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          2692808                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         38798848                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        404992                       # Number of bytes read from this memory
system.physmem.bytes_read::total             81610900                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      3867700                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      2692808                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         6560508                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks    100759808                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20812                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::total         100780624                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         2339                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         1938                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst            100840                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            548855                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         3510                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         3482                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             42182                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            606250                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6328                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1315724                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1574372                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2602                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1576975                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          3173                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          2629                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               81983                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              744542                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          4762                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          4724                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               57079                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              822409                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             8585                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1729885                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          81983                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          57079                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             139061                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2135779                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                441                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2136220                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2135779                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         3173                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         2629                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              81983                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             744984                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         4762                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         4724                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              57079                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             822409                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            8585                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3866105                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data            8                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           204                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          160                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           16                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             46                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                4                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst            1                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            3                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               4                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                   123914                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               123914                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walkWaitTime::samples       123914                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0         123914    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       123914                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walksPending::samples     22846000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0       22846000    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total     22846000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        95376     89.74%     89.74% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        10905     10.26%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total       106281                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       123914                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       123914                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       106281                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       106281                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       230195                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    91355479                       # DTB read hits
system.cpu0.dtb.read_misses                     87819                       # DTB read misses
system.cpu0.dtb.write_hits                   84601943                       # DTB write hits
system.cpu0.dtb.write_misses                    36095                       # DTB write misses
system.cpu0.dtb.flush_tlb                          16                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              49428                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                   1118                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   36260                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  5461                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                    10344                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                91443298                       # DTB read accesses
system.cpu0.dtb.write_accesses               84638038                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        175957422                       # DTB hits
system.cpu0.dtb.misses                         123914                       # DTB misses
system.cpu0.dtb.accesses                    176081336                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                    60226                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                60226                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walkWaitTime::samples        60226                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0          60226    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        60226                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walksPending::samples     22844500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0       22844500    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total     22844500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        54190     98.81%     98.81% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M          654      1.19%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        54844                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        60226                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        60226                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        54844                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        54844                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       115070                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   491372488                       # ITB inst hits
system.cpu0.itb.inst_misses                     60226                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          16                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              49428                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                   1118                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   25015                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               491432714                       # ITB inst accesses
system.cpu0.itb.hits                        491372488                       # DTB hits
system.cpu0.itb.misses                          60226                       # DTB misses
system.cpu0.itb.accesses                    491432714                       # DTB accesses
system.cpu0.numCycles                     94354173207                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                  491139120                       # Number of instructions committed
system.cpu0.committedOps                    577575160                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            529301791                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                523058                       # Number of float alu accesses
system.cpu0.num_func_calls                   28573576                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     75495865                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   529301791                       # number of integer instructions
system.cpu0.num_fp_insts                       523058                       # number of float instructions
system.cpu0.num_int_register_reads          775565033                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         419986522                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              843711                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             444676                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           132153354                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes          131825344                       # number of times the CC registers were written
system.cpu0.num_mem_refs                    176058068                       # number of memory refs
system.cpu0.num_load_insts                   91428761                       # Number of load instructions
system.cpu0.num_store_insts                  84629307                       # Number of store instructions
system.cpu0.num_idle_cycles              93776262262.183929                       # Number of idle cycles
system.cpu0.num_busy_cycles              577910944.816068                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.006125                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.993875                       # Percentage of idle cycles
system.cpu0.Branches                        109891880                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                400497126     69.30%     69.30% # Class of executed instruction
system.cpu0.op_class::IntMult                 1218559      0.21%     69.51% # Class of executed instruction
system.cpu0.op_class::IntDiv                    59561      0.01%     69.52% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  8      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                 13      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                 21      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc             73140      0.01%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::MemRead                91428761     15.82%     85.36% # Class of executed instruction
system.cpu0.op_class::MemWrite               84629307     14.64%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 577906497                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   13193                       # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements          6189405                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          506.263112                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          169698310                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          6189917                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            27.415280                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         35630500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   506.263112                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.988795                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.988795                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          198                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          303                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           11                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        358274198                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       358274198                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     84971856                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       84971856                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     79868150                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      79868150                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       214674                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       214674                       # number of SoftPFReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       260533                       # number of WriteInvalidateReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::total       260533                       # number of WriteInvalidateReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      2068908                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      2068908                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2028668                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      2028668                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    164840006                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       164840006                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    165054680                       # number of overall hits
system.cpu0.dcache.overall_hits::total      165054680                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      3260277                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      3260277                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1458399                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1458399                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       767112                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       767112                       # number of SoftPFReq misses
system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data       819206                       # number of WriteInvalidateReq misses
system.cpu0.dcache.WriteInvalidateReq_misses::total       819206                       # number of WriteInvalidateReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       116959                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       116959                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data       156094                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total       156094                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      4718676                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       4718676                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      5485788                       # number of overall misses
system.cpu0.dcache.overall_misses::total      5485788                       # number of overall misses
system.cpu0.dcache.ReadReq_accesses::cpu0.data     88232133                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     88232133                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     81326549                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     81326549                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       981786                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       981786                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data      1079739                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::total      1079739                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2185867                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      2185867                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2184762                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      2184762                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    169558682                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    169558682                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    170540468                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    170540468                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.036951                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.036951                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.017933                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.017933                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.781343                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.781343                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data     0.758707                       # miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.758707                       # miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.053507                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.053507                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.071447                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.071447                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.027829                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.027829                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.032167                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.032167                       # miss rate for overall accesses
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      4407988                       # number of writebacks
system.cpu0.dcache.writebacks::total          4407988                       # number of writebacks
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          5467768                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.988996                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          485959047                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          5468280                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            88.868721                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       5759896500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.988996                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999979                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999979                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          202                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          262                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           47                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        988322949                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       988322949                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    485959047                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      485959047                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    485959047                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       485959047                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    485959047                       # number of overall hits
system.cpu0.icache.overall_hits::total      485959047                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      5468285                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      5468285                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      5468285                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       5468285                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      5468285                       # number of overall misses
system.cpu0.icache.overall_misses::total      5468285                       # number of overall misses
system.cpu0.icache.ReadReq_accesses::cpu0.inst    491427332                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    491427332                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    491427332                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    491427332                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    491427332                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    491427332                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011127                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.011127                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011127                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.011127                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011127                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.011127                       # miss rate for overall accesses
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified            0                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage            0                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements         2648971                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16219.904236                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs          11415809                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs         2665005                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            4.283598                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle       290949000                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks  5428.449185                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    50.127041                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    51.911966                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4608.843039                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data  6080.573004                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.331326                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003060                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.003168                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.281301                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.371129                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.989984                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           65                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15969                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           50                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            4                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           10                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          181                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1130                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4626                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         5485                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         4547                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.003967                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.974670                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses       274915962                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses      274915962                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       266204                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       139155                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.inst      4917807                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.data      2910870                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total       8234036                       # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks      4407988                       # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total      4407988                       # number of Writeback hits
system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data       219663                       # number of WriteInvalidateReq hits
system.cpu0.l2cache.WriteInvalidateReq_hits::total       219663                       # number of WriteInvalidateReq hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data         3562                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total         3562                       # number of UpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       630387                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       630387                       # number of ReadExReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       266204                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker       139155                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      4917807                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data      3541257                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        8864423                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       266204                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker       139155                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      4917807                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data      3541257                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       8864423                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        10959                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         8288                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.inst       550478                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.data      1233478                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total      1803203                       # number of ReadReq misses
system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data       599179                       # number of WriteInvalidateReq misses
system.cpu0.l2cache.WriteInvalidateReq_misses::total       599179                       # number of WriteInvalidateReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       125865                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total       125865                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       156094                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total       156094                       # number of SCUpgradeReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data       698949                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total       698949                       # number of ReadExReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        10959                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker         8288                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       550478                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data      1932427                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total      2502152                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        10959                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker         8288                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       550478                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data      1932427                       # number of overall misses
system.cpu0.l2cache.overall_misses::total      2502152                       # number of overall misses
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       277163                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       147443                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      5468285                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.data      4144348                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total     10037239                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks      4407988                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total      4407988                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data       818842                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.l2cache.WriteInvalidateReq_accesses::total       818842                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       129427                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total       129427                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       156094                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total       156094                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1329336                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total      1329336                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       277163                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       147443                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      5468285                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data      5473684                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total     11366575                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       277163                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       147443                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      5468285                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data      5473684                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total     11366575                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.039540                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.056212                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.100667                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.297629                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.179651                       # miss rate for ReadReq accesses
system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data     0.731739                       # miss rate for WriteInvalidateReq accesses
system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total     0.731739                       # miss rate for WriteInvalidateReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.972479                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.972479                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.525788                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.525788                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.039540                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.056212                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.100667                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.353040                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.220132                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.039540                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.056212                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.100667                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.353040                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.220132                       # miss rate for overall accesses
system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks      1542533                       # number of writebacks
system.cpu0.l2cache.writebacks::total         1542533                       # number of writebacks
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq      10228504                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp     10228504                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        32523                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        32523                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback      4407988                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq       818842                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp       818842                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq       129427                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       156094                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       285521                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq      1329336                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp      1329336                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     11022820                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     17694214                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       359792                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       720614                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total         29797440                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    350142740                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    685026670                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1439168                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      2882456                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total        1039491034                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    3383860                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples     20196192                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       5.158528                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.365236                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::5          16994523     84.15%     84.15% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::6           3201669     15.85%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total      20196192                       # Request fanout histogram
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                   144852                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               144852                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walkWaitTime::samples       144852                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0         144852    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       144852                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walksPending::samples   -274403872                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     -274403872    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   -274403872                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K       112422     89.02%     89.02% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M        13865     10.98%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total       126287                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       144852                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       144852                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       126287                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       126287                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       271139                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    91720002                       # DTB read hits
system.cpu1.dtb.read_misses                    112244                       # DTB read misses
system.cpu1.dtb.write_hits                   82499013                       # DTB write hits
system.cpu1.dtb.write_misses                    32608                       # DTB write misses
system.cpu1.dtb.flush_tlb                          16                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              49428                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                   1118                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   45118                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  4542                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    11534                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                91832246                       # DTB read accesses
system.cpu1.dtb.write_accesses               82531621                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        174219015                       # DTB hits
system.cpu1.dtb.misses                         144852                       # DTB misses
system.cpu1.dtb.accesses                    174363867                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                    61939                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                61939                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walkWaitTime::samples        61939                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0          61939    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        61939                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walksPending::samples   -274404872                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     -274404872    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   -274404872                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        54929     99.06%     99.06% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M          521      0.94%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        55450                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        61939                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        61939                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        55450                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        55450                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       117389                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   485906850                       # ITB inst hits
system.cpu1.itb.inst_misses                     61939                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          16                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              49428                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                   1118                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   31863                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               485968789                       # ITB inst accesses
system.cpu1.itb.hits                        485906850                       # DTB hits
system.cpu1.itb.misses                          61939                       # DTB misses
system.cpu1.itb.accesses                    485968789                       # DTB accesses
system.cpu1.numCycles                     94354166192                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                  485652916                       # Number of instructions committed
system.cpu1.committedOps                    571511718                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses            524558211                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                375128                       # Number of float alu accesses
system.cpu1.num_func_calls                   28666071                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts     74347572                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                   524558211                       # number of integer instructions
system.cpu1.num_fp_insts                       375128                       # number of float instructions
system.cpu1.num_int_register_reads          774388464                       # number of times the integer registers were read
system.cpu1.num_int_register_writes         417530639                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads              610571                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes             303256                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           128278137                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes          127991607                       # number of times the CC registers were written
system.cpu1.num_mem_refs                    174340371                       # number of memory refs
system.cpu1.num_load_insts                   91819242                       # Number of load instructions
system.cpu1.num_store_insts                  82521129                       # Number of store instructions
system.cpu1.num_idle_cycles              93782340058.888657                       # Number of idle cycles
system.cpu1.num_busy_cycles              571826133.111340                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.006060                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.993940                       # Percentage of idle cycles
system.cpu1.Branches                        108195111                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                396230726     69.29%     69.29% # Class of executed instruction
system.cpu1.op_class::IntMult                 1151823      0.20%     69.49% # Class of executed instruction
system.cpu1.op_class::IntDiv                    61886      0.01%     69.51% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc             36426      0.01%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::MemRead                91819242     16.06%     85.57% # Class of executed instruction
system.cpu1.op_class::MemWrite               82521129     14.43%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                 571821232                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    6178                       # number of quiesce instructions executed
system.cpu1.dcache.tags.replacements          6025220                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          443.938244                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs          168203685                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs          6025731                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            27.914237                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     8470277778500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   443.938244                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.867067                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.867067                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0          151                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          360                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses        354758936                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses       354758936                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data     85201700                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       85201700                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data     78314445                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total      78314445                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data       188411                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total       188411                       # number of SoftPFReq hits
system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data        65692                       # number of WriteInvalidateReq hits
system.cpu1.dcache.WriteInvalidateReq_hits::total        65692                       # number of WriteInvalidateReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      2073864                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total      2073864                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data      2064069                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total      2064069                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data    163516145                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total       163516145                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data    163704556                       # number of overall hits
system.cpu1.dcache.overall_hits::total      163704556                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data      3403274                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total      3403274                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      1467363                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      1467363                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data       796168                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total       796168                       # number of SoftPFReq misses
system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data       438523                       # number of WriteInvalidateReq misses
system.cpu1.dcache.WriteInvalidateReq_misses::total       438523                       # number of WriteInvalidateReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       149383                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total       149383                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data       157982                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total       157982                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      4870637                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       4870637                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      5666805                       # number of overall misses
system.cpu1.dcache.overall_misses::total      5666805                       # number of overall misses
system.cpu1.dcache.ReadReq_accesses::cpu1.data     88604974                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     88604974                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data     79781808                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total     79781808                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       984579                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       984579                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data       504215                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.dcache.WriteInvalidateReq_accesses::total       504215                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      2223247                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total      2223247                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      2222051                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total      2222051                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data    168386782                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total    168386782                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data    169371361                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total    169371361                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.038410                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.038410                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.018392                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.018392                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.808638                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.808638                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data     0.869714                       # miss rate for WriteInvalidateReq accesses
system.cpu1.dcache.WriteInvalidateReq_miss_rate::total     0.869714                       # miss rate for WriteInvalidateReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.067191                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.067191                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.071097                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.071097                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.028925                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.028925                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.033458                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.033458                       # miss rate for overall accesses
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks      4091318                       # number of writebacks
system.cpu1.dcache.writebacks::total          4091318                       # number of writebacks
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements          4818195                       # number of replacements
system.cpu1.icache.tags.tagsinuse          496.412963                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs          481143593                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          4818707                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            99.849107                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     8470205816000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   496.412963                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.969557                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.969557                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          329                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          144                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses        976743307                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses       976743307                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst    481143593                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total      481143593                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst    481143593                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total       481143593                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst    481143593                       # number of overall hits
system.cpu1.icache.overall_hits::total      481143593                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      4818707                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      4818707                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      4818707                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       4818707                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      4818707                       # number of overall misses
system.cpu1.icache.overall_misses::total      4818707                       # number of overall misses
system.cpu1.icache.ReadReq_accesses::cpu1.inst    485962300                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total    485962300                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst    485962300                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total    485962300                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst    485962300                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total    485962300                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.009916                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.009916                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.009916                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.009916                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.009916                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.009916                       # miss rate for overall accesses
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified            0                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage            0                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements         2333825                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       13484.024344                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs          11006559                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs         2349876                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs            4.683889                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle    9726491548000                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks  5253.379361                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    67.604678                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    75.064726                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  2656.476360                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data  5431.499219                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.320641                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004126                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.004582                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.162138                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.331512                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.823000                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1023          103                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        15948                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::0            1                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            4                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           59                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           13                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           26                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           78                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1580                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         5821                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4453                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         4016                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.006287                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.973389                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses       257480243                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses      257480243                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       323221                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       141798                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.inst      4279723                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.data      3095607                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total       7840349                       # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks      4091318                       # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total      4091318                       # number of Writeback hits
system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data       167179                       # number of WriteInvalidateReq hits
system.cpu1.l2cache.WriteInvalidateReq_hits::total       167179                       # number of WriteInvalidateReq hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         3859                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total         3859                       # number of UpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data       621347                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total       621347                       # number of ReadExReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       323221                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker       141798                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      4279723                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data      3716954                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total        8461696                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       323221                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker       141798                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      4279723                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data      3716954                       # number of overall hits
system.cpu1.l2cache.overall_hits::total       8461696                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        12537                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         9802                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.inst       538984                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.data      1253218                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total      1814541                       # number of ReadReq misses
system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data       271117                       # number of WriteInvalidateReq misses
system.cpu1.l2cache.WriteInvalidateReq_misses::total       271117                       # number of WriteInvalidateReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       133664                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total       133664                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       157982                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total       157982                       # number of SCUpgradeReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data       708720                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total       708720                       # number of ReadExReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        12537                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker         9802                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       538984                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data      1961938                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total      2523261                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        12537                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker         9802                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       538984                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data      1961938                       # number of overall misses
system.cpu1.l2cache.overall_misses::total      2523261                       # number of overall misses
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       335758                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       151600                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst      4818707                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.data      4348825                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total      9654890                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks      4091318                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total      4091318                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data       438296                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.l2cache.WriteInvalidateReq_accesses::total       438296                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       137523                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total       137523                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       157982                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total       157982                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1330067                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total      1330067                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       335758                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       151600                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      4818707                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data      5678892                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total     10984957                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       335758                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       151600                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      4818707                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data      5678892                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total     10984957                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.037339                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.064657                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.111852                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.288174                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.187940                       # miss rate for ReadReq accesses
system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data     0.618571                       # miss rate for WriteInvalidateReq accesses
system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total     0.618571                       # miss rate for WriteInvalidateReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.971939                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.971939                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.532845                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.532845                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.037339                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.064657                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.111852                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.345479                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.229701                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.037339                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.064657                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.111852                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.345479                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.229701                       # miss rate for overall accesses
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks      1212706                       # number of writebacks
system.cpu1.l2cache.writebacks::total         1212706                       # number of writebacks
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq       9779239                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp      9779239                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq         6380                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         6380                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback      4091318                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq       438296                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp       438296                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq       137523                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       157982                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp       295505                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq      1330067                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp      1330067                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      9637674                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16942172                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       370292                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       840154                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total         27790292                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    308397768                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    653382681                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1481168                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      3360616                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total         966622233                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                    3659793                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples     19426876                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       5.180108                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.384277                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::5          15927941     81.99%     81.99% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::6           3498935     18.01%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total      19426876                       # Request fanout histogram
system.iobus.trans_dist::ReadReq                40346                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40346                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136741                       # Transaction distribution
system.iobus.trans_dist::WriteResp              30013                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp       106728                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47950                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122884                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  354174                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47970                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155991                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338856                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7338856                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7496933                       # Cumulative packet size per connected master and slave (bytes)
system.iocache.tags.replacements               115586                       # number of replacements
system.iocache.tags.tagsinuse               11.286927                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115602                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         9107775783009                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.855232                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     7.431695                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.240952                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.464481                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.705433                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1040802                       # Number of tag accesses
system.iocache.tags.data_accesses             1040802                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8877                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8914                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide       106728                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total       106728                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8877                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8917                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8877                       # number of overall misses
system.iocache.overall_misses::total             8917                       # number of overall misses
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8877                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8914                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide       106728                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total       106728                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8877                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8917                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8877                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8917                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106694                       # number of writebacks
system.iocache.writebacks::total               106694                       # number of writebacks
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                  1764050                       # number of replacements
system.l2c.tags.tagsinuse                62893.103184                       # Cycle average of tags in use
system.l2c.tags.total_refs                    3693923                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1823047                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.026236                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                482634500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   35252.715261                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    32.297168                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker    36.889266                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3199.431904                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     6870.253722                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   308.072507                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   447.332489                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     2890.642136                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data    13855.468731                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.537914                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000493                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000563                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.048819                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.104832                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.004701                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.006826                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.044108                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.211418                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.959673                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023          209                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        58788                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2            4                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          204                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          542                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         3602                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5588                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        49009                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.003189                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.897034                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 66315846                       # Number of tag accesses
system.l2c.tags.data_accesses                66315846                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker         5920                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         4325                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             492739                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             723130                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker         5730                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         3764                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             496903                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             707011                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                2439522                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks         2755239                       # number of Writeback hits
system.l2c.Writeback_hits::total              2755239                       # number of Writeback hits
system.l2c.WriteInvalidateReq_hits::cpu0.data       115462                       # number of WriteInvalidateReq hits
system.l2c.WriteInvalidateReq_hits::cpu1.data       102925                       # number of WriteInvalidateReq hits
system.l2c.WriteInvalidateReq_hits::total       218387                       # number of WriteInvalidateReq hits
system.l2c.UpgradeReq_hits::cpu0.data           13978                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data           10743                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               24721                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data          1494                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data          1282                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total              2776                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           196550                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data           177871                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               374421                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker          5920                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          4325                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              492739                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              919680                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          5730                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          3764                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              496903                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              884882                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2813943                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         5920                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         4325                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             492739                       # number of overall hits
system.l2c.overall_hits::cpu0.data             919680                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         5730                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         3764                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             496903                       # number of overall hits
system.l2c.overall_hits::cpu1.data             884882                       # number of overall hits
system.l2c.overall_hits::total                2813943                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker         2339                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker         1938                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst            57739                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data           182657                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker         3510                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker         3482                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst            42081                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data           192722                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               486468                       # number of ReadReq misses
system.l2c.WriteInvalidateReq_misses::cpu0.data       475939                       # number of WriteInvalidateReq misses
system.l2c.WriteInvalidateReq_misses::cpu1.data       161383                       # number of WriteInvalidateReq misses
system.l2c.WriteInvalidateReq_misses::total       637322                       # number of WriteInvalidateReq misses
system.l2c.UpgradeReq_misses::cpu0.data         57732                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         55051                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total            112783                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data         7557                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         7409                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total           14966                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         376574                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data         420815                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             797389                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker         2339                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         1938                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             57739                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            559231                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         3510                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         3482                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             42081                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            613537                       # number of demand (read+write) misses
system.l2c.demand_misses::total               1283857                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         2339                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         1938                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            57739                       # number of overall misses
system.l2c.overall_misses::cpu0.data           559231                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         3510                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         3482                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            42081                       # number of overall misses
system.l2c.overall_misses::cpu1.data           613537                       # number of overall misses
system.l2c.overall_misses::total              1283857                       # number of overall misses
system.l2c.ReadReq_accesses::cpu0.dtb.walker         8259                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         6263                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         550478                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         905787                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker         9240                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         7246                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         538984                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         899733                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2925990                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks      2755239                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          2755239                       # number of Writeback accesses(hits+misses)
system.l2c.WriteInvalidateReq_accesses::cpu0.data       591401                       # number of WriteInvalidateReq accesses(hits+misses)
system.l2c.WriteInvalidateReq_accesses::cpu1.data       264308                       # number of WriteInvalidateReq accesses(hits+misses)
system.l2c.WriteInvalidateReq_accesses::total       855709                       # number of WriteInvalidateReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        71710                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data        65794                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total          137504                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data         9051                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         8691                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total         17742                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       573124                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       598686                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total          1171810                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         8259                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         6263                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          550478                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         1478911                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         9240                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         7246                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          538984                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data         1498419                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             4097800                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         8259                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         6263                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         550478                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        1478911                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         9240                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         7246                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         538984                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data        1498419                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            4097800                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.283206                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.309436                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.104889                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.201656                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.379870                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.480541                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.078075                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.214199                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.166258                       # miss rate for ReadReq accesses
system.l2c.WriteInvalidateReq_miss_rate::cpu0.data     0.804765                       # miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_miss_rate::cpu1.data     0.610587                       # miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_miss_rate::total     0.744788                       # miss rate for WriteInvalidateReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.805076                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.836718                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.820216                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.834935                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.852491                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.843535                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.657055                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.702898                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.680476                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.283206                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.309436                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.104889                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.378137                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.379870                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.480541                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.078075                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.409456                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.313304                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.283206                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.309436                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.104889                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.378137                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.379870                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.480541                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.078075                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.409456                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.313304                       # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks             1467678                       # number of writebacks
system.l2c.writebacks::total                  1467678                       # number of writebacks
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              577534                       # Transaction distribution
system.membus.trans_dist::ReadResp             577534                       # Transaction distribution
system.membus.trans_dist::WriteReq              38903                       # Transaction distribution
system.membus.trans_dist::WriteResp             38903                       # Transaction distribution
system.membus.trans_dist::Writeback           1574372                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq       739425                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp       739425                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           325897                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq         311300                       # Transaction distribution
system.membus.trans_dist::UpgradeResp          149445                       # Transaction distribution
system.membus.trans_dist::ReadExReq            961374                       # Transaction distribution
system.membus.trans_dist::ReadExResp           780321                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122884                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           92                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        27406                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      6326067                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      6476449                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       337984                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       337984                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                6814433                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155991                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          204                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        54812                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    215692580                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    215903587                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14229504                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total     14229504                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               230133091                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples           4407750                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 4407750    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             4407750                       # Request fanout histogram
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             164                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              164                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.toL2Bus.trans_dist::ReadReq            3699896                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           3699896                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             38903                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            38903                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback          2755239                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq       855709                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateResp       855709                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          328922                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq        314076                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         642998                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq          1352863                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp         1352863                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8525495                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7410482                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              15935977                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    295216066                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    254408545                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              549624611                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          117315                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          9340198                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.012381                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.110581                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                9224553     98.76%     98.76% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                 115645      1.24%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            9340198                       # Request fanout histogram

---------- End Simulation Statistics   ----------