stats.txt revision 10585
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.177080 # Number of seconds simulated 4sim_ticks 47177080006500 # Number of ticks simulated 5final_tick 47177080006500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1024538 # Simulator instruction rate (inst/s) 8host_op_rate 1205255 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 49483118923 # Simulator tick rate (ticks/s) 10host_mem_usage 669884 # Number of bytes of host memory used 11host_seconds 953.40 # Real time elapsed on the host 12sim_insts 976792036 # Number of instructions simulated 13sim_ops 1149086878 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 149696 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 124032 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 3867700 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 35125336 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.dtb.walker 224640 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.itb.walker 222848 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 2692808 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 38798848 # Number of bytes read from this memory 24system.physmem.bytes_read::realview.ide 404992 # Number of bytes read from this memory 25system.physmem.bytes_read::total 81610900 # Number of bytes read from this memory 26system.physmem.bytes_inst_read::cpu0.inst 3867700 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu1.inst 2692808 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::total 6560508 # Number of instructions bytes read from this memory 29system.physmem.bytes_written::writebacks 100759808 # Number of bytes written to this memory 30system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 32system.physmem.bytes_written::total 100780624 # Number of bytes written to this memory 33system.physmem.num_reads::cpu0.dtb.walker 2339 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.itb.walker 1938 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.inst 100840 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.data 548855 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.dtb.walker 3510 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.itb.walker 3482 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.inst 42182 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.data 606250 # Number of read requests responded to by this memory 41system.physmem.num_reads::realview.ide 6328 # Number of read requests responded to by this memory 42system.physmem.num_reads::total 1315724 # Number of read requests responded to by this memory 43system.physmem.num_writes::writebacks 1574372 # Number of write requests responded to by this memory 44system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory 45system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 46system.physmem.num_writes::total 1576975 # Number of write requests responded to by this memory 47system.physmem.bw_read::cpu0.dtb.walker 3173 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu0.itb.walker 2629 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu0.inst 81983 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.data 744542 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu1.dtb.walker 4762 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.itb.walker 4724 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu1.inst 57079 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.data 822409 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::realview.ide 8585 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::total 1729885 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_inst_read::cpu0.inst 81983 # Instruction read bandwidth from this memory (bytes/s) 58system.physmem.bw_inst_read::cpu1.inst 57079 # Instruction read bandwidth from this memory (bytes/s) 59system.physmem.bw_inst_read::total 139061 # Instruction read bandwidth from this memory (bytes/s) 60system.physmem.bw_write::writebacks 2135779 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_write::cpu0.data 441 # Write bandwidth from this memory (bytes/s) 62system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 63system.physmem.bw_write::total 2136220 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_total::writebacks 2135779 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu0.dtb.walker 3173 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.itb.walker 2629 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu0.inst 81983 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.data 744984 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu1.dtb.walker 4762 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu1.itb.walker 4724 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.inst 57079 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu1.data 822409 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::realview.ide 8585 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::total 3866105 # Total bandwidth to/from this memory (bytes/s) 75system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 76system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 77system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 78system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 79system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 80system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 81system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 82system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 83system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 84system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 85system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 86system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 87system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 88system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 89system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 90system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 91system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 92system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 93system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 94system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 95system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 96system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 97system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 98system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 99system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 100system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 101system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 102system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 103system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 104system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 105system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 106system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 107system.cpu_clk_domain.clock 500 # Clock period in ticks 108system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 109system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 110system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 111system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 112system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 113system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 114system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 115system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 116system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 117system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 118system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 119system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 120system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 121system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 122system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 123system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 124system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 125system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 126system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 127system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 128system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 129system.cpu0.dtb.inst_hits 0 # ITB inst hits 130system.cpu0.dtb.inst_misses 0 # ITB inst misses 131system.cpu0.dtb.read_hits 91355479 # DTB read hits 132system.cpu0.dtb.read_misses 87819 # DTB read misses 133system.cpu0.dtb.write_hits 84601943 # DTB write hits 134system.cpu0.dtb.write_misses 36095 # DTB write misses 135system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed 136system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 137system.cpu0.dtb.flush_tlb_mva_asid 49428 # Number of times TLB was flushed by MVA & ASID 138system.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 139system.cpu0.dtb.flush_entries 36260 # Number of entries that have been flushed from TLB 140system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 141system.cpu0.dtb.prefetch_faults 5461 # Number of TLB faults due to prefetch 142system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 143system.cpu0.dtb.perms_faults 10344 # Number of TLB faults due to permissions restrictions 144system.cpu0.dtb.read_accesses 91443298 # DTB read accesses 145system.cpu0.dtb.write_accesses 84638038 # DTB write accesses 146system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 147system.cpu0.dtb.hits 175957422 # DTB hits 148system.cpu0.dtb.misses 123914 # DTB misses 149system.cpu0.dtb.accesses 176081336 # DTB accesses 150system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 151system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 152system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 153system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 154system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 155system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 156system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 157system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 158system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 159system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 160system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 161system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 162system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 163system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 164system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 165system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 166system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 167system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 168system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 169system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 170system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 171system.cpu0.itb.inst_hits 491372488 # ITB inst hits 172system.cpu0.itb.inst_misses 60226 # ITB inst misses 173system.cpu0.itb.read_hits 0 # DTB read hits 174system.cpu0.itb.read_misses 0 # DTB read misses 175system.cpu0.itb.write_hits 0 # DTB write hits 176system.cpu0.itb.write_misses 0 # DTB write misses 177system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed 178system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 179system.cpu0.itb.flush_tlb_mva_asid 49428 # Number of times TLB was flushed by MVA & ASID 180system.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 181system.cpu0.itb.flush_entries 25015 # Number of entries that have been flushed from TLB 182system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 183system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 184system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 185system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 186system.cpu0.itb.read_accesses 0 # DTB read accesses 187system.cpu0.itb.write_accesses 0 # DTB write accesses 188system.cpu0.itb.inst_accesses 491432714 # ITB inst accesses 189system.cpu0.itb.hits 491372488 # DTB hits 190system.cpu0.itb.misses 60226 # DTB misses 191system.cpu0.itb.accesses 491432714 # DTB accesses 192system.cpu0.numCycles 94354173207 # number of cpu cycles simulated 193system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 194system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 195system.cpu0.committedInsts 491139120 # Number of instructions committed 196system.cpu0.committedOps 577575160 # Number of ops (including micro ops) committed 197system.cpu0.num_int_alu_accesses 529301791 # Number of integer alu accesses 198system.cpu0.num_fp_alu_accesses 523058 # Number of float alu accesses 199system.cpu0.num_func_calls 28573576 # number of times a function call or return occured 200system.cpu0.num_conditional_control_insts 75495865 # number of instructions that are conditional controls 201system.cpu0.num_int_insts 529301791 # number of integer instructions 202system.cpu0.num_fp_insts 523058 # number of float instructions 203system.cpu0.num_int_register_reads 775565033 # number of times the integer registers were read 204system.cpu0.num_int_register_writes 419986522 # number of times the integer registers were written 205system.cpu0.num_fp_register_reads 843711 # number of times the floating registers were read 206system.cpu0.num_fp_register_writes 444676 # number of times the floating registers were written 207system.cpu0.num_cc_register_reads 132153354 # number of times the CC registers were read 208system.cpu0.num_cc_register_writes 131825344 # number of times the CC registers were written 209system.cpu0.num_mem_refs 176058068 # number of memory refs 210system.cpu0.num_load_insts 91428761 # Number of load instructions 211system.cpu0.num_store_insts 84629307 # Number of store instructions 212system.cpu0.num_idle_cycles 93776262262.183929 # Number of idle cycles 213system.cpu0.num_busy_cycles 577910944.816068 # Number of busy cycles 214system.cpu0.not_idle_fraction 0.006125 # Percentage of non-idle cycles 215system.cpu0.idle_fraction 0.993875 # Percentage of idle cycles 216system.cpu0.Branches 109891880 # Number of branches fetched 217system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 218system.cpu0.op_class::IntAlu 400497126 69.30% 69.30% # Class of executed instruction 219system.cpu0.op_class::IntMult 1218559 0.21% 69.51% # Class of executed instruction 220system.cpu0.op_class::IntDiv 59561 0.01% 69.52% # Class of executed instruction 221system.cpu0.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction 222system.cpu0.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction 223system.cpu0.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction 224system.cpu0.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction 225system.cpu0.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction 226system.cpu0.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction 227system.cpu0.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction 228system.cpu0.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction 229system.cpu0.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction 230system.cpu0.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction 231system.cpu0.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction 232system.cpu0.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction 233system.cpu0.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction 234system.cpu0.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction 235system.cpu0.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction 236system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction 237system.cpu0.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction 238system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.52% # Class of executed instruction 239system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction 240system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.52% # Class of executed instruction 241system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.52% # Class of executed instruction 242system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction 243system.cpu0.op_class::SimdFloatMisc 73140 0.01% 69.54% # Class of executed instruction 244system.cpu0.op_class::SimdFloatMult 0 0.00% 69.54% # Class of executed instruction 245system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.54% # Class of executed instruction 246system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.54% # Class of executed instruction 247system.cpu0.op_class::MemRead 91428761 15.82% 85.36% # Class of executed instruction 248system.cpu0.op_class::MemWrite 84629307 14.64% 100.00% # Class of executed instruction 249system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 250system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 251system.cpu0.op_class::total 577906497 # Class of executed instruction 252system.cpu0.kern.inst.arm 0 # number of arm instructions executed 253system.cpu0.kern.inst.quiesce 13193 # number of quiesce instructions executed 254system.cpu0.dcache.tags.replacements 6189405 # number of replacements 255system.cpu0.dcache.tags.tagsinuse 506.263112 # Cycle average of tags in use 256system.cpu0.dcache.tags.total_refs 169698310 # Total number of references to valid blocks. 257system.cpu0.dcache.tags.sampled_refs 6189917 # Sample count of references to valid blocks. 258system.cpu0.dcache.tags.avg_refs 27.415280 # Average number of references to valid blocks. 259system.cpu0.dcache.tags.warmup_cycle 35630500 # Cycle when the warmup percentage was hit. 260system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.263112 # Average occupied blocks per requestor 261system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988795 # Average percentage of cache occupancy 262system.cpu0.dcache.tags.occ_percent::total 0.988795 # Average percentage of cache occupancy 263system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 264system.cpu0.dcache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id 265system.cpu0.dcache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id 266system.cpu0.dcache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id 267system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 268system.cpu0.dcache.tags.tag_accesses 358274198 # Number of tag accesses 269system.cpu0.dcache.tags.data_accesses 358274198 # Number of data accesses 270system.cpu0.dcache.ReadReq_hits::cpu0.data 84971856 # number of ReadReq hits 271system.cpu0.dcache.ReadReq_hits::total 84971856 # number of ReadReq hits 272system.cpu0.dcache.WriteReq_hits::cpu0.data 79868150 # number of WriteReq hits 273system.cpu0.dcache.WriteReq_hits::total 79868150 # number of WriteReq hits 274system.cpu0.dcache.SoftPFReq_hits::cpu0.data 214674 # number of SoftPFReq hits 275system.cpu0.dcache.SoftPFReq_hits::total 214674 # number of SoftPFReq hits 276system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 260533 # number of WriteInvalidateReq hits 277system.cpu0.dcache.WriteInvalidateReq_hits::total 260533 # number of WriteInvalidateReq hits 278system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2068908 # number of LoadLockedReq hits 279system.cpu0.dcache.LoadLockedReq_hits::total 2068908 # number of LoadLockedReq hits 280system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2028668 # number of StoreCondReq hits 281system.cpu0.dcache.StoreCondReq_hits::total 2028668 # number of StoreCondReq hits 282system.cpu0.dcache.demand_hits::cpu0.data 164840006 # number of demand (read+write) hits 283system.cpu0.dcache.demand_hits::total 164840006 # number of demand (read+write) hits 284system.cpu0.dcache.overall_hits::cpu0.data 165054680 # number of overall hits 285system.cpu0.dcache.overall_hits::total 165054680 # number of overall hits 286system.cpu0.dcache.ReadReq_misses::cpu0.data 3260277 # number of ReadReq misses 287system.cpu0.dcache.ReadReq_misses::total 3260277 # number of ReadReq misses 288system.cpu0.dcache.WriteReq_misses::cpu0.data 1458399 # number of WriteReq misses 289system.cpu0.dcache.WriteReq_misses::total 1458399 # number of WriteReq misses 290system.cpu0.dcache.SoftPFReq_misses::cpu0.data 767112 # number of SoftPFReq misses 291system.cpu0.dcache.SoftPFReq_misses::total 767112 # number of SoftPFReq misses 292system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 819206 # number of WriteInvalidateReq misses 293system.cpu0.dcache.WriteInvalidateReq_misses::total 819206 # number of WriteInvalidateReq misses 294system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 116959 # number of LoadLockedReq misses 295system.cpu0.dcache.LoadLockedReq_misses::total 116959 # number of LoadLockedReq misses 296system.cpu0.dcache.StoreCondReq_misses::cpu0.data 156094 # number of StoreCondReq misses 297system.cpu0.dcache.StoreCondReq_misses::total 156094 # number of StoreCondReq misses 298system.cpu0.dcache.demand_misses::cpu0.data 4718676 # number of demand (read+write) misses 299system.cpu0.dcache.demand_misses::total 4718676 # number of demand (read+write) misses 300system.cpu0.dcache.overall_misses::cpu0.data 5485788 # number of overall misses 301system.cpu0.dcache.overall_misses::total 5485788 # number of overall misses 302system.cpu0.dcache.ReadReq_accesses::cpu0.data 88232133 # number of ReadReq accesses(hits+misses) 303system.cpu0.dcache.ReadReq_accesses::total 88232133 # number of ReadReq accesses(hits+misses) 304system.cpu0.dcache.WriteReq_accesses::cpu0.data 81326549 # number of WriteReq accesses(hits+misses) 305system.cpu0.dcache.WriteReq_accesses::total 81326549 # number of WriteReq accesses(hits+misses) 306system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 981786 # number of SoftPFReq accesses(hits+misses) 307system.cpu0.dcache.SoftPFReq_accesses::total 981786 # number of SoftPFReq accesses(hits+misses) 308system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1079739 # number of WriteInvalidateReq accesses(hits+misses) 309system.cpu0.dcache.WriteInvalidateReq_accesses::total 1079739 # number of WriteInvalidateReq accesses(hits+misses) 310system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2185867 # number of LoadLockedReq accesses(hits+misses) 311system.cpu0.dcache.LoadLockedReq_accesses::total 2185867 # number of LoadLockedReq accesses(hits+misses) 312system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2184762 # number of StoreCondReq accesses(hits+misses) 313system.cpu0.dcache.StoreCondReq_accesses::total 2184762 # number of StoreCondReq accesses(hits+misses) 314system.cpu0.dcache.demand_accesses::cpu0.data 169558682 # number of demand (read+write) accesses 315system.cpu0.dcache.demand_accesses::total 169558682 # number of demand (read+write) accesses 316system.cpu0.dcache.overall_accesses::cpu0.data 170540468 # number of overall (read+write) accesses 317system.cpu0.dcache.overall_accesses::total 170540468 # number of overall (read+write) accesses 318system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036951 # miss rate for ReadReq accesses 319system.cpu0.dcache.ReadReq_miss_rate::total 0.036951 # miss rate for ReadReq accesses 320system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017933 # miss rate for WriteReq accesses 321system.cpu0.dcache.WriteReq_miss_rate::total 0.017933 # miss rate for WriteReq accesses 322system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781343 # miss rate for SoftPFReq accesses 323system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781343 # miss rate for SoftPFReq accesses 324system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.758707 # miss rate for WriteInvalidateReq accesses 325system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.758707 # miss rate for WriteInvalidateReq accesses 326system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053507 # miss rate for LoadLockedReq accesses 327system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053507 # miss rate for LoadLockedReq accesses 328system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.071447 # miss rate for StoreCondReq accesses 329system.cpu0.dcache.StoreCondReq_miss_rate::total 0.071447 # miss rate for StoreCondReq accesses 330system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027829 # miss rate for demand accesses 331system.cpu0.dcache.demand_miss_rate::total 0.027829 # miss rate for demand accesses 332system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032167 # miss rate for overall accesses 333system.cpu0.dcache.overall_miss_rate::total 0.032167 # miss rate for overall accesses 334system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 335system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 336system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 337system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 338system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 339system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 340system.cpu0.dcache.fast_writes 0 # number of fast writes performed 341system.cpu0.dcache.cache_copies 0 # number of cache copies performed 342system.cpu0.dcache.writebacks::writebacks 4407988 # number of writebacks 343system.cpu0.dcache.writebacks::total 4407988 # number of writebacks 344system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 345system.cpu0.icache.tags.replacements 5467768 # number of replacements 346system.cpu0.icache.tags.tagsinuse 511.988996 # Cycle average of tags in use 347system.cpu0.icache.tags.total_refs 485959047 # Total number of references to valid blocks. 348system.cpu0.icache.tags.sampled_refs 5468280 # Sample count of references to valid blocks. 349system.cpu0.icache.tags.avg_refs 88.868721 # Average number of references to valid blocks. 350system.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit. 351system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.988996 # Average occupied blocks per requestor 352system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy 353system.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy 354system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 355system.cpu0.icache.tags.age_task_id_blocks_1024::0 202 # Occupied blocks per task id 356system.cpu0.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id 357system.cpu0.icache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id 358system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 359system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 360system.cpu0.icache.tags.tag_accesses 988322949 # Number of tag accesses 361system.cpu0.icache.tags.data_accesses 988322949 # Number of data accesses 362system.cpu0.icache.ReadReq_hits::cpu0.inst 485959047 # number of ReadReq hits 363system.cpu0.icache.ReadReq_hits::total 485959047 # number of ReadReq hits 364system.cpu0.icache.demand_hits::cpu0.inst 485959047 # number of demand (read+write) hits 365system.cpu0.icache.demand_hits::total 485959047 # number of demand (read+write) hits 366system.cpu0.icache.overall_hits::cpu0.inst 485959047 # number of overall hits 367system.cpu0.icache.overall_hits::total 485959047 # number of overall hits 368system.cpu0.icache.ReadReq_misses::cpu0.inst 5468285 # number of ReadReq misses 369system.cpu0.icache.ReadReq_misses::total 5468285 # number of ReadReq misses 370system.cpu0.icache.demand_misses::cpu0.inst 5468285 # number of demand (read+write) misses 371system.cpu0.icache.demand_misses::total 5468285 # number of demand (read+write) misses 372system.cpu0.icache.overall_misses::cpu0.inst 5468285 # number of overall misses 373system.cpu0.icache.overall_misses::total 5468285 # number of overall misses 374system.cpu0.icache.ReadReq_accesses::cpu0.inst 491427332 # number of ReadReq accesses(hits+misses) 375system.cpu0.icache.ReadReq_accesses::total 491427332 # number of ReadReq accesses(hits+misses) 376system.cpu0.icache.demand_accesses::cpu0.inst 491427332 # number of demand (read+write) accesses 377system.cpu0.icache.demand_accesses::total 491427332 # number of demand (read+write) accesses 378system.cpu0.icache.overall_accesses::cpu0.inst 491427332 # number of overall (read+write) accesses 379system.cpu0.icache.overall_accesses::total 491427332 # number of overall (read+write) accesses 380system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011127 # miss rate for ReadReq accesses 381system.cpu0.icache.ReadReq_miss_rate::total 0.011127 # miss rate for ReadReq accesses 382system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011127 # miss rate for demand accesses 383system.cpu0.icache.demand_miss_rate::total 0.011127 # miss rate for demand accesses 384system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011127 # miss rate for overall accesses 385system.cpu0.icache.overall_miss_rate::total 0.011127 # miss rate for overall accesses 386system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 387system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 388system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 389system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 390system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 391system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 392system.cpu0.icache.fast_writes 0 # number of fast writes performed 393system.cpu0.icache.cache_copies 0 # number of cache copies performed 394system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 395system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified 396system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 397system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 398system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 399system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 400system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 401system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued 402system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 403system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 404system.cpu0.l2cache.tags.replacements 2648971 # number of replacements 405system.cpu0.l2cache.tags.tagsinuse 16219.904236 # Cycle average of tags in use 406system.cpu0.l2cache.tags.total_refs 11415809 # Total number of references to valid blocks. 407system.cpu0.l2cache.tags.sampled_refs 2665005 # Sample count of references to valid blocks. 408system.cpu0.l2cache.tags.avg_refs 4.283598 # Average number of references to valid blocks. 409system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. 410system.cpu0.l2cache.tags.occ_blocks::writebacks 5428.449185 # Average occupied blocks per requestor 411system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 50.127041 # Average occupied blocks per requestor 412system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 51.911966 # Average occupied blocks per requestor 413system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4608.843039 # Average occupied blocks per requestor 414system.cpu0.l2cache.tags.occ_blocks::cpu0.data 6080.573004 # Average occupied blocks per requestor 415system.cpu0.l2cache.tags.occ_percent::writebacks 0.331326 # Average percentage of cache occupancy 416system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003060 # Average percentage of cache occupancy 417system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003168 # Average percentage of cache occupancy 418system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.281301 # Average percentage of cache occupancy 419system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.371129 # Average percentage of cache occupancy 420system.cpu0.l2cache.tags.occ_percent::total 0.989984 # Average percentage of cache occupancy 421system.cpu0.l2cache.tags.occ_task_id_blocks::1023 65 # Occupied blocks per task id 422system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15969 # Occupied blocks per task id 423system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 424system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 50 # Occupied blocks per task id 425system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id 426system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id 427system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id 428system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1130 # Occupied blocks per task id 429system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4626 # Occupied blocks per task id 430system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5485 # Occupied blocks per task id 431system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4547 # Occupied blocks per task id 432system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003967 # Percentage of cache occupancy per task id 433system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.974670 # Percentage of cache occupancy per task id 434system.cpu0.l2cache.tags.tag_accesses 274915962 # Number of tag accesses 435system.cpu0.l2cache.tags.data_accesses 274915962 # Number of data accesses 436system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 266204 # number of ReadReq hits 437system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 139155 # number of ReadReq hits 438system.cpu0.l2cache.ReadReq_hits::cpu0.inst 4917807 # number of ReadReq hits 439system.cpu0.l2cache.ReadReq_hits::cpu0.data 2910870 # number of ReadReq hits 440system.cpu0.l2cache.ReadReq_hits::total 8234036 # number of ReadReq hits 441system.cpu0.l2cache.Writeback_hits::writebacks 4407988 # number of Writeback hits 442system.cpu0.l2cache.Writeback_hits::total 4407988 # number of Writeback hits 443system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 219663 # number of WriteInvalidateReq hits 444system.cpu0.l2cache.WriteInvalidateReq_hits::total 219663 # number of WriteInvalidateReq hits 445system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 3562 # number of UpgradeReq hits 446system.cpu0.l2cache.UpgradeReq_hits::total 3562 # number of UpgradeReq hits 447system.cpu0.l2cache.ReadExReq_hits::cpu0.data 630387 # number of ReadExReq hits 448system.cpu0.l2cache.ReadExReq_hits::total 630387 # number of ReadExReq hits 449system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 266204 # number of demand (read+write) hits 450system.cpu0.l2cache.demand_hits::cpu0.itb.walker 139155 # number of demand (read+write) hits 451system.cpu0.l2cache.demand_hits::cpu0.inst 4917807 # number of demand (read+write) hits 452system.cpu0.l2cache.demand_hits::cpu0.data 3541257 # number of demand (read+write) hits 453system.cpu0.l2cache.demand_hits::total 8864423 # number of demand (read+write) hits 454system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 266204 # number of overall hits 455system.cpu0.l2cache.overall_hits::cpu0.itb.walker 139155 # number of overall hits 456system.cpu0.l2cache.overall_hits::cpu0.inst 4917807 # number of overall hits 457system.cpu0.l2cache.overall_hits::cpu0.data 3541257 # number of overall hits 458system.cpu0.l2cache.overall_hits::total 8864423 # number of overall hits 459system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10959 # number of ReadReq misses 460system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8288 # number of ReadReq misses 461system.cpu0.l2cache.ReadReq_misses::cpu0.inst 550478 # number of ReadReq misses 462system.cpu0.l2cache.ReadReq_misses::cpu0.data 1233478 # number of ReadReq misses 463system.cpu0.l2cache.ReadReq_misses::total 1803203 # number of ReadReq misses 464system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 599179 # number of WriteInvalidateReq misses 465system.cpu0.l2cache.WriteInvalidateReq_misses::total 599179 # number of WriteInvalidateReq misses 466system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 125865 # number of UpgradeReq misses 467system.cpu0.l2cache.UpgradeReq_misses::total 125865 # number of UpgradeReq misses 468system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 156094 # number of SCUpgradeReq misses 469system.cpu0.l2cache.SCUpgradeReq_misses::total 156094 # number of SCUpgradeReq misses 470system.cpu0.l2cache.ReadExReq_misses::cpu0.data 698949 # number of ReadExReq misses 471system.cpu0.l2cache.ReadExReq_misses::total 698949 # number of ReadExReq misses 472system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10959 # number of demand (read+write) misses 473system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8288 # number of demand (read+write) misses 474system.cpu0.l2cache.demand_misses::cpu0.inst 550478 # number of demand (read+write) misses 475system.cpu0.l2cache.demand_misses::cpu0.data 1932427 # number of demand (read+write) misses 476system.cpu0.l2cache.demand_misses::total 2502152 # number of demand (read+write) misses 477system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10959 # number of overall misses 478system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8288 # number of overall misses 479system.cpu0.l2cache.overall_misses::cpu0.inst 550478 # number of overall misses 480system.cpu0.l2cache.overall_misses::cpu0.data 1932427 # number of overall misses 481system.cpu0.l2cache.overall_misses::total 2502152 # number of overall misses 482system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 277163 # number of ReadReq accesses(hits+misses) 483system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 147443 # number of ReadReq accesses(hits+misses) 484system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 5468285 # number of ReadReq accesses(hits+misses) 485system.cpu0.l2cache.ReadReq_accesses::cpu0.data 4144348 # number of ReadReq accesses(hits+misses) 486system.cpu0.l2cache.ReadReq_accesses::total 10037239 # number of ReadReq accesses(hits+misses) 487system.cpu0.l2cache.Writeback_accesses::writebacks 4407988 # number of Writeback accesses(hits+misses) 488system.cpu0.l2cache.Writeback_accesses::total 4407988 # number of Writeback accesses(hits+misses) 489system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 818842 # number of WriteInvalidateReq accesses(hits+misses) 490system.cpu0.l2cache.WriteInvalidateReq_accesses::total 818842 # number of WriteInvalidateReq accesses(hits+misses) 491system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 129427 # number of UpgradeReq accesses(hits+misses) 492system.cpu0.l2cache.UpgradeReq_accesses::total 129427 # number of UpgradeReq accesses(hits+misses) 493system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 156094 # number of SCUpgradeReq accesses(hits+misses) 494system.cpu0.l2cache.SCUpgradeReq_accesses::total 156094 # number of SCUpgradeReq accesses(hits+misses) 495system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1329336 # number of ReadExReq accesses(hits+misses) 496system.cpu0.l2cache.ReadExReq_accesses::total 1329336 # number of ReadExReq accesses(hits+misses) 497system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 277163 # number of demand (read+write) accesses 498system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 147443 # number of demand (read+write) accesses 499system.cpu0.l2cache.demand_accesses::cpu0.inst 5468285 # number of demand (read+write) accesses 500system.cpu0.l2cache.demand_accesses::cpu0.data 5473684 # number of demand (read+write) accesses 501system.cpu0.l2cache.demand_accesses::total 11366575 # number of demand (read+write) accesses 502system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 277163 # number of overall (read+write) accesses 503system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 147443 # number of overall (read+write) accesses 504system.cpu0.l2cache.overall_accesses::cpu0.inst 5468285 # number of overall (read+write) accesses 505system.cpu0.l2cache.overall_accesses::cpu0.data 5473684 # number of overall (read+write) accesses 506system.cpu0.l2cache.overall_accesses::total 11366575 # number of overall (read+write) accesses 507system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.039540 # miss rate for ReadReq accesses 508system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.056212 # miss rate for ReadReq accesses 509system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.100667 # miss rate for ReadReq accesses 510system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.297629 # miss rate for ReadReq accesses 511system.cpu0.l2cache.ReadReq_miss_rate::total 0.179651 # miss rate for ReadReq accesses 512system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.731739 # miss rate for WriteInvalidateReq accesses 513system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.731739 # miss rate for WriteInvalidateReq accesses 514system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.972479 # miss rate for UpgradeReq accesses 515system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.972479 # miss rate for UpgradeReq accesses 516system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 517system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 518system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.525788 # miss rate for ReadExReq accesses 519system.cpu0.l2cache.ReadExReq_miss_rate::total 0.525788 # miss rate for ReadExReq accesses 520system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.039540 # miss rate for demand accesses 521system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.056212 # miss rate for demand accesses 522system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.100667 # miss rate for demand accesses 523system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.353040 # miss rate for demand accesses 524system.cpu0.l2cache.demand_miss_rate::total 0.220132 # miss rate for demand accesses 525system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.039540 # miss rate for overall accesses 526system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.056212 # miss rate for overall accesses 527system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.100667 # miss rate for overall accesses 528system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.353040 # miss rate for overall accesses 529system.cpu0.l2cache.overall_miss_rate::total 0.220132 # miss rate for overall accesses 530system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 531system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 532system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 533system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 534system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 535system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 536system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 537system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 538system.cpu0.l2cache.writebacks::writebacks 1542533 # number of writebacks 539system.cpu0.l2cache.writebacks::total 1542533 # number of writebacks 540system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 541system.cpu0.toL2Bus.trans_dist::ReadReq 10228504 # Transaction distribution 542system.cpu0.toL2Bus.trans_dist::ReadResp 10228504 # Transaction distribution 543system.cpu0.toL2Bus.trans_dist::WriteReq 32523 # Transaction distribution 544system.cpu0.toL2Bus.trans_dist::WriteResp 32523 # Transaction distribution 545system.cpu0.toL2Bus.trans_dist::Writeback 4407988 # Transaction distribution 546system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 818842 # Transaction distribution 547system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 818842 # Transaction distribution 548system.cpu0.toL2Bus.trans_dist::UpgradeReq 129427 # Transaction distribution 549system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 156094 # Transaction distribution 550system.cpu0.toL2Bus.trans_dist::UpgradeResp 285521 # Transaction distribution 551system.cpu0.toL2Bus.trans_dist::ReadExReq 1329336 # Transaction distribution 552system.cpu0.toL2Bus.trans_dist::ReadExResp 1329336 # Transaction distribution 553system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 11022820 # Packet count per connected master and slave (bytes) 554system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17694214 # Packet count per connected master and slave (bytes) 555system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 359792 # Packet count per connected master and slave (bytes) 556system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 720614 # Packet count per connected master and slave (bytes) 557system.cpu0.toL2Bus.pkt_count::total 29797440 # Packet count per connected master and slave (bytes) 558system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 350142740 # Cumulative packet size per connected master and slave (bytes) 559system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 685026670 # Cumulative packet size per connected master and slave (bytes) 560system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1439168 # Cumulative packet size per connected master and slave (bytes) 561system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2882456 # Cumulative packet size per connected master and slave (bytes) 562system.cpu0.toL2Bus.pkt_size::total 1039491034 # Cumulative packet size per connected master and slave (bytes) 563system.cpu0.toL2Bus.snoops 3383860 # Total snoops (count) 564system.cpu0.toL2Bus.snoop_fanout::samples 20196192 # Request fanout histogram 565system.cpu0.toL2Bus.snoop_fanout::mean 5.158528 # Request fanout histogram 566system.cpu0.toL2Bus.snoop_fanout::stdev 0.365236 # Request fanout histogram 567system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 568system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 569system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 570system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 571system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 572system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 573system.cpu0.toL2Bus.snoop_fanout::5 16994523 84.15% 84.15% # Request fanout histogram 574system.cpu0.toL2Bus.snoop_fanout::6 3201669 15.85% 100.00% # Request fanout histogram 575system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 576system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 577system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 578system.cpu0.toL2Bus.snoop_fanout::total 20196192 # Request fanout histogram 579system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 580system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 581system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 582system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 583system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 584system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 585system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 586system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 587system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 588system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 589system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 590system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 591system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 592system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 593system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 594system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 595system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 596system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 597system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 598system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 599system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 600system.cpu1.dtb.inst_hits 0 # ITB inst hits 601system.cpu1.dtb.inst_misses 0 # ITB inst misses 602system.cpu1.dtb.read_hits 91720002 # DTB read hits 603system.cpu1.dtb.read_misses 112244 # DTB read misses 604system.cpu1.dtb.write_hits 82499013 # DTB write hits 605system.cpu1.dtb.write_misses 32608 # DTB write misses 606system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed 607system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 608system.cpu1.dtb.flush_tlb_mva_asid 49428 # Number of times TLB was flushed by MVA & ASID 609system.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 610system.cpu1.dtb.flush_entries 45118 # Number of entries that have been flushed from TLB 611system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 612system.cpu1.dtb.prefetch_faults 4542 # Number of TLB faults due to prefetch 613system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 614system.cpu1.dtb.perms_faults 11534 # Number of TLB faults due to permissions restrictions 615system.cpu1.dtb.read_accesses 91832246 # DTB read accesses 616system.cpu1.dtb.write_accesses 82531621 # DTB write accesses 617system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 618system.cpu1.dtb.hits 174219015 # DTB hits 619system.cpu1.dtb.misses 144852 # DTB misses 620system.cpu1.dtb.accesses 174363867 # DTB accesses 621system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 622system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 623system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 624system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 625system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 626system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 627system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 628system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 629system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 630system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 631system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 632system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 633system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 634system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 635system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 636system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 637system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 638system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 639system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 640system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 641system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 642system.cpu1.itb.inst_hits 485906850 # ITB inst hits 643system.cpu1.itb.inst_misses 61939 # ITB inst misses 644system.cpu1.itb.read_hits 0 # DTB read hits 645system.cpu1.itb.read_misses 0 # DTB read misses 646system.cpu1.itb.write_hits 0 # DTB write hits 647system.cpu1.itb.write_misses 0 # DTB write misses 648system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed 649system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 650system.cpu1.itb.flush_tlb_mva_asid 49428 # Number of times TLB was flushed by MVA & ASID 651system.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 652system.cpu1.itb.flush_entries 31863 # Number of entries that have been flushed from TLB 653system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 654system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 655system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 656system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 657system.cpu1.itb.read_accesses 0 # DTB read accesses 658system.cpu1.itb.write_accesses 0 # DTB write accesses 659system.cpu1.itb.inst_accesses 485968789 # ITB inst accesses 660system.cpu1.itb.hits 485906850 # DTB hits 661system.cpu1.itb.misses 61939 # DTB misses 662system.cpu1.itb.accesses 485968789 # DTB accesses 663system.cpu1.numCycles 94354166192 # number of cpu cycles simulated 664system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 665system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 666system.cpu1.committedInsts 485652916 # Number of instructions committed 667system.cpu1.committedOps 571511718 # Number of ops (including micro ops) committed 668system.cpu1.num_int_alu_accesses 524558211 # Number of integer alu accesses 669system.cpu1.num_fp_alu_accesses 375128 # Number of float alu accesses 670system.cpu1.num_func_calls 28666071 # number of times a function call or return occured 671system.cpu1.num_conditional_control_insts 74347572 # number of instructions that are conditional controls 672system.cpu1.num_int_insts 524558211 # number of integer instructions 673system.cpu1.num_fp_insts 375128 # number of float instructions 674system.cpu1.num_int_register_reads 774388464 # number of times the integer registers were read 675system.cpu1.num_int_register_writes 417530639 # number of times the integer registers were written 676system.cpu1.num_fp_register_reads 610571 # number of times the floating registers were read 677system.cpu1.num_fp_register_writes 303256 # number of times the floating registers were written 678system.cpu1.num_cc_register_reads 128278137 # number of times the CC registers were read 679system.cpu1.num_cc_register_writes 127991607 # number of times the CC registers were written 680system.cpu1.num_mem_refs 174340371 # number of memory refs 681system.cpu1.num_load_insts 91819242 # Number of load instructions 682system.cpu1.num_store_insts 82521129 # Number of store instructions 683system.cpu1.num_idle_cycles 93782340058.888657 # Number of idle cycles 684system.cpu1.num_busy_cycles 571826133.111340 # Number of busy cycles 685system.cpu1.not_idle_fraction 0.006060 # Percentage of non-idle cycles 686system.cpu1.idle_fraction 0.993940 # Percentage of idle cycles 687system.cpu1.Branches 108195111 # Number of branches fetched 688system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 689system.cpu1.op_class::IntAlu 396230726 69.29% 69.29% # Class of executed instruction 690system.cpu1.op_class::IntMult 1151823 0.20% 69.49% # Class of executed instruction 691system.cpu1.op_class::IntDiv 61886 0.01% 69.51% # Class of executed instruction 692system.cpu1.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction 693system.cpu1.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction 694system.cpu1.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction 695system.cpu1.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction 696system.cpu1.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction 697system.cpu1.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction 698system.cpu1.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction 699system.cpu1.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction 700system.cpu1.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction 701system.cpu1.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction 702system.cpu1.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction 703system.cpu1.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction 704system.cpu1.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction 705system.cpu1.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction 706system.cpu1.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction 707system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction 708system.cpu1.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction 709system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.51% # Class of executed instruction 710system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction 711system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.51% # Class of executed instruction 712system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.51% # Class of executed instruction 713system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction 714system.cpu1.op_class::SimdFloatMisc 36426 0.01% 69.51% # Class of executed instruction 715system.cpu1.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction 716system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction 717system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction 718system.cpu1.op_class::MemRead 91819242 16.06% 85.57% # Class of executed instruction 719system.cpu1.op_class::MemWrite 82521129 14.43% 100.00% # Class of executed instruction 720system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 721system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 722system.cpu1.op_class::total 571821232 # Class of executed instruction 723system.cpu1.kern.inst.arm 0 # number of arm instructions executed 724system.cpu1.kern.inst.quiesce 6178 # number of quiesce instructions executed 725system.cpu1.dcache.tags.replacements 6025220 # number of replacements 726system.cpu1.dcache.tags.tagsinuse 443.938244 # Cycle average of tags in use 727system.cpu1.dcache.tags.total_refs 168203685 # Total number of references to valid blocks. 728system.cpu1.dcache.tags.sampled_refs 6025731 # Sample count of references to valid blocks. 729system.cpu1.dcache.tags.avg_refs 27.914237 # Average number of references to valid blocks. 730system.cpu1.dcache.tags.warmup_cycle 8470277778500 # Cycle when the warmup percentage was hit. 731system.cpu1.dcache.tags.occ_blocks::cpu1.data 443.938244 # Average occupied blocks per requestor 732system.cpu1.dcache.tags.occ_percent::cpu1.data 0.867067 # Average percentage of cache occupancy 733system.cpu1.dcache.tags.occ_percent::total 0.867067 # Average percentage of cache occupancy 734system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 735system.cpu1.dcache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id 736system.cpu1.dcache.tags.age_task_id_blocks_1024::1 360 # Occupied blocks per task id 737system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 738system.cpu1.dcache.tags.tag_accesses 354758936 # Number of tag accesses 739system.cpu1.dcache.tags.data_accesses 354758936 # Number of data accesses 740system.cpu1.dcache.ReadReq_hits::cpu1.data 85201700 # number of ReadReq hits 741system.cpu1.dcache.ReadReq_hits::total 85201700 # number of ReadReq hits 742system.cpu1.dcache.WriteReq_hits::cpu1.data 78314445 # number of WriteReq hits 743system.cpu1.dcache.WriteReq_hits::total 78314445 # number of WriteReq hits 744system.cpu1.dcache.SoftPFReq_hits::cpu1.data 188411 # number of SoftPFReq hits 745system.cpu1.dcache.SoftPFReq_hits::total 188411 # number of SoftPFReq hits 746system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 65692 # number of WriteInvalidateReq hits 747system.cpu1.dcache.WriteInvalidateReq_hits::total 65692 # number of WriteInvalidateReq hits 748system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2073864 # number of LoadLockedReq hits 749system.cpu1.dcache.LoadLockedReq_hits::total 2073864 # number of LoadLockedReq hits 750system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2064069 # number of StoreCondReq hits 751system.cpu1.dcache.StoreCondReq_hits::total 2064069 # number of StoreCondReq hits 752system.cpu1.dcache.demand_hits::cpu1.data 163516145 # number of demand (read+write) hits 753system.cpu1.dcache.demand_hits::total 163516145 # number of demand (read+write) hits 754system.cpu1.dcache.overall_hits::cpu1.data 163704556 # number of overall hits 755system.cpu1.dcache.overall_hits::total 163704556 # number of overall hits 756system.cpu1.dcache.ReadReq_misses::cpu1.data 3403274 # number of ReadReq misses 757system.cpu1.dcache.ReadReq_misses::total 3403274 # number of ReadReq misses 758system.cpu1.dcache.WriteReq_misses::cpu1.data 1467363 # number of WriteReq misses 759system.cpu1.dcache.WriteReq_misses::total 1467363 # number of WriteReq misses 760system.cpu1.dcache.SoftPFReq_misses::cpu1.data 796168 # number of SoftPFReq misses 761system.cpu1.dcache.SoftPFReq_misses::total 796168 # number of SoftPFReq misses 762system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 438523 # number of WriteInvalidateReq misses 763system.cpu1.dcache.WriteInvalidateReq_misses::total 438523 # number of WriteInvalidateReq misses 764system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 149383 # number of LoadLockedReq misses 765system.cpu1.dcache.LoadLockedReq_misses::total 149383 # number of LoadLockedReq misses 766system.cpu1.dcache.StoreCondReq_misses::cpu1.data 157982 # number of StoreCondReq misses 767system.cpu1.dcache.StoreCondReq_misses::total 157982 # number of StoreCondReq misses 768system.cpu1.dcache.demand_misses::cpu1.data 4870637 # number of demand (read+write) misses 769system.cpu1.dcache.demand_misses::total 4870637 # number of demand (read+write) misses 770system.cpu1.dcache.overall_misses::cpu1.data 5666805 # number of overall misses 771system.cpu1.dcache.overall_misses::total 5666805 # number of overall misses 772system.cpu1.dcache.ReadReq_accesses::cpu1.data 88604974 # number of ReadReq accesses(hits+misses) 773system.cpu1.dcache.ReadReq_accesses::total 88604974 # number of ReadReq accesses(hits+misses) 774system.cpu1.dcache.WriteReq_accesses::cpu1.data 79781808 # number of WriteReq accesses(hits+misses) 775system.cpu1.dcache.WriteReq_accesses::total 79781808 # number of WriteReq accesses(hits+misses) 776system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 984579 # number of SoftPFReq accesses(hits+misses) 777system.cpu1.dcache.SoftPFReq_accesses::total 984579 # number of SoftPFReq accesses(hits+misses) 778system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 504215 # number of WriteInvalidateReq accesses(hits+misses) 779system.cpu1.dcache.WriteInvalidateReq_accesses::total 504215 # number of WriteInvalidateReq accesses(hits+misses) 780system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2223247 # number of LoadLockedReq accesses(hits+misses) 781system.cpu1.dcache.LoadLockedReq_accesses::total 2223247 # number of LoadLockedReq accesses(hits+misses) 782system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2222051 # number of StoreCondReq accesses(hits+misses) 783system.cpu1.dcache.StoreCondReq_accesses::total 2222051 # number of StoreCondReq accesses(hits+misses) 784system.cpu1.dcache.demand_accesses::cpu1.data 168386782 # number of demand (read+write) accesses 785system.cpu1.dcache.demand_accesses::total 168386782 # number of demand (read+write) accesses 786system.cpu1.dcache.overall_accesses::cpu1.data 169371361 # number of overall (read+write) accesses 787system.cpu1.dcache.overall_accesses::total 169371361 # number of overall (read+write) accesses 788system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038410 # miss rate for ReadReq accesses 789system.cpu1.dcache.ReadReq_miss_rate::total 0.038410 # miss rate for ReadReq accesses 790system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018392 # miss rate for WriteReq accesses 791system.cpu1.dcache.WriteReq_miss_rate::total 0.018392 # miss rate for WriteReq accesses 792system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808638 # miss rate for SoftPFReq accesses 793system.cpu1.dcache.SoftPFReq_miss_rate::total 0.808638 # miss rate for SoftPFReq accesses 794system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.869714 # miss rate for WriteInvalidateReq accesses 795system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.869714 # miss rate for WriteInvalidateReq accesses 796system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.067191 # miss rate for LoadLockedReq accesses 797system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.067191 # miss rate for LoadLockedReq accesses 798system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071097 # miss rate for StoreCondReq accesses 799system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071097 # miss rate for StoreCondReq accesses 800system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028925 # miss rate for demand accesses 801system.cpu1.dcache.demand_miss_rate::total 0.028925 # miss rate for demand accesses 802system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033458 # miss rate for overall accesses 803system.cpu1.dcache.overall_miss_rate::total 0.033458 # miss rate for overall accesses 804system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 805system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 806system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 807system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 808system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 809system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 810system.cpu1.dcache.fast_writes 0 # number of fast writes performed 811system.cpu1.dcache.cache_copies 0 # number of cache copies performed 812system.cpu1.dcache.writebacks::writebacks 4091318 # number of writebacks 813system.cpu1.dcache.writebacks::total 4091318 # number of writebacks 814system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 815system.cpu1.icache.tags.replacements 4818195 # number of replacements 816system.cpu1.icache.tags.tagsinuse 496.412963 # Cycle average of tags in use 817system.cpu1.icache.tags.total_refs 481143593 # Total number of references to valid blocks. 818system.cpu1.icache.tags.sampled_refs 4818707 # Sample count of references to valid blocks. 819system.cpu1.icache.tags.avg_refs 99.849107 # Average number of references to valid blocks. 820system.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit. 821system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.412963 # Average occupied blocks per requestor 822system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969557 # Average percentage of cache occupancy 823system.cpu1.icache.tags.occ_percent::total 0.969557 # Average percentage of cache occupancy 824system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 825system.cpu1.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 826system.cpu1.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id 827system.cpu1.icache.tags.age_task_id_blocks_1024::2 144 # Occupied blocks per task id 828system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 829system.cpu1.icache.tags.tag_accesses 976743307 # Number of tag accesses 830system.cpu1.icache.tags.data_accesses 976743307 # Number of data accesses 831system.cpu1.icache.ReadReq_hits::cpu1.inst 481143593 # number of ReadReq hits 832system.cpu1.icache.ReadReq_hits::total 481143593 # number of ReadReq hits 833system.cpu1.icache.demand_hits::cpu1.inst 481143593 # number of demand (read+write) hits 834system.cpu1.icache.demand_hits::total 481143593 # number of demand (read+write) hits 835system.cpu1.icache.overall_hits::cpu1.inst 481143593 # number of overall hits 836system.cpu1.icache.overall_hits::total 481143593 # number of overall hits 837system.cpu1.icache.ReadReq_misses::cpu1.inst 4818707 # number of ReadReq misses 838system.cpu1.icache.ReadReq_misses::total 4818707 # number of ReadReq misses 839system.cpu1.icache.demand_misses::cpu1.inst 4818707 # number of demand (read+write) misses 840system.cpu1.icache.demand_misses::total 4818707 # number of demand (read+write) misses 841system.cpu1.icache.overall_misses::cpu1.inst 4818707 # number of overall misses 842system.cpu1.icache.overall_misses::total 4818707 # number of overall misses 843system.cpu1.icache.ReadReq_accesses::cpu1.inst 485962300 # number of ReadReq accesses(hits+misses) 844system.cpu1.icache.ReadReq_accesses::total 485962300 # number of ReadReq accesses(hits+misses) 845system.cpu1.icache.demand_accesses::cpu1.inst 485962300 # number of demand (read+write) accesses 846system.cpu1.icache.demand_accesses::total 485962300 # number of demand (read+write) accesses 847system.cpu1.icache.overall_accesses::cpu1.inst 485962300 # number of overall (read+write) accesses 848system.cpu1.icache.overall_accesses::total 485962300 # number of overall (read+write) accesses 849system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009916 # miss rate for ReadReq accesses 850system.cpu1.icache.ReadReq_miss_rate::total 0.009916 # miss rate for ReadReq accesses 851system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009916 # miss rate for demand accesses 852system.cpu1.icache.demand_miss_rate::total 0.009916 # miss rate for demand accesses 853system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009916 # miss rate for overall accesses 854system.cpu1.icache.overall_miss_rate::total 0.009916 # miss rate for overall accesses 855system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 856system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 857system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 858system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 859system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 860system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 861system.cpu1.icache.fast_writes 0 # number of fast writes performed 862system.cpu1.icache.cache_copies 0 # number of cache copies performed 863system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 864system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified 865system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 866system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 867system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 868system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 869system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 870system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued 871system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 872system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 873system.cpu1.l2cache.tags.replacements 2333825 # number of replacements 874system.cpu1.l2cache.tags.tagsinuse 13484.024344 # Cycle average of tags in use 875system.cpu1.l2cache.tags.total_refs 11006559 # Total number of references to valid blocks. 876system.cpu1.l2cache.tags.sampled_refs 2349876 # Sample count of references to valid blocks. 877system.cpu1.l2cache.tags.avg_refs 4.683889 # Average number of references to valid blocks. 878system.cpu1.l2cache.tags.warmup_cycle 9726491548000 # Cycle when the warmup percentage was hit. 879system.cpu1.l2cache.tags.occ_blocks::writebacks 5253.379361 # Average occupied blocks per requestor 880system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 67.604678 # Average occupied blocks per requestor 881system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 75.064726 # Average occupied blocks per requestor 882system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2656.476360 # Average occupied blocks per requestor 883system.cpu1.l2cache.tags.occ_blocks::cpu1.data 5431.499219 # Average occupied blocks per requestor 884system.cpu1.l2cache.tags.occ_percent::writebacks 0.320641 # Average percentage of cache occupancy 885system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004126 # Average percentage of cache occupancy 886system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004582 # Average percentage of cache occupancy 887system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.162138 # Average percentage of cache occupancy 888system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.331512 # Average percentage of cache occupancy 889system.cpu1.l2cache.tags.occ_percent::total 0.823000 # Average percentage of cache occupancy 890system.cpu1.l2cache.tags.occ_task_id_blocks::1023 103 # Occupied blocks per task id 891system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15948 # Occupied blocks per task id 892system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id 893system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id 894system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 59 # Occupied blocks per task id 895system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id 896system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 26 # Occupied blocks per task id 897system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id 898system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1580 # Occupied blocks per task id 899system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5821 # Occupied blocks per task id 900system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4453 # Occupied blocks per task id 901system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4016 # Occupied blocks per task id 902system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006287 # Percentage of cache occupancy per task id 903system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.973389 # Percentage of cache occupancy per task id 904system.cpu1.l2cache.tags.tag_accesses 257480243 # Number of tag accesses 905system.cpu1.l2cache.tags.data_accesses 257480243 # Number of data accesses 906system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 323221 # number of ReadReq hits 907system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 141798 # number of ReadReq hits 908system.cpu1.l2cache.ReadReq_hits::cpu1.inst 4279723 # number of ReadReq hits 909system.cpu1.l2cache.ReadReq_hits::cpu1.data 3095607 # number of ReadReq hits 910system.cpu1.l2cache.ReadReq_hits::total 7840349 # number of ReadReq hits 911system.cpu1.l2cache.Writeback_hits::writebacks 4091318 # number of Writeback hits 912system.cpu1.l2cache.Writeback_hits::total 4091318 # number of Writeback hits 913system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 167179 # number of WriteInvalidateReq hits 914system.cpu1.l2cache.WriteInvalidateReq_hits::total 167179 # number of WriteInvalidateReq hits 915system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 3859 # number of UpgradeReq hits 916system.cpu1.l2cache.UpgradeReq_hits::total 3859 # number of UpgradeReq hits 917system.cpu1.l2cache.ReadExReq_hits::cpu1.data 621347 # number of ReadExReq hits 918system.cpu1.l2cache.ReadExReq_hits::total 621347 # number of ReadExReq hits 919system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 323221 # number of demand (read+write) hits 920system.cpu1.l2cache.demand_hits::cpu1.itb.walker 141798 # number of demand (read+write) hits 921system.cpu1.l2cache.demand_hits::cpu1.inst 4279723 # number of demand (read+write) hits 922system.cpu1.l2cache.demand_hits::cpu1.data 3716954 # number of demand (read+write) hits 923system.cpu1.l2cache.demand_hits::total 8461696 # number of demand (read+write) hits 924system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 323221 # number of overall hits 925system.cpu1.l2cache.overall_hits::cpu1.itb.walker 141798 # number of overall hits 926system.cpu1.l2cache.overall_hits::cpu1.inst 4279723 # number of overall hits 927system.cpu1.l2cache.overall_hits::cpu1.data 3716954 # number of overall hits 928system.cpu1.l2cache.overall_hits::total 8461696 # number of overall hits 929system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12537 # number of ReadReq misses 930system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9802 # number of ReadReq misses 931system.cpu1.l2cache.ReadReq_misses::cpu1.inst 538984 # number of ReadReq misses 932system.cpu1.l2cache.ReadReq_misses::cpu1.data 1253218 # number of ReadReq misses 933system.cpu1.l2cache.ReadReq_misses::total 1814541 # number of ReadReq misses 934system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 271117 # number of WriteInvalidateReq misses 935system.cpu1.l2cache.WriteInvalidateReq_misses::total 271117 # number of WriteInvalidateReq misses 936system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 133664 # number of UpgradeReq misses 937system.cpu1.l2cache.UpgradeReq_misses::total 133664 # number of UpgradeReq misses 938system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 157982 # number of SCUpgradeReq misses 939system.cpu1.l2cache.SCUpgradeReq_misses::total 157982 # number of SCUpgradeReq misses 940system.cpu1.l2cache.ReadExReq_misses::cpu1.data 708720 # number of ReadExReq misses 941system.cpu1.l2cache.ReadExReq_misses::total 708720 # number of ReadExReq misses 942system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12537 # number of demand (read+write) misses 943system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9802 # number of demand (read+write) misses 944system.cpu1.l2cache.demand_misses::cpu1.inst 538984 # number of demand (read+write) misses 945system.cpu1.l2cache.demand_misses::cpu1.data 1961938 # number of demand (read+write) misses 946system.cpu1.l2cache.demand_misses::total 2523261 # number of demand (read+write) misses 947system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12537 # number of overall misses 948system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9802 # number of overall misses 949system.cpu1.l2cache.overall_misses::cpu1.inst 538984 # number of overall misses 950system.cpu1.l2cache.overall_misses::cpu1.data 1961938 # number of overall misses 951system.cpu1.l2cache.overall_misses::total 2523261 # number of overall misses 952system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 335758 # number of ReadReq accesses(hits+misses) 953system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 151600 # number of ReadReq accesses(hits+misses) 954system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 4818707 # number of ReadReq accesses(hits+misses) 955system.cpu1.l2cache.ReadReq_accesses::cpu1.data 4348825 # number of ReadReq accesses(hits+misses) 956system.cpu1.l2cache.ReadReq_accesses::total 9654890 # number of ReadReq accesses(hits+misses) 957system.cpu1.l2cache.Writeback_accesses::writebacks 4091318 # number of Writeback accesses(hits+misses) 958system.cpu1.l2cache.Writeback_accesses::total 4091318 # number of Writeback accesses(hits+misses) 959system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 438296 # number of WriteInvalidateReq accesses(hits+misses) 960system.cpu1.l2cache.WriteInvalidateReq_accesses::total 438296 # number of WriteInvalidateReq accesses(hits+misses) 961system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 137523 # number of UpgradeReq accesses(hits+misses) 962system.cpu1.l2cache.UpgradeReq_accesses::total 137523 # number of UpgradeReq accesses(hits+misses) 963system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 157982 # number of SCUpgradeReq accesses(hits+misses) 964system.cpu1.l2cache.SCUpgradeReq_accesses::total 157982 # number of SCUpgradeReq accesses(hits+misses) 965system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1330067 # number of ReadExReq accesses(hits+misses) 966system.cpu1.l2cache.ReadExReq_accesses::total 1330067 # number of ReadExReq accesses(hits+misses) 967system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 335758 # number of demand (read+write) accesses 968system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 151600 # number of demand (read+write) accesses 969system.cpu1.l2cache.demand_accesses::cpu1.inst 4818707 # number of demand (read+write) accesses 970system.cpu1.l2cache.demand_accesses::cpu1.data 5678892 # number of demand (read+write) accesses 971system.cpu1.l2cache.demand_accesses::total 10984957 # number of demand (read+write) accesses 972system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 335758 # number of overall (read+write) accesses 973system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 151600 # number of overall (read+write) accesses 974system.cpu1.l2cache.overall_accesses::cpu1.inst 4818707 # number of overall (read+write) accesses 975system.cpu1.l2cache.overall_accesses::cpu1.data 5678892 # number of overall (read+write) accesses 976system.cpu1.l2cache.overall_accesses::total 10984957 # number of overall (read+write) accesses 977system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.037339 # miss rate for ReadReq accesses 978system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.064657 # miss rate for ReadReq accesses 979system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.111852 # miss rate for ReadReq accesses 980system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.288174 # miss rate for ReadReq accesses 981system.cpu1.l2cache.ReadReq_miss_rate::total 0.187940 # miss rate for ReadReq accesses 982system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.618571 # miss rate for WriteInvalidateReq accesses 983system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.618571 # miss rate for WriteInvalidateReq accesses 984system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.971939 # miss rate for UpgradeReq accesses 985system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.971939 # miss rate for UpgradeReq accesses 986system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 987system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 988system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.532845 # miss rate for ReadExReq accesses 989system.cpu1.l2cache.ReadExReq_miss_rate::total 0.532845 # miss rate for ReadExReq accesses 990system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.037339 # miss rate for demand accesses 991system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.064657 # miss rate for demand accesses 992system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.111852 # miss rate for demand accesses 993system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.345479 # miss rate for demand accesses 994system.cpu1.l2cache.demand_miss_rate::total 0.229701 # miss rate for demand accesses 995system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.037339 # miss rate for overall accesses 996system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.064657 # miss rate for overall accesses 997system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.111852 # miss rate for overall accesses 998system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.345479 # miss rate for overall accesses 999system.cpu1.l2cache.overall_miss_rate::total 0.229701 # miss rate for overall accesses 1000system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1001system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1002system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1003system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1004system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1005system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1006system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1007system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 1008system.cpu1.l2cache.writebacks::writebacks 1212706 # number of writebacks 1009system.cpu1.l2cache.writebacks::total 1212706 # number of writebacks 1010system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1011system.cpu1.toL2Bus.trans_dist::ReadReq 9779239 # Transaction distribution 1012system.cpu1.toL2Bus.trans_dist::ReadResp 9779239 # Transaction distribution 1013system.cpu1.toL2Bus.trans_dist::WriteReq 6380 # Transaction distribution 1014system.cpu1.toL2Bus.trans_dist::WriteResp 6380 # Transaction distribution 1015system.cpu1.toL2Bus.trans_dist::Writeback 4091318 # Transaction distribution 1016system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 438296 # Transaction distribution 1017system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 438296 # Transaction distribution 1018system.cpu1.toL2Bus.trans_dist::UpgradeReq 137523 # Transaction distribution 1019system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 157982 # Transaction distribution 1020system.cpu1.toL2Bus.trans_dist::UpgradeResp 295505 # Transaction distribution 1021system.cpu1.toL2Bus.trans_dist::ReadExReq 1330067 # Transaction distribution 1022system.cpu1.toL2Bus.trans_dist::ReadExResp 1330067 # Transaction distribution 1023system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9637674 # Packet count per connected master and slave (bytes) 1024system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16942172 # Packet count per connected master and slave (bytes) 1025system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 370292 # Packet count per connected master and slave (bytes) 1026system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 840154 # Packet count per connected master and slave (bytes) 1027system.cpu1.toL2Bus.pkt_count::total 27790292 # Packet count per connected master and slave (bytes) 1028system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 308397768 # Cumulative packet size per connected master and slave (bytes) 1029system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 653382681 # Cumulative packet size per connected master and slave (bytes) 1030system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1481168 # Cumulative packet size per connected master and slave (bytes) 1031system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3360616 # Cumulative packet size per connected master and slave (bytes) 1032system.cpu1.toL2Bus.pkt_size::total 966622233 # Cumulative packet size per connected master and slave (bytes) 1033system.cpu1.toL2Bus.snoops 3659793 # Total snoops (count) 1034system.cpu1.toL2Bus.snoop_fanout::samples 19426876 # Request fanout histogram 1035system.cpu1.toL2Bus.snoop_fanout::mean 5.180108 # Request fanout histogram 1036system.cpu1.toL2Bus.snoop_fanout::stdev 0.384277 # Request fanout histogram 1037system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1038system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1039system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1040system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1041system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1042system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1043system.cpu1.toL2Bus.snoop_fanout::5 15927941 81.99% 81.99% # Request fanout histogram 1044system.cpu1.toL2Bus.snoop_fanout::6 3498935 18.01% 100.00% # Request fanout histogram 1045system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1046system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1047system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1048system.cpu1.toL2Bus.snoop_fanout::total 19426876 # Request fanout histogram 1049system.iobus.trans_dist::ReadReq 40346 # Transaction distribution 1050system.iobus.trans_dist::ReadResp 40346 # Transaction distribution 1051system.iobus.trans_dist::WriteReq 136741 # Transaction distribution 1052system.iobus.trans_dist::WriteResp 30013 # Transaction distribution 1053system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution 1054system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47950 # Packet count per connected master and slave (bytes) 1055system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1056system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1057system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1058system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1059system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1060system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1061system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1062system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1063system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1064system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 1065system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 1066system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 1067system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1068system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 1069system.iobus.pkt_count_system.bridge.master::total 122884 # Packet count per connected master and slave (bytes) 1070system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231210 # Packet count per connected master and slave (bytes) 1071system.iobus.pkt_count_system.realview.ide.dma::total 231210 # Packet count per connected master and slave (bytes) 1072system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1073system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 1074system.iobus.pkt_count::total 354174 # Packet count per connected master and slave (bytes) 1075system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47970 # Cumulative packet size per connected master and slave (bytes) 1076system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1077system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1078system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1079system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1080system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1081system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1082system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1083system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1084system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1085system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 1086system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 1087system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 1088system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 1089system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1090system.iobus.pkt_size_system.bridge.master::total 155991 # Cumulative packet size per connected master and slave (bytes) 1091system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338856 # Cumulative packet size per connected master and slave (bytes) 1092system.iobus.pkt_size_system.realview.ide.dma::total 7338856 # Cumulative packet size per connected master and slave (bytes) 1093system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1094system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 1095system.iobus.pkt_size::total 7496933 # Cumulative packet size per connected master and slave (bytes) 1096system.iocache.tags.replacements 115586 # number of replacements 1097system.iocache.tags.tagsinuse 11.286927 # Cycle average of tags in use 1098system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 1099system.iocache.tags.sampled_refs 115602 # Sample count of references to valid blocks. 1100system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 1101system.iocache.tags.warmup_cycle 9107775783009 # Cycle when the warmup percentage was hit. 1102system.iocache.tags.occ_blocks::realview.ethernet 3.855232 # Average occupied blocks per requestor 1103system.iocache.tags.occ_blocks::realview.ide 7.431695 # Average occupied blocks per requestor 1104system.iocache.tags.occ_percent::realview.ethernet 0.240952 # Average percentage of cache occupancy 1105system.iocache.tags.occ_percent::realview.ide 0.464481 # Average percentage of cache occupancy 1106system.iocache.tags.occ_percent::total 0.705433 # Average percentage of cache occupancy 1107system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1108system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1109system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1110system.iocache.tags.tag_accesses 1040802 # Number of tag accesses 1111system.iocache.tags.data_accesses 1040802 # Number of data accesses 1112system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 1113system.iocache.ReadReq_misses::realview.ide 8877 # number of ReadReq misses 1114system.iocache.ReadReq_misses::total 8914 # number of ReadReq misses 1115system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1116system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1117system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses 1118system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses 1119system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 1120system.iocache.demand_misses::realview.ide 8877 # number of demand (read+write) misses 1121system.iocache.demand_misses::total 8917 # number of demand (read+write) misses 1122system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 1123system.iocache.overall_misses::realview.ide 8877 # number of overall misses 1124system.iocache.overall_misses::total 8917 # number of overall misses 1125system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 1126system.iocache.ReadReq_accesses::realview.ide 8877 # number of ReadReq accesses(hits+misses) 1127system.iocache.ReadReq_accesses::total 8914 # number of ReadReq accesses(hits+misses) 1128system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1129system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1130system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) 1131system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) 1132system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 1133system.iocache.demand_accesses::realview.ide 8877 # number of demand (read+write) accesses 1134system.iocache.demand_accesses::total 8917 # number of demand (read+write) accesses 1135system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 1136system.iocache.overall_accesses::realview.ide 8877 # number of overall (read+write) accesses 1137system.iocache.overall_accesses::total 8917 # number of overall (read+write) accesses 1138system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1139system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1140system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1141system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1142system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1143system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 1144system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 1145system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 1146system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1147system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1148system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 1149system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1150system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1151system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1152system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1153system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1154system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1155system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1156system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1157system.iocache.fast_writes 0 # number of fast writes performed 1158system.iocache.cache_copies 0 # number of cache copies performed 1159system.iocache.writebacks::writebacks 106694 # number of writebacks 1160system.iocache.writebacks::total 106694 # number of writebacks 1161system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1162system.l2c.tags.replacements 1764050 # number of replacements 1163system.l2c.tags.tagsinuse 62893.103184 # Cycle average of tags in use 1164system.l2c.tags.total_refs 3693923 # Total number of references to valid blocks. 1165system.l2c.tags.sampled_refs 1823047 # Sample count of references to valid blocks. 1166system.l2c.tags.avg_refs 2.026236 # Average number of references to valid blocks. 1167system.l2c.tags.warmup_cycle 482634500 # Cycle when the warmup percentage was hit. 1168system.l2c.tags.occ_blocks::writebacks 35252.715261 # Average occupied blocks per requestor 1169system.l2c.tags.occ_blocks::cpu0.dtb.walker 32.297168 # Average occupied blocks per requestor 1170system.l2c.tags.occ_blocks::cpu0.itb.walker 36.889266 # Average occupied blocks per requestor 1171system.l2c.tags.occ_blocks::cpu0.inst 3199.431904 # Average occupied blocks per requestor 1172system.l2c.tags.occ_blocks::cpu0.data 6870.253722 # Average occupied blocks per requestor 1173system.l2c.tags.occ_blocks::cpu1.dtb.walker 308.072507 # Average occupied blocks per requestor 1174system.l2c.tags.occ_blocks::cpu1.itb.walker 447.332489 # Average occupied blocks per requestor 1175system.l2c.tags.occ_blocks::cpu1.inst 2890.642136 # Average occupied blocks per requestor 1176system.l2c.tags.occ_blocks::cpu1.data 13855.468731 # Average occupied blocks per requestor 1177system.l2c.tags.occ_percent::writebacks 0.537914 # Average percentage of cache occupancy 1178system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000493 # Average percentage of cache occupancy 1179system.l2c.tags.occ_percent::cpu0.itb.walker 0.000563 # Average percentage of cache occupancy 1180system.l2c.tags.occ_percent::cpu0.inst 0.048819 # Average percentage of cache occupancy 1181system.l2c.tags.occ_percent::cpu0.data 0.104832 # Average percentage of cache occupancy 1182system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004701 # Average percentage of cache occupancy 1183system.l2c.tags.occ_percent::cpu1.itb.walker 0.006826 # Average percentage of cache occupancy 1184system.l2c.tags.occ_percent::cpu1.inst 0.044108 # Average percentage of cache occupancy 1185system.l2c.tags.occ_percent::cpu1.data 0.211418 # Average percentage of cache occupancy 1186system.l2c.tags.occ_percent::total 0.959673 # Average percentage of cache occupancy 1187system.l2c.tags.occ_task_id_blocks::1023 209 # Occupied blocks per task id 1188system.l2c.tags.occ_task_id_blocks::1024 58788 # Occupied blocks per task id 1189system.l2c.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id 1190system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 1191system.l2c.tags.age_task_id_blocks_1023::4 204 # Occupied blocks per task id 1192system.l2c.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id 1193system.l2c.tags.age_task_id_blocks_1024::1 542 # Occupied blocks per task id 1194system.l2c.tags.age_task_id_blocks_1024::2 3602 # Occupied blocks per task id 1195system.l2c.tags.age_task_id_blocks_1024::3 5588 # Occupied blocks per task id 1196system.l2c.tags.age_task_id_blocks_1024::4 49009 # Occupied blocks per task id 1197system.l2c.tags.occ_task_id_percent::1023 0.003189 # Percentage of cache occupancy per task id 1198system.l2c.tags.occ_task_id_percent::1024 0.897034 # Percentage of cache occupancy per task id 1199system.l2c.tags.tag_accesses 66315846 # Number of tag accesses 1200system.l2c.tags.data_accesses 66315846 # Number of data accesses 1201system.l2c.ReadReq_hits::cpu0.dtb.walker 5920 # number of ReadReq hits 1202system.l2c.ReadReq_hits::cpu0.itb.walker 4325 # number of ReadReq hits 1203system.l2c.ReadReq_hits::cpu0.inst 492739 # number of ReadReq hits 1204system.l2c.ReadReq_hits::cpu0.data 723130 # number of ReadReq hits 1205system.l2c.ReadReq_hits::cpu1.dtb.walker 5730 # number of ReadReq hits 1206system.l2c.ReadReq_hits::cpu1.itb.walker 3764 # number of ReadReq hits 1207system.l2c.ReadReq_hits::cpu1.inst 496903 # number of ReadReq hits 1208system.l2c.ReadReq_hits::cpu1.data 707011 # number of ReadReq hits 1209system.l2c.ReadReq_hits::total 2439522 # number of ReadReq hits 1210system.l2c.Writeback_hits::writebacks 2755239 # number of Writeback hits 1211system.l2c.Writeback_hits::total 2755239 # number of Writeback hits 1212system.l2c.WriteInvalidateReq_hits::cpu0.data 115462 # number of WriteInvalidateReq hits 1213system.l2c.WriteInvalidateReq_hits::cpu1.data 102925 # number of WriteInvalidateReq hits 1214system.l2c.WriteInvalidateReq_hits::total 218387 # number of WriteInvalidateReq hits 1215system.l2c.UpgradeReq_hits::cpu0.data 13978 # number of UpgradeReq hits 1216system.l2c.UpgradeReq_hits::cpu1.data 10743 # number of UpgradeReq hits 1217system.l2c.UpgradeReq_hits::total 24721 # number of UpgradeReq hits 1218system.l2c.SCUpgradeReq_hits::cpu0.data 1494 # number of SCUpgradeReq hits 1219system.l2c.SCUpgradeReq_hits::cpu1.data 1282 # number of SCUpgradeReq hits 1220system.l2c.SCUpgradeReq_hits::total 2776 # number of SCUpgradeReq hits 1221system.l2c.ReadExReq_hits::cpu0.data 196550 # number of ReadExReq hits 1222system.l2c.ReadExReq_hits::cpu1.data 177871 # number of ReadExReq hits 1223system.l2c.ReadExReq_hits::total 374421 # number of ReadExReq hits 1224system.l2c.demand_hits::cpu0.dtb.walker 5920 # number of demand (read+write) hits 1225system.l2c.demand_hits::cpu0.itb.walker 4325 # number of demand (read+write) hits 1226system.l2c.demand_hits::cpu0.inst 492739 # number of demand (read+write) hits 1227system.l2c.demand_hits::cpu0.data 919680 # number of demand (read+write) hits 1228system.l2c.demand_hits::cpu1.dtb.walker 5730 # number of demand (read+write) hits 1229system.l2c.demand_hits::cpu1.itb.walker 3764 # number of demand (read+write) hits 1230system.l2c.demand_hits::cpu1.inst 496903 # number of demand (read+write) hits 1231system.l2c.demand_hits::cpu1.data 884882 # number of demand (read+write) hits 1232system.l2c.demand_hits::total 2813943 # number of demand (read+write) hits 1233system.l2c.overall_hits::cpu0.dtb.walker 5920 # number of overall hits 1234system.l2c.overall_hits::cpu0.itb.walker 4325 # number of overall hits 1235system.l2c.overall_hits::cpu0.inst 492739 # number of overall hits 1236system.l2c.overall_hits::cpu0.data 919680 # number of overall hits 1237system.l2c.overall_hits::cpu1.dtb.walker 5730 # number of overall hits 1238system.l2c.overall_hits::cpu1.itb.walker 3764 # number of overall hits 1239system.l2c.overall_hits::cpu1.inst 496903 # number of overall hits 1240system.l2c.overall_hits::cpu1.data 884882 # number of overall hits 1241system.l2c.overall_hits::total 2813943 # number of overall hits 1242system.l2c.ReadReq_misses::cpu0.dtb.walker 2339 # number of ReadReq misses 1243system.l2c.ReadReq_misses::cpu0.itb.walker 1938 # number of ReadReq misses 1244system.l2c.ReadReq_misses::cpu0.inst 57739 # number of ReadReq misses 1245system.l2c.ReadReq_misses::cpu0.data 182657 # number of ReadReq misses 1246system.l2c.ReadReq_misses::cpu1.dtb.walker 3510 # number of ReadReq misses 1247system.l2c.ReadReq_misses::cpu1.itb.walker 3482 # number of ReadReq misses 1248system.l2c.ReadReq_misses::cpu1.inst 42081 # number of ReadReq misses 1249system.l2c.ReadReq_misses::cpu1.data 192722 # number of ReadReq misses 1250system.l2c.ReadReq_misses::total 486468 # number of ReadReq misses 1251system.l2c.WriteInvalidateReq_misses::cpu0.data 475939 # number of WriteInvalidateReq misses 1252system.l2c.WriteInvalidateReq_misses::cpu1.data 161383 # number of WriteInvalidateReq misses 1253system.l2c.WriteInvalidateReq_misses::total 637322 # number of WriteInvalidateReq misses 1254system.l2c.UpgradeReq_misses::cpu0.data 57732 # number of UpgradeReq misses 1255system.l2c.UpgradeReq_misses::cpu1.data 55051 # number of UpgradeReq misses 1256system.l2c.UpgradeReq_misses::total 112783 # number of UpgradeReq misses 1257system.l2c.SCUpgradeReq_misses::cpu0.data 7557 # number of SCUpgradeReq misses 1258system.l2c.SCUpgradeReq_misses::cpu1.data 7409 # number of SCUpgradeReq misses 1259system.l2c.SCUpgradeReq_misses::total 14966 # number of SCUpgradeReq misses 1260system.l2c.ReadExReq_misses::cpu0.data 376574 # number of ReadExReq misses 1261system.l2c.ReadExReq_misses::cpu1.data 420815 # number of ReadExReq misses 1262system.l2c.ReadExReq_misses::total 797389 # number of ReadExReq misses 1263system.l2c.demand_misses::cpu0.dtb.walker 2339 # number of demand (read+write) misses 1264system.l2c.demand_misses::cpu0.itb.walker 1938 # number of demand (read+write) misses 1265system.l2c.demand_misses::cpu0.inst 57739 # number of demand (read+write) misses 1266system.l2c.demand_misses::cpu0.data 559231 # number of demand (read+write) misses 1267system.l2c.demand_misses::cpu1.dtb.walker 3510 # number of demand (read+write) misses 1268system.l2c.demand_misses::cpu1.itb.walker 3482 # number of demand (read+write) misses 1269system.l2c.demand_misses::cpu1.inst 42081 # number of demand (read+write) misses 1270system.l2c.demand_misses::cpu1.data 613537 # number of demand (read+write) misses 1271system.l2c.demand_misses::total 1283857 # number of demand (read+write) misses 1272system.l2c.overall_misses::cpu0.dtb.walker 2339 # number of overall misses 1273system.l2c.overall_misses::cpu0.itb.walker 1938 # number of overall misses 1274system.l2c.overall_misses::cpu0.inst 57739 # number of overall misses 1275system.l2c.overall_misses::cpu0.data 559231 # number of overall misses 1276system.l2c.overall_misses::cpu1.dtb.walker 3510 # number of overall misses 1277system.l2c.overall_misses::cpu1.itb.walker 3482 # number of overall misses 1278system.l2c.overall_misses::cpu1.inst 42081 # number of overall misses 1279system.l2c.overall_misses::cpu1.data 613537 # number of overall misses 1280system.l2c.overall_misses::total 1283857 # number of overall misses 1281system.l2c.ReadReq_accesses::cpu0.dtb.walker 8259 # number of ReadReq accesses(hits+misses) 1282system.l2c.ReadReq_accesses::cpu0.itb.walker 6263 # number of ReadReq accesses(hits+misses) 1283system.l2c.ReadReq_accesses::cpu0.inst 550478 # number of ReadReq accesses(hits+misses) 1284system.l2c.ReadReq_accesses::cpu0.data 905787 # number of ReadReq accesses(hits+misses) 1285system.l2c.ReadReq_accesses::cpu1.dtb.walker 9240 # number of ReadReq accesses(hits+misses) 1286system.l2c.ReadReq_accesses::cpu1.itb.walker 7246 # number of ReadReq accesses(hits+misses) 1287system.l2c.ReadReq_accesses::cpu1.inst 538984 # number of ReadReq accesses(hits+misses) 1288system.l2c.ReadReq_accesses::cpu1.data 899733 # number of ReadReq accesses(hits+misses) 1289system.l2c.ReadReq_accesses::total 2925990 # number of ReadReq accesses(hits+misses) 1290system.l2c.Writeback_accesses::writebacks 2755239 # number of Writeback accesses(hits+misses) 1291system.l2c.Writeback_accesses::total 2755239 # number of Writeback accesses(hits+misses) 1292system.l2c.WriteInvalidateReq_accesses::cpu0.data 591401 # number of WriteInvalidateReq accesses(hits+misses) 1293system.l2c.WriteInvalidateReq_accesses::cpu1.data 264308 # number of WriteInvalidateReq accesses(hits+misses) 1294system.l2c.WriteInvalidateReq_accesses::total 855709 # number of WriteInvalidateReq accesses(hits+misses) 1295system.l2c.UpgradeReq_accesses::cpu0.data 71710 # number of UpgradeReq accesses(hits+misses) 1296system.l2c.UpgradeReq_accesses::cpu1.data 65794 # number of UpgradeReq accesses(hits+misses) 1297system.l2c.UpgradeReq_accesses::total 137504 # number of UpgradeReq accesses(hits+misses) 1298system.l2c.SCUpgradeReq_accesses::cpu0.data 9051 # number of SCUpgradeReq accesses(hits+misses) 1299system.l2c.SCUpgradeReq_accesses::cpu1.data 8691 # number of SCUpgradeReq accesses(hits+misses) 1300system.l2c.SCUpgradeReq_accesses::total 17742 # number of SCUpgradeReq accesses(hits+misses) 1301system.l2c.ReadExReq_accesses::cpu0.data 573124 # number of ReadExReq accesses(hits+misses) 1302system.l2c.ReadExReq_accesses::cpu1.data 598686 # number of ReadExReq accesses(hits+misses) 1303system.l2c.ReadExReq_accesses::total 1171810 # number of ReadExReq accesses(hits+misses) 1304system.l2c.demand_accesses::cpu0.dtb.walker 8259 # number of demand (read+write) accesses 1305system.l2c.demand_accesses::cpu0.itb.walker 6263 # number of demand (read+write) accesses 1306system.l2c.demand_accesses::cpu0.inst 550478 # number of demand (read+write) accesses 1307system.l2c.demand_accesses::cpu0.data 1478911 # number of demand (read+write) accesses 1308system.l2c.demand_accesses::cpu1.dtb.walker 9240 # number of demand (read+write) accesses 1309system.l2c.demand_accesses::cpu1.itb.walker 7246 # number of demand (read+write) accesses 1310system.l2c.demand_accesses::cpu1.inst 538984 # number of demand (read+write) accesses 1311system.l2c.demand_accesses::cpu1.data 1498419 # number of demand (read+write) accesses 1312system.l2c.demand_accesses::total 4097800 # number of demand (read+write) accesses 1313system.l2c.overall_accesses::cpu0.dtb.walker 8259 # number of overall (read+write) accesses 1314system.l2c.overall_accesses::cpu0.itb.walker 6263 # number of overall (read+write) accesses 1315system.l2c.overall_accesses::cpu0.inst 550478 # number of overall (read+write) accesses 1316system.l2c.overall_accesses::cpu0.data 1478911 # number of overall (read+write) accesses 1317system.l2c.overall_accesses::cpu1.dtb.walker 9240 # number of overall (read+write) accesses 1318system.l2c.overall_accesses::cpu1.itb.walker 7246 # number of overall (read+write) accesses 1319system.l2c.overall_accesses::cpu1.inst 538984 # number of overall (read+write) accesses 1320system.l2c.overall_accesses::cpu1.data 1498419 # number of overall (read+write) accesses 1321system.l2c.overall_accesses::total 4097800 # number of overall (read+write) accesses 1322system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.283206 # miss rate for ReadReq accesses 1323system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.309436 # miss rate for ReadReq accesses 1324system.l2c.ReadReq_miss_rate::cpu0.inst 0.104889 # miss rate for ReadReq accesses 1325system.l2c.ReadReq_miss_rate::cpu0.data 0.201656 # miss rate for ReadReq accesses 1326system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.379870 # miss rate for ReadReq accesses 1327system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.480541 # miss rate for ReadReq accesses 1328system.l2c.ReadReq_miss_rate::cpu1.inst 0.078075 # miss rate for ReadReq accesses 1329system.l2c.ReadReq_miss_rate::cpu1.data 0.214199 # miss rate for ReadReq accesses 1330system.l2c.ReadReq_miss_rate::total 0.166258 # miss rate for ReadReq accesses 1331system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.804765 # miss rate for WriteInvalidateReq accesses 1332system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.610587 # miss rate for WriteInvalidateReq accesses 1333system.l2c.WriteInvalidateReq_miss_rate::total 0.744788 # miss rate for WriteInvalidateReq accesses 1334system.l2c.UpgradeReq_miss_rate::cpu0.data 0.805076 # miss rate for UpgradeReq accesses 1335system.l2c.UpgradeReq_miss_rate::cpu1.data 0.836718 # miss rate for UpgradeReq accesses 1336system.l2c.UpgradeReq_miss_rate::total 0.820216 # miss rate for UpgradeReq accesses 1337system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.834935 # miss rate for SCUpgradeReq accesses 1338system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.852491 # miss rate for SCUpgradeReq accesses 1339system.l2c.SCUpgradeReq_miss_rate::total 0.843535 # miss rate for SCUpgradeReq accesses 1340system.l2c.ReadExReq_miss_rate::cpu0.data 0.657055 # miss rate for ReadExReq accesses 1341system.l2c.ReadExReq_miss_rate::cpu1.data 0.702898 # miss rate for ReadExReq accesses 1342system.l2c.ReadExReq_miss_rate::total 0.680476 # miss rate for ReadExReq accesses 1343system.l2c.demand_miss_rate::cpu0.dtb.walker 0.283206 # miss rate for demand accesses 1344system.l2c.demand_miss_rate::cpu0.itb.walker 0.309436 # miss rate for demand accesses 1345system.l2c.demand_miss_rate::cpu0.inst 0.104889 # miss rate for demand accesses 1346system.l2c.demand_miss_rate::cpu0.data 0.378137 # miss rate for demand accesses 1347system.l2c.demand_miss_rate::cpu1.dtb.walker 0.379870 # miss rate for demand accesses 1348system.l2c.demand_miss_rate::cpu1.itb.walker 0.480541 # miss rate for demand accesses 1349system.l2c.demand_miss_rate::cpu1.inst 0.078075 # miss rate for demand accesses 1350system.l2c.demand_miss_rate::cpu1.data 0.409456 # miss rate for demand accesses 1351system.l2c.demand_miss_rate::total 0.313304 # miss rate for demand accesses 1352system.l2c.overall_miss_rate::cpu0.dtb.walker 0.283206 # miss rate for overall accesses 1353system.l2c.overall_miss_rate::cpu0.itb.walker 0.309436 # miss rate for overall accesses 1354system.l2c.overall_miss_rate::cpu0.inst 0.104889 # miss rate for overall accesses 1355system.l2c.overall_miss_rate::cpu0.data 0.378137 # miss rate for overall accesses 1356system.l2c.overall_miss_rate::cpu1.dtb.walker 0.379870 # miss rate for overall accesses 1357system.l2c.overall_miss_rate::cpu1.itb.walker 0.480541 # miss rate for overall accesses 1358system.l2c.overall_miss_rate::cpu1.inst 0.078075 # miss rate for overall accesses 1359system.l2c.overall_miss_rate::cpu1.data 0.409456 # miss rate for overall accesses 1360system.l2c.overall_miss_rate::total 0.313304 # miss rate for overall accesses 1361system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1362system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1363system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1364system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1365system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1366system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1367system.l2c.fast_writes 0 # number of fast writes performed 1368system.l2c.cache_copies 0 # number of cache copies performed 1369system.l2c.writebacks::writebacks 1467678 # number of writebacks 1370system.l2c.writebacks::total 1467678 # number of writebacks 1371system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1372system.membus.trans_dist::ReadReq 577534 # Transaction distribution 1373system.membus.trans_dist::ReadResp 577534 # Transaction distribution 1374system.membus.trans_dist::WriteReq 38903 # Transaction distribution 1375system.membus.trans_dist::WriteResp 38903 # Transaction distribution 1376system.membus.trans_dist::Writeback 1574372 # Transaction distribution 1377system.membus.trans_dist::WriteInvalidateReq 739425 # Transaction distribution 1378system.membus.trans_dist::WriteInvalidateResp 739425 # Transaction distribution 1379system.membus.trans_dist::UpgradeReq 325897 # Transaction distribution 1380system.membus.trans_dist::SCUpgradeReq 311300 # Transaction distribution 1381system.membus.trans_dist::UpgradeResp 149445 # Transaction distribution 1382system.membus.trans_dist::ReadExReq 961374 # Transaction distribution 1383system.membus.trans_dist::ReadExResp 780321 # Transaction distribution 1384system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122884 # Packet count per connected master and slave (bytes) 1385system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 1386system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27406 # Packet count per connected master and slave (bytes) 1387system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6326067 # Packet count per connected master and slave (bytes) 1388system.membus.pkt_count_system.l2c.mem_side::total 6476449 # Packet count per connected master and slave (bytes) 1389system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337984 # Packet count per connected master and slave (bytes) 1390system.membus.pkt_count_system.iocache.mem_side::total 337984 # Packet count per connected master and slave (bytes) 1391system.membus.pkt_count::total 6814433 # Packet count per connected master and slave (bytes) 1392system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155991 # Cumulative packet size per connected master and slave (bytes) 1393system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 1394system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54812 # Cumulative packet size per connected master and slave (bytes) 1395system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 215692580 # Cumulative packet size per connected master and slave (bytes) 1396system.membus.pkt_size_system.l2c.mem_side::total 215903587 # Cumulative packet size per connected master and slave (bytes) 1397system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14229504 # Cumulative packet size per connected master and slave (bytes) 1398system.membus.pkt_size_system.iocache.mem_side::total 14229504 # Cumulative packet size per connected master and slave (bytes) 1399system.membus.pkt_size::total 230133091 # Cumulative packet size per connected master and slave (bytes) 1400system.membus.snoops 0 # Total snoops (count) 1401system.membus.snoop_fanout::samples 4407750 # Request fanout histogram 1402system.membus.snoop_fanout::mean 1 # Request fanout histogram 1403system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1404system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1405system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1406system.membus.snoop_fanout::1 4407750 100.00% 100.00% # Request fanout histogram 1407system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1408system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1409system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1410system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1411system.membus.snoop_fanout::total 4407750 # Request fanout histogram 1412system.realview.ethernet.txBytes 966 # Bytes Transmitted 1413system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 1414system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 1415system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 1416system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 1417system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1418system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1419system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1420system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1421system.realview.ethernet.totBandwidth 164 # Total Bandwidth (bits/s) 1422system.realview.ethernet.totPackets 3 # Total Packets 1423system.realview.ethernet.totBytes 966 # Total Bytes 1424system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 1425system.realview.ethernet.txBandwidth 164 # Transmit Bandwidth (bits/s) 1426system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 1427system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1428system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 1429system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1430system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1431system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 1432system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1433system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1434system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 1435system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1436system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1437system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 1438system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1439system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1440system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 1441system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1442system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1443system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 1444system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1445system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1446system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 1447system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1448system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1449system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 1450system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1451system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1452system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1453system.realview.ethernet.droppedPackets 0 # number of packets dropped 1454system.toL2Bus.trans_dist::ReadReq 3699896 # Transaction distribution 1455system.toL2Bus.trans_dist::ReadResp 3699896 # Transaction distribution 1456system.toL2Bus.trans_dist::WriteReq 38903 # Transaction distribution 1457system.toL2Bus.trans_dist::WriteResp 38903 # Transaction distribution 1458system.toL2Bus.trans_dist::Writeback 2755239 # Transaction distribution 1459system.toL2Bus.trans_dist::WriteInvalidateReq 855709 # Transaction distribution 1460system.toL2Bus.trans_dist::WriteInvalidateResp 855709 # Transaction distribution 1461system.toL2Bus.trans_dist::UpgradeReq 328922 # Transaction distribution 1462system.toL2Bus.trans_dist::SCUpgradeReq 314076 # Transaction distribution 1463system.toL2Bus.trans_dist::UpgradeResp 642998 # Transaction distribution 1464system.toL2Bus.trans_dist::ReadExReq 1352863 # Transaction distribution 1465system.toL2Bus.trans_dist::ReadExResp 1352863 # Transaction distribution 1466system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8525495 # Packet count per connected master and slave (bytes) 1467system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7410482 # Packet count per connected master and slave (bytes) 1468system.toL2Bus.pkt_count::total 15935977 # Packet count per connected master and slave (bytes) 1469system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 295216066 # Cumulative packet size per connected master and slave (bytes) 1470system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 254408545 # Cumulative packet size per connected master and slave (bytes) 1471system.toL2Bus.pkt_size::total 549624611 # Cumulative packet size per connected master and slave (bytes) 1472system.toL2Bus.snoops 117315 # Total snoops (count) 1473system.toL2Bus.snoop_fanout::samples 9340198 # Request fanout histogram 1474system.toL2Bus.snoop_fanout::mean 1.012381 # Request fanout histogram 1475system.toL2Bus.snoop_fanout::stdev 0.110581 # Request fanout histogram 1476system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1477system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1478system.toL2Bus.snoop_fanout::1 9224553 98.76% 98.76% # Request fanout histogram 1479system.toL2Bus.snoop_fanout::2 115645 1.24% 100.00% # Request fanout histogram 1480system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1481system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1482system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1483system.toL2Bus.snoop_fanout::total 9340198 # Request fanout histogram 1484 1485---------- End Simulation Statistics ---------- 1486