stats.txt revision 11754
110515SAli.Saidi@ARM.com 210515SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 311687Sandreas.hansson@arm.comsim_seconds 51.558690 # Number of seconds simulated 411754Sandreas.hansson@arm.comsim_ticks 51558689626000 # Number of ticks simulated 511754Sandreas.hansson@arm.comfinal_tick 51558689626000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 711754Sandreas.hansson@arm.comhost_inst_rate 210245 # Simulator instruction rate (inst/s) 811754Sandreas.hansson@arm.comhost_op_rate 247121 # Simulator op (including micro ops) rate (op/s) 911754Sandreas.hansson@arm.comhost_tick_rate 9737217389 # Simulator tick rate (ticks/s) 1011754Sandreas.hansson@arm.comhost_mem_usage 695392 # Number of bytes of host memory used 1111754Sandreas.hansson@arm.comhost_seconds 5295.01 # Real time elapsed on the host 1211754Sandreas.hansson@arm.comsim_insts 1113248331 # Number of instructions simulated 1311754Sandreas.hansson@arm.comsim_ops 1308509399 # Number of ops (including micro ops) simulated 1410515SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611754Sandreas.hansson@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 1711754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.dtb.walker 688064 # Number of bytes read from this memory 1811754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.itb.walker 572736 # Number of bytes read from this memory 1911754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 6466080 # Number of bytes read from this memory 2011754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 114242184 # Number of bytes read from this memory 2111754Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 427328 # Number of bytes read from this memory 2211754Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 122396392 # Number of bytes read from this memory 2311754Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 6466080 # Number of instructions bytes read from this memory 2411754Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 6466080 # Number of instructions bytes read from this memory 2511754Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 142998784 # Number of bytes written to this memory 2610585Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory 2711754Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 143019364 # Number of bytes written to this memory 2811754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.dtb.walker 10751 # Number of read requests responded to by this memory 2911754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.itb.walker 8949 # Number of read requests responded to by this memory 3011754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 116985 # Number of read requests responded to by this memory 3111754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 1785047 # Number of read requests responded to by this memory 3211754Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 6677 # Number of read requests responded to by this memory 3311754Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1928409 # Number of read requests responded to by this memory 3411754Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 2234356 # Number of write requests responded to by this memory 3510585Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory 3611754Sandreas.hansson@arm.comsystem.physmem.num_writes::total 2236929 # Number of write requests responded to by this memory 3711754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.dtb.walker 13345 # Total read bandwidth from this memory (bytes/s) 3811754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.itb.walker 11108 # Total read bandwidth from this memory (bytes/s) 3911754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 125412 # Total read bandwidth from this memory (bytes/s) 4011754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 2215770 # Total read bandwidth from this memory (bytes/s) 4111754Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 8288 # Total read bandwidth from this memory (bytes/s) 4211754Sandreas.hansson@arm.comsystem.physmem.bw_read::total 2373924 # Total read bandwidth from this memory (bytes/s) 4311754Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 125412 # Instruction read bandwidth from this memory (bytes/s) 4411754Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 125412 # Instruction read bandwidth from this memory (bytes/s) 4511754Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 2773515 # Write bandwidth from this memory (bytes/s) 4611606Sandreas.sandberg@arm.comsystem.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s) 4711754Sandreas.hansson@arm.comsystem.physmem.bw_write::total 2773914 # Write bandwidth from this memory (bytes/s) 4811754Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 2773515 # Total bandwidth to/from this memory (bytes/s) 4911754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.dtb.walker 13345 # Total bandwidth to/from this memory (bytes/s) 5011754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.itb.walker 11108 # Total bandwidth to/from this memory (bytes/s) 5111754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 125412 # Total bandwidth to/from this memory (bytes/s) 5211754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 2216169 # Total bandwidth to/from this memory (bytes/s) 5311754Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 8288 # Total bandwidth to/from this memory (bytes/s) 5411754Sandreas.hansson@arm.comsystem.physmem.bw_total::total 5147838 # Total bandwidth to/from this memory (bytes/s) 5511754Sandreas.hansson@arm.comsystem.physmem.readReqs 1928410 # Number of read requests accepted 5611754Sandreas.hansson@arm.comsystem.physmem.writeReqs 2236929 # Number of write requests accepted 5711754Sandreas.hansson@arm.comsystem.physmem.readBursts 1928410 # Number of DRAM read bursts, including those serviced by the write queue 5811754Sandreas.hansson@arm.comsystem.physmem.writeBursts 2236929 # Number of DRAM write bursts, including those merged in the write queue 5911754Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 123382976 # Total number of bytes read from DRAM 6011754Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 35200 # Total number of bytes read from write queue 6111754Sandreas.hansson@arm.comsystem.physmem.bytesWritten 143016896 # Total number of bytes written to DRAM 6211754Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 122396456 # Total read bytes from the system interface side 6311754Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 143019364 # Total written bytes from the system interface side 6411754Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 550 # Number of DRAM read bursts serviced by the write queue 6511754Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 2266 # Number of DRAM write bursts merged with an existing one 6611336Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 6711754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 114164 # Per bank write bursts 6811754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 120325 # Per bank write bursts 6911754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 121021 # Per bank write bursts 7011754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 117289 # Per bank write bursts 7111754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 115474 # Per bank write bursts 7211754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 125294 # Per bank write bursts 7311754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 117554 # Per bank write bursts 7411754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 120469 # Per bank write bursts 7511754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 115697 # Per bank write bursts 7611754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 146662 # Per bank write bursts 7711754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 119160 # Per bank write bursts 7811754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 123181 # Per bank write bursts 7911754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 118002 # Per bank write bursts 8011754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 121360 # Per bank write bursts 8111754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 114093 # Per bank write bursts 8211754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 118114 # Per bank write bursts 8311754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 133629 # Per bank write bursts 8411754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 139072 # Per bank write bursts 8511754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 140295 # Per bank write bursts 8611754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 139312 # Per bank write bursts 8711754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 138711 # Per bank write bursts 8811754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 145043 # Per bank write bursts 8911754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 137653 # Per bank write bursts 9011754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 140751 # Per bank write bursts 9111754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 137271 # Per bank write bursts 9211754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 144471 # Per bank write bursts 9311754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 139139 # Per bank write bursts 9411754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 142751 # Per bank write bursts 9511754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 139024 # Per bank write bursts 9611754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 141466 # Per bank write bursts 9711754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 137078 # Per bank write bursts 9811754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 138973 # Per bank write bursts 9910515SAli.Saidi@ARM.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 10011754Sandreas.hansson@arm.comsystem.physmem.numWrRetry 512 # Number of times write queue was full causing retry 10111754Sandreas.hansson@arm.comsystem.physmem.totGap 51558688241500 # Total gap between requests 10210515SAli.Saidi@ARM.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 10310515SAli.Saidi@ARM.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 10410515SAli.Saidi@ARM.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 10510515SAli.Saidi@ARM.comsystem.physmem.readPktSize::3 13 # Read request sizes (log2) 10610515SAli.Saidi@ARM.comsystem.physmem.readPktSize::4 21272 # Read request sizes (log2) 10710515SAli.Saidi@ARM.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 10811754Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 1907125 # Read request sizes (log2) 10910515SAli.Saidi@ARM.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 11010515SAli.Saidi@ARM.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 11110515SAli.Saidi@ARM.comsystem.physmem.writePktSize::2 1 # Write request sizes (log2) 11210515SAli.Saidi@ARM.comsystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 11310515SAli.Saidi@ARM.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 11410515SAli.Saidi@ARM.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 11511754Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 2234356 # Write request sizes (log2) 11611754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 1137157 # What read queue length does an incoming req see 11711754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 697006 # What read queue length does an incoming req see 11811754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 62243 # What read queue length does an incoming req see 11911754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 25848 # What read queue length does an incoming req see 12011754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 659 # What read queue length does an incoming req see 12111754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 474 # What read queue length does an incoming req see 12211754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 617 # What read queue length does an incoming req see 12311754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 529 # What read queue length does an incoming req see 12411754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 986 # What read queue length does an incoming req see 12511754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 614 # What read queue length does an incoming req see 12611754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 333 # What read queue length does an incoming req see 12711754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 299 # What read queue length does an incoming req see 12811754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 219 # What read queue length does an incoming req see 12911754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 172 # What read queue length does an incoming req see 13011754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 146 # What read queue length does an incoming req see 13111754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 125 # What read queue length does an incoming req see 13211754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 121 # What read queue length does an incoming req see 13311754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 115 # What read queue length does an incoming req see 13411754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 96 # What read queue length does an incoming req see 13511754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 87 # What read queue length does an incoming req see 13611754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see 13711754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see 13811353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 13911353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 14010515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 14110515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 14210515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 14310515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 14410515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 14510515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 14610515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 14710515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 14810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 14910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 15010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 15110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 15210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 15310515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 15410515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 15510515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 15610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 15710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 15810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 15910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 16010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 16110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 16210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 16311754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 28528 # What write queue length does an incoming req see 16411754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 36181 # What write queue length does an incoming req see 16511754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 84750 # What write queue length does an incoming req see 16611754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 118181 # What write queue length does an incoming req see 16711754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 127464 # What write queue length does an incoming req see 16811754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 131678 # What write queue length does an incoming req see 16911754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 133520 # What write queue length does an incoming req see 17011754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 138083 # What write queue length does an incoming req see 17111754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 140930 # What write queue length does an incoming req see 17211754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 136900 # What write queue length does an incoming req see 17311754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 140021 # What write queue length does an incoming req see 17411754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 142369 # What write queue length does an incoming req see 17511754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 134210 # What write queue length does an incoming req see 17611754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 132730 # What write queue length does an incoming req see 17711754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 134518 # What write queue length does an incoming req see 17811754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 146577 # What write queue length does an incoming req see 17911754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 128734 # What write queue length does an incoming req see 18011754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 131799 # What write queue length does an incoming req see 18111754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 5920 # What write queue length does an incoming req see 18211754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 4225 # What write queue length does an incoming req see 18311754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 3385 # What write queue length does an incoming req see 18411754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 2939 # What write queue length does an incoming req see 18511754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 2825 # What write queue length does an incoming req see 18611687Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 2565 # What write queue length does an incoming req see 18711754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 2591 # What write queue length does an incoming req see 18811754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 2354 # What write queue length does an incoming req see 18911754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 2282 # What write queue length does an incoming req see 19011754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 2240 # What write queue length does an incoming req see 19111754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 2238 # What write queue length does an incoming req see 19211754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 2279 # What write queue length does an incoming req see 19311754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 1968 # What write queue length does an incoming req see 19411754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 1976 # What write queue length does an incoming req see 19511754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 1926 # What write queue length does an incoming req see 19611754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 1784 # What write queue length does an incoming req see 19711754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 2020 # What write queue length does an incoming req see 19811754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 1898 # What write queue length does an incoming req see 19911754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 1694 # What write queue length does an incoming req see 20011754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 1774 # What write queue length does an incoming req see 20111754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 1771 # What write queue length does an incoming req see 20211754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 1642 # What write queue length does an incoming req see 20311754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 1664 # What write queue length does an incoming req see 20411754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 1959 # What write queue length does an incoming req see 20511754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 1560 # What write queue length does an incoming req see 20611754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 1314 # What write queue length does an incoming req see 20711754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 1520 # What write queue length does an incoming req see 20811754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 1794 # What write queue length does an incoming req see 20911754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 1483 # What write queue length does an incoming req see 21011754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 726 # What write queue length does an incoming req see 21111754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 1159 # What write queue length does an incoming req see 21211754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 946985 # Bytes accessed per row activation 21311754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 281.313381 # Bytes accessed per row activation 21411754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 167.848752 # Bytes accessed per row activation 21511754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 307.664857 # Bytes accessed per row activation 21611754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 373897 39.48% 39.48% # Bytes accessed per row activation 21711754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 237629 25.09% 64.58% # Bytes accessed per row activation 21811754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 90926 9.60% 74.18% # Bytes accessed per row activation 21911754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 53224 5.62% 79.80% # Bytes accessed per row activation 22011754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 39122 4.13% 83.93% # Bytes accessed per row activation 22111754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 27360 2.89% 86.82% # Bytes accessed per row activation 22211754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 21677 2.29% 89.11% # Bytes accessed per row activation 22311754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 17745 1.87% 90.98% # Bytes accessed per row activation 22411754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 85405 9.02% 100.00% # Bytes accessed per row activation 22511754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 946985 # Bytes accessed per row activation 22611754Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 117910 # Reads before turning the bus around for writes 22711754Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 16.350064 # Reads before turning the bus around for writes 22811754Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 51.964300 # Reads before turning the bus around for writes 22911754Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-511 117905 100.00% 100.00% # Reads before turning the bus around for writes 23011754Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::512-1023 2 0.00% 100.00% # Reads before turning the bus around for writes 23111680SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes 23211353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes 23311353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes 23411754Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 117910 # Reads before turning the bus around for writes 23511754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 117910 # Writes before turning the bus around for reads 23611754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 18.952074 # Writes before turning the bus around for reads 23711754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 17.420057 # Writes before turning the bus around for reads 23811754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 17.842093 # Writes before turning the bus around for reads 23911754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16-31 113720 96.45% 96.45% # Writes before turning the bus around for reads 24011754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32-47 1383 1.17% 97.62% # Writes before turning the bus around for reads 24111754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48-63 426 0.36% 97.98% # Writes before turning the bus around for reads 24211754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::64-79 819 0.69% 98.68% # Writes before turning the bus around for reads 24311754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::80-95 466 0.40% 99.07% # Writes before turning the bus around for reads 24411754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::96-111 257 0.22% 99.29% # Writes before turning the bus around for reads 24511754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::112-127 350 0.30% 99.59% # Writes before turning the bus around for reads 24611754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::128-143 159 0.13% 99.72% # Writes before turning the bus around for reads 24711754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::144-159 44 0.04% 99.76% # Writes before turning the bus around for reads 24811754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::160-175 53 0.04% 99.80% # Writes before turning the bus around for reads 24911754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::176-191 45 0.04% 99.84% # Writes before turning the bus around for reads 25011754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::192-207 26 0.02% 99.86% # Writes before turning the bus around for reads 25111754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::208-223 14 0.01% 99.87% # Writes before turning the bus around for reads 25211754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::224-239 12 0.01% 99.88% # Writes before turning the bus around for reads 25311754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::240-255 23 0.02% 99.90% # Writes before turning the bus around for reads 25411754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::256-271 25 0.02% 99.93% # Writes before turning the bus around for reads 25511754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::272-287 22 0.02% 99.94% # Writes before turning the bus around for reads 25611754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::288-303 13 0.01% 99.96% # Writes before turning the bus around for reads 25711754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::304-319 4 0.00% 99.96% # Writes before turning the bus around for reads 25811754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::320-335 1 0.00% 99.96% # Writes before turning the bus around for reads 25911754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::336-351 2 0.00% 99.96% # Writes before turning the bus around for reads 26011754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::352-367 3 0.00% 99.96% # Writes before turning the bus around for reads 26111754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::368-383 7 0.01% 99.97% # Writes before turning the bus around for reads 26211754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::384-399 7 0.01% 99.98% # Writes before turning the bus around for reads 26311754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::400-415 3 0.00% 99.98% # Writes before turning the bus around for reads 26411754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::464-479 1 0.00% 99.98% # Writes before turning the bus around for reads 26511754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::480-495 2 0.00% 99.98% # Writes before turning the bus around for reads 26611754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::496-511 4 0.00% 99.98% # Writes before turning the bus around for reads 26711754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::512-527 2 0.00% 99.99% # Writes before turning the bus around for reads 26811754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::528-543 1 0.00% 99.99% # Writes before turning the bus around for reads 26911754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::560-575 1 0.00% 99.99% # Writes before turning the bus around for reads 27011754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::576-591 2 0.00% 99.99% # Writes before turning the bus around for reads 27111754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::624-639 3 0.00% 99.99% # Writes before turning the bus around for reads 27211754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::640-655 1 0.00% 99.99% # Writes before turning the bus around for reads 27311754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::656-671 1 0.00% 99.99% # Writes before turning the bus around for reads 27411754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::736-751 1 0.00% 99.99% # Writes before turning the bus around for reads 27511754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::752-767 3 0.00% 100.00% # Writes before turning the bus around for reads 27611754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::768-783 1 0.00% 100.00% # Writes before turning the bus around for reads 27711754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::864-879 1 0.00% 100.00% # Writes before turning the bus around for reads 27811754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::880-895 2 0.00% 100.00% # Writes before turning the bus around for reads 27911754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 117910 # Writes before turning the bus around for reads 28011754Sandreas.hansson@arm.comsystem.physmem.totQLat 71195410655 # Total ticks spent queuing 28111754Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 107342766905 # Total ticks spent from burst creation until serviced by the DRAM 28211754Sandreas.hansson@arm.comsystem.physmem.totBusLat 9639295000 # Total ticks spent in databus transfers 28311754Sandreas.hansson@arm.comsystem.physmem.avgQLat 36929.76 # Average queueing delay per DRAM burst 28410515SAli.Saidi@ARM.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 28511754Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 55679.75 # Average memory access latency per DRAM burst 28611754Sandreas.hansson@arm.comsystem.physmem.avgRdBW 2.39 # Average DRAM read bandwidth in MiByte/s 28711754Sandreas.hansson@arm.comsystem.physmem.avgWrBW 2.77 # Average achieved write bandwidth in MiByte/s 28811754Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 2.37 # Average system read bandwidth in MiByte/s 28911754Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 2.77 # Average system write bandwidth in MiByte/s 29010515SAli.Saidi@ARM.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 29111606Sandreas.sandberg@arm.comsystem.physmem.busUtil 0.04 # Data bus utilization in percentage 29211606Sandreas.sandberg@arm.comsystem.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 29311606Sandreas.sandberg@arm.comsystem.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 29411754Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing 29511754Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 24.83 # Average write queue length when enqueuing 29611754Sandreas.hansson@arm.comsystem.physmem.readRowHits 1556076 # Number of row buffer hits during reads 29711754Sandreas.hansson@arm.comsystem.physmem.writeRowHits 1659436 # Number of row buffer hits during writes 29811754Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 80.72 # Row buffer hit rate for reads 29911754Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 74.26 # Row buffer hit rate for writes 30011754Sandreas.hansson@arm.comsystem.physmem.avgGap 12378029.31 # Average gap between requests 30111754Sandreas.hansson@arm.comsystem.physmem.pageHitRate 77.25 # Row buffer hit rate, read and write combined 30211754Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 3355628640 # Energy for activate commands per rank (pJ) 30311754Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 1783558920 # Energy for precharge commands per rank (pJ) 30411754Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 6794352600 # Energy for read commands per rank (pJ) 30511754Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 5817512520 # Energy for write commands per rank (pJ) 30611754Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 51361776960.000008 # Energy for refresh commands per rank (pJ) 30711754Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 51335807970 # Energy for active background per rank (pJ) 30811754Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 3128372160 # Energy for precharge background per rank (pJ) 30911754Sandreas.hansson@arm.comsystem.physmem_0.actPowerDownEnergy 100703099850 # Energy for active power-down per rank (pJ) 31011754Sandreas.hansson@arm.comsystem.physmem_0.prePowerDownEnergy 75728818080 # Energy for precharge power-down per rank (pJ) 31111754Sandreas.hansson@arm.comsystem.physmem_0.selfRefreshEnergy 12253311191655 # Energy for self refresh per rank (pJ) 31211754Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 12553360719255 # Total energy per rank (pJ) 31311754Sandreas.hansson@arm.comsystem.physmem_0.averagePower 243.477109 # Core power per rank (mW) 31411754Sandreas.hansson@arm.comsystem.physmem_0.totalIdleTime 51437874182990 # Total Idle time Per DRAM Rank 31511754Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 5229192000 # Time in different power states 31611754Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 21823720000 # Time in different power states 31711754Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::SREF 51019823371500 # Time in different power states 31811754Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 197210375905 # Time in different power states 31911754Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 93762531010 # Time in different power states 32011754Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 220840435585 # Time in different power states 32111754Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 3405851400 # Energy for activate commands per rank (pJ) 32211754Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 1810249155 # Energy for precharge commands per rank (pJ) 32311754Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 6970560660 # Energy for read commands per rank (pJ) 32411754Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 5847303060 # Energy for write commands per rank (pJ) 32511754Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 52613798640.000015 # Energy for refresh commands per rank (pJ) 32611754Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 52063882650 # Energy for active background per rank (pJ) 32711754Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 3186128160 # Energy for precharge background per rank (pJ) 32811754Sandreas.hansson@arm.comsystem.physmem_1.actPowerDownEnergy 104825729160 # Energy for active power-down per rank (pJ) 32911754Sandreas.hansson@arm.comsystem.physmem_1.prePowerDownEnergy 76862967360 # Energy for precharge power-down per rank (pJ) 33011754Sandreas.hansson@arm.comsystem.physmem_1.selfRefreshEnergy 12250174362465 # Energy for self refresh per rank (pJ) 33111754Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 12557802494490 # Total energy per rank (pJ) 33211754Sandreas.hansson@arm.comsystem.physmem_1.averagePower 243.563259 # Core power per rank (mW) 33311754Sandreas.hansson@arm.comsystem.physmem_1.totalIdleTime 51436124881809 # Total Idle time Per DRAM Rank 33411754Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 5313449750 # Time in different power states 33511754Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 22355242000 # Time in different power states 33611754Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::SREF 51006079595250 # Time in different power states 33711754Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 200164062707 # Time in different power states 33811754Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 94896006191 # Time in different power states 33911754Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 229881270102 # Time in different power states 34011754Sandreas.hansson@arm.comsystem.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 34111201Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory 34210585Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 34311201Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory 34411201Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_inst_read::cpu.inst 384 # Number of instructions bytes read from this memory 34511201Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_inst_read::total 384 # Number of instructions bytes read from this memory 34611201Sandreas.hansson@arm.comsystem.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory 34710585Sandreas.hansson@arm.comsystem.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 34811201Sandreas.hansson@arm.comsystem.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory 34911201Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) 35010585Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 35111167Sjthestness@gmail.comsystem.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) 35211201Sandreas.hansson@arm.comsystem.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) 35311201Sandreas.hansson@arm.comsystem.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) 35411201Sandreas.hansson@arm.comsystem.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) 35510585Sandreas.hansson@arm.comsystem.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 35611167Sjthestness@gmail.comsystem.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) 35711754Sandreas.hansson@arm.comsystem.realview.vram.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 35811754Sandreas.hansson@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 35911754Sandreas.hansson@arm.comsystem.bridge.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 36010585Sandreas.hansson@arm.comsystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 36110585Sandreas.hansson@arm.comsystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 36210585Sandreas.hansson@arm.comsystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 36310585Sandreas.hansson@arm.comsystem.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 36410585Sandreas.hansson@arm.comsystem.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 36510585Sandreas.hansson@arm.comsystem.cf0.dma_write_txs 1669 # Number of DMA write transactions. 36611754Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 291746368 # Number of BP lookups 36711754Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 199670043 # Number of conditional branches predicted 36811754Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 13704274 # Number of conditional branches incorrect 36911754Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 209695065 # Number of BTB lookups 37011754Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 131330914 # Number of BTB hits 37110585Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 37211754Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 62.629473 # BTB Hit Percentage 37311754Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 37689025 # Number of times the RAS was used to get a target. 37411754Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 403296 # Number of incorrect RAS predictions. 37511754Sandreas.hansson@arm.comsystem.cpu.branchPred.indirectLookups 8150983 # Number of indirect predictor lookups. 37611754Sandreas.hansson@arm.comsystem.cpu.branchPred.indirectHits 6071547 # Number of indirect target hits. 37711754Sandreas.hansson@arm.comsystem.cpu.branchPred.indirectMisses 2079436 # Number of indirect misses. 37811754Sandreas.hansson@arm.comsystem.cpu.branchPredindirectMispredicted 799941 # Number of mispredicted indirect branches. 37910585Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 38011754Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 38110628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 38210628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 38310628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 38410628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 38510628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 38610628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 38710628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 38810628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 38910585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 39010585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 39110585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 39210585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 39310585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 39410585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 39510585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 39610585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 39710585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 39810585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 39910585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 40010585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 40110585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 40210585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 40310585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 40410585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 40510585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 40610585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 40710585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 40810585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 40910585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 41011754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 41111754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walks 1432753 # Table walker walks requested 41211754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksLong 1432753 # Table walker walks initiated with long descriptors 41311754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksLongTerminationLevel::Level2 31582 # Level at which table walker walks with long descriptors terminate 41411754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksLongTerminationLevel::Level3 277767 # Level at which table walker walks with long descriptors terminate 41511754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksSquashedBefore 672727 # Table walks squashed before starting 41611754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::samples 760026 # Table walker wait (enqueue to first request) latency 41711754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::mean 2835.541153 # Table walker wait (enqueue to first request) latency 41811754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::stdev 21869.031891 # Table walker wait (enqueue to first request) latency 41911754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::0-65535 752912 99.06% 99.06% # Table walker wait (enqueue to first request) latency 42011754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::65536-131071 4648 0.61% 99.68% # Table walker wait (enqueue to first request) latency 42111754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::131072-196607 979 0.13% 99.80% # Table walker wait (enqueue to first request) latency 42211754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::196608-262143 465 0.06% 99.87% # Table walker wait (enqueue to first request) latency 42311754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::262144-327679 329 0.04% 99.91% # Table walker wait (enqueue to first request) latency 42411754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::327680-393215 37 0.00% 99.91% # Table walker wait (enqueue to first request) latency 42511754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::393216-458751 227 0.03% 99.94% # Table walker wait (enqueue to first request) latency 42611754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::458752-524287 31 0.00% 99.95% # Table walker wait (enqueue to first request) latency 42711754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::524288-589823 15 0.00% 99.95% # Table walker wait (enqueue to first request) latency 42811754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::589824-655359 373 0.05% 100.00% # Table walker wait (enqueue to first request) latency 42911754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::655360-720895 8 0.00% 100.00% # Table walker wait (enqueue to first request) latency 43011680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 43111754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::786432-851967 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 43211754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::total 760026 # Table walker wait (enqueue to first request) latency 43311754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::samples 802864 # Table walker service (enqueue to completion) latency 43411754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::mean 26261.811465 # Table walker service (enqueue to completion) latency 43511754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::gmean 21447.525498 # Table walker service (enqueue to completion) latency 43611754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::stdev 20174.954942 # Table walker service (enqueue to completion) latency 43711754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::0-65535 783898 97.64% 97.64% # Table walker service (enqueue to completion) latency 43811754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::65536-131071 15255 1.90% 99.54% # Table walker service (enqueue to completion) latency 43911754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::131072-196607 1830 0.23% 99.77% # Table walker service (enqueue to completion) latency 44011754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::196608-262143 1111 0.14% 99.90% # Table walker service (enqueue to completion) latency 44111754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::262144-327679 417 0.05% 99.96% # Table walker service (enqueue to completion) latency 44211754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::327680-393215 138 0.02% 99.97% # Table walker service (enqueue to completion) latency 44311754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::393216-458751 67 0.01% 99.98% # Table walker service (enqueue to completion) latency 44411754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::458752-524287 44 0.01% 99.99% # Table walker service (enqueue to completion) latency 44511687Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::524288-589823 12 0.00% 99.99% # Table walker service (enqueue to completion) latency 44611754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::589824-655359 88 0.01% 100.00% # Table walker service (enqueue to completion) latency 44711754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 44811754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 44911754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::total 802864 # Table walker service (enqueue to completion) latency 45011754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::samples 1071344974520 # Table walker pending requests distribution 45111754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::mean 0.740930 # Table walker pending requests distribution 45211754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::stdev 0.520683 # Table walker pending requests distribution 45311754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::0-1 1067157103520 99.61% 99.61% # Table walker pending requests distribution 45411754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::2-3 2648963000 0.25% 99.86% # Table walker pending requests distribution 45511754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::4-5 765456500 0.07% 99.93% # Table walker pending requests distribution 45611754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::6-7 299226500 0.03% 99.96% # Table walker pending requests distribution 45711754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::8-9 205947000 0.02% 99.97% # Table walker pending requests distribution 45811754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::10-11 124770000 0.01% 99.99% # Table walker pending requests distribution 45911754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::12-13 49360500 0.00% 99.99% # Table walker pending requests distribution 46011754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::14-15 91134000 0.01% 100.00% # Table walker pending requests distribution 46111754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::16-17 2962000 0.00% 100.00% # Table walker pending requests distribution 46211754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::18-19 28500 0.00% 100.00% # Table walker pending requests distribution 46311754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::20-21 23000 0.00% 100.00% # Table walker pending requests distribution 46411754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::total 1071344974520 # Table walker pending requests distribution 46511754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkPageSizes::4K 277768 89.79% 89.79% # Table walker page sizes translated 46611754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkPageSizes::2M 31582 10.21% 100.00% # Table walker page sizes translated 46711754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkPageSizes::total 309350 # Table walker page sizes translated 46811754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1432753 # Table walker requests started/completed, data/inst 46910628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 47011754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 1432753 # Table walker requests started/completed, data/inst 47111754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 309350 # Table walker requests started/completed, data/inst 47210628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 47311754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 309350 # Table walker requests started/completed, data/inst 47411754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 1742103 # Table walker requests started/completed, data/inst 47510585Sandreas.hansson@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 47610585Sandreas.hansson@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 47711754Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 218702786 # DTB read hits 47811754Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses 1008685 # DTB read misses 47911754Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 193509885 # DTB write hits 48011754Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 424068 # DTB write misses 48111606Sandreas.sandberg@arm.comsystem.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 48210585Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 48311754Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 63704 # Number of times TLB was flushed by MVA & ASID 48411680SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_asid 1209 # Number of times TLB was flushed by ASID 48511754Sandreas.hansson@arm.comsystem.cpu.dtb.flush_entries 88843 # Number of entries that have been flushed from TLB 48611754Sandreas.hansson@arm.comsystem.cpu.dtb.align_faults 110 # Number of TLB faults due to alignment restrictions 48711754Sandreas.hansson@arm.comsystem.cpu.dtb.prefetch_faults 16314 # Number of TLB faults due to prefetch 48810585Sandreas.hansson@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 48911754Sandreas.hansson@arm.comsystem.cpu.dtb.perms_faults 85947 # Number of TLB faults due to permissions restrictions 49011754Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 219711471 # DTB read accesses 49111754Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 193933953 # DTB write accesses 49210585Sandreas.hansson@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 49311754Sandreas.hansson@arm.comsystem.cpu.dtb.hits 412212671 # DTB hits 49411754Sandreas.hansson@arm.comsystem.cpu.dtb.misses 1432753 # DTB misses 49511754Sandreas.hansson@arm.comsystem.cpu.dtb.accesses 413645424 # DTB accesses 49611754Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 49710628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 49810628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 49910628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 50010628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 50110628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 50210628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 50310628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 50410628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 50510585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 50610585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 50710585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 50810585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 50910585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 51010585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 51110585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 51210585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 51310585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 51410585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 51510585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 51610585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 51710585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 51810585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 51910585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 52010585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 52110585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 52210585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 52310585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 52410585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 52510585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 52611754Sandreas.hansson@arm.comsystem.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 52711754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walks 178667 # Table walker walks requested 52811754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksLong 178667 # Table walker walks initiated with long descriptors 52911754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksLongTerminationLevel::Level2 1505 # Level at which table walker walks with long descriptors terminate 53011754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksLongTerminationLevel::Level3 129431 # Level at which table walker walks with long descriptors terminate 53111754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksSquashedBefore 20285 # Table walks squashed before starting 53211754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::samples 158382 # Table walker wait (enqueue to first request) latency 53311754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::mean 1812.216666 # Table walker wait (enqueue to first request) latency 53411754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::stdev 18363.278107 # Table walker wait (enqueue to first request) latency 53511754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::0-65535 157121 99.20% 99.20% # Table walker wait (enqueue to first request) latency 53611754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::65536-131071 1064 0.67% 99.88% # Table walker wait (enqueue to first request) latency 53711754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::131072-196607 45 0.03% 99.90% # Table walker wait (enqueue to first request) latency 53811754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::196608-262143 30 0.02% 99.92% # Table walker wait (enqueue to first request) latency 53911754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::262144-327679 12 0.01% 99.93% # Table walker wait (enqueue to first request) latency 54011754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::327680-393215 8 0.01% 99.94% # Table walker wait (enqueue to first request) latency 54111754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::393216-458751 4 0.00% 99.94% # Table walker wait (enqueue to first request) latency 54211754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::458752-524287 1 0.00% 99.94% # Table walker wait (enqueue to first request) latency 54311754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::524288-589823 38 0.02% 99.96% # Table walker wait (enqueue to first request) latency 54411754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::589824-655359 58 0.04% 100.00% # Table walker wait (enqueue to first request) latency 54511754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 54611754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::total 158382 # Table walker wait (enqueue to first request) latency 54711754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::samples 151221 # Table walker service (enqueue to completion) latency 54811754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::mean 29741.047870 # Table walker service (enqueue to completion) latency 54911754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::gmean 23638.717531 # Table walker service (enqueue to completion) latency 55011754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::stdev 30785.807578 # Table walker service (enqueue to completion) latency 55111754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::0-65535 145088 95.94% 95.94% # Table walker service (enqueue to completion) latency 55211754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::65536-131071 5051 3.34% 99.28% # Table walker service (enqueue to completion) latency 55311754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::131072-196607 405 0.27% 99.55% # Table walker service (enqueue to completion) latency 55411754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::196608-262143 372 0.25% 99.80% # Table walker service (enqueue to completion) latency 55511754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::262144-327679 84 0.06% 99.85% # Table walker service (enqueue to completion) latency 55611754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::327680-393215 62 0.04% 99.89% # Table walker service (enqueue to completion) latency 55711754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::393216-458751 13 0.01% 99.90% # Table walker service (enqueue to completion) latency 55811754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::458752-524287 11 0.01% 99.91% # Table walker service (enqueue to completion) latency 55911754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::524288-589823 6 0.00% 99.91% # Table walker service (enqueue to completion) latency 56011754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::589824-655359 89 0.06% 99.97% # Table walker service (enqueue to completion) latency 56111754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::655360-720895 6 0.00% 99.98% # Table walker service (enqueue to completion) latency 56211754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::720896-786431 31 0.02% 100.00% # Table walker service (enqueue to completion) latency 56311754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::786432-851967 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 56411754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 56511754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::total 151221 # Table walker service (enqueue to completion) latency 56611754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::samples 912431133568 # Table walker pending requests distribution 56711754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::mean 0.946195 # Table walker pending requests distribution 56811754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::stdev 0.225953 # Table walker pending requests distribution 56911754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::0 49158537652 5.39% 5.39% # Table walker pending requests distribution 57011754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::1 863207621416 94.61% 99.99% # Table walker pending requests distribution 57111754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::2 64327000 0.01% 100.00% # Table walker pending requests distribution 57211754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::3 645500 0.00% 100.00% # Table walker pending requests distribution 57311754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::4 2000 0.00% 100.00% # Table walker pending requests distribution 57411754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::total 912431133568 # Table walker pending requests distribution 57511754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkPageSizes::4K 129431 98.85% 98.85% # Table walker page sizes translated 57611754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkPageSizes::2M 1505 1.15% 100.00% # Table walker page sizes translated 57711754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkPageSizes::total 130936 # Table walker page sizes translated 57810628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 57911754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 178667 # Table walker requests started/completed, data/inst 58011754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 178667 # Table walker requests started/completed, data/inst 58110628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 58211754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 130936 # Table walker requests started/completed, data/inst 58311754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 130936 # Table walker requests started/completed, data/inst 58411754Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 309603 # Table walker requests started/completed, data/inst 58511754Sandreas.hansson@arm.comsystem.cpu.itb.inst_hits 465155459 # ITB inst hits 58611754Sandreas.hansson@arm.comsystem.cpu.itb.inst_misses 178667 # ITB inst misses 58710585Sandreas.hansson@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 58810585Sandreas.hansson@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 58910585Sandreas.hansson@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 59010585Sandreas.hansson@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 59111606Sandreas.sandberg@arm.comsystem.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 59210585Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 59311754Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_mva_asid 63704 # Number of times TLB was flushed by MVA & ASID 59411680SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_asid 1209 # Number of times TLB was flushed by ASID 59511754Sandreas.hansson@arm.comsystem.cpu.itb.flush_entries 62700 # Number of entries that have been flushed from TLB 59610585Sandreas.hansson@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 59710585Sandreas.hansson@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 59810585Sandreas.hansson@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 59911754Sandreas.hansson@arm.comsystem.cpu.itb.perms_faults 443616 # Number of TLB faults due to permissions restrictions 60010585Sandreas.hansson@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 60110585Sandreas.hansson@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 60211754Sandreas.hansson@arm.comsystem.cpu.itb.inst_accesses 465334126 # ITB inst accesses 60311754Sandreas.hansson@arm.comsystem.cpu.itb.hits 465155459 # DTB hits 60411754Sandreas.hansson@arm.comsystem.cpu.itb.misses 178667 # DTB misses 60511754Sandreas.hansson@arm.comsystem.cpu.itb.accesses 465334126 # DTB accesses 60611754Sandreas.hansson@arm.comsystem.cpu.numPwrStateTransitions 34326 # Number of power state transitions 60711754Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::samples 17163 # Distribution of time spent in the clock gated state 60811754Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::mean 2940291030.619589 # Distribution of time spent in the clock gated state 60911754Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::stdev 58535247231.170448 # Distribution of time spent in the clock gated state 61011754Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::underflows 7840 45.68% 45.68% # Distribution of time spent in the clock gated state 61111754Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::1000-5e+10 9287 54.11% 99.79% # Distribution of time spent in the clock gated state 61211687Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state 61311606Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.84% # Distribution of time spent in the clock gated state 61411606Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state 61511606Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state 61611687Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state 61711687Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state 61811687Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 61911687Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 62011680SCurtis.Dunham@arm.comsystem.cpu.pwrStateClkGateDist::9.5e+11-1e+12 1 0.01% 99.90% # Distribution of time spent in the clock gated state 62111680SCurtis.Dunham@arm.comsystem.cpu.pwrStateClkGateDist::overflows 18 0.10% 100.00% # Distribution of time spent in the clock gated state 62211570SCurtis.Dunham@arm.comsystem.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 62311687Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::max_value 1988780762168 # Distribution of time spent in the clock gated state 62411754Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::total 17163 # Distribution of time spent in the clock gated state 62511754Sandreas.hansson@arm.comsystem.cpu.pwrStateResidencyTicks::ON 1094474667476 # Cumulative time (in ticks) in various power states 62611754Sandreas.hansson@arm.comsystem.cpu.pwrStateResidencyTicks::CLK_GATED 50464214958524 # Cumulative time (in ticks) in various power states 62711754Sandreas.hansson@arm.comsystem.cpu.numCycles 2188958665 # number of cpu cycles simulated 62810585Sandreas.hansson@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 62910585Sandreas.hansson@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 63011754Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 793327228 # Number of cycles fetch is stalled on an Icache miss 63111754Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 1301291266 # Number of instructions fetch has processed 63211754Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 291746368 # Number of branches that fetch encountered 63311754Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 175091486 # Number of branches that fetch has predicted taken 63411754Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 1303318637 # Number of cycles fetch has run and was not squashing or blocked 63511754Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 29494258 # Number of cycles fetch has spent squashing 63611754Sandreas.hansson@arm.comsystem.cpu.fetch.TlbCycles 4691335 # Number of cycles fetch has spent waiting for tlb 63711754Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 27171 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 63811754Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 11697076 # Number of stall cycles due to pending traps 63911754Sandreas.hansson@arm.comsystem.cpu.fetch.PendingQuiesceStallCycles 1210879 # Number of stall cycles due to pending quiesce instructions 64011754Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 1191 # Number of stall cycles due to full MSHR 64111754Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 464693718 # Number of cache lines fetched 64211754Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 6899661 # Number of outstanding Icache misses that were squashed 64311754Sandreas.hansson@arm.comsystem.cpu.fetch.ItlbSquashes 52634 # Number of outstanding ITLB misses that were squashed 64411754Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 2129020646 # Number of instructions fetched each cycle (Total) 64511754Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 0.716284 # Number of instructions fetched each cycle (Total) 64611754Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 1.134063 # Number of instructions fetched each cycle (Total) 64710585Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 64811754Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 1402178691 65.86% 65.86% # Number of instructions fetched each cycle (Total) 64911754Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 283295913 13.31% 79.17% # Number of instructions fetched each cycle (Total) 65011754Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 88951632 4.18% 83.34% # Number of instructions fetched each cycle (Total) 65111754Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 354594410 16.66% 100.00% # Number of instructions fetched each cycle (Total) 65210585Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 65310585Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 65410585Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 65511754Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 2129020646 # Number of instructions fetched each cycle (Total) 65611754Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.133281 # Number of branch fetches per cycle 65711754Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.594480 # Number of inst fetches per cycle 65811754Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 614901243 # Number of cycles decode is idle 65911754Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 887926164 # Number of cycles decode is blocked 66011754Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 542267168 # Number of cycles decode is running 66111754Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 73189541 # Number of cycles decode is unblocking 66211754Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 10736530 # Number of cycles decode is squashing 66311754Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 41417664 # Number of times decode resolved a branch 66411754Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 4068147 # Number of times decode detected a branch misprediction 66511754Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 1415615504 # Number of instructions handled by decode 66611754Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 33076716 # Number of squashed instructions handled by decode 66711754Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 10736530 # Number of cycles rename is squashing 66811754Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 677683388 # Number of cycles rename is idle 66911754Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 94369025 # Number of cycles rename is blocking 67011754Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 569420569 # count of cycles rename stalled for serializing inst 67111754Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 556850066 # Number of cycles rename is running 67211754Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 219961068 # Number of cycles rename is unblocking 67311754Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 1391316215 # Number of instructions processed by rename 67411754Sandreas.hansson@arm.comsystem.cpu.rename.SquashedInsts 8139294 # Number of squashed instructions processed by rename 67511754Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 7433415 # Number of times rename has blocked due to ROB full 67611754Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 989914 # Number of times rename has blocked due to IQ full 67711754Sandreas.hansson@arm.comsystem.cpu.rename.LQFullEvents 1107412 # Number of times rename has blocked due to LQ full 67811754Sandreas.hansson@arm.comsystem.cpu.rename.SQFullEvents 140152556 # Number of times rename has blocked due to SQ full 67911754Sandreas.hansson@arm.comsystem.cpu.rename.FullRegisterEvents 22881 # Number of times there has been no free registers 68011754Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 1341380585 # Number of destination operands rename has renamed 68111754Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 2214711658 # Number of register rename lookups that rename has made 68211754Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 1650667847 # Number of integer rename lookups 68311754Sandreas.hansson@arm.comsystem.cpu.rename.fp_rename_lookups 1431319 # Number of floating rename lookups 68411754Sandreas.hansson@arm.comsystem.cpu.rename.CommittedMaps 1262462841 # Number of HB maps that are committed 68511754Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 78917741 # Number of HB maps that are undone due to squashing 68611754Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 44085987 # count of serializing insts renamed 68711754Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 39608884 # count of temporary serializing insts renamed 68811754Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 160777326 # count of insts added to the skid buffer 68911754Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 223759172 # Number of loads inserted to the mem dependence unit. 69011754Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 197950271 # Number of stores inserted to the mem dependence unit. 69111754Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 12848262 # Number of conflicting loads. 69211754Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingStores 11112686 # Number of conflicting stores. 69311754Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 1338031616 # Number of instructions added to the IQ (excludes non-spec) 69411754Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 44396038 # Number of non-speculative instructions added to the IQ 69511754Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 1368016868 # Number of instructions issued 69611754Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 4222413 # Number of squashed instructions issued 69711754Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 73918251 # Number of squashed instructions iterated over during squash; mainly for profiling 69811754Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 42115616 # Number of squashed operands that are examined and possibly removed from graph 69911754Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 367601 # Number of squashed non-spec instructions that were removed 70011754Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 2129020646 # Number of insts issued each cycle 70111754Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.642557 # Number of insts issued each cycle 70211754Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 0.913774 # Number of insts issued each cycle 70310585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 70411754Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 1277602195 60.01% 60.01% # Number of insts issued each cycle 70511754Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 452152764 21.24% 81.25% # Number of insts issued each cycle 70611754Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 292326493 13.73% 94.98% # Number of insts issued each cycle 70711754Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 96574735 4.54% 99.51% # Number of insts issued each cycle 70811754Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 10335382 0.49% 100.00% # Number of insts issued each cycle 70911754Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 29077 0.00% 100.00% # Number of insts issued each cycle 71010585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 71110585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 71210585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 71310585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 71410585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 71510585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 71611754Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 2129020646 # Number of insts issued each cycle 71710585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 71811754Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 73998347 33.81% 33.81% # attempts to use FU when none available 71911754Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 90252 0.04% 33.85% # attempts to use FU when none available 72011754Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 26750 0.01% 33.87% # attempts to use FU when none available 72111687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 33.87% # attempts to use FU when none available 72211687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 33.87% # attempts to use FU when none available 72311687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 33.87% # attempts to use FU when none available 72411687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 33.87% # attempts to use FU when none available 72511687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMultAcc 0 0.00% 33.87% # attempts to use FU when none available 72611687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 33.87% # attempts to use FU when none available 72711754Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMisc 451 0.00% 33.87% # attempts to use FU when none available 72811687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.87% # attempts to use FU when none available 72911687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 33.87% # attempts to use FU when none available 73011687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.87% # attempts to use FU when none available 73111687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 33.87% # attempts to use FU when none available 73211687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 33.87% # attempts to use FU when none available 73311687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 33.87% # attempts to use FU when none available 73411687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 33.87% # attempts to use FU when none available 73511687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 33.87% # attempts to use FU when none available 73611687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.87% # attempts to use FU when none available 73711687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 33.87% # attempts to use FU when none available 73811687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.87% # attempts to use FU when none available 73911687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.87% # attempts to use FU when none available 74011687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.87% # attempts to use FU when none available 74111687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.87% # attempts to use FU when none available 74211687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.87% # attempts to use FU when none available 74311687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.87% # attempts to use FU when none available 74411687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.87% # attempts to use FU when none available 74511687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.87% # attempts to use FU when none available 74611687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.87% # attempts to use FU when none available 74711687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.87% # attempts to use FU when none available 74811687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.87% # attempts to use FU when none available 74911754Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 58933248 26.93% 60.80% # attempts to use FU when none available 75011754Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 85092406 38.88% 99.68% # attempts to use FU when none available 75111754Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMemRead 64953 0.03% 99.71% # attempts to use FU when none available 75211754Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMemWrite 641116 0.29% 100.00% # attempts to use FU when none available 75310585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 75410585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 75511754Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::No_OpClass 41 0.00% 0.00% # Type of FU issued 75611754Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 945166591 69.09% 69.09% # Type of FU issued 75711754Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 2943445 0.22% 69.31% # Type of FU issued 75811754Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 129819 0.01% 69.31% # Type of FU issued 75911754Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 9 0.00% 69.31% # Type of FU issued 76011687Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 15 0.00% 69.31% # Type of FU issued 76111687Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 24 0.00% 69.31% # Type of FU issued 76211606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.31% # Type of FU issued 76311687Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 69.31% # Type of FU issued 76411606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.31% # Type of FU issued 76511754Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMisc 112220 0.01% 69.32% # Type of FU issued 76611687Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.32% # Type of FU issued 76711687Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.32% # Type of FU issued 76811687Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.32% # Type of FU issued 76911687Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.32% # Type of FU issued 77011687Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.32% # Type of FU issued 77111687Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.32% # Type of FU issued 77211687Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.32% # Type of FU issued 77311687Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.32% # Type of FU issued 77411687Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.32% # Type of FU issued 77511687Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.32% # Type of FU issued 77611687Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.32% # Type of FU issued 77711687Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.32% # Type of FU issued 77811687Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.32% # Type of FU issued 77911687Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.32% # Type of FU issued 78011687Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.32% # Type of FU issued 78111687Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.32% # Type of FU issued 78211687Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.32% # Type of FU issued 78311687Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.32% # Type of FU issued 78411606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.32% # Type of FU issued 78511606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.32% # Type of FU issued 78611606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.32% # Type of FU issued 78711754Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 223636421 16.35% 85.67% # Type of FU issued 78811754Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 195247662 14.27% 99.94% # Type of FU issued 78911754Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMemRead 119006 0.01% 99.95% # Type of FU issued 79011754Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMemWrite 661615 0.05% 100.00% # Type of FU issued 79110585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 79210585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 79311754Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 1368016868 # Type of FU issued 79411754Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.624962 # Inst issue rate 79511754Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 218847523 # FU busy when requested 79611754Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.159974 # FU busy rate (busy events/executed inst) 79711754Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 5085629992 # Number of integer instruction queue reads 79811754Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 1455613237 # Number of integer instruction queue writes 79911754Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 1345805572 # Number of integer instruction queue wakeup accesses 80011754Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_reads 2494325 # Number of floating instruction queue reads 80111754Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 915085 # Number of floating instruction queue writes 80211754Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 886623 # Number of floating instruction queue wakeup accesses 80311754Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 1585264941 # Number of integer alu accesses 80411754Sandreas.hansson@arm.comsystem.cpu.iq.fp_alu_accesses 1599409 # Number of floating point alu accesses 80511754Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 5699315 # Number of loads that had data forwarded from stores 80610585Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 80711754Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 17397321 # Number of loads squashed 80811754Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 21752 # Number of memory responses ignored because the instruction is squashed 80911754Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 184120 # Number of memory ordering violations 81011754Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 8002822 # Number of stores squashed 81110585Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 81210585Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 81311754Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 3610863 # Number of loads that were rescheduled 81411754Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 2045833 # Number of times an access to memory failed due to the cache being blocked 81510585Sandreas.hansson@arm.comsystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 81611754Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 10736530 # Number of cycles IEW is squashing 81711754Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 13380632 # Number of cycles IEW is blocking 81811754Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 5317474 # Number of cycles IEW is unblocking 81911754Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 1382714005 # Number of instructions dispatched to IQ 82010585Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 82111754Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 223759172 # Number of dispatched load instructions 82211754Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 197950271 # Number of dispatched store instructions 82311754Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 39068255 # Number of dispatched non-speculative instructions 82411754Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 183844 # Number of times the IQ has become full, causing a stall 82511754Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 4942045 # Number of times the LSQ has become full, causing a stall 82611754Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 184120 # Number of memory order violations 82711754Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 4054774 # Number of branches that were predicted taken incorrectly 82811754Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 6111734 # Number of branches that were predicted not taken incorrectly 82911754Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 10166508 # Number of branch mispredicts detected at execute 83011754Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 1354334153 # Number of executed instructions 83111754Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 218708027 # Number of load instructions executed 83211754Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 12279784 # Number of squashed instructions skipped in execute 83310585Sandreas.hansson@arm.comsystem.cpu.iew.exec_swp 0 # number of swp insts executed 83411754Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 286351 # number of nop insts executed 83511754Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 412227919 # number of memory reference insts executed 83611754Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 257147927 # Number of branches executed 83711754Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 193519892 # Number of stores executed 83811754Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.618712 # Inst execution rate 83911754Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 1347736728 # cumulative count of insts sent to commit 84011754Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 1346692195 # cumulative count of insts written-back 84111754Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 575598964 # num instructions producing a value 84211754Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 947631330 # num instructions consuming a value 84311754Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.615220 # insts written-back per cycle 84411754Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.607408 # average fanout of values written-back 84511754Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 63004798 # The number of squashed insts skipped by commit 84611754Sandreas.hansson@arm.comsystem.cpu.commit.commitNonSpecStalls 44028437 # The number of times commit has been forced to stall to communicate backwards 84711754Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 9693675 # The number of times a branch was mispredicted 84811754Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 2114795220 # Number of insts commited each cycle 84911754Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.618740 # Number of insts commited each cycle 85011754Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.263829 # Number of insts commited each cycle 85110585Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 85211754Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 1434472892 67.83% 67.83% # Number of insts commited each cycle 85311754Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 397205670 18.78% 86.61% # Number of insts commited each cycle 85411754Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 150685224 7.13% 93.74% # Number of insts commited each cycle 85511754Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 44578118 2.11% 95.85% # Number of insts commited each cycle 85611754Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 36046556 1.70% 97.55% # Number of insts commited each cycle 85711754Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 18010679 0.85% 98.40% # Number of insts commited each cycle 85811754Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 11270632 0.53% 98.93% # Number of insts commited each cycle 85911754Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 5868076 0.28% 99.21% # Number of insts commited each cycle 86011754Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 16657373 0.79% 100.00% # Number of insts commited each cycle 86110585Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 86210585Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 86310585Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 86411754Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 2114795220 # Number of insts commited each cycle 86511754Sandreas.hansson@arm.comsystem.cpu.commit.committedInsts 1113248331 # Number of instructions committed 86611754Sandreas.hansson@arm.comsystem.cpu.commit.committedOps 1308509399 # Number of ops (including micro ops) committed 86710585Sandreas.hansson@arm.comsystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 86811754Sandreas.hansson@arm.comsystem.cpu.commit.refs 396309299 # Number of memory references committed 86911754Sandreas.hansson@arm.comsystem.cpu.commit.loads 206361850 # Number of loads committed 87011754Sandreas.hansson@arm.comsystem.cpu.commit.membars 9184659 # Number of memory barriers committed 87111754Sandreas.hansson@arm.comsystem.cpu.commit.branches 248844974 # Number of branches committed 87211754Sandreas.hansson@arm.comsystem.cpu.commit.fp_insts 874713 # Number of committed floating point instructions. 87311754Sandreas.hansson@arm.comsystem.cpu.commit.int_insts 1195788175 # Number of committed integer instructions. 87411754Sandreas.hansson@arm.comsystem.cpu.commit.function_calls 31054705 # Number of function calls committed. 87510585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 87611754Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntAlu 909436322 69.50% 69.50% # Class of committed instruction 87711754Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntMult 2554044 0.20% 69.70% # Class of committed instruction 87811754Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntDiv 103998 0.01% 69.70% # Class of committed instruction 87911687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatAdd 8 0.00% 69.70% # Class of committed instruction 88011687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCmp 13 0.00% 69.70% # Class of committed instruction 88111687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCvt 21 0.00% 69.70% # Class of committed instruction 88211606Sandreas.sandberg@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 69.70% # Class of committed instruction 88311687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 69.70% # Class of committed instruction 88411606Sandreas.sandberg@arm.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.70% # Class of committed instruction 88511687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMisc 105694 0.01% 69.71% # Class of committed instruction 88611687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.71% # Class of committed instruction 88711687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.71% # Class of committed instruction 88811687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.71% # Class of committed instruction 88911687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.71% # Class of committed instruction 89011687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.71% # Class of committed instruction 89111687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.71% # Class of committed instruction 89211687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.71% # Class of committed instruction 89311687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 69.71% # Class of committed instruction 89411687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.71% # Class of committed instruction 89511687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 69.71% # Class of committed instruction 89611687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.71% # Class of committed instruction 89711687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.71% # Class of committed instruction 89811687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 69.71% # Class of committed instruction 89911687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.71% # Class of committed instruction 90011687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 69.71% # Class of committed instruction 90111687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 69.71% # Class of committed instruction 90211687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.71% # Class of committed instruction 90311687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 69.71% # Class of committed instruction 90411606Sandreas.sandberg@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.71% # Class of committed instruction 90511606Sandreas.sandberg@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.71% # Class of committed instruction 90611606Sandreas.sandberg@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.71% # Class of committed instruction 90711754Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 206248879 15.76% 85.48% # Class of committed instruction 90811754Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 189291443 14.47% 99.94% # Class of committed instruction 90911754Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMemRead 112971 0.01% 99.95% # Class of committed instruction 91011754Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMemWrite 656006 0.05% 100.00% # Class of committed instruction 91110585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 91210585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 91311754Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::total 1308509399 # Class of committed instruction 91411754Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 16657373 # number cycles where commit BW limit reached 91511754Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 3460150362 # The number of ROB reads 91611754Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 2757143126 # The number of ROB writes 91711754Sandreas.hansson@arm.comsystem.cpu.timesIdled 9093879 # Number of times that the entire CPU went into an idle state and unscheduled itself 91811754Sandreas.hansson@arm.comsystem.cpu.idleCycles 59938019 # Total number of cycles that the CPU has spent unscheduled due to idling 91911754Sandreas.hansson@arm.comsystem.cpu.quiesceCycles 100928420629 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 92011754Sandreas.hansson@arm.comsystem.cpu.committedInsts 1113248331 # Number of Instructions Simulated 92111754Sandreas.hansson@arm.comsystem.cpu.committedOps 1308509399 # Number of Ops (including micro ops) Simulated 92211754Sandreas.hansson@arm.comsystem.cpu.cpi 1.966281 # CPI: Cycles Per Instruction 92311754Sandreas.hansson@arm.comsystem.cpu.cpi_total 1.966281 # CPI: Total CPI of All Threads 92411754Sandreas.hansson@arm.comsystem.cpu.ipc 0.508574 # IPC: Instructions Per Cycle 92511754Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.508574 # IPC: Total IPC of All Threads 92611754Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 1608691208 # number of integer regfile reads 92711754Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 947917634 # number of integer regfile writes 92811754Sandreas.hansson@arm.comsystem.cpu.fp_regfile_reads 1422673 # number of floating regfile reads 92911754Sandreas.hansson@arm.comsystem.cpu.fp_regfile_writes 763952 # number of floating regfile writes 93011754Sandreas.hansson@arm.comsystem.cpu.cc_regfile_reads 314581614 # number of cc regfile reads 93111754Sandreas.hansson@arm.comsystem.cpu.cc_regfile_writes 315450766 # number of cc regfile writes 93211754Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 3476012517 # number of misc regfile reads 93311754Sandreas.hansson@arm.comsystem.cpu.misc_regfile_writes 44950556 # number of misc regfile writes 93411754Sandreas.hansson@arm.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 93511754Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 13775006 # number of replacements 93611754Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 511.982219 # Cycle average of tags in use 93711754Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 363107662 # Total number of references to valid blocks. 93811754Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 13775518 # Sample count of references to valid blocks. 93911754Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 26.358912 # Average number of references to valid blocks. 94011680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.warmup_cycle 1801582500 # Cycle when the warmup percentage was hit. 94111754Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.982219 # Average occupied blocks per requestor 94211680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999965 # Average percentage of cache occupancy 94311680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy 94410585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 94511754Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id 94611754Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 385 # Occupied blocks per task id 94711754Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id 94810585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 94911754Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 1608531103 # Number of tag accesses 95011754Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 1608531103 # Number of data accesses 95111754Sandreas.hansson@arm.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 95211754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 187963659 # number of ReadReq hits 95311754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 187963659 # number of ReadReq hits 95411754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 164128124 # number of WriteReq hits 95511754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 164128124 # number of WriteReq hits 95611754Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 464529 # number of SoftPFReq hits 95711754Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 464529 # number of SoftPFReq hits 95811754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_hits::cpu.data 334911 # number of WriteLineReq hits 95911754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_hits::total 334911 # number of WriteLineReq hits 96011754Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 4841304 # number of LoadLockedReq hits 96111754Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 4841304 # number of LoadLockedReq hits 96211754Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 5331661 # number of StoreCondReq hits 96311754Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 5331661 # number of StoreCondReq hits 96411754Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 352426694 # number of demand (read+write) hits 96511754Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 352426694 # number of demand (read+write) hits 96611754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 352891223 # number of overall hits 96711754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 352891223 # number of overall hits 96811754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 12866276 # number of ReadReq misses 96911754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 12866276 # number of ReadReq misses 97011754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 18869425 # number of WriteReq misses 97111754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 18869425 # number of WriteReq misses 97211754Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 2066021 # number of SoftPFReq misses 97311754Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 2066021 # number of SoftPFReq misses 97411754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_misses::cpu.data 1270837 # number of WriteLineReq misses 97511754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_misses::total 1270837 # number of WriteLineReq misses 97611754Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 552138 # number of LoadLockedReq misses 97711754Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 552138 # number of LoadLockedReq misses 97811680SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_misses::cpu.data 8 # number of StoreCondReq misses 97911680SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_misses::total 8 # number of StoreCondReq misses 98011754Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 33006538 # number of demand (read+write) misses 98111754Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 33006538 # number of demand (read+write) misses 98211754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 35072559 # number of overall misses 98311754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 35072559 # number of overall misses 98411754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 225016613000 # number of ReadReq miss cycles 98511754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 225016613000 # number of ReadReq miss cycles 98611754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 1113555465610 # number of WriteReq miss cycles 98711754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 1113555465610 # number of WriteReq miss cycles 98811754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_miss_latency::cpu.data 30066239407 # number of WriteLineReq miss cycles 98911754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_miss_latency::total 30066239407 # number of WriteLineReq miss cycles 99011754Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 9389478000 # number of LoadLockedReq miss cycles 99111754Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 9389478000 # number of LoadLockedReq miss cycles 99211754Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::cpu.data 268500 # number of StoreCondReq miss cycles 99311754Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::total 268500 # number of StoreCondReq miss cycles 99411754Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 1368638318017 # number of demand (read+write) miss cycles 99511754Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 1368638318017 # number of demand (read+write) miss cycles 99611754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 1368638318017 # number of overall miss cycles 99711754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 1368638318017 # number of overall miss cycles 99811754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 200829935 # number of ReadReq accesses(hits+misses) 99911754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 200829935 # number of ReadReq accesses(hits+misses) 100011754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 182997549 # number of WriteReq accesses(hits+misses) 100111754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 182997549 # number of WriteReq accesses(hits+misses) 100211754Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 2530550 # number of SoftPFReq accesses(hits+misses) 100311754Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 2530550 # number of SoftPFReq accesses(hits+misses) 100411754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_accesses::cpu.data 1605748 # number of WriteLineReq accesses(hits+misses) 100511754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_accesses::total 1605748 # number of WriteLineReq accesses(hits+misses) 100611754Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 5393442 # number of LoadLockedReq accesses(hits+misses) 100711754Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 5393442 # number of LoadLockedReq accesses(hits+misses) 100811754Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 5331669 # number of StoreCondReq accesses(hits+misses) 100911754Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 5331669 # number of StoreCondReq accesses(hits+misses) 101011754Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 385433232 # number of demand (read+write) accesses 101111754Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 385433232 # number of demand (read+write) accesses 101211754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 387963782 # number of overall (read+write) accesses 101311754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 387963782 # number of overall (read+write) accesses 101411754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.064066 # miss rate for ReadReq accesses 101511754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.064066 # miss rate for ReadReq accesses 101611754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.103113 # miss rate for WriteReq accesses 101711754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.103113 # miss rate for WriteReq accesses 101811754Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.816432 # miss rate for SoftPFReq accesses 101911754Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.816432 # miss rate for SoftPFReq accesses 102011754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791430 # miss rate for WriteLineReq accesses 102111754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_miss_rate::total 0.791430 # miss rate for WriteLineReq accesses 102211754Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.102372 # miss rate for LoadLockedReq accesses 102311754Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.102372 # miss rate for LoadLockedReq accesses 102411754Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses 102511754Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses 102611754Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.085635 # miss rate for demand accesses 102711754Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.085635 # miss rate for demand accesses 102811754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.090402 # miss rate for overall accesses 102911754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.090402 # miss rate for overall accesses 103011754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17488.868807 # average ReadReq miss latency 103111754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 17488.868807 # average ReadReq miss latency 103211754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59013.746609 # average WriteReq miss latency 103311754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 59013.746609 # average WriteReq miss latency 103411754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 23658.611928 # average WriteLineReq miss latency 103511754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_avg_miss_latency::total 23658.611928 # average WriteLineReq miss latency 103611754Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17005.672495 # average LoadLockedReq miss latency 103711754Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17005.672495 # average LoadLockedReq miss latency 103811754Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 33562.500000 # average StoreCondReq miss latency 103911754Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::total 33562.500000 # average StoreCondReq miss latency 104011754Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 41465.673195 # average overall miss latency 104111754Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 41465.673195 # average overall miss latency 104211754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 39023.052695 # average overall miss latency 104311754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 39023.052695 # average overall miss latency 104411754Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 29226576 # number of cycles access was blocked 104510585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 104611754Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 2109542 # number of cycles access was blocked 104710585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 104811754Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 13.854465 # average number of cycles each access was blocked 104910585Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 105011754Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 10412623 # number of writebacks 105111754Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 10412623 # number of writebacks 105211754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 5753869 # number of ReadReq MSHR hits 105311754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 5753869 # number of ReadReq MSHR hits 105411754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 15770096 # number of WriteReq MSHR hits 105511754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 15770096 # number of WriteReq MSHR hits 105611754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 6914 # number of WriteLineReq MSHR hits 105711754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_hits::total 6914 # number of WriteLineReq MSHR hits 105811754Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 268040 # number of LoadLockedReq MSHR hits 105911754Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 268040 # number of LoadLockedReq MSHR hits 106011754Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 21530879 # number of demand (read+write) MSHR hits 106111754Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 21530879 # number of demand (read+write) MSHR hits 106211754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 21530879 # number of overall MSHR hits 106311754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 21530879 # number of overall MSHR hits 106411754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 7112407 # number of ReadReq MSHR misses 106511754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 7112407 # number of ReadReq MSHR misses 106611754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 3099329 # number of WriteReq MSHR misses 106711754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 3099329 # number of WriteReq MSHR misses 106811754Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 2059217 # number of SoftPFReq MSHR misses 106911754Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::total 2059217 # number of SoftPFReq MSHR misses 107011754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1263923 # number of WriteLineReq MSHR misses 107111754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_misses::total 1263923 # number of WriteLineReq MSHR misses 107211754Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 284098 # number of LoadLockedReq MSHR misses 107311754Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::total 284098 # number of LoadLockedReq MSHR misses 107411680SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 8 # number of StoreCondReq MSHR misses 107511680SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses 107611754Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 11475659 # number of demand (read+write) MSHR misses 107711754Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 11475659 # number of demand (read+write) MSHR misses 107811754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 13534876 # number of overall MSHR misses 107911754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 13534876 # number of overall MSHR misses 108011606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33692 # number of ReadReq MSHR uncacheable 108111606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable::total 33692 # number of ReadReq MSHR uncacheable 108211606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33703 # number of WriteReq MSHR uncacheable 108311606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable::total 33703 # number of WriteReq MSHR uncacheable 108411606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67395 # number of overall MSHR uncacheable misses 108511606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_misses::total 67395 # number of overall MSHR uncacheable misses 108611754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 119879387000 # number of ReadReq MSHR miss cycles 108711754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 119879387000 # number of ReadReq MSHR miss cycles 108811754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 164321917838 # number of WriteReq MSHR miss cycles 108911754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 164321917838 # number of WriteReq MSHR miss cycles 109011754Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 34890815500 # number of SoftPFReq MSHR miss cycles 109111754Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 34890815500 # number of SoftPFReq MSHR miss cycles 109211754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 28496186907 # number of WriteLineReq MSHR miss cycles 109311754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_miss_latency::total 28496186907 # number of WriteLineReq MSHR miss cycles 109411754Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 4243086000 # number of LoadLockedReq MSHR miss cycles 109511754Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 4243086000 # number of LoadLockedReq MSHR miss cycles 109611754Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 260500 # number of StoreCondReq MSHR miss cycles 109711754Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::total 260500 # number of StoreCondReq MSHR miss cycles 109811754Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 312697491745 # number of demand (read+write) MSHR miss cycles 109911754Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 312697491745 # number of demand (read+write) MSHR miss cycles 110011754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 347588307245 # number of overall MSHR miss cycles 110111754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 347588307245 # number of overall MSHR miss cycles 110211754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6225622500 # number of ReadReq MSHR uncacheable cycles 110311754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6225622500 # number of ReadReq MSHR uncacheable cycles 110411754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6225622500 # number of overall MSHR uncacheable cycles 110511754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::total 6225622500 # number of overall MSHR uncacheable cycles 110611754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035415 # mshr miss rate for ReadReq accesses 110711754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035415 # mshr miss rate for ReadReq accesses 110811754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016936 # mshr miss rate for WriteReq accesses 110911754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016936 # mshr miss rate for WriteReq accesses 111011754Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.813743 # mshr miss rate for SoftPFReq accesses 111111754Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.813743 # mshr miss rate for SoftPFReq accesses 111211754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787124 # mshr miss rate for WriteLineReq accesses 111311754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787124 # mshr miss rate for WriteLineReq accesses 111411754Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.052675 # mshr miss rate for LoadLockedReq accesses 111511754Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.052675 # mshr miss rate for LoadLockedReq accesses 111611754Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses 111711754Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses 111811754Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029773 # mshr miss rate for demand accesses 111911754Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.029773 # mshr miss rate for demand accesses 112011754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034887 # mshr miss rate for overall accesses 112111754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.034887 # mshr miss rate for overall accesses 112211754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16854.967242 # average ReadReq mshr miss latency 112311754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16854.967242 # average ReadReq mshr miss latency 112411754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53018.546220 # average WriteReq mshr miss latency 112511754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53018.546220 # average WriteReq mshr miss latency 112611754Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16943.729340 # average SoftPFReq mshr miss latency 112711754Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16943.729340 # average SoftPFReq mshr miss latency 112811754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 22545.825107 # average WriteLineReq mshr miss latency 112911754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 22545.825107 # average WriteLineReq mshr miss latency 113011754Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14935.289935 # average LoadLockedReq mshr miss latency 113111754Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14935.289935 # average LoadLockedReq mshr miss latency 113211754Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 32562.500000 # average StoreCondReq mshr miss latency 113311754Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 32562.500000 # average StoreCondReq mshr miss latency 113411754Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27248.761204 # average overall mshr miss latency 113511754Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 27248.761204 # average overall mshr miss latency 113611754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25680.937693 # average overall mshr miss latency 113711754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 25680.937693 # average overall mshr miss latency 113811754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184780.437493 # average ReadReq mshr uncacheable latency 113911754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184780.437493 # average ReadReq mshr uncacheable latency 114011754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92375.139105 # average overall mshr uncacheable latency 114111754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92375.139105 # average overall mshr uncacheable latency 114211754Sandreas.hansson@arm.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 114311754Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 16945634 # number of replacements 114411754Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 511.953469 # Cycle average of tags in use 114511754Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 446936468 # Total number of references to valid blocks. 114611754Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 16946146 # Sample count of references to valid blocks. 114711754Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 26.373930 # Average number of references to valid blocks. 114811754Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 13767479500 # Cycle when the warmup percentage was hit. 114911754Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 511.953469 # Average occupied blocks per requestor 115011680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.999909 # Average percentage of cache occupancy 115111680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy 115210585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 115311754Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id 115411754Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id 115511754Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 77 # Occupied blocks per task id 115610585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 115711754Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 481618789 # Number of tag accesses 115811754Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 481618789 # Number of data accesses 115911754Sandreas.hansson@arm.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 116011754Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 446936468 # number of ReadReq hits 116111754Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 446936468 # number of ReadReq hits 116211754Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 446936468 # number of demand (read+write) hits 116311754Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 446936468 # number of demand (read+write) hits 116411754Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 446936468 # number of overall hits 116511754Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 446936468 # number of overall hits 116611754Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 17735952 # number of ReadReq misses 116711754Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 17735952 # number of ReadReq misses 116811754Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 17735952 # number of demand (read+write) misses 116911754Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 17735952 # number of demand (read+write) misses 117011754Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 17735952 # number of overall misses 117111754Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 17735952 # number of overall misses 117211754Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 237635395867 # number of ReadReq miss cycles 117311754Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 237635395867 # number of ReadReq miss cycles 117411754Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 237635395867 # number of demand (read+write) miss cycles 117511754Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 237635395867 # number of demand (read+write) miss cycles 117611754Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 237635395867 # number of overall miss cycles 117711754Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 237635395867 # number of overall miss cycles 117811754Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 464672420 # number of ReadReq accesses(hits+misses) 117911754Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 464672420 # number of ReadReq accesses(hits+misses) 118011754Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 464672420 # number of demand (read+write) accesses 118111754Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 464672420 # number of demand (read+write) accesses 118211754Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 464672420 # number of overall (read+write) accesses 118311754Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 464672420 # number of overall (read+write) accesses 118411754Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.038169 # miss rate for ReadReq accesses 118511754Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.038169 # miss rate for ReadReq accesses 118611754Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.038169 # miss rate for demand accesses 118711754Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.038169 # miss rate for demand accesses 118811754Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.038169 # miss rate for overall accesses 118911754Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.038169 # miss rate for overall accesses 119011754Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13398.513701 # average ReadReq miss latency 119111754Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 13398.513701 # average ReadReq miss latency 119211754Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 13398.513701 # average overall miss latency 119311754Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 13398.513701 # average overall miss latency 119411754Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 13398.513701 # average overall miss latency 119511754Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 13398.513701 # average overall miss latency 119611754Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 21075 # number of cycles access was blocked 119710585Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 119811754Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 1467 # number of cycles access was blocked 119910585Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 120011754Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 14.366053 # average number of cycles each access was blocked 120110585Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 120211754Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::writebacks 16945634 # number of writebacks 120311754Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::total 16945634 # number of writebacks 120411754Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 789581 # number of ReadReq MSHR hits 120511754Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 789581 # number of ReadReq MSHR hits 120611754Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 789581 # number of demand (read+write) MSHR hits 120711754Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 789581 # number of demand (read+write) MSHR hits 120811754Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 789581 # number of overall MSHR hits 120911754Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 789581 # number of overall MSHR hits 121011754Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 16946371 # number of ReadReq MSHR misses 121111754Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 16946371 # number of ReadReq MSHR misses 121211754Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 16946371 # number of demand (read+write) MSHR misses 121311754Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 16946371 # number of demand (read+write) MSHR misses 121411754Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 16946371 # number of overall MSHR misses 121511754Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 16946371 # number of overall MSHR misses 121611201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21294 # number of ReadReq MSHR uncacheable 121711201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable::total 21294 # number of ReadReq MSHR uncacheable 121811201Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses 121911201Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_misses::total 21294 # number of overall MSHR uncacheable misses 122011754Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 213535123378 # number of ReadReq MSHR miss cycles 122111754Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 213535123378 # number of ReadReq MSHR miss cycles 122211754Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 213535123378 # number of demand (read+write) MSHR miss cycles 122311754Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 213535123378 # number of demand (read+write) MSHR miss cycles 122411754Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 213535123378 # number of overall MSHR miss cycles 122511754Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 213535123378 # number of overall MSHR miss cycles 122611680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1752662500 # number of ReadReq MSHR uncacheable cycles 122711680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1752662500 # number of ReadReq MSHR uncacheable cycles 122811680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1752662500 # number of overall MSHR uncacheable cycles 122911680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_uncacheable_latency::total 1752662500 # number of overall MSHR uncacheable cycles 123011754Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.036470 # mshr miss rate for ReadReq accesses 123111754Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.036470 # mshr miss rate for ReadReq accesses 123211754Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.036470 # mshr miss rate for demand accesses 123311754Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.036470 # mshr miss rate for demand accesses 123411754Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.036470 # mshr miss rate for overall accesses 123511754Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.036470 # mshr miss rate for overall accesses 123611754Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12600.640183 # average ReadReq mshr miss latency 123711754Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12600.640183 # average ReadReq mshr miss latency 123811754Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12600.640183 # average overall mshr miss latency 123911754Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 12600.640183 # average overall mshr miss latency 124011754Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12600.640183 # average overall mshr miss latency 124111754Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 12600.640183 # average overall mshr miss latency 124211680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82307.809712 # average ReadReq mshr uncacheable latency 124311680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82307.809712 # average ReadReq mshr uncacheable latency 124411680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82307.809712 # average overall mshr uncacheable latency 124511680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82307.809712 # average overall mshr uncacheable latency 124611754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 124711754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 2400192 # number of replacements 124811754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 65402.662910 # Cycle average of tags in use 124911754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 59310777 # Total number of references to valid blocks. 125011754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 2462586 # Sample count of references to valid blocks. 125111754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 24.084754 # Average number of references to valid blocks. 125211754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 2677803000 # Cycle when the warmup percentage was hit. 125311754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 9273.019739 # Average occupied blocks per requestor 125411754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 380.440424 # Average occupied blocks per requestor 125511754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 420.878818 # Average occupied blocks per requestor 125611754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 6709.693607 # Average occupied blocks per requestor 125711754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 48618.630322 # Average occupied blocks per requestor 125811754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.141495 # Average percentage of cache occupancy 125911754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005805 # Average percentage of cache occupancy 126011754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006422 # Average percentage of cache occupancy 126111754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.102382 # Average percentage of cache occupancy 126211754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.741861 # Average percentage of cache occupancy 126311754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.997965 # Average percentage of cache occupancy 126411754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1023 239 # Occupied blocks per task id 126511754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 62155 # Occupied blocks per task id 126611754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1023::4 239 # Occupied blocks per task id 126711754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id 126811754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 336 # Occupied blocks per task id 126911754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 998 # Occupied blocks per task id 127011754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 5581 # Occupied blocks per task id 127111754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 55200 # Occupied blocks per task id 127211754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1023 0.003647 # Percentage of cache occupancy per task id 127311754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.948410 # Percentage of cache occupancy per task id 127411754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 508162919 # Number of tag accesses 127511754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 508162919 # Number of data accesses 127611754Sandreas.hansson@arm.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 127711754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 1310607 # number of ReadReq hits 127811754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.itb.walker 311860 # number of ReadReq hits 127911754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 1622467 # number of ReadReq hits 128011754Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 10412623 # number of WritebackDirty hits 128111754Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 10412623 # number of WritebackDirty hits 128211754Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 16942916 # number of WritebackClean hits 128311754Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 16942916 # number of WritebackClean hits 128411754Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 39365 # number of UpgradeReq hits 128511754Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 39365 # number of UpgradeReq hits 128611754Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::cpu.data 5 # number of SCUpgradeReq hits 128711754Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::total 5 # number of SCUpgradeReq hits 128811754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 1729760 # number of ReadExReq hits 128911754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 1729760 # number of ReadExReq hits 129011754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16850415 # number of ReadCleanReq hits 129111754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 16850415 # number of ReadCleanReq hits 129211754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 8995594 # number of ReadSharedReq hits 129311754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 8995594 # number of ReadSharedReq hits 129411754Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_hits::cpu.data 670573 # number of InvalidateReq hits 129511754Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_hits::total 670573 # number of InvalidateReq hits 129611754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.dtb.walker 1310607 # number of demand (read+write) hits 129711754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.itb.walker 311860 # number of demand (read+write) hits 129811754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 16850415 # number of demand (read+write) hits 129911754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 10725354 # number of demand (read+write) hits 130011754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 29198236 # number of demand (read+write) hits 130111754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.dtb.walker 1310607 # number of overall hits 130211754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.itb.walker 311860 # number of overall hits 130311754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 16850415 # number of overall hits 130411754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 10725354 # number of overall hits 130511754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 29198236 # number of overall hits 130611754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 10751 # number of ReadReq misses 130711754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.itb.walker 8953 # number of ReadReq misses 130811754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 19704 # number of ReadReq misses 130911754Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 4081 # number of UpgradeReq misses 131011754Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 4081 # number of UpgradeReq misses 131111754Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses 131211754Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses 131311754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 1342610 # number of ReadExReq misses 131411754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 1342610 # number of ReadExReq misses 131511754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 95730 # number of ReadCleanReq misses 131611754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 95730 # number of ReadCleanReq misses 131711754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 443644 # number of ReadSharedReq misses 131811754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 443644 # number of ReadSharedReq misses 131911754Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_misses::cpu.data 593350 # number of InvalidateReq misses 132011754Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_misses::total 593350 # number of InvalidateReq misses 132111754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.dtb.walker 10751 # number of demand (read+write) misses 132211754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.itb.walker 8953 # number of demand (read+write) misses 132311754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 95730 # number of demand (read+write) misses 132411754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 1786254 # number of demand (read+write) misses 132511754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 1901688 # number of demand (read+write) misses 132611754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.dtb.walker 10751 # number of overall misses 132711754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.itb.walker 8953 # number of overall misses 132811754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 95730 # number of overall misses 132911754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 1786254 # number of overall misses 133011754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 1901688 # number of overall misses 133111754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1481609000 # number of ReadReq miss cycles 133211754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 989051000 # number of ReadReq miss cycles 133311754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 2470660000 # number of ReadReq miss cycles 133411754Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 73641000 # number of UpgradeReq miss cycles 133511754Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::total 73641000 # number of UpgradeReq miss cycles 133611754Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162500 # number of SCUpgradeReq miss cycles 133711754Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::total 162500 # number of SCUpgradeReq miss cycles 133811754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 140820985000 # number of ReadExReq miss cycles 133911754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 140820985000 # number of ReadExReq miss cycles 134011754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 10474446000 # number of ReadCleanReq miss cycles 134111754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 10474446000 # number of ReadCleanReq miss cycles 134211754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49360603500 # number of ReadSharedReq miss cycles 134311754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 49360603500 # number of ReadSharedReq miss cycles 134411754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1481609000 # number of demand (read+write) miss cycles 134511754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.itb.walker 989051000 # number of demand (read+write) miss cycles 134611754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 10474446000 # number of demand (read+write) miss cycles 134711754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 190181588500 # number of demand (read+write) miss cycles 134811754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 203126694500 # number of demand (read+write) miss cycles 134911754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1481609000 # number of overall miss cycles 135011754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.itb.walker 989051000 # number of overall miss cycles 135111754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 10474446000 # number of overall miss cycles 135211754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 190181588500 # number of overall miss cycles 135311754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 203126694500 # number of overall miss cycles 135411754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 1321358 # number of ReadReq accesses(hits+misses) 135511754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 320813 # number of ReadReq accesses(hits+misses) 135611754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 1642171 # number of ReadReq accesses(hits+misses) 135711754Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 10412623 # number of WritebackDirty accesses(hits+misses) 135811754Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 10412623 # number of WritebackDirty accesses(hits+misses) 135911754Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 16942916 # number of WritebackClean accesses(hits+misses) 136011754Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 16942916 # number of WritebackClean accesses(hits+misses) 136111754Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 43446 # number of UpgradeReq accesses(hits+misses) 136211754Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 43446 # number of UpgradeReq accesses(hits+misses) 136311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 8 # number of SCUpgradeReq accesses(hits+misses) 136411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::total 8 # number of SCUpgradeReq accesses(hits+misses) 136511754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 3072370 # number of ReadExReq accesses(hits+misses) 136611754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 3072370 # number of ReadExReq accesses(hits+misses) 136711754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 16946145 # number of ReadCleanReq accesses(hits+misses) 136811754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 16946145 # number of ReadCleanReq accesses(hits+misses) 136911754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 9439238 # number of ReadSharedReq accesses(hits+misses) 137011754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 9439238 # number of ReadSharedReq accesses(hits+misses) 137111754Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_accesses::cpu.data 1263923 # number of InvalidateReq accesses(hits+misses) 137211754Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_accesses::total 1263923 # number of InvalidateReq accesses(hits+misses) 137311754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.dtb.walker 1321358 # number of demand (read+write) accesses 137411754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.itb.walker 320813 # number of demand (read+write) accesses 137511754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 16946145 # number of demand (read+write) accesses 137611754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 12511608 # number of demand (read+write) accesses 137711754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 31099924 # number of demand (read+write) accesses 137811754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.dtb.walker 1321358 # number of overall (read+write) accesses 137911754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.itb.walker 320813 # number of overall (read+write) accesses 138011754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 16946145 # number of overall (read+write) accesses 138111754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 12511608 # number of overall (read+write) accesses 138211754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 31099924 # number of overall (read+write) accesses 138311754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.008136 # miss rate for ReadReq accesses 138411754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.027907 # miss rate for ReadReq accesses 138511754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.011999 # miss rate for ReadReq accesses 138611754Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.093933 # miss rate for UpgradeReq accesses 138711754Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.093933 # miss rate for UpgradeReq accesses 138811754Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.375000 # miss rate for SCUpgradeReq accesses 138911754Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.375000 # miss rate for SCUpgradeReq accesses 139011754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436995 # miss rate for ReadExReq accesses 139111754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.436995 # miss rate for ReadExReq accesses 139211754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005649 # miss rate for ReadCleanReq accesses 139311754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005649 # miss rate for ReadCleanReq accesses 139411754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.047000 # miss rate for ReadSharedReq accesses 139511754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.047000 # miss rate for ReadSharedReq accesses 139611754Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.469451 # miss rate for InvalidateReq accesses 139711754Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_miss_rate::total 0.469451 # miss rate for InvalidateReq accesses 139811754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.008136 # miss rate for demand accesses 139911754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.027907 # miss rate for demand accesses 140011754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.005649 # miss rate for demand accesses 140111754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.142768 # miss rate for demand accesses 140211754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.061148 # miss rate for demand accesses 140311754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.008136 # miss rate for overall accesses 140411754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.027907 # miss rate for overall accesses 140511754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.005649 # miss rate for overall accesses 140611754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.142768 # miss rate for overall accesses 140711754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.061148 # miss rate for overall accesses 140811754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137811.273370 # average ReadReq miss latency 140911754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 110471.462080 # average ReadReq miss latency 141011754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 125388.753553 # average ReadReq miss latency 141111754Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 18044.841951 # average UpgradeReq miss latency 141211754Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 18044.841951 # average UpgradeReq miss latency 141311754Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 54166.666667 # average SCUpgradeReq miss latency 141411754Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 54166.666667 # average SCUpgradeReq miss latency 141511754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 104885.994444 # average ReadExReq miss latency 141611754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 104885.994444 # average ReadExReq miss latency 141711754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 109416.546537 # average ReadCleanReq miss latency 141811754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 109416.546537 # average ReadCleanReq miss latency 141911754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 111261.740269 # average ReadSharedReq miss latency 142011754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 111261.740269 # average ReadSharedReq miss latency 142111754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137811.273370 # average overall miss latency 142211754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 110471.462080 # average overall miss latency 142311754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 109416.546537 # average overall miss latency 142411754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 106469.510215 # average overall miss latency 142511754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 106813.890870 # average overall miss latency 142611754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137811.273370 # average overall miss latency 142711754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 110471.462080 # average overall miss latency 142811754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 109416.546537 # average overall miss latency 142911754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 106469.510215 # average overall miss latency 143011754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 106813.890870 # average overall miss latency 143110585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 143210585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 143310585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 143410585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 143510585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 143610585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 143711754Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 2127726 # number of writebacks 143811754Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 2127726 # number of writebacks 143911754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.itb.walker 4 # number of ReadReq MSHR hits 144011754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits 144111353Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits 144211353Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits 144311754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.itb.walker 4 # number of demand (read+write) MSHR hits 144411353Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits 144511754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 25 # number of demand (read+write) MSHR hits 144611754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.itb.walker 4 # number of overall MSHR hits 144711353Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits 144811754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 25 # number of overall MSHR hits 144911754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 10751 # number of ReadReq MSHR misses 145011754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 8949 # number of ReadReq MSHR misses 145111754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 19700 # number of ReadReq MSHR misses 145211754Sandreas.hansson@arm.comsystem.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses 145311754Sandreas.hansson@arm.comsystem.cpu.l2cache.CleanEvict_mshr_misses::total 2 # number of CleanEvict MSHR misses 145411754Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4081 # number of UpgradeReq MSHR misses 145511754Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 4081 # number of UpgradeReq MSHR misses 145611754Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses 145711754Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses 145811754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1342610 # number of ReadExReq MSHR misses 145911754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 1342610 # number of ReadExReq MSHR misses 146011754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 95730 # number of ReadCleanReq MSHR misses 146111754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 95730 # number of ReadCleanReq MSHR misses 146211754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 443623 # number of ReadSharedReq MSHR misses 146311754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 443623 # number of ReadSharedReq MSHR misses 146411754Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 593350 # number of InvalidateReq MSHR misses 146511754Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_misses::total 593350 # number of InvalidateReq MSHR misses 146611754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 10751 # number of demand (read+write) MSHR misses 146711754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 8949 # number of demand (read+write) MSHR misses 146811754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 95730 # number of demand (read+write) MSHR misses 146911754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 1786233 # number of demand (read+write) MSHR misses 147011754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 1901663 # number of demand (read+write) MSHR misses 147111754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 10751 # number of overall MSHR misses 147211754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 8949 # number of overall MSHR misses 147311754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 95730 # number of overall MSHR misses 147411754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 1786233 # number of overall MSHR misses 147511754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 1901663 # number of overall MSHR misses 147611201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 21294 # number of ReadReq MSHR uncacheable 147711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33692 # number of ReadReq MSHR uncacheable 147811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::total 54986 # number of ReadReq MSHR uncacheable 147911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33703 # number of WriteReq MSHR uncacheable 148011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable::total 33703 # number of WriteReq MSHR uncacheable 148111201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses 148211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67395 # number of overall MSHR uncacheable misses 148311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::total 88689 # number of overall MSHR uncacheable misses 148411754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1374099000 # number of ReadReq MSHR miss cycles 148511754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 899358000 # number of ReadReq MSHR miss cycles 148611754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 2273457000 # number of ReadReq MSHR miss cycles 148711754Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 77835000 # number of UpgradeReq MSHR miss cycles 148811754Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 77835000 # number of UpgradeReq MSHR miss cycles 148911754Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 163000 # number of SCUpgradeReq MSHR miss cycles 149011754Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 163000 # number of SCUpgradeReq MSHR miss cycles 149111754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 127394865041 # number of ReadExReq MSHR miss cycles 149211754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 127394865041 # number of ReadExReq MSHR miss cycles 149311754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 9517134048 # number of ReadCleanReq MSHR miss cycles 149411754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 9517134048 # number of ReadCleanReq MSHR miss cycles 149511754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 44922827064 # number of ReadSharedReq MSHR miss cycles 149611754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 44922827064 # number of ReadSharedReq MSHR miss cycles 149711754Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 12274426752 # number of InvalidateReq MSHR miss cycles 149811754Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 12274426752 # number of InvalidateReq MSHR miss cycles 149911754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1374099000 # number of demand (read+write) MSHR miss cycles 150011754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 899358000 # number of demand (read+write) MSHR miss cycles 150111754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9517134048 # number of demand (read+write) MSHR miss cycles 150211754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 172317692105 # number of demand (read+write) MSHR miss cycles 150311754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 184108283153 # number of demand (read+write) MSHR miss cycles 150411754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1374099000 # number of overall MSHR miss cycles 150511754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 899358000 # number of overall MSHR miss cycles 150611754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9517134048 # number of overall MSHR miss cycles 150711754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 172317692105 # number of overall MSHR miss cycles 150811754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 184108283153 # number of overall MSHR miss cycles 150911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1486487500 # number of ReadReq MSHR uncacheable cycles 151011754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5804330500 # number of ReadReq MSHR uncacheable cycles 151111754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7290818000 # number of ReadReq MSHR uncacheable cycles 151211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1486487500 # number of overall MSHR uncacheable cycles 151311754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5804330500 # number of overall MSHR uncacheable cycles 151411754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::total 7290818000 # number of overall MSHR uncacheable cycles 151511754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.008136 # mshr miss rate for ReadReq accesses 151611754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.027895 # mshr miss rate for ReadReq accesses 151711754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.011996 # mshr miss rate for ReadReq accesses 151810892Sandreas.hansson@arm.comsystem.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 151910892Sandreas.hansson@arm.comsystem.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 152011754Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.093933 # mshr miss rate for UpgradeReq accesses 152111754Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.093933 # mshr miss rate for UpgradeReq accesses 152211754Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.375000 # mshr miss rate for SCUpgradeReq accesses 152311754Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.375000 # mshr miss rate for SCUpgradeReq accesses 152411754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436995 # mshr miss rate for ReadExReq accesses 152511754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436995 # mshr miss rate for ReadExReq accesses 152611754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005649 # mshr miss rate for ReadCleanReq accesses 152711754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005649 # mshr miss rate for ReadCleanReq accesses 152811754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.046998 # mshr miss rate for ReadSharedReq accesses 152911754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.046998 # mshr miss rate for ReadSharedReq accesses 153011754Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.469451 # mshr miss rate for InvalidateReq accesses 153111754Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.469451 # mshr miss rate for InvalidateReq accesses 153211754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.008136 # mshr miss rate for demand accesses 153311754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.027895 # mshr miss rate for demand accesses 153411754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005649 # mshr miss rate for demand accesses 153511754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.142766 # mshr miss rate for demand accesses 153611754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.061147 # mshr miss rate for demand accesses 153711754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.008136 # mshr miss rate for overall accesses 153811754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.027895 # mshr miss rate for overall accesses 153911754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005649 # mshr miss rate for overall accesses 154011754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.142766 # mshr miss rate for overall accesses 154111754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.061147 # mshr miss rate for overall accesses 154211754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127811.273370 # average ReadReq mshr miss latency 154311754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 100498.156219 # average ReadReq mshr miss latency 154411754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 115403.908629 # average ReadReq mshr miss latency 154511754Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19072.531242 # average UpgradeReq mshr miss latency 154611754Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19072.531242 # average UpgradeReq mshr miss latency 154711754Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 54333.333333 # average SCUpgradeReq mshr miss latency 154811754Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 54333.333333 # average SCUpgradeReq mshr miss latency 154911754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 94885.979578 # average ReadExReq mshr miss latency 155011754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 94885.979578 # average ReadExReq mshr miss latency 155111754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 99416.421686 # average ReadCleanReq mshr miss latency 155211754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 99416.421686 # average ReadCleanReq mshr miss latency 155311754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 101263.521197 # average ReadSharedReq mshr miss latency 155411754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 101263.521197 # average ReadSharedReq mshr miss latency 155511754Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20686.655013 # average InvalidateReq mshr miss latency 155611754Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20686.655013 # average InvalidateReq mshr miss latency 155711754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127811.273370 # average overall mshr miss latency 155811754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 100498.156219 # average overall mshr miss latency 155911754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 99416.421686 # average overall mshr miss latency 156011754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96469.885007 # average overall mshr miss latency 156111754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 96814.358355 # average overall mshr miss latency 156211754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127811.273370 # average overall mshr miss latency 156311754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 100498.156219 # average overall mshr miss latency 156411754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 99416.421686 # average overall mshr miss latency 156511754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96469.885007 # average overall mshr miss latency 156611754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 96814.358355 # average overall mshr miss latency 156711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69807.809712 # average ReadReq mshr uncacheable latency 156811754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172276.222842 # average ReadReq mshr uncacheable latency 156911754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132594.078493 # average ReadReq mshr uncacheable latency 157011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69807.809712 # average overall mshr uncacheable latency 157111754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86124.052229 # average overall mshr uncacheable latency 157211754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 82206.564512 # average overall mshr uncacheable latency 157311754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 62406736 # Total number of requests made to the snoop filter. 157411754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 31684635 # Number of requests hitting in the snoop filter with a single holder of the requested data. 157511754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 4771 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 157611754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 2157 # Total number of snoops made to the snoop filter. 157711754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 2157 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 157811138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 157911754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 158011754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 2262463 # Transaction distribution 158111754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 28648866 # Transaction distribution 158211606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::WriteReq 33703 # Transaction distribution 158311606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::WriteResp 33703 # Transaction distribution 158411754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 12540349 # Transaction distribution 158511754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 16945634 # Transaction distribution 158611754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 3634849 # Transaction distribution 158711754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 43449 # Transaction distribution 158811680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::SCUpgradeReq 8 # Transaction distribution 158911754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 43457 # Transaction distribution 159011754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 3072370 # Transaction distribution 159111754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 3072370 # Transaction distribution 159211754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 16946371 # Transaction distribution 159311754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 9441630 # Transaction distribution 159411754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::InvalidateReq 1296845 # Transaction distribution 159511754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::InvalidateResp 1263929 # Transaction distribution 159611754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50880736 # Packet count per connected master and slave (bytes) 159711754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41548571 # Packet count per connected master and slave (bytes) 159811754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 789343 # Packet count per connected master and slave (bytes) 159911754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3060305 # Packet count per connected master and slave (bytes) 160011754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 96278955 # Packet count per connected master and slave (bytes) 160111754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2169414432 # Cumulative packet size per connected master and slave (bytes) 160211754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1467392114 # Cumulative packet size per connected master and slave (bytes) 160311754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2566504 # Cumulative packet size per connected master and slave (bytes) 160411754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10570864 # Cumulative packet size per connected master and slave (bytes) 160511754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 3649943914 # Cumulative packet size per connected master and slave (bytes) 160611754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 3001846 # Total snoops (count) 160711754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopTraffic 140762320 # Total snoop traffic (bytes) 160811754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 35497041 # Request fanout histogram 160911754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.026133 # Request fanout histogram 161011754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.159532 # Request fanout histogram 161110585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 161211754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 34569387 97.39% 97.39% # Request fanout histogram 161311754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 927654 2.61% 100.00% # Request fanout histogram 161411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 161510585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 161611138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 161711138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 161811754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 35497041 # Request fanout histogram 161911754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 59266206483 # Layer occupancy (ticks) 162010585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 162111754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.occupancy 1503389 # Layer occupancy (ticks) 162210585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 162311754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 25451406259 # Layer occupancy (ticks) 162410585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 162511754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 19476952327 # Layer occupancy (ticks) 162610585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 162711754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer2.occupancy 468902194 # Layer occupancy (ticks) 162810585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 162911754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer3.occupancy 1739672503 # Layer occupancy (ticks) 163010585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 163111754Sandreas.hansson@arm.comsystem.iobus.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 163211754Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 40306 # Transaction distribution 163311754Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 40306 # Transaction distribution 163410892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 136571 # Transaction distribution 163510892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 136571 # Transaction distribution 163610726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) 163710585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 163811245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 163910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 164010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 164110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 164210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 164310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 164410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 164510585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 164610585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 164710892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 164810585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 164910892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) 165011754Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230970 # Packet count per connected master and slave (bytes) 165111754Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 230970 # Packet count per connected master and slave (bytes) 165210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 165310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 165411754Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 353754 # Packet count per connected master and slave (bytes) 165510726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) 165610585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 165711245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 165810585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 165910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 166010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 166110585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 166210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 166310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 166410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 166510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 166610892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 166710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 166810892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) 166911754Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334312 # Cumulative packet size per connected master and slave (bytes) 167011754Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7334312 # Cumulative packet size per connected master and slave (bytes) 167110585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 167210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 167311754Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 7492232 # Cumulative packet size per connected master and slave (bytes) 167411754Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 41898000 # Layer occupancy (ticks) 167510585Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 167611754Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) 167710585Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 167811754Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 340000 # Layer occupancy (ticks) 167910585Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 168011201Sandreas.hansson@arm.comsystem.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) 168110585Sandreas.hansson@arm.comsystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 168211245Sandreas.sandberg@arm.comsystem.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) 168311245Sandreas.sandberg@arm.comsystem.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 168411201Sandreas.hansson@arm.comsystem.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) 168510585Sandreas.hansson@arm.comsystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 168611606Sandreas.sandberg@arm.comsystem.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) 168710585Sandreas.hansson@arm.comsystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 168811201Sandreas.hansson@arm.comsystem.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) 168910585Sandreas.hansson@arm.comsystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 169011201Sandreas.hansson@arm.comsystem.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) 169110585Sandreas.hansson@arm.comsystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 169211680SCurtis.Dunham@arm.comsystem.iobus.reqLayer16.occupancy 14500 # Layer occupancy (ticks) 169310585Sandreas.hansson@arm.comsystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 169411201Sandreas.hansson@arm.comsystem.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 169510585Sandreas.hansson@arm.comsystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 169611754Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 25176500 # Layer occupancy (ticks) 169710585Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 169811754Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 36502500 # Layer occupancy (ticks) 169910585Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 170011754Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 568938305 # Layer occupancy (ticks) 170110585Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 170210892Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) 170310585Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 170411754Sandreas.hansson@arm.comsystem.iobus.respLayer3.occupancy 147730000 # Layer occupancy (ticks) 170510585Sandreas.hansson@arm.comsystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 170610892Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 170710585Sandreas.hansson@arm.comsystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 170811754Sandreas.hansson@arm.comsystem.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 170911754Sandreas.hansson@arm.comsystem.iocache.tags.replacements 115466 # number of replacements 171011754Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 10.450358 # Cycle average of tags in use 171110585Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 171211754Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 115482 # Sample count of references to valid blocks. 171310585Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 171411754Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 13091904723000 # Cycle when the warmup percentage was hit. 171511754Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 3.528286 # Average occupied blocks per requestor 171611754Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 6.922072 # Average occupied blocks per requestor 171711687Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.220518 # Average percentage of cache occupancy 171811754Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.432629 # Average percentage of cache occupancy 171911754Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.653147 # Average percentage of cache occupancy 172010585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 172110585Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 172210585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 172311754Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 1039722 # Number of tag accesses 172411754Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 1039722 # Number of data accesses 172511754Sandreas.hansson@arm.comsystem.iocache.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 172610585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 172711754Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ide 8821 # number of ReadReq misses 172811754Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 8858 # number of ReadReq misses 172910585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 173010585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 173110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 173210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 173310585Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 173411754Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ide 115485 # number of demand (read+write) misses 173511754Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 115525 # number of demand (read+write) misses 173610585Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 173711754Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ide 115485 # number of overall misses 173811754Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 115525 # number of overall misses 173911680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5085500 # number of ReadReq miss cycles 174011754Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ide 1915316073 # number of ReadReq miss cycles 174111754Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 1920401573 # number of ReadReq miss cycles 174210892Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 174310892Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles 174411754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::realview.ide 13385817732 # number of WriteLineReq miss cycles 174511754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::total 13385817732 # number of WriteLineReq miss cycles 174611680SCurtis.Dunham@arm.comsystem.iocache.demand_miss_latency::realview.ethernet 5436500 # number of demand (read+write) miss cycles 174711754Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ide 15301133805 # number of demand (read+write) miss cycles 174811754Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 15306570305 # number of demand (read+write) miss cycles 174911680SCurtis.Dunham@arm.comsystem.iocache.overall_miss_latency::realview.ethernet 5436500 # number of overall miss cycles 175011754Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ide 15301133805 # number of overall miss cycles 175111754Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 15306570305 # number of overall miss cycles 175210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 175311754Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8821 # number of ReadReq accesses(hits+misses) 175411754Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 8858 # number of ReadReq accesses(hits+misses) 175510585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 175610585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 175710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 175810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 175910585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 176011754Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ide 115485 # number of demand (read+write) accesses 176111754Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 115525 # number of demand (read+write) accesses 176210585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 176311754Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 115485 # number of overall (read+write) accesses 176411754Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 115525 # number of overall (read+write) accesses 176510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 176610585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 176710585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 176810585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 176910585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 177010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 177110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 177210585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 177310585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 177410585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 177510585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 177610585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 177710585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 177811680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 137445.945946 # average ReadReq miss latency 177911754Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 217131.399274 # average ReadReq miss latency 178011754Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 216798.551930 # average ReadReq miss latency 178110892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 178210892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency 178311754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::realview.ide 125495.178617 # average WriteLineReq miss latency 178411754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 125495.178617 # average WriteLineReq miss latency 178511680SCurtis.Dunham@arm.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency 178611754Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ide 132494.556046 # average overall miss latency 178711754Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 132495.739494 # average overall miss latency 178811680SCurtis.Dunham@arm.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency 178911754Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ide 132494.556046 # average overall miss latency 179011754Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 132495.739494 # average overall miss latency 179111754Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 46527 # number of cycles access was blocked 179210585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 179311754Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 3437 # number of cycles access was blocked 179410585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 179511754Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 13.537096 # average number of cycles each access was blocked 179610585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 179710726Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 106630 # number of writebacks 179810726Sandreas.hansson@arm.comsystem.iocache.writebacks::total 106630 # number of writebacks 179910585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 180011754Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8821 # number of ReadReq MSHR misses 180111754Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::total 8858 # number of ReadReq MSHR misses 180210585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 180310585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 180410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 180510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 180610585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 180711754Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ide 115485 # number of demand (read+write) MSHR misses 180811754Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::total 115525 # number of demand (read+write) MSHR misses 180910585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 181011754Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ide 115485 # number of overall MSHR misses 181111754Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::total 115525 # number of overall MSHR misses 181211680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3235500 # number of ReadReq MSHR miss cycles 181311754Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1474266073 # number of ReadReq MSHR miss cycles 181411754Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 1477501573 # number of ReadReq MSHR miss cycles 181510892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 181610892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 181711754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8047307820 # number of WriteLineReq MSHR miss cycles 181811754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 8047307820 # number of WriteLineReq MSHR miss cycles 181911680SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3436500 # number of demand (read+write) MSHR miss cycles 182011754Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ide 9521573893 # number of demand (read+write) MSHR miss cycles 182111754Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 9525010393 # number of demand (read+write) MSHR miss cycles 182211680SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3436500 # number of overall MSHR miss cycles 182311754Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ide 9521573893 # number of overall MSHR miss cycles 182411754Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 9525010393 # number of overall MSHR miss cycles 182510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 182610585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 182710585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 182810585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 182910585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 183010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 183110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 183210585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 183310585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 183410585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 183510585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 183610585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 183710585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 183811680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87445.945946 # average ReadReq mshr miss latency 183911754Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 167131.399274 # average ReadReq mshr miss latency 184011754Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 166798.551930 # average ReadReq mshr miss latency 184110892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 184210892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 184311754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75445.396947 # average WriteLineReq mshr miss latency 184411754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 75445.396947 # average WriteLineReq mshr miss latency 184511680SCurtis.Dunham@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency 184611754Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 82448.576811 # average overall mshr miss latency 184711754Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 82449.776178 # average overall mshr miss latency 184811680SCurtis.Dunham@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency 184911754Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 82448.576811 # average overall mshr miss latency 185011754Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 82449.776178 # average overall mshr miss latency 185111754Sandreas.hansson@arm.comsystem.membus.snoop_filter.tot_requests 5129530 # Total number of requests made to the snoop filter. 185211754Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_single_requests 2552281 # Number of requests hitting in the snoop filter with a single holder of the requested data. 185311754Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_multi_requests 3338 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 185411606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 185511606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 185611606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 185711754Sandreas.hansson@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 185811606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadReq 54986 # Transaction distribution 185911754Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 622896 # Transaction distribution 186011606Sandreas.sandberg@arm.comsystem.membus.trans_dist::WriteReq 33703 # Transaction distribution 186111606Sandreas.sandberg@arm.comsystem.membus.trans_dist::WriteResp 33703 # Transaction distribution 186211754Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty 2234356 # Transaction distribution 186311754Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 280040 # Transaction distribution 186411754Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 4640 # Transaction distribution 186511754Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution 186611336Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 8 # Transaction distribution 186711754Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 1342054 # Transaction distribution 186811754Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 1342054 # Transaction distribution 186911754Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 567911 # Transaction distribution 187011754Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 700014 # Transaction distribution 187111754Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 32639 # Transaction distribution 187210892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) 187311201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) 187411606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6900 # Packet count per connected master and slave (bytes) 187511754Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6846190 # Packet count per connected master and slave (bytes) 187611754Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 6975852 # Packet count per connected master and slave (bytes) 187711754Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237668 # Packet count per connected master and slave (bytes) 187811754Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 237668 # Packet count per connected master and slave (bytes) 187911754Sandreas.hansson@arm.comsystem.membus.pkt_count::total 7213520 # Packet count per connected master and slave (bytes) 188010892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) 188111201Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes) 188211606Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13800 # Cumulative packet size per connected master and slave (bytes) 188311754Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 258164108 # Cumulative packet size per connected master and slave (bytes) 188411754Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 258334162 # Cumulative packet size per connected master and slave (bytes) 188511754Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7251648 # Cumulative packet size per connected master and slave (bytes) 188611754Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7251648 # Cumulative packet size per connected master and slave (bytes) 188711754Sandreas.hansson@arm.comsystem.membus.pkt_size::total 265585810 # Cumulative packet size per connected master and slave (bytes) 188811754Sandreas.hansson@arm.comsystem.membus.snoops 35487 # Total snoops (count) 188911754Sandreas.hansson@arm.comsystem.membus.snoopTraffic 181760 # Total snoop traffic (bytes) 189011754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 2703311 # Request fanout histogram 189111754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0.013318 # Request fanout histogram 189211754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0.114632 # Request fanout histogram 189310515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 189411754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 2667309 98.67% 98.67% # Request fanout histogram 189511754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 36002 1.33% 100.00% # Request fanout histogram 189610515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 189710515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 189811606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 189910515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 190011754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 2703311 # Request fanout histogram 190111754Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 104009500 # Layer occupancy (ticks) 190210515SAli.Saidi@ARM.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 190311441Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 32500 # Layer occupancy (ticks) 190410515SAli.Saidi@ARM.comsystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 190511754Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 5608500 # Layer occupancy (ticks) 190610515SAli.Saidi@ARM.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 190711754Sandreas.hansson@arm.comsystem.membus.reqLayer5.occupancy 14476553313 # Layer occupancy (ticks) 190810585Sandreas.hansson@arm.comsystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 190911754Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 10180600996 # Layer occupancy (ticks) 191010515SAli.Saidi@ARM.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 191111754Sandreas.hansson@arm.comsystem.membus.respLayer3.occupancy 79038203 # Layer occupancy (ticks) 191210515SAli.Saidi@ARM.comsystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 191311754Sandreas.hansson@arm.comsystem.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 191411754Sandreas.hansson@arm.comsystem.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 191511754Sandreas.hansson@arm.comsystem.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 191611754Sandreas.hansson@arm.comsystem.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 191711754Sandreas.hansson@arm.comsystem.realview.gic.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 191811754Sandreas.hansson@arm.comsystem.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 191911754Sandreas.hansson@arm.comsystem.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 192011239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 192111239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 192211239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 192311239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 192411239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 192511239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 192611754Sandreas.hansson@arm.comsystem.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 192711754Sandreas.hansson@arm.comsystem.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 192810515SAli.Saidi@ARM.comsystem.realview.ethernet.txBytes 966 # Bytes Transmitted 192910515SAli.Saidi@ARM.comsystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 193010515SAli.Saidi@ARM.comsystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 193110515SAli.Saidi@ARM.comsystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 193210515SAli.Saidi@ARM.comsystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 193310515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 193410515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 193510515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 193610515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 193711606Sandreas.sandberg@arm.comsystem.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) 193810515SAli.Saidi@ARM.comsystem.realview.ethernet.totPackets 3 # Total Packets 193910515SAli.Saidi@ARM.comsystem.realview.ethernet.totBytes 966 # Total Bytes 194010515SAli.Saidi@ARM.comsystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 194111606Sandreas.sandberg@arm.comsystem.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) 194210515SAli.Saidi@ARM.comsystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 194310515SAli.Saidi@ARM.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 194410515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 194510515SAli.Saidi@ARM.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 194610515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 194710515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 194810515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 194910515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 195010515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 195110515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 195210515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 195310515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 195410515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 195510515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 195610515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 195710515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 195810515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 195910515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 196010515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 196110515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 196210515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 196310515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 196410515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 196510515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 196610515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 196710515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 196810515SAli.Saidi@ARM.comsystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 196910515SAli.Saidi@ARM.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 197011754Sandreas.hansson@arm.comsystem.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 197111754Sandreas.hansson@arm.comsystem.realview.ide.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 197211754Sandreas.hansson@arm.comsystem.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 197311754Sandreas.hansson@arm.comsystem.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 197411754Sandreas.hansson@arm.comsystem.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 197511754Sandreas.hansson@arm.comsystem.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 197611754Sandreas.hansson@arm.comsystem.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 197711239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 197811239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 197911239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 198011239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 198111754Sandreas.hansson@arm.comsystem.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 198211754Sandreas.hansson@arm.comsystem.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 198311754Sandreas.hansson@arm.comsystem.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 198411754Sandreas.hansson@arm.comsystem.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 198511754Sandreas.hansson@arm.comsystem.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 198611754Sandreas.hansson@arm.comsystem.realview.uart.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 198711754Sandreas.hansson@arm.comsystem.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 198811754Sandreas.hansson@arm.comsystem.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 198911754Sandreas.hansson@arm.comsystem.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 199011754Sandreas.hansson@arm.comsystem.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 199111754Sandreas.hansson@arm.comsystem.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 199211754Sandreas.hansson@arm.comsystem.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states 199310515SAli.Saidi@ARM.comsystem.cpu.kern.inst.arm 0 # number of arm instructions executed 199411754Sandreas.hansson@arm.comsystem.cpu.kern.inst.quiesce 17163 # number of quiesce instructions executed 199510515SAli.Saidi@ARM.com 199610515SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 1997