xref: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.327143                       # Number of seconds simulated
sim_ticks                                51327142820000                       # Number of ticks simulated
final_tick                               51327142820000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 147527                       # Simulator instruction rate (inst/s)
host_op_rate                                   173346                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             8926963197                       # Simulator tick rate (ticks/s)
host_mem_usage                                 681308                       # Number of bytes of host memory used
host_seconds                                  5749.68                       # Real time elapsed on the host
sim_insts                                   848230502                       # Number of instructions simulated
sim_ops                                     996685945                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.dtb.walker       227712                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker       212864                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           5673056                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          41642312                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        444928                       # Number of bytes read from this memory
system.physmem.bytes_read::total             48200872                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      5673056                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         5673056                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     68445056                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
system.physmem.bytes_written::total          68465636                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker         3558                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker         3326                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst             104594                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             650674                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6952                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                769104                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1069454                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1072027                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker           4436                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker           4147                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               110527                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data               811312                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             8668                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                  939091                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          110527                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             110527                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1333506                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data                 401                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1333907                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1333506                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          4436                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker          4147                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              110527                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data              811713                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            8668                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2272998                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        769104                       # Number of read requests accepted
system.physmem.writeReqs                      1072027                       # Number of write requests accepted
system.physmem.readBursts                      769104                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1072027                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 49176064                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     46592                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  68464384                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  48200872                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               68465636                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      728                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2250                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               44564                       # Per bank write bursts
system.physmem.perBankRdBursts::1               52315                       # Per bank write bursts
system.physmem.perBankRdBursts::2               47721                       # Per bank write bursts
system.physmem.perBankRdBursts::3               44538                       # Per bank write bursts
system.physmem.perBankRdBursts::4               44659                       # Per bank write bursts
system.physmem.perBankRdBursts::5               50872                       # Per bank write bursts
system.physmem.perBankRdBursts::6               46439                       # Per bank write bursts
system.physmem.perBankRdBursts::7               47959                       # Per bank write bursts
system.physmem.perBankRdBursts::8               44018                       # Per bank write bursts
system.physmem.perBankRdBursts::9               71274                       # Per bank write bursts
system.physmem.perBankRdBursts::10              43972                       # Per bank write bursts
system.physmem.perBankRdBursts::11              51692                       # Per bank write bursts
system.physmem.perBankRdBursts::12              45026                       # Per bank write bursts
system.physmem.perBankRdBursts::13              46672                       # Per bank write bursts
system.physmem.perBankRdBursts::14              42515                       # Per bank write bursts
system.physmem.perBankRdBursts::15              44140                       # Per bank write bursts
system.physmem.perBankWrBursts::0               64758                       # Per bank write bursts
system.physmem.perBankWrBursts::1               69412                       # Per bank write bursts
system.physmem.perBankWrBursts::2               67623                       # Per bank write bursts
system.physmem.perBankWrBursts::3               66442                       # Per bank write bursts
system.physmem.perBankWrBursts::4               66817                       # Per bank write bursts
system.physmem.perBankWrBursts::5               69740                       # Per bank write bursts
system.physmem.perBankWrBursts::6               65132                       # Per bank write bursts
system.physmem.perBankWrBursts::7               69008                       # Per bank write bursts
system.physmem.perBankWrBursts::8               65482                       # Per bank write bursts
system.physmem.perBankWrBursts::9               70623                       # Per bank write bursts
system.physmem.perBankWrBursts::10              64235                       # Per bank write bursts
system.physmem.perBankWrBursts::11              70444                       # Per bank write bursts
system.physmem.perBankWrBursts::12              64965                       # Per bank write bursts
system.physmem.perBankWrBursts::13              66804                       # Per bank write bursts
system.physmem.perBankWrBursts::14              64273                       # Per bank write bursts
system.physmem.perBankWrBursts::15              63998                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          34                       # Number of times write queue was full causing retry
system.physmem.totGap                    51327141408500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
system.physmem.readPktSize::4                   21272                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  747819                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1069454                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    515353                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    203905                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     30484                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     12938                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       574                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       579                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       553                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      1284                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       806                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       364                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      401                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      183                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      172                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      141                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      125                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      125                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      111                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      106                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       94                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       69                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        9                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    26806                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    32475                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    49254                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    54613                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    60437                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    61007                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    61838                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    62183                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    62151                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    69842                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    64006                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    76985                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    62423                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    65026                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    68511                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    60500                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    59306                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    57192                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     3147                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     1524                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     1240                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      919                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      939                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      829                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      673                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      609                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      591                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      462                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      293                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      314                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      359                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      262                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      302                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      251                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      241                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      318                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      215                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      262                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      145                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      182                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      155                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      167                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      131                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      121                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      143                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      131                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      126                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       82                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       74                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       471870                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      249.306089                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     149.569568                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     290.567780                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         207742     44.03%     44.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       122462     25.95%     69.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        42886      9.09%     79.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        22733      4.82%     83.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        14982      3.18%     87.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         9606      2.04%     89.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         7566      1.60%     90.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         6003      1.27%     91.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        37890      8.03%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         471870                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         54238                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        14.166341                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev       76.651597                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511           54233     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-1023            2      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1535            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::13824-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           54238                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         54238                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        19.723367                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.775784                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        8.950161                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           40620     74.89%     74.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23            4585      8.45%     83.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27            5200      9.59%     92.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31            1381      2.55%     95.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             413      0.76%     96.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             235      0.43%     96.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             311      0.57%     97.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47             127      0.23%     97.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51             390      0.72%     98.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55             127      0.23%     98.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              50      0.09%     98.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              65      0.12%     98.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             327      0.60%     99.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              36      0.07%     99.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              29      0.05%     99.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79             111      0.20%     99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83             166      0.31%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               3      0.01%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               3      0.01%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               1      0.00%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               1      0.00%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.00%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.00%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             2      0.00%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             2      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             1      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             5      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            17      0.03%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             2      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147            12      0.02%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             5      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183             2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::212-215             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           54238                       # Writes before turning the bus around for reads
system.physmem.totQLat                    15209667379                       # Total ticks spent queuing
system.physmem.totMemAccLat               29616717379                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   3841880000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       19794.56                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  38544.56                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           0.96                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.33                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        0.94                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.33                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        23.49                       # Average write queue length when enqueuing
system.physmem.readRowHits                     580662                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    785598                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   75.57                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.44                       # Row buffer hit rate for writes
system.physmem.avgGap                     27878049.64                       # Average gap between requests
system.physmem.pageHitRate                      74.33                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 1803657240                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  984138375                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                2956722600                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               3492279360                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3352439216880                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1235640856320                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           29712388110000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             34309704980775                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.451533                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   49429181288166                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1713925980000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    184032075584                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 1763679960                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  962325375                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                3036563400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               3439739520                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3352439216880                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1235034526230                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           29712919978500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             34309596029865                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.449411                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   49430060847495                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1713925980000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    183155359005                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu.inst          384                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           420                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst          384                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          384                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             29                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst             7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.data             1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst            7                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu.branchPred.lookups               225047911                       # Number of BP lookups
system.cpu.branchPred.condPredicted         149825196                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          12305756                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            158986930                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                98148773                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             61.733863                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                30878370                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             343644                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups         6734089                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits            4745857                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses          1988232                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted       765703                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks                    948773                       # Table walker walks requested
system.cpu.dtb.walker.walksLong                948773                       # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walksLongTerminationLevel::Level2        15596                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksLongTerminationLevel::Level3       155468                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksSquashedBefore       437937                       # Table walks squashed before starting
system.cpu.dtb.walker.walkWaitTime::samples       510836                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::mean  2285.186439                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::stdev 14758.274331                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0-65535       507265     99.30%     99.30% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::65536-131071         2025      0.40%     99.70% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::131072-196607         1066      0.21%     99.91% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::196608-262143          211      0.04%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::262144-327679          145      0.03%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::327680-393215           26      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::393216-458751           51      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::458752-524287           43      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::524288-589823            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::655360-720895            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total       510836                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples       488329                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 23221.803333                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 18175.804190                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 21042.780895                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-65535       476828     97.64%     97.64% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::65536-131071         7891      1.62%     99.26% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-196607         2533      0.52%     99.78% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::196608-262143          229      0.05%     99.83% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-327679          568      0.12%     99.94% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::327680-393215          131      0.03%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::393216-458751          114      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::458752-524287           26      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::524288-589823            6      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total       488329                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples 779668986876                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::mean     0.725199                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::stdev     0.523523                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0-1  777411937376     99.71%     99.71% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::2-3    1169683000      0.15%     99.86% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::4-5     513347500      0.07%     99.93% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::6-7     208116000      0.03%     99.95% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::8-9     157188000      0.02%     99.97% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::10-11    121226500      0.02%     99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::12-13     32342000      0.00%     99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::14-15     52541000      0.01%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::16-17      2605500      0.00%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total 779668986876                       # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K        155469     90.88%     90.88% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::2M         15596      9.12%    100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total       171065                       # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       948773                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total       948773                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       171065                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total       171065                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total      1119838                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                    169411407                       # DTB read hits
system.cpu.dtb.read_misses                     675369                       # DTB read misses
system.cpu.dtb.write_hits                   147344334                       # DTB write hits
system.cpu.dtb.write_misses                    273404                       # DTB write misses
system.cpu.dtb.flush_tlb                           10                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid               39385                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                    1019                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                    71963                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                       101                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                  10047                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                     69388                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                170086776                       # DTB read accesses
system.cpu.dtb.write_accesses               147617738                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                         316755741                       # DTB hits
system.cpu.dtb.misses                          948773                       # DTB misses
system.cpu.dtb.accesses                     317704514                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks                    162181                       # Table walker walks requested
system.cpu.itb.walker.walksLong                162181                       # Table walker walks initiated with long descriptors
system.cpu.itb.walker.walksLongTerminationLevel::Level2         1496                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksLongTerminationLevel::Level3       120027                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksSquashedBefore        17971                       # Table walks squashed before starting
system.cpu.itb.walker.walkWaitTime::samples       144210                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::mean  1137.740101                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::stdev  9342.723838                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0-32767       143038     99.19%     99.19% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::32768-65535          619      0.43%     99.62% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::65536-98303           86      0.06%     99.68% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::98304-131071          189      0.13%     99.81% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::131072-163839          221      0.15%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::163840-196607           35      0.02%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::196608-229375            6      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::229376-262143            8      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::262144-294911            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::294912-327679            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::327680-360447            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::360448-393215            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::393216-425983            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total       144210                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples       139494                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 29066.088864                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 24052.553358                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 24213.231696                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-65535       136396     97.78%     97.78% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::65536-131071          707      0.51%     98.29% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-196607         1985      1.42%     99.71% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::196608-262143          151      0.11%     99.82% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::262144-327679          171      0.12%     99.94% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::327680-393215           34      0.02%     99.96% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::393216-458751           34      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::458752-524287            9      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::524288-589823            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total       139494                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples 676589720772                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::mean     0.947980                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::stdev     0.222341                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0     35236838356      5.21%      5.21% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::1    641313182416     94.79%     99.99% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::2        39010000      0.01%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::3          686000      0.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::4            4000      0.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total 676589720772                       # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K        120027     98.77%     98.77% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::2M          1496      1.23%    100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total       121523                       # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       162181                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total       162181                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       121523                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total       121523                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total       283704                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                    357038073                       # ITB inst hits
system.cpu.itb.inst_misses                     162181                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           10                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid               39385                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                    1019                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                    52848                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                    357344                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                357200254                       # ITB inst accesses
system.cpu.itb.hits                         357038073                       # DTB hits
system.cpu.itb.misses                          162181                       # DTB misses
system.cpu.itb.accesses                     357200254                       # DTB accesses
system.cpu.numPwrStateTransitions               32228                       # Number of power state transitions
system.cpu.pwrStateClkGateDist::samples         16114                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::mean     3134631677.512784                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::stdev    60494120707.852806                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::underflows         6793     42.16%     42.16% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1000-5e+10         9285     57.62%     99.78% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::5e+10-1e+11            5      0.03%     99.81% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1e+11-1.5e+11            4      0.02%     99.83% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1.5e+11-2e+11            1      0.01%     99.84% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2e+11-2.5e+11            2      0.01%     99.85% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2.5e+11-3e+11            1      0.01%     99.86% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::3e+11-3.5e+11            2      0.01%     99.87% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::5e+11-5.5e+11            2      0.01%     99.88% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::7e+11-7.5e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::overflows           18      0.11%    100.00% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::max_value 1988780762168                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::total           16114                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateResidencyTicks::ON    815687968559                       # Cumulative time (in ticks) in various power states
system.cpu.pwrStateResidencyTicks::CLK_GATED 50511454851441                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                       1631385344                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles          646877625                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     1002761410                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   225047911                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          133773000                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     898188451                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                26266186                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                    3841497                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles                30548                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles       8722394                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles      1026877                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles         1034                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 356664988                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               6247416                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                   47904                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples         1571821519                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.747042                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.149310                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0               1014113227     64.52%     64.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                214297646     13.63%     78.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 70312417      4.47%     82.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                273098229     17.37%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total           1571821519                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.137949                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.614669                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                526332322                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             552246914                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 434136742                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              49729183                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                9376358                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             33563941                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred               3814299                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts             1086052117                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts              29449193                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                9376358                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                571289803                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                66024800                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles      371545208                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 438989582                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles             114595768                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             1065754363                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts               6907795                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents               5097238                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 334375                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                 639506                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents               63573833                       # Number of times rename has blocked due to SQ full
system.cpu.rename.FullRegisterEvents            20465                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands          1013430764                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1640279788                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1259572075                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups           1474026                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             947250209                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 66180552                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts           26901106                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts       23243208                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 101784051                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            173837388                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           150829276                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           9883117                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          9014861                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 1030729252                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded            27201158                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                1045808358                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           3377405                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        61244461                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     34071399                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         308913                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples    1571821519                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.665348                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        0.919634                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           924230442     58.80%     58.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           334342298     21.27%     80.07% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           234750151     14.93%     95.01% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            72048277      4.58%     99.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             6430828      0.41%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5               19523      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total      1571821519                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                57691324     35.03%     35.03% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                 100152      0.06%     35.09% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                   26730      0.02%     35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc              622      0.00%     35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               44285841     26.89%     62.00% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite              62576075     38.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                11      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             720343690     68.88%     68.88% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult              2530628      0.24%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                122776      0.01%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                 375      0.00%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               8      0.00%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp              15      0.00%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt              23      0.00%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc         119191      0.01%     69.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     69.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     69.14% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            173490543     16.59%     85.73% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           149201098     14.27%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             1045808358                       # Type of FU issued
system.cpu.iq.rate                           0.641055                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                   164680744                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.157467                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         3829023509                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        1118377930                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   1027460456                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads             2472874                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes             938610                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses       909796                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             1208933693                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                 1555398                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          4274316                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     14173969                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        14495                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       142953                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      6059351                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      2526453                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked       1440750                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                9376358                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 7004216                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               6913167                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          1058165202                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             173837388                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            150829276                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts           22819114                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                  57849                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents               6781828                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         142953                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        3462734                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      5495013                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              8957747                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            1034296660                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             169399584                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          10573772                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                        234792                       # number of nop insts executed
system.cpu.iew.exec_refs                    316739180                       # number of memory reference insts executed
system.cpu.iew.exec_branches                196198672                       # Number of branches executed
system.cpu.iew.exec_stores                  147339596                       # Number of stores executed
system.cpu.iew.exec_rate                     0.633999                       # Inst execution rate
system.cpu.iew.wb_sent                     1029187818                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    1028370252                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 437853372                       # num instructions producing a value
system.cpu.iew.wb_consumers                 708400240                       # num instructions consuming a value
system.cpu.iew.wb_rate                       0.630366                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.618088                       # average fanout of values written-back
system.cpu.commit.commitSquashedInsts        51884426                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls        26892245                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           8549021                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples   1559762540                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.638999                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.273827                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0   1047991029     67.19%     67.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    288035307     18.47%     85.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2    120100080      7.70%     93.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     36659789      2.35%     95.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     28506606      1.83%     97.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     13942789      0.89%     98.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      8651847      0.55%     98.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      4181084      0.27%     99.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     11694009      0.75%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total   1559762540                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            848230502                       # Number of instructions committed
system.cpu.commit.committedOps              996685945                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      304433343                       # Number of memory references committed
system.cpu.commit.loads                     159663418                       # Number of loads committed
system.cpu.commit.membars                     6927415                       # Number of memory barriers committed
system.cpu.commit.branches                  189324067                       # Number of branches committed
system.cpu.commit.fp_insts                     898712                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 915721971                       # Number of committed integer instructions.
system.cpu.commit.function_calls             25285288                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        689893101     69.22%     69.22% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult         2149376      0.22%     69.43% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv            98151      0.01%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            8      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp           13      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt           21      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc       111932      0.01%     69.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     69.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.46% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead       159663418     16.02%     85.47% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite      144769925     14.53%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         996685945                       # Class of committed instruction
system.cpu.commit.bw_lim_events              11694009                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                   2589097882                       # The number of ROB reads
system.cpu.rob.rob_writes                  2109106528                       # The number of ROB writes
system.cpu.timesIdled                         8171713                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        59563825                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                 101022900419                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                   848230502                       # Number of Instructions Simulated
system.cpu.committedOps                     996685945                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               1.923281                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.923281                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.519945                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.519945                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1223820104                       # number of integer regfile reads
system.cpu.int_regfile_writes               731394790                       # number of integer regfile writes
system.cpu.fp_regfile_reads                   1462803                       # number of floating regfile reads
system.cpu.fp_regfile_writes                   780644                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 225050166                       # number of cc regfile reads
system.cpu.cc_regfile_writes                225684828                       # number of cc regfile writes
system.cpu.misc_regfile_reads              2558325337                       # number of misc regfile reads
system.cpu.misc_regfile_writes               26931155                       # number of misc regfile writes
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements           9701158                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.972800                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           283187639                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           9701670                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             29.189577                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        2743199500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.972800                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999947                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999947                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           97                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          392                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           23                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1237018765                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1237018765                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data    147199934                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       147199934                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    128255410                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      128255410                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data       377663                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total        377663                       # number of SoftPFReq hits
system.cpu.dcache.WriteLineReq_hits::cpu.data       323814                       # number of WriteLineReq hits
system.cpu.dcache.WriteLineReq_hits::total       323814                       # number of WriteLineReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      3295431                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      3295431                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      3691256                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      3691256                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     275779158                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        275779158                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    276156821                       # number of overall hits
system.cpu.dcache.overall_hits::total       276156821                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      9580915                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       9580915                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data     11254027                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total     11254027                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data      1170464                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total      1170464                       # number of SoftPFReq misses
system.cpu.dcache.WriteLineReq_misses::cpu.data      1233639                       # number of WriteLineReq misses
system.cpu.dcache.WriteLineReq_misses::total      1233639                       # number of WriteLineReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data       446709                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total       446709                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            8                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            8                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data     22068581                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total       22068581                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data     23239045                       # number of overall misses
system.cpu.dcache.overall_misses::total      23239045                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 168767240000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 168767240000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 444298934810                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 444298934810                       # number of WriteReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  52375248289                       # number of WriteLineReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::total  52375248289                       # number of WriteLineReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   6883962000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total   6883962000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       380500                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       380500                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 665441423099                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 665441423099                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 665441423099                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 665441423099                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    156780849                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    156780849                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    139509437                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    139509437                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data      1548127                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total      1548127                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::cpu.data      1557453                       # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::total      1557453                       # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3742140                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      3742140                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      3691264                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      3691264                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    297847739                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    297847739                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    299395866                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    299395866                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.061110                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.061110                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080669                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.080669                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.756052                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.756052                       # miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.792087                       # miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::total     0.792087                       # miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.119373                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.119373                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000002                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000002                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.074093                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.074093                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.077620                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.077620                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17614.939700                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17614.939700                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39479.106884                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 39479.106884                       # average WriteReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 42455.895354                       # average WriteLineReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::total 42455.895354                       # average WriteLineReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15410.394686                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15410.394686                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 47562.500000                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 47562.500000                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 30153.339859                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 30153.339859                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 28634.628622                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 28634.628622                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs     32224409                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs           1601607                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    20.120048                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks      7504086                       # number of writebacks
system.cpu.dcache.writebacks::total           7504086                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4456599                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      4456599                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      9250788                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      9250788                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data         7056                       # number of WriteLineReq MSHR hits
system.cpu.dcache.WriteLineReq_mshr_hits::total         7056                       # number of WriteLineReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       219268                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total       219268                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data     13714443                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total     13714443                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data     13714443                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total     13714443                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5124316                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      5124316                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2003239                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      2003239                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1163648                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total      1163648                       # number of SoftPFReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1226583                       # number of WriteLineReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::total      1226583                       # number of WriteLineReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       227441                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total       227441                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            8                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            8                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      8354138                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      8354138                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      9517786                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      9517786                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33678                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total        33678                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33696                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67374                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total        67374                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  84959954500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  84959954500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  77558080846                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  77558080846                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  23723735000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  23723735000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  50708992789                       # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  50708992789                       # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3202218000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3202218000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       372500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       372500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 213227028135                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 213227028135                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 236950763135                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 236950763135                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6192056000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6192056000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6192056000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total   6192056000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032685                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032685                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014359                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014359                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.751649                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.751649                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.787557                       # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.787557                       # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.060778                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.060778                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000002                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.028048                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.028048                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.031790                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.031790                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16579.764890                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16579.764890                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38716.339311                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38716.339311                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20387.380892                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20387.380892                       # average SoftPFReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 41341.672589                       # average WriteLineReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 41341.672589                       # average WriteLineReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14079.334860                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14079.334860                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 46562.500000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 46562.500000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25523.522371                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25523.522371                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24895.575834                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 24895.575834                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183860.561791                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183860.561791                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91905.720308                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91905.720308                       # average overall mshr uncacheable latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements          15134592                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.928988                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           340756209                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs          15135104                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             22.514296                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       20447572500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.928988                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.999861                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.999861                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          124                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          299                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           89                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         371779021                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        371779021                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst    340756209                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       340756209                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     340756209                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        340756209                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    340756209                       # number of overall hits
system.cpu.icache.overall_hits::total       340756209                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst     15887482                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total      15887482                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst     15887482                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total       15887482                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst     15887482                       # number of overall misses
system.cpu.icache.overall_misses::total      15887482                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 214918228873                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 214918228873                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 214918228873                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 214918228873                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 214918228873                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 214918228873                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    356643691                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    356643691                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    356643691                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    356643691                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    356643691                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    356643691                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.044547                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.044547                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.044547                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.044547                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.044547                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.044547                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13527.519897                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13527.519897                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13527.519897                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13527.519897                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13527.519897                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13527.519897                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs        24649                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs              1517                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    16.248517                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks     15134592                       # number of writebacks
system.cpu.icache.writebacks::total          15134592                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst       752151                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total       752151                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst       752151                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total       752151                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst       752151                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total       752151                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst     15135331                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total     15135331                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst     15135331                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total     15135331                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst     15135331                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total     15135331                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        21294                       # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total        21294                       # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        21294                       # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total        21294                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192625378387                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 192625378387                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192625378387                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 192625378387                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192625378387                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 192625378387                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   2684938500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   2684938500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   2684938500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total   2684938500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.042438                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.042438                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.042438                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.042438                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.042438                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.042438                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12726.869230                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12726.869230                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12726.869230                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12726.869230                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12726.869230                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12726.869230                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126088.968724                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126088.968724                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126088.968724                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126088.968724                       # average overall mshr uncacheable latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements          1148622                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65301.900403                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs           46289210                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          1211379                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            38.211996                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle       4512200500                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 37189.560843                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   293.778433                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   476.562000                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  7800.369043                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 19541.630085                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.567468                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004483                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.007272                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.119024                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.298182                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.996428                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023          234                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        62523                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4          234                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           67                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          564                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2712                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5162                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54018                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.003571                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.954025                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        410396361                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       410396361                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       787478                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       297374                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1084852                       # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks      7504086                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total      7504086                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks     15131991                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total     15131991                       # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data         9360                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total         9360                       # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            4                       # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total            4                       # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1568311                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1568311                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     15051780                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total     15051780                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6254855                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      6254855                       # number of ReadSharedReq hits
system.cpu.l2cache.InvalidateReq_hits::cpu.data       727039                       # number of InvalidateReq hits
system.cpu.l2cache.InvalidateReq_hits::total       727039                       # number of InvalidateReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker       787478                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker       297374                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst     15051780                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      7823166                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total        23959798                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker       787478                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker       297374                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst     15051780                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      7823166                       # number of overall hits
system.cpu.l2cache.overall_hits::total       23959798                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         3559                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         3326                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total         6885                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data        34185                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total        34185                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            4                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            4                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       394921                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       394921                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        83338                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        83338                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data       257015                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total       257015                       # number of ReadSharedReq misses
system.cpu.l2cache.InvalidateReq_misses::cpu.data       499544                       # number of InvalidateReq misses
system.cpu.l2cache.InvalidateReq_misses::total       499544                       # number of InvalidateReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker         3559                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker         3326                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        83338                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       651936                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        742159                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker         3559                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker         3326                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        83338                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       651936                       # number of overall misses
system.cpu.l2cache.overall_misses::total       742159                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    491952000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    462404000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total    954356000                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data   1389212000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total   1389212000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       239000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total       239000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  55032106500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  55032106500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst  11239521500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total  11239521500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  35839167500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total  35839167500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data      7495000                       # number of InvalidateReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::total      7495000                       # number of InvalidateReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    491952000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    462404000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst  11239521500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  90871274000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 103065151500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    491952000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    462404000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst  11239521500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  90871274000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 103065151500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       791037                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       300700                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1091737                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::writebacks      7504086                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total      7504086                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks     15131991                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total     15131991                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data        43545                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total        43545                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            8                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            8                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      1963232                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      1963232                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     15135118                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total     15135118                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      6511870                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      6511870                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1226583                       # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::total      1226583                       # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker       791037                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker       300700                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst     15135118                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      8475102                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total     24701957                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker       791037                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker       300700                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst     15135118                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      8475102                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total     24701957                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.004499                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.011061                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.006306                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.785050                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.785050                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.500000                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.500000                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.201159                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.201159                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005506                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005506                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.039469                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.039469                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.407265                       # miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::total     0.407265                       # miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.004499                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.011061                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005506                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.076924                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.030045                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.004499                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.011061                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005506                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.076924                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.030045                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 138227.592020                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 139027.059531                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 138613.798112                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 40638.057628                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 40638.057628                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        59750                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        59750                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 139349.658539                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 139349.658539                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134866.705464                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134866.705464                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 139443.874871                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 139443.874871                       # average ReadSharedReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data    15.003683                       # average InvalidateReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::total    15.003683                       # average InvalidateReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 138227.592020                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 139027.059531                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134866.705464                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 139386.801772                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 138872.063129                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 138227.592020                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 139027.059531                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134866.705464                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 139386.801772                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 138872.063129                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks       962824                       # number of writebacks
system.cpu.l2cache.writebacks::total           962824                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.dtb.walker            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           21                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total           21                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.dtb.walker            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           21                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           22                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.dtb.walker            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           21                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           22                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         3558                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         3326                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total         6884                       # number of ReadReq MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            1                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total            1                       # number of CleanEvict MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        34185                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total        34185                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            4                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            4                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       394921                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       394921                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        83338                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        83338                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       256994                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total       256994                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       499544                       # number of InvalidateReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::total       499544                       # number of InvalidateReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         3558                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         3326                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        83338                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       651915                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       742137                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         3558                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         3326                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        83338                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       651915                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       742137                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        21294                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33678                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total        54972                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        33696                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        21294                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67374                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total        88668                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    456305510                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    429144000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total    885449510                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   2325232000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   2325232000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       277500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       277500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  51081891916                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  51081891916                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst  10406063168                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total  10406063168                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  33266030305                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  33266030305                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  34915200500                       # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  34915200500                       # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    456305510                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    429144000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  10406063168                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  84347922221                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  95639434899                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    456305510                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    429144000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  10406063168                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  84347922221                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  95639434899                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   2418763500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5770936000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8189699500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   2418763500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5770936000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   8189699500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.004498                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.011061                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.006306                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.785050                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.785050                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.500000                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.201159                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.201159                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005506                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005506                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.039465                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.039465                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.407265                       # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.407265                       # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.004498                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.011061                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005506                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.076921                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.030044                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.004498                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.011061                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005506                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.076921                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.030044                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 128247.754356                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 129027.059531                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 128624.275131                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68019.072693                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68019.072693                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        69375                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        69375                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129347.114780                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129347.114780                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124865.765533                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124865.765533                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 129442.828646                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 129442.828646                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69894.144460                       # average InvalidateReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69894.144460                       # average InvalidateReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128247.754356                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 129027.059531                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124865.765533                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 129384.846523                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128870.322998                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128247.754356                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 129027.059531                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124865.765533                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129384.846523                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128870.322998                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.968724                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171356.256310                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148979.471367                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.968724                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85655.237926                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 92363.643028                       # average overall mshr uncacheable latency
system.cpu.toL2Bus.snoop_filter.tot_requests     50407203                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests     25570213                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3413                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         2115                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2115                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq        1618708                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp      23266675                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         33696                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        33696                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty      8573574                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean     15134592                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict      2391693                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq        43548                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            8                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp        43556                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      1963232                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      1963232                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq     15135331                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      6520715                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq      1333247                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateResp      1226583                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     45447628                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     29327152                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       726647                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1928826                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          77430253                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1937602080                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1022907422                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2405600                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6328296                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total         2969243398                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                     1852603                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic              72285944                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples     27912596                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.024958                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.155996                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0           27215961     97.50%     97.50% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1             696635      2.50%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       27912596                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy    48339894491                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy      1459384                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy   22733591738                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   13401353655                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy     426266814                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy    1138134788                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                40293                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40293                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230944                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       230944                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353728                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334208                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334208                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492128                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             41884500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                11500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               345000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 9500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                 9500                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               14500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            25117000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            36500500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           567323274                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147704000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements               115453                       # number of replacements
system.iocache.tags.tagsinuse               10.423128                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115469                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13098782503000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.544201                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     6.878927                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.221513                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.429933                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.651446                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039605                       # Number of tag accesses
system.iocache.tags.data_accesses             1039605                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8808                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8845                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide       115472                       # number of demand (read+write) misses
system.iocache.demand_misses::total            115512                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide       115472                       # number of overall misses
system.iocache.overall_misses::total           115512                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5076000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1670063987                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1675139987                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  13414774287                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  13414774287                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5427000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide  15084838274                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  15090265274                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5427000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide  15084838274                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  15090265274                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8808                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8845                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide       115472                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total          115512                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide       115472                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total         115512                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137189.189189                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 189607.627952                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 189388.353533                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125766.653107                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 125766.653107                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       135675                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 130636.329794                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 130638.074607                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       135675                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 130636.329794                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 130638.074607                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         33964                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3510                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.676353                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks          106630                       # number of writebacks
system.iocache.writebacks::total               106630                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8808                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8845                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide       115472                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total       115512                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide       115472                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total       115512                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3226000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1229663987                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1232889987                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8076516803                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   8076516803                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3427000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   9306180790                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   9309607790                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3427000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   9306180790                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   9309607790                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87189.189189                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139607.627952                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 139388.353533                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75719.238009                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75719.238009                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85675                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 80592.531436                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 80594.291416                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85675                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 80592.531436                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 80594.291416                       # average overall mshr miss latency
system.membus.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               54972                       # Transaction distribution
system.membus.trans_dist::ReadResp             411033                       # Transaction distribution
system.membus.trans_dist::WriteReq              33696                       # Transaction distribution
system.membus.trans_dist::WriteResp             33696                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1069454                       # Transaction distribution
system.membus.trans_dist::CleanEvict           193565                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            34895                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              4                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               8                       # Transaction distribution
system.membus.trans_dist::ReadExReq            394310                       # Transaction distribution
system.membus.trans_dist::ReadExResp           394310                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        356061                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        606112                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6858                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3212019                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3341639                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237917                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       237917                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                3579556                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          420                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13716                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    109397260                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total    109567230                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7269248                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7269248                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               116836478                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             2560                       # Total snoops (count)
system.membus.snoopTraffic                     163328                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples           2743103                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 2743103    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             2743103                       # Request fanout histogram
system.membus.reqLayer0.occupancy           103939500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               32500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             5573000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          7172212711                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         4075256665                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           44789891                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    16114                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------