stats.txt revision 11103
110515SAli.Saidi@ARM.com 210515SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 311103Snilay@cs.wisc.edusim_seconds 51.562170 # Number of seconds simulated 411103Snilay@cs.wisc.edusim_ticks 51562169701000 # Number of ticks simulated 511103Snilay@cs.wisc.edufinal_tick 51562169701000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 711103Snilay@cs.wisc.eduhost_inst_rate 82472 # Simulator instruction rate (inst/s) 811103Snilay@cs.wisc.eduhost_op_rate 96938 # Simulator op (including micro ops) rate (op/s) 911103Snilay@cs.wisc.eduhost_tick_rate 3850541751 # Simulator tick rate (ticks/s) 1011103Snilay@cs.wisc.eduhost_mem_usage 726532 # Number of bytes of host memory used 1111103Snilay@cs.wisc.eduhost_seconds 13390.89 # Real time elapsed on the host 1211103Snilay@cs.wisc.edusim_insts 1104366834 # Number of instructions simulated 1311103Snilay@cs.wisc.edusim_ops 1298086167 # Number of ops (including micro ops) simulated 1410515SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611103Snilay@cs.wisc.edusystem.physmem.bytes_read::cpu.dtb.walker 657984 # Number of bytes read from this memory 1711103Snilay@cs.wisc.edusystem.physmem.bytes_read::cpu.itb.walker 557504 # Number of bytes read from this memory 1811103Snilay@cs.wisc.edusystem.physmem.bytes_read::cpu.inst 6634080 # Number of bytes read from this memory 1911103Snilay@cs.wisc.edusystem.physmem.bytes_read::cpu.data 148649160 # Number of bytes read from this memory 2011103Snilay@cs.wisc.edusystem.physmem.bytes_read::realview.ide 417792 # Number of bytes read from this memory 2111103Snilay@cs.wisc.edusystem.physmem.bytes_read::total 156916520 # Number of bytes read from this memory 2211103Snilay@cs.wisc.edusystem.physmem.bytes_inst_read::cpu.inst 6634080 # Number of instructions bytes read from this memory 2311103Snilay@cs.wisc.edusystem.physmem.bytes_inst_read::total 6634080 # Number of instructions bytes read from this memory 2411103Snilay@cs.wisc.edusystem.physmem.bytes_written::writebacks 139624832 # Number of bytes written to this memory 2510585Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory 2611103Snilay@cs.wisc.edusystem.physmem.bytes_written::total 139645412 # Number of bytes written to this memory 2711103Snilay@cs.wisc.edusystem.physmem.num_reads::cpu.dtb.walker 10281 # Number of read requests responded to by this memory 2811103Snilay@cs.wisc.edusystem.physmem.num_reads::cpu.itb.walker 8711 # Number of read requests responded to by this memory 2911103Snilay@cs.wisc.edusystem.physmem.num_reads::cpu.inst 119610 # Number of read requests responded to by this memory 3011103Snilay@cs.wisc.edusystem.physmem.num_reads::cpu.data 2322656 # Number of read requests responded to by this memory 3111103Snilay@cs.wisc.edusystem.physmem.num_reads::realview.ide 6528 # Number of read requests responded to by this memory 3211103Snilay@cs.wisc.edusystem.physmem.num_reads::total 2467786 # Number of read requests responded to by this memory 3311103Snilay@cs.wisc.edusystem.physmem.num_writes::writebacks 2181638 # Number of write requests responded to by this memory 3410585Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory 3511103Snilay@cs.wisc.edusystem.physmem.num_writes::total 2184211 # Number of write requests responded to by this memory 3611103Snilay@cs.wisc.edusystem.physmem.bw_read::cpu.dtb.walker 12761 # Total read bandwidth from this memory (bytes/s) 3711103Snilay@cs.wisc.edusystem.physmem.bw_read::cpu.itb.walker 10812 # Total read bandwidth from this memory (bytes/s) 3811103Snilay@cs.wisc.edusystem.physmem.bw_read::cpu.inst 128662 # Total read bandwidth from this memory (bytes/s) 3911103Snilay@cs.wisc.edusystem.physmem.bw_read::cpu.data 2882911 # Total read bandwidth from this memory (bytes/s) 4011103Snilay@cs.wisc.edusystem.physmem.bw_read::realview.ide 8103 # Total read bandwidth from this memory (bytes/s) 4111103Snilay@cs.wisc.edusystem.physmem.bw_read::total 3043249 # Total read bandwidth from this memory (bytes/s) 4211103Snilay@cs.wisc.edusystem.physmem.bw_inst_read::cpu.inst 128662 # Instruction read bandwidth from this memory (bytes/s) 4311103Snilay@cs.wisc.edusystem.physmem.bw_inst_read::total 128662 # Instruction read bandwidth from this memory (bytes/s) 4411103Snilay@cs.wisc.edusystem.physmem.bw_write::writebacks 2707893 # Write bandwidth from this memory (bytes/s) 4511103Snilay@cs.wisc.edusystem.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s) 4611103Snilay@cs.wisc.edusystem.physmem.bw_write::total 2708292 # Write bandwidth from this memory (bytes/s) 4711103Snilay@cs.wisc.edusystem.physmem.bw_total::writebacks 2707893 # Total bandwidth to/from this memory (bytes/s) 4811103Snilay@cs.wisc.edusystem.physmem.bw_total::cpu.dtb.walker 12761 # Total bandwidth to/from this memory (bytes/s) 4911103Snilay@cs.wisc.edusystem.physmem.bw_total::cpu.itb.walker 10812 # Total bandwidth to/from this memory (bytes/s) 5011103Snilay@cs.wisc.edusystem.physmem.bw_total::cpu.inst 128662 # Total bandwidth to/from this memory (bytes/s) 5111103Snilay@cs.wisc.edusystem.physmem.bw_total::cpu.data 2883310 # Total bandwidth to/from this memory (bytes/s) 5211103Snilay@cs.wisc.edusystem.physmem.bw_total::realview.ide 8103 # Total bandwidth to/from this memory (bytes/s) 5311103Snilay@cs.wisc.edusystem.physmem.bw_total::total 5751541 # Total bandwidth to/from this memory (bytes/s) 5411103Snilay@cs.wisc.edusystem.physmem.readReqs 2467786 # Number of read requests accepted 5511103Snilay@cs.wisc.edusystem.physmem.writeReqs 2184211 # Number of write requests accepted 5611103Snilay@cs.wisc.edusystem.physmem.readBursts 2467786 # Number of DRAM read bursts, including those serviced by the write queue 5711103Snilay@cs.wisc.edusystem.physmem.writeBursts 2184211 # Number of DRAM write bursts, including those merged in the write queue 5811103Snilay@cs.wisc.edusystem.physmem.bytesReadDRAM 157889856 # Total number of bytes read from DRAM 5911103Snilay@cs.wisc.edusystem.physmem.bytesReadWrQ 48448 # Total number of bytes read from write queue 6011103Snilay@cs.wisc.edusystem.physmem.bytesWritten 139644224 # Total number of bytes written to DRAM 6111103Snilay@cs.wisc.edusystem.physmem.bytesReadSys 156916520 # Total read bytes from the system interface side 6211103Snilay@cs.wisc.edusystem.physmem.bytesWrittenSys 139645412 # Total written bytes from the system interface side 6311103Snilay@cs.wisc.edusystem.physmem.servicedByWrQ 757 # Number of DRAM read bursts serviced by the write queue 6411103Snilay@cs.wisc.edusystem.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one 6511103Snilay@cs.wisc.edusystem.physmem.neitherReadNorWriteReqs 155211 # Number of requests that are neither read nor write 6611103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::0 149005 # Per bank write bursts 6711103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::1 156339 # Per bank write bursts 6811103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::2 155955 # Per bank write bursts 6911103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::3 150628 # Per bank write bursts 7011103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::4 148084 # Per bank write bursts 7111103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::5 159303 # Per bank write bursts 7211103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::6 149188 # Per bank write bursts 7311103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::7 152515 # Per bank write bursts 7411103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::8 150862 # Per bank write bursts 7511103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::9 179370 # Per bank write bursts 7611103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::10 150320 # Per bank write bursts 7711103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::11 155893 # Per bank write bursts 7811103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::12 152080 # Per bank write bursts 7911103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::13 155961 # Per bank write bursts 8011103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::14 150556 # Per bank write bursts 8111103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::15 150970 # Per bank write bursts 8211103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::0 132106 # Per bank write bursts 8311103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::1 138501 # Per bank write bursts 8411103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::2 137398 # Per bank write bursts 8511103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::3 135602 # Per bank write bursts 8611103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::4 133392 # Per bank write bursts 8711103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::5 140433 # Per bank write bursts 8811103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::6 132940 # Per bank write bursts 8911103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::7 137025 # Per bank write bursts 9011103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::8 135656 # Per bank write bursts 9111103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::9 141181 # Per bank write bursts 9211103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::10 134433 # Per bank write bursts 9311103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::11 138339 # Per bank write bursts 9411103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::12 136301 # Per bank write bursts 9511103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::13 138853 # Per bank write bursts 9611103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::14 135122 # Per bank write bursts 9711103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::15 134659 # Per bank write bursts 9810515SAli.Saidi@ARM.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 9911103Snilay@cs.wisc.edusystem.physmem.numWrRetry 21 # Number of times write queue was full causing retry 10011103Snilay@cs.wisc.edusystem.physmem.totGap 51562168447500 # Total gap between requests 10110515SAli.Saidi@ARM.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 10210515SAli.Saidi@ARM.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 10310515SAli.Saidi@ARM.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 10410515SAli.Saidi@ARM.comsystem.physmem.readPktSize::3 13 # Read request sizes (log2) 10510515SAli.Saidi@ARM.comsystem.physmem.readPktSize::4 21272 # Read request sizes (log2) 10610515SAli.Saidi@ARM.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 10711103Snilay@cs.wisc.edusystem.physmem.readPktSize::6 2446501 # Read request sizes (log2) 10810515SAli.Saidi@ARM.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 10910515SAli.Saidi@ARM.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 11010515SAli.Saidi@ARM.comsystem.physmem.writePktSize::2 1 # Write request sizes (log2) 11110515SAli.Saidi@ARM.comsystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 11210515SAli.Saidi@ARM.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 11310515SAli.Saidi@ARM.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 11411103Snilay@cs.wisc.edusystem.physmem.writePktSize::6 2181638 # Write request sizes (log2) 11511103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::0 1276105 # What read queue length does an incoming req see 11611103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::1 831313 # What read queue length does an incoming req see 11711103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::2 193469 # What read queue length does an incoming req see 11811103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::3 160610 # What read queue length does an incoming req see 11911103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::4 761 # What read queue length does an incoming req see 12011103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::5 490 # What read queue length does an incoming req see 12111103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::6 489 # What read queue length does an incoming req see 12211103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::7 524 # What read queue length does an incoming req see 12311103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::8 829 # What read queue length does an incoming req see 12411103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::9 946 # What read queue length does an incoming req see 12511103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::10 413 # What read queue length does an incoming req see 12611103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::11 181 # What read queue length does an incoming req see 12711103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::12 164 # What read queue length does an incoming req see 12811103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::13 125 # What read queue length does an incoming req see 12911103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::14 127 # What read queue length does an incoming req see 13011103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::15 120 # What read queue length does an incoming req see 13110892Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 106 # What read queue length does an incoming req see 13211103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::17 102 # What read queue length does an incoming req see 13311103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::18 81 # What read queue length does an incoming req see 13411103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::19 58 # What read queue length does an incoming req see 13511103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see 13611103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see 13711103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see 13811103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::23 3 # What read queue length does an incoming req see 13910515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 14010515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 14110515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 14210515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 14310515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 14410515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 14510515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 14610515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 14710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 14810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 14910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 15010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 15110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 15210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 15310515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 15410515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 15510515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 15610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 15710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 15810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 15910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 16010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 16110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 16211103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::15 20208 # What write queue length does an incoming req see 16311103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::16 23029 # What write queue length does an incoming req see 16411103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::17 68337 # What write queue length does an incoming req see 16511103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::18 107857 # What write queue length does an incoming req see 16611103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::19 119474 # What write queue length does an incoming req see 16711103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::20 131451 # What write queue length does an incoming req see 16811103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::21 131860 # What write queue length does an incoming req see 16911103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::22 135328 # What write queue length does an incoming req see 17011103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::23 136231 # What write queue length does an incoming req see 17111103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::24 138984 # What write queue length does an incoming req see 17211103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::25 139007 # What write queue length does an incoming req see 17311103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::26 140497 # What write queue length does an incoming req see 17411103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::27 136343 # What write queue length does an incoming req see 17511103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::28 166652 # What write queue length does an incoming req see 17611103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::29 162914 # What write queue length does an incoming req see 17711103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::30 137438 # What write queue length does an incoming req see 17811103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::31 145049 # What write queue length does an incoming req see 17911103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::32 131294 # What write queue length does an incoming req see 18011103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::33 1298 # What write queue length does an incoming req see 18111103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::34 600 # What write queue length does an incoming req see 18211103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::35 677 # What write queue length does an incoming req see 18311103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::36 476 # What write queue length does an incoming req see 18411103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::37 374 # What write queue length does an incoming req see 18511103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::38 384 # What write queue length does an incoming req see 18611103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::39 409 # What write queue length does an incoming req see 18711103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::40 493 # What write queue length does an incoming req see 18811103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::41 389 # What write queue length does an incoming req see 18911103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::42 344 # What write queue length does an incoming req see 19011103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::43 343 # What write queue length does an incoming req see 19111103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::44 290 # What write queue length does an incoming req see 19211103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::45 311 # What write queue length does an incoming req see 19311103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::46 367 # What write queue length does an incoming req see 19411103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::47 330 # What write queue length does an incoming req see 19511103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::48 311 # What write queue length does an incoming req see 19611103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::49 290 # What write queue length does an incoming req see 19711103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::50 249 # What write queue length does an incoming req see 19811103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::51 261 # What write queue length does an incoming req see 19911103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::52 293 # What write queue length does an incoming req see 20011103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::53 219 # What write queue length does an incoming req see 20111103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::54 217 # What write queue length does an incoming req see 20211103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::55 239 # What write queue length does an incoming req see 20311103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::56 185 # What write queue length does an incoming req see 20411103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::57 140 # What write queue length does an incoming req see 20511103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::58 114 # What write queue length does an incoming req see 20611103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::59 81 # What write queue length does an incoming req see 20711103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::60 99 # What write queue length does an incoming req see 20811103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::61 114 # What write queue length does an incoming req see 20911103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::62 44 # What write queue length does an incoming req see 21011103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::63 55 # What write queue length does an incoming req see 21111103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::samples 938073 # Bytes accessed per row activation 21211103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::mean 317.175418 # Bytes accessed per row activation 21311103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::gmean 184.850858 # Bytes accessed per row activation 21411103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::stdev 334.830774 # Bytes accessed per row activation 21511103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::0-127 348981 37.20% 37.20% # Bytes accessed per row activation 21611103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::128-255 217922 23.23% 60.43% # Bytes accessed per row activation 21711103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::256-383 89990 9.59% 70.03% # Bytes accessed per row activation 21811103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::384-511 51985 5.54% 75.57% # Bytes accessed per row activation 21911103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::512-639 41514 4.43% 79.99% # Bytes accessed per row activation 22011103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::640-767 28050 2.99% 82.98% # Bytes accessed per row activation 22111103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::768-895 24686 2.63% 85.61% # Bytes accessed per row activation 22211103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::896-1023 20558 2.19% 87.81% # Bytes accessed per row activation 22311103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::1024-1151 114387 12.19% 100.00% # Bytes accessed per row activation 22411103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::total 938073 # Bytes accessed per row activation 22511103Snilay@cs.wisc.edusystem.physmem.rdPerTurnAround::samples 129462 # Reads before turning the bus around for writes 22611103Snilay@cs.wisc.edusystem.physmem.rdPerTurnAround::mean 19.055908 # Reads before turning the bus around for writes 22711103Snilay@cs.wisc.edusystem.physmem.rdPerTurnAround::stdev 183.344638 # Reads before turning the bus around for writes 22811103Snilay@cs.wisc.edusystem.physmem.rdPerTurnAround::0-2047 129459 100.00% 100.00% # Reads before turning the bus around for writes 22910892Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes 23010892Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes 23110892Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::63488-65535 1 0.00% 100.00% # Reads before turning the bus around for writes 23211103Snilay@cs.wisc.edusystem.physmem.rdPerTurnAround::total 129462 # Reads before turning the bus around for writes 23311103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::samples 129462 # Writes before turning the bus around for reads 23411103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::mean 16.853911 # Writes before turning the bus around for reads 23511103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::gmean 16.595936 # Writes before turning the bus around for reads 23611103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::stdev 4.789289 # Writes before turning the bus around for reads 23711103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::16-19 125866 97.22% 97.22% # Writes before turning the bus around for reads 23811103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::20-23 1229 0.95% 98.17% # Writes before turning the bus around for reads 23911103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::24-27 433 0.33% 98.51% # Writes before turning the bus around for reads 24011103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::28-31 197 0.15% 98.66% # Writes before turning the bus around for reads 24111103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::32-35 330 0.25% 98.91% # Writes before turning the bus around for reads 24211103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::36-39 524 0.40% 99.32% # Writes before turning the bus around for reads 24311103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::40-43 121 0.09% 99.41% # Writes before turning the bus around for reads 24411103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::44-47 23 0.02% 99.43% # Writes before turning the bus around for reads 24511103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::48-51 39 0.03% 99.46% # Writes before turning the bus around for reads 24611103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::52-55 16 0.01% 99.47% # Writes before turning the bus around for reads 24711103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::56-59 43 0.03% 99.50% # Writes before turning the bus around for reads 24811103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::60-63 23 0.02% 99.52% # Writes before turning the bus around for reads 24911103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::64-67 425 0.33% 99.85% # Writes before turning the bus around for reads 25011103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::68-71 36 0.03% 99.88% # Writes before turning the bus around for reads 25111103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::72-75 42 0.03% 99.91% # Writes before turning the bus around for reads 25211103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::76-79 37 0.03% 99.94% # Writes before turning the bus around for reads 25311103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::80-83 19 0.01% 99.95% # Writes before turning the bus around for reads 25411103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::88-91 1 0.00% 99.96% # Writes before turning the bus around for reads 25511103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::92-95 1 0.00% 99.96% # Writes before turning the bus around for reads 25611103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::96-99 3 0.00% 99.96% # Writes before turning the bus around for reads 25711103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::100-103 2 0.00% 99.96% # Writes before turning the bus around for reads 25811103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::112-115 2 0.00% 99.96% # Writes before turning the bus around for reads 25911103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::124-127 1 0.00% 99.96% # Writes before turning the bus around for reads 26011103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::128-131 35 0.03% 99.99% # Writes before turning the bus around for reads 26111103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::132-135 1 0.00% 99.99% # Writes before turning the bus around for reads 26211103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::144-147 3 0.00% 99.99% # Writes before turning the bus around for reads 26311103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::148-151 1 0.00% 99.99% # Writes before turning the bus around for reads 26411103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::164-167 6 0.00% 100.00% # Writes before turning the bus around for reads 26510892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads 26610892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads 26711103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::total 129462 # Writes before turning the bus around for reads 26811103Snilay@cs.wisc.edusystem.physmem.totQLat 61876185756 # Total ticks spent queuing 26911103Snilay@cs.wisc.edusystem.physmem.totMemAccLat 108132979506 # Total ticks spent from burst creation until serviced by the DRAM 27011103Snilay@cs.wisc.edusystem.physmem.totBusLat 12335145000 # Total ticks spent in databus transfers 27111103Snilay@cs.wisc.edusystem.physmem.avgQLat 25081.26 # Average queueing delay per DRAM burst 27210515SAli.Saidi@ARM.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 27311103Snilay@cs.wisc.edusystem.physmem.avgMemAccLat 43831.26 # Average memory access latency per DRAM burst 27411103Snilay@cs.wisc.edusystem.physmem.avgRdBW 3.06 # Average DRAM read bandwidth in MiByte/s 27511103Snilay@cs.wisc.edusystem.physmem.avgWrBW 2.71 # Average achieved write bandwidth in MiByte/s 27611103Snilay@cs.wisc.edusystem.physmem.avgRdBWSys 3.04 # Average system read bandwidth in MiByte/s 27711103Snilay@cs.wisc.edusystem.physmem.avgWrBWSys 2.71 # Average system write bandwidth in MiByte/s 27810515SAli.Saidi@ARM.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 27911103Snilay@cs.wisc.edusystem.physmem.busUtil 0.05 # Data bus utilization in percentage 28011103Snilay@cs.wisc.edusystem.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 28111103Snilay@cs.wisc.edusystem.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 28210892Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing 28311103Snilay@cs.wisc.edusystem.physmem.avgWrQLen 25.36 # Average write queue length when enqueuing 28411103Snilay@cs.wisc.edusystem.physmem.readRowHits 2056722 # Number of row buffer hits during reads 28511103Snilay@cs.wisc.edusystem.physmem.writeRowHits 1654173 # Number of row buffer hits during writes 28611103Snilay@cs.wisc.edusystem.physmem.readRowHitRate 83.37 # Row buffer hit rate for reads 28711103Snilay@cs.wisc.edusystem.physmem.writeRowHitRate 75.81 # Row buffer hit rate for writes 28811103Snilay@cs.wisc.edusystem.physmem.avgGap 11083878.27 # Average gap between requests 28911103Snilay@cs.wisc.edusystem.physmem.pageHitRate 79.82 # Row buffer hit rate, read and write combined 29011103Snilay@cs.wisc.edusystem.physmem_0.actEnergy 3550765680 # Energy for activate commands per rank (pJ) 29111103Snilay@cs.wisc.edusystem.physmem_0.preEnergy 1937421750 # Energy for precharge commands per rank (pJ) 29211103Snilay@cs.wisc.edusystem.physmem_0.readEnergy 9523885800 # Energy for read commands per rank (pJ) 29311103Snilay@cs.wisc.edusystem.physmem_0.writeEnergy 7046332560 # Energy for write commands per rank (pJ) 29411103Snilay@cs.wisc.edusystem.physmem_0.refreshEnergy 3367790100480 # Energy for refresh commands per rank (pJ) 29511103Snilay@cs.wisc.edusystem.physmem_0.actBackEnergy 1313489115900 # Energy for active background per rank (pJ) 29611103Snilay@cs.wisc.edusystem.physmem_0.preBackEnergy 29785116936750 # Energy for precharge background per rank (pJ) 29711103Snilay@cs.wisc.edusystem.physmem_0.totalEnergy 34488454558920 # Total energy per rank (pJ) 29811103Snilay@cs.wisc.edusystem.physmem_0.averagePower 668.871313 # Core power per rank (mW) 29911103Snilay@cs.wisc.edusystem.physmem_0.memoryStateTime::IDLE 49548907375208 # Time in different power states 30011103Snilay@cs.wisc.edusystem.physmem_0.memoryStateTime::REF 1721774080000 # Time in different power states 30110628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 30211103Snilay@cs.wisc.edusystem.physmem_0.memoryStateTime::ACT 291487862292 # Time in different power states 30310628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 30411103Snilay@cs.wisc.edusystem.physmem_1.actEnergy 3541066200 # Energy for activate commands per rank (pJ) 30511103Snilay@cs.wisc.edusystem.physmem_1.preEnergy 1932129375 # Energy for precharge commands per rank (pJ) 30611103Snilay@cs.wisc.edusystem.physmem_1.readEnergy 9718893600 # Energy for read commands per rank (pJ) 30711103Snilay@cs.wisc.edusystem.physmem_1.writeEnergy 7092645120 # Energy for write commands per rank (pJ) 30811103Snilay@cs.wisc.edusystem.physmem_1.refreshEnergy 3367790100480 # Energy for refresh commands per rank (pJ) 30911103Snilay@cs.wisc.edusystem.physmem_1.actBackEnergy 1316895447015 # Energy for active background per rank (pJ) 31011103Snilay@cs.wisc.edusystem.physmem_1.preBackEnergy 29782128927000 # Energy for precharge background per rank (pJ) 31111103Snilay@cs.wisc.edusystem.physmem_1.totalEnergy 34489099208790 # Total energy per rank (pJ) 31211103Snilay@cs.wisc.edusystem.physmem_1.averagePower 668.883816 # Core power per rank (mW) 31311103Snilay@cs.wisc.edusystem.physmem_1.memoryStateTime::IDLE 49543906734220 # Time in different power states 31411103Snilay@cs.wisc.edusystem.physmem_1.memoryStateTime::REF 1721774080000 # Time in different power states 31510628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 31611103Snilay@cs.wisc.edusystem.physmem_1.memoryStateTime::ACT 296486485780 # Time in different power states 31710628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 31810585Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory 31910585Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 32010585Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::total 436 # Number of bytes read from this memory 32110585Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_inst_read::cpu.inst 400 # Number of instructions bytes read from this memory 32210585Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_inst_read::total 400 # Number of instructions bytes read from this memory 32310585Sandreas.hansson@arm.comsystem.realview.nvmem.num_reads::cpu.inst 25 # Number of read requests responded to by this memory 32410585Sandreas.hansson@arm.comsystem.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 32510585Sandreas.hansson@arm.comsystem.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory 32610585Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) 32710585Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 32810585Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) 32910585Sandreas.hansson@arm.comsystem.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) 33010585Sandreas.hansson@arm.comsystem.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) 33110585Sandreas.hansson@arm.comsystem.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) 33210585Sandreas.hansson@arm.comsystem.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 33310585Sandreas.hansson@arm.comsystem.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) 33410585Sandreas.hansson@arm.comsystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 33510585Sandreas.hansson@arm.comsystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 33610585Sandreas.hansson@arm.comsystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 33710585Sandreas.hansson@arm.comsystem.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 33810585Sandreas.hansson@arm.comsystem.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 33910585Sandreas.hansson@arm.comsystem.cf0.dma_write_txs 1669 # Number of DMA write transactions. 34011103Snilay@cs.wisc.edusystem.cpu.branchPred.lookups 288825634 # Number of BP lookups 34111103Snilay@cs.wisc.edusystem.cpu.branchPred.condPredicted 198097109 # Number of conditional branches predicted 34211103Snilay@cs.wisc.edusystem.cpu.branchPred.condIncorrect 13566789 # Number of conditional branches incorrect 34311103Snilay@cs.wisc.edusystem.cpu.branchPred.BTBLookups 207338959 # Number of BTB lookups 34411103Snilay@cs.wisc.edusystem.cpu.branchPred.BTBHits 136913226 # Number of BTB hits 34510585Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 34611103Snilay@cs.wisc.edusystem.cpu.branchPred.BTBHitPct 66.033526 # BTB Hit Percentage 34711103Snilay@cs.wisc.edusystem.cpu.branchPred.usedRAS 37451224 # Number of times the RAS was used to get a target. 34811103Snilay@cs.wisc.edusystem.cpu.branchPred.RASInCorrect 402112 # Number of incorrect RAS predictions. 34910585Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 35010628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 35110628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 35210628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 35310628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 35410628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 35510628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 35610628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 35710628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 35810585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 35910585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 36010585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 36110585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 36210585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 36310585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 36410585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 36510585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 36610585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 36710585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 36810585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 36910585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 37010585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 37110585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 37210585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 37310585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 37410585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 37510585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 37610585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 37710585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 37810585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 37911103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walks 1430156 # Table walker walks requested 38011103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walksLong 1430156 # Table walker walks initiated with long descriptors 38111103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walksLongTerminationLevel::Level2 30793 # Level at which table walker walks with long descriptors terminate 38211103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walksLongTerminationLevel::Level3 273791 # Level at which table walker walks with long descriptors terminate 38311103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walksSquashedBefore 677378 # Table walks squashed before starting 38411103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkWaitTime::samples 752778 # Table walker wait (enqueue to first request) latency 38511103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkWaitTime::mean 2375.228819 # Table walker wait (enqueue to first request) latency 38611103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkWaitTime::stdev 15567.513073 # Table walker wait (enqueue to first request) latency 38711103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkWaitTime::0-65535 746726 99.20% 99.20% # Table walker wait (enqueue to first request) latency 38811103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkWaitTime::65536-131071 4359 0.58% 99.78% # Table walker wait (enqueue to first request) latency 38911103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkWaitTime::131072-196607 685 0.09% 99.87% # Table walker wait (enqueue to first request) latency 39011103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkWaitTime::196608-262143 394 0.05% 99.92% # Table walker wait (enqueue to first request) latency 39111103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkWaitTime::262144-327679 311 0.04% 99.96% # Table walker wait (enqueue to first request) latency 39211103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkWaitTime::327680-393215 120 0.02% 99.98% # Table walker wait (enqueue to first request) latency 39311103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkWaitTime::393216-458751 171 0.02% 100.00% # Table walker wait (enqueue to first request) latency 39411103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkWaitTime::458752-524287 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency 39511103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency 39611103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 39711103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkWaitTime::total 752778 # Table walker wait (enqueue to first request) latency 39811103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkCompletionTime::samples 802636 # Table walker service (enqueue to completion) latency 39911103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkCompletionTime::mean 25959.455469 # Table walker service (enqueue to completion) latency 40011103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkCompletionTime::gmean 21570.790504 # Table walker service (enqueue to completion) latency 40111103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkCompletionTime::stdev 17698.477360 # Table walker service (enqueue to completion) latency 40211103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkCompletionTime::0-65535 783977 97.68% 97.68% # Table walker service (enqueue to completion) latency 40311103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkCompletionTime::65536-131071 16023 2.00% 99.67% # Table walker service (enqueue to completion) latency 40411103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkCompletionTime::131072-196607 1555 0.19% 99.87% # Table walker service (enqueue to completion) latency 40511103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkCompletionTime::196608-262143 558 0.07% 99.93% # Table walker service (enqueue to completion) latency 40611103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkCompletionTime::262144-327679 316 0.04% 99.97% # Table walker service (enqueue to completion) latency 40711103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkCompletionTime::327680-393215 129 0.02% 99.99% # Table walker service (enqueue to completion) latency 40811103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkCompletionTime::393216-458751 37 0.00% 99.99% # Table walker service (enqueue to completion) latency 40911103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkCompletionTime::458752-524287 19 0.00% 100.00% # Table walker service (enqueue to completion) latency 41011103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkCompletionTime::524288-589823 22 0.00% 100.00% # Table walker service (enqueue to completion) latency 41111103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkCompletionTime::total 802636 # Table walker service (enqueue to completion) latency 41211103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walksPending::samples 1044763922448 # Table walker pending requests distribution 41311103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walksPending::mean 0.739319 # Table walker pending requests distribution 41411103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walksPending::stdev 0.520240 # Table walker pending requests distribution 41511103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walksPending::0-1 1040800473448 99.62% 99.62% # Table walker pending requests distribution 41611103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walksPending::2-3 2579873000 0.25% 99.87% # Table walker pending requests distribution 41711103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walksPending::4-5 637994000 0.06% 99.93% # Table walker pending requests distribution 41811103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walksPending::6-7 271834500 0.03% 99.95% # Table walker pending requests distribution 41911103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walksPending::8-9 201274500 0.02% 99.97% # Table walker pending requests distribution 42011103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walksPending::10-11 132884500 0.01% 99.99% # Table walker pending requests distribution 42111103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walksPending::12-13 46819000 0.00% 99.99% # Table walker pending requests distribution 42211103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walksPending::14-15 89469000 0.01% 100.00% # Table walker pending requests distribution 42311103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walksPending::16-17 3255500 0.00% 100.00% # Table walker pending requests distribution 42411103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walksPending::18-19 45000 0.00% 100.00% # Table walker pending requests distribution 42511103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walksPending::total 1044763922448 # Table walker pending requests distribution 42611103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkPageSizes::4K 273792 89.89% 89.89% # Table walker page sizes translated 42711103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkPageSizes::2M 30793 10.11% 100.00% # Table walker page sizes translated 42811103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkPageSizes::total 304585 # Table walker page sizes translated 42911103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1430156 # Table walker requests started/completed, data/inst 43010628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 43111103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 1430156 # Table walker requests started/completed, data/inst 43211103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 304585 # Table walker requests started/completed, data/inst 43310628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 43411103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 304585 # Table walker requests started/completed, data/inst 43511103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkRequestOrigin::total 1734741 # Table walker requests started/completed, data/inst 43610585Sandreas.hansson@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 43710585Sandreas.hansson@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 43811103Snilay@cs.wisc.edusystem.cpu.dtb.read_hits 217117628 # DTB read hits 43911103Snilay@cs.wisc.edusystem.cpu.dtb.read_misses 1002788 # DTB read misses 44011103Snilay@cs.wisc.edusystem.cpu.dtb.write_hits 192115888 # DTB write hits 44111103Snilay@cs.wisc.edusystem.cpu.dtb.write_misses 427368 # DTB write misses 44211103Snilay@cs.wisc.edusystem.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 44310585Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 44411103Snilay@cs.wisc.edusystem.cpu.dtb.flush_tlb_mva_asid 63203 # Number of times TLB was flushed by MVA & ASID 44511103Snilay@cs.wisc.edusystem.cpu.dtb.flush_tlb_asid 1203 # Number of times TLB was flushed by ASID 44611103Snilay@cs.wisc.edusystem.cpu.dtb.flush_entries 87986 # Number of entries that have been flushed from TLB 44710892Sandreas.hansson@arm.comsystem.cpu.dtb.align_faults 110 # Number of TLB faults due to alignment restrictions 44811103Snilay@cs.wisc.edusystem.cpu.dtb.prefetch_faults 15675 # Number of TLB faults due to prefetch 44910585Sandreas.hansson@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 45011103Snilay@cs.wisc.edusystem.cpu.dtb.perms_faults 85972 # Number of TLB faults due to permissions restrictions 45111103Snilay@cs.wisc.edusystem.cpu.dtb.read_accesses 218120416 # DTB read accesses 45211103Snilay@cs.wisc.edusystem.cpu.dtb.write_accesses 192543256 # DTB write accesses 45310585Sandreas.hansson@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 45411103Snilay@cs.wisc.edusystem.cpu.dtb.hits 409233516 # DTB hits 45511103Snilay@cs.wisc.edusystem.cpu.dtb.misses 1430156 # DTB misses 45611103Snilay@cs.wisc.edusystem.cpu.dtb.accesses 410663672 # DTB accesses 45710628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 45810628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 45910628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 46010628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 46110628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 46210628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 46310628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 46410628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 46510585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 46610585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 46710585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 46810585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 46910585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 47010585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 47110585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 47210585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 47310585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 47410585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 47510585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 47610585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 47710585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 47810585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 47910585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 48010585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 48110585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 48210585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 48310585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 48410585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 48510585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 48611103Snilay@cs.wisc.edusystem.cpu.itb.walker.walks 177415 # Table walker walks requested 48711103Snilay@cs.wisc.edusystem.cpu.itb.walker.walksLong 177415 # Table walker walks initiated with long descriptors 48811103Snilay@cs.wisc.edusystem.cpu.itb.walker.walksLongTerminationLevel::Level2 1441 # Level at which table walker walks with long descriptors terminate 48911103Snilay@cs.wisc.edusystem.cpu.itb.walker.walksLongTerminationLevel::Level3 130680 # Level at which table walker walks with long descriptors terminate 49011103Snilay@cs.wisc.edusystem.cpu.itb.walker.walksSquashedBefore 19804 # Table walks squashed before starting 49111103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkWaitTime::samples 157611 # Table walker wait (enqueue to first request) latency 49211103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkWaitTime::mean 1499.045117 # Table walker wait (enqueue to first request) latency 49311103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkWaitTime::stdev 10189.386950 # Table walker wait (enqueue to first request) latency 49411103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkWaitTime::0-32767 155888 98.91% 98.91% # Table walker wait (enqueue to first request) latency 49511103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkWaitTime::32768-65535 579 0.37% 99.27% # Table walker wait (enqueue to first request) latency 49611103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkWaitTime::65536-98303 739 0.47% 99.74% # Table walker wait (enqueue to first request) latency 49711103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkWaitTime::98304-131071 292 0.19% 99.93% # Table walker wait (enqueue to first request) latency 49811103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkWaitTime::131072-163839 35 0.02% 99.95% # Table walker wait (enqueue to first request) latency 49911103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkWaitTime::163840-196607 38 0.02% 99.97% # Table walker wait (enqueue to first request) latency 50011103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkWaitTime::196608-229375 19 0.01% 99.99% # Table walker wait (enqueue to first request) latency 50111103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkWaitTime::229376-262143 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency 50211103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkWaitTime::262144-294911 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency 50310892Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::294912-327679 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency 50411103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkWaitTime::327680-360447 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency 50511103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkWaitTime::total 157611 # Table walker wait (enqueue to first request) latency 50611103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkCompletionTime::samples 151925 # Table walker service (enqueue to completion) latency 50711103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkCompletionTime::mean 29463.087050 # Table walker service (enqueue to completion) latency 50811103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkCompletionTime::gmean 24547.770920 # Table walker service (enqueue to completion) latency 50911103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkCompletionTime::stdev 22228.579404 # Table walker service (enqueue to completion) latency 51011103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkCompletionTime::0-65535 146250 96.26% 96.26% # Table walker service (enqueue to completion) latency 51111103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkCompletionTime::65536-131071 4800 3.16% 99.42% # Table walker service (enqueue to completion) latency 51211103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkCompletionTime::131072-196607 534 0.35% 99.78% # Table walker service (enqueue to completion) latency 51311103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkCompletionTime::196608-262143 196 0.13% 99.90% # Table walker service (enqueue to completion) latency 51411103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkCompletionTime::262144-327679 80 0.05% 99.96% # Table walker service (enqueue to completion) latency 51511103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkCompletionTime::327680-393215 44 0.03% 99.99% # Table walker service (enqueue to completion) latency 51611103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkCompletionTime::393216-458751 15 0.01% 100.00% # Table walker service (enqueue to completion) latency 51711103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency 51810726Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 51911103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkCompletionTime::total 151925 # Table walker service (enqueue to completion) latency 52011103Snilay@cs.wisc.edusystem.cpu.itb.walker.walksPending::samples 920206753364 # Table walker pending requests distribution 52111103Snilay@cs.wisc.edusystem.cpu.itb.walker.walksPending::mean 0.948994 # Table walker pending requests distribution 52211103Snilay@cs.wisc.edusystem.cpu.itb.walker.walksPending::stdev 0.220270 # Table walker pending requests distribution 52311103Snilay@cs.wisc.edusystem.cpu.itb.walker.walksPending::0 46987798652 5.11% 5.11% # Table walker pending requests distribution 52411103Snilay@cs.wisc.edusystem.cpu.itb.walker.walksPending::1 873167595712 94.89% 99.99% # Table walker pending requests distribution 52511103Snilay@cs.wisc.edusystem.cpu.itb.walker.walksPending::2 50573500 0.01% 100.00% # Table walker pending requests distribution 52611103Snilay@cs.wisc.edusystem.cpu.itb.walker.walksPending::3 783500 0.00% 100.00% # Table walker pending requests distribution 52710892Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::4 2000 0.00% 100.00% # Table walker pending requests distribution 52811103Snilay@cs.wisc.edusystem.cpu.itb.walker.walksPending::total 920206753364 # Table walker pending requests distribution 52911103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkPageSizes::4K 130680 98.91% 98.91% # Table walker page sizes translated 53011103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkPageSizes::2M 1441 1.09% 100.00% # Table walker page sizes translated 53111103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkPageSizes::total 132121 # Table walker page sizes translated 53210628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 53311103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 177415 # Table walker requests started/completed, data/inst 53411103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkRequestOrigin_Requested::total 177415 # Table walker requests started/completed, data/inst 53510628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 53611103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 132121 # Table walker requests started/completed, data/inst 53711103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkRequestOrigin_Completed::total 132121 # Table walker requests started/completed, data/inst 53811103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkRequestOrigin::total 309536 # Table walker requests started/completed, data/inst 53911103Snilay@cs.wisc.edusystem.cpu.itb.inst_hits 461294711 # ITB inst hits 54011103Snilay@cs.wisc.edusystem.cpu.itb.inst_misses 177415 # ITB inst misses 54110585Sandreas.hansson@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 54210585Sandreas.hansson@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 54310585Sandreas.hansson@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 54410585Sandreas.hansson@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 54511103Snilay@cs.wisc.edusystem.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 54610585Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 54711103Snilay@cs.wisc.edusystem.cpu.itb.flush_tlb_mva_asid 63203 # Number of times TLB was flushed by MVA & ASID 54811103Snilay@cs.wisc.edusystem.cpu.itb.flush_tlb_asid 1203 # Number of times TLB was flushed by ASID 54911103Snilay@cs.wisc.edusystem.cpu.itb.flush_entries 62159 # Number of entries that have been flushed from TLB 55010585Sandreas.hansson@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 55110585Sandreas.hansson@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 55210585Sandreas.hansson@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 55311103Snilay@cs.wisc.edusystem.cpu.itb.perms_faults 458083 # Number of TLB faults due to permissions restrictions 55410585Sandreas.hansson@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 55510585Sandreas.hansson@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 55611103Snilay@cs.wisc.edusystem.cpu.itb.inst_accesses 461472126 # ITB inst accesses 55711103Snilay@cs.wisc.edusystem.cpu.itb.hits 461294711 # DTB hits 55811103Snilay@cs.wisc.edusystem.cpu.itb.misses 177415 # DTB misses 55911103Snilay@cs.wisc.edusystem.cpu.itb.accesses 461472126 # DTB accesses 56011103Snilay@cs.wisc.edusystem.cpu.numCycles 2141240199 # number of cpu cycles simulated 56110585Sandreas.hansson@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 56210585Sandreas.hansson@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 56311103Snilay@cs.wisc.edusystem.cpu.fetch.icacheStallCycles 785638694 # Number of cycles fetch is stalled on an Icache miss 56411103Snilay@cs.wisc.edusystem.cpu.fetch.Insts 1289733601 # Number of instructions fetch has processed 56511103Snilay@cs.wisc.edusystem.cpu.fetch.Branches 288825634 # Number of branches that fetch encountered 56611103Snilay@cs.wisc.edusystem.cpu.fetch.predictedBranches 174364450 # Number of branches that fetch has predicted taken 56711103Snilay@cs.wisc.edusystem.cpu.fetch.Cycles 1267374465 # Number of cycles fetch has run and was not squashing or blocked 56811103Snilay@cs.wisc.edusystem.cpu.fetch.SquashCycles 29210356 # Number of cycles fetch has spent squashing 56911103Snilay@cs.wisc.edusystem.cpu.fetch.TlbCycles 4418623 # Number of cycles fetch has spent waiting for tlb 57011103Snilay@cs.wisc.edusystem.cpu.fetch.MiscStallCycles 28241 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 57111103Snilay@cs.wisc.edusystem.cpu.fetch.PendingTrapStallCycles 12152128 # Number of stall cycles due to pending traps 57211103Snilay@cs.wisc.edusystem.cpu.fetch.PendingQuiesceStallCycles 1217886 # Number of stall cycles due to pending quiesce instructions 57311103Snilay@cs.wisc.edusystem.cpu.fetch.IcacheWaitRetryStallCycles 633 # Number of stall cycles due to full MSHR 57411103Snilay@cs.wisc.edusystem.cpu.fetch.CacheLines 460817774 # Number of cache lines fetched 57511103Snilay@cs.wisc.edusystem.cpu.fetch.IcacheSquashes 6728045 # Number of outstanding Icache misses that were squashed 57611103Snilay@cs.wisc.edusystem.cpu.fetch.ItlbSquashes 53516 # Number of outstanding ITLB misses that were squashed 57711103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::samples 2085435848 # Number of instructions fetched each cycle (Total) 57811103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::mean 0.725171 # Number of instructions fetched each cycle (Total) 57911103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::stdev 1.139838 # Number of instructions fetched each cycle (Total) 58010585Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 58111103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::0 1366680941 65.53% 65.53% # Number of instructions fetched each cycle (Total) 58211103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::1 278589155 13.36% 78.89% # Number of instructions fetched each cycle (Total) 58311103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::2 86788366 4.16% 83.05% # Number of instructions fetched each cycle (Total) 58411103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::3 353377386 16.95% 100.00% # Number of instructions fetched each cycle (Total) 58510585Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 58610585Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 58710585Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 58811103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::total 2085435848 # Number of instructions fetched each cycle (Total) 58911103Snilay@cs.wisc.edusystem.cpu.fetch.branchRate 0.134887 # Number of branch fetches per cycle 59011103Snilay@cs.wisc.edusystem.cpu.fetch.rate 0.602330 # Number of inst fetches per cycle 59111103Snilay@cs.wisc.edusystem.cpu.decode.IdleCycles 612239538 # Number of cycles decode is idle 59211103Snilay@cs.wisc.edusystem.cpu.decode.BlockedCycles 852574124 # Number of cycles decode is blocked 59311103Snilay@cs.wisc.edusystem.cpu.decode.RunCycles 529946172 # Number of cycles decode is running 59411103Snilay@cs.wisc.edusystem.cpu.decode.UnblockCycles 80118083 # Number of cycles decode is unblocking 59511103Snilay@cs.wisc.edusystem.cpu.decode.SquashCycles 10557931 # Number of cycles decode is squashing 59611103Snilay@cs.wisc.edusystem.cpu.decode.BranchResolved 41219534 # Number of times decode resolved a branch 59711103Snilay@cs.wisc.edusystem.cpu.decode.BranchMispred 4107385 # Number of times decode detected a branch misprediction 59811103Snilay@cs.wisc.edusystem.cpu.decode.DecodedInsts 1403247413 # Number of instructions handled by decode 59911103Snilay@cs.wisc.edusystem.cpu.decode.SquashedInsts 32566835 # Number of squashed instructions handled by decode 60011103Snilay@cs.wisc.edusystem.cpu.rename.SquashCycles 10557931 # Number of cycles rename is squashing 60111103Snilay@cs.wisc.edusystem.cpu.rename.IdleCycles 674962554 # Number of cycles rename is idle 60211103Snilay@cs.wisc.edusystem.cpu.rename.BlockCycles 85247440 # Number of cycles rename is blocking 60311103Snilay@cs.wisc.edusystem.cpu.rename.serializeStallCycles 550746700 # count of cycles rename stalled for serializing inst 60411103Snilay@cs.wisc.edusystem.cpu.rename.RunCycles 547461697 # Number of cycles rename is running 60511103Snilay@cs.wisc.edusystem.cpu.rename.UnblockCycles 216459526 # Number of cycles rename is unblocking 60611103Snilay@cs.wisc.edusystem.cpu.rename.RenamedInsts 1379612307 # Number of instructions processed by rename 60711103Snilay@cs.wisc.edusystem.cpu.rename.SquashedInsts 7971383 # Number of squashed instructions processed by rename 60811103Snilay@cs.wisc.edusystem.cpu.rename.ROBFullEvents 7360618 # Number of times rename has blocked due to ROB full 60911103Snilay@cs.wisc.edusystem.cpu.rename.IQFullEvents 963827 # Number of times rename has blocked due to IQ full 61011103Snilay@cs.wisc.edusystem.cpu.rename.LQFullEvents 1074082 # Number of times rename has blocked due to LQ full 61111103Snilay@cs.wisc.edusystem.cpu.rename.SQFullEvents 133209723 # Number of times rename has blocked due to SQ full 61211103Snilay@cs.wisc.edusystem.cpu.rename.FullRegisterEvents 22971 # Number of times there has been no free registers 61311103Snilay@cs.wisc.edusystem.cpu.rename.RenamedOperands 1329803577 # Number of destination operands rename has renamed 61411103Snilay@cs.wisc.edusystem.cpu.rename.RenameLookups 2195861380 # Number of register rename lookups that rename has made 61511103Snilay@cs.wisc.edusystem.cpu.rename.int_rename_lookups 1637517470 # Number of integer rename lookups 61611103Snilay@cs.wisc.edusystem.cpu.rename.fp_rename_lookups 1437183 # Number of floating rename lookups 61711103Snilay@cs.wisc.edusystem.cpu.rename.CommittedMaps 1251935276 # Number of HB maps that are committed 61811103Snilay@cs.wisc.edusystem.cpu.rename.UndoneMaps 77868298 # Number of HB maps that are undone due to squashing 61911103Snilay@cs.wisc.edusystem.cpu.rename.serializingInsts 43546894 # count of serializing insts renamed 62011103Snilay@cs.wisc.edusystem.cpu.rename.tempSerializingInsts 39087703 # count of temporary serializing insts renamed 62111103Snilay@cs.wisc.edusystem.cpu.rename.skidInsts 166786807 # count of insts added to the skid buffer 62211103Snilay@cs.wisc.edusystem.cpu.memDep0.insertedLoads 221659276 # Number of loads inserted to the mem dependence unit. 62311103Snilay@cs.wisc.edusystem.cpu.memDep0.insertedStores 196613901 # Number of stores inserted to the mem dependence unit. 62411103Snilay@cs.wisc.edusystem.cpu.memDep0.conflictingLoads 12565776 # Number of conflicting loads. 62511103Snilay@cs.wisc.edusystem.cpu.memDep0.conflictingStores 11015266 # Number of conflicting stores. 62611103Snilay@cs.wisc.edusystem.cpu.iq.iqInstsAdded 1326936815 # Number of instructions added to the IQ (excludes non-spec) 62711103Snilay@cs.wisc.edusystem.cpu.iq.iqNonSpecInstsAdded 43849103 # Number of non-speculative instructions added to the IQ 62811103Snilay@cs.wisc.edusystem.cpu.iq.iqInstsIssued 1356961205 # Number of instructions issued 62911103Snilay@cs.wisc.edusystem.cpu.iq.iqSquashedInstsIssued 4098709 # Number of squashed instructions issued 63011103Snilay@cs.wisc.edusystem.cpu.iq.iqSquashedInstsExamined 72699747 # Number of squashed instructions iterated over during squash; mainly for profiling 63111103Snilay@cs.wisc.edusystem.cpu.iq.iqSquashedOperandsExamined 41430931 # Number of squashed operands that are examined and possibly removed from graph 63211103Snilay@cs.wisc.edusystem.cpu.iq.iqSquashedNonSpecRemoved 372473 # Number of squashed non-spec instructions that were removed 63311103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::samples 2085435848 # Number of insts issued each cycle 63411103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::mean 0.650685 # Number of insts issued each cycle 63511103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::stdev 0.914510 # Number of insts issued each cycle 63610585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 63711103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::0 1239320860 59.43% 59.43% # Number of insts issued each cycle 63811103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::1 449936886 21.58% 81.00% # Number of insts issued each cycle 63911103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::2 291017288 13.95% 94.96% # Number of insts issued each cycle 64011103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::3 95682212 4.59% 99.55% # Number of insts issued each cycle 64111103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::4 9449903 0.45% 100.00% # Number of insts issued each cycle 64211103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::5 28699 0.00% 100.00% # Number of insts issued each cycle 64310585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 64410585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 64510585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 64610585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 64710585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 64810585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 64911103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::total 2085435848 # Number of insts issued each cycle 65010585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 65111103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::IntAlu 73477453 34.17% 34.17% # attempts to use FU when none available 65211103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::IntMult 90486 0.04% 34.21% # attempts to use FU when none available 65311103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::IntDiv 26768 0.01% 34.22% # attempts to use FU when none available 65411103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatAdd 0 0.00% 34.22% # attempts to use FU when none available 65511103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatCmp 0 0.00% 34.22% # attempts to use FU when none available 65611103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatCvt 0 0.00% 34.22% # attempts to use FU when none available 65711103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatMult 0 0.00% 34.22% # attempts to use FU when none available 65811103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatDiv 0 0.00% 34.22% # attempts to use FU when none available 65911103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.22% # attempts to use FU when none available 66011103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdAdd 0 0.00% 34.22% # attempts to use FU when none available 66111103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.22% # attempts to use FU when none available 66211103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdAlu 0 0.00% 34.22% # attempts to use FU when none available 66311103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdCmp 0 0.00% 34.22% # attempts to use FU when none available 66411103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdCvt 0 0.00% 34.22% # attempts to use FU when none available 66511103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdMisc 0 0.00% 34.22% # attempts to use FU when none available 66611103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdMult 0 0.00% 34.22% # attempts to use FU when none available 66711103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.22% # attempts to use FU when none available 66811103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdShift 0 0.00% 34.22% # attempts to use FU when none available 66911103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.22% # attempts to use FU when none available 67011103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.22% # attempts to use FU when none available 67111103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.22% # attempts to use FU when none available 67211103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.22% # attempts to use FU when none available 67311103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.22% # attempts to use FU when none available 67411103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.22% # attempts to use FU when none available 67511103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.22% # attempts to use FU when none available 67611103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatMisc 385 0.00% 34.22% # attempts to use FU when none available 67711103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.22% # attempts to use FU when none available 67811103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.22% # attempts to use FU when none available 67911103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.22% # attempts to use FU when none available 68011103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::MemRead 57876005 26.91% 61.13% # attempts to use FU when none available 68111103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::MemWrite 83594438 38.87% 100.00% # attempts to use FU when none available 68210585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 68310585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 68411103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::No_OpClass 31 0.00% 0.00% # Type of FU issued 68511103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::IntAlu 937288786 69.07% 69.07% # Type of FU issued 68611103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::IntMult 2936989 0.22% 69.29% # Type of FU issued 68711103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::IntDiv 129444 0.01% 69.30% # Type of FU issued 68811103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatAdd 372 0.00% 69.30% # Type of FU issued 68911103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.30% # Type of FU issued 69011103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.30% # Type of FU issued 69111103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.30% # Type of FU issued 69211103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.30% # Type of FU issued 69311103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.30% # Type of FU issued 69411103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.30% # Type of FU issued 69511103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.30% # Type of FU issued 69611103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.30% # Type of FU issued 69711103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.30% # Type of FU issued 69811103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.30% # Type of FU issued 69911103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.30% # Type of FU issued 70011103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.30% # Type of FU issued 70111103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.30% # Type of FU issued 70211103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.30% # Type of FU issued 70311103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.30% # Type of FU issued 70411103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.30% # Type of FU issued 70511103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.30% # Type of FU issued 70611103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.30% # Type of FU issued 70711103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.30% # Type of FU issued 70811103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.30% # Type of FU issued 70911103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.30% # Type of FU issued 71011103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatMisc 114407 0.01% 69.31% # Type of FU issued 71111103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.31% # Type of FU issued 71211103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.31% # Type of FU issued 71311103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.31% # Type of FU issued 71411103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::MemRead 221949724 16.36% 85.66% # Type of FU issued 71511103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::MemWrite 194541406 14.34% 100.00% # Type of FU issued 71610585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 71710585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 71811103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::total 1356961205 # Type of FU issued 71911103Snilay@cs.wisc.edusystem.cpu.iq.rate 0.633727 # Inst issue rate 72011103Snilay@cs.wisc.edusystem.cpu.iq.fu_busy_cnt 215065535 # FU busy when requested 72111103Snilay@cs.wisc.edusystem.cpu.iq.fu_busy_rate 0.158491 # FU busy rate (busy events/executed inst) 72211103Snilay@cs.wisc.edusystem.cpu.iq.int_inst_queue_reads 5016097714 # Number of integer instruction queue reads 72311103Snilay@cs.wisc.edusystem.cpu.iq.int_inst_queue_writes 1442740685 # Number of integer instruction queue writes 72411103Snilay@cs.wisc.edusystem.cpu.iq.int_inst_queue_wakeup_accesses 1335189379 # Number of integer instruction queue wakeup accesses 72511103Snilay@cs.wisc.edusystem.cpu.iq.fp_inst_queue_reads 2424787 # Number of floating instruction queue reads 72611103Snilay@cs.wisc.edusystem.cpu.iq.fp_inst_queue_writes 927446 # Number of floating instruction queue writes 72711103Snilay@cs.wisc.edusystem.cpu.iq.fp_inst_queue_wakeup_accesses 888349 # Number of floating instruction queue wakeup accesses 72811103Snilay@cs.wisc.edusystem.cpu.iq.int_alu_accesses 1570502436 # Number of integer alu accesses 72911103Snilay@cs.wisc.edusystem.cpu.iq.fp_alu_accesses 1524273 # Number of floating point alu accesses 73011103Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.forwLoads 5709357 # Number of loads that had data forwarded from stores 73110585Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 73211103Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.squashedLoads 16902439 # Number of loads squashed 73311103Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.ignoredResponses 24350 # Number of memory responses ignored because the instruction is squashed 73411103Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.memOrderViolation 184211 # Number of memory ordering violations 73511103Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.squashedStores 8196884 # Number of stores squashed 73610585Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 73710585Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 73811103Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.rescheduledLoads 3577769 # Number of loads that were rescheduled 73911103Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.cacheBlocked 1870440 # Number of times an access to memory failed due to the cache being blocked 74010585Sandreas.hansson@arm.comsystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 74111103Snilay@cs.wisc.edusystem.cpu.iew.iewSquashCycles 10557931 # Number of cycles IEW is squashing 74211103Snilay@cs.wisc.edusystem.cpu.iew.iewBlockCycles 12374030 # Number of cycles IEW is blocking 74311103Snilay@cs.wisc.edusystem.cpu.iew.iewUnblockCycles 7706525 # Number of cycles IEW is unblocking 74411103Snilay@cs.wisc.edusystem.cpu.iew.iewDispatchedInsts 1371058602 # Number of instructions dispatched to IQ 74510585Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 74611103Snilay@cs.wisc.edusystem.cpu.iew.iewDispLoadInsts 221659276 # Number of dispatched load instructions 74711103Snilay@cs.wisc.edusystem.cpu.iew.iewDispStoreInsts 196613901 # Number of dispatched store instructions 74811103Snilay@cs.wisc.edusystem.cpu.iew.iewDispNonSpecInsts 38550114 # Number of dispatched non-speculative instructions 74911103Snilay@cs.wisc.edusystem.cpu.iew.iewIQFullEvents 178028 # Number of times the IQ has become full, causing a stall 75011103Snilay@cs.wisc.edusystem.cpu.iew.iewLSQFullEvents 7343410 # Number of times the LSQ has become full, causing a stall 75111103Snilay@cs.wisc.edusystem.cpu.iew.memOrderViolationEvents 184211 # Number of memory order violations 75211103Snilay@cs.wisc.edusystem.cpu.iew.predictedTakenIncorrect 4239042 # Number of branches that were predicted taken incorrectly 75311103Snilay@cs.wisc.edusystem.cpu.iew.predictedNotTakenIncorrect 5703306 # Number of branches that were predicted not taken incorrectly 75411103Snilay@cs.wisc.edusystem.cpu.iew.branchMispredicts 9942348 # Number of branch mispredicts detected at execute 75511103Snilay@cs.wisc.edusystem.cpu.iew.iewExecutedInsts 1343677933 # Number of executed instructions 75611103Snilay@cs.wisc.edusystem.cpu.iew.iewExecLoadInsts 217120223 # Number of load instructions executed 75711103Snilay@cs.wisc.edusystem.cpu.iew.iewExecSquashedInsts 11882036 # Number of squashed instructions skipped in execute 75810585Sandreas.hansson@arm.comsystem.cpu.iew.exec_swp 0 # number of swp insts executed 75911103Snilay@cs.wisc.edusystem.cpu.iew.exec_nop 272684 # number of nop insts executed 76011103Snilay@cs.wisc.edusystem.cpu.iew.exec_refs 409245203 # number of memory reference insts executed 76111103Snilay@cs.wisc.edusystem.cpu.iew.exec_branches 255119365 # Number of branches executed 76211103Snilay@cs.wisc.edusystem.cpu.iew.exec_stores 192124980 # Number of stores executed 76311103Snilay@cs.wisc.edusystem.cpu.iew.exec_rate 0.627523 # Inst execution rate 76411103Snilay@cs.wisc.edusystem.cpu.iew.wb_sent 1337102879 # cumulative count of insts sent to commit 76511103Snilay@cs.wisc.edusystem.cpu.iew.wb_count 1336077728 # cumulative count of insts written-back 76611103Snilay@cs.wisc.edusystem.cpu.iew.wb_producers 573421420 # num instructions producing a value 76711103Snilay@cs.wisc.edusystem.cpu.iew.wb_consumers 940568778 # num instructions consuming a value 76810585Sandreas.hansson@arm.comsystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 76911103Snilay@cs.wisc.edusystem.cpu.iew.wb_rate 0.623974 # insts written-back per cycle 77011103Snilay@cs.wisc.edusystem.cpu.iew.wb_fanout 0.609654 # average fanout of values written-back 77110585Sandreas.hansson@arm.comsystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 77211103Snilay@cs.wisc.edusystem.cpu.commit.commitSquashedInsts 62140410 # The number of squashed insts skipped by commit 77311103Snilay@cs.wisc.edusystem.cpu.commit.commitNonSpecStalls 43476630 # The number of times commit has been forced to stall to communicate backwards 77411103Snilay@cs.wisc.edusystem.cpu.commit.branchMispredicts 9519542 # The number of times a branch was mispredicted 77511103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::samples 2071346493 # Number of insts commited each cycle 77611103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::mean 0.626687 # Number of insts commited each cycle 77711103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::stdev 1.267080 # Number of insts commited each cycle 77810585Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 77911103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::0 1395640231 67.38% 67.38% # Number of insts commited each cycle 78011103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::1 393909449 19.02% 86.40% # Number of insts commited each cycle 78111103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::2 150461425 7.26% 93.66% # Number of insts commited each cycle 78211103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::3 44316735 2.14% 95.80% # Number of insts commited each cycle 78311103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::4 35977476 1.74% 97.54% # Number of insts commited each cycle 78411103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::5 18232281 0.88% 98.42% # Number of insts commited each cycle 78511103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::6 10892931 0.53% 98.94% # Number of insts commited each cycle 78611103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::7 5452952 0.26% 99.21% # Number of insts commited each cycle 78711103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::8 16463013 0.79% 100.00% # Number of insts commited each cycle 78810585Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 78910585Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 79010585Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 79111103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::total 2071346493 # Number of insts commited each cycle 79211103Snilay@cs.wisc.edusystem.cpu.commit.committedInsts 1104366834 # Number of instructions committed 79311103Snilay@cs.wisc.edusystem.cpu.commit.committedOps 1298086167 # Number of ops (including micro ops) committed 79410585Sandreas.hansson@arm.comsystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 79511103Snilay@cs.wisc.edusystem.cpu.commit.refs 393173853 # Number of memory references committed 79611103Snilay@cs.wisc.edusystem.cpu.commit.loads 204756836 # Number of loads committed 79711103Snilay@cs.wisc.edusystem.cpu.commit.membars 9104821 # Number of memory barriers committed 79811103Snilay@cs.wisc.edusystem.cpu.commit.branches 246834909 # Number of branches committed 79911103Snilay@cs.wisc.edusystem.cpu.commit.fp_insts 874964 # Number of committed floating point instructions. 80011103Snilay@cs.wisc.edusystem.cpu.commit.int_insts 1186447841 # Number of committed integer instructions. 80111103Snilay@cs.wisc.edusystem.cpu.commit.function_calls 30876862 # Number of function calls committed. 80210585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 80311103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::IntAlu 902159630 69.50% 69.50% # Class of committed instruction 80411103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::IntMult 2542825 0.20% 69.70% # Class of committed instruction 80511103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::IntDiv 103949 0.01% 69.70% # Class of committed instruction 80611103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.70% # Class of committed instruction 80711103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.70% # Class of committed instruction 80811103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.70% # Class of committed instruction 80911103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatMult 0 0.00% 69.70% # Class of committed instruction 81011103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.70% # Class of committed instruction 81111103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.70% # Class of committed instruction 81211103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.70% # Class of committed instruction 81311103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.70% # Class of committed instruction 81411103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.70% # Class of committed instruction 81511103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.70% # Class of committed instruction 81611103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.70% # Class of committed instruction 81711103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.70% # Class of committed instruction 81811103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdMult 0 0.00% 69.70% # Class of committed instruction 81911103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.70% # Class of committed instruction 82011103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdShift 0 0.00% 69.70% # Class of committed instruction 82111103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.70% # Class of committed instruction 82211103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.70% # Class of committed instruction 82311103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.70% # Class of committed instruction 82411103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.70% # Class of committed instruction 82511103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.70% # Class of committed instruction 82611103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.70% # Class of committed instruction 82711103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.70% # Class of committed instruction 82811103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatMisc 105868 0.01% 69.71% # Class of committed instruction 82911103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.71% # Class of committed instruction 83011103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.71% # Class of committed instruction 83111103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.71% # Class of committed instruction 83211103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::MemRead 204756836 15.77% 85.49% # Class of committed instruction 83311103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::MemWrite 188417017 14.51% 100.00% # Class of committed instruction 83410585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 83510585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 83611103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::total 1298086167 # Class of committed instruction 83711103Snilay@cs.wisc.edusystem.cpu.commit.bw_lim_events 16463013 # number cycles where commit BW limit reached 83811103Snilay@cs.wisc.edusystem.cpu.rob.rob_reads 3405665880 # The number of ROB reads 83911103Snilay@cs.wisc.edusystem.cpu.rob.rob_writes 2734432791 # The number of ROB writes 84011103Snilay@cs.wisc.edusystem.cpu.timesIdled 9009507 # Number of times that the entire CPU went into an idle state and unscheduled itself 84111103Snilay@cs.wisc.edusystem.cpu.idleCycles 55804351 # Total number of cycles that the CPU has spent unscheduled due to idling 84211103Snilay@cs.wisc.edusystem.cpu.quiesceCycles 100983102115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 84311103Snilay@cs.wisc.edusystem.cpu.committedInsts 1104366834 # Number of Instructions Simulated 84411103Snilay@cs.wisc.edusystem.cpu.committedOps 1298086167 # Number of Ops (including micro ops) Simulated 84511103Snilay@cs.wisc.edusystem.cpu.cpi 1.938885 # CPI: Cycles Per Instruction 84611103Snilay@cs.wisc.edusystem.cpu.cpi_total 1.938885 # CPI: Total CPI of All Threads 84711103Snilay@cs.wisc.edusystem.cpu.ipc 0.515760 # IPC: Instructions Per Cycle 84811103Snilay@cs.wisc.edusystem.cpu.ipc_total 0.515760 # IPC: Total IPC of All Threads 84911103Snilay@cs.wisc.edusystem.cpu.int_regfile_reads 1596434625 # number of integer regfile reads 85011103Snilay@cs.wisc.edusystem.cpu.int_regfile_writes 940526203 # number of integer regfile writes 85111103Snilay@cs.wisc.edusystem.cpu.fp_regfile_reads 1424965 # number of floating regfile reads 85211103Snilay@cs.wisc.edusystem.cpu.fp_regfile_writes 765828 # number of floating regfile writes 85311103Snilay@cs.wisc.edusystem.cpu.cc_regfile_reads 311708448 # number of cc regfile reads 85411103Snilay@cs.wisc.edusystem.cpu.cc_regfile_writes 312593649 # number of cc regfile writes 85511103Snilay@cs.wisc.edusystem.cpu.misc_regfile_reads 3410532874 # number of misc regfile reads 85611103Snilay@cs.wisc.edusystem.cpu.misc_regfile_writes 44362921 # number of misc regfile writes 85711103Snilay@cs.wisc.edusystem.cpu.dcache.tags.replacements 13614186 # number of replacements 85811103Snilay@cs.wisc.edusystem.cpu.dcache.tags.tagsinuse 511.983787 # Cycle average of tags in use 85911103Snilay@cs.wisc.edusystem.cpu.dcache.tags.total_refs 360288791 # Total number of references to valid blocks. 86011103Snilay@cs.wisc.edusystem.cpu.dcache.tags.sampled_refs 13614698 # Sample count of references to valid blocks. 86111103Snilay@cs.wisc.edusystem.cpu.dcache.tags.avg_refs 26.463223 # Average number of references to valid blocks. 86210892Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 1642601500 # Cycle when the warmup percentage was hit. 86311103Snilay@cs.wisc.edusystem.cpu.dcache.tags.occ_blocks::cpu.data 511.983787 # Average occupied blocks per requestor 86410726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999968 # Average percentage of cache occupancy 86510726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy 86610585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 86711103Snilay@cs.wisc.edusystem.cpu.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id 86810892Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id 86911103Snilay@cs.wisc.edusystem.cpu.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id 87011103Snilay@cs.wisc.edusystem.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 87110585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 87211103Snilay@cs.wisc.edusystem.cpu.dcache.tags.tag_accesses 1595334423 # Number of tag accesses 87311103Snilay@cs.wisc.edusystem.cpu.dcache.tags.data_accesses 1595334423 # Number of data accesses 87411103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_hits::cpu.data 186468319 # number of ReadReq hits 87511103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_hits::total 186468319 # number of ReadReq hits 87611103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::cpu.data 162903680 # number of WriteReq hits 87711103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::total 162903680 # number of WriteReq hits 87811103Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_hits::cpu.data 463393 # number of SoftPFReq hits 87911103Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_hits::total 463393 # number of SoftPFReq hits 88011103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_hits::cpu.data 334025 # number of WriteLineReq hits 88111103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_hits::total 334025 # number of WriteLineReq hits 88211103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_hits::cpu.data 4787397 # number of LoadLockedReq hits 88311103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_hits::total 4787397 # number of LoadLockedReq hits 88411103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_hits::cpu.data 5271269 # number of StoreCondReq hits 88511103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_hits::total 5271269 # number of StoreCondReq hits 88611103Snilay@cs.wisc.edusystem.cpu.dcache.demand_hits::cpu.data 349371999 # number of demand (read+write) hits 88711103Snilay@cs.wisc.edusystem.cpu.dcache.demand_hits::total 349371999 # number of demand (read+write) hits 88811103Snilay@cs.wisc.edusystem.cpu.dcache.overall_hits::cpu.data 349835392 # number of overall hits 88911103Snilay@cs.wisc.edusystem.cpu.dcache.overall_hits::total 349835392 # number of overall hits 89011103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::cpu.data 12723000 # number of ReadReq misses 89111103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::total 12723000 # number of ReadReq misses 89211103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::cpu.data 18625078 # number of WriteReq misses 89311103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::total 18625078 # number of WriteReq misses 89411103Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_misses::cpu.data 2035956 # number of SoftPFReq misses 89511103Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_misses::total 2035956 # number of SoftPFReq misses 89611103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_misses::cpu.data 1270469 # number of WriteLineReq misses 89711103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_misses::total 1270469 # number of WriteLineReq misses 89811103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_misses::cpu.data 547335 # number of LoadLockedReq misses 89911103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_misses::total 547335 # number of LoadLockedReq misses 90010892Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::cpu.data 7 # number of StoreCondReq misses 90110892Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses 90211103Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::cpu.data 31348078 # number of demand (read+write) misses 90311103Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::total 31348078 # number of demand (read+write) misses 90411103Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::cpu.data 33384034 # number of overall misses 90511103Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::total 33384034 # number of overall misses 90611103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_latency::cpu.data 203343916000 # number of ReadReq miss cycles 90711103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_latency::total 203343916000 # number of ReadReq miss cycles 90811103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_latency::cpu.data 979374659621 # number of WriteReq miss cycles 90911103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_latency::total 979374659621 # number of WriteReq miss cycles 91011103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_miss_latency::cpu.data 74427778402 # number of WriteLineReq miss cycles 91111103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_miss_latency::total 74427778402 # number of WriteLineReq miss cycles 91211103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 8800618500 # number of LoadLockedReq miss cycles 91311103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_miss_latency::total 8800618500 # number of LoadLockedReq miss cycles 91410892Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::cpu.data 251000 # number of StoreCondReq miss cycles 91510892Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::total 251000 # number of StoreCondReq miss cycles 91611103Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_latency::cpu.data 1182718575621 # number of demand (read+write) miss cycles 91711103Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_latency::total 1182718575621 # number of demand (read+write) miss cycles 91811103Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_latency::cpu.data 1182718575621 # number of overall miss cycles 91911103Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_latency::total 1182718575621 # number of overall miss cycles 92011103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_accesses::cpu.data 199191319 # number of ReadReq accesses(hits+misses) 92111103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_accesses::total 199191319 # number of ReadReq accesses(hits+misses) 92211103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_accesses::cpu.data 181528758 # number of WriteReq accesses(hits+misses) 92311103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_accesses::total 181528758 # number of WriteReq accesses(hits+misses) 92411103Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_accesses::cpu.data 2499349 # number of SoftPFReq accesses(hits+misses) 92511103Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_accesses::total 2499349 # number of SoftPFReq accesses(hits+misses) 92611103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_accesses::cpu.data 1604494 # number of WriteLineReq accesses(hits+misses) 92711103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_accesses::total 1604494 # number of WriteLineReq accesses(hits+misses) 92811103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 5334732 # number of LoadLockedReq accesses(hits+misses) 92911103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_accesses::total 5334732 # number of LoadLockedReq accesses(hits+misses) 93011103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_accesses::cpu.data 5271276 # number of StoreCondReq accesses(hits+misses) 93111103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_accesses::total 5271276 # number of StoreCondReq accesses(hits+misses) 93211103Snilay@cs.wisc.edusystem.cpu.dcache.demand_accesses::cpu.data 380720077 # number of demand (read+write) accesses 93311103Snilay@cs.wisc.edusystem.cpu.dcache.demand_accesses::total 380720077 # number of demand (read+write) accesses 93411103Snilay@cs.wisc.edusystem.cpu.dcache.overall_accesses::cpu.data 383219426 # number of overall (read+write) accesses 93511103Snilay@cs.wisc.edusystem.cpu.dcache.overall_accesses::total 383219426 # number of overall (read+write) accesses 93611103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.063873 # miss rate for ReadReq accesses 93711103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_rate::total 0.063873 # miss rate for ReadReq accesses 93811103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.102601 # miss rate for WriteReq accesses 93911103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::total 0.102601 # miss rate for WriteReq accesses 94011103Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.814595 # miss rate for SoftPFReq accesses 94111103Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_miss_rate::total 0.814595 # miss rate for SoftPFReq accesses 94211103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791819 # miss rate for WriteLineReq accesses 94311103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_miss_rate::total 0.791819 # miss rate for WriteLineReq accesses 94411103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.102598 # miss rate for LoadLockedReq accesses 94511103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.102598 # miss rate for LoadLockedReq accesses 94611103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses 94711103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses 94811103Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_rate::cpu.data 0.082339 # miss rate for demand accesses 94911103Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_rate::total 0.082339 # miss rate for demand accesses 95011103Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_rate::cpu.data 0.087115 # miss rate for overall accesses 95111103Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_rate::total 0.087115 # miss rate for overall accesses 95211103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15982.387487 # average ReadReq miss latency 95311103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_miss_latency::total 15982.387487 # average ReadReq miss latency 95411103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52583.654126 # average WriteReq miss latency 95511103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_miss_latency::total 52583.654126 # average WriteReq miss latency 95611103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 58582.915759 # average WriteLineReq miss latency 95711103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_avg_miss_latency::total 58582.915759 # average WriteLineReq miss latency 95811103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16079.034778 # average LoadLockedReq miss latency 95911103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16079.034778 # average LoadLockedReq miss latency 96010892Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 35857.142857 # average StoreCondReq miss latency 96110892Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::total 35857.142857 # average StoreCondReq miss latency 96211103Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_miss_latency::cpu.data 37728.583412 # average overall miss latency 96311103Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_miss_latency::total 37728.583412 # average overall miss latency 96411103Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_miss_latency::cpu.data 35427.671072 # average overall miss latency 96511103Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_miss_latency::total 35427.671072 # average overall miss latency 96611103Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_mshrs 46020939 # number of cycles access was blocked 96710585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 96811103Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_mshrs 2096301 # number of cycles access was blocked 96910585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 97011103Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_mshrs 21.953402 # average number of cycles each access was blocked 97110585Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 97210585Sandreas.hansson@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 97310585Sandreas.hansson@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 97411103Snilay@cs.wisc.edusystem.cpu.dcache.writebacks::writebacks 10299062 # number of writebacks 97511103Snilay@cs.wisc.edusystem.cpu.dcache.writebacks::total 10299062 # number of writebacks 97611103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 5706012 # number of ReadReq MSHR hits 97711103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_hits::total 5706012 # number of ReadReq MSHR hits 97811103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 15543150 # number of WriteReq MSHR hits 97911103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_hits::total 15543150 # number of WriteReq MSHR hits 98011103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7171 # number of WriteLineReq MSHR hits 98111103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_mshr_hits::total 7171 # number of WriteLineReq MSHR hits 98211103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 263403 # number of LoadLockedReq MSHR hits 98311103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_mshr_hits::total 263403 # number of LoadLockedReq MSHR hits 98411103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_hits::cpu.data 21249162 # number of demand (read+write) MSHR hits 98511103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_hits::total 21249162 # number of demand (read+write) MSHR hits 98611103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_hits::cpu.data 21249162 # number of overall MSHR hits 98711103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_hits::total 21249162 # number of overall MSHR hits 98811103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 7016988 # number of ReadReq MSHR misses 98911103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_misses::total 7016988 # number of ReadReq MSHR misses 99011103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 3081928 # number of WriteReq MSHR misses 99111103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_misses::total 3081928 # number of WriteReq MSHR misses 99211103Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 2029224 # number of SoftPFReq MSHR misses 99311103Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_mshr_misses::total 2029224 # number of SoftPFReq MSHR misses 99411103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1263298 # number of WriteLineReq MSHR misses 99511103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_mshr_misses::total 1263298 # number of WriteLineReq MSHR misses 99611103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 283932 # number of LoadLockedReq MSHR misses 99711103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_mshr_misses::total 283932 # number of LoadLockedReq MSHR misses 99810892Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 7 # number of StoreCondReq MSHR misses 99910892Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses 100011103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_misses::cpu.data 10098916 # number of demand (read+write) MSHR misses 100111103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_misses::total 10098916 # number of demand (read+write) MSHR misses 100211103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_misses::cpu.data 12128140 # number of overall MSHR misses 100311103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_misses::total 12128140 # number of overall MSHR misses 100411103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33692 # number of ReadReq MSHR uncacheable 100511103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_uncacheable::total 33692 # number of ReadReq MSHR uncacheable 100611103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33703 # number of WriteReq MSHR uncacheable 100711103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_uncacheable::total 33703 # number of WriteReq MSHR uncacheable 100811103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67395 # number of overall MSHR uncacheable misses 100911103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_uncacheable_misses::total 67395 # number of overall MSHR uncacheable misses 101011103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109410315500 # number of ReadReq MSHR miss cycles 101111103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_latency::total 109410315500 # number of ReadReq MSHR miss cycles 101211103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 144646896672 # number of WriteReq MSHR miss cycles 101311103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_latency::total 144646896672 # number of WriteReq MSHR miss cycles 101411103Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 32373018500 # number of SoftPFReq MSHR miss cycles 101511103Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 32373018500 # number of SoftPFReq MSHR miss cycles 101611103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 72874671402 # number of WriteLineReq MSHR miss cycles 101711103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_mshr_miss_latency::total 72874671402 # number of WriteLineReq MSHR miss cycles 101811103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 4076865500 # number of LoadLockedReq MSHR miss cycles 101911103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 4076865500 # number of LoadLockedReq MSHR miss cycles 102010892Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 244000 # number of StoreCondReq MSHR miss cycles 102110892Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::total 244000 # number of StoreCondReq MSHR miss cycles 102211103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 254057212172 # number of demand (read+write) MSHR miss cycles 102311103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_latency::total 254057212172 # number of demand (read+write) MSHR miss cycles 102411103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 286430230672 # number of overall MSHR miss cycles 102511103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_latency::total 286430230672 # number of overall MSHR miss cycles 102611103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5829096500 # number of ReadReq MSHR uncacheable cycles 102711103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5829096500 # number of ReadReq MSHR uncacheable cycles 102811103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5708243467 # number of WriteReq MSHR uncacheable cycles 102911103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5708243467 # number of WriteReq MSHR uncacheable cycles 103011103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11537339967 # number of overall MSHR uncacheable cycles 103111103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_uncacheable_latency::total 11537339967 # number of overall MSHR uncacheable cycles 103211103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035227 # mshr miss rate for ReadReq accesses 103311103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035227 # mshr miss rate for ReadReq accesses 103411103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016978 # mshr miss rate for WriteReq accesses 103511103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016978 # mshr miss rate for WriteReq accesses 103611103Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.811901 # mshr miss rate for SoftPFReq accesses 103711103Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.811901 # mshr miss rate for SoftPFReq accesses 103811103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787350 # mshr miss rate for WriteLineReq accesses 103911103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787350 # mshr miss rate for WriteLineReq accesses 104011103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.053223 # mshr miss rate for LoadLockedReq accesses 104111103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.053223 # mshr miss rate for LoadLockedReq accesses 104211103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses 104311103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses 104411103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026526 # mshr miss rate for demand accesses 104511103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_rate::total 0.026526 # mshr miss rate for demand accesses 104611103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031648 # mshr miss rate for overall accesses 104711103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_rate::total 0.031648 # mshr miss rate for overall accesses 104811103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15592.205017 # average ReadReq mshr miss latency 104911103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15592.205017 # average ReadReq mshr miss latency 105011103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46933.898739 # average WriteReq mshr miss latency 105111103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46933.898739 # average WriteReq mshr miss latency 105211103Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15953.398196 # average SoftPFReq mshr miss latency 105311103Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15953.398196 # average SoftPFReq mshr miss latency 105411103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 57686.049849 # average WriteLineReq mshr miss latency 105511103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 57686.049849 # average WriteLineReq mshr miss latency 105611103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14358.598185 # average LoadLockedReq mshr miss latency 105711103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14358.598185 # average LoadLockedReq mshr miss latency 105810892Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 34857.142857 # average StoreCondReq mshr miss latency 105910892Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 34857.142857 # average StoreCondReq mshr miss latency 106011103Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25156.879429 # average overall mshr miss latency 106111103Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_mshr_miss_latency::total 25156.879429 # average overall mshr miss latency 106211103Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23616.995737 # average overall mshr miss latency 106311103Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_mshr_miss_latency::total 23616.995737 # average overall mshr miss latency 106411103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173011.293482 # average ReadReq mshr uncacheable latency 106511103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173011.293482 # average ReadReq mshr uncacheable latency 106611103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 169369.001780 # average WriteReq mshr uncacheable latency 106711103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169369.001780 # average WriteReq mshr uncacheable latency 106811103Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171189.850389 # average overall mshr uncacheable latency 106911103Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171189.850389 # average overall mshr uncacheable latency 107010585Sandreas.hansson@arm.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 107111103Snilay@cs.wisc.edusystem.cpu.icache.tags.replacements 16756542 # number of replacements 107211103Snilay@cs.wisc.edusystem.cpu.icache.tags.tagsinuse 511.945135 # Cycle average of tags in use 107311103Snilay@cs.wisc.edusystem.cpu.icache.tags.total_refs 443237235 # Total number of references to valid blocks. 107411103Snilay@cs.wisc.edusystem.cpu.icache.tags.sampled_refs 16757054 # Sample count of references to valid blocks. 107511103Snilay@cs.wisc.edusystem.cpu.icache.tags.avg_refs 26.450785 # Average number of references to valid blocks. 107610892Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 17214303500 # Cycle when the warmup percentage was hit. 107711103Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_blocks::cpu.inst 511.945135 # Average occupied blocks per requestor 107811103Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_percent::cpu.inst 0.999893 # Average percentage of cache occupancy 107911103Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_percent::total 0.999893 # Average percentage of cache occupancy 108010585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 108111103Snilay@cs.wisc.edusystem.cpu.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id 108211103Snilay@cs.wisc.edusystem.cpu.icache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id 108311103Snilay@cs.wisc.edusystem.cpu.icache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id 108410585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 108511103Snilay@cs.wisc.edusystem.cpu.icache.tags.tag_accesses 477553750 # Number of tag accesses 108611103Snilay@cs.wisc.edusystem.cpu.icache.tags.data_accesses 477553750 # Number of data accesses 108711103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_hits::cpu.inst 443237235 # number of ReadReq hits 108811103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_hits::total 443237235 # number of ReadReq hits 108911103Snilay@cs.wisc.edusystem.cpu.icache.demand_hits::cpu.inst 443237235 # number of demand (read+write) hits 109011103Snilay@cs.wisc.edusystem.cpu.icache.demand_hits::total 443237235 # number of demand (read+write) hits 109111103Snilay@cs.wisc.edusystem.cpu.icache.overall_hits::cpu.inst 443237235 # number of overall hits 109211103Snilay@cs.wisc.edusystem.cpu.icache.overall_hits::total 443237235 # number of overall hits 109311103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_misses::cpu.inst 17559241 # number of ReadReq misses 109411103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_misses::total 17559241 # number of ReadReq misses 109511103Snilay@cs.wisc.edusystem.cpu.icache.demand_misses::cpu.inst 17559241 # number of demand (read+write) misses 109611103Snilay@cs.wisc.edusystem.cpu.icache.demand_misses::total 17559241 # number of demand (read+write) misses 109711103Snilay@cs.wisc.edusystem.cpu.icache.overall_misses::cpu.inst 17559241 # number of overall misses 109811103Snilay@cs.wisc.edusystem.cpu.icache.overall_misses::total 17559241 # number of overall misses 109911103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_latency::cpu.inst 232141013891 # number of ReadReq miss cycles 110011103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_latency::total 232141013891 # number of ReadReq miss cycles 110111103Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_latency::cpu.inst 232141013891 # number of demand (read+write) miss cycles 110211103Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_latency::total 232141013891 # number of demand (read+write) miss cycles 110311103Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_latency::cpu.inst 232141013891 # number of overall miss cycles 110411103Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_latency::total 232141013891 # number of overall miss cycles 110511103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_accesses::cpu.inst 460796476 # number of ReadReq accesses(hits+misses) 110611103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_accesses::total 460796476 # number of ReadReq accesses(hits+misses) 110711103Snilay@cs.wisc.edusystem.cpu.icache.demand_accesses::cpu.inst 460796476 # number of demand (read+write) accesses 110811103Snilay@cs.wisc.edusystem.cpu.icache.demand_accesses::total 460796476 # number of demand (read+write) accesses 110911103Snilay@cs.wisc.edusystem.cpu.icache.overall_accesses::cpu.inst 460796476 # number of overall (read+write) accesses 111011103Snilay@cs.wisc.edusystem.cpu.icache.overall_accesses::total 460796476 # number of overall (read+write) accesses 111111103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.038106 # miss rate for ReadReq accesses 111211103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_rate::total 0.038106 # miss rate for ReadReq accesses 111311103Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_rate::cpu.inst 0.038106 # miss rate for demand accesses 111411103Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_rate::total 0.038106 # miss rate for demand accesses 111511103Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_rate::cpu.inst 0.038106 # miss rate for overall accesses 111611103Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_rate::total 0.038106 # miss rate for overall accesses 111711103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13220.446937 # average ReadReq miss latency 111811103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_avg_miss_latency::total 13220.446937 # average ReadReq miss latency 111911103Snilay@cs.wisc.edusystem.cpu.icache.demand_avg_miss_latency::cpu.inst 13220.446937 # average overall miss latency 112011103Snilay@cs.wisc.edusystem.cpu.icache.demand_avg_miss_latency::total 13220.446937 # average overall miss latency 112111103Snilay@cs.wisc.edusystem.cpu.icache.overall_avg_miss_latency::cpu.inst 13220.446937 # average overall miss latency 112211103Snilay@cs.wisc.edusystem.cpu.icache.overall_avg_miss_latency::total 13220.446937 # average overall miss latency 112311103Snilay@cs.wisc.edusystem.cpu.icache.blocked_cycles::no_mshrs 15959 # number of cycles access was blocked 112410585Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 112511103Snilay@cs.wisc.edusystem.cpu.icache.blocked::no_mshrs 1225 # number of cycles access was blocked 112610585Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 112711103Snilay@cs.wisc.edusystem.cpu.icache.avg_blocked_cycles::no_mshrs 13.027755 # average number of cycles each access was blocked 112810585Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 112910585Sandreas.hansson@arm.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 113010585Sandreas.hansson@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 113111103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 801966 # number of ReadReq MSHR hits 113211103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_hits::total 801966 # number of ReadReq MSHR hits 113311103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_hits::cpu.inst 801966 # number of demand (read+write) MSHR hits 113411103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_hits::total 801966 # number of demand (read+write) MSHR hits 113511103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_hits::cpu.inst 801966 # number of overall MSHR hits 113611103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_hits::total 801966 # number of overall MSHR hits 113711103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 16757275 # number of ReadReq MSHR misses 113811103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_misses::total 16757275 # number of ReadReq MSHR misses 113911103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_misses::cpu.inst 16757275 # number of demand (read+write) MSHR misses 114011103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_misses::total 16757275 # number of demand (read+write) MSHR misses 114111103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_misses::cpu.inst 16757275 # number of overall MSHR misses 114211103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_misses::total 16757275 # number of overall MSHR misses 114310827Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21295 # number of ReadReq MSHR uncacheable 114410827Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable::total 21295 # number of ReadReq MSHR uncacheable 114510827Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21295 # number of overall MSHR uncacheable misses 114610827Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_misses::total 21295 # number of overall MSHR uncacheable misses 114711103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 208567956898 # number of ReadReq MSHR miss cycles 114811103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_miss_latency::total 208567956898 # number of ReadReq MSHR miss cycles 114911103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 208567956898 # number of demand (read+write) MSHR miss cycles 115011103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_miss_latency::total 208567956898 # number of demand (read+write) MSHR miss cycles 115111103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 208567956898 # number of overall MSHR miss cycles 115211103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_miss_latency::total 208567956898 # number of overall MSHR miss cycles 115310892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1594412000 # number of ReadReq MSHR uncacheable cycles 115410892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1594412000 # number of ReadReq MSHR uncacheable cycles 115510892Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1594412000 # number of overall MSHR uncacheable cycles 115610892Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_latency::total 1594412000 # number of overall MSHR uncacheable cycles 115711103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.036366 # mshr miss rate for ReadReq accesses 115811103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.036366 # mshr miss rate for ReadReq accesses 115911103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.036366 # mshr miss rate for demand accesses 116011103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_miss_rate::total 0.036366 # mshr miss rate for demand accesses 116111103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.036366 # mshr miss rate for overall accesses 116211103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_miss_rate::total 0.036366 # mshr miss rate for overall accesses 116311103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12446.412492 # average ReadReq mshr miss latency 116411103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12446.412492 # average ReadReq mshr miss latency 116511103Snilay@cs.wisc.edusystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12446.412492 # average overall mshr miss latency 116611103Snilay@cs.wisc.edusystem.cpu.icache.demand_avg_mshr_miss_latency::total 12446.412492 # average overall mshr miss latency 116711103Snilay@cs.wisc.edusystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12446.412492 # average overall mshr miss latency 116811103Snilay@cs.wisc.edusystem.cpu.icache.overall_avg_mshr_miss_latency::total 12446.412492 # average overall mshr miss latency 116910892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74872.599202 # average ReadReq mshr uncacheable latency 117010892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 74872.599202 # average ReadReq mshr uncacheable latency 117110892Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74872.599202 # average overall mshr uncacheable latency 117210892Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74872.599202 # average overall mshr uncacheable latency 117310585Sandreas.hansson@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 117411103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.replacements 2345734 # number of replacements 117511103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.tagsinuse 65318.237935 # Cycle average of tags in use 117611103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.total_refs 55622573 # Total number of references to valid blocks. 117711103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.sampled_refs 2409067 # Sample count of references to valid blocks. 117811103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.avg_refs 23.088844 # Average number of references to valid blocks. 117910892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 15659706000 # Cycle when the warmup percentage was hit. 118011103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_blocks::writebacks 35816.547430 # Average occupied blocks per requestor 118111103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 265.508156 # Average occupied blocks per requestor 118211103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 348.644093 # Average occupied blocks per requestor 118311103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_blocks::cpu.inst 6890.433367 # Average occupied blocks per requestor 118411103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_blocks::cpu.data 21997.104889 # Average occupied blocks per requestor 118511103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_percent::writebacks 0.546517 # Average percentage of cache occupancy 118611103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004051 # Average percentage of cache occupancy 118711103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.005320 # Average percentage of cache occupancy 118811103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.105140 # Average percentage of cache occupancy 118911103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_percent::cpu.data 0.335649 # Average percentage of cache occupancy 119011103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_percent::total 0.996677 # Average percentage of cache occupancy 119111103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_task_id_blocks::1023 240 # Occupied blocks per task id 119211103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_task_id_blocks::1024 63093 # Occupied blocks per task id 119311103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.age_task_id_blocks_1023::4 240 # Occupied blocks per task id 119411103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id 119511103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 558 # Occupied blocks per task id 119611103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 2664 # Occupied blocks per task id 119711103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 5217 # Occupied blocks per task id 119811103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 54586 # Occupied blocks per task id 119911103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_task_id_percent::1023 0.003662 # Percentage of cache occupancy per task id 120011103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.962723 # Percentage of cache occupancy per task id 120111103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.tag_accesses 506469360 # Number of tag accesses 120211103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.data_accesses 506469360 # Number of data accesses 120311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 1313351 # number of ReadReq hits 120411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_hits::cpu.itb.walker 329734 # number of ReadReq hits 120511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_hits::total 1643085 # number of ReadReq hits 120611103Snilay@cs.wisc.edusystem.cpu.l2cache.Writeback_hits::writebacks 10299062 # number of Writeback hits 120711103Snilay@cs.wisc.edusystem.cpu.l2cache.Writeback_hits::total 10299062 # number of Writeback hits 120811103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_hits::cpu.data 12887 # number of UpgradeReq hits 120911103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_hits::total 12887 # number of UpgradeReq hits 121010892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::cpu.data 4 # number of SCUpgradeReq hits 121110892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits 121211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_hits::cpu.data 1723701 # number of ReadExReq hits 121311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_hits::total 1723701 # number of ReadExReq hits 121411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16658716 # number of ReadCleanReq hits 121511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_hits::total 16658716 # number of ReadCleanReq hits 121611103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 8894179 # number of ReadSharedReq hits 121711103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_hits::total 8894179 # number of ReadSharedReq hits 121811103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_hits::cpu.data 672751 # number of InvalidateReq hits 121911103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_hits::total 672751 # number of InvalidateReq hits 122011103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_hits::cpu.dtb.walker 1313351 # number of demand (read+write) hits 122111103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_hits::cpu.itb.walker 329734 # number of demand (read+write) hits 122211103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_hits::cpu.inst 16658716 # number of demand (read+write) hits 122311103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_hits::cpu.data 10617880 # number of demand (read+write) hits 122411103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_hits::total 28919681 # number of demand (read+write) hits 122511103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_hits::cpu.dtb.walker 1313351 # number of overall hits 122611103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_hits::cpu.itb.walker 329734 # number of overall hits 122711103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_hits::cpu.inst 16658716 # number of overall hits 122811103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_hits::cpu.data 10617880 # number of overall hits 122911103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_hits::total 28919681 # number of overall hits 123011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 10281 # number of ReadReq misses 123111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_misses::cpu.itb.walker 8711 # number of ReadReq misses 123211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_misses::total 18992 # number of ReadReq misses 123311103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_misses::cpu.data 47777 # number of UpgradeReq misses 123411103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_misses::total 47777 # number of UpgradeReq misses 123510726Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses 123610726Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses 123711103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_misses::cpu.data 1312732 # number of ReadExReq misses 123811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_misses::total 1312732 # number of ReadExReq misses 123911103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 98354 # number of ReadCleanReq misses 124011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_misses::total 98354 # number of ReadCleanReq misses 124111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 420801 # number of ReadSharedReq misses 124211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_misses::total 420801 # number of ReadSharedReq misses 124311103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_misses::cpu.data 590547 # number of InvalidateReq misses 124411103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_misses::total 590547 # number of InvalidateReq misses 124511103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_misses::cpu.dtb.walker 10281 # number of demand (read+write) misses 124611103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_misses::cpu.itb.walker 8711 # number of demand (read+write) misses 124711103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_misses::cpu.inst 98354 # number of demand (read+write) misses 124811103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_misses::cpu.data 1733533 # number of demand (read+write) misses 124911103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_misses::total 1850879 # number of demand (read+write) misses 125011103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_misses::cpu.dtb.walker 10281 # number of overall misses 125111103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_misses::cpu.itb.walker 8711 # number of overall misses 125211103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_misses::cpu.inst 98354 # number of overall misses 125311103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_misses::cpu.data 1733533 # number of overall misses 125411103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_misses::total 1850879 # number of overall misses 125511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 914040000 # number of ReadReq miss cycles 125611103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 769017500 # number of ReadReq miss cycles 125711103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_miss_latency::total 1683057500 # number of ReadReq miss cycles 125811103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 621639500 # number of UpgradeReq miss cycles 125911103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_miss_latency::total 621639500 # number of UpgradeReq miss cycles 126010892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 160500 # number of SCUpgradeReq miss cycles 126110892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::total 160500 # number of SCUpgradeReq miss cycles 126211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 120138160000 # number of ReadExReq miss cycles 126311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_miss_latency::total 120138160000 # number of ReadExReq miss cycles 126411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 8298337000 # number of ReadCleanReq miss cycles 126511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_miss_latency::total 8298337000 # number of ReadCleanReq miss cycles 126611103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 37547469500 # number of ReadSharedReq miss cycles 126711103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_miss_latency::total 37547469500 # number of ReadSharedReq miss cycles 126811103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 62416970000 # number of InvalidateReq miss cycles 126911103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_miss_latency::total 62416970000 # number of InvalidateReq miss cycles 127011103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 914040000 # number of demand (read+write) miss cycles 127111103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_latency::cpu.itb.walker 769017500 # number of demand (read+write) miss cycles 127211103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_latency::cpu.inst 8298337000 # number of demand (read+write) miss cycles 127311103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_latency::cpu.data 157685629500 # number of demand (read+write) miss cycles 127411103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_latency::total 167667024000 # number of demand (read+write) miss cycles 127511103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 914040000 # number of overall miss cycles 127611103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_latency::cpu.itb.walker 769017500 # number of overall miss cycles 127711103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_latency::cpu.inst 8298337000 # number of overall miss cycles 127811103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_latency::cpu.data 157685629500 # number of overall miss cycles 127911103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_latency::total 167667024000 # number of overall miss cycles 128011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 1323632 # number of ReadReq accesses(hits+misses) 128111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 338445 # number of ReadReq accesses(hits+misses) 128211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_accesses::total 1662077 # number of ReadReq accesses(hits+misses) 128311103Snilay@cs.wisc.edusystem.cpu.l2cache.Writeback_accesses::writebacks 10299062 # number of Writeback accesses(hits+misses) 128411103Snilay@cs.wisc.edusystem.cpu.l2cache.Writeback_accesses::total 10299062 # number of Writeback accesses(hits+misses) 128511103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 60664 # number of UpgradeReq accesses(hits+misses) 128611103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_accesses::total 60664 # number of UpgradeReq accesses(hits+misses) 128710892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 7 # number of SCUpgradeReq accesses(hits+misses) 128810892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::total 7 # number of SCUpgradeReq accesses(hits+misses) 128911103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_accesses::cpu.data 3036433 # number of ReadExReq accesses(hits+misses) 129011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_accesses::total 3036433 # number of ReadExReq accesses(hits+misses) 129111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 16757070 # number of ReadCleanReq accesses(hits+misses) 129211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_accesses::total 16757070 # number of ReadCleanReq accesses(hits+misses) 129311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 9314980 # number of ReadSharedReq accesses(hits+misses) 129411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_accesses::total 9314980 # number of ReadSharedReq accesses(hits+misses) 129511103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_accesses::cpu.data 1263298 # number of InvalidateReq accesses(hits+misses) 129611103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_accesses::total 1263298 # number of InvalidateReq accesses(hits+misses) 129711103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_accesses::cpu.dtb.walker 1323632 # number of demand (read+write) accesses 129811103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_accesses::cpu.itb.walker 338445 # number of demand (read+write) accesses 129911103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_accesses::cpu.inst 16757070 # number of demand (read+write) accesses 130011103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_accesses::cpu.data 12351413 # number of demand (read+write) accesses 130111103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_accesses::total 30770560 # number of demand (read+write) accesses 130211103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_accesses::cpu.dtb.walker 1323632 # number of overall (read+write) accesses 130311103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_accesses::cpu.itb.walker 338445 # number of overall (read+write) accesses 130411103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_accesses::cpu.inst 16757070 # number of overall (read+write) accesses 130511103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_accesses::cpu.data 12351413 # number of overall (read+write) accesses 130611103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_accesses::total 30770560 # number of overall (read+write) accesses 130711103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.007767 # miss rate for ReadReq accesses 130811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.025738 # miss rate for ReadReq accesses 130911103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_miss_rate::total 0.011427 # miss rate for ReadReq accesses 131011103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.787568 # miss rate for UpgradeReq accesses 131111103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.787568 # miss rate for UpgradeReq accesses 131210892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.428571 # miss rate for SCUpgradeReq accesses 131310892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.428571 # miss rate for SCUpgradeReq accesses 131411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.432327 # miss rate for ReadExReq accesses 131511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 0.432327 # miss rate for ReadExReq accesses 131611103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005869 # miss rate for ReadCleanReq accesses 131711103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005869 # miss rate for ReadCleanReq accesses 131811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.045175 # miss rate for ReadSharedReq accesses 131911103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.045175 # miss rate for ReadSharedReq accesses 132011103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.467465 # miss rate for InvalidateReq accesses 132111103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_miss_rate::total 0.467465 # miss rate for InvalidateReq accesses 132211103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.007767 # miss rate for demand accesses 132311103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.025738 # miss rate for demand accesses 132411103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.005869 # miss rate for demand accesses 132511103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_rate::cpu.data 0.140351 # miss rate for demand accesses 132611103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_rate::total 0.060151 # miss rate for demand accesses 132711103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.007767 # miss rate for overall accesses 132811103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.025738 # miss rate for overall accesses 132911103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.005869 # miss rate for overall accesses 133011103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_rate::cpu.data 0.140351 # miss rate for overall accesses 133111103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_rate::total 0.060151 # miss rate for overall accesses 133211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 88905.748468 # average ReadReq miss latency 133311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 88281.196189 # average ReadReq miss latency 133411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_avg_miss_latency::total 88619.287068 # average ReadReq miss latency 133511103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 13011.271114 # average UpgradeReq miss latency 133611103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 13011.271114 # average UpgradeReq miss latency 133710892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 53500 # average SCUpgradeReq miss latency 133810892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 53500 # average SCUpgradeReq miss latency 133911103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91517.659355 # average ReadExReq miss latency 134011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 91517.659355 # average ReadExReq miss latency 134111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84372.135348 # average ReadCleanReq miss latency 134211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84372.135348 # average ReadCleanReq miss latency 134311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89228.565284 # average ReadSharedReq miss latency 134411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89228.565284 # average ReadSharedReq miss latency 134511103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 105693.484177 # average InvalidateReq miss latency 134611103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_avg_miss_latency::total 105693.484177 # average InvalidateReq miss latency 134711103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 88905.748468 # average overall miss latency 134811103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 88281.196189 # average overall miss latency 134911103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84372.135348 # average overall miss latency 135011103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 90962.000435 # average overall miss latency 135111103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_miss_latency::total 90587.782346 # average overall miss latency 135211103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 88905.748468 # average overall miss latency 135311103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 88281.196189 # average overall miss latency 135411103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84372.135348 # average overall miss latency 135511103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 90962.000435 # average overall miss latency 135611103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_miss_latency::total 90587.782346 # average overall miss latency 135710585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 135810585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 135910585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 136010585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 136110585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 136210585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 136310585Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 136410585Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 136511103Snilay@cs.wisc.edusystem.cpu.l2cache.writebacks::writebacks 2075008 # number of writebacks 136611103Snilay@cs.wisc.edusystem.cpu.l2cache.writebacks::total 2075008 # number of writebacks 136711103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 22 # number of ReadSharedReq MSHR hits 136811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_mshr_hits::total 22 # number of ReadSharedReq MSHR hits 136911103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_hits::cpu.data 22 # number of demand (read+write) MSHR hits 137011103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits 137111103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_hits::cpu.data 22 # number of overall MSHR hits 137211103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_hits::total 22 # number of overall MSHR hits 137311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 10281 # number of ReadReq MSHR misses 137411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 8711 # number of ReadReq MSHR misses 137511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_misses::total 18992 # number of ReadReq MSHR misses 137611103Snilay@cs.wisc.edusystem.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1261 # number of CleanEvict MSHR misses 137711103Snilay@cs.wisc.edusystem.cpu.l2cache.CleanEvict_mshr_misses::total 1261 # number of CleanEvict MSHR misses 137811103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 47777 # number of UpgradeReq MSHR misses 137911103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_mshr_misses::total 47777 # number of UpgradeReq MSHR misses 138010726Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses 138110726Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses 138211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1312732 # number of ReadExReq MSHR misses 138311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_misses::total 1312732 # number of ReadExReq MSHR misses 138411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 98354 # number of ReadCleanReq MSHR misses 138511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 98354 # number of ReadCleanReq MSHR misses 138611103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 420779 # number of ReadSharedReq MSHR misses 138711103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 420779 # number of ReadSharedReq MSHR misses 138811103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 590547 # number of InvalidateReq MSHR misses 138911103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_mshr_misses::total 590547 # number of InvalidateReq MSHR misses 139011103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 10281 # number of demand (read+write) MSHR misses 139111103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 8711 # number of demand (read+write) MSHR misses 139211103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_misses::cpu.inst 98354 # number of demand (read+write) MSHR misses 139311103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_misses::cpu.data 1733511 # number of demand (read+write) MSHR misses 139411103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_misses::total 1850857 # number of demand (read+write) MSHR misses 139511103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 10281 # number of overall MSHR misses 139611103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 8711 # number of overall MSHR misses 139711103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_misses::cpu.inst 98354 # number of overall MSHR misses 139811103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_misses::cpu.data 1733511 # number of overall MSHR misses 139911103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_misses::total 1850857 # number of overall MSHR misses 140010827Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 21295 # number of ReadReq MSHR uncacheable 140111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33692 # number of ReadReq MSHR uncacheable 140211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_uncacheable::total 54987 # number of ReadReq MSHR uncacheable 140311103Snilay@cs.wisc.edusystem.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33703 # number of WriteReq MSHR uncacheable 140411103Snilay@cs.wisc.edusystem.cpu.l2cache.WriteReq_mshr_uncacheable::total 33703 # number of WriteReq MSHR uncacheable 140510827Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 21295 # number of overall MSHR uncacheable misses 140611103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67395 # number of overall MSHR uncacheable misses 140711103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_uncacheable_misses::total 88690 # number of overall MSHR uncacheable misses 140811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 811230000 # number of ReadReq MSHR miss cycles 140911103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 681907500 # number of ReadReq MSHR miss cycles 141011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 1493137500 # number of ReadReq MSHR miss cycles 141111103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 993052500 # number of UpgradeReq MSHR miss cycles 141211103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 993052500 # number of UpgradeReq MSHR miss cycles 141310892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 161500 # number of SCUpgradeReq MSHR miss cycles 141410892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 161500 # number of SCUpgradeReq MSHR miss cycles 141511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 107010840000 # number of ReadExReq MSHR miss cycles 141611103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 107010840000 # number of ReadExReq MSHR miss cycles 141711103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 7314797000 # number of ReadCleanReq MSHR miss cycles 141811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 7314797000 # number of ReadCleanReq MSHR miss cycles 141911103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 33338388000 # number of ReadSharedReq MSHR miss cycles 142011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 33338388000 # number of ReadSharedReq MSHR miss cycles 142111103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 56511500000 # number of InvalidateReq MSHR miss cycles 142211103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 56511500000 # number of InvalidateReq MSHR miss cycles 142311103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 811230000 # number of demand (read+write) MSHR miss cycles 142411103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 681907500 # number of demand (read+write) MSHR miss cycles 142511103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7314797000 # number of demand (read+write) MSHR miss cycles 142611103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 140349228000 # number of demand (read+write) MSHR miss cycles 142711103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_latency::total 149157162500 # number of demand (read+write) MSHR miss cycles 142811103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 811230000 # number of overall MSHR miss cycles 142911103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 681907500 # number of overall MSHR miss cycles 143011103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7314797000 # number of overall MSHR miss cycles 143111103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 140349228000 # number of overall MSHR miss cycles 143211103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_latency::total 149157162500 # number of overall MSHR miss cycles 143310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1328224500 # number of ReadReq MSHR uncacheable cycles 143411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5407939500 # number of ReadReq MSHR uncacheable cycles 143511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6736164000 # number of ReadReq MSHR uncacheable cycles 143611103Snilay@cs.wisc.edusystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5316157000 # number of WriteReq MSHR uncacheable cycles 143711103Snilay@cs.wisc.edusystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5316157000 # number of WriteReq MSHR uncacheable cycles 143810892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1328224500 # number of overall MSHR uncacheable cycles 143911103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10724096500 # number of overall MSHR uncacheable cycles 144011103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_uncacheable_latency::total 12052321000 # number of overall MSHR uncacheable cycles 144111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.007767 # mshr miss rate for ReadReq accesses 144211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.025738 # mshr miss rate for ReadReq accesses 144311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.011427 # mshr miss rate for ReadReq accesses 144410892Sandreas.hansson@arm.comsystem.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 144510892Sandreas.hansson@arm.comsystem.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 144611103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.787568 # mshr miss rate for UpgradeReq accesses 144711103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.787568 # mshr miss rate for UpgradeReq accesses 144810892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.428571 # mshr miss rate for SCUpgradeReq accesses 144910892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.428571 # mshr miss rate for SCUpgradeReq accesses 145011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.432327 # mshr miss rate for ReadExReq accesses 145111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.432327 # mshr miss rate for ReadExReq accesses 145211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005869 # mshr miss rate for ReadCleanReq accesses 145311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005869 # mshr miss rate for ReadCleanReq accesses 145411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.045172 # mshr miss rate for ReadSharedReq accesses 145511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.045172 # mshr miss rate for ReadSharedReq accesses 145611103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.467465 # mshr miss rate for InvalidateReq accesses 145711103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.467465 # mshr miss rate for InvalidateReq accesses 145811103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.007767 # mshr miss rate for demand accesses 145911103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.025738 # mshr miss rate for demand accesses 146011103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005869 # mshr miss rate for demand accesses 146111103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.140349 # mshr miss rate for demand accesses 146211103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_rate::total 0.060150 # mshr miss rate for demand accesses 146311103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.007767 # mshr miss rate for overall accesses 146411103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.025738 # mshr miss rate for overall accesses 146511103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005869 # mshr miss rate for overall accesses 146611103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.140349 # mshr miss rate for overall accesses 146711103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_rate::total 0.060150 # mshr miss rate for overall accesses 146811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 78905.748468 # average ReadReq mshr miss latency 146911103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 78281.196189 # average ReadReq mshr miss latency 147011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 78619.287068 # average ReadReq mshr miss latency 147111103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20785.158130 # average UpgradeReq mshr miss latency 147211103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20785.158130 # average UpgradeReq mshr miss latency 147310892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 53833.333333 # average SCUpgradeReq mshr miss latency 147410892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 53833.333333 # average SCUpgradeReq mshr miss latency 147511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81517.659355 # average ReadExReq mshr miss latency 147611103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81517.659355 # average ReadExReq mshr miss latency 147711103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74372.135348 # average ReadCleanReq mshr miss latency 147811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74372.135348 # average ReadCleanReq mshr miss latency 147911103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79230.161201 # average ReadSharedReq mshr miss latency 148011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79230.161201 # average ReadSharedReq mshr miss latency 148111103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 95693.484177 # average InvalidateReq mshr miss latency 148211103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 95693.484177 # average InvalidateReq mshr miss latency 148311103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 78905.748468 # average overall mshr miss latency 148411103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 78281.196189 # average overall mshr miss latency 148511103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74372.135348 # average overall mshr miss latency 148611103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80962.409815 # average overall mshr miss latency 148711103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 80588.161322 # average overall mshr miss latency 148811103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 78905.748468 # average overall mshr miss latency 148911103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 78281.196189 # average overall mshr miss latency 149011103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74372.135348 # average overall mshr miss latency 149111103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80962.409815 # average overall mshr miss latency 149211103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 80588.161322 # average overall mshr miss latency 149310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62372.599202 # average ReadReq mshr uncacheable latency 149411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160511.085718 # average ReadReq mshr uncacheable latency 149511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 122504.664739 # average ReadReq mshr uncacheable latency 149611103Snilay@cs.wisc.edusystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157735.424146 # average WriteReq mshr uncacheable latency 149711103Snilay@cs.wisc.edusystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157735.424146 # average WriteReq mshr uncacheable latency 149810892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62372.599202 # average overall mshr uncacheable latency 149911103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159123.028415 # average overall mshr uncacheable latency 150011103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 135892.671102 # average overall mshr uncacheable latency 150110585Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 150211103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::ReadReq 2244083 # Transaction distribution 150311103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::ReadResp 28317103 # Transaction distribution 150411103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::WriteReq 33703 # Transaction distribution 150511103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::WriteResp 33703 # Transaction distribution 150611103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::Writeback 12480720 # Transaction distribution 150711103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::CleanEvict 20347986 # Transaction distribution 150811103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::UpgradeReq 60667 # Transaction distribution 150910892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution 151011103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::UpgradeResp 60674 # Transaction distribution 151111103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::ReadExReq 3036433 # Transaction distribution 151211103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::ReadExResp 3036433 # Transaction distribution 151311103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::ReadCleanReq 16757275 # Transaction distribution 151411103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::ReadSharedReq 9323830 # Transaction distribution 151511103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::InvalidateReq 1369962 # Transaction distribution 151611103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::InvalidateResp 1263298 # Transaction distribution 151711103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50310988 # Packet count per connected master and slave (bytes) 151811103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41099763 # Packet count per connected master and slave (bytes) 151911103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 807461 # Packet count per connected master and slave (bytes) 152011103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3043712 # Packet count per connected master and slave (bytes) 152111103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_count::total 95261924 # Packet count per connected master and slave (bytes) 152211103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1072793136 # Cumulative packet size per connected master and slave (bytes) 152311103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1449869810 # Cumulative packet size per connected master and slave (bytes) 152411103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2707560 # Cumulative packet size per connected master and slave (bytes) 152511103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10589056 # Cumulative packet size per connected master and slave (bytes) 152611103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_size::total 2535959562 # Cumulative packet size per connected master and slave (bytes) 152711103Snilay@cs.wisc.edusystem.cpu.toL2Bus.snoops 3104722 # Total snoops (count) 152811103Snilay@cs.wisc.edusystem.cpu.toL2Bus.snoop_fanout::samples 65657900 # Request fanout histogram 152911103Snilay@cs.wisc.edusystem.cpu.toL2Bus.snoop_fanout::mean 1.072586 # Request fanout histogram 153011103Snilay@cs.wisc.edusystem.cpu.toL2Bus.snoop_fanout::stdev 0.259455 # Request fanout histogram 153110585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 153210585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 153311103Snilay@cs.wisc.edusystem.cpu.toL2Bus.snoop_fanout::1 60892075 92.74% 92.74% # Request fanout histogram 153411103Snilay@cs.wisc.edusystem.cpu.toL2Bus.snoop_fanout::2 4765825 7.26% 100.00% # Request fanout histogram 153510585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 153610827Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 153710827Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 153811103Snilay@cs.wisc.edusystem.cpu.toL2Bus.snoop_fanout::total 65657900 # Request fanout histogram 153911103Snilay@cs.wisc.edusystem.cpu.toL2Bus.reqLayer0.occupancy 41856500497 # Layer occupancy (ticks) 154010585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 154111103Snilay@cs.wisc.edusystem.cpu.toL2Bus.snoopLayer0.occupancy 1150500 # Layer occupancy (ticks) 154210585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 154311103Snilay@cs.wisc.edusystem.cpu.toL2Bus.respLayer0.occupancy 25164199957 # Layer occupancy (ticks) 154410585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 154511103Snilay@cs.wisc.edusystem.cpu.toL2Bus.respLayer1.occupancy 19241199390 # Layer occupancy (ticks) 154610585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 154711103Snilay@cs.wisc.edusystem.cpu.toL2Bus.respLayer2.occupancy 469526277 # Layer occupancy (ticks) 154810585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 154911103Snilay@cs.wisc.edusystem.cpu.toL2Bus.respLayer3.occupancy 1720822991 # Layer occupancy (ticks) 155010585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 155111103Snilay@cs.wisc.edusystem.iobus.trans_dist::ReadReq 40298 # Transaction distribution 155211103Snilay@cs.wisc.edusystem.iobus.trans_dist::ReadResp 40298 # Transaction distribution 155310892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 136571 # Transaction distribution 155410892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 136571 # Transaction distribution 155510726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) 155610585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 155710585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 155810585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 155910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 156010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 156110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 156210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 156310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 156410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 156510892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 156610585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 156710585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 156810585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 156910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 157010892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) 157111103Snilay@cs.wisc.edusystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes) 157211103Snilay@cs.wisc.edusystem.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes) 157310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 157410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 157511103Snilay@cs.wisc.edusystem.iobus.pkt_count::total 353738 # Packet count per connected master and slave (bytes) 157610726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) 157710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 157810585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 157910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 158010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 158110585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 158210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 158310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 158410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 158510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 158610892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 158710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 158810585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 158910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 159010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 159110892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) 159211103Snilay@cs.wisc.edusystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) 159311103Snilay@cs.wisc.edusystem.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes) 159410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 159510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 159611103Snilay@cs.wisc.edusystem.iobus.pkt_size::total 7492168 # Cumulative packet size per connected master and slave (bytes) 159710726Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) 159810585Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 159910585Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 160010585Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 160110585Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 160210585Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 160310585Sandreas.hansson@arm.comsystem.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 160410585Sandreas.hansson@arm.comsystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 160510585Sandreas.hansson@arm.comsystem.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 160610585Sandreas.hansson@arm.comsystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 160710585Sandreas.hansson@arm.comsystem.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 160810585Sandreas.hansson@arm.comsystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 160910585Sandreas.hansson@arm.comsystem.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 161010585Sandreas.hansson@arm.comsystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 161110585Sandreas.hansson@arm.comsystem.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 161210585Sandreas.hansson@arm.comsystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 161310585Sandreas.hansson@arm.comsystem.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 161410585Sandreas.hansson@arm.comsystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 161510585Sandreas.hansson@arm.comsystem.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 161610585Sandreas.hansson@arm.comsystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 161710892Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) 161810585Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 161910585Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 162010585Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 162110585Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 162210585Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 162310585Sandreas.hansson@arm.comsystem.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 162410585Sandreas.hansson@arm.comsystem.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 162511103Snilay@cs.wisc.edusystem.iobus.reqLayer27.occupancy 568892559 # Layer occupancy (ticks) 162610585Sandreas.hansson@arm.comsystem.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 162710585Sandreas.hansson@arm.comsystem.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 162810585Sandreas.hansson@arm.comsystem.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 162910892Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) 163010585Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 163111103Snilay@cs.wisc.edusystem.iobus.respLayer3.occupancy 147714000 # Layer occupancy (ticks) 163210585Sandreas.hansson@arm.comsystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 163310892Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 163410585Sandreas.hansson@arm.comsystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 163511103Snilay@cs.wisc.edusystem.iocache.tags.replacements 115458 # number of replacements 163611103Snilay@cs.wisc.edusystem.iocache.tags.tagsinuse 10.449705 # Cycle average of tags in use 163710585Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 163811103Snilay@cs.wisc.edusystem.iocache.tags.sampled_refs 115474 # Sample count of references to valid blocks. 163910585Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 164011103Snilay@cs.wisc.edusystem.iocache.tags.warmup_cycle 13095311633000 # Cycle when the warmup percentage was hit. 164111103Snilay@cs.wisc.edusystem.iocache.tags.occ_blocks::realview.ethernet 3.528028 # Average occupied blocks per requestor 164211103Snilay@cs.wisc.edusystem.iocache.tags.occ_blocks::realview.ide 6.921676 # Average occupied blocks per requestor 164311103Snilay@cs.wisc.edusystem.iocache.tags.occ_percent::realview.ethernet 0.220502 # Average percentage of cache occupancy 164411103Snilay@cs.wisc.edusystem.iocache.tags.occ_percent::realview.ide 0.432605 # Average percentage of cache occupancy 164511103Snilay@cs.wisc.edusystem.iocache.tags.occ_percent::total 0.653107 # Average percentage of cache occupancy 164610585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 164710585Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 164810585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 164911103Snilay@cs.wisc.edusystem.iocache.tags.tag_accesses 1039650 # Number of tag accesses 165011103Snilay@cs.wisc.edusystem.iocache.tags.data_accesses 1039650 # Number of data accesses 165110585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 165211103Snilay@cs.wisc.edusystem.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses 165311103Snilay@cs.wisc.edusystem.iocache.ReadReq_misses::total 8850 # number of ReadReq misses 165410585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 165510585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 165610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 165710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 165810585Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 165911103Snilay@cs.wisc.edusystem.iocache.demand_misses::realview.ide 8813 # number of demand (read+write) misses 166011103Snilay@cs.wisc.edusystem.iocache.demand_misses::total 8853 # number of demand (read+write) misses 166110585Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 166211103Snilay@cs.wisc.edusystem.iocache.overall_misses::realview.ide 8813 # number of overall misses 166311103Snilay@cs.wisc.edusystem.iocache.overall_misses::total 8853 # number of overall misses 166410892Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles 166511103Snilay@cs.wisc.edusystem.iocache.ReadReq_miss_latency::realview.ide 1615020135 # number of ReadReq miss cycles 166611103Snilay@cs.wisc.edusystem.iocache.ReadReq_miss_latency::total 1620089135 # number of ReadReq miss cycles 166710892Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 166810892Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles 166911103Snilay@cs.wisc.edusystem.iocache.WriteLineReq_miss_latency::realview.ide 12610143424 # number of WriteLineReq miss cycles 167011103Snilay@cs.wisc.edusystem.iocache.WriteLineReq_miss_latency::total 12610143424 # number of WriteLineReq miss cycles 167110892Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ethernet 5420000 # number of demand (read+write) miss cycles 167211103Snilay@cs.wisc.edusystem.iocache.demand_miss_latency::realview.ide 1615020135 # number of demand (read+write) miss cycles 167311103Snilay@cs.wisc.edusystem.iocache.demand_miss_latency::total 1620440135 # number of demand (read+write) miss cycles 167410892Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ethernet 5420000 # number of overall miss cycles 167511103Snilay@cs.wisc.edusystem.iocache.overall_miss_latency::realview.ide 1615020135 # number of overall miss cycles 167611103Snilay@cs.wisc.edusystem.iocache.overall_miss_latency::total 1620440135 # number of overall miss cycles 167710585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 167811103Snilay@cs.wisc.edusystem.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) 167911103Snilay@cs.wisc.edusystem.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) 168010585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 168110585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 168210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 168310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 168410585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 168511103Snilay@cs.wisc.edusystem.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses 168611103Snilay@cs.wisc.edusystem.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses 168710585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 168811103Snilay@cs.wisc.edusystem.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses 168911103Snilay@cs.wisc.edusystem.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses 169010585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 169110585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 169210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 169310585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 169410585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 169510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 169610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 169710585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 169810585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 169910585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 170010585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 170110585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 170210585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 170310892Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency 170411103Snilay@cs.wisc.edusystem.iocache.ReadReq_avg_miss_latency::realview.ide 183254.298763 # average ReadReq miss latency 170511103Snilay@cs.wisc.edusystem.iocache.ReadReq_avg_miss_latency::total 183060.919209 # average ReadReq miss latency 170610892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 170710892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency 170811103Snilay@cs.wisc.edusystem.iocache.WriteLineReq_avg_miss_latency::realview.ide 118223.050176 # average WriteLineReq miss latency 170911103Snilay@cs.wisc.edusystem.iocache.WriteLineReq_avg_miss_latency::total 118223.050176 # average WriteLineReq miss latency 171010892Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 135500 # average overall miss latency 171111103Snilay@cs.wisc.edusystem.iocache.demand_avg_miss_latency::realview.ide 183254.298763 # average overall miss latency 171211103Snilay@cs.wisc.edusystem.iocache.demand_avg_miss_latency::total 183038.533266 # average overall miss latency 171310892Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 135500 # average overall miss latency 171411103Snilay@cs.wisc.edusystem.iocache.overall_avg_miss_latency::realview.ide 183254.298763 # average overall miss latency 171511103Snilay@cs.wisc.edusystem.iocache.overall_avg_miss_latency::total 183038.533266 # average overall miss latency 171611103Snilay@cs.wisc.edusystem.iocache.blocked_cycles::no_mshrs 31319 # number of cycles access was blocked 171710585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 171811103Snilay@cs.wisc.edusystem.iocache.blocked::no_mshrs 3376 # number of cycles access was blocked 171910585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 172011103Snilay@cs.wisc.edusystem.iocache.avg_blocked_cycles::no_mshrs 9.276955 # average number of cycles each access was blocked 172110585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 172210585Sandreas.hansson@arm.comsystem.iocache.fast_writes 0 # number of fast writes performed 172310585Sandreas.hansson@arm.comsystem.iocache.cache_copies 0 # number of cache copies performed 172410726Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 106630 # number of writebacks 172510726Sandreas.hansson@arm.comsystem.iocache.writebacks::total 106630 # number of writebacks 172610585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 172711103Snilay@cs.wisc.edusystem.iocache.ReadReq_mshr_misses::realview.ide 8813 # number of ReadReq MSHR misses 172811103Snilay@cs.wisc.edusystem.iocache.ReadReq_mshr_misses::total 8850 # number of ReadReq MSHR misses 172910585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 173010585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 173110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 173210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 173310585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 173411103Snilay@cs.wisc.edusystem.iocache.demand_mshr_misses::realview.ide 8813 # number of demand (read+write) MSHR misses 173511103Snilay@cs.wisc.edusystem.iocache.demand_mshr_misses::total 8853 # number of demand (read+write) MSHR misses 173610585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 173711103Snilay@cs.wisc.edusystem.iocache.overall_mshr_misses::realview.ide 8813 # number of overall MSHR misses 173811103Snilay@cs.wisc.edusystem.iocache.overall_mshr_misses::total 8853 # number of overall MSHR misses 173910892Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219000 # number of ReadReq MSHR miss cycles 174011103Snilay@cs.wisc.edusystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1174370135 # number of ReadReq MSHR miss cycles 174111103Snilay@cs.wisc.edusystem.iocache.ReadReq_mshr_miss_latency::total 1177589135 # number of ReadReq MSHR miss cycles 174210892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 174310892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 174411103Snilay@cs.wisc.edusystem.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7276943424 # number of WriteLineReq MSHR miss cycles 174511103Snilay@cs.wisc.edusystem.iocache.WriteLineReq_mshr_miss_latency::total 7276943424 # number of WriteLineReq MSHR miss cycles 174610892Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3420000 # number of demand (read+write) MSHR miss cycles 174711103Snilay@cs.wisc.edusystem.iocache.demand_mshr_miss_latency::realview.ide 1174370135 # number of demand (read+write) MSHR miss cycles 174811103Snilay@cs.wisc.edusystem.iocache.demand_mshr_miss_latency::total 1177790135 # number of demand (read+write) MSHR miss cycles 174910892Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3420000 # number of overall MSHR miss cycles 175011103Snilay@cs.wisc.edusystem.iocache.overall_mshr_miss_latency::realview.ide 1174370135 # number of overall MSHR miss cycles 175111103Snilay@cs.wisc.edusystem.iocache.overall_mshr_miss_latency::total 1177790135 # number of overall MSHR miss cycles 175210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 175310585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 175410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 175510585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 175610585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 175710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 175810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 175910585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 176010585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 176110585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 176210585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 176310585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 176410585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 176510892Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87000 # average ReadReq mshr miss latency 176611103Snilay@cs.wisc.edusystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133254.298763 # average ReadReq mshr miss latency 176711103Snilay@cs.wisc.edusystem.iocache.ReadReq_avg_mshr_miss_latency::total 133060.919209 # average ReadReq mshr miss latency 176810892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 176910892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 177011103Snilay@cs.wisc.edusystem.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68223.050176 # average WriteLineReq mshr miss latency 177111103Snilay@cs.wisc.edusystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 68223.050176 # average WriteLineReq mshr miss latency 177210892Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency 177311103Snilay@cs.wisc.edusystem.iocache.demand_avg_mshr_miss_latency::realview.ide 133254.298763 # average overall mshr miss latency 177411103Snilay@cs.wisc.edusystem.iocache.demand_avg_mshr_miss_latency::total 133038.533266 # average overall mshr miss latency 177510892Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency 177611103Snilay@cs.wisc.edusystem.iocache.overall_avg_mshr_miss_latency::realview.ide 133254.298763 # average overall mshr miss latency 177711103Snilay@cs.wisc.edusystem.iocache.overall_avg_mshr_miss_latency::total 133038.533266 # average overall mshr miss latency 177810585Sandreas.hansson@arm.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 177911103Snilay@cs.wisc.edusystem.membus.trans_dist::ReadReq 54987 # Transaction distribution 178011103Snilay@cs.wisc.edusystem.membus.trans_dist::ReadResp 601962 # Transaction distribution 178111103Snilay@cs.wisc.edusystem.membus.trans_dist::WriteReq 33703 # Transaction distribution 178211103Snilay@cs.wisc.edusystem.membus.trans_dist::WriteResp 33703 # Transaction distribution 178311103Snilay@cs.wisc.edusystem.membus.trans_dist::Writeback 2181638 # Transaction distribution 178411103Snilay@cs.wisc.edusystem.membus.trans_dist::CleanEvict 277040 # Transaction distribution 178511103Snilay@cs.wisc.edusystem.membus.trans_dist::UpgradeReq 48552 # Transaction distribution 178610726Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution 178711103Snilay@cs.wisc.edusystem.membus.trans_dist::UpgradeResp 48555 # Transaction distribution 178811103Snilay@cs.wisc.edusystem.membus.trans_dist::ReadExReq 1902507 # Transaction distribution 178911103Snilay@cs.wisc.edusystem.membus.trans_dist::ReadExResp 1902507 # Transaction distribution 179011103Snilay@cs.wisc.edusystem.membus.trans_dist::ReadSharedReq 546975 # Transaction distribution 179110892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 106664 # Transaction distribution 179210892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 106664 # Transaction distribution 179310892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) 179410515SAli.Saidi@ARM.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes) 179511103Snilay@cs.wisc.edusystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6900 # Packet count per connected master and slave (bytes) 179611103Snilay@cs.wisc.edusystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7371150 # Packet count per connected master and slave (bytes) 179711103Snilay@cs.wisc.edusystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 7500814 # Packet count per connected master and slave (bytes) 179811103Snilay@cs.wisc.edusystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341657 # Packet count per connected master and slave (bytes) 179911103Snilay@cs.wisc.edusystem.membus.pkt_count_system.iocache.mem_side::total 341657 # Packet count per connected master and slave (bytes) 180011103Snilay@cs.wisc.edusystem.membus.pkt_count::total 7842471 # Packet count per connected master and slave (bytes) 180110892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) 180210515SAli.Saidi@ARM.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes) 180311103Snilay@cs.wisc.edusystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13800 # Cumulative packet size per connected master and slave (bytes) 180411103Snilay@cs.wisc.edusystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 289319820 # Cumulative packet size per connected master and slave (bytes) 180511103Snilay@cs.wisc.edusystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 289489890 # Cumulative packet size per connected master and slave (bytes) 180611103Snilay@cs.wisc.edusystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7242112 # Cumulative packet size per connected master and slave (bytes) 180711103Snilay@cs.wisc.edusystem.membus.pkt_size_system.iocache.mem_side::total 7242112 # Cumulative packet size per connected master and slave (bytes) 180811103Snilay@cs.wisc.edusystem.membus.pkt_size::total 296732002 # Cumulative packet size per connected master and slave (bytes) 180911103Snilay@cs.wisc.edusystem.membus.snoops 2989 # Total snoops (count) 181011103Snilay@cs.wisc.edusystem.membus.snoop_fanout::samples 5154600 # Request fanout histogram 181110515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 181210515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 181310515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 181410515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 181511103Snilay@cs.wisc.edusystem.membus.snoop_fanout::1 5154600 100.00% 100.00% # Request fanout histogram 181610515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 181710515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 181810515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 181910515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 182011103Snilay@cs.wisc.edusystem.membus.snoop_fanout::total 5154600 # Request fanout histogram 182111103Snilay@cs.wisc.edusystem.membus.reqLayer0.occupancy 104456000 # Layer occupancy (ticks) 182210515SAli.Saidi@ARM.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 182310726Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 33000 # Layer occupancy (ticks) 182410515SAli.Saidi@ARM.comsystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 182511103Snilay@cs.wisc.edusystem.membus.reqLayer2.occupancy 5495500 # Layer occupancy (ticks) 182610515SAli.Saidi@ARM.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 182711103Snilay@cs.wisc.edusystem.membus.reqLayer5.occupancy 14230820482 # Layer occupancy (ticks) 182810585Sandreas.hansson@arm.comsystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 182911103Snilay@cs.wisc.edusystem.membus.respLayer2.occupancy 13100845399 # Layer occupancy (ticks) 183010515SAli.Saidi@ARM.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 183111103Snilay@cs.wisc.edusystem.membus.respLayer3.occupancy 228852771 # Layer occupancy (ticks) 183210515SAli.Saidi@ARM.comsystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 183310515SAli.Saidi@ARM.comsystem.realview.ethernet.txBytes 966 # Bytes Transmitted 183410515SAli.Saidi@ARM.comsystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 183510515SAli.Saidi@ARM.comsystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 183610515SAli.Saidi@ARM.comsystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 183710515SAli.Saidi@ARM.comsystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 183810515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 183910515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 184010515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 184110515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 184211103Snilay@cs.wisc.edusystem.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) 184310515SAli.Saidi@ARM.comsystem.realview.ethernet.totPackets 3 # Total Packets 184410515SAli.Saidi@ARM.comsystem.realview.ethernet.totBytes 966 # Total Bytes 184510515SAli.Saidi@ARM.comsystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 184611103Snilay@cs.wisc.edusystem.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) 184710515SAli.Saidi@ARM.comsystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 184810515SAli.Saidi@ARM.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 184910515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 185010515SAli.Saidi@ARM.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 185110515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 185210515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 185310515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 185410515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 185510515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 185610515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 185710515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 185810515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 185910515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 186010515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 186110515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 186210515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 186310515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 186410515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 186510515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 186610515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 186710515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 186810515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 186910515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 187010515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 187110515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 187210515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 187310515SAli.Saidi@ARM.comsystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 187410515SAli.Saidi@ARM.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 187511103Snilay@cs.wisc.edusystem.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks 187611014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks 187711014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks 187811014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks 187911014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks 188011014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks 188111014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks 188211014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks 188311014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks 188411014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks 188510515SAli.Saidi@ARM.comsystem.cpu.kern.inst.arm 0 # number of arm instructions executed 188611103Snilay@cs.wisc.edusystem.cpu.kern.inst.quiesce 20008 # number of quiesce instructions executed 188710515SAli.Saidi@ARM.com 188810515SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 1889