110515SAli.Saidi@ARM.com 210515SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 311860Sandreas.hansson@arm.comsim_seconds 51.277959 # Number of seconds simulated 411860Sandreas.hansson@arm.comsim_ticks 51277959410000 # Number of ticks simulated 511860Sandreas.hansson@arm.comfinal_tick 51277959410000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 711860Sandreas.hansson@arm.comhost_inst_rate 210382 # Simulator instruction rate (inst/s) 811860Sandreas.hansson@arm.comhost_op_rate 250295 # Simulator op (including micro ops) rate (op/s) 911860Sandreas.hansson@arm.comhost_tick_rate 13357159040 # Simulator tick rate (ticks/s) 1011860Sandreas.hansson@arm.comhost_mem_usage 689664 # Number of bytes of host memory used 1111860Sandreas.hansson@arm.comhost_seconds 3838.99 # Real time elapsed on the host 1211860Sandreas.hansson@arm.comsim_insts 807652759 # Number of instructions simulated 1311860Sandreas.hansson@arm.comsim_ops 960879271 # Number of ops (including micro ops) simulated 1410515SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611860Sandreas.hansson@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 1711860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.dtb.walker 253184 # Number of bytes read from this memory 1811860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.itb.walker 234496 # Number of bytes read from this memory 1911860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 5589856 # Number of bytes read from this memory 2011860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 47714440 # Number of bytes read from this memory 2111860Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 412800 # Number of bytes read from this memory 2211860Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 54204776 # Number of bytes read from this memory 2311860Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 5589856 # Number of instructions bytes read from this memory 2411860Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 5589856 # Number of instructions bytes read from this memory 2511860Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 74605824 # Number of bytes written to this memory 2610585Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory 2711860Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 74626404 # Number of bytes written to this memory 2811860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.dtb.walker 3956 # Number of read requests responded to by this memory 2911860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.itb.walker 3664 # Number of read requests responded to by this memory 3011860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 88894 # Number of read requests responded to by this memory 3111860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 745551 # Number of read requests responded to by this memory 3211860Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 6450 # Number of read requests responded to by this memory 3311860Sandreas.hansson@arm.comsystem.physmem.num_reads::total 848515 # Number of read requests responded to by this memory 3411860Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 1165716 # Number of write requests responded to by this memory 3510585Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory 3611860Sandreas.hansson@arm.comsystem.physmem.num_writes::total 1168289 # Number of write requests responded to by this memory 3711860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.dtb.walker 4937 # Total read bandwidth from this memory (bytes/s) 3811860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.itb.walker 4573 # Total read bandwidth from this memory (bytes/s) 3911860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 109011 # Total read bandwidth from this memory (bytes/s) 4011860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 930506 # Total read bandwidth from this memory (bytes/s) 4111860Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 8050 # Total read bandwidth from this memory (bytes/s) 4211860Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1057077 # Total read bandwidth from this memory (bytes/s) 4311860Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 109011 # Instruction read bandwidth from this memory (bytes/s) 4411860Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 109011 # Instruction read bandwidth from this memory (bytes/s) 4511860Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 1454930 # Write bandwidth from this memory (bytes/s) 4611860Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) 4711860Sandreas.hansson@arm.comsystem.physmem.bw_write::total 1455331 # Write bandwidth from this memory (bytes/s) 4811860Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 1454930 # Total bandwidth to/from this memory (bytes/s) 4911860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.dtb.walker 4937 # Total bandwidth to/from this memory (bytes/s) 5011860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.itb.walker 4573 # Total bandwidth to/from this memory (bytes/s) 5111860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 109011 # Total bandwidth to/from this memory (bytes/s) 5211860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 930907 # Total bandwidth to/from this memory (bytes/s) 5311860Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 8050 # Total bandwidth to/from this memory (bytes/s) 5411860Sandreas.hansson@arm.comsystem.physmem.bw_total::total 2512408 # Total bandwidth to/from this memory (bytes/s) 5511860Sandreas.hansson@arm.comsystem.physmem.readReqs 848516 # Number of read requests accepted 5611860Sandreas.hansson@arm.comsystem.physmem.writeReqs 1168289 # Number of write requests accepted 5711860Sandreas.hansson@arm.comsystem.physmem.readBursts 848516 # Number of DRAM read bursts, including those serviced by the write queue 5811860Sandreas.hansson@arm.comsystem.physmem.writeBursts 1168289 # Number of DRAM write bursts, including those merged in the write queue 5911860Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 54258624 # Total number of bytes read from DRAM 6011860Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 46336 # Total number of bytes read from write queue 6111860Sandreas.hansson@arm.comsystem.physmem.bytesWritten 74623296 # Total number of bytes written to DRAM 6211860Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 54204840 # Total read bytes from the system interface side 6311860Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 74626404 # Total written bytes from the system interface side 6411860Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 724 # Number of DRAM read bursts serviced by the write queue 6511860Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 2278 # Number of DRAM write bursts merged with an existing one 6611336Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 6711860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 50870 # Per bank write bursts 6811860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 59107 # Per bank write bursts 6911860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 53673 # Per bank write bursts 7011860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 52283 # Per bank write bursts 7111860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 52009 # Per bank write bursts 7211860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 59846 # Per bank write bursts 7311860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 50421 # Per bank write bursts 7411860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 52784 # Per bank write bursts 7511860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 49319 # Per bank write bursts 7611860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 57871 # Per bank write bursts 7711860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 53663 # Per bank write bursts 7811860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 59850 # Per bank write bursts 7911860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 49313 # Per bank write bursts 8011860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 51526 # Per bank write bursts 8111860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 46865 # Per bank write bursts 8211860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 48391 # Per bank write bursts 8311860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 70028 # Per bank write bursts 8411860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 76221 # Per bank write bursts 8511860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 72051 # Per bank write bursts 8611860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 73117 # Per bank write bursts 8711860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 72572 # Per bank write bursts 8811860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 78772 # Per bank write bursts 8911860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 71408 # Per bank write bursts 9011860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 73272 # Per bank write bursts 9111860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 71515 # Per bank write bursts 9211860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 77080 # Per bank write bursts 9311860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 72838 # Per bank write bursts 9411860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 77780 # Per bank write bursts 9511860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 69170 # Per bank write bursts 9611860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 71642 # Per bank write bursts 9711860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 68698 # Per bank write bursts 9811860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 69825 # Per bank write bursts 9910515SAli.Saidi@ARM.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 10011860Sandreas.hansson@arm.comsystem.physmem.numWrRetry 522 # Number of times write queue was full causing retry 10111860Sandreas.hansson@arm.comsystem.physmem.totGap 51277958025500 # Total gap between requests 10210515SAli.Saidi@ARM.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 10310515SAli.Saidi@ARM.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 10410515SAli.Saidi@ARM.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 10510515SAli.Saidi@ARM.comsystem.physmem.readPktSize::3 13 # Read request sizes (log2) 10611860Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 2072 # Read request sizes (log2) 10710515SAli.Saidi@ARM.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 10811860Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 846431 # Read request sizes (log2) 10910515SAli.Saidi@ARM.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 11010515SAli.Saidi@ARM.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 11110515SAli.Saidi@ARM.comsystem.physmem.writePktSize::2 1 # Write request sizes (log2) 11210515SAli.Saidi@ARM.comsystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 11310515SAli.Saidi@ARM.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 11410515SAli.Saidi@ARM.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 11511860Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 1165716 # Write request sizes (log2) 11611860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 541295 # What read queue length does an incoming req see 11711860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 247060 # What read queue length does an incoming req see 11811860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 38783 # What read queue length does an incoming req see 11911860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 15383 # What read queue length does an incoming req see 12011860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 573 # What read queue length does an incoming req see 12111860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 464 # What read queue length does an incoming req see 12211860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 597 # What read queue length does an incoming req see 12311860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 524 # What read queue length does an incoming req see 12411860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 939 # What read queue length does an incoming req see 12511860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 638 # What read queue length does an incoming req see 12611860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 319 # What read queue length does an incoming req see 12711860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 277 # What read queue length does an incoming req see 12811860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 193 # What read queue length does an incoming req see 12911860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 154 # What read queue length does an incoming req see 13011860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 122 # What read queue length does an incoming req see 13111860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 112 # What read queue length does an incoming req see 13211860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 103 # What read queue length does an incoming req see 13311860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 95 # What read queue length does an incoming req see 13411860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 81 # What read queue length does an incoming req see 13511860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 69 # What read queue length does an incoming req see 13611860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see 13711860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see 13811353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 13911353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 14010515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 14110515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 14210515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 14310515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 14410515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 14510515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 14610515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 14710515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 14810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 14910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 15010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 15110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 15210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 15310515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 15410515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 15510515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 15610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 15710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 15810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 15910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 16010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 16110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 16210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 16311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 18590 # What write queue length does an incoming req see 16411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 25743 # What write queue length does an incoming req see 16511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 45741 # What write queue length does an incoming req see 16611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 55757 # What write queue length does an incoming req see 16711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 63122 # What write queue length does an incoming req see 16811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 66457 # What write queue length does an incoming req see 16911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 68011 # What write queue length does an incoming req see 17011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 72400 # What write queue length does an incoming req see 17111860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 75195 # What write queue length does an incoming req see 17211860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 71101 # What write queue length does an incoming req see 17311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 74150 # What write queue length does an incoming req see 17411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 75214 # What write queue length does an incoming req see 17511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 67195 # What write queue length does an incoming req see 17611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 65816 # What write queue length does an incoming req see 17711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 65315 # What write queue length does an incoming req see 17811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 67462 # What write queue length does an incoming req see 17911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 61130 # What write queue length does an incoming req see 18011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 60486 # What write queue length does an incoming req see 18111860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 5440 # What write queue length does an incoming req see 18211860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 4298 # What write queue length does an incoming req see 18311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 3581 # What write queue length does an incoming req see 18411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 2994 # What write queue length does an incoming req see 18511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 2748 # What write queue length does an incoming req see 18611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 2603 # What write queue length does an incoming req see 18711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 2553 # What write queue length does an incoming req see 18811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 2355 # What write queue length does an incoming req see 18911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 2335 # What write queue length does an incoming req see 19011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 2239 # What write queue length does an incoming req see 19111860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 2251 # What write queue length does an incoming req see 19211860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 2250 # What write queue length does an incoming req see 19311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 1876 # What write queue length does an incoming req see 19411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 1953 # What write queue length does an incoming req see 19511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 1922 # What write queue length does an incoming req see 19611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 1642 # What write queue length does an incoming req see 19711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 1940 # What write queue length does an incoming req see 19811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 1886 # What write queue length does an incoming req see 19911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 1643 # What write queue length does an incoming req see 20011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 1747 # What write queue length does an incoming req see 20111860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 1870 # What write queue length does an incoming req see 20211860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 1729 # What write queue length does an incoming req see 20311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 1705 # What write queue length does an incoming req see 20411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 1986 # What write queue length does an incoming req see 20511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 1571 # What write queue length does an incoming req see 20611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 1442 # What write queue length does an incoming req see 20711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 1488 # What write queue length does an incoming req see 20811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 1772 # What write queue length does an incoming req see 20911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 1419 # What write queue length does an incoming req see 21011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 718 # What write queue length does an incoming req see 21111860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 1155 # What write queue length does an incoming req see 21211860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 505782 # Bytes accessed per row activation 21311860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 254.816375 # Bytes accessed per row activation 21411860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 152.511846 # Bytes accessed per row activation 21511860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 294.316020 # Bytes accessed per row activation 21611860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 218537 43.21% 43.21% # Bytes accessed per row activation 21711860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 130980 25.90% 69.10% # Bytes accessed per row activation 21811860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 46546 9.20% 78.31% # Bytes accessed per row activation 21911860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 24886 4.92% 83.23% # Bytes accessed per row activation 22011860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 16948 3.35% 86.58% # Bytes accessed per row activation 22111860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 10705 2.12% 88.69% # Bytes accessed per row activation 22211860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 8138 1.61% 90.30% # Bytes accessed per row activation 22311860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 6857 1.36% 91.66% # Bytes accessed per row activation 22411860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 42185 8.34% 100.00% # Bytes accessed per row activation 22511860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 505782 # Bytes accessed per row activation 22611860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 52835 # Reads before turning the bus around for writes 22711860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 16.045538 # Reads before turning the bus around for writes 22811860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 23.735472 # Reads before turning the bus around for writes 22911860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-255 52822 99.98% 99.98% # Reads before turning the bus around for writes 23011860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::256-511 8 0.02% 99.99% # Reads before turning the bus around for writes 23111860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::768-1023 3 0.01% 100.00% # Reads before turning the bus around for writes 23211860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::1024-1279 1 0.00% 100.00% # Reads before turning the bus around for writes 23311860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::4352-4607 1 0.00% 100.00% # Reads before turning the bus around for writes 23411860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 52835 # Reads before turning the bus around for writes 23511860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 52835 # Writes before turning the bus around for reads 23611860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 22.068496 # Writes before turning the bus around for reads 23711860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 18.791739 # Writes before turning the bus around for reads 23811860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 25.919021 # Writes before turning the bus around for reads 23911860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16-31 48708 92.19% 92.19% # Writes before turning the bus around for reads 24011860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32-47 1351 2.56% 94.75% # Writes before turning the bus around for reads 24111860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48-63 388 0.73% 95.48% # Writes before turning the bus around for reads 24211860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::64-79 806 1.53% 97.01% # Writes before turning the bus around for reads 24311860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::80-95 454 0.86% 97.87% # Writes before turning the bus around for reads 24411860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::96-111 263 0.50% 98.36% # Writes before turning the bus around for reads 24511860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::112-127 370 0.70% 99.06% # Writes before turning the bus around for reads 24611860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::128-143 158 0.30% 99.36% # Writes before turning the bus around for reads 24711860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::144-159 43 0.08% 99.44% # Writes before turning the bus around for reads 24811860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::160-175 52 0.10% 99.54% # Writes before turning the bus around for reads 24911860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::176-191 56 0.11% 99.65% # Writes before turning the bus around for reads 25011860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::192-207 28 0.05% 99.70% # Writes before turning the bus around for reads 25111860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::208-223 16 0.03% 99.73% # Writes before turning the bus around for reads 25211860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::224-239 21 0.04% 99.77% # Writes before turning the bus around for reads 25311860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::240-255 12 0.02% 99.79% # Writes before turning the bus around for reads 25411860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::256-271 27 0.05% 99.84% # Writes before turning the bus around for reads 25511860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::272-287 19 0.04% 99.88% # Writes before turning the bus around for reads 25611860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::288-303 15 0.03% 99.91% # Writes before turning the bus around for reads 25711860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::304-319 3 0.01% 99.91% # Writes before turning the bus around for reads 25811860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::320-335 5 0.01% 99.92% # Writes before turning the bus around for reads 25911860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::336-351 1 0.00% 99.93% # Writes before turning the bus around for reads 26011860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::352-367 4 0.01% 99.93% # Writes before turning the bus around for reads 26111860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::368-383 8 0.02% 99.95% # Writes before turning the bus around for reads 26211860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::384-399 3 0.01% 99.95% # Writes before turning the bus around for reads 26311860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::416-431 1 0.00% 99.96% # Writes before turning the bus around for reads 26411860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::448-463 1 0.00% 99.96% # Writes before turning the bus around for reads 26511860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::480-495 2 0.00% 99.96% # Writes before turning the bus around for reads 26611860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::496-511 1 0.00% 99.96% # Writes before turning the bus around for reads 26711860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::512-527 2 0.00% 99.97% # Writes before turning the bus around for reads 26811860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::528-543 2 0.00% 99.97% # Writes before turning the bus around for reads 26911860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::544-559 1 0.00% 99.97% # Writes before turning the bus around for reads 27011860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::592-607 1 0.00% 99.98% # Writes before turning the bus around for reads 27111860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::608-623 2 0.00% 99.98% # Writes before turning the bus around for reads 27211860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::624-639 1 0.00% 99.98% # Writes before turning the bus around for reads 27311860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::640-655 4 0.01% 99.99% # Writes before turning the bus around for reads 27411754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::656-671 1 0.00% 99.99% # Writes before turning the bus around for reads 27511860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::704-719 1 0.00% 99.99% # Writes before turning the bus around for reads 27611754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::736-751 1 0.00% 99.99% # Writes before turning the bus around for reads 27711860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::880-895 1 0.00% 100.00% # Writes before turning the bus around for reads 27811860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::912-927 1 0.00% 100.00% # Writes before turning the bus around for reads 27911860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::992-1007 1 0.00% 100.00% # Writes before turning the bus around for reads 28011860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 52835 # Writes before turning the bus around for reads 28111860Sandreas.hansson@arm.comsystem.physmem.totQLat 32888008041 # Total ticks spent queuing 28211860Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 48784089291 # Total ticks spent from burst creation until serviced by the DRAM 28311860Sandreas.hansson@arm.comsystem.physmem.totBusLat 4238955000 # Total ticks spent in databus transfers 28411860Sandreas.hansson@arm.comsystem.physmem.avgQLat 38792.54 # Average queueing delay per DRAM burst 28511860Sandreas.hansson@arm.comsystem.physmem.avgBusLat 4999.99 # Average bus latency per DRAM burst 28611860Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 57542.52 # Average memory access latency per DRAM burst 28711860Sandreas.hansson@arm.comsystem.physmem.avgRdBW 1.06 # Average DRAM read bandwidth in MiByte/s 28811860Sandreas.hansson@arm.comsystem.physmem.avgWrBW 1.46 # Average achieved write bandwidth in MiByte/s 28911860Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 1.06 # Average system read bandwidth in MiByte/s 29011860Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 1.46 # Average system write bandwidth in MiByte/s 29110515SAli.Saidi@ARM.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 29211860Sandreas.hansson@arm.comsystem.physmem.busUtil 0.02 # Data bus utilization in percentage 29311860Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 29411860Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 29511754Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing 29611860Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 26.62 # Average write queue length when enqueuing 29711860Sandreas.hansson@arm.comsystem.physmem.readRowHits 648292 # Number of row buffer hits during reads 29811860Sandreas.hansson@arm.comsystem.physmem.writeRowHits 859704 # Number of row buffer hits during writes 29911860Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 76.47 # Row buffer hit rate for reads 30011860Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 73.73 # Row buffer hit rate for writes 30111860Sandreas.hansson@arm.comsystem.physmem.avgGap 25425342.57 # Average gap between requests 30211860Sandreas.hansson@arm.comsystem.physmem.pageHitRate 74.88 # Row buffer hit rate, read and write combined 30311860Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 1849802640 # Energy for activate commands per rank (pJ) 30411860Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 983185830 # Energy for precharge commands per rank (pJ) 30511860Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 3077290020 # Energy for read commands per rank (pJ) 30611860Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 3066442020 # Energy for write commands per rank (pJ) 30711860Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 32858039760.000008 # Energy for refresh commands per rank (pJ) 30811860Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 30159163980 # Energy for active background per rank (pJ) 30911860Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 1958344800 # Energy for precharge background per rank (pJ) 31011860Sandreas.hansson@arm.comsystem.physmem_0.actPowerDownEnergy 66073114650 # Energy for active power-down per rank (pJ) 31111860Sandreas.hansson@arm.comsystem.physmem_0.prePowerDownEnergy 46519620000 # Energy for precharge power-down per rank (pJ) 31211860Sandreas.hansson@arm.comsystem.physmem_0.selfRefreshEnergy 12231781860420 # Energy for self refresh per rank (pJ) 31311860Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 12418342348350 # Total energy per rank (pJ) 31411860Sandreas.hansson@arm.comsystem.physmem_0.averagePower 242.176999 # Core power per rank (mW) 31511860Sandreas.hansson@arm.comsystem.physmem_0.totalIdleTime 51206686329778 # Total Idle time Per DRAM Rank 31611860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 3544531992 # Time in different power states 31711860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 13966174000 # Time in different power states 31811860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::SREF 50940644588000 # Time in different power states 31911860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 121144747142 # Time in different power states 32011860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 53762327980 # Time in different power states 32111860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 144897040886 # Time in different power states 32211860Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 1761495120 # Energy for activate commands per rank (pJ) 32311860Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 936256860 # Energy for precharge commands per rank (pJ) 32411860Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 2975937720 # Energy for read commands per rank (pJ) 32511860Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 3020020560 # Energy for write commands per rank (pJ) 32611860Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 32012909760.000008 # Energy for refresh commands per rank (pJ) 32711860Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 29684228010 # Energy for active background per rank (pJ) 32811860Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 1902447840 # Energy for precharge background per rank (pJ) 32911860Sandreas.hansson@arm.comsystem.physmem_1.actPowerDownEnergy 63461801580 # Energy for active power-down per rank (pJ) 33011860Sandreas.hansson@arm.comsystem.physmem_1.prePowerDownEnergy 45299969760 # Energy for precharge power-down per rank (pJ) 33111860Sandreas.hansson@arm.comsystem.physmem_1.selfRefreshEnergy 12234156504570 # Energy for self refresh per rank (pJ) 33211860Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 12415225828860 # Total energy per rank (pJ) 33311860Sandreas.hansson@arm.comsystem.physmem_1.averagePower 242.116222 # Core power per rank (mW) 33411860Sandreas.hansson@arm.comsystem.physmem_1.totalIdleTime 51207876412176 # Total Idle time Per DRAM Rank 33511860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 3424177242 # Time in different power states 33611860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 13608086000 # Time in different power states 33711860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::SREF 50950737151500 # Time in different power states 33811860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 117968786503 # Time in different power states 33911860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 53050734582 # Time in different power states 34011860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 139170474173 # Time in different power states 34111860Sandreas.hansson@arm.comsystem.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 34211201Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory 34310585Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 34411201Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory 34511201Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_inst_read::cpu.inst 384 # Number of instructions bytes read from this memory 34611201Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_inst_read::total 384 # Number of instructions bytes read from this memory 34711201Sandreas.hansson@arm.comsystem.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory 34810585Sandreas.hansson@arm.comsystem.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 34911201Sandreas.hansson@arm.comsystem.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory 35011201Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) 35110585Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 35211167Sjthestness@gmail.comsystem.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) 35311201Sandreas.hansson@arm.comsystem.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) 35411201Sandreas.hansson@arm.comsystem.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) 35511201Sandreas.hansson@arm.comsystem.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) 35610585Sandreas.hansson@arm.comsystem.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 35711167Sjthestness@gmail.comsystem.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) 35811860Sandreas.hansson@arm.comsystem.realview.vram.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 35911860Sandreas.hansson@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 36011860Sandreas.hansson@arm.comsystem.bridge.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 36110585Sandreas.hansson@arm.comsystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 36210585Sandreas.hansson@arm.comsystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 36310585Sandreas.hansson@arm.comsystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 36410585Sandreas.hansson@arm.comsystem.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 36510585Sandreas.hansson@arm.comsystem.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 36610585Sandreas.hansson@arm.comsystem.cf0.dma_write_txs 1669 # Number of DMA write transactions. 36711860Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 214792288 # Number of BP lookups 36811860Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 137846282 # Number of conditional branches predicted 36911860Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 12464803 # Number of conditional branches incorrect 37011860Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 146135265 # Number of BTB lookups 37111860Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 84448125 # Number of BTB hits 37210585Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 37311860Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 57.787643 # BTB Hit Percentage 37411860Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 31594768 # Number of times the RAS was used to get a target. 37511860Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 349324 # Number of incorrect RAS predictions. 37611860Sandreas.hansson@arm.comsystem.cpu.branchPred.indirectLookups 6874034 # Number of indirect predictor lookups. 37711860Sandreas.hansson@arm.comsystem.cpu.branchPred.indirectHits 4883721 # Number of indirect target hits. 37811860Sandreas.hansson@arm.comsystem.cpu.branchPred.indirectMisses 1990313 # Number of indirect misses. 37911860Sandreas.hansson@arm.comsystem.cpu.branchPredindirectMispredicted 771971 # Number of mispredicted indirect branches. 38010585Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 38111860Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 38210628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 38310628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 38410628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 38510628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 38610628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 38710628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 38810628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 38910628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 39010585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 39110585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 39210585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 39310585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 39410585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 39510585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 39610585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 39710585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 39810585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 39910585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 40010585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 40110585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 40210585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 40310585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 40410585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 40510585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 40610585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 40710585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 40810585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 40910585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 41010585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 41111860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 41211860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walks 970467 # Table walker walks requested 41311860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksLong 970467 # Table walker walks initiated with long descriptors 41411860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksLongTerminationLevel::Level2 18061 # Level at which table walker walks with long descriptors terminate 41511860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksLongTerminationLevel::Level3 162102 # Level at which table walker walks with long descriptors terminate 41611860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksSquashedBefore 433748 # Table walks squashed before starting 41711860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::samples 536719 # Table walker wait (enqueue to first request) latency 41811860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::mean 2148.778970 # Table walker wait (enqueue to first request) latency 41911860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::stdev 14488.438649 # Table walker wait (enqueue to first request) latency 42011860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::0-65535 533045 99.32% 99.32% # Table walker wait (enqueue to first request) latency 42111860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::65536-131071 2702 0.50% 99.82% # Table walker wait (enqueue to first request) latency 42211860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::131072-196607 468 0.09% 99.91% # Table walker wait (enqueue to first request) latency 42311860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::196608-262143 229 0.04% 99.95% # Table walker wait (enqueue to first request) latency 42411860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::262144-327679 124 0.02% 99.97% # Table walker wait (enqueue to first request) latency 42511860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::327680-393215 18 0.00% 99.98% # Table walker wait (enqueue to first request) latency 42611860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::393216-458751 94 0.02% 99.99% # Table walker wait (enqueue to first request) latency 42711860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::458752-524287 8 0.00% 99.99% # Table walker wait (enqueue to first request) latency 42811860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::524288-589823 9 0.00% 100.00% # Table walker wait (enqueue to first request) latency 42911860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::589824-655359 22 0.00% 100.00% # Table walker wait (enqueue to first request) latency 43011860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::total 536719 # Table walker wait (enqueue to first request) latency 43111860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::samples 489559 # Table walker service (enqueue to completion) latency 43211860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::mean 21856.142978 # Table walker service (enqueue to completion) latency 43311860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::gmean 16984.908569 # Table walker service (enqueue to completion) latency 43411860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::stdev 19510.602702 # Table walker service (enqueue to completion) latency 43511860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::0-65535 478829 97.81% 97.81% # Table walker service (enqueue to completion) latency 43611860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::65536-131071 9216 1.88% 99.69% # Table walker service (enqueue to completion) latency 43711860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::131072-196607 680 0.14% 99.83% # Table walker service (enqueue to completion) latency 43811860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::196608-262143 491 0.10% 99.93% # Table walker service (enqueue to completion) latency 43911860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::262144-327679 167 0.03% 99.96% # Table walker service (enqueue to completion) latency 44011860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::327680-393215 30 0.01% 99.97% # Table walker service (enqueue to completion) latency 44111860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::393216-458751 18 0.00% 99.97% # Table walker service (enqueue to completion) latency 44211860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::458752-524287 13 0.00% 99.98% # Table walker service (enqueue to completion) latency 44311860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::524288-589823 15 0.00% 99.98% # Table walker service (enqueue to completion) latency 44411860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::589824-655359 87 0.02% 100.00% # Table walker service (enqueue to completion) latency 44511860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::655360-720895 13 0.00% 100.00% # Table walker service (enqueue to completion) latency 44611860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::total 489559 # Table walker service (enqueue to completion) latency 44711860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::samples 687539152416 # Table walker pending requests distribution 44811860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::mean 0.766147 # Table walker pending requests distribution 44911860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::stdev 0.508794 # Table walker pending requests distribution 45011860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::0-1 685391448916 99.69% 99.69% # Table walker pending requests distribution 45111860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::2-3 1144327500 0.17% 99.85% # Table walker pending requests distribution 45211860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::4-5 477284500 0.07% 99.92% # Table walker pending requests distribution 45311860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::6-7 191925000 0.03% 99.95% # Table walker pending requests distribution 45411860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::8-9 139963500 0.02% 99.97% # Table walker pending requests distribution 45511860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::10-11 102241500 0.01% 99.99% # Table walker pending requests distribution 45611860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::12-13 33074500 0.00% 99.99% # Table walker pending requests distribution 45711860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::14-15 56365000 0.01% 100.00% # Table walker pending requests distribution 45811860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::16-17 2522000 0.00% 100.00% # Table walker pending requests distribution 45911860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::total 687539152416 # Table walker pending requests distribution 46011860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkPageSizes::4K 162103 89.98% 89.98% # Table walker page sizes translated 46111860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkPageSizes::2M 18061 10.02% 100.00% # Table walker page sizes translated 46211860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkPageSizes::total 180164 # Table walker page sizes translated 46311860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 970467 # Table walker requests started/completed, data/inst 46410628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 46511860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 970467 # Table walker requests started/completed, data/inst 46611860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 180164 # Table walker requests started/completed, data/inst 46710628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 46811860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 180164 # Table walker requests started/completed, data/inst 46911860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 1150631 # Table walker requests started/completed, data/inst 47010585Sandreas.hansson@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 47110585Sandreas.hansson@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 47211860Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 174485449 # DTB read hits 47311860Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses 696020 # DTB read misses 47411860Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 152010399 # DTB write hits 47511860Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 274447 # DTB write misses 47611860Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed 47710585Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 47811860Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 41510 # Number of times TLB was flushed by MVA & ASID 47911860Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_asid 1047 # Number of times TLB was flushed by ASID 48011860Sandreas.hansson@arm.comsystem.cpu.dtb.flush_entries 74778 # Number of entries that have been flushed from TLB 48111860Sandreas.hansson@arm.comsystem.cpu.dtb.align_faults 103 # Number of TLB faults due to alignment restrictions 48211860Sandreas.hansson@arm.comsystem.cpu.dtb.prefetch_faults 10363 # Number of TLB faults due to prefetch 48310585Sandreas.hansson@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 48411860Sandreas.hansson@arm.comsystem.cpu.dtb.perms_faults 69607 # Number of TLB faults due to permissions restrictions 48511860Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 175181469 # DTB read accesses 48611860Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 152284846 # DTB write accesses 48710585Sandreas.hansson@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 48811860Sandreas.hansson@arm.comsystem.cpu.dtb.hits 326495848 # DTB hits 48911860Sandreas.hansson@arm.comsystem.cpu.dtb.misses 970467 # DTB misses 49011860Sandreas.hansson@arm.comsystem.cpu.dtb.accesses 327466315 # DTB accesses 49111860Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 49210628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 49310628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 49410628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 49510628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 49610628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 49710628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 49810628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 49910628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 50010585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 50110585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 50210585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 50310585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 50410585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 50510585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 50610585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 50710585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 50810585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 50910585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 51010585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 51110585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 51210585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 51310585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 51410585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 51510585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 51610585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 51710585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 51810585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 51910585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 52010585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 52111860Sandreas.hansson@arm.comsystem.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 52211860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walks 166329 # Table walker walks requested 52311860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksLong 166329 # Table walker walks initiated with long descriptors 52411860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksLongTerminationLevel::Level2 1543 # Level at which table walker walks with long descriptors terminate 52511860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksLongTerminationLevel::Level3 121824 # Level at which table walker walks with long descriptors terminate 52611860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksSquashedBefore 18039 # Table walks squashed before starting 52711860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::samples 148290 # Table walker wait (enqueue to first request) latency 52811860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::mean 1030.507789 # Table walker wait (enqueue to first request) latency 52911860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::stdev 10121.197556 # Table walker wait (enqueue to first request) latency 53011860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::0-65535 147791 99.66% 99.66% # Table walker wait (enqueue to first request) latency 53111860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::65536-131071 435 0.29% 99.96% # Table walker wait (enqueue to first request) latency 53211860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::131072-196607 25 0.02% 99.97% # Table walker wait (enqueue to first request) latency 53311860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::196608-262143 11 0.01% 99.98% # Table walker wait (enqueue to first request) latency 53411860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::262144-327679 5 0.00% 99.98% # Table walker wait (enqueue to first request) latency 53511860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::327680-393215 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency 53611860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::458752-524287 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency 53711860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::524288-589823 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency 53811860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::589824-655359 11 0.01% 100.00% # Table walker wait (enqueue to first request) latency 53911860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 54011860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::total 148290 # Table walker wait (enqueue to first request) latency 54111860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::samples 141406 # Table walker service (enqueue to completion) latency 54211860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::mean 26889.721794 # Table walker service (enqueue to completion) latency 54311860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::gmean 22183.567838 # Table walker service (enqueue to completion) latency 54411860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::stdev 21940.142141 # Table walker service (enqueue to completion) latency 54511860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::0-65535 138369 97.85% 97.85% # Table walker service (enqueue to completion) latency 54611860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::65536-131071 2580 1.82% 99.68% # Table walker service (enqueue to completion) latency 54711860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::131072-196607 191 0.14% 99.81% # Table walker service (enqueue to completion) latency 54811860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::196608-262143 150 0.11% 99.92% # Table walker service (enqueue to completion) latency 54911860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::262144-327679 40 0.03% 99.95% # Table walker service (enqueue to completion) latency 55011860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::327680-393215 18 0.01% 99.96% # Table walker service (enqueue to completion) latency 55111860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::393216-458751 2 0.00% 99.96% # Table walker service (enqueue to completion) latency 55211860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::524288-589823 2 0.00% 99.96% # Table walker service (enqueue to completion) latency 55311860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::589824-655359 49 0.03% 100.00% # Table walker service (enqueue to completion) latency 55411860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::655360-720895 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 55511860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 55611860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::total 141406 # Table walker service (enqueue to completion) latency 55711860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::samples 580161918016 # Table walker pending requests distribution 55811860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::mean 0.951845 # Table walker pending requests distribution 55911860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::stdev 0.214419 # Table walker pending requests distribution 56011860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::0 27974300560 4.82% 4.82% # Table walker pending requests distribution 56111860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::1 552153156456 95.17% 99.99% # Table walker pending requests distribution 56211860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::2 33290000 0.01% 100.00% # Table walker pending requests distribution 56311860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::3 609500 0.00% 100.00% # Table walker pending requests distribution 56411860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::4 49000 0.00% 100.00% # Table walker pending requests distribution 56511860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::5 512500 0.00% 100.00% # Table walker pending requests distribution 56611860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::total 580161918016 # Table walker pending requests distribution 56711860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkPageSizes::4K 121824 98.75% 98.75% # Table walker page sizes translated 56811860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkPageSizes::2M 1543 1.25% 100.00% # Table walker page sizes translated 56911860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkPageSizes::total 123367 # Table walker page sizes translated 57010628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 57111860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 166329 # Table walker requests started/completed, data/inst 57211860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 166329 # Table walker requests started/completed, data/inst 57310628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 57411860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 123367 # Table walker requests started/completed, data/inst 57511860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 123367 # Table walker requests started/completed, data/inst 57611860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 289696 # Table walker requests started/completed, data/inst 57711860Sandreas.hansson@arm.comsystem.cpu.itb.inst_hits 333977355 # ITB inst hits 57811860Sandreas.hansson@arm.comsystem.cpu.itb.inst_misses 166329 # ITB inst misses 57910585Sandreas.hansson@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 58010585Sandreas.hansson@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 58110585Sandreas.hansson@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 58210585Sandreas.hansson@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 58311860Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed 58410585Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 58511860Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_mva_asid 41510 # Number of times TLB was flushed by MVA & ASID 58611860Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_asid 1047 # Number of times TLB was flushed by ASID 58711860Sandreas.hansson@arm.comsystem.cpu.itb.flush_entries 54464 # Number of entries that have been flushed from TLB 58810585Sandreas.hansson@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 58910585Sandreas.hansson@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 59010585Sandreas.hansson@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 59111860Sandreas.hansson@arm.comsystem.cpu.itb.perms_faults 373131 # Number of TLB faults due to permissions restrictions 59210585Sandreas.hansson@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 59310585Sandreas.hansson@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 59411860Sandreas.hansson@arm.comsystem.cpu.itb.inst_accesses 334143684 # ITB inst accesses 59511860Sandreas.hansson@arm.comsystem.cpu.itb.hits 333977355 # DTB hits 59611860Sandreas.hansson@arm.comsystem.cpu.itb.misses 166329 # DTB misses 59711860Sandreas.hansson@arm.comsystem.cpu.itb.accesses 334143684 # DTB accesses 59811860Sandreas.hansson@arm.comsystem.cpu.numPwrStateTransitions 32546 # Number of power state transitions 59911860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::samples 16273 # Distribution of time spent in the clock gated state 60011860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::mean 3107516335.044798 # Distribution of time spent in the clock gated state 60111860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::stdev 60196725189.485252 # Distribution of time spent in the clock gated state 60211860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::underflows 6948 42.70% 42.70% # Distribution of time spent in the clock gated state 60311860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::1000-5e+10 9289 57.08% 99.78% # Distribution of time spent in the clock gated state 60411860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state 60511860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.83% # Distribution of time spent in the clock gated state 60611860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state 60711860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state 60811860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state 60911860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state 61011687Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 61111860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 61211860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 61311860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state 61411570SCurtis.Dunham@arm.comsystem.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 61511687Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::max_value 1988780762168 # Distribution of time spent in the clock gated state 61611860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::total 16273 # Distribution of time spent in the clock gated state 61711860Sandreas.hansson@arm.comsystem.cpu.pwrStateResidencyTicks::ON 709346089816 # Cumulative time (in ticks) in various power states 61811860Sandreas.hansson@arm.comsystem.cpu.pwrStateResidencyTicks::CLK_GATED 50568613320184 # Cumulative time (in ticks) in various power states 61911860Sandreas.hansson@arm.comsystem.cpu.numCycles 1418701600 # number of cpu cycles simulated 62010585Sandreas.hansson@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 62110585Sandreas.hansson@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 62211860Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 626970761 # Number of cycles fetch is stalled on an Icache miss 62311860Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 964955706 # Number of instructions fetch has processed 62411860Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 214792288 # Number of branches that fetch encountered 62511860Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 120926614 # Number of branches that fetch has predicted taken 62611860Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 712354427 # Number of cycles fetch has run and was not squashing or blocked 62711860Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 26627776 # Number of cycles fetch has spent squashing 62811860Sandreas.hansson@arm.comsystem.cpu.fetch.TlbCycles 3832226 # Number of cycles fetch has spent waiting for tlb 62911860Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 25955 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 63011860Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 9044924 # Number of stall cycles due to pending traps 63111860Sandreas.hansson@arm.comsystem.cpu.fetch.PendingQuiesceStallCycles 1035738 # Number of stall cycles due to pending quiesce instructions 63211860Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 1059 # Number of stall cycles due to full MSHR 63311860Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 333569052 # Number of cache lines fetched 63411860Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 6336680 # Number of outstanding Icache misses that were squashed 63511860Sandreas.hansson@arm.comsystem.cpu.fetch.ItlbSquashes 48713 # Number of outstanding ITLB misses that were squashed 63611860Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 1366578978 # Number of instructions fetched each cycle (Total) 63711860Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 0.835386 # Number of instructions fetched each cycle (Total) 63811860Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 1.187527 # Number of instructions fetched each cycle (Total) 63910585Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 64011860Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 828034594 60.59% 60.59% # Number of instructions fetched each cycle (Total) 64111860Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 202016384 14.78% 75.37% # Number of instructions fetched each cycle (Total) 64211860Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 69979562 5.12% 80.50% # Number of instructions fetched each cycle (Total) 64311860Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 266548438 19.50% 100.00% # Number of instructions fetched each cycle (Total) 64410585Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 64510585Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 64610585Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 64711860Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 1366578978 # Number of instructions fetched each cycle (Total) 64811860Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.151401 # Number of branch fetches per cycle 64911860Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.680168 # Number of inst fetches per cycle 65011860Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 523831535 # Number of cycles decode is idle 65111860Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 358407215 # Number of cycles decode is blocked 65211860Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 444986242 # Number of cycles decode is running 65311860Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 29823356 # Number of cycles decode is unblocking 65411860Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 9530630 # Number of cycles decode is squashing 65511860Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 82997397 # Number of times decode resolved a branch 65611860Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 3840205 # Number of times decode detected a branch misprediction 65711860Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 1051662188 # Number of instructions handled by decode 65811860Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 29872784 # Number of squashed instructions handled by decode 65911860Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 9530630 # Number of cycles rename is squashing 66011860Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 559062030 # Number of cycles rename is idle 66111860Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 58275029 # Number of cycles rename is blocking 66211860Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 221284587 # count of cycles rename stalled for serializing inst 66311860Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 439543391 # Number of cycles rename is running 66411860Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 78883311 # Number of cycles rename is unblocking 66511860Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 1030946151 # Number of instructions processed by rename 66611860Sandreas.hansson@arm.comsystem.cpu.rename.SquashedInsts 7084405 # Number of squashed instructions processed by rename 66711860Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 5220432 # Number of times rename has blocked due to ROB full 66811860Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 401053 # Number of times rename has blocked due to IQ full 66911860Sandreas.hansson@arm.comsystem.cpu.rename.LQFullEvents 689601 # Number of times rename has blocked due to LQ full 67011860Sandreas.hansson@arm.comsystem.cpu.rename.SQFullEvents 52909282 # Number of times rename has blocked due to SQ full 67111860Sandreas.hansson@arm.comsystem.cpu.rename.FullRegisterEvents 20659 # Number of times there has been no free registers 67211860Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 944726342 # Number of destination operands rename has renamed 67311860Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 1460373617 # Number of register rename lookups that rename has made 67411860Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 1214391439 # Number of integer rename lookups 67511860Sandreas.hansson@arm.comsystem.cpu.rename.fp_rename_lookups 1466073 # Number of floating rename lookups 67611860Sandreas.hansson@arm.comsystem.cpu.rename.CommittedMaps 877604087 # Number of HB maps that are committed 67711860Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 67122252 # Number of HB maps that are undone due to squashing 67811860Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 11621737 # count of serializing insts renamed 67911860Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 7877357 # count of temporary serializing insts renamed 68011860Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 58456344 # count of insts added to the skid buffer 68111860Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 178961087 # Number of loads inserted to the mem dependence unit. 68211860Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 155538156 # Number of stores inserted to the mem dependence unit. 68311860Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 10194150 # Number of conflicting loads. 68411860Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingStores 9195511 # Number of conflicting stores. 68511860Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 1010975595 # Number of instructions added to the IQ (excludes non-spec) 68611860Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 11936880 # Number of non-speculative instructions added to the IQ 68711860Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 1010573430 # Number of instructions issued 68811860Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 3406540 # Number of squashed instructions issued 68911860Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 62033200 # Number of squashed instructions iterated over during squash; mainly for profiling 69011860Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 34713553 # Number of squashed operands that are examined and possibly removed from graph 69111860Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 312805 # Number of squashed non-spec instructions that were removed 69211860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 1366578978 # Number of insts issued each cycle 69311860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.739491 # Number of insts issued each cycle 69411860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 0.966076 # Number of insts issued each cycle 69510585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 69611860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 766524619 56.09% 56.09% # Number of insts issued each cycle 69711860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 278054062 20.35% 76.44% # Number of insts issued each cycle 69811860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 240507320 17.60% 94.04% # Number of insts issued each cycle 69911860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 74487645 5.45% 99.49% # Number of insts issued each cycle 70011860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 6984867 0.51% 100.00% # Number of insts issued each cycle 70111860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 20465 0.00% 100.00% # Number of insts issued each cycle 70210585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 70310585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 70410585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 70510585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 70610585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 70710585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 70811860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 1366578978 # Number of insts issued each cycle 70910585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 71011860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 59327643 34.80% 34.80% # attempts to use FU when none available 71111860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 97860 0.06% 34.86% # attempts to use FU when none available 71211860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 26629 0.02% 34.87% # attempts to use FU when none available 71311860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 34.87% # attempts to use FU when none available 71411860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 34.87% # attempts to use FU when none available 71511860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 34.87% # attempts to use FU when none available 71611860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 34.87% # attempts to use FU when none available 71711860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMultAcc 0 0.00% 34.87% # attempts to use FU when none available 71811860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 34.87% # attempts to use FU when none available 71911860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMisc 606 0.00% 34.87% # attempts to use FU when none available 72011860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.87% # attempts to use FU when none available 72111860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 34.87% # attempts to use FU when none available 72211860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.87% # attempts to use FU when none available 72311860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 34.87% # attempts to use FU when none available 72411860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 34.87% # attempts to use FU when none available 72511860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 34.87% # attempts to use FU when none available 72611860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 34.87% # attempts to use FU when none available 72711860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 34.87% # attempts to use FU when none available 72811860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.87% # attempts to use FU when none available 72911860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 34.87% # attempts to use FU when none available 73011860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.87% # attempts to use FU when none available 73111860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.87% # attempts to use FU when none available 73211860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.87% # attempts to use FU when none available 73311860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.87% # attempts to use FU when none available 73411860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.87% # attempts to use FU when none available 73511860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.87% # attempts to use FU when none available 73611860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.87% # attempts to use FU when none available 73711860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.87% # attempts to use FU when none available 73811860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.87% # attempts to use FU when none available 73911860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.87% # attempts to use FU when none available 74011860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.87% # attempts to use FU when none available 74111860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 45774518 26.85% 61.72% # attempts to use FU when none available 74211860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 64550245 37.86% 99.58% # attempts to use FU when none available 74311860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMemRead 65013 0.04% 99.62% # attempts to use FU when none available 74411860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMemWrite 650262 0.38% 100.00% # attempts to use FU when none available 74510585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 74610585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 74711860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued 74811860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 675222587 66.82% 66.82% # Type of FU issued 74911860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 2579661 0.26% 67.07% # Type of FU issued 75011860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 123552 0.01% 67.08% # Type of FU issued 75111860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 381 0.00% 67.08% # Type of FU issued 75211860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 15 0.00% 67.08% # Type of FU issued 75311860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 24 0.00% 67.08% # Type of FU issued 75411860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.08% # Type of FU issued 75511860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.08% # Type of FU issued 75611860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.08% # Type of FU issued 75711860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMisc 118042 0.01% 67.10% # Type of FU issued 75811860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.10% # Type of FU issued 75911860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.10% # Type of FU issued 76011860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.10% # Type of FU issued 76111860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.10% # Type of FU issued 76211860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.10% # Type of FU issued 76311860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.10% # Type of FU issued 76411860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.10% # Type of FU issued 76511860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.10% # Type of FU issued 76611860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.10% # Type of FU issued 76711860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.10% # Type of FU issued 76811860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.10% # Type of FU issued 76911860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.10% # Type of FU issued 77011860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.10% # Type of FU issued 77111860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.10% # Type of FU issued 77211860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.10% # Type of FU issued 77311860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.10% # Type of FU issued 77411860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.10% # Type of FU issued 77511860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.10% # Type of FU issued 77611860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10% # Type of FU issued 77711860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.10% # Type of FU issued 77811860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10% # Type of FU issued 77911860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 178525210 17.67% 84.76% # Type of FU issued 78011860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 153211297 15.16% 99.92% # Type of FU issued 78111860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMemRead 117761 0.01% 99.93% # Type of FU issued 78211860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMemWrite 674889 0.07% 100.00% # Type of FU issued 78310585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 78410585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 78511860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 1010573430 # Type of FU issued 78611860Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.712323 # Inst issue rate 78711860Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 170492776 # FU busy when requested 78811860Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.168709 # FU busy rate (busy events/executed inst) 78911860Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 3559085350 # Number of integer instruction queue reads 79011860Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 1084154908 # Number of integer instruction queue writes 79111860Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 991977756 # Number of integer instruction queue wakeup accesses 79211860Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_reads 2539803 # Number of floating instruction queue reads 79311860Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 933979 # Number of floating instruction queue writes 79411860Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 905255 # Number of floating instruction queue wakeup accesses 79511860Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 1179439202 # Number of integer alu accesses 79611860Sandreas.hansson@arm.comsystem.cpu.iq.fp_alu_accesses 1626993 # Number of floating point alu accesses 79711860Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 4435926 # Number of loads that had data forwarded from stores 79810585Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 79911860Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 14385160 # Number of loads squashed 80011860Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 15174 # Number of memory responses ignored because the instruction is squashed 80111860Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 144472 # Number of memory ordering violations 80211860Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 6174251 # Number of stores squashed 80310585Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 80410585Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 80511860Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 2629445 # Number of loads that were rescheduled 80611860Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 1524875 # Number of times an access to memory failed due to the cache being blocked 80710585Sandreas.hansson@arm.comsystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 80811860Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 9530630 # Number of cycles IEW is squashing 80911860Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 7210038 # Number of cycles IEW is blocking 81011860Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 4323845 # Number of cycles IEW is unblocking 81111860Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 1023153770 # Number of instructions dispatched to IQ 81210585Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 81311860Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 178961087 # Number of dispatched load instructions 81411860Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 155538156 # Number of dispatched store instructions 81511860Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 7437223 # Number of dispatched non-speculative instructions 81611860Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 69213 # Number of times the IQ has become full, causing a stall 81711860Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 4169498 # Number of times the LSQ has become full, causing a stall 81811860Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 144472 # Number of memory order violations 81911860Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 3542728 # Number of branches that were predicted taken incorrectly 82011860Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 5585702 # Number of branches that were predicted not taken incorrectly 82111860Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 9128430 # Number of branch mispredicts detected at execute 82211860Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 998939859 # Number of executed instructions 82311860Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 174475303 # Number of load instructions executed 82411860Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 10677060 # Number of squashed instructions skipped in execute 82510585Sandreas.hansson@arm.comsystem.cpu.iew.exec_swp 0 # number of swp insts executed 82611860Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 241295 # number of nop insts executed 82711860Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 326482764 # number of memory reference insts executed 82811860Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 185483896 # Number of branches executed 82911860Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 152007461 # Number of stores executed 83011860Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.704123 # Inst execution rate 83111860Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 993723823 # cumulative count of insts sent to commit 83211860Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 992883011 # cumulative count of insts written-back 83311860Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 420701773 # num instructions producing a value 83411860Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 671731184 # num instructions consuming a value 83511860Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.699853 # insts written-back per cycle 83611860Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.626295 # average fanout of values written-back 83711860Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 52581924 # The number of squashed insts skipped by commit 83811860Sandreas.hansson@arm.comsystem.cpu.commit.commitNonSpecStalls 11624075 # The number of times commit has been forced to stall to communicate backwards 83911860Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 8681545 # The number of times a branch was mispredicted 84011860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 1354317292 # Number of insts commited each cycle 84111860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.709493 # Number of insts commited each cycle 84211860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.365584 # Number of insts commited each cycle 84310585Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 84411860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 893350952 65.96% 65.96% # Number of insts commited each cycle 84511860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 231145639 17.07% 83.03% # Number of insts commited each cycle 84611860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 123165028 9.09% 92.12% # Number of insts commited each cycle 84711860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 37514552 2.77% 94.89% # Number of insts commited each cycle 84811860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 29252763 2.16% 97.05% # Number of insts commited each cycle 84911860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 14325561 1.06% 98.11% # Number of insts commited each cycle 85011860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 8938173 0.66% 98.77% # Number of insts commited each cycle 85111860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 4404967 0.33% 99.10% # Number of insts commited each cycle 85211860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 12219657 0.90% 100.00% # Number of insts commited each cycle 85310585Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 85410585Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 85510585Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 85611860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 1354317292 # Number of insts commited each cycle 85711860Sandreas.hansson@arm.comsystem.cpu.commit.committedInsts 807652759 # Number of instructions committed 85811860Sandreas.hansson@arm.comsystem.cpu.commit.committedOps 960879271 # Number of ops (including micro ops) committed 85910585Sandreas.hansson@arm.comsystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 86011860Sandreas.hansson@arm.comsystem.cpu.commit.refs 313939831 # Number of memory references committed 86111860Sandreas.hansson@arm.comsystem.cpu.commit.loads 164575926 # Number of loads committed 86211860Sandreas.hansson@arm.comsystem.cpu.commit.membars 7185354 # Number of memory barriers committed 86311860Sandreas.hansson@arm.comsystem.cpu.commit.branches 178524482 # Number of branches committed 86411860Sandreas.hansson@arm.comsystem.cpu.commit.fp_insts 893967 # Number of committed floating point instructions. 86511860Sandreas.hansson@arm.comsystem.cpu.commit.int_insts 893684330 # Number of committed integer instructions. 86611860Sandreas.hansson@arm.comsystem.cpu.commit.function_calls 25910780 # Number of function calls committed. 86710585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 86811860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntAlu 644536442 67.08% 67.08% # Class of committed instruction 86911860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntMult 2193608 0.23% 67.31% # Class of committed instruction 87011860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntDiv 98465 0.01% 67.32% # Class of committed instruction 87111860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatAdd 8 0.00% 67.32% # Class of committed instruction 87211860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCmp 13 0.00% 67.32% # Class of committed instruction 87311860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCvt 21 0.00% 67.32% # Class of committed instruction 87411860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 67.32% # Class of committed instruction 87511860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 67.32% # Class of committed instruction 87611860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.32% # Class of committed instruction 87711860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMisc 110883 0.01% 67.33% # Class of committed instruction 87811860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.33% # Class of committed instruction 87911860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.33% # Class of committed instruction 88011860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.33% # Class of committed instruction 88111860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.33% # Class of committed instruction 88211860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.33% # Class of committed instruction 88311860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.33% # Class of committed instruction 88411860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.33% # Class of committed instruction 88511860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 67.33% # Class of committed instruction 88611860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.33% # Class of committed instruction 88711860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 67.33% # Class of committed instruction 88811860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.33% # Class of committed instruction 88911860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.33% # Class of committed instruction 89011860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.33% # Class of committed instruction 89111860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.33% # Class of committed instruction 89211860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.33% # Class of committed instruction 89311860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.33% # Class of committed instruction 89411860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.33% # Class of committed instruction 89511860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.33% # Class of committed instruction 89611860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.33% # Class of committed instruction 89711860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.33% # Class of committed instruction 89811860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.33% # Class of committed instruction 89911860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 164464107 17.12% 84.44% # Class of committed instruction 90011860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 148692682 15.47% 99.92% # Class of committed instruction 90111860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMemRead 111819 0.01% 99.93% # Class of committed instruction 90211860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMemWrite 671223 0.07% 100.00% # Class of committed instruction 90310585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 90410585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 90511860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::total 960879271 # Class of committed instruction 90611860Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 12219657 # number cycles where commit BW limit reached 90711860Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 2347791153 # The number of ROB reads 90811860Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 2039089805 # The number of ROB writes 90911860Sandreas.hansson@arm.comsystem.cpu.timesIdled 8233460 # Number of times that the entire CPU went into an idle state and unscheduled itself 91011860Sandreas.hansson@arm.comsystem.cpu.idleCycles 52122622 # Total number of cycles that the CPU has spent unscheduled due to idling 91111860Sandreas.hansson@arm.comsystem.cpu.quiesceCycles 101137217350 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 91211860Sandreas.hansson@arm.comsystem.cpu.committedInsts 807652759 # Number of Instructions Simulated 91311860Sandreas.hansson@arm.comsystem.cpu.committedOps 960879271 # Number of Ops (including micro ops) Simulated 91411860Sandreas.hansson@arm.comsystem.cpu.cpi 1.756574 # CPI: Cycles Per Instruction 91511860Sandreas.hansson@arm.comsystem.cpu.cpi_total 1.756574 # CPI: Total CPI of All Threads 91611860Sandreas.hansson@arm.comsystem.cpu.ipc 0.569290 # IPC: Instructions Per Cycle 91711860Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.569290 # IPC: Total IPC of All Threads 91811860Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 1178021092 # number of integer regfile reads 91911860Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 719548586 # number of integer regfile writes 92011860Sandreas.hansson@arm.comsystem.cpu.fp_regfile_reads 1455011 # number of floating regfile reads 92111860Sandreas.hansson@arm.comsystem.cpu.fp_regfile_writes 777624 # number of floating regfile writes 92211860Sandreas.hansson@arm.comsystem.cpu.cc_regfile_reads 183031164 # number of cc regfile reads 92311860Sandreas.hansson@arm.comsystem.cpu.cc_regfile_writes 183683629 # number of cc regfile writes 92411860Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 2245464732 # number of misc regfile reads 92511860Sandreas.hansson@arm.comsystem.cpu.misc_regfile_writes 11742996 # number of misc regfile writes 92611860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 92711860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 10097387 # number of replacements 92811860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 511.998168 # Cycle average of tags in use 92911860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 291447803 # Total number of references to valid blocks. 93011860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 10097899 # Sample count of references to valid blocks. 93111860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 28.862222 # Average number of references to valid blocks. 93211860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 194046500 # Cycle when the warmup percentage was hit. 93311860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.998168 # Average occupied blocks per requestor 93411860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy 93511860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy 93610585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 93711860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id 93811860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 399 # Occupied blocks per task id 93911860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id 94011860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 94110585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 94211860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 1275104379 # Number of tag accesses 94311860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 1275104379 # Number of data accesses 94411860Sandreas.hansson@arm.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 94511860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 151424979 # number of ReadReq hits 94611860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 151424979 # number of ReadReq hits 94711860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 131950159 # number of WriteReq hits 94811860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 131950159 # number of WriteReq hits 94911860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 388682 # number of SoftPFReq hits 95011860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 388682 # number of SoftPFReq hits 95111860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_hits::cpu.data 326177 # number of WriteLineReq hits 95211860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_hits::total 326177 # number of WriteLineReq hits 95311860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 3459521 # number of LoadLockedReq hits 95411860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 3459521 # number of LoadLockedReq hits 95511860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 3868336 # number of StoreCondReq hits 95611860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 3868336 # number of StoreCondReq hits 95711860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 283701315 # number of demand (read+write) hits 95811860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 283701315 # number of demand (read+write) hits 95911860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 284089997 # number of overall hits 96011860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 284089997 # number of overall hits 96111860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 9913119 # number of ReadReq misses 96211860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 9913119 # number of ReadReq misses 96311860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 11970495 # number of WriteReq misses 96411860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 11970495 # number of WriteReq misses 96511860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 1253745 # number of SoftPFReq misses 96611860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 1253745 # number of SoftPFReq misses 96711860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_misses::cpu.data 1236891 # number of WriteLineReq misses 96811860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_misses::total 1236891 # number of WriteLineReq misses 96911860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 459501 # number of LoadLockedReq misses 97011860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 459501 # number of LoadLockedReq misses 97111860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::cpu.data 9 # number of StoreCondReq misses 97211860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::total 9 # number of StoreCondReq misses 97311860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 23120505 # number of demand (read+write) misses 97411860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 23120505 # number of demand (read+write) misses 97511860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 24374250 # number of overall misses 97611860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 24374250 # number of overall misses 97711860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 163455721000 # number of ReadReq miss cycles 97811860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 163455721000 # number of ReadReq miss cycles 97911860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 418494791659 # number of WriteReq miss cycles 98011860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 418494791659 # number of WriteReq miss cycles 98111860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_miss_latency::cpu.data 27820801905 # number of WriteLineReq miss cycles 98211860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_miss_latency::total 27820801905 # number of WriteLineReq miss cycles 98311860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6946845500 # number of LoadLockedReq miss cycles 98411860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 6946845500 # number of LoadLockedReq miss cycles 98511860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::cpu.data 284500 # number of StoreCondReq miss cycles 98611860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::total 284500 # number of StoreCondReq miss cycles 98711860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 609771314564 # number of demand (read+write) miss cycles 98811860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 609771314564 # number of demand (read+write) miss cycles 98911860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 609771314564 # number of overall miss cycles 99011860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 609771314564 # number of overall miss cycles 99111860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 161338098 # number of ReadReq accesses(hits+misses) 99211860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 161338098 # number of ReadReq accesses(hits+misses) 99311860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 143920654 # number of WriteReq accesses(hits+misses) 99411860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 143920654 # number of WriteReq accesses(hits+misses) 99511860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 1642427 # number of SoftPFReq accesses(hits+misses) 99611860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 1642427 # number of SoftPFReq accesses(hits+misses) 99711860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_accesses::cpu.data 1563068 # number of WriteLineReq accesses(hits+misses) 99811860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_accesses::total 1563068 # number of WriteLineReq accesses(hits+misses) 99911860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 3919022 # number of LoadLockedReq accesses(hits+misses) 100011860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 3919022 # number of LoadLockedReq accesses(hits+misses) 100111860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 3868345 # number of StoreCondReq accesses(hits+misses) 100211860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 3868345 # number of StoreCondReq accesses(hits+misses) 100311860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 306821820 # number of demand (read+write) accesses 100411860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 306821820 # number of demand (read+write) accesses 100511860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 308464247 # number of overall (read+write) accesses 100611860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 308464247 # number of overall (read+write) accesses 100711860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061443 # miss rate for ReadReq accesses 100811860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.061443 # miss rate for ReadReq accesses 100911860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.083174 # miss rate for WriteReq accesses 101011860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.083174 # miss rate for WriteReq accesses 101111860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.763349 # miss rate for SoftPFReq accesses 101211860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.763349 # miss rate for SoftPFReq accesses 101311860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791323 # miss rate for WriteLineReq accesses 101411860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_miss_rate::total 0.791323 # miss rate for WriteLineReq accesses 101511860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.117249 # miss rate for LoadLockedReq accesses 101611860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.117249 # miss rate for LoadLockedReq accesses 101711754Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses 101811754Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses 101911860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.075355 # miss rate for demand accesses 102011860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.075355 # miss rate for demand accesses 102111860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.079018 # miss rate for overall accesses 102211860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.079018 # miss rate for overall accesses 102311860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16488.828693 # average ReadReq miss latency 102411860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 16488.828693 # average ReadReq miss latency 102511860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34960.525163 # average WriteReq miss latency 102611860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 34960.525163 # average WriteReq miss latency 102711860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 22492.525134 # average WriteLineReq miss latency 102811860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_avg_miss_latency::total 22492.525134 # average WriteLineReq miss latency 102911860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15118.238045 # average LoadLockedReq miss latency 103011860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15118.238045 # average LoadLockedReq miss latency 103111860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 31611.111111 # average StoreCondReq miss latency 103211860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::total 31611.111111 # average StoreCondReq miss latency 103311860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 26373.615739 # average overall miss latency 103411860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 26373.615739 # average overall miss latency 103511860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 25017.028814 # average overall miss latency 103611860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 25017.028814 # average overall miss latency 103711860Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 19489299 # number of cycles access was blocked 103810585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 103911860Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 1643530 # number of cycles access was blocked 104010585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 104111860Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 11.858195 # average number of cycles each access was blocked 104210585Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 104311860Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 7764980 # number of writebacks 104411860Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 7764980 # number of writebacks 104511860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 4590646 # number of ReadReq MSHR hits 104611860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 4590646 # number of ReadReq MSHR hits 104711860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 9875948 # number of WriteReq MSHR hits 104811860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 9875948 # number of WriteReq MSHR hits 104911860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 6846 # number of WriteLineReq MSHR hits 105011860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_hits::total 6846 # number of WriteLineReq MSHR hits 105111860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 225673 # number of LoadLockedReq MSHR hits 105211860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 225673 # number of LoadLockedReq MSHR hits 105311860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 14473440 # number of demand (read+write) MSHR hits 105411860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 14473440 # number of demand (read+write) MSHR hits 105511860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 14473440 # number of overall MSHR hits 105611860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 14473440 # number of overall MSHR hits 105711860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 5322473 # number of ReadReq MSHR misses 105811860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 5322473 # number of ReadReq MSHR misses 105911860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 2094547 # number of WriteReq MSHR misses 106011860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 2094547 # number of WriteReq MSHR misses 106111860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1246940 # number of SoftPFReq MSHR misses 106211860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::total 1246940 # number of SoftPFReq MSHR misses 106311860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1230045 # number of WriteLineReq MSHR misses 106411860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_misses::total 1230045 # number of WriteLineReq MSHR misses 106511860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 233828 # number of LoadLockedReq MSHR misses 106611860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::total 233828 # number of LoadLockedReq MSHR misses 106711860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 9 # number of StoreCondReq MSHR misses 106811860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::total 9 # number of StoreCondReq MSHR misses 106911860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 8647065 # number of demand (read+write) MSHR misses 107011860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 8647065 # number of demand (read+write) MSHR misses 107111860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 9894005 # number of overall MSHR misses 107211860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 9894005 # number of overall MSHR misses 107311860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33590 # number of ReadReq MSHR uncacheable 107411860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable::total 33590 # number of ReadReq MSHR uncacheable 107511860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33609 # number of WriteReq MSHR uncacheable 107611860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable::total 33609 # number of WriteReq MSHR uncacheable 107711860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67199 # number of overall MSHR uncacheable misses 107811860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_misses::total 67199 # number of overall MSHR uncacheable misses 107911860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84299556500 # number of ReadReq MSHR miss cycles 108011860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 84299556500 # number of ReadReq MSHR miss cycles 108111860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 70150658430 # number of WriteReq MSHR miss cycles 108211860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 70150658430 # number of WriteReq MSHR miss cycles 108311860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 22795031000 # number of SoftPFReq MSHR miss cycles 108411860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 22795031000 # number of SoftPFReq MSHR miss cycles 108511860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 26312863405 # number of WriteLineReq MSHR miss cycles 108611860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_miss_latency::total 26312863405 # number of WriteLineReq MSHR miss cycles 108711860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3251889000 # number of LoadLockedReq MSHR miss cycles 108811860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3251889000 # number of LoadLockedReq MSHR miss cycles 108911860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 275500 # number of StoreCondReq MSHR miss cycles 109011860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::total 275500 # number of StoreCondReq MSHR miss cycles 109111860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 180763078335 # number of demand (read+write) MSHR miss cycles 109211860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 180763078335 # number of demand (read+write) MSHR miss cycles 109311860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 203558109335 # number of overall MSHR miss cycles 109411860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 203558109335 # number of overall MSHR miss cycles 109511860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6204454000 # number of ReadReq MSHR uncacheable cycles 109611860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6204454000 # number of ReadReq MSHR uncacheable cycles 109711860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6204454000 # number of overall MSHR uncacheable cycles 109811860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::total 6204454000 # number of overall MSHR uncacheable cycles 109911860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032990 # mshr miss rate for ReadReq accesses 110011860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032990 # mshr miss rate for ReadReq accesses 110111860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014553 # mshr miss rate for WriteReq accesses 110211860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014553 # mshr miss rate for WriteReq accesses 110311860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.759206 # mshr miss rate for SoftPFReq accesses 110411860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.759206 # mshr miss rate for SoftPFReq accesses 110511860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786943 # mshr miss rate for WriteLineReq accesses 110611860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786943 # mshr miss rate for WriteLineReq accesses 110711860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.059665 # mshr miss rate for LoadLockedReq accesses 110811860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.059665 # mshr miss rate for LoadLockedReq accesses 110911754Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses 111011754Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses 111111860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028183 # mshr miss rate for demand accesses 111211860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.028183 # mshr miss rate for demand accesses 111311860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032075 # mshr miss rate for overall accesses 111411860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.032075 # mshr miss rate for overall accesses 111511860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15838.418814 # average ReadReq mshr miss latency 111611860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15838.418814 # average ReadReq mshr miss latency 111711860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33492.043115 # average WriteReq mshr miss latency 111811860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33492.043115 # average WriteReq mshr miss latency 111911860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18280.776140 # average SoftPFReq mshr miss latency 112011860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18280.776140 # average SoftPFReq mshr miss latency 112111860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 21391.789248 # average WriteLineReq mshr miss latency 112211860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 21391.789248 # average WriteLineReq mshr miss latency 112311860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13907.183913 # average LoadLockedReq mshr miss latency 112411860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13907.183913 # average LoadLockedReq mshr miss latency 112511860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 30611.111111 # average StoreCondReq mshr miss latency 112611860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 30611.111111 # average StoreCondReq mshr miss latency 112711860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20904.558753 # average overall mshr miss latency 112811860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 20904.558753 # average overall mshr miss latency 112911860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20573.883815 # average overall mshr miss latency 113011860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 20573.883815 # average overall mshr miss latency 113111860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184711.342662 # average ReadReq mshr uncacheable latency 113211860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184711.342662 # average ReadReq mshr uncacheable latency 113311860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92329.558476 # average overall mshr uncacheable latency 113411860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92329.558476 # average overall mshr uncacheable latency 113511860Sandreas.hansson@arm.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 113611860Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 15304958 # number of replacements 113711860Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 511.969276 # Cycle average of tags in use 113811860Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 317502771 # Total number of references to valid blocks. 113911860Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 15305470 # Sample count of references to valid blocks. 114011860Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 20.744399 # Average number of references to valid blocks. 114111860Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 12156673500 # Cycle when the warmup percentage was hit. 114211860Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 511.969276 # Average occupied blocks per requestor 114311860Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.999940 # Average percentage of cache occupancy 114411860Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.999940 # Average percentage of cache occupancy 114510585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 114611860Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id 114711860Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id 114811860Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id 114910585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 115011860Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 348872656 # Number of tag accesses 115111860Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 348872656 # Number of data accesses 115211860Sandreas.hansson@arm.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 115311860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 317502771 # number of ReadReq hits 115411860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 317502771 # number of ReadReq hits 115511860Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 317502771 # number of demand (read+write) hits 115611860Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 317502771 # number of demand (read+write) hits 115711860Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 317502771 # number of overall hits 115811860Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 317502771 # number of overall hits 115911860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 16064183 # number of ReadReq misses 116011860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 16064183 # number of ReadReq misses 116111860Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 16064183 # number of demand (read+write) misses 116211860Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 16064183 # number of demand (read+write) misses 116311860Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 16064183 # number of overall misses 116411860Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 16064183 # number of overall misses 116511860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 215226774877 # number of ReadReq miss cycles 116611860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 215226774877 # number of ReadReq miss cycles 116711860Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 215226774877 # number of demand (read+write) miss cycles 116811860Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 215226774877 # number of demand (read+write) miss cycles 116911860Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 215226774877 # number of overall miss cycles 117011860Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 215226774877 # number of overall miss cycles 117111860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 333566954 # number of ReadReq accesses(hits+misses) 117211860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 333566954 # number of ReadReq accesses(hits+misses) 117311860Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 333566954 # number of demand (read+write) accesses 117411860Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 333566954 # number of demand (read+write) accesses 117511860Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 333566954 # number of overall (read+write) accesses 117611860Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 333566954 # number of overall (read+write) accesses 117711860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.048159 # miss rate for ReadReq accesses 117811860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.048159 # miss rate for ReadReq accesses 117911860Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.048159 # miss rate for demand accesses 118011860Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.048159 # miss rate for demand accesses 118111860Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.048159 # miss rate for overall accesses 118211860Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.048159 # miss rate for overall accesses 118311860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13397.928477 # average ReadReq miss latency 118411860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 13397.928477 # average ReadReq miss latency 118511860Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 13397.928477 # average overall miss latency 118611860Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 13397.928477 # average overall miss latency 118711860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 13397.928477 # average overall miss latency 118811860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 13397.928477 # average overall miss latency 118911860Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 20885 # number of cycles access was blocked 119010585Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 119111860Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 1543 # number of cycles access was blocked 119210585Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 119311860Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 13.535321 # average number of cycles each access was blocked 119410585Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 119511860Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::writebacks 15304958 # number of writebacks 119611860Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::total 15304958 # number of writebacks 119711860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 758480 # number of ReadReq MSHR hits 119811860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 758480 # number of ReadReq MSHR hits 119911860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 758480 # number of demand (read+write) MSHR hits 120011860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 758480 # number of demand (read+write) MSHR hits 120111860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 758480 # number of overall MSHR hits 120211860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 758480 # number of overall MSHR hits 120311860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 15305703 # number of ReadReq MSHR misses 120411860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 15305703 # number of ReadReq MSHR misses 120511860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 15305703 # number of demand (read+write) MSHR misses 120611860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 15305703 # number of demand (read+write) MSHR misses 120711860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 15305703 # number of overall MSHR misses 120811860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 15305703 # number of overall MSHR misses 120911860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 2094 # number of ReadReq MSHR uncacheable 121011860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable::total 2094 # number of ReadReq MSHR uncacheable 121111860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 2094 # number of overall MSHR uncacheable misses 121211860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_misses::total 2094 # number of overall MSHR uncacheable misses 121311860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 193058693887 # number of ReadReq MSHR miss cycles 121411860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 193058693887 # number of ReadReq MSHR miss cycles 121511860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 193058693887 # number of demand (read+write) MSHR miss cycles 121611860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 193058693887 # number of demand (read+write) MSHR miss cycles 121711860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 193058693887 # number of overall MSHR miss cycles 121811860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 193058693887 # number of overall MSHR miss cycles 121911860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 174071500 # number of ReadReq MSHR uncacheable cycles 122011860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable_latency::total 174071500 # number of ReadReq MSHR uncacheable cycles 122111860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 174071500 # number of overall MSHR uncacheable cycles 122211860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_latency::total 174071500 # number of overall MSHR uncacheable cycles 122311860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.045885 # mshr miss rate for ReadReq accesses 122411860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.045885 # mshr miss rate for ReadReq accesses 122511860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.045885 # mshr miss rate for demand accesses 122611860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.045885 # mshr miss rate for demand accesses 122711860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.045885 # mshr miss rate for overall accesses 122811860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.045885 # mshr miss rate for overall accesses 122911860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12613.513661 # average ReadReq mshr miss latency 123011860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12613.513661 # average ReadReq mshr miss latency 123111860Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12613.513661 # average overall mshr miss latency 123211860Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 12613.513661 # average overall mshr miss latency 123311860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12613.513661 # average overall mshr miss latency 123411860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 12613.513661 # average overall mshr miss latency 123511860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 83128.701051 # average ReadReq mshr uncacheable latency 123611860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 83128.701051 # average ReadReq mshr uncacheable latency 123711860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 83128.701051 # average overall mshr uncacheable latency 123811860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_uncacheable_latency::total 83128.701051 # average overall mshr uncacheable latency 123911860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 124011860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 1248689 # number of replacements 124111860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 65406.058647 # Cycle average of tags in use 124211860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 49295549 # Total number of references to valid blocks. 124311860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 1311963 # Sample count of references to valid blocks. 124411860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 37.573887 # Average number of references to valid blocks. 124511860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 1068241000 # Cycle when the warmup percentage was hit. 124611860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 9667.637617 # Average occupied blocks per requestor 124711860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 499.308772 # Average occupied blocks per requestor 124811860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 609.219516 # Average occupied blocks per requestor 124911860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 6963.202905 # Average occupied blocks per requestor 125011860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 47666.689838 # Average occupied blocks per requestor 125111860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.147516 # Average percentage of cache occupancy 125211860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.007619 # Average percentage of cache occupancy 125311860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.009296 # Average percentage of cache occupancy 125411860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.106250 # Average percentage of cache occupancy 125511860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.727336 # Average percentage of cache occupancy 125611860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.998017 # Average percentage of cache occupancy 125711860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1023 512 # Occupied blocks per task id 125811860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 62762 # Occupied blocks per task id 125911860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1023::4 512 # Occupied blocks per task id 126011860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id 126111860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 377 # Occupied blocks per task id 126211860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 1132 # Occupied blocks per task id 126311860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 5479 # Occupied blocks per task id 126411860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 55729 # Occupied blocks per task id 126511860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1023 0.007812 # Percentage of cache occupancy per task id 126611860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.957672 # Percentage of cache occupancy per task id 126711860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 417429422 # Number of tag accesses 126811860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 417429422 # Number of data accesses 126911860Sandreas.hansson@arm.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 127011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 796619 # number of ReadReq hits 127111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.itb.walker 283100 # number of ReadReq hits 127211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 1079719 # number of ReadReq hits 127311860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 7764980 # number of WritebackDirty hits 127411860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 7764980 # number of WritebackDirty hits 127511860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 15302294 # number of WritebackClean hits 127611860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 15302294 # number of WritebackClean hits 127711860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 25817 # number of UpgradeReq hits 127811860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 25817 # number of UpgradeReq hits 127911860Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::cpu.data 6 # number of SCUpgradeReq hits 128011860Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::total 6 # number of SCUpgradeReq hits 128111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 1591016 # number of ReadExReq hits 128211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 1591016 # number of ReadExReq hits 128311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 15218653 # number of ReadCleanReq hits 128411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 15218653 # number of ReadCleanReq hits 128511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 6530102 # number of ReadSharedReq hits 128611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 6530102 # number of ReadSharedReq hits 128711860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_hits::cpu.data 728891 # number of InvalidateReq hits 128811860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_hits::total 728891 # number of InvalidateReq hits 128911860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.dtb.walker 796619 # number of demand (read+write) hits 129011860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.itb.walker 283100 # number of demand (read+write) hits 129111860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 15218653 # number of demand (read+write) hits 129211860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 8121118 # number of demand (read+write) hits 129311860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 24419490 # number of demand (read+write) hits 129411860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.dtb.walker 796619 # number of overall hits 129511860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.itb.walker 283100 # number of overall hits 129611860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 15218653 # number of overall hits 129711860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 8121118 # number of overall hits 129811860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 24419490 # number of overall hits 129911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3956 # number of ReadReq misses 130011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3665 # number of ReadReq misses 130111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 7621 # number of ReadReq misses 130211860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 4094 # number of UpgradeReq misses 130311860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 4094 # number of UpgradeReq misses 130411754Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses 130511754Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses 130611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 478353 # number of ReadExReq misses 130711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 478353 # number of ReadExReq misses 130811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 86839 # number of ReadCleanReq misses 130911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 86839 # number of ReadCleanReq misses 131011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 268407 # number of ReadSharedReq misses 131111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 268407 # number of ReadSharedReq misses 131211860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_misses::cpu.data 501154 # number of InvalidateReq misses 131311860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_misses::total 501154 # number of InvalidateReq misses 131411860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.dtb.walker 3956 # number of demand (read+write) misses 131511860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.itb.walker 3665 # number of demand (read+write) misses 131611860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 86839 # number of demand (read+write) misses 131711860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 746760 # number of demand (read+write) misses 131811860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 841220 # number of demand (read+write) misses 131911860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.dtb.walker 3956 # number of overall misses 132011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.itb.walker 3665 # number of overall misses 132111860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 86839 # number of overall misses 132211860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 746760 # number of overall misses 132311860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 841220 # number of overall misses 132411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 431772500 # number of ReadReq miss cycles 132511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 382599000 # number of ReadReq miss cycles 132611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 814371500 # number of ReadReq miss cycles 132711860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 72848000 # number of UpgradeReq miss cycles 132811860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::total 72848000 # number of UpgradeReq miss cycles 132911754Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162500 # number of SCUpgradeReq miss cycles 133011754Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::total 162500 # number of SCUpgradeReq miss cycles 133111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 49637800000 # number of ReadExReq miss cycles 133211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 49637800000 # number of ReadExReq miss cycles 133311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 9658072000 # number of ReadCleanReq miss cycles 133411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 9658072000 # number of ReadCleanReq miss cycles 133511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30942623000 # number of ReadSharedReq miss cycles 133611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 30942623000 # number of ReadSharedReq miss cycles 133711860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 431772500 # number of demand (read+write) miss cycles 133811860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.itb.walker 382599000 # number of demand (read+write) miss cycles 133911860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 9658072000 # number of demand (read+write) miss cycles 134011860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 80580423000 # number of demand (read+write) miss cycles 134111860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 91052866500 # number of demand (read+write) miss cycles 134211860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 431772500 # number of overall miss cycles 134311860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.itb.walker 382599000 # number of overall miss cycles 134411860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 9658072000 # number of overall miss cycles 134511860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 80580423000 # number of overall miss cycles 134611860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 91052866500 # number of overall miss cycles 134711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 800575 # number of ReadReq accesses(hits+misses) 134811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 286765 # number of ReadReq accesses(hits+misses) 134911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 1087340 # number of ReadReq accesses(hits+misses) 135011860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 7764980 # number of WritebackDirty accesses(hits+misses) 135111860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 7764980 # number of WritebackDirty accesses(hits+misses) 135211860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 15302294 # number of WritebackClean accesses(hits+misses) 135311860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 15302294 # number of WritebackClean accesses(hits+misses) 135411860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 29911 # number of UpgradeReq accesses(hits+misses) 135511860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 29911 # number of UpgradeReq accesses(hits+misses) 135611860Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 9 # number of SCUpgradeReq accesses(hits+misses) 135711860Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::total 9 # number of SCUpgradeReq accesses(hits+misses) 135811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 2069369 # number of ReadExReq accesses(hits+misses) 135911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 2069369 # number of ReadExReq accesses(hits+misses) 136011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15305492 # number of ReadCleanReq accesses(hits+misses) 136111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 15305492 # number of ReadCleanReq accesses(hits+misses) 136211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6798509 # number of ReadSharedReq accesses(hits+misses) 136311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 6798509 # number of ReadSharedReq accesses(hits+misses) 136411860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_accesses::cpu.data 1230045 # number of InvalidateReq accesses(hits+misses) 136511860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_accesses::total 1230045 # number of InvalidateReq accesses(hits+misses) 136611860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.dtb.walker 800575 # number of demand (read+write) accesses 136711860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.itb.walker 286765 # number of demand (read+write) accesses 136811860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 15305492 # number of demand (read+write) accesses 136911860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 8867878 # number of demand (read+write) accesses 137011860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 25260710 # number of demand (read+write) accesses 137111860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.dtb.walker 800575 # number of overall (read+write) accesses 137211860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.itb.walker 286765 # number of overall (read+write) accesses 137311860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 15305492 # number of overall (read+write) accesses 137411860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 8867878 # number of overall (read+write) accesses 137511860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 25260710 # number of overall (read+write) accesses 137611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.004941 # miss rate for ReadReq accesses 137711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.012780 # miss rate for ReadReq accesses 137811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.007009 # miss rate for ReadReq accesses 137911860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.136873 # miss rate for UpgradeReq accesses 138011860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.136873 # miss rate for UpgradeReq accesses 138111860Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.333333 # miss rate for SCUpgradeReq accesses 138211860Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.333333 # miss rate for SCUpgradeReq accesses 138311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.231159 # miss rate for ReadExReq accesses 138411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.231159 # miss rate for ReadExReq accesses 138511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005674 # miss rate for ReadCleanReq accesses 138611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005674 # miss rate for ReadCleanReq accesses 138711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.039480 # miss rate for ReadSharedReq accesses 138811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.039480 # miss rate for ReadSharedReq accesses 138911860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.407427 # miss rate for InvalidateReq accesses 139011860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_miss_rate::total 0.407427 # miss rate for InvalidateReq accesses 139111860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.004941 # miss rate for demand accesses 139211860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.012780 # miss rate for demand accesses 139311860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.005674 # miss rate for demand accesses 139411860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.084210 # miss rate for demand accesses 139511860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.033302 # miss rate for demand accesses 139611860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.004941 # miss rate for overall accesses 139711860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.012780 # miss rate for overall accesses 139811860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.005674 # miss rate for overall accesses 139911860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.084210 # miss rate for overall accesses 140011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.033302 # miss rate for overall accesses 140111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 109143.705763 # average ReadReq miss latency 140211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 104392.633015 # average ReadReq miss latency 140311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 106858.876788 # average ReadReq miss latency 140411860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 17793.844651 # average UpgradeReq miss latency 140511860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 17793.844651 # average UpgradeReq miss latency 140611754Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 54166.666667 # average SCUpgradeReq miss latency 140711754Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 54166.666667 # average SCUpgradeReq miss latency 140811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 103768.137756 # average ReadExReq miss latency 140911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 103768.137756 # average ReadExReq miss latency 141011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 111218.139315 # average ReadCleanReq miss latency 141111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 111218.139315 # average ReadCleanReq miss latency 141211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 115282.474004 # average ReadSharedReq miss latency 141311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 115282.474004 # average ReadSharedReq miss latency 141411860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 109143.705763 # average overall miss latency 141511860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 104392.633015 # average overall miss latency 141611860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 111218.139315 # average overall miss latency 141711860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 107906.721035 # average overall miss latency 141811860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 108239.065286 # average overall miss latency 141911860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 109143.705763 # average overall miss latency 142011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 104392.633015 # average overall miss latency 142111860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 111218.139315 # average overall miss latency 142211860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 107906.721035 # average overall miss latency 142311860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 108239.065286 # average overall miss latency 142410585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 142510585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 142610585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 142710585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 142810585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 142910585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 143011860Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 1059086 # number of writebacks 143111860Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 1059086 # number of writebacks 143211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.itb.walker 1 # number of ReadReq MSHR hits 143311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 143411353Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits 143511353Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits 143611860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.itb.walker 1 # number of demand (read+write) MSHR hits 143711353Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits 143811860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits 143911860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.itb.walker 1 # number of overall MSHR hits 144011353Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits 144111860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 22 # number of overall MSHR hits 144211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3956 # number of ReadReq MSHR misses 144311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3664 # number of ReadReq MSHR misses 144411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 7620 # number of ReadReq MSHR misses 144511754Sandreas.hansson@arm.comsystem.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses 144611754Sandreas.hansson@arm.comsystem.cpu.l2cache.CleanEvict_mshr_misses::total 2 # number of CleanEvict MSHR misses 144711860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4094 # number of UpgradeReq MSHR misses 144811860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 4094 # number of UpgradeReq MSHR misses 144911754Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses 145011754Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses 145111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 478353 # number of ReadExReq MSHR misses 145211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 478353 # number of ReadExReq MSHR misses 145311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 86839 # number of ReadCleanReq MSHR misses 145411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 86839 # number of ReadCleanReq MSHR misses 145511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 268386 # number of ReadSharedReq MSHR misses 145611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 268386 # 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number of overall MSHR misses 146511860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3664 # number of overall MSHR misses 146611860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 86839 # number of overall MSHR misses 146711860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 746739 # number of overall MSHR misses 146811860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 841198 # number of overall MSHR misses 146911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 2094 # number of ReadReq MSHR uncacheable 147011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33590 # number of ReadReq MSHR uncacheable 147111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::total 35684 # number of ReadReq MSHR uncacheable 147211860Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33609 # number of WriteReq MSHR uncacheable 147311860Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable::total 33609 # number of WriteReq MSHR uncacheable 147411860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 2094 # number of overall MSHR uncacheable misses 147511860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67199 # number of overall MSHR uncacheable misses 147611860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::total 69293 # number of overall MSHR uncacheable misses 147711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 392212500 # number of ReadReq MSHR miss cycles 147811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 345880000 # number of ReadReq MSHR miss cycles 147911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 738092500 # number of ReadReq MSHR miss cycles 148011860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 78102500 # number of UpgradeReq MSHR miss cycles 148111860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 78102500 # number of UpgradeReq MSHR miss cycles 148211754Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 163000 # number of SCUpgradeReq MSHR miss cycles 148311754Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 163000 # number of SCUpgradeReq MSHR miss cycles 148411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 44854250540 # number of ReadExReq MSHR miss cycles 148511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 44854250540 # number of ReadExReq MSHR miss cycles 148611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8789667055 # number of ReadCleanReq MSHR miss cycles 148711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8789667055 # number of ReadCleanReq MSHR miss cycles 148811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28257377566 # number of ReadSharedReq MSHR miss cycles 148911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28257377566 # number of ReadSharedReq MSHR miss cycles 149011860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 10480376502 # number of InvalidateReq MSHR miss cycles 149111860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 10480376502 # number of InvalidateReq MSHR miss cycles 149211860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 392212500 # number of demand (read+write) MSHR miss cycles 149311860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 345880000 # number of demand (read+write) MSHR miss cycles 149411860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8789667055 # number of demand (read+write) MSHR miss cycles 149511860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 73111628106 # number of demand (read+write) MSHR miss cycles 149611860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 82639387661 # number of demand (read+write) MSHR miss cycles 149711860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 392212500 # number of overall MSHR miss cycles 149811860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 345880000 # number of overall MSHR miss cycles 149911860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8789667055 # number of overall MSHR miss cycles 150011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 73111628106 # number of overall MSHR miss cycles 150111860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 82639387661 # number of overall MSHR miss cycles 150211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 147896500 # number of ReadReq MSHR uncacheable cycles 150311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5784421000 # number of ReadReq MSHR uncacheable cycles 150411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5932317500 # number of ReadReq MSHR uncacheable cycles 150511860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 147896500 # number of overall MSHR uncacheable cycles 150611860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5784421000 # number of overall MSHR uncacheable cycles 150711860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::total 5932317500 # number of overall MSHR uncacheable cycles 150811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004941 # mshr miss rate for ReadReq accesses 150911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.012777 # mshr miss rate for ReadReq accesses 151011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.007008 # mshr miss rate for ReadReq accesses 151110892Sandreas.hansson@arm.comsystem.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 151210892Sandreas.hansson@arm.comsystem.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 151311860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.136873 # mshr miss rate for UpgradeReq accesses 151411860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.136873 # mshr miss rate for UpgradeReq accesses 151511860Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SCUpgradeReq accesses 151611860Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SCUpgradeReq accesses 151711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.231159 # mshr miss rate for ReadExReq accesses 151811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.231159 # mshr miss rate for ReadExReq accesses 151911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005674 # mshr miss rate for ReadCleanReq accesses 152011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005674 # mshr miss rate for ReadCleanReq accesses 152111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.039477 # mshr miss rate for ReadSharedReq accesses 152211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.039477 # mshr miss rate for ReadSharedReq accesses 152311860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.407427 # mshr miss rate for InvalidateReq accesses 152411860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.407427 # mshr miss rate for InvalidateReq accesses 152511860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004941 # mshr miss rate for demand accesses 152611860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.012777 # mshr miss rate for demand accesses 152711860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005674 # mshr miss rate for demand accesses 152811860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.084207 # mshr miss rate for demand accesses 152911860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.033301 # mshr miss rate for demand accesses 153011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004941 # mshr miss rate for overall accesses 153111860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.012777 # mshr miss rate for overall accesses 153211860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005674 # mshr miss rate for overall accesses 153311860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.084207 # mshr miss rate for overall accesses 153411860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.033301 # mshr miss rate for overall accesses 153511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 99143.705763 # average ReadReq mshr miss latency 153611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 94399.563319 # average ReadReq mshr miss latency 153711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 96862.532808 # average ReadReq mshr miss latency 153811860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19077.308256 # average UpgradeReq mshr miss latency 153911860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19077.308256 # average UpgradeReq mshr miss latency 154011754Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 54333.333333 # average SCUpgradeReq mshr miss latency 154111754Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 54333.333333 # average SCUpgradeReq mshr miss latency 154211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93768.097075 # average ReadExReq mshr miss latency 154311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93768.097075 # average ReadExReq mshr miss latency 154411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 101217.967215 # average ReadCleanReq mshr miss latency 154511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 101217.967215 # average ReadCleanReq mshr miss latency 154611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 105286.332245 # average ReadSharedReq mshr miss latency 154711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 105286.332245 # average ReadSharedReq mshr miss latency 154811860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20912.486984 # average InvalidateReq mshr miss latency 154911860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20912.486984 # average InvalidateReq mshr miss latency 155011860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 99143.705763 # average overall mshr miss latency 155111860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 94399.563319 # average overall mshr miss latency 155211860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 101217.967215 # average overall mshr miss latency 155311860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 97907.874245 # average overall mshr miss latency 155411860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 98240.114291 # average overall mshr miss latency 155511860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 99143.705763 # average overall mshr miss latency 155611860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 94399.563319 # average overall mshr miss latency 155711860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 101217.967215 # average overall mshr miss latency 155811860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 97907.874245 # average overall mshr miss latency 155911860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 98240.114291 # average overall mshr miss latency 156011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 70628.701051 # average ReadReq mshr uncacheable latency 156111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172206.638881 # average ReadReq mshr uncacheable latency 156211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 166245.866495 # average ReadReq mshr uncacheable latency 156311860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 70628.701051 # average overall mshr uncacheable latency 156411860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86078.974389 # average overall mshr uncacheable latency 156511860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 85612.074813 # average overall mshr uncacheable latency 156611860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 51553426 # Total number of requests made to the snoop filter. 156711860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 26149596 # Number of requests hitting in the snoop filter with a single holder of the requested data. 156811860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 7713 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 156911860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 1993 # Total number of snoops made to the snoop filter. 157011860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 1993 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 157111138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 157211860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 157311860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 1662998 # Transaction distribution 157411860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 23767979 # Transaction distribution 157511860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteReq 33609 # Transaction distribution 157611860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteResp 33609 # Transaction distribution 157711860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 8824066 # Transaction distribution 157811860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 15304958 # Transaction distribution 157911860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 2522010 # Transaction distribution 158011860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 29914 # Transaction distribution 158111860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::SCUpgradeReq 9 # Transaction distribution 158211860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 29923 # Transaction distribution 158311860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 2069369 # Transaction distribution 158411860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 2069369 # Transaction distribution 158511860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 15305703 # Transaction distribution 158611860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 6801111 # Transaction distribution 158711860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::InvalidateReq 1260813 # Transaction distribution 158811860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::InvalidateResp 1230062 # Transaction distribution 158911860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45920340 # Packet count per connected master and slave (bytes) 159011860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 30488261 # Packet count per connected master and slave (bytes) 159111860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 721887 # Packet count per connected master and slave (bytes) 159211860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1992767 # Packet count per connected master and slave (bytes) 159311860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 79123255 # Packet count per connected master and slave (bytes) 159411860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1959102240 # Cumulative packet size per connected master and slave (bytes) 159511860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1064742138 # Cumulative packet size per connected master and slave (bytes) 159611860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2294120 # Cumulative packet size per connected master and slave (bytes) 159711860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6404600 # Cumulative packet size per connected master and slave (bytes) 159811860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 3032543098 # Cumulative packet size per connected master and slave (bytes) 159911860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 1823037 # Total snoops (count) 160011860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopTraffic 72164080 # Total snoop traffic (bytes) 160111860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 28412224 # Request fanout histogram 160211860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.025596 # Request fanout histogram 160311860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.157926 # Request fanout histogram 160410585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 160511860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 27684996 97.44% 97.44% # Request fanout histogram 160611860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 727226 2.56% 100.00% # Request fanout histogram 160711860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 2 0.00% 100.00% # Request fanout histogram 160810585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 160911138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 161011860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 161111860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 28412224 # Request fanout histogram 161211860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 49353009980 # Layer occupancy (ticks) 161310585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 161411860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.occupancy 1469889 # Layer occupancy (ticks) 161510585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 161611860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 22969214259 # Layer occupancy (ticks) 161710585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 161811860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 13985386089 # Layer occupancy (ticks) 161910585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 162011860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer2.occupancy 435462274 # Layer occupancy (ticks) 162110585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 162211860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer3.occupancy 1192643074 # Layer occupancy (ticks) 162310585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 162411860Sandreas.hansson@arm.comsystem.iobus.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 162511860Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 40205 # Transaction distribution 162611860Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 40205 # Transaction distribution 162711860Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 136485 # Transaction distribution 162811860Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 136485 # Transaction distribution 162911860Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47478 # Packet count per connected master and slave (bytes) 163010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 163111245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 163210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 163310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 163410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 163510585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 163610585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 163710585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 163810585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 163910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 164010892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 164110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 164211860Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122360 # Packet count per connected master and slave (bytes) 164311860Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230940 # Packet count per connected master and slave (bytes) 164411860Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 230940 # Packet count per connected master and slave (bytes) 164510585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 164610585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 164711860Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 353380 # Packet count per connected master and slave (bytes) 164811860Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47498 # Cumulative packet size per connected master and slave (bytes) 164910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 165011245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 165110585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 165210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 165310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 165410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 165510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 165610585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 165710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 165810585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 165910892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 166010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 166111860Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 155490 # Cumulative packet size per connected master and slave (bytes) 166211860Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334192 # Cumulative packet size per connected master and slave (bytes) 166311860Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7334192 # Cumulative packet size per connected master and slave (bytes) 166410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 166510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 166611860Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 7491768 # Cumulative packet size per connected master and slave (bytes) 166711860Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 41589500 # Layer occupancy (ticks) 166810585Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 166911754Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) 167010585Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 167111860Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 341500 # Layer occupancy (ticks) 167210585Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 167311860Sandreas.hansson@arm.comsystem.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) 167410585Sandreas.hansson@arm.comsystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 167511860Sandreas.hansson@arm.comsystem.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks) 167611245Sandreas.sandberg@arm.comsystem.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 167711201Sandreas.hansson@arm.comsystem.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) 167810585Sandreas.hansson@arm.comsystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 167911606Sandreas.sandberg@arm.comsystem.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) 168010585Sandreas.hansson@arm.comsystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 168111201Sandreas.hansson@arm.comsystem.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) 168210585Sandreas.hansson@arm.comsystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 168311201Sandreas.hansson@arm.comsystem.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) 168410585Sandreas.hansson@arm.comsystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 168511680SCurtis.Dunham@arm.comsystem.iobus.reqLayer16.occupancy 14500 # Layer occupancy (ticks) 168610585Sandreas.hansson@arm.comsystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 168711860Sandreas.hansson@arm.comsystem.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) 168810585Sandreas.hansson@arm.comsystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 168911860Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 25178000 # Layer occupancy (ticks) 169010585Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 169111860Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 36502000 # Layer occupancy (ticks) 169210585Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 169311860Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 568968268 # Layer occupancy (ticks) 169410585Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 169511860Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 92542000 # Layer occupancy (ticks) 169610585Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 169711860Sandreas.hansson@arm.comsystem.iobus.respLayer3.occupancy 147700000 # Layer occupancy (ticks) 169810585Sandreas.hansson@arm.comsystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 169910892Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 170010585Sandreas.hansson@arm.comsystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 170111860Sandreas.hansson@arm.comsystem.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 170211860Sandreas.hansson@arm.comsystem.iocache.tags.replacements 115451 # number of replacements 170311860Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 10.420620 # Cycle average of tags in use 170410585Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 170511860Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 115467 # Sample count of references to valid blocks. 170610585Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 170711860Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 13090295539000 # Cycle when the warmup percentage was hit. 170811860Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 3.547144 # Average occupied blocks per requestor 170911860Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 6.873475 # Average occupied blocks per requestor 171011860Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.221697 # Average percentage of cache occupancy 171111860Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.429592 # Average percentage of cache occupancy 171211860Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.651289 # Average percentage of cache occupancy 171310585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 171410585Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 171510585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 171611860Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 1039587 # Number of tag accesses 171711860Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 1039587 # Number of data accesses 171811860Sandreas.hansson@arm.comsystem.iocache.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 171910585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 172011860Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ide 8806 # number of ReadReq misses 172111860Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 8843 # number of ReadReq misses 172210585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 172310585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 172410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 172510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 172610585Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 172711860Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ide 115470 # number of demand (read+write) misses 172811860Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 115510 # number of demand (read+write) misses 172910585Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 173011860Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ide 115470 # number of overall misses 173111860Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 115510 # number of overall misses 173211860Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles 173311860Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ide 1876442585 # number of ReadReq miss cycles 173411860Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 1881528585 # number of ReadReq miss cycles 173510892Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 173610892Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles 173711860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::realview.ide 13387619683 # number of WriteLineReq miss cycles 173811860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::total 13387619683 # number of WriteLineReq miss cycles 173911860Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles 174011860Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ide 15264062268 # number of demand (read+write) miss cycles 174111860Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 15269499268 # number of demand (read+write) miss cycles 174211860Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles 174311860Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ide 15264062268 # number of overall miss cycles 174411860Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 15269499268 # number of overall miss cycles 174510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 174611860Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8806 # number of ReadReq accesses(hits+misses) 174711860Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 8843 # number of ReadReq accesses(hits+misses) 174810585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 174910585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 175010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 175110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 175210585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 175311860Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ide 115470 # number of demand (read+write) accesses 175411860Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 115510 # number of demand (read+write) accesses 175510585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 175611860Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 115470 # number of overall (read+write) accesses 175711860Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 115510 # number of overall (read+write) accesses 175810585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 175910585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 176010585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 176110585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 176210585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 176310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 176410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 176510585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 176610585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 176710585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 176810585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 176910585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 177010585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 177111860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency 177211860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 213086.825460 # average ReadReq miss latency 177311860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 212770.392966 # average ReadReq miss latency 177410892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 177510892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency 177611860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::realview.ide 125512.072330 # average WriteLineReq miss latency 177711860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 125512.072330 # average WriteLineReq miss latency 177811860Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency 177911860Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ide 132190.718524 # average overall miss latency 178011860Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 132192.011670 # average overall miss latency 178111860Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency 178211860Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ide 132190.718524 # average overall miss latency 178311860Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 132192.011670 # average overall miss latency 178411860Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 45104 # number of cycles access was blocked 178510585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 178611860Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 3423 # number of cycles access was blocked 178710585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 178811860Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 13.176746 # average number of cycles each access was blocked 178910585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 179010726Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 106630 # number of writebacks 179110726Sandreas.hansson@arm.comsystem.iocache.writebacks::total 106630 # number of writebacks 179210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 179311860Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8806 # number of ReadReq MSHR misses 179411860Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::total 8843 # number of ReadReq MSHR misses 179510585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 179610585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 179710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 179810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 179910585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 180011860Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ide 115470 # number of demand (read+write) MSHR misses 180111860Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::total 115510 # number of demand (read+write) MSHR misses 180210585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 180311860Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ide 115470 # number of overall MSHR misses 180411860Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::total 115510 # number of overall MSHR misses 180511860Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles 180611860Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1436142585 # number of ReadReq MSHR miss cycles 180711860Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 1439378585 # number of ReadReq MSHR miss cycles 180810892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 180910892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 181011860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8048941203 # number of WriteLineReq MSHR miss cycles 181111860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 8048941203 # number of WriteLineReq MSHR miss cycles 181211860Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles 181311860Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ide 9485083788 # number of demand (read+write) MSHR miss cycles 181411860Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 9488520788 # number of demand (read+write) MSHR miss cycles 181511860Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles 181611860Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ide 9485083788 # number of overall MSHR miss cycles 181711860Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 9488520788 # number of overall MSHR miss cycles 181810585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 181910585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 182010585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 182110585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 182210585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 182310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 182410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 182510585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 182610585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 182710585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 182810585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 182910585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 183010585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 183111860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency 183211860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 163086.825460 # average ReadReq mshr miss latency 183311860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 162770.392966 # average ReadReq mshr miss latency 183410892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 183510892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 183611860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75460.710296 # average WriteLineReq mshr miss latency 183711860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 75460.710296 # average WriteLineReq mshr miss latency 183811860Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency 183911860Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 82143.273474 # average overall mshr miss latency 184011860Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 82144.583049 # average overall mshr miss latency 184111860Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency 184211860Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 82143.273474 # average overall mshr miss latency 184311860Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 82144.583049 # average overall mshr miss latency 184411860Sandreas.hansson@arm.comsystem.membus.snoop_filter.tot_requests 2825507 # Total number of requests made to the snoop filter. 184511860Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_single_requests 1398744 # Number of requests hitting in the snoop filter with a single holder of the requested data. 184611860Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_multi_requests 3574 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 184711606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 184811606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 184911606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 185011860Sandreas.hansson@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 185111860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 35684 # Transaction distribution 185211860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 407371 # Transaction distribution 185311860Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 33609 # Transaction distribution 185411860Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 33609 # Transaction distribution 185511860Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty 1165716 # Transaction distribution 185611860Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 197310 # Transaction distribution 185711860Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 4655 # Transaction distribution 185811754Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution 185911336Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 8 # Transaction distribution 186011860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 477795 # Transaction distribution 186111860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 477795 # Transaction distribution 186211860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 371688 # Transaction distribution 186311860Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 607818 # Transaction distribution 186411860Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 30461 # Transaction distribution 186511860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122360 # Packet count per connected master and slave (bytes) 186611201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) 186711860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6852 # Packet count per connected master and slave (bytes) 186811860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3443320 # Packet count per connected master and slave (bytes) 186911860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 3572590 # Packet count per connected master and slave (bytes) 187011860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237411 # Packet count per connected master and slave (bytes) 187111860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 237411 # Packet count per connected master and slave (bytes) 187211860Sandreas.hansson@arm.comsystem.membus.pkt_count::total 3810001 # Packet count per connected master and slave (bytes) 187311860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155490 # Cumulative packet size per connected master and slave (bytes) 187411201Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes) 187511860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13704 # Cumulative packet size per connected master and slave (bytes) 187611860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 121594060 # Cumulative packet size per connected master and slave (bytes) 187711860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 121763674 # Cumulative packet size per connected master and slave (bytes) 187811860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7237120 # Cumulative packet size per connected master and slave (bytes) 187911860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7237120 # Cumulative packet size per connected master and slave (bytes) 188011860Sandreas.hansson@arm.comsystem.membus.pkt_size::total 129000794 # Cumulative packet size per connected master and slave (bytes) 188111860Sandreas.hansson@arm.comsystem.membus.snoops 33521 # Total snoops (count) 188211860Sandreas.hansson@arm.comsystem.membus.snoopTraffic 195328 # Total snoop traffic (bytes) 188311860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 1531252 # Request fanout histogram 188411860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0.022242 # Request fanout histogram 188511860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0.147469 # Request fanout histogram 188610515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 188711860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 1497194 97.78% 97.78% # Request fanout histogram 188811860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 34058 2.22% 100.00% # Request fanout histogram 188910515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 189010515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 189111606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 189210515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 189311860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 1531252 # Request fanout histogram 189411860Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 103704000 # Layer occupancy (ticks) 189510515SAli.Saidi@ARM.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 189611441Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 32500 # Layer occupancy (ticks) 189710515SAli.Saidi@ARM.comsystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 189811860Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 5582500 # Layer occupancy (ticks) 189910515SAli.Saidi@ARM.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 190011860Sandreas.hansson@arm.comsystem.membus.reqLayer5.occupancy 7711716413 # Layer occupancy (ticks) 190110585Sandreas.hansson@arm.comsystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 190211860Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 4552014688 # Layer occupancy (ticks) 190310515SAli.Saidi@ARM.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 190411860Sandreas.hansson@arm.comsystem.membus.respLayer3.occupancy 76660254 # Layer occupancy (ticks) 190510515SAli.Saidi@ARM.comsystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 190611860Sandreas.hansson@arm.comsystem.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 190711860Sandreas.hansson@arm.comsystem.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 190811860Sandreas.hansson@arm.comsystem.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 190911860Sandreas.hansson@arm.comsystem.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 191011860Sandreas.hansson@arm.comsystem.realview.gic.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 191111860Sandreas.hansson@arm.comsystem.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 191211860Sandreas.hansson@arm.comsystem.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 191311239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 191411239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 191511239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 191611239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 191711239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 191811239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 191911860Sandreas.hansson@arm.comsystem.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 192011860Sandreas.hansson@arm.comsystem.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 192110515SAli.Saidi@ARM.comsystem.realview.ethernet.txBytes 966 # Bytes Transmitted 192210515SAli.Saidi@ARM.comsystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 192310515SAli.Saidi@ARM.comsystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 192410515SAli.Saidi@ARM.comsystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 192510515SAli.Saidi@ARM.comsystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 192610515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 192710515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 192810515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 192910515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 193011860Sandreas.hansson@arm.comsystem.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) 193110515SAli.Saidi@ARM.comsystem.realview.ethernet.totPackets 3 # Total Packets 193210515SAli.Saidi@ARM.comsystem.realview.ethernet.totBytes 966 # Total Bytes 193310515SAli.Saidi@ARM.comsystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 193411860Sandreas.hansson@arm.comsystem.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) 193510515SAli.Saidi@ARM.comsystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 193610515SAli.Saidi@ARM.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 193710515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 193810515SAli.Saidi@ARM.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 193910515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 194010515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 194110515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 194210515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 194310515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 194410515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 194510515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 194610515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 194710515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 194810515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 194910515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 195010515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 195110515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 195210515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 195310515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 195410515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 195510515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 195610515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 195710515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 195810515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 195910515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 196010515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 196110515SAli.Saidi@ARM.comsystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 196210515SAli.Saidi@ARM.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 196311860Sandreas.hansson@arm.comsystem.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 196411860Sandreas.hansson@arm.comsystem.realview.ide.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 196511860Sandreas.hansson@arm.comsystem.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 196611860Sandreas.hansson@arm.comsystem.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 196711860Sandreas.hansson@arm.comsystem.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 196811860Sandreas.hansson@arm.comsystem.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 196911860Sandreas.hansson@arm.comsystem.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 197011239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 197111239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 197211239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 197311239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 197411860Sandreas.hansson@arm.comsystem.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 197511860Sandreas.hansson@arm.comsystem.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 197611860Sandreas.hansson@arm.comsystem.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 197711860Sandreas.hansson@arm.comsystem.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 197811860Sandreas.hansson@arm.comsystem.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 197911860Sandreas.hansson@arm.comsystem.realview.uart.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 198011860Sandreas.hansson@arm.comsystem.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 198111860Sandreas.hansson@arm.comsystem.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 198211860Sandreas.hansson@arm.comsystem.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 198311860Sandreas.hansson@arm.comsystem.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 198411860Sandreas.hansson@arm.comsystem.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 198511860Sandreas.hansson@arm.comsystem.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states 198610515SAli.Saidi@ARM.comsystem.cpu.kern.inst.arm 0 # number of arm instructions executed 198711860Sandreas.hansson@arm.comsystem.cpu.kern.inst.quiesce 16273 # number of quiesce instructions executed 198810515SAli.Saidi@ARM.com 198910515SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 1990