stats.txt revision 11589:af2f7fef4875
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.384351 # Number of seconds simulated 4sim_ticks 47384351300000 # Number of ticks simulated 5final_tick 47384351300000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 183431 # Simulator instruction rate (inst/s) 8host_op_rate 207694 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 7126665146 # Simulator tick rate (ticks/s) 10host_mem_usage 777076 # Number of bytes of host memory used 11host_seconds 6648.88 # Real time elapsed on the host 12sim_insts 1219610005 # Number of instructions simulated 13sim_ops 1380933056 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 205248 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 202880 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 4270112 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 16788488 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 21729728 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 123968 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.itb.walker 83584 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.inst 3109600 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.data 10061712 # Number of bytes read from this memory 26system.physmem.bytes_read::cpu1.l2cache.prefetcher 12393536 # Number of bytes read from this memory 27system.physmem.bytes_read::realview.ide 438400 # Number of bytes read from this memory 28system.physmem.bytes_read::total 69407256 # Number of bytes read from this memory 29system.physmem.bytes_inst_read::cpu0.inst 4270112 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::cpu1.inst 3109600 # Number of instructions bytes read from this memory 31system.physmem.bytes_inst_read::total 7379712 # Number of instructions bytes read from this memory 32system.physmem.bytes_written::writebacks 85545984 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 34system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 35system.physmem.bytes_written::total 85566568 # Number of bytes written to this memory 36system.physmem.num_reads::cpu0.dtb.walker 3207 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.itb.walker 3170 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.inst 82673 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.data 262333 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu0.l2cache.prefetcher 339527 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.dtb.walker 1937 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.itb.walker 1306 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.inst 48631 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.data 157227 # Number of read requests responded to by this memory 45system.physmem.num_reads::cpu1.l2cache.prefetcher 193649 # Number of read requests responded to by this memory 46system.physmem.num_reads::realview.ide 6850 # Number of read requests responded to by this memory 47system.physmem.num_reads::total 1100510 # Number of read requests responded to by this memory 48system.physmem.num_writes::writebacks 1336656 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 50system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 51system.physmem.num_writes::total 1339230 # Number of write requests responded to by this memory 52system.physmem.bw_read::cpu0.dtb.walker 4332 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.itb.walker 4282 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.inst 90117 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.data 354304 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu0.l2cache.prefetcher 458584 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.dtb.walker 2616 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.itb.walker 1764 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.inst 65625 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.data 212343 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::cpu1.l2cache.prefetcher 261553 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::realview.ide 9252 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_read::total 1464772 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu0.inst 90117 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::cpu1.inst 65625 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_inst_read::total 155742 # Instruction read bandwidth from this memory (bytes/s) 67system.physmem.bw_write::writebacks 1805364 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_write::total 1805798 # Write bandwidth from this memory (bytes/s) 71system.physmem.bw_total::writebacks 1805364 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.dtb.walker 4332 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.itb.walker 4282 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.inst 90117 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.data 354739 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu0.l2cache.prefetcher 458584 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.dtb.walker 2616 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.itb.walker 1764 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.inst 65625 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.data 212343 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::cpu1.l2cache.prefetcher 261553 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::realview.ide 9252 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::total 3270570 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.readReqs 1100510 # Number of read requests accepted 85system.physmem.writeReqs 1339230 # Number of write requests accepted 86system.physmem.readBursts 1100510 # Number of DRAM read bursts, including those serviced by the write queue 87system.physmem.writeBursts 1339230 # Number of DRAM write bursts, including those merged in the write queue 88system.physmem.bytesReadDRAM 70408640 # Total number of bytes read from DRAM 89system.physmem.bytesReadWrQ 24000 # Total number of bytes read from write queue 90system.physmem.bytesWritten 85564992 # Total number of bytes written to DRAM 91system.physmem.bytesReadSys 69407256 # Total read bytes from the system interface side 92system.physmem.bytesWrittenSys 85566568 # Total written bytes from the system interface side 93system.physmem.servicedByWrQ 375 # Number of DRAM read bursts serviced by the write queue 94system.physmem.mergedWrBursts 2249 # Number of DRAM write bursts merged with an existing one 95system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 96system.physmem.perBankRdBursts::0 70416 # Per bank write bursts 97system.physmem.perBankRdBursts::1 75191 # Per bank write bursts 98system.physmem.perBankRdBursts::2 64063 # Per bank write bursts 99system.physmem.perBankRdBursts::3 69912 # Per bank write bursts 100system.physmem.perBankRdBursts::4 59812 # Per bank write bursts 101system.physmem.perBankRdBursts::5 69643 # Per bank write bursts 102system.physmem.perBankRdBursts::6 65430 # Per bank write bursts 103system.physmem.perBankRdBursts::7 68144 # Per bank write bursts 104system.physmem.perBankRdBursts::8 61950 # Per bank write bursts 105system.physmem.perBankRdBursts::9 89644 # Per bank write bursts 106system.physmem.perBankRdBursts::10 68037 # Per bank write bursts 107system.physmem.perBankRdBursts::11 70586 # Per bank write bursts 108system.physmem.perBankRdBursts::12 61163 # Per bank write bursts 109system.physmem.perBankRdBursts::13 71056 # Per bank write bursts 110system.physmem.perBankRdBursts::14 65094 # Per bank write bursts 111system.physmem.perBankRdBursts::15 69994 # Per bank write bursts 112system.physmem.perBankWrBursts::0 85481 # Per bank write bursts 113system.physmem.perBankWrBursts::1 90029 # Per bank write bursts 114system.physmem.perBankWrBursts::2 81966 # Per bank write bursts 115system.physmem.perBankWrBursts::3 85433 # Per bank write bursts 116system.physmem.perBankWrBursts::4 77921 # Per bank write bursts 117system.physmem.perBankWrBursts::5 84076 # Per bank write bursts 118system.physmem.perBankWrBursts::6 83054 # Per bank write bursts 119system.physmem.perBankWrBursts::7 85039 # Per bank write bursts 120system.physmem.perBankWrBursts::8 78873 # Per bank write bursts 121system.physmem.perBankWrBursts::9 84297 # Per bank write bursts 122system.physmem.perBankWrBursts::10 83224 # Per bank write bursts 123system.physmem.perBankWrBursts::11 86586 # Per bank write bursts 124system.physmem.perBankWrBursts::12 79852 # Per bank write bursts 125system.physmem.perBankWrBursts::13 85124 # Per bank write bursts 126system.physmem.perBankWrBursts::14 80745 # Per bank write bursts 127system.physmem.perBankWrBursts::15 85253 # Per bank write bursts 128system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 129system.physmem.numWrRetry 51215 # Number of times write queue was full causing retry 130system.physmem.totGap 47384349786500 # Total gap between requests 131system.physmem.readPktSize::0 0 # Read request sizes (log2) 132system.physmem.readPktSize::1 0 # Read request sizes (log2) 133system.physmem.readPktSize::2 0 # Read request sizes (log2) 134system.physmem.readPktSize::3 25 # Read request sizes (log2) 135system.physmem.readPktSize::4 21333 # Read request sizes (log2) 136system.physmem.readPktSize::5 0 # Read request sizes (log2) 137system.physmem.readPktSize::6 1079152 # Read request sizes (log2) 138system.physmem.writePktSize::0 0 # Write request sizes (log2) 139system.physmem.writePktSize::1 0 # Write request sizes (log2) 140system.physmem.writePktSize::2 2 # Write request sizes (log2) 141system.physmem.writePktSize::3 2572 # Write request sizes (log2) 142system.physmem.writePktSize::4 0 # Write request sizes (log2) 143system.physmem.writePktSize::5 0 # Write request sizes (log2) 144system.physmem.writePktSize::6 1336656 # Write request sizes (log2) 145system.physmem.rdQLenPdf::0 480448 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::1 272774 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::2 88894 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::3 67384 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::4 42690 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::5 36411 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::6 33268 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::7 30721 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::8 27820 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::9 7595 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::10 4180 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::11 2606 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::12 1628 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::13 1243 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::14 684 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::15 590 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::16 501 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::17 390 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::18 173 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::19 105 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::20 17 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::21 8 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::22 4 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 176system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 177system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::15 24574 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::16 28512 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::17 38198 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::18 43791 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::19 48248 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::20 52275 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::21 57744 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::22 62191 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::23 67593 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::24 69901 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::25 75312 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::26 79272 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::27 77429 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::28 80341 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::29 90816 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::30 80863 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::31 73646 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::32 69003 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::33 5131 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::34 3743 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::35 2880 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::36 2292 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::37 1969 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::38 1733 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::39 1620 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::40 1427 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::41 1318 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::42 1452 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::43 1364 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::44 1312 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::45 1279 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::46 1419 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::47 1515 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::48 1588 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::49 1785 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::50 1829 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::51 1988 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::52 2100 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::53 2366 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::54 2471 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::55 2894 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::56 3089 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::57 3468 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::58 3580 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::59 3839 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::60 4719 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::61 6200 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::62 24545 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::63 120342 # What write queue length does an incoming req see 241system.physmem.bytesPerActivate::samples 1069816 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::mean 145.794462 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::gmean 98.799028 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::stdev 192.755385 # Bytes accessed per row activation 245system.physmem.bytesPerActivate::0-127 712470 66.60% 66.60% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::128-255 211048 19.73% 86.32% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::256-383 55044 5.15% 91.47% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::384-511 23596 2.21% 93.68% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::512-639 18557 1.73% 95.41% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::640-767 10547 0.99% 96.40% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::768-895 7452 0.70% 97.09% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::896-1023 5550 0.52% 97.61% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::1024-1151 25552 2.39% 100.00% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::total 1069816 # Bytes accessed per row activation 255system.physmem.rdPerTurnAround::samples 62458 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::mean 17.613853 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::stdev 71.325725 # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::0-511 62454 99.99% 99.99% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::512-1023 2 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes 262system.physmem.rdPerTurnAround::total 62458 # Reads before turning the bus around for writes 263system.physmem.wrPerTurnAround::samples 62458 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::mean 21.405633 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::gmean 17.660061 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::stdev 609.107080 # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::0-4095 62456 100.00% 100.00% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::45056-49151 1 0.00% 100.00% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::143360-147455 1 0.00% 100.00% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::total 62458 # Writes before turning the bus around for reads 271system.physmem.totQLat 48895390505 # Total ticks spent queuing 272system.physmem.totMemAccLat 69522921755 # Total ticks spent from burst creation until serviced by the DRAM 273system.physmem.totBusLat 5500675000 # Total ticks spent in databus transfers 274system.physmem.avgQLat 44444.90 # Average queueing delay per DRAM burst 275system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 276system.physmem.avgMemAccLat 63194.90 # Average memory access latency per DRAM burst 277system.physmem.avgRdBW 1.49 # Average DRAM read bandwidth in MiByte/s 278system.physmem.avgWrBW 1.81 # Average achieved write bandwidth in MiByte/s 279system.physmem.avgRdBWSys 1.46 # Average system read bandwidth in MiByte/s 280system.physmem.avgWrBWSys 1.81 # Average system write bandwidth in MiByte/s 281system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 282system.physmem.busUtil 0.03 # Data bus utilization in percentage 283system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 284system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 285system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing 286system.physmem.avgWrQLen 26.21 # Average write queue length when enqueuing 287system.physmem.readRowHits 830166 # Number of row buffer hits during reads 288system.physmem.writeRowHits 537104 # Number of row buffer hits during writes 289system.physmem.readRowHitRate 75.46 # Row buffer hit rate for reads 290system.physmem.writeRowHitRate 40.17 # Row buffer hit rate for writes 291system.physmem.avgGap 19421885.03 # Average gap between requests 292system.physmem.pageHitRate 56.10 # Row buffer hit rate, read and write combined 293system.physmem_0.actEnergy 4087639080 # Energy for activate commands per rank (pJ) 294system.physmem_0.preEnergy 2230358625 # Energy for precharge commands per rank (pJ) 295system.physmem_0.readEnergy 4232326800 # Energy for read commands per rank (pJ) 296system.physmem_0.writeEnergy 4361033520 # Energy for write commands per rank (pJ) 297system.physmem_0.refreshEnergy 3094915112640 # Energy for refresh commands per rank (pJ) 298system.physmem_0.actBackEnergy 1166279241240 # Energy for active background per rank (pJ) 299system.physmem_0.preBackEnergy 27407555547000 # Energy for precharge background per rank (pJ) 300system.physmem_0.totalEnergy 31683661258905 # Total energy per rank (pJ) 301system.physmem_0.averagePower 668.652499 # Core power per rank (mW) 302system.physmem_0.memoryStateTime::IDLE 45594888254330 # Time in different power states 303system.physmem_0.memoryStateTime::REF 1582267440000 # Time in different power states 304system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 305system.physmem_0.memoryStateTime::ACT 207195159170 # Time in different power states 306system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 307system.physmem_1.actEnergy 4000169880 # Energy for activate commands per rank (pJ) 308system.physmem_1.preEnergy 2182632375 # Energy for precharge commands per rank (pJ) 309system.physmem_1.readEnergy 4348679400 # Energy for read commands per rank (pJ) 310system.physmem_1.writeEnergy 4302421920 # Energy for write commands per rank (pJ) 311system.physmem_1.refreshEnergy 3094915112640 # Energy for refresh commands per rank (pJ) 312system.physmem_1.actBackEnergy 1168435080135 # Energy for active background per rank (pJ) 313system.physmem_1.preBackEnergy 27405664460250 # Energy for precharge background per rank (pJ) 314system.physmem_1.totalEnergy 31683848556600 # Total energy per rank (pJ) 315system.physmem_1.averagePower 668.656452 # Core power per rank (mW) 316system.physmem_1.memoryStateTime::IDLE 45591701065782 # Time in different power states 317system.physmem_1.memoryStateTime::REF 1582267440000 # Time in different power states 318system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 319system.physmem_1.memoryStateTime::ACT 210382633218 # Time in different power states 320system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 321system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 322system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory 323system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 324system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory 325system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 326system.realview.nvmem.bytes_read::total 556 # Number of bytes read from this memory 327system.realview.nvmem.bytes_inst_read::cpu0.inst 368 # Number of instructions bytes read from this memory 328system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory 329system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory 330system.realview.nvmem.num_reads::cpu0.inst 23 # Number of read requests responded to by this memory 331system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 332system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory 333system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 334system.realview.nvmem.num_reads::total 38 # Number of read requests responded to by this memory 335system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) 336system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 337system.realview.nvmem.bw_read::cpu1.inst 3 # Total read bandwidth from this memory (bytes/s) 338system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 339system.realview.nvmem.bw_read::total 12 # Total read bandwidth from this memory (bytes/s) 340system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) 341system.realview.nvmem.bw_inst_read::cpu1.inst 3 # Instruction read bandwidth from this memory (bytes/s) 342system.realview.nvmem.bw_inst_read::total 11 # Instruction read bandwidth from this memory (bytes/s) 343system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) 344system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 345system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s) 346system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 347system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s) 348system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 349system.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 350system.bridge.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 351system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 352system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 353system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 354system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 355system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 356system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 357system.cpu0.branchPred.lookups 199183431 # Number of BP lookups 358system.cpu0.branchPred.condPredicted 140489040 # Number of conditional branches predicted 359system.cpu0.branchPred.condIncorrect 7036065 # Number of conditional branches incorrect 360system.cpu0.branchPred.BTBLookups 156342542 # Number of BTB lookups 361system.cpu0.branchPred.BTBHits 99990575 # Number of BTB hits 362system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 363system.cpu0.branchPred.BTBHitPct 63.956089 # BTB Hit Percentage 364system.cpu0.branchPred.usedRAS 20013017 # Number of times the RAS was used to get a target. 365system.cpu0.branchPred.RASInCorrect 198399 # Number of incorrect RAS predictions. 366system.cpu0.branchPred.indirectLookups 4618183 # Number of indirect predictor lookups. 367system.cpu0.branchPred.indirectHits 2919648 # Number of indirect target hits. 368system.cpu0.branchPred.indirectMisses 1698535 # Number of indirect misses. 369system.cpu0.branchPredindirectMispredicted 412858 # Number of mispredicted indirect branches. 370system.cpu_clk_domain.clock 500 # Clock period in ticks 371system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 372system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 373system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 374system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 375system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 376system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 377system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 378system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 379system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 380system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 381system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 382system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 383system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 384system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 385system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 386system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 387system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 388system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 389system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 390system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 391system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 392system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 393system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 394system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 395system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 396system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 397system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 398system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 399system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 400system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 401system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 402system.cpu0.dtb.walker.walks 607513 # Table walker walks requested 403system.cpu0.dtb.walker.walksLong 607513 # Table walker walks initiated with long descriptors 404system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 13877 # Level at which table walker walks with long descriptors terminate 405system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 97395 # Level at which table walker walks with long descriptors terminate 406system.cpu0.dtb.walker.walksSquashedBefore 289192 # Table walks squashed before starting 407system.cpu0.dtb.walker.walkWaitTime::samples 318321 # Table walker wait (enqueue to first request) latency 408system.cpu0.dtb.walker.walkWaitTime::mean 2219.643065 # Table walker wait (enqueue to first request) latency 409system.cpu0.dtb.walker.walkWaitTime::stdev 12711.673990 # Table walker wait (enqueue to first request) latency 410system.cpu0.dtb.walker.walkWaitTime::0-65535 315923 99.25% 99.25% # Table walker wait (enqueue to first request) latency 411system.cpu0.dtb.walker.walkWaitTime::65536-131071 1786 0.56% 99.81% # Table walker wait (enqueue to first request) latency 412system.cpu0.dtb.walker.walkWaitTime::131072-196607 409 0.13% 99.94% # Table walker wait (enqueue to first request) latency 413system.cpu0.dtb.walker.walkWaitTime::196608-262143 127 0.04% 99.98% # Table walker wait (enqueue to first request) latency 414system.cpu0.dtb.walker.walkWaitTime::262144-327679 41 0.01% 99.99% # Table walker wait (enqueue to first request) latency 415system.cpu0.dtb.walker.walkWaitTime::327680-393215 31 0.01% 100.00% # Table walker wait (enqueue to first request) latency 416system.cpu0.dtb.walker.walkWaitTime::393216-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 417system.cpu0.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 418system.cpu0.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 419system.cpu0.dtb.walker.walkWaitTime::total 318321 # Table walker wait (enqueue to first request) latency 420system.cpu0.dtb.walker.walkCompletionTime::samples 324666 # Table walker service (enqueue to completion) latency 421system.cpu0.dtb.walker.walkCompletionTime::mean 20482.457356 # Table walker service (enqueue to completion) latency 422system.cpu0.dtb.walker.walkCompletionTime::gmean 17703.017560 # Table walker service (enqueue to completion) latency 423system.cpu0.dtb.walker.walkCompletionTime::stdev 16938.599592 # Table walker service (enqueue to completion) latency 424system.cpu0.dtb.walker.walkCompletionTime::0-65535 320665 98.77% 98.77% # Table walker service (enqueue to completion) latency 425system.cpu0.dtb.walker.walkCompletionTime::65536-131071 2783 0.86% 99.62% # Table walker service (enqueue to completion) latency 426system.cpu0.dtb.walker.walkCompletionTime::131072-196607 369 0.11% 99.74% # Table walker service (enqueue to completion) latency 427system.cpu0.dtb.walker.walkCompletionTime::196608-262143 625 0.19% 99.93% # Table walker service (enqueue to completion) latency 428system.cpu0.dtb.walker.walkCompletionTime::262144-327679 139 0.04% 99.97% # Table walker service (enqueue to completion) latency 429system.cpu0.dtb.walker.walkCompletionTime::327680-393215 57 0.02% 99.99% # Table walker service (enqueue to completion) latency 430system.cpu0.dtb.walker.walkCompletionTime::393216-458751 21 0.01% 100.00% # Table walker service (enqueue to completion) latency 431system.cpu0.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 432system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 433system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 434system.cpu0.dtb.walker.walkCompletionTime::total 324666 # Table walker service (enqueue to completion) latency 435system.cpu0.dtb.walker.walksPending::samples 513372677252 # Table walker pending requests distribution 436system.cpu0.dtb.walker.walksPending::mean 0.571567 # Table walker pending requests distribution 437system.cpu0.dtb.walker.walksPending::stdev 0.552695 # Table walker pending requests distribution 438system.cpu0.dtb.walker.walksPending::0-1 512028975252 99.74% 99.74% # Table walker pending requests distribution 439system.cpu0.dtb.walker.walksPending::2-3 726675000 0.14% 99.88% # Table walker pending requests distribution 440system.cpu0.dtb.walker.walksPending::4-5 290458500 0.06% 99.94% # Table walker pending requests distribution 441system.cpu0.dtb.walker.walksPending::6-7 129299000 0.03% 99.96% # Table walker pending requests distribution 442system.cpu0.dtb.walker.walksPending::8-9 102361000 0.02% 99.98% # Table walker pending requests distribution 443system.cpu0.dtb.walker.walksPending::10-11 55725500 0.01% 99.99% # Table walker pending requests distribution 444system.cpu0.dtb.walker.walksPending::12-13 16517000 0.00% 100.00% # Table walker pending requests distribution 445system.cpu0.dtb.walker.walksPending::14-15 21785000 0.00% 100.00% # Table walker pending requests distribution 446system.cpu0.dtb.walker.walksPending::16-17 858500 0.00% 100.00% # Table walker pending requests distribution 447system.cpu0.dtb.walker.walksPending::18-19 22500 0.00% 100.00% # Table walker pending requests distribution 448system.cpu0.dtb.walker.walksPending::total 513372677252 # Table walker pending requests distribution 449system.cpu0.dtb.walker.walkPageSizes::4K 97395 87.53% 87.53% # Table walker page sizes translated 450system.cpu0.dtb.walker.walkPageSizes::2M 13877 12.47% 100.00% # Table walker page sizes translated 451system.cpu0.dtb.walker.walkPageSizes::total 111272 # Table walker page sizes translated 452system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 607513 # Table walker requests started/completed, data/inst 453system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 454system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 607513 # Table walker requests started/completed, data/inst 455system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 111272 # Table walker requests started/completed, data/inst 456system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 457system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 111272 # Table walker requests started/completed, data/inst 458system.cpu0.dtb.walker.walkRequestOrigin::total 718785 # Table walker requests started/completed, data/inst 459system.cpu0.dtb.inst_hits 0 # ITB inst hits 460system.cpu0.dtb.inst_misses 0 # ITB inst misses 461system.cpu0.dtb.read_hits 141538315 # DTB read hits 462system.cpu0.dtb.read_misses 437252 # DTB read misses 463system.cpu0.dtb.write_hits 86796370 # DTB write hits 464system.cpu0.dtb.write_misses 170261 # DTB write misses 465system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 466system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 467system.cpu0.dtb.flush_tlb_mva_asid 44490 # Number of times TLB was flushed by MVA & ASID 468system.cpu0.dtb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID 469system.cpu0.dtb.flush_entries 43183 # Number of entries that have been flushed from TLB 470system.cpu0.dtb.align_faults 271 # Number of TLB faults due to alignment restrictions 471system.cpu0.dtb.prefetch_faults 6902 # Number of TLB faults due to prefetch 472system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 473system.cpu0.dtb.perms_faults 42288 # Number of TLB faults due to permissions restrictions 474system.cpu0.dtb.read_accesses 141975567 # DTB read accesses 475system.cpu0.dtb.write_accesses 86966631 # DTB write accesses 476system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 477system.cpu0.dtb.hits 228334685 # DTB hits 478system.cpu0.dtb.misses 607513 # DTB misses 479system.cpu0.dtb.accesses 228942198 # DTB accesses 480system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 481system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 482system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 483system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 484system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 485system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 486system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 487system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 488system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 489system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 490system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 491system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 492system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 493system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 494system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 495system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 496system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 497system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 498system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 499system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 500system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 501system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 502system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 503system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 504system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 505system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 506system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 507system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 508system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 509system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 510system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 511system.cpu0.itb.walker.walks 87943 # Table walker walks requested 512system.cpu0.itb.walker.walksLong 87943 # Table walker walks initiated with long descriptors 513system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1130 # Level at which table walker walks with long descriptors terminate 514system.cpu0.itb.walker.walksLongTerminationLevel::Level3 62851 # Level at which table walker walks with long descriptors terminate 515system.cpu0.itb.walker.walksSquashedBefore 10253 # Table walks squashed before starting 516system.cpu0.itb.walker.walkWaitTime::samples 77690 # Table walker wait (enqueue to first request) latency 517system.cpu0.itb.walker.walkWaitTime::mean 1458.353713 # Table walker wait (enqueue to first request) latency 518system.cpu0.itb.walker.walkWaitTime::stdev 10159.922633 # Table walker wait (enqueue to first request) latency 519system.cpu0.itb.walker.walkWaitTime::0-32767 76707 98.73% 98.73% # Table walker wait (enqueue to first request) latency 520system.cpu0.itb.walker.walkWaitTime::32768-65535 405 0.52% 99.26% # Table walker wait (enqueue to first request) latency 521system.cpu0.itb.walker.walkWaitTime::65536-98303 337 0.43% 99.69% # Table walker wait (enqueue to first request) latency 522system.cpu0.itb.walker.walkWaitTime::98304-131071 198 0.25% 99.94% # Table walker wait (enqueue to first request) latency 523system.cpu0.itb.walker.walkWaitTime::131072-163839 9 0.01% 99.96% # Table walker wait (enqueue to first request) latency 524system.cpu0.itb.walker.walkWaitTime::163840-196607 14 0.02% 99.97% # Table walker wait (enqueue to first request) latency 525system.cpu0.itb.walker.walkWaitTime::196608-229375 9 0.01% 99.99% # Table walker wait (enqueue to first request) latency 526system.cpu0.itb.walker.walkWaitTime::262144-294911 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency 527system.cpu0.itb.walker.walkWaitTime::294912-327679 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency 528system.cpu0.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 529system.cpu0.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 530system.cpu0.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 531system.cpu0.itb.walker.walkWaitTime::total 77690 # Table walker wait (enqueue to first request) latency 532system.cpu0.itb.walker.walkCompletionTime::samples 74234 # Table walker service (enqueue to completion) latency 533system.cpu0.itb.walker.walkCompletionTime::mean 26234.178409 # Table walker service (enqueue to completion) latency 534system.cpu0.itb.walker.walkCompletionTime::gmean 23080.051735 # Table walker service (enqueue to completion) latency 535system.cpu0.itb.walker.walkCompletionTime::stdev 21732.027543 # Table walker service (enqueue to completion) latency 536system.cpu0.itb.walker.walkCompletionTime::0-65535 71871 96.82% 96.82% # Table walker service (enqueue to completion) latency 537system.cpu0.itb.walker.walkCompletionTime::65536-131071 1986 2.68% 99.49% # Table walker service (enqueue to completion) latency 538system.cpu0.itb.walker.walkCompletionTime::131072-196607 153 0.21% 99.70% # Table walker service (enqueue to completion) latency 539system.cpu0.itb.walker.walkCompletionTime::196608-262143 128 0.17% 99.87% # Table walker service (enqueue to completion) latency 540system.cpu0.itb.walker.walkCompletionTime::262144-327679 62 0.08% 99.95% # Table walker service (enqueue to completion) latency 541system.cpu0.itb.walker.walkCompletionTime::327680-393215 21 0.03% 99.98% # Table walker service (enqueue to completion) latency 542system.cpu0.itb.walker.walkCompletionTime::393216-458751 9 0.01% 99.99% # Table walker service (enqueue to completion) latency 543system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 544system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 545system.cpu0.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 546system.cpu0.itb.walker.walkCompletionTime::total 74234 # Table walker service (enqueue to completion) latency 547system.cpu0.itb.walker.walksPending::samples 410290287148 # Table walker pending requests distribution 548system.cpu0.itb.walker.walksPending::mean 0.846605 # Table walker pending requests distribution 549system.cpu0.itb.walker.walksPending::stdev 0.360675 # Table walker pending requests distribution 550system.cpu0.itb.walker.walksPending::0 62979367364 15.35% 15.35% # Table walker pending requests distribution 551system.cpu0.itb.walker.walksPending::1 347270506784 84.64% 99.99% # Table walker pending requests distribution 552system.cpu0.itb.walker.walksPending::2 38246000 0.01% 100.00% # Table walker pending requests distribution 553system.cpu0.itb.walker.walksPending::3 1931000 0.00% 100.00% # Table walker pending requests distribution 554system.cpu0.itb.walker.walksPending::4 236000 0.00% 100.00% # Table walker pending requests distribution 555system.cpu0.itb.walker.walksPending::total 410290287148 # Table walker pending requests distribution 556system.cpu0.itb.walker.walkPageSizes::4K 62851 98.23% 98.23% # Table walker page sizes translated 557system.cpu0.itb.walker.walkPageSizes::2M 1130 1.77% 100.00% # Table walker page sizes translated 558system.cpu0.itb.walker.walkPageSizes::total 63981 # Table walker page sizes translated 559system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 560system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 87943 # Table walker requests started/completed, data/inst 561system.cpu0.itb.walker.walkRequestOrigin_Requested::total 87943 # Table walker requests started/completed, data/inst 562system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 563system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 63981 # Table walker requests started/completed, data/inst 564system.cpu0.itb.walker.walkRequestOrigin_Completed::total 63981 # Table walker requests started/completed, data/inst 565system.cpu0.itb.walker.walkRequestOrigin::total 151924 # Table walker requests started/completed, data/inst 566system.cpu0.itb.inst_hits 282848559 # ITB inst hits 567system.cpu0.itb.inst_misses 87943 # ITB inst misses 568system.cpu0.itb.read_hits 0 # DTB read hits 569system.cpu0.itb.read_misses 0 # DTB read misses 570system.cpu0.itb.write_hits 0 # DTB write hits 571system.cpu0.itb.write_misses 0 # DTB write misses 572system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 573system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 574system.cpu0.itb.flush_tlb_mva_asid 44490 # Number of times TLB was flushed by MVA & ASID 575system.cpu0.itb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID 576system.cpu0.itb.flush_entries 30949 # Number of entries that have been flushed from TLB 577system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 578system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 579system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 580system.cpu0.itb.perms_faults 212727 # Number of TLB faults due to permissions restrictions 581system.cpu0.itb.read_accesses 0 # DTB read accesses 582system.cpu0.itb.write_accesses 0 # DTB write accesses 583system.cpu0.itb.inst_accesses 282936502 # ITB inst accesses 584system.cpu0.itb.hits 282848559 # DTB hits 585system.cpu0.itb.misses 87943 # DTB misses 586system.cpu0.itb.accesses 282936502 # DTB accesses 587system.cpu0.numPwrStateTransitions 28168 # Number of power state transitions 588system.cpu0.pwrStateClkGateDist::samples 14084 # Distribution of time spent in the clock gated state 589system.cpu0.pwrStateClkGateDist::mean 3333377849.836978 # Distribution of time spent in the clock gated state 590system.cpu0.pwrStateClkGateDist::stdev 92382687873.308472 # Distribution of time spent in the clock gated state 591system.cpu0.pwrStateClkGateDist::underflows 4020 28.54% 28.54% # Distribution of time spent in the clock gated state 592system.cpu0.pwrStateClkGateDist::1000-5e+10 10033 71.24% 99.78% # Distribution of time spent in the clock gated state 593system.cpu0.pwrStateClkGateDist::5e+10-1e+11 12 0.09% 99.87% # Distribution of time spent in the clock gated state 594system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state 595system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 596system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 597system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state 598system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.91% # Distribution of time spent in the clock gated state 599system.cpu0.pwrStateClkGateDist::overflows 13 0.09% 100.00% # Distribution of time spent in the clock gated state 600system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 601system.cpu0.pwrStateClkGateDist::max_value 6914082605000 # Distribution of time spent in the clock gated state 602system.cpu0.pwrStateClkGateDist::total 14084 # Distribution of time spent in the clock gated state 603system.cpu0.pwrStateResidencyTicks::ON 437057662896 # Cumulative time (in ticks) in various power states 604system.cpu0.pwrStateResidencyTicks::CLK_GATED 46947293637104 # Cumulative time (in ticks) in various power states 605system.cpu0.numCycles 874125395 # number of cpu cycles simulated 606system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 607system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 608system.cpu0.fetch.icacheStallCycles 92275983 # Number of cycles fetch is stalled on an Icache miss 609system.cpu0.fetch.Insts 768900237 # Number of instructions fetch has processed 610system.cpu0.fetch.Branches 199183431 # Number of branches that fetch encountered 611system.cpu0.fetch.predictedBranches 122923240 # Number of branches that fetch has predicted taken 612system.cpu0.fetch.Cycles 738928784 # Number of cycles fetch has run and was not squashing or blocked 613system.cpu0.fetch.SquashCycles 15190816 # Number of cycles fetch has spent squashing 614system.cpu0.fetch.TlbCycles 2037144 # Number of cycles fetch has spent waiting for tlb 615system.cpu0.fetch.MiscStallCycles 294842 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 616system.cpu0.fetch.PendingTrapStallCycles 6072240 # Number of stall cycles due to pending traps 617system.cpu0.fetch.PendingQuiesceStallCycles 792344 # Number of stall cycles due to pending quiesce instructions 618system.cpu0.fetch.IcacheWaitRetryStallCycles 839757 # Number of stall cycles due to full MSHR 619system.cpu0.fetch.CacheLines 282635522 # Number of cache lines fetched 620system.cpu0.fetch.IcacheSquashes 1737700 # Number of outstanding Icache misses that were squashed 621system.cpu0.fetch.ItlbSquashes 28623 # Number of outstanding ITLB misses that were squashed 622system.cpu0.fetch.rateDist::samples 848836502 # Number of instructions fetched each cycle (Total) 623system.cpu0.fetch.rateDist::mean 1.034930 # Number of instructions fetched each cycle (Total) 624system.cpu0.fetch.rateDist::stdev 1.208968 # Number of instructions fetched each cycle (Total) 625system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 626system.cpu0.fetch.rateDist::0 416377385 49.05% 49.05% # Number of instructions fetched each cycle (Total) 627system.cpu0.fetch.rateDist::1 176079063 20.74% 69.80% # Number of instructions fetched each cycle (Total) 628system.cpu0.fetch.rateDist::2 66732959 7.86% 77.66% # Number of instructions fetched each cycle (Total) 629system.cpu0.fetch.rateDist::3 189647095 22.34% 100.00% # Number of instructions fetched each cycle (Total) 630system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 631system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 632system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 633system.cpu0.fetch.rateDist::total 848836502 # Number of instructions fetched each cycle (Total) 634system.cpu0.fetch.branchRate 0.227866 # Number of branch fetches per cycle 635system.cpu0.fetch.rate 0.879622 # Number of inst fetches per cycle 636system.cpu0.decode.IdleCycles 110330106 # Number of cycles decode is idle 637system.cpu0.decode.BlockedCycles 381856903 # Number of cycles decode is blocked 638system.cpu0.decode.RunCycles 311429263 # Number of cycles decode is running 639system.cpu0.decode.UnblockCycles 39757521 # Number of cycles decode is unblocking 640system.cpu0.decode.SquashCycles 5462709 # Number of cycles decode is squashing 641system.cpu0.decode.BranchResolved 29836532 # Number of times decode resolved a branch 642system.cpu0.decode.BranchMispred 2173523 # Number of times decode detected a branch misprediction 643system.cpu0.decode.DecodedInsts 791623702 # Number of instructions handled by decode 644system.cpu0.decode.SquashedInsts 24444549 # Number of squashed instructions handled by decode 645system.cpu0.rename.SquashCycles 5462709 # Number of cycles rename is squashing 646system.cpu0.rename.IdleCycles 147675961 # Number of cycles rename is idle 647system.cpu0.rename.BlockCycles 53914284 # Number of cycles rename is blocking 648system.cpu0.rename.serializeStallCycles 258297798 # count of cycles rename stalled for serializing inst 649system.cpu0.rename.RunCycles 313275075 # Number of cycles rename is running 650system.cpu0.rename.UnblockCycles 70210675 # Number of cycles rename is unblocking 651system.cpu0.rename.RenamedInsts 773227105 # Number of instructions processed by rename 652system.cpu0.rename.SquashedInsts 6509157 # Number of squashed instructions processed by rename 653system.cpu0.rename.ROBFullEvents 10689754 # Number of times rename has blocked due to ROB full 654system.cpu0.rename.IQFullEvents 377832 # Number of times rename has blocked due to IQ full 655system.cpu0.rename.LQFullEvents 811571 # Number of times rename has blocked due to LQ full 656system.cpu0.rename.SQFullEvents 32991272 # Number of times rename has blocked due to SQ full 657system.cpu0.rename.FullRegisterEvents 11799 # Number of times there has been no free registers 658system.cpu0.rename.RenamedOperands 742885425 # Number of destination operands rename has renamed 659system.cpu0.rename.RenameLookups 1169549966 # Number of register rename lookups that rename has made 660system.cpu0.rename.int_rename_lookups 880889153 # Number of integer rename lookups 661system.cpu0.rename.fp_rename_lookups 700737 # Number of floating rename lookups 662system.cpu0.rename.CommittedMaps 682115784 # Number of HB maps that are committed 663system.cpu0.rename.UndoneMaps 60769635 # Number of HB maps that are undone due to squashing 664system.cpu0.rename.serializingInsts 16576266 # count of serializing insts renamed 665system.cpu0.rename.tempSerializingInsts 14423738 # count of temporary serializing insts renamed 666system.cpu0.rename.skidInsts 79729853 # count of insts added to the skid buffer 667system.cpu0.memDep0.insertedLoads 141637487 # Number of loads inserted to the mem dependence unit. 668system.cpu0.memDep0.insertedStores 90242008 # Number of stores inserted to the mem dependence unit. 669system.cpu0.memDep0.conflictingLoads 9692958 # Number of conflicting loads. 670system.cpu0.memDep0.conflictingStores 8374311 # Number of conflicting stores. 671system.cpu0.iq.iqInstsAdded 749539213 # Number of instructions added to the IQ (excludes non-spec) 672system.cpu0.iq.iqNonSpecInstsAdded 16620515 # Number of non-speculative instructions added to the IQ 673system.cpu0.iq.iqInstsIssued 754385019 # Number of instructions issued 674system.cpu0.iq.iqSquashedInstsIssued 2849937 # Number of squashed instructions issued 675system.cpu0.iq.iqSquashedInstsExamined 57154900 # Number of squashed instructions iterated over during squash; mainly for profiling 676system.cpu0.iq.iqSquashedOperandsExamined 36998097 # Number of squashed operands that are examined and possibly removed from graph 677system.cpu0.iq.iqSquashedNonSpecRemoved 294454 # Number of squashed non-spec instructions that were removed 678system.cpu0.iq.issued_per_cycle::samples 848836502 # Number of insts issued each cycle 679system.cpu0.iq.issued_per_cycle::mean 0.888728 # Number of insts issued each cycle 680system.cpu0.iq.issued_per_cycle::stdev 1.088535 # Number of insts issued each cycle 681system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 682system.cpu0.iq.issued_per_cycle::0 442949824 52.18% 52.18% # Number of insts issued each cycle 683system.cpu0.iq.issued_per_cycle::1 161566736 19.03% 71.22% # Number of insts issued each cycle 684system.cpu0.iq.issued_per_cycle::2 148384909 17.48% 88.70% # Number of insts issued each cycle 685system.cpu0.iq.issued_per_cycle::3 87697049 10.33% 99.03% # Number of insts issued each cycle 686system.cpu0.iq.issued_per_cycle::4 8232602 0.97% 100.00% # Number of insts issued each cycle 687system.cpu0.iq.issued_per_cycle::5 5382 0.00% 100.00% # Number of insts issued each cycle 688system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 689system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 690system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 691system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 692system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 693system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 694system.cpu0.iq.issued_per_cycle::total 848836502 # Number of insts issued each cycle 695system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 696system.cpu0.iq.fu_full::IntAlu 74538342 48.88% 48.88% # attempts to use FU when none available 697system.cpu0.iq.fu_full::IntMult 62447 0.04% 48.92% # attempts to use FU when none available 698system.cpu0.iq.fu_full::IntDiv 15099 0.01% 48.93% # attempts to use FU when none available 699system.cpu0.iq.fu_full::FloatAdd 0 0.00% 48.93% # attempts to use FU when none available 700system.cpu0.iq.fu_full::FloatCmp 0 0.00% 48.93% # attempts to use FU when none available 701system.cpu0.iq.fu_full::FloatCvt 0 0.00% 48.93% # attempts to use FU when none available 702system.cpu0.iq.fu_full::FloatMult 0 0.00% 48.93% # attempts to use FU when none available 703system.cpu0.iq.fu_full::FloatDiv 0 0.00% 48.93% # attempts to use FU when none available 704system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 48.93% # attempts to use FU when none available 705system.cpu0.iq.fu_full::SimdAdd 0 0.00% 48.93% # attempts to use FU when none available 706system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 48.93% # attempts to use FU when none available 707system.cpu0.iq.fu_full::SimdAlu 0 0.00% 48.93% # attempts to use FU when none available 708system.cpu0.iq.fu_full::SimdCmp 0 0.00% 48.93% # attempts to use FU when none available 709system.cpu0.iq.fu_full::SimdCvt 0 0.00% 48.93% # attempts to use FU when none available 710system.cpu0.iq.fu_full::SimdMisc 0 0.00% 48.93% # attempts to use FU when none available 711system.cpu0.iq.fu_full::SimdMult 0 0.00% 48.93% # attempts to use FU when none available 712system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 48.93% # attempts to use FU when none available 713system.cpu0.iq.fu_full::SimdShift 0 0.00% 48.93% # attempts to use FU when none available 714system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 48.93% # attempts to use FU when none available 715system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 48.93% # attempts to use FU when none available 716system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 48.93% # attempts to use FU when none available 717system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 48.93% # attempts to use FU when none available 718system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 48.93% # attempts to use FU when none available 719system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 48.93% # attempts to use FU when none available 720system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 48.93% # attempts to use FU when none available 721system.cpu0.iq.fu_full::SimdFloatMisc 9 0.00% 48.93% # attempts to use FU when none available 722system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 48.93% # attempts to use FU when none available 723system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.93% # attempts to use FU when none available 724system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 48.93% # attempts to use FU when none available 725system.cpu0.iq.fu_full::MemRead 37581602 24.64% 73.57% # attempts to use FU when none available 726system.cpu0.iq.fu_full::MemWrite 40298347 26.43% 100.00% # attempts to use FU when none available 727system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 728system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 729system.cpu0.iq.FU_type_0::No_OpClass 51 0.00% 0.00% # Type of FU issued 730system.cpu0.iq.FU_type_0::IntAlu 519755806 68.90% 68.90% # Type of FU issued 731system.cpu0.iq.FU_type_0::IntMult 1543884 0.20% 69.10% # Type of FU issued 732system.cpu0.iq.FU_type_0::IntDiv 77211 0.01% 69.11% # Type of FU issued 733system.cpu0.iq.FU_type_0::FloatAdd 64 0.00% 69.11% # Type of FU issued 734system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.11% # Type of FU issued 735system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.11% # Type of FU issued 736system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.11% # Type of FU issued 737system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 69.11% # Type of FU issued 738system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.11% # Type of FU issued 739system.cpu0.iq.FU_type_0::SimdAdd 2 0.00% 69.11% # Type of FU issued 740system.cpu0.iq.FU_type_0::SimdAddAcc 1 0.00% 69.11% # Type of FU issued 741system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 69.11% # Type of FU issued 742system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.11% # Type of FU issued 743system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.11% # Type of FU issued 744system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.11% # Type of FU issued 745system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.11% # Type of FU issued 746system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.11% # Type of FU issued 747system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.11% # Type of FU issued 748system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.11% # Type of FU issued 749system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.11% # Type of FU issued 750system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.11% # Type of FU issued 751system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.11% # Type of FU issued 752system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.11% # Type of FU issued 753system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.11% # Type of FU issued 754system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.11% # Type of FU issued 755system.cpu0.iq.FU_type_0::SimdFloatMisc 42719 0.01% 69.12% # Type of FU issued 756system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.12% # Type of FU issued 757system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.12% # Type of FU issued 758system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.12% # Type of FU issued 759system.cpu0.iq.FU_type_0::MemRead 144854124 19.20% 88.32% # Type of FU issued 760system.cpu0.iq.FU_type_0::MemWrite 88111156 11.68% 100.00% # Type of FU issued 761system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 762system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 763system.cpu0.iq.FU_type_0::total 754385019 # Type of FU issued 764system.cpu0.iq.rate 0.863017 # Inst issue rate 765system.cpu0.iq.fu_busy_cnt 152495846 # FU busy when requested 766system.cpu0.iq.fu_busy_rate 0.202146 # FU busy rate (busy events/executed inst) 767system.cpu0.iq.int_inst_queue_reads 2511823586 # Number of integer instruction queue reads 768system.cpu0.iq.int_inst_queue_writes 823027375 # Number of integer instruction queue writes 769system.cpu0.iq.int_inst_queue_wakeup_accesses 736101219 # Number of integer instruction queue wakeup accesses 770system.cpu0.iq.fp_inst_queue_reads 1128735 # Number of floating instruction queue reads 771system.cpu0.iq.fp_inst_queue_writes 443604 # Number of floating instruction queue writes 772system.cpu0.iq.fp_inst_queue_wakeup_accesses 415332 # Number of floating instruction queue wakeup accesses 773system.cpu0.iq.int_alu_accesses 906176667 # Number of integer alu accesses 774system.cpu0.iq.fp_alu_accesses 704147 # Number of floating point alu accesses 775system.cpu0.iew.lsq.thread0.forwLoads 2868207 # Number of loads that had data forwarded from stores 776system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 777system.cpu0.iew.lsq.thread0.squashedLoads 13104832 # Number of loads squashed 778system.cpu0.iew.lsq.thread0.ignoredResponses 17724 # Number of memory responses ignored because the instruction is squashed 779system.cpu0.iew.lsq.thread0.memOrderViolation 157642 # Number of memory ordering violations 780system.cpu0.iew.lsq.thread0.squashedStores 5794849 # Number of stores squashed 781system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 782system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 783system.cpu0.iew.lsq.thread0.rescheduledLoads 2875718 # Number of loads that were rescheduled 784system.cpu0.iew.lsq.thread0.cacheBlocked 4918474 # Number of times an access to memory failed due to the cache being blocked 785system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 786system.cpu0.iew.iewSquashCycles 5462709 # Number of cycles IEW is squashing 787system.cpu0.iew.iewBlockCycles 7926079 # Number of cycles IEW is blocking 788system.cpu0.iew.iewUnblockCycles 1884320 # Number of cycles IEW is unblocking 789system.cpu0.iew.iewDispatchedInsts 766295642 # Number of instructions dispatched to IQ 790system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 791system.cpu0.iew.iewDispLoadInsts 141637487 # Number of dispatched load instructions 792system.cpu0.iew.iewDispStoreInsts 90242008 # Number of dispatched store instructions 793system.cpu0.iew.iewDispNonSpecInsts 14144816 # Number of dispatched non-speculative instructions 794system.cpu0.iew.iewIQFullEvents 61216 # Number of times the IQ has become full, causing a stall 795system.cpu0.iew.iewLSQFullEvents 1749510 # Number of times the LSQ has become full, causing a stall 796system.cpu0.iew.memOrderViolationEvents 157642 # Number of memory order violations 797system.cpu0.iew.predictedTakenIncorrect 2035907 # Number of branches that were predicted taken incorrectly 798system.cpu0.iew.predictedNotTakenIncorrect 3235941 # Number of branches that were predicted not taken incorrectly 799system.cpu0.iew.branchMispredicts 5271848 # Number of branch mispredicts detected at execute 800system.cpu0.iew.iewExecutedInsts 745963336 # Number of executed instructions 801system.cpu0.iew.iewExecLoadInsts 141529970 # Number of load instructions executed 802system.cpu0.iew.iewExecSquashedInsts 7821454 # Number of squashed instructions skipped in execute 803system.cpu0.iew.exec_swp 0 # number of swp insts executed 804system.cpu0.iew.exec_nop 135914 # number of nop insts executed 805system.cpu0.iew.exec_refs 228324326 # number of memory reference insts executed 806system.cpu0.iew.exec_branches 170531782 # Number of branches executed 807system.cpu0.iew.exec_stores 86794356 # Number of stores executed 808system.cpu0.iew.exec_rate 0.853383 # Inst execution rate 809system.cpu0.iew.wb_sent 737330155 # cumulative count of insts sent to commit 810system.cpu0.iew.wb_count 736516551 # cumulative count of insts written-back 811system.cpu0.iew.wb_producers 351214969 # num instructions producing a value 812system.cpu0.iew.wb_consumers 595098705 # num instructions consuming a value 813system.cpu0.iew.wb_rate 0.842575 # insts written-back per cycle 814system.cpu0.iew.wb_fanout 0.590179 # average fanout of values written-back 815system.cpu0.commit.commitSquashedInsts 49835507 # The number of squashed insts skipped by commit 816system.cpu0.commit.commitNonSpecStalls 16326061 # The number of times commit has been forced to stall to communicate backwards 817system.cpu0.commit.branchMispredicts 4903366 # The number of times a branch was mispredicted 818system.cpu0.commit.committed_per_cycle::samples 839368834 # Number of insts commited each cycle 819system.cpu0.commit.committed_per_cycle::mean 0.844688 # Number of insts commited each cycle 820system.cpu0.commit.committed_per_cycle::stdev 1.533259 # Number of insts commited each cycle 821system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 822system.cpu0.commit.committed_per_cycle::0 512658006 61.08% 61.08% # Number of insts commited each cycle 823system.cpu0.commit.committed_per_cycle::1 158759517 18.91% 79.99% # Number of insts commited each cycle 824system.cpu0.commit.committed_per_cycle::2 92536082 11.02% 91.02% # Number of insts commited each cycle 825system.cpu0.commit.committed_per_cycle::3 27862473 3.32% 94.33% # Number of insts commited each cycle 826system.cpu0.commit.committed_per_cycle::4 13576189 1.62% 95.95% # Number of insts commited each cycle 827system.cpu0.commit.committed_per_cycle::5 9358920 1.11% 97.07% # Number of insts commited each cycle 828system.cpu0.commit.committed_per_cycle::6 6289735 0.75% 97.82% # Number of insts commited each cycle 829system.cpu0.commit.committed_per_cycle::7 3875341 0.46% 98.28% # Number of insts commited each cycle 830system.cpu0.commit.committed_per_cycle::8 14452571 1.72% 100.00% # Number of insts commited each cycle 831system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 832system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 833system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 834system.cpu0.commit.committed_per_cycle::total 839368834 # Number of insts commited each cycle 835system.cpu0.commit.committedInsts 622433451 # Number of instructions committed 836system.cpu0.commit.committedOps 709004821 # Number of ops (including micro ops) committed 837system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 838system.cpu0.commit.refs 212979813 # Number of memory references committed 839system.cpu0.commit.loads 128532654 # Number of loads committed 840system.cpu0.commit.membars 3921678 # Number of memory barriers committed 841system.cpu0.commit.branches 164749224 # Number of branches committed 842system.cpu0.commit.fp_insts 407380 # Number of committed floating point instructions. 843system.cpu0.commit.int_insts 634275437 # Number of committed integer instructions. 844system.cpu0.commit.function_calls 14942203 # Number of function calls committed. 845system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 846system.cpu0.commit.op_class_0::IntAlu 494636379 69.76% 69.76% # Class of committed instruction 847system.cpu0.commit.op_class_0::IntMult 1291078 0.18% 69.95% # Class of committed instruction 848system.cpu0.commit.op_class_0::IntDiv 60530 0.01% 69.96% # Class of committed instruction 849system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.96% # Class of committed instruction 850system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.96% # Class of committed instruction 851system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.96% # Class of committed instruction 852system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.96% # Class of committed instruction 853system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.96% # Class of committed instruction 854system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.96% # Class of committed instruction 855system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.96% # Class of committed instruction 856system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.96% # Class of committed instruction 857system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.96% # Class of committed instruction 858system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.96% # Class of committed instruction 859system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.96% # Class of committed instruction 860system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.96% # Class of committed instruction 861system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.96% # Class of committed instruction 862system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.96% # Class of committed instruction 863system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.96% # Class of committed instruction 864system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.96% # Class of committed instruction 865system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.96% # Class of committed instruction 866system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.96% # Class of committed instruction 867system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.96% # Class of committed instruction 868system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.96% # Class of committed instruction 869system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.96% # Class of committed instruction 870system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.96% # Class of committed instruction 871system.cpu0.commit.op_class_0::SimdFloatMisc 37021 0.01% 69.96% # Class of committed instruction 872system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.96% # Class of committed instruction 873system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.96% # Class of committed instruction 874system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.96% # Class of committed instruction 875system.cpu0.commit.op_class_0::MemRead 128532654 18.13% 88.09% # Class of committed instruction 876system.cpu0.commit.op_class_0::MemWrite 84447159 11.91% 100.00% # Class of committed instruction 877system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 878system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 879system.cpu0.commit.op_class_0::total 709004821 # Class of committed instruction 880system.cpu0.commit.bw_lim_events 14452571 # number cycles where commit BW limit reached 881system.cpu0.rob.rob_reads 1579278211 # The number of ROB reads 882system.cpu0.rob.rob_writes 1527109253 # The number of ROB writes 883system.cpu0.timesIdled 1033857 # Number of times that the entire CPU went into an idle state and unscheduled itself 884system.cpu0.idleCycles 25288893 # Total number of cycles that the CPU has spent unscheduled due to idling 885system.cpu0.quiesceCycles 93894577230 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 886system.cpu0.committedInsts 622433451 # Number of Instructions Simulated 887system.cpu0.committedOps 709004821 # Number of Ops (including micro ops) Simulated 888system.cpu0.cpi 1.404368 # CPI: Cycles Per Instruction 889system.cpu0.cpi_total 1.404368 # CPI: Total CPI of All Threads 890system.cpu0.ipc 0.712064 # IPC: Instructions Per Cycle 891system.cpu0.ipc_total 0.712064 # IPC: Total IPC of All Threads 892system.cpu0.int_regfile_reads 848778973 # number of integer regfile reads 893system.cpu0.int_regfile_writes 506977822 # number of integer regfile writes 894system.cpu0.fp_regfile_reads 685984 # number of floating regfile reads 895system.cpu0.fp_regfile_writes 317032 # number of floating regfile writes 896system.cpu0.cc_regfile_reads 188384037 # number of cc regfile reads 897system.cpu0.cc_regfile_writes 189031095 # number of cc regfile writes 898system.cpu0.misc_regfile_reads 1602344785 # number of misc regfile reads 899system.cpu0.misc_regfile_writes 16401028 # number of misc regfile writes 900system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 901system.cpu0.dcache.tags.replacements 6409966 # number of replacements 902system.cpu0.dcache.tags.tagsinuse 480.619482 # Cycle average of tags in use 903system.cpu0.dcache.tags.total_refs 199938758 # Total number of references to valid blocks. 904system.cpu0.dcache.tags.sampled_refs 6410478 # Sample count of references to valid blocks. 905system.cpu0.dcache.tags.avg_refs 31.189368 # Average number of references to valid blocks. 906system.cpu0.dcache.tags.warmup_cycle 1908955000 # Cycle when the warmup percentage was hit. 907system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.619482 # Average occupied blocks per requestor 908system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938710 # Average percentage of cache occupancy 909system.cpu0.dcache.tags.occ_percent::total 0.938710 # Average percentage of cache occupancy 910system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 911system.cpu0.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id 912system.cpu0.dcache.tags.age_task_id_blocks_1024::1 395 # Occupied blocks per task id 913system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id 914system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 915system.cpu0.dcache.tags.tag_accesses 439216738 # Number of tag accesses 916system.cpu0.dcache.tags.data_accesses 439216738 # Number of data accesses 917system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 918system.cpu0.dcache.ReadReq_hits::cpu0.data 121629785 # number of ReadReq hits 919system.cpu0.dcache.ReadReq_hits::total 121629785 # number of ReadReq hits 920system.cpu0.dcache.WriteReq_hits::cpu0.data 73254039 # number of WriteReq hits 921system.cpu0.dcache.WriteReq_hits::total 73254039 # number of WriteReq hits 922system.cpu0.dcache.SoftPFReq_hits::cpu0.data 225954 # number of SoftPFReq hits 923system.cpu0.dcache.SoftPFReq_hits::total 225954 # number of SoftPFReq hits 924system.cpu0.dcache.WriteLineReq_hits::cpu0.data 195110 # number of WriteLineReq hits 925system.cpu0.dcache.WriteLineReq_hits::total 195110 # number of WriteLineReq hits 926system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1865486 # number of LoadLockedReq hits 927system.cpu0.dcache.LoadLockedReq_hits::total 1865486 # number of LoadLockedReq hits 928system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1919454 # number of StoreCondReq hits 929system.cpu0.dcache.StoreCondReq_hits::total 1919454 # number of StoreCondReq hits 930system.cpu0.dcache.demand_hits::cpu0.data 195078934 # number of demand (read+write) hits 931system.cpu0.dcache.demand_hits::total 195078934 # number of demand (read+write) hits 932system.cpu0.dcache.overall_hits::cpu0.data 195304888 # number of overall hits 933system.cpu0.dcache.overall_hits::total 195304888 # number of overall hits 934system.cpu0.dcache.ReadReq_misses::cpu0.data 7140435 # number of ReadReq misses 935system.cpu0.dcache.ReadReq_misses::total 7140435 # number of ReadReq misses 936system.cpu0.dcache.WriteReq_misses::cpu0.data 8024708 # number of WriteReq misses 937system.cpu0.dcache.WriteReq_misses::total 8024708 # number of WriteReq misses 938system.cpu0.dcache.SoftPFReq_misses::cpu0.data 776369 # number of SoftPFReq misses 939system.cpu0.dcache.SoftPFReq_misses::total 776369 # number of SoftPFReq misses 940system.cpu0.dcache.WriteLineReq_misses::cpu0.data 838591 # number of WriteLineReq misses 941system.cpu0.dcache.WriteLineReq_misses::total 838591 # number of WriteLineReq misses 942system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 289464 # number of LoadLockedReq misses 943system.cpu0.dcache.LoadLockedReq_misses::total 289464 # number of LoadLockedReq misses 944system.cpu0.dcache.StoreCondReq_misses::cpu0.data 195968 # number of StoreCondReq misses 945system.cpu0.dcache.StoreCondReq_misses::total 195968 # number of StoreCondReq misses 946system.cpu0.dcache.demand_misses::cpu0.data 16003734 # number of demand (read+write) misses 947system.cpu0.dcache.demand_misses::total 16003734 # number of demand (read+write) misses 948system.cpu0.dcache.overall_misses::cpu0.data 16780103 # number of overall misses 949system.cpu0.dcache.overall_misses::total 16780103 # number of overall misses 950system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 108528058000 # number of ReadReq miss cycles 951system.cpu0.dcache.ReadReq_miss_latency::total 108528058000 # number of ReadReq miss cycles 952system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 153779451872 # number of WriteReq miss cycles 953system.cpu0.dcache.WriteReq_miss_latency::total 153779451872 # number of WriteReq miss cycles 954system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 31763636892 # number of WriteLineReq miss cycles 955system.cpu0.dcache.WriteLineReq_miss_latency::total 31763636892 # number of WriteLineReq miss cycles 956system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4317295000 # number of LoadLockedReq miss cycles 957system.cpu0.dcache.LoadLockedReq_miss_latency::total 4317295000 # number of LoadLockedReq miss cycles 958system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4927286000 # number of StoreCondReq miss cycles 959system.cpu0.dcache.StoreCondReq_miss_latency::total 4927286000 # number of StoreCondReq miss cycles 960system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3123500 # number of StoreCondFailReq miss cycles 961system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3123500 # number of StoreCondFailReq miss cycles 962system.cpu0.dcache.demand_miss_latency::cpu0.data 294071146764 # number of demand (read+write) miss cycles 963system.cpu0.dcache.demand_miss_latency::total 294071146764 # number of demand (read+write) miss cycles 964system.cpu0.dcache.overall_miss_latency::cpu0.data 294071146764 # number of overall miss cycles 965system.cpu0.dcache.overall_miss_latency::total 294071146764 # number of overall miss cycles 966system.cpu0.dcache.ReadReq_accesses::cpu0.data 128770220 # number of ReadReq accesses(hits+misses) 967system.cpu0.dcache.ReadReq_accesses::total 128770220 # number of ReadReq accesses(hits+misses) 968system.cpu0.dcache.WriteReq_accesses::cpu0.data 81278747 # number of WriteReq accesses(hits+misses) 969system.cpu0.dcache.WriteReq_accesses::total 81278747 # number of WriteReq accesses(hits+misses) 970system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1002323 # number of SoftPFReq accesses(hits+misses) 971system.cpu0.dcache.SoftPFReq_accesses::total 1002323 # number of SoftPFReq accesses(hits+misses) 972system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1033701 # number of WriteLineReq accesses(hits+misses) 973system.cpu0.dcache.WriteLineReq_accesses::total 1033701 # number of WriteLineReq accesses(hits+misses) 974system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2154950 # number of LoadLockedReq accesses(hits+misses) 975system.cpu0.dcache.LoadLockedReq_accesses::total 2154950 # number of LoadLockedReq accesses(hits+misses) 976system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2115422 # number of StoreCondReq accesses(hits+misses) 977system.cpu0.dcache.StoreCondReq_accesses::total 2115422 # number of StoreCondReq accesses(hits+misses) 978system.cpu0.dcache.demand_accesses::cpu0.data 211082668 # number of demand (read+write) accesses 979system.cpu0.dcache.demand_accesses::total 211082668 # number of demand (read+write) accesses 980system.cpu0.dcache.overall_accesses::cpu0.data 212084991 # number of overall (read+write) accesses 981system.cpu0.dcache.overall_accesses::total 212084991 # number of overall (read+write) accesses 982system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.055451 # miss rate for ReadReq accesses 983system.cpu0.dcache.ReadReq_miss_rate::total 0.055451 # miss rate for ReadReq accesses 984system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.098731 # miss rate for WriteReq accesses 985system.cpu0.dcache.WriteReq_miss_rate::total 0.098731 # miss rate for WriteReq accesses 986system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.774570 # miss rate for SoftPFReq accesses 987system.cpu0.dcache.SoftPFReq_miss_rate::total 0.774570 # miss rate for SoftPFReq accesses 988system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.811251 # miss rate for WriteLineReq accesses 989system.cpu0.dcache.WriteLineReq_miss_rate::total 0.811251 # miss rate for WriteLineReq accesses 990system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.134325 # miss rate for LoadLockedReq accesses 991system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.134325 # miss rate for LoadLockedReq accesses 992system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.092638 # miss rate for StoreCondReq accesses 993system.cpu0.dcache.StoreCondReq_miss_rate::total 0.092638 # miss rate for StoreCondReq accesses 994system.cpu0.dcache.demand_miss_rate::cpu0.data 0.075817 # miss rate for demand accesses 995system.cpu0.dcache.demand_miss_rate::total 0.075817 # miss rate for demand accesses 996system.cpu0.dcache.overall_miss_rate::cpu0.data 0.079120 # miss rate for overall accesses 997system.cpu0.dcache.overall_miss_rate::total 0.079120 # miss rate for overall accesses 998system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15199.082129 # average ReadReq miss latency 999system.cpu0.dcache.ReadReq_avg_miss_latency::total 15199.082129 # average ReadReq miss latency 1000system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19163.245799 # average WriteReq miss latency 1001system.cpu0.dcache.WriteReq_avg_miss_latency::total 19163.245799 # average WriteReq miss latency 1002system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 37877.388252 # average WriteLineReq miss latency 1003system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 37877.388252 # average WriteLineReq miss latency 1004system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14914.790786 # average LoadLockedReq miss latency 1005system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14914.790786 # average LoadLockedReq miss latency 1006system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25143.319317 # average StoreCondReq miss latency 1007system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25143.319317 # average StoreCondReq miss latency 1008system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 1009system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1010system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 18375.158370 # average overall miss latency 1011system.cpu0.dcache.demand_avg_miss_latency::total 18375.158370 # average overall miss latency 1012system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17524.990566 # average overall miss latency 1013system.cpu0.dcache.overall_avg_miss_latency::total 17524.990566 # average overall miss latency 1014system.cpu0.dcache.blocked_cycles::no_mshrs 9668545 # number of cycles access was blocked 1015system.cpu0.dcache.blocked_cycles::no_targets 23532840 # number of cycles access was blocked 1016system.cpu0.dcache.blocked::no_mshrs 779892 # number of cycles access was blocked 1017system.cpu0.dcache.blocked::no_targets 794197 # number of cycles access was blocked 1018system.cpu0.dcache.avg_blocked_cycles::no_mshrs 12.397287 # average number of cycles each access was blocked 1019system.cpu0.dcache.avg_blocked_cycles::no_targets 29.630986 # average number of cycles each access was blocked 1020system.cpu0.dcache.writebacks::writebacks 6410042 # number of writebacks 1021system.cpu0.dcache.writebacks::total 6410042 # number of writebacks 1022system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3690786 # number of ReadReq MSHR hits 1023system.cpu0.dcache.ReadReq_mshr_hits::total 3690786 # number of ReadReq MSHR hits 1024system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6446005 # number of WriteReq MSHR hits 1025system.cpu0.dcache.WriteReq_mshr_hits::total 6446005 # number of WriteReq MSHR hits 1026system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4347 # number of WriteLineReq MSHR hits 1027system.cpu0.dcache.WriteLineReq_mshr_hits::total 4347 # number of WriteLineReq MSHR hits 1028system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 149571 # number of LoadLockedReq MSHR hits 1029system.cpu0.dcache.LoadLockedReq_mshr_hits::total 149571 # number of LoadLockedReq MSHR hits 1030system.cpu0.dcache.demand_mshr_hits::cpu0.data 10141138 # number of demand (read+write) MSHR hits 1031system.cpu0.dcache.demand_mshr_hits::total 10141138 # number of demand (read+write) MSHR hits 1032system.cpu0.dcache.overall_mshr_hits::cpu0.data 10141138 # number of overall MSHR hits 1033system.cpu0.dcache.overall_mshr_hits::total 10141138 # number of overall MSHR hits 1034system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3449649 # number of ReadReq MSHR misses 1035system.cpu0.dcache.ReadReq_mshr_misses::total 3449649 # number of ReadReq MSHR misses 1036system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1578703 # number of WriteReq MSHR misses 1037system.cpu0.dcache.WriteReq_mshr_misses::total 1578703 # number of WriteReq MSHR misses 1038system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 769355 # number of SoftPFReq MSHR misses 1039system.cpu0.dcache.SoftPFReq_mshr_misses::total 769355 # number of SoftPFReq MSHR misses 1040system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 834244 # number of WriteLineReq MSHR misses 1041system.cpu0.dcache.WriteLineReq_mshr_misses::total 834244 # number of WriteLineReq MSHR misses 1042system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 139893 # number of LoadLockedReq MSHR misses 1043system.cpu0.dcache.LoadLockedReq_mshr_misses::total 139893 # number of LoadLockedReq MSHR misses 1044system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 195965 # number of StoreCondReq MSHR misses 1045system.cpu0.dcache.StoreCondReq_mshr_misses::total 195965 # number of StoreCondReq MSHR misses 1046system.cpu0.dcache.demand_mshr_misses::cpu0.data 5862596 # number of demand (read+write) MSHR misses 1047system.cpu0.dcache.demand_mshr_misses::total 5862596 # number of demand (read+write) MSHR misses 1048system.cpu0.dcache.overall_mshr_misses::cpu0.data 6631951 # number of overall MSHR misses 1049system.cpu0.dcache.overall_mshr_misses::total 6631951 # number of overall MSHR misses 1050system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31285 # number of ReadReq MSHR uncacheable 1051system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31285 # number of ReadReq MSHR uncacheable 1052system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 30958 # number of WriteReq MSHR uncacheable 1053system.cpu0.dcache.WriteReq_mshr_uncacheable::total 30958 # number of WriteReq MSHR uncacheable 1054system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 62243 # number of overall MSHR uncacheable misses 1055system.cpu0.dcache.overall_mshr_uncacheable_misses::total 62243 # number of overall MSHR uncacheable misses 1056system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 50416416500 # number of ReadReq MSHR miss cycles 1057system.cpu0.dcache.ReadReq_mshr_miss_latency::total 50416416500 # number of ReadReq MSHR miss cycles 1058system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 33875543231 # number of WriteReq MSHR miss cycles 1059system.cpu0.dcache.WriteReq_mshr_miss_latency::total 33875543231 # number of WriteReq MSHR miss cycles 1060system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17245260500 # number of SoftPFReq MSHR miss cycles 1061system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17245260500 # number of SoftPFReq MSHR miss cycles 1062system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 30759768392 # number of WriteLineReq MSHR miss cycles 1063system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 30759768392 # number of WriteLineReq MSHR miss cycles 1064system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1918237000 # number of LoadLockedReq MSHR miss cycles 1065system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1918237000 # number of LoadLockedReq MSHR miss cycles 1066system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4731380000 # number of StoreCondReq MSHR miss cycles 1067system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4731380000 # number of StoreCondReq MSHR miss cycles 1068system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3064500 # number of StoreCondFailReq MSHR miss cycles 1069system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3064500 # number of StoreCondFailReq MSHR miss cycles 1070system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 115051728123 # number of demand (read+write) MSHR miss cycles 1071system.cpu0.dcache.demand_mshr_miss_latency::total 115051728123 # number of demand (read+write) MSHR miss cycles 1072system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 132296988623 # number of overall MSHR miss cycles 1073system.cpu0.dcache.overall_mshr_miss_latency::total 132296988623 # number of overall MSHR miss cycles 1074system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6062914000 # number of ReadReq MSHR uncacheable cycles 1075system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6062914000 # number of ReadReq MSHR uncacheable cycles 1076system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6062914000 # number of overall MSHR uncacheable cycles 1077system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6062914000 # number of overall MSHR uncacheable cycles 1078system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.026789 # mshr miss rate for ReadReq accesses 1079system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026789 # mshr miss rate for ReadReq accesses 1080system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019423 # mshr miss rate for WriteReq accesses 1081system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019423 # mshr miss rate for WriteReq accesses 1082system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.767572 # mshr miss rate for SoftPFReq accesses 1083system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.767572 # mshr miss rate for SoftPFReq accesses 1084system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.807046 # mshr miss rate for WriteLineReq accesses 1085system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.807046 # mshr miss rate for WriteLineReq accesses 1086system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064917 # mshr miss rate for LoadLockedReq accesses 1087system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064917 # mshr miss rate for LoadLockedReq accesses 1088system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.092636 # mshr miss rate for StoreCondReq accesses 1089system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.092636 # mshr miss rate for StoreCondReq accesses 1090system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027774 # mshr miss rate for demand accesses 1091system.cpu0.dcache.demand_mshr_miss_rate::total 0.027774 # mshr miss rate for demand accesses 1092system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031270 # mshr miss rate for overall accesses 1093system.cpu0.dcache.overall_mshr_miss_rate::total 0.031270 # mshr miss rate for overall accesses 1094system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14614.940969 # average ReadReq mshr miss latency 1095system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14614.940969 # average ReadReq mshr miss latency 1096system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21457.831670 # average WriteReq mshr miss latency 1097system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21457.831670 # average WriteReq mshr miss latency 1098system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22415.218592 # average SoftPFReq mshr miss latency 1099system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22415.218592 # average SoftPFReq mshr miss latency 1100system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 36871.428973 # average WriteLineReq mshr miss latency 1101system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 36871.428973 # average WriteLineReq mshr miss latency 1102system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13712.172875 # average LoadLockedReq mshr miss latency 1103system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13712.172875 # average LoadLockedReq mshr miss latency 1104system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24144.005307 # average StoreCondReq mshr miss latency 1105system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24144.005307 # average StoreCondReq mshr miss latency 1106system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1107system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1108system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19624.706891 # average overall mshr miss latency 1109system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19624.706891 # average overall mshr miss latency 1110system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19948.426733 # average overall mshr miss latency 1111system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19948.426733 # average overall mshr miss latency 1112system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193796.196260 # average ReadReq mshr uncacheable latency 1113system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193796.196260 # average ReadReq mshr uncacheable latency 1114system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97407.162251 # average overall mshr uncacheable latency 1115system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 97407.162251 # average overall mshr uncacheable latency 1116system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 1117system.cpu0.icache.tags.replacements 6234341 # number of replacements 1118system.cpu0.icache.tags.tagsinuse 511.962382 # Cycle average of tags in use 1119system.cpu0.icache.tags.total_refs 276007197 # Total number of references to valid blocks. 1120system.cpu0.icache.tags.sampled_refs 6234853 # Sample count of references to valid blocks. 1121system.cpu0.icache.tags.avg_refs 44.268437 # Average number of references to valid blocks. 1122system.cpu0.icache.tags.warmup_cycle 12884658000 # Cycle when the warmup percentage was hit. 1123system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.962382 # Average occupied blocks per requestor 1124system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999927 # Average percentage of cache occupancy 1125system.cpu0.icache.tags.occ_percent::total 0.999927 # Average percentage of cache occupancy 1126system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1127system.cpu0.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id 1128system.cpu0.icache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id 1129system.cpu0.icache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id 1130system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1131system.cpu0.icache.tags.tag_accesses 571449747 # Number of tag accesses 1132system.cpu0.icache.tags.data_accesses 571449747 # Number of data accesses 1133system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 1134system.cpu0.icache.ReadReq_hits::cpu0.inst 276007197 # number of ReadReq hits 1135system.cpu0.icache.ReadReq_hits::total 276007197 # number of ReadReq hits 1136system.cpu0.icache.demand_hits::cpu0.inst 276007197 # number of demand (read+write) hits 1137system.cpu0.icache.demand_hits::total 276007197 # number of demand (read+write) hits 1138system.cpu0.icache.overall_hits::cpu0.inst 276007197 # number of overall hits 1139system.cpu0.icache.overall_hits::total 276007197 # number of overall hits 1140system.cpu0.icache.ReadReq_misses::cpu0.inst 6600102 # number of ReadReq misses 1141system.cpu0.icache.ReadReq_misses::total 6600102 # number of ReadReq misses 1142system.cpu0.icache.demand_misses::cpu0.inst 6600102 # number of demand (read+write) misses 1143system.cpu0.icache.demand_misses::total 6600102 # number of demand (read+write) misses 1144system.cpu0.icache.overall_misses::cpu0.inst 6600102 # number of overall misses 1145system.cpu0.icache.overall_misses::total 6600102 # number of overall misses 1146system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 71550800576 # number of ReadReq miss cycles 1147system.cpu0.icache.ReadReq_miss_latency::total 71550800576 # number of ReadReq miss cycles 1148system.cpu0.icache.demand_miss_latency::cpu0.inst 71550800576 # number of demand (read+write) miss cycles 1149system.cpu0.icache.demand_miss_latency::total 71550800576 # number of demand (read+write) miss cycles 1150system.cpu0.icache.overall_miss_latency::cpu0.inst 71550800576 # number of overall miss cycles 1151system.cpu0.icache.overall_miss_latency::total 71550800576 # number of overall miss cycles 1152system.cpu0.icache.ReadReq_accesses::cpu0.inst 282607299 # number of ReadReq accesses(hits+misses) 1153system.cpu0.icache.ReadReq_accesses::total 282607299 # number of ReadReq accesses(hits+misses) 1154system.cpu0.icache.demand_accesses::cpu0.inst 282607299 # number of demand (read+write) accesses 1155system.cpu0.icache.demand_accesses::total 282607299 # number of demand (read+write) accesses 1156system.cpu0.icache.overall_accesses::cpu0.inst 282607299 # number of overall (read+write) accesses 1157system.cpu0.icache.overall_accesses::total 282607299 # number of overall (read+write) accesses 1158system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.023354 # miss rate for ReadReq accesses 1159system.cpu0.icache.ReadReq_miss_rate::total 0.023354 # miss rate for ReadReq accesses 1160system.cpu0.icache.demand_miss_rate::cpu0.inst 0.023354 # miss rate for demand accesses 1161system.cpu0.icache.demand_miss_rate::total 0.023354 # miss rate for demand accesses 1162system.cpu0.icache.overall_miss_rate::cpu0.inst 0.023354 # miss rate for overall accesses 1163system.cpu0.icache.overall_miss_rate::total 0.023354 # miss rate for overall accesses 1164system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10840.862850 # average ReadReq miss latency 1165system.cpu0.icache.ReadReq_avg_miss_latency::total 10840.862850 # average ReadReq miss latency 1166system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10840.862850 # average overall miss latency 1167system.cpu0.icache.demand_avg_miss_latency::total 10840.862850 # average overall miss latency 1168system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10840.862850 # average overall miss latency 1169system.cpu0.icache.overall_avg_miss_latency::total 10840.862850 # average overall miss latency 1170system.cpu0.icache.blocked_cycles::no_mshrs 10420482 # number of cycles access was blocked 1171system.cpu0.icache.blocked_cycles::no_targets 1138 # number of cycles access was blocked 1172system.cpu0.icache.blocked::no_mshrs 752268 # number of cycles access was blocked 1173system.cpu0.icache.blocked::no_targets 11 # number of cycles access was blocked 1174system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.852087 # average number of cycles each access was blocked 1175system.cpu0.icache.avg_blocked_cycles::no_targets 103.454545 # average number of cycles each access was blocked 1176system.cpu0.icache.writebacks::writebacks 6234341 # number of writebacks 1177system.cpu0.icache.writebacks::total 6234341 # number of writebacks 1178system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 364953 # number of ReadReq MSHR hits 1179system.cpu0.icache.ReadReq_mshr_hits::total 364953 # number of ReadReq MSHR hits 1180system.cpu0.icache.demand_mshr_hits::cpu0.inst 364953 # number of demand (read+write) MSHR hits 1181system.cpu0.icache.demand_mshr_hits::total 364953 # number of demand (read+write) MSHR hits 1182system.cpu0.icache.overall_mshr_hits::cpu0.inst 364953 # number of overall MSHR hits 1183system.cpu0.icache.overall_mshr_hits::total 364953 # number of overall MSHR hits 1184system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6235149 # number of ReadReq MSHR misses 1185system.cpu0.icache.ReadReq_mshr_misses::total 6235149 # number of ReadReq MSHR misses 1186system.cpu0.icache.demand_mshr_misses::cpu0.inst 6235149 # number of demand (read+write) MSHR misses 1187system.cpu0.icache.demand_mshr_misses::total 6235149 # number of demand (read+write) MSHR misses 1188system.cpu0.icache.overall_mshr_misses::cpu0.inst 6235149 # number of overall MSHR misses 1189system.cpu0.icache.overall_mshr_misses::total 6235149 # number of overall MSHR misses 1190system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable 1191system.cpu0.icache.ReadReq_mshr_uncacheable::total 21293 # number of ReadReq MSHR uncacheable 1192system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses 1193system.cpu0.icache.overall_mshr_uncacheable_misses::total 21293 # number of overall MSHR uncacheable misses 1194system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 64720811973 # number of ReadReq MSHR miss cycles 1195system.cpu0.icache.ReadReq_mshr_miss_latency::total 64720811973 # number of ReadReq MSHR miss cycles 1196system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 64720811973 # number of demand (read+write) MSHR miss cycles 1197system.cpu0.icache.demand_mshr_miss_latency::total 64720811973 # number of demand (read+write) MSHR miss cycles 1198system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 64720811973 # number of overall MSHR miss cycles 1199system.cpu0.icache.overall_mshr_miss_latency::total 64720811973 # number of overall MSHR miss cycles 1200system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1885677498 # number of ReadReq MSHR uncacheable cycles 1201system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1885677498 # number of ReadReq MSHR uncacheable cycles 1202system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1885677498 # number of overall MSHR uncacheable cycles 1203system.cpu0.icache.overall_mshr_uncacheable_latency::total 1885677498 # number of overall MSHR uncacheable cycles 1204system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.022063 # mshr miss rate for ReadReq accesses 1205system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.022063 # mshr miss rate for ReadReq accesses 1206system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.022063 # mshr miss rate for demand accesses 1207system.cpu0.icache.demand_mshr_miss_rate::total 0.022063 # mshr miss rate for demand accesses 1208system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.022063 # mshr miss rate for overall accesses 1209system.cpu0.icache.overall_mshr_miss_rate::total 0.022063 # mshr miss rate for overall accesses 1210system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10379.994443 # average ReadReq mshr miss latency 1211system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10379.994443 # average ReadReq mshr miss latency 1212system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10379.994443 # average overall mshr miss latency 1213system.cpu0.icache.demand_avg_mshr_miss_latency::total 10379.994443 # average overall mshr miss latency 1214system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10379.994443 # average overall mshr miss latency 1215system.cpu0.icache.overall_avg_mshr_miss_latency::total 10379.994443 # average overall mshr miss latency 1216system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average ReadReq mshr uncacheable latency 1217system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88558.563753 # average ReadReq mshr uncacheable latency 1218system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average overall mshr uncacheable latency 1219system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88558.563753 # average overall mshr uncacheable latency 1220system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 1221system.cpu0.l2cache.prefetcher.num_hwpf_issued 8818791 # number of hwpf issued 1222system.cpu0.l2cache.prefetcher.pfIdentified 8829534 # number of prefetch candidates identified 1223system.cpu0.l2cache.prefetcher.pfBufferHit 9675 # number of redundant prefetches already in prefetch queue 1224system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1225system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1226system.cpu0.l2cache.prefetcher.pfSpanPage 1134314 # number of prefetches not generated due to page crossing 1227system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 1228system.cpu0.l2cache.tags.replacements 2939155 # number of replacements 1229system.cpu0.l2cache.tags.tagsinuse 16147.226336 # Cycle average of tags in use 1230system.cpu0.l2cache.tags.total_refs 18219506 # Total number of references to valid blocks. 1231system.cpu0.l2cache.tags.sampled_refs 2955258 # Sample count of references to valid blocks. 1232system.cpu0.l2cache.tags.avg_refs 6.165115 # Average number of references to valid blocks. 1233system.cpu0.l2cache.tags.warmup_cycle 2212473000 # Cycle when the warmup percentage was hit. 1234system.cpu0.l2cache.tags.occ_blocks::writebacks 15244.220202 # Average occupied blocks per requestor 1235system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 58.043386 # Average occupied blocks per requestor 1236system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 62.165258 # Average occupied blocks per requestor 1237system.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.000002 # Average occupied blocks per requestor 1238system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 782.797489 # Average occupied blocks per requestor 1239system.cpu0.l2cache.tags.occ_percent::writebacks 0.930433 # Average percentage of cache occupancy 1240system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003543 # Average percentage of cache occupancy 1241system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003794 # Average percentage of cache occupancy 1242system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.000000 # Average percentage of cache occupancy 1243system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.047778 # Average percentage of cache occupancy 1244system.cpu0.l2cache.tags.occ_percent::total 0.985548 # Average percentage of cache occupancy 1245system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1151 # Occupied blocks per task id 1246system.cpu0.l2cache.tags.occ_task_id_blocks::1023 81 # Occupied blocks per task id 1247system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14871 # Occupied blocks per task id 1248system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 14 # Occupied blocks per task id 1249system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 189 # Occupied blocks per task id 1250system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 576 # Occupied blocks per task id 1251system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 372 # Occupied blocks per task id 1252system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id 1253system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 48 # Occupied blocks per task id 1254system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 14 # Occupied blocks per task id 1255system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id 1256system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id 1257system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1385 # Occupied blocks per task id 1258system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6005 # Occupied blocks per task id 1259system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4408 # Occupied blocks per task id 1260system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2945 # Occupied blocks per task id 1261system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.070251 # Percentage of cache occupancy per task id 1262system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004944 # Percentage of cache occupancy per task id 1263system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.907654 # Percentage of cache occupancy per task id 1264system.cpu0.l2cache.tags.tag_accesses 433411639 # Number of tag accesses 1265system.cpu0.l2cache.tags.data_accesses 433411639 # Number of data accesses 1266system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 1267system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 616680 # number of ReadReq hits 1268system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 198735 # number of ReadReq hits 1269system.cpu0.l2cache.ReadReq_hits::total 815415 # number of ReadReq hits 1270system.cpu0.l2cache.WritebackDirty_hits::writebacks 4206029 # number of WritebackDirty hits 1271system.cpu0.l2cache.WritebackDirty_hits::total 4206029 # number of WritebackDirty hits 1272system.cpu0.l2cache.WritebackClean_hits::writebacks 8435953 # number of WritebackClean hits 1273system.cpu0.l2cache.WritebackClean_hits::total 8435953 # number of WritebackClean hits 1274system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 888 # number of UpgradeReq hits 1275system.cpu0.l2cache.UpgradeReq_hits::total 888 # number of UpgradeReq hits 1276system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2 # number of SCUpgradeReq hits 1277system.cpu0.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits 1278system.cpu0.l2cache.ReadExReq_hits::cpu0.data 1016467 # number of ReadExReq hits 1279system.cpu0.l2cache.ReadExReq_hits::total 1016467 # number of ReadExReq hits 1280system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5621992 # number of ReadCleanReq hits 1281system.cpu0.l2cache.ReadCleanReq_hits::total 5621992 # number of ReadCleanReq hits 1282system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3255070 # number of ReadSharedReq hits 1283system.cpu0.l2cache.ReadSharedReq_hits::total 3255070 # number of ReadSharedReq hits 1284system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 189931 # number of InvalidateReq hits 1285system.cpu0.l2cache.InvalidateReq_hits::total 189931 # number of InvalidateReq hits 1286system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 616680 # number of demand (read+write) hits 1287system.cpu0.l2cache.demand_hits::cpu0.itb.walker 198735 # number of demand (read+write) hits 1288system.cpu0.l2cache.demand_hits::cpu0.inst 5621992 # number of demand (read+write) hits 1289system.cpu0.l2cache.demand_hits::cpu0.data 4271537 # number of demand (read+write) hits 1290system.cpu0.l2cache.demand_hits::total 10708944 # number of demand (read+write) hits 1291system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 616680 # number of overall hits 1292system.cpu0.l2cache.overall_hits::cpu0.itb.walker 198735 # number of overall hits 1293system.cpu0.l2cache.overall_hits::cpu0.inst 5621992 # number of overall hits 1294system.cpu0.l2cache.overall_hits::cpu0.data 4271537 # number of overall hits 1295system.cpu0.l2cache.overall_hits::total 10708944 # number of overall hits 1296system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 13303 # number of ReadReq misses 1297system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10046 # number of ReadReq misses 1298system.cpu0.l2cache.ReadReq_misses::total 23349 # number of ReadReq misses 1299system.cpu0.l2cache.WritebackDirty_misses::writebacks 5 # number of WritebackDirty misses 1300system.cpu0.l2cache.WritebackDirty_misses::total 5 # number of WritebackDirty misses 1301system.cpu0.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses 1302system.cpu0.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses 1303system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 270883 # number of UpgradeReq misses 1304system.cpu0.l2cache.UpgradeReq_misses::total 270883 # number of UpgradeReq misses 1305system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 195959 # number of SCUpgradeReq misses 1306system.cpu0.l2cache.SCUpgradeReq_misses::total 195959 # number of SCUpgradeReq misses 1307system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses 1308system.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses 1309system.cpu0.l2cache.ReadExReq_misses::cpu0.data 300699 # number of ReadExReq misses 1310system.cpu0.l2cache.ReadExReq_misses::total 300699 # number of ReadExReq misses 1311system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 612692 # number of ReadCleanReq misses 1312system.cpu0.l2cache.ReadCleanReq_misses::total 612692 # number of ReadCleanReq misses 1313system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1101459 # number of ReadSharedReq misses 1314system.cpu0.l2cache.ReadSharedReq_misses::total 1101459 # number of ReadSharedReq misses 1315system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 642386 # number of InvalidateReq misses 1316system.cpu0.l2cache.InvalidateReq_misses::total 642386 # number of InvalidateReq misses 1317system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 13303 # number of demand (read+write) misses 1318system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10046 # number of demand (read+write) misses 1319system.cpu0.l2cache.demand_misses::cpu0.inst 612692 # number of demand (read+write) misses 1320system.cpu0.l2cache.demand_misses::cpu0.data 1402158 # number of demand (read+write) misses 1321system.cpu0.l2cache.demand_misses::total 2038199 # number of demand (read+write) misses 1322system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 13303 # number of overall misses 1323system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10046 # number of overall misses 1324system.cpu0.l2cache.overall_misses::cpu0.inst 612692 # number of overall misses 1325system.cpu0.l2cache.overall_misses::cpu0.data 1402158 # number of overall misses 1326system.cpu0.l2cache.overall_misses::total 2038199 # number of overall misses 1327system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 571435000 # number of ReadReq miss cycles 1328system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 478645000 # number of ReadReq miss cycles 1329system.cpu0.l2cache.ReadReq_miss_latency::total 1050080000 # number of ReadReq miss cycles 1330system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2108781500 # number of UpgradeReq miss cycles 1331system.cpu0.l2cache.UpgradeReq_miss_latency::total 2108781500 # number of UpgradeReq miss cycles 1332system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1542924500 # number of SCUpgradeReq miss cycles 1333system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1542924500 # number of SCUpgradeReq miss cycles 1334system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2975499 # number of SCUpgradeFailReq miss cycles 1335system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2975499 # number of SCUpgradeFailReq miss cycles 1336system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 16979785000 # number of ReadExReq miss cycles 1337system.cpu0.l2cache.ReadExReq_miss_latency::total 16979785000 # number of ReadExReq miss cycles 1338system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 21306863000 # number of ReadCleanReq miss cycles 1339system.cpu0.l2cache.ReadCleanReq_miss_latency::total 21306863000 # number of ReadCleanReq miss cycles 1340system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 41322461986 # number of ReadSharedReq miss cycles 1341system.cpu0.l2cache.ReadSharedReq_miss_latency::total 41322461986 # number of ReadSharedReq miss cycles 1342system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 313374000 # number of InvalidateReq miss cycles 1343system.cpu0.l2cache.InvalidateReq_miss_latency::total 313374000 # number of InvalidateReq miss cycles 1344system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 571435000 # number of demand (read+write) miss cycles 1345system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 478645000 # number of demand (read+write) miss cycles 1346system.cpu0.l2cache.demand_miss_latency::cpu0.inst 21306863000 # number of demand (read+write) miss cycles 1347system.cpu0.l2cache.demand_miss_latency::cpu0.data 58302246986 # number of demand (read+write) miss cycles 1348system.cpu0.l2cache.demand_miss_latency::total 80659189986 # number of demand (read+write) miss cycles 1349system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 571435000 # number of overall miss cycles 1350system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 478645000 # number of overall miss cycles 1351system.cpu0.l2cache.overall_miss_latency::cpu0.inst 21306863000 # number of overall miss cycles 1352system.cpu0.l2cache.overall_miss_latency::cpu0.data 58302246986 # number of overall miss cycles 1353system.cpu0.l2cache.overall_miss_latency::total 80659189986 # number of overall miss cycles 1354system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 629983 # number of ReadReq accesses(hits+misses) 1355system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 208781 # number of ReadReq accesses(hits+misses) 1356system.cpu0.l2cache.ReadReq_accesses::total 838764 # number of ReadReq accesses(hits+misses) 1357system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4206034 # number of WritebackDirty accesses(hits+misses) 1358system.cpu0.l2cache.WritebackDirty_accesses::total 4206034 # number of WritebackDirty accesses(hits+misses) 1359system.cpu0.l2cache.WritebackClean_accesses::writebacks 8435954 # number of WritebackClean accesses(hits+misses) 1360system.cpu0.l2cache.WritebackClean_accesses::total 8435954 # number of WritebackClean accesses(hits+misses) 1361system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 271771 # number of UpgradeReq accesses(hits+misses) 1362system.cpu0.l2cache.UpgradeReq_accesses::total 271771 # number of UpgradeReq accesses(hits+misses) 1363system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 195961 # number of SCUpgradeReq accesses(hits+misses) 1364system.cpu0.l2cache.SCUpgradeReq_accesses::total 195961 # number of SCUpgradeReq accesses(hits+misses) 1365system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 4 # number of SCUpgradeFailReq accesses(hits+misses) 1366system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) 1367system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1317166 # number of ReadExReq accesses(hits+misses) 1368system.cpu0.l2cache.ReadExReq_accesses::total 1317166 # number of ReadExReq accesses(hits+misses) 1369system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 6234684 # number of ReadCleanReq accesses(hits+misses) 1370system.cpu0.l2cache.ReadCleanReq_accesses::total 6234684 # number of ReadCleanReq accesses(hits+misses) 1371system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4356529 # number of ReadSharedReq accesses(hits+misses) 1372system.cpu0.l2cache.ReadSharedReq_accesses::total 4356529 # number of ReadSharedReq accesses(hits+misses) 1373system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 832317 # number of InvalidateReq accesses(hits+misses) 1374system.cpu0.l2cache.InvalidateReq_accesses::total 832317 # number of InvalidateReq accesses(hits+misses) 1375system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 629983 # number of demand (read+write) accesses 1376system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 208781 # number of demand (read+write) accesses 1377system.cpu0.l2cache.demand_accesses::cpu0.inst 6234684 # number of demand (read+write) accesses 1378system.cpu0.l2cache.demand_accesses::cpu0.data 5673695 # number of demand (read+write) accesses 1379system.cpu0.l2cache.demand_accesses::total 12747143 # number of demand (read+write) accesses 1380system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 629983 # number of overall (read+write) accesses 1381system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 208781 # number of overall (read+write) accesses 1382system.cpu0.l2cache.overall_accesses::cpu0.inst 6234684 # number of overall (read+write) accesses 1383system.cpu0.l2cache.overall_accesses::cpu0.data 5673695 # number of overall (read+write) accesses 1384system.cpu0.l2cache.overall_accesses::total 12747143 # number of overall (read+write) accesses 1385system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.021116 # miss rate for ReadReq accesses 1386system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.048117 # miss rate for ReadReq accesses 1387system.cpu0.l2cache.ReadReq_miss_rate::total 0.027837 # miss rate for ReadReq accesses 1388system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses 1389system.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses 1390system.cpu0.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses 1391system.cpu0.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses 1392system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.996733 # miss rate for UpgradeReq accesses 1393system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.996733 # miss rate for UpgradeReq accesses 1394system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999990 # miss rate for SCUpgradeReq accesses 1395system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999990 # miss rate for SCUpgradeReq accesses 1396system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1397system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1398system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.228292 # miss rate for ReadExReq accesses 1399system.cpu0.l2cache.ReadExReq_miss_rate::total 0.228292 # miss rate for ReadExReq accesses 1400system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.098272 # miss rate for ReadCleanReq accesses 1401system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.098272 # miss rate for ReadCleanReq accesses 1402system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.252829 # miss rate for ReadSharedReq accesses 1403system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.252829 # miss rate for ReadSharedReq accesses 1404system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.771804 # miss rate for InvalidateReq accesses 1405system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.771804 # miss rate for InvalidateReq accesses 1406system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.021116 # miss rate for demand accesses 1407system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.048117 # miss rate for demand accesses 1408system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.098272 # miss rate for demand accesses 1409system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.247133 # miss rate for demand accesses 1410system.cpu0.l2cache.demand_miss_rate::total 0.159895 # miss rate for demand accesses 1411system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.021116 # miss rate for overall accesses 1412system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.048117 # miss rate for overall accesses 1413system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.098272 # miss rate for overall accesses 1414system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.247133 # miss rate for overall accesses 1415system.cpu0.l2cache.overall_miss_rate::total 0.159895 # miss rate for overall accesses 1416system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 42955.348418 # average ReadReq miss latency 1417system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 47645.331475 # average ReadReq miss latency 1418system.cpu0.l2cache.ReadReq_avg_miss_latency::total 44973.232258 # average ReadReq miss latency 1419system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 7784.842533 # average UpgradeReq miss latency 1420system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 7784.842533 # average UpgradeReq miss latency 1421system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 7873.710827 # average SCUpgradeReq miss latency 1422system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 7873.710827 # average SCUpgradeReq miss latency 1423system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 743874.750000 # average SCUpgradeFailReq miss latency 1424system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 743874.750000 # average SCUpgradeFailReq miss latency 1425system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 56467.713561 # average ReadExReq miss latency 1426system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 56467.713561 # average ReadExReq miss latency 1427system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 34775.813949 # average ReadCleanReq miss latency 1428system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 34775.813949 # average ReadCleanReq miss latency 1429system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 37516.114523 # average ReadSharedReq miss latency 1430system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 37516.114523 # average ReadSharedReq miss latency 1431system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 487.828191 # average InvalidateReq miss latency 1432system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 487.828191 # average InvalidateReq miss latency 1433system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 42955.348418 # average overall miss latency 1434system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 47645.331475 # average overall miss latency 1435system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34775.813949 # average overall miss latency 1436system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 41580.368964 # average overall miss latency 1437system.cpu0.l2cache.demand_avg_miss_latency::total 39573.756040 # average overall miss latency 1438system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 42955.348418 # average overall miss latency 1439system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 47645.331475 # average overall miss latency 1440system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34775.813949 # average overall miss latency 1441system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 41580.368964 # average overall miss latency 1442system.cpu0.l2cache.overall_avg_miss_latency::total 39573.756040 # average overall miss latency 1443system.cpu0.l2cache.blocked_cycles::no_mshrs 834 # number of cycles access was blocked 1444system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1445system.cpu0.l2cache.blocked::no_mshrs 18 # number of cycles access was blocked 1446system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1447system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 46.333333 # average number of cycles each access was blocked 1448system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1449system.cpu0.l2cache.unused_prefetches 51227 # number of HardPF blocks evicted w/o reference 1450system.cpu0.l2cache.writebacks::writebacks 1850658 # number of writebacks 1451system.cpu0.l2cache.writebacks::total 1850658 # number of writebacks 1452system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 4 # number of ReadReq MSHR hits 1453system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 8 # number of ReadReq MSHR hits 1454system.cpu0.l2cache.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits 1455system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 18696 # number of ReadExReq MSHR hits 1456system.cpu0.l2cache.ReadExReq_mshr_hits::total 18696 # number of ReadExReq MSHR hits 1457system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 3 # number of ReadCleanReq MSHR hits 1458system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits 1459system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 5802 # number of ReadSharedReq MSHR hits 1460system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 5802 # number of ReadSharedReq MSHR hits 1461system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 11 # number of InvalidateReq MSHR hits 1462system.cpu0.l2cache.InvalidateReq_mshr_hits::total 11 # number of InvalidateReq MSHR hits 1463system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 4 # number of demand (read+write) MSHR hits 1464system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 8 # number of demand (read+write) MSHR hits 1465system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits 1466system.cpu0.l2cache.demand_mshr_hits::cpu0.data 24498 # number of demand (read+write) MSHR hits 1467system.cpu0.l2cache.demand_mshr_hits::total 24513 # number of demand (read+write) MSHR hits 1468system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 4 # number of overall MSHR hits 1469system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 8 # number of overall MSHR hits 1470system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits 1471system.cpu0.l2cache.overall_mshr_hits::cpu0.data 24498 # number of overall MSHR hits 1472system.cpu0.l2cache.overall_mshr_hits::total 24513 # number of overall MSHR hits 1473system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 13299 # number of ReadReq MSHR misses 1474system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 10038 # number of ReadReq MSHR misses 1475system.cpu0.l2cache.ReadReq_mshr_misses::total 23337 # number of ReadReq MSHR misses 1476system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 5 # number of WritebackDirty MSHR misses 1477system.cpu0.l2cache.WritebackDirty_mshr_misses::total 5 # number of WritebackDirty MSHR misses 1478system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses 1479system.cpu0.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses 1480system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 927770 # number of HardPFReq MSHR misses 1481system.cpu0.l2cache.HardPFReq_mshr_misses::total 927770 # number of HardPFReq MSHR misses 1482system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 270883 # number of UpgradeReq MSHR misses 1483system.cpu0.l2cache.UpgradeReq_mshr_misses::total 270883 # number of UpgradeReq MSHR misses 1484system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 195959 # number of SCUpgradeReq MSHR misses 1485system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 195959 # number of SCUpgradeReq MSHR misses 1486system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 4 # number of SCUpgradeFailReq MSHR misses 1487system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses 1488system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 282003 # number of ReadExReq MSHR misses 1489system.cpu0.l2cache.ReadExReq_mshr_misses::total 282003 # number of ReadExReq MSHR misses 1490system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 612689 # number of ReadCleanReq MSHR misses 1491system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 612689 # number of ReadCleanReq MSHR misses 1492system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1095657 # number of ReadSharedReq MSHR misses 1493system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1095657 # number of ReadSharedReq MSHR misses 1494system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 642375 # number of InvalidateReq MSHR misses 1495system.cpu0.l2cache.InvalidateReq_mshr_misses::total 642375 # number of InvalidateReq MSHR misses 1496system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 13299 # number of demand (read+write) MSHR misses 1497system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 10038 # number of demand (read+write) MSHR misses 1498system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 612689 # number of demand (read+write) MSHR misses 1499system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1377660 # number of demand (read+write) MSHR misses 1500system.cpu0.l2cache.demand_mshr_misses::total 2013686 # number of demand (read+write) MSHR misses 1501system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 13299 # number of overall MSHR misses 1502system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 10038 # number of overall MSHR misses 1503system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 612689 # number of overall MSHR misses 1504system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1377660 # number of overall MSHR misses 1505system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 927770 # number of overall MSHR misses 1506system.cpu0.l2cache.overall_mshr_misses::total 2941456 # number of overall MSHR misses 1507system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable 1508system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31285 # number of ReadReq MSHR uncacheable 1509system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 52578 # number of ReadReq MSHR uncacheable 1510system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 30958 # number of WriteReq MSHR uncacheable 1511system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 30958 # number of WriteReq MSHR uncacheable 1512system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses 1513system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 62243 # number of overall MSHR uncacheable misses 1514system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 83536 # number of overall MSHR uncacheable misses 1515system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 491572000 # number of ReadReq MSHR miss cycles 1516system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 418271000 # number of ReadReq MSHR miss cycles 1517system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 909843000 # number of ReadReq MSHR miss cycles 1518system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 52503366783 # number of HardPFReq MSHR miss cycles 1519system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 52503366783 # number of HardPFReq MSHR miss cycles 1520system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 5568283996 # number of UpgradeReq MSHR miss cycles 1521system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 5568283996 # number of UpgradeReq MSHR miss cycles 1522system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3258361996 # number of SCUpgradeReq MSHR miss cycles 1523system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3258361996 # number of SCUpgradeReq MSHR miss cycles 1524system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2621499 # number of SCUpgradeFailReq MSHR miss cycles 1525system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2621499 # number of SCUpgradeFailReq MSHR miss cycles 1526system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 12639099000 # number of ReadExReq MSHR miss cycles 1527system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 12639099000 # number of ReadExReq MSHR miss cycles 1528system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 17630608000 # number of ReadCleanReq MSHR miss cycles 1529system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 17630608000 # number of ReadCleanReq MSHR miss cycles 1530system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 34375466986 # number of ReadSharedReq MSHR miss cycles 1531system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 34375466986 # number of ReadSharedReq MSHR miss cycles 1532system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 23514926497 # number of InvalidateReq MSHR miss cycles 1533system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 23514926497 # number of InvalidateReq MSHR miss cycles 1534system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 491572000 # number of demand (read+write) MSHR miss cycles 1535system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 418271000 # number of demand (read+write) MSHR miss cycles 1536system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 17630608000 # number of demand (read+write) MSHR miss cycles 1537system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 47014565986 # number of demand (read+write) MSHR miss cycles 1538system.cpu0.l2cache.demand_mshr_miss_latency::total 65555016986 # number of demand (read+write) MSHR miss cycles 1539system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 491572000 # number of overall MSHR miss cycles 1540system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 418271000 # number of overall MSHR miss cycles 1541system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 17630608000 # number of overall MSHR miss cycles 1542system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 47014565986 # number of overall MSHR miss cycles 1543system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 52503366783 # number of overall MSHR miss cycles 1544system.cpu0.l2cache.overall_mshr_miss_latency::total 118058383769 # number of overall MSHR miss cycles 1545system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1725979000 # number of ReadReq MSHR uncacheable cycles 1546system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5812178000 # number of ReadReq MSHR uncacheable cycles 1547system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7538157000 # number of ReadReq MSHR uncacheable cycles 1548system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1725979000 # number of overall MSHR uncacheable cycles 1549system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5812178000 # number of overall MSHR uncacheable cycles 1550system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7538157000 # number of overall MSHR uncacheable cycles 1551system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021110 # mshr miss rate for ReadReq accesses 1552system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.048079 # mshr miss rate for ReadReq accesses 1553system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.027823 # mshr miss rate for ReadReq accesses 1554system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses 1555system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses 1556system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses 1557system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses 1558system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1559system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1560system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.996733 # mshr miss rate for UpgradeReq accesses 1561system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.996733 # mshr miss rate for UpgradeReq accesses 1562system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999990 # mshr miss rate for SCUpgradeReq accesses 1563system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999990 # mshr miss rate for SCUpgradeReq accesses 1564system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1565system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1566system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.214098 # mshr miss rate for ReadExReq accesses 1567system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.214098 # mshr miss rate for ReadExReq accesses 1568system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.098271 # mshr miss rate for ReadCleanReq accesses 1569system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.098271 # mshr miss rate for ReadCleanReq accesses 1570system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.251498 # mshr miss rate for ReadSharedReq accesses 1571system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.251498 # mshr miss rate for ReadSharedReq accesses 1572system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.771791 # mshr miss rate for InvalidateReq accesses 1573system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.771791 # mshr miss rate for InvalidateReq accesses 1574system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021110 # mshr miss rate for demand accesses 1575system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.048079 # mshr miss rate for demand accesses 1576system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.098271 # mshr miss rate for demand accesses 1577system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.242815 # mshr miss rate for demand accesses 1578system.cpu0.l2cache.demand_mshr_miss_rate::total 0.157972 # mshr miss rate for demand accesses 1579system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021110 # mshr miss rate for overall accesses 1580system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.048079 # mshr miss rate for overall accesses 1581system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.098271 # mshr miss rate for overall accesses 1582system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.242815 # mshr miss rate for overall accesses 1583system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1584system.cpu0.l2cache.overall_mshr_miss_rate::total 0.230754 # mshr miss rate for overall accesses 1585system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 36963.079931 # average ReadReq mshr miss latency 1586system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 41668.758717 # average ReadReq mshr miss latency 1587system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38987.144877 # average ReadReq mshr miss latency 1588system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56590.929630 # average HardPFReq mshr miss latency 1589system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56590.929630 # average HardPFReq mshr miss latency 1590system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20556.048168 # average UpgradeReq mshr miss latency 1591system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20556.048168 # average UpgradeReq mshr miss latency 1592system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16627.774157 # average SCUpgradeReq mshr miss latency 1593system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16627.774157 # average SCUpgradeReq mshr miss latency 1594system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 655374.750000 # average SCUpgradeFailReq mshr miss latency 1595system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 655374.750000 # average SCUpgradeFailReq mshr miss latency 1596system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 44819.023202 # average ReadExReq mshr miss latency 1597system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 44819.023202 # average ReadExReq mshr miss latency 1598system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28775.786737 # average ReadCleanReq mshr miss latency 1599system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28775.786737 # average ReadCleanReq mshr miss latency 1600system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31374.295958 # average ReadSharedReq mshr miss latency 1601system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31374.295958 # average ReadSharedReq mshr miss latency 1602system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 36606.229223 # average InvalidateReq mshr miss latency 1603system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 36606.229223 # average InvalidateReq mshr miss latency 1604system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 36963.079931 # average overall mshr miss latency 1605system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 41668.758717 # average overall mshr miss latency 1606system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28775.786737 # average overall mshr miss latency 1607system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34126.392569 # average overall mshr miss latency 1608system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32554.736432 # average overall mshr miss latency 1609system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 36963.079931 # average overall mshr miss latency 1610system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 41668.758717 # average overall mshr miss latency 1611system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28775.786737 # average overall mshr miss latency 1612system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34126.392569 # average overall mshr miss latency 1613system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56590.929630 # average overall mshr miss latency 1614system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 40136.035953 # average overall mshr miss latency 1615system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81058.516883 # average ReadReq mshr uncacheable latency 1616system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185781.620585 # average ReadReq mshr uncacheable latency 1617system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 143370.934611 # average ReadReq mshr uncacheable latency 1618system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81058.516883 # average overall mshr uncacheable latency 1619system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 93378.821715 # average overall mshr uncacheable latency 1620system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 90238.424152 # average overall mshr uncacheable latency 1621system.cpu0.toL2Bus.snoop_filter.tot_requests 26220064 # Total number of requests made to the snoop filter. 1622system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13479100 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1623system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2657 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1624system.cpu0.toL2Bus.snoop_filter.tot_snoops 2182451 # Total number of snoops made to the snoop filter. 1625system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2181920 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1626system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 531 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1627system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 1628system.cpu0.toL2Bus.trans_dist::ReadReq 979416 # Transaction distribution 1629system.cpu0.toL2Bus.trans_dist::ReadResp 11666319 # Transaction distribution 1630system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution 1631system.cpu0.toL2Bus.trans_dist::WriteReq 30958 # Transaction distribution 1632system.cpu0.toL2Bus.trans_dist::WriteResp 30958 # Transaction distribution 1633system.cpu0.toL2Bus.trans_dist::WritebackDirty 6060800 # Transaction distribution 1634system.cpu0.toL2Bus.trans_dist::WritebackClean 8438347 # Transaction distribution 1635system.cpu0.toL2Bus.trans_dist::CleanEvict 2860883 # Transaction distribution 1636system.cpu0.toL2Bus.trans_dist::HardPFReq 1184490 # Transaction distribution 1637system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 1638system.cpu0.toL2Bus.trans_dist::UpgradeReq 488552 # Transaction distribution 1639system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 348527 # Transaction distribution 1640system.cpu0.toL2Bus.trans_dist::UpgradeResp 533031 # Transaction distribution 1641system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 69 # Transaction distribution 1642system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 124 # Transaction distribution 1643system.cpu0.toL2Bus.trans_dist::ReadExReq 1347603 # Transaction distribution 1644system.cpu0.toL2Bus.trans_dist::ReadExResp 1325056 # Transaction distribution 1645system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6235149 # Transaction distribution 1646system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5307790 # Transaction distribution 1647system.cpu0.toL2Bus.trans_dist::InvalidateReq 891051 # Transaction distribution 1648system.cpu0.toL2Bus.trans_dist::InvalidateResp 832317 # Transaction distribution 1649system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18746760 # Packet count per connected master and slave (bytes) 1650system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20650560 # Packet count per connected master and slave (bytes) 1651system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 436622 # Packet count per connected master and slave (bytes) 1652system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1328978 # Packet count per connected master and slave (bytes) 1653system.cpu0.toL2Bus.pkt_count::total 41162920 # Packet count per connected master and slave (bytes) 1654system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 798358288 # Cumulative packet size per connected master and slave (bytes) 1655system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 780155262 # Cumulative packet size per connected master and slave (bytes) 1656system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1670248 # Cumulative packet size per connected master and slave (bytes) 1657system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5039864 # Cumulative packet size per connected master and slave (bytes) 1658system.cpu0.toL2Bus.pkt_size::total 1585223662 # Cumulative packet size per connected master and slave (bytes) 1659system.cpu0.toL2Bus.snoops 7567060 # Total snoops (count) 1660system.cpu0.toL2Bus.snoopTraffic 126041936 # Total snoop traffic (bytes) 1661system.cpu0.toL2Bus.snoop_fanout::samples 21529267 # Request fanout histogram 1662system.cpu0.toL2Bus.snoop_fanout::mean 0.118569 # Request fanout histogram 1663system.cpu0.toL2Bus.snoop_fanout::stdev 0.323357 # Request fanout histogram 1664system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1665system.cpu0.toL2Bus.snoop_fanout::0 18977100 88.15% 88.15% # Request fanout histogram 1666system.cpu0.toL2Bus.snoop_fanout::1 2551636 11.85% 100.00% # Request fanout histogram 1667system.cpu0.toL2Bus.snoop_fanout::2 531 0.00% 100.00% # Request fanout histogram 1668system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1669system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1670system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1671system.cpu0.toL2Bus.snoop_fanout::total 21529267 # Request fanout histogram 1672system.cpu0.toL2Bus.reqLayer0.occupancy 26091722433 # Layer occupancy (ticks) 1673system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1674system.cpu0.toL2Bus.snoopLayer0.occupancy 187623310 # Layer occupancy (ticks) 1675system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1676system.cpu0.toL2Bus.respLayer0.occupancy 9380939070 # Layer occupancy (ticks) 1677system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1678system.cpu0.toL2Bus.respLayer1.occupancy 9216328089 # Layer occupancy (ticks) 1679system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1680system.cpu0.toL2Bus.respLayer2.occupancy 228203766 # Layer occupancy (ticks) 1681system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1682system.cpu0.toL2Bus.respLayer3.occupancy 699632706 # Layer occupancy (ticks) 1683system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1684system.cpu1.branchPred.lookups 194671556 # Number of BP lookups 1685system.cpu1.branchPred.condPredicted 153305610 # Number of conditional branches predicted 1686system.cpu1.branchPred.condIncorrect 6254288 # Number of conditional branches incorrect 1687system.cpu1.branchPred.BTBLookups 157865267 # Number of BTB lookups 1688system.cpu1.branchPred.BTBHits 88709282 # Number of BTB hits 1689system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1690system.cpu1.branchPred.BTBHitPct 56.193033 # BTB Hit Percentage 1691system.cpu1.branchPred.usedRAS 16475486 # Number of times the RAS was used to get a target. 1692system.cpu1.branchPred.RASInCorrect 172497 # Number of incorrect RAS predictions. 1693system.cpu1.branchPred.indirectLookups 3896881 # Number of indirect predictor lookups. 1694system.cpu1.branchPred.indirectHits 2381021 # Number of indirect target hits. 1695system.cpu1.branchPred.indirectMisses 1515860 # Number of indirect misses. 1696system.cpu1.branchPredindirectMispredicted 389837 # Number of mispredicted indirect branches. 1697system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 1698system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1699system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1700system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1701system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1702system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1703system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1704system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1705system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1706system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1707system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1708system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1709system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1710system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1711system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1712system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1713system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1714system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1715system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1716system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1717system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1718system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1719system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1720system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1721system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1722system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1723system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1724system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1725system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1726system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1727system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 1728system.cpu1.dtb.walker.walks 533309 # Table walker walks requested 1729system.cpu1.dtb.walker.walksLong 533309 # Table walker walks initiated with long descriptors 1730system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10503 # Level at which table walker walks with long descriptors terminate 1731system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 81680 # Level at which table walker walks with long descriptors terminate 1732system.cpu1.dtb.walker.walksSquashedBefore 248509 # Table walks squashed before starting 1733system.cpu1.dtb.walker.walkWaitTime::samples 284800 # Table walker wait (enqueue to first request) latency 1734system.cpu1.dtb.walker.walkWaitTime::mean 2470.932233 # Table walker wait (enqueue to first request) latency 1735system.cpu1.dtb.walker.walkWaitTime::stdev 13518.648671 # Table walker wait (enqueue to first request) latency 1736system.cpu1.dtb.walker.walkWaitTime::0-32767 279405 98.11% 98.11% # Table walker wait (enqueue to first request) latency 1737system.cpu1.dtb.walker.walkWaitTime::32768-65535 3083 1.08% 99.19% # Table walker wait (enqueue to first request) latency 1738system.cpu1.dtb.walker.walkWaitTime::65536-98303 908 0.32% 99.51% # Table walker wait (enqueue to first request) latency 1739system.cpu1.dtb.walker.walkWaitTime::98304-131071 713 0.25% 99.76% # Table walker wait (enqueue to first request) latency 1740system.cpu1.dtb.walker.walkWaitTime::131072-163839 284 0.10% 99.86% # Table walker wait (enqueue to first request) latency 1741system.cpu1.dtb.walker.walkWaitTime::163840-196607 163 0.06% 99.91% # Table walker wait (enqueue to first request) latency 1742system.cpu1.dtb.walker.walkWaitTime::196608-229375 124 0.04% 99.96% # Table walker wait (enqueue to first request) latency 1743system.cpu1.dtb.walker.walkWaitTime::229376-262143 32 0.01% 99.97% # Table walker wait (enqueue to first request) latency 1744system.cpu1.dtb.walker.walkWaitTime::262144-294911 13 0.00% 99.97% # Table walker wait (enqueue to first request) latency 1745system.cpu1.dtb.walker.walkWaitTime::294912-327679 40 0.01% 99.99% # Table walker wait (enqueue to first request) latency 1746system.cpu1.dtb.walker.walkWaitTime::327680-360447 32 0.01% 100.00% # Table walker wait (enqueue to first request) latency 1747system.cpu1.dtb.walker.walkWaitTime::425984-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1748system.cpu1.dtb.walker.walkWaitTime::total 284800 # Table walker wait (enqueue to first request) latency 1749system.cpu1.dtb.walker.walkCompletionTime::samples 268382 # Table walker service (enqueue to completion) latency 1750system.cpu1.dtb.walker.walkCompletionTime::mean 19517.668845 # Table walker service (enqueue to completion) latency 1751system.cpu1.dtb.walker.walkCompletionTime::gmean 17136.373439 # Table walker service (enqueue to completion) latency 1752system.cpu1.dtb.walker.walkCompletionTime::stdev 13227.910444 # Table walker service (enqueue to completion) latency 1753system.cpu1.dtb.walker.walkCompletionTime::0-32767 250971 93.51% 93.51% # Table walker service (enqueue to completion) latency 1754system.cpu1.dtb.walker.walkCompletionTime::32768-65535 15361 5.72% 99.24% # Table walker service (enqueue to completion) latency 1755system.cpu1.dtb.walker.walkCompletionTime::65536-98303 757 0.28% 99.52% # Table walker service (enqueue to completion) latency 1756system.cpu1.dtb.walker.walkCompletionTime::98304-131071 835 0.31% 99.83% # Table walker service (enqueue to completion) latency 1757system.cpu1.dtb.walker.walkCompletionTime::131072-163839 87 0.03% 99.86% # Table walker service (enqueue to completion) latency 1758system.cpu1.dtb.walker.walkCompletionTime::163840-196607 116 0.04% 99.90% # Table walker service (enqueue to completion) latency 1759system.cpu1.dtb.walker.walkCompletionTime::196608-229375 116 0.04% 99.95% # Table walker service (enqueue to completion) latency 1760system.cpu1.dtb.walker.walkCompletionTime::229376-262143 51 0.02% 99.97% # Table walker service (enqueue to completion) latency 1761system.cpu1.dtb.walker.walkCompletionTime::262144-294911 29 0.01% 99.98% # Table walker service (enqueue to completion) latency 1762system.cpu1.dtb.walker.walkCompletionTime::294912-327679 31 0.01% 99.99% # Table walker service (enqueue to completion) latency 1763system.cpu1.dtb.walker.walkCompletionTime::327680-360447 7 0.00% 99.99% # Table walker service (enqueue to completion) latency 1764system.cpu1.dtb.walker.walkCompletionTime::360448-393215 15 0.01% 100.00% # Table walker service (enqueue to completion) latency 1765system.cpu1.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 1766system.cpu1.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1767system.cpu1.dtb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1768system.cpu1.dtb.walker.walkCompletionTime::total 268382 # Table walker service (enqueue to completion) latency 1769system.cpu1.dtb.walker.walksPending::samples 466126532996 # Table walker pending requests distribution 1770system.cpu1.dtb.walker.walksPending::mean 0.617043 # Table walker pending requests distribution 1771system.cpu1.dtb.walker.walksPending::stdev 0.546089 # Table walker pending requests distribution 1772system.cpu1.dtb.walker.walksPending::0-1 464998520496 99.76% 99.76% # Table walker pending requests distribution 1773system.cpu1.dtb.walker.walksPending::2-3 569195000 0.12% 99.88% # Table walker pending requests distribution 1774system.cpu1.dtb.walker.walksPending::4-5 249472000 0.05% 99.93% # Table walker pending requests distribution 1775system.cpu1.dtb.walker.walksPending::6-7 122508000 0.03% 99.96% # Table walker pending requests distribution 1776system.cpu1.dtb.walker.walksPending::8-9 91886000 0.02% 99.98% # Table walker pending requests distribution 1777system.cpu1.dtb.walker.walksPending::10-11 55274500 0.01% 99.99% # Table walker pending requests distribution 1778system.cpu1.dtb.walker.walksPending::12-13 15901500 0.00% 99.99% # Table walker pending requests distribution 1779system.cpu1.dtb.walker.walksPending::14-15 23390500 0.01% 100.00% # Table walker pending requests distribution 1780system.cpu1.dtb.walker.walksPending::16-17 385000 0.00% 100.00% # Table walker pending requests distribution 1781system.cpu1.dtb.walker.walksPending::total 466126532996 # Table walker pending requests distribution 1782system.cpu1.dtb.walker.walkPageSizes::4K 81681 88.61% 88.61% # Table walker page sizes translated 1783system.cpu1.dtb.walker.walkPageSizes::2M 10503 11.39% 100.00% # Table walker page sizes translated 1784system.cpu1.dtb.walker.walkPageSizes::total 92184 # Table walker page sizes translated 1785system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 533309 # Table walker requests started/completed, data/inst 1786system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1787system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 533309 # Table walker requests started/completed, data/inst 1788system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 92184 # Table walker requests started/completed, data/inst 1789system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1790system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 92184 # Table walker requests started/completed, data/inst 1791system.cpu1.dtb.walker.walkRequestOrigin::total 625493 # Table walker requests started/completed, data/inst 1792system.cpu1.dtb.inst_hits 0 # ITB inst hits 1793system.cpu1.dtb.inst_misses 0 # ITB inst misses 1794system.cpu1.dtb.read_hits 161844710 # DTB read hits 1795system.cpu1.dtb.read_misses 366883 # DTB read misses 1796system.cpu1.dtb.write_hits 74184112 # DTB write hits 1797system.cpu1.dtb.write_misses 166426 # DTB write misses 1798system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1799system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1800system.cpu1.dtb.flush_tlb_mva_asid 44490 # Number of times TLB was flushed by MVA & ASID 1801system.cpu1.dtb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID 1802system.cpu1.dtb.flush_entries 34599 # Number of entries that have been flushed from TLB 1803system.cpu1.dtb.align_faults 386 # Number of TLB faults due to alignment restrictions 1804system.cpu1.dtb.prefetch_faults 6272 # Number of TLB faults due to prefetch 1805system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1806system.cpu1.dtb.perms_faults 37354 # Number of TLB faults due to permissions restrictions 1807system.cpu1.dtb.read_accesses 162211593 # DTB read accesses 1808system.cpu1.dtb.write_accesses 74350538 # DTB write accesses 1809system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1810system.cpu1.dtb.hits 236028822 # DTB hits 1811system.cpu1.dtb.misses 533309 # DTB misses 1812system.cpu1.dtb.accesses 236562131 # DTB accesses 1813system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 1814system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1815system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1816system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1817system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1818system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1819system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1820system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1821system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1822system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1823system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1824system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1825system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1826system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1827system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1828system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1829system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1830system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1831system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1832system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1833system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1834system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1835system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1836system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1837system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1838system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1839system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1840system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1841system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1842system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1843system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 1844system.cpu1.itb.walker.walks 80718 # Table walker walks requested 1845system.cpu1.itb.walker.walksLong 80718 # Table walker walks initiated with long descriptors 1846system.cpu1.itb.walker.walksLongTerminationLevel::Level2 768 # Level at which table walker walks with long descriptors terminate 1847system.cpu1.itb.walker.walksLongTerminationLevel::Level3 57037 # Level at which table walker walks with long descriptors terminate 1848system.cpu1.itb.walker.walksSquashedBefore 10137 # Table walks squashed before starting 1849system.cpu1.itb.walker.walkWaitTime::samples 70581 # Table walker wait (enqueue to first request) latency 1850system.cpu1.itb.walker.walkWaitTime::mean 996.309205 # Table walker wait (enqueue to first request) latency 1851system.cpu1.itb.walker.walkWaitTime::stdev 6981.449622 # Table walker wait (enqueue to first request) latency 1852system.cpu1.itb.walker.walkWaitTime::0-32767 70036 99.23% 99.23% # Table walker wait (enqueue to first request) latency 1853system.cpu1.itb.walker.walkWaitTime::32768-65535 380 0.54% 99.77% # Table walker wait (enqueue to first request) latency 1854system.cpu1.itb.walker.walkWaitTime::65536-98303 60 0.09% 99.85% # Table walker wait (enqueue to first request) latency 1855system.cpu1.itb.walker.walkWaitTime::98304-131071 83 0.12% 99.97% # Table walker wait (enqueue to first request) latency 1856system.cpu1.itb.walker.walkWaitTime::131072-163839 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency 1857system.cpu1.itb.walker.walkWaitTime::163840-196607 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency 1858system.cpu1.itb.walker.walkWaitTime::196608-229375 5 0.01% 100.00% # Table walker wait (enqueue to first request) latency 1859system.cpu1.itb.walker.walkWaitTime::229376-262143 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1860system.cpu1.itb.walker.walkWaitTime::262144-294911 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1861system.cpu1.itb.walker.walkWaitTime::total 70581 # Table walker wait (enqueue to first request) latency 1862system.cpu1.itb.walker.walkCompletionTime::samples 67942 # Table walker service (enqueue to completion) latency 1863system.cpu1.itb.walker.walkCompletionTime::mean 24162.219246 # Table walker service (enqueue to completion) latency 1864system.cpu1.itb.walker.walkCompletionTime::gmean 22142.693859 # Table walker service (enqueue to completion) latency 1865system.cpu1.itb.walker.walkCompletionTime::stdev 15015.121608 # Table walker service (enqueue to completion) latency 1866system.cpu1.itb.walker.walkCompletionTime::0-65535 66991 98.60% 98.60% # Table walker service (enqueue to completion) latency 1867system.cpu1.itb.walker.walkCompletionTime::65536-131071 778 1.15% 99.75% # Table walker service (enqueue to completion) latency 1868system.cpu1.itb.walker.walkCompletionTime::131072-196607 100 0.15% 99.89% # Table walker service (enqueue to completion) latency 1869system.cpu1.itb.walker.walkCompletionTime::196608-262143 45 0.07% 99.96% # Table walker service (enqueue to completion) latency 1870system.cpu1.itb.walker.walkCompletionTime::262144-327679 20 0.03% 99.99% # Table walker service (enqueue to completion) latency 1871system.cpu1.itb.walker.walkCompletionTime::327680-393215 5 0.01% 100.00% # Table walker service (enqueue to completion) latency 1872system.cpu1.itb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1873system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1874system.cpu1.itb.walker.walkCompletionTime::total 67942 # Table walker service (enqueue to completion) latency 1875system.cpu1.itb.walker.walksPending::samples 397380257260 # Table walker pending requests distribution 1876system.cpu1.itb.walker.walksPending::mean 0.877039 # Table walker pending requests distribution 1877system.cpu1.itb.walker.walksPending::stdev 0.328570 # Table walker pending requests distribution 1878system.cpu1.itb.walker.walksPending::0 48883602860 12.30% 12.30% # Table walker pending requests distribution 1879system.cpu1.itb.walker.walksPending::1 348476867900 87.69% 100.00% # Table walker pending requests distribution 1880system.cpu1.itb.walker.walksPending::2 18158500 0.00% 100.00% # Table walker pending requests distribution 1881system.cpu1.itb.walker.walksPending::3 1572000 0.00% 100.00% # Table walker pending requests distribution 1882system.cpu1.itb.walker.walksPending::4 56000 0.00% 100.00% # Table walker pending requests distribution 1883system.cpu1.itb.walker.walksPending::total 397380257260 # Table walker pending requests distribution 1884system.cpu1.itb.walker.walkPageSizes::4K 57037 98.67% 98.67% # Table walker page sizes translated 1885system.cpu1.itb.walker.walkPageSizes::2M 768 1.33% 100.00% # Table walker page sizes translated 1886system.cpu1.itb.walker.walkPageSizes::total 57805 # Table walker page sizes translated 1887system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1888system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 80718 # Table walker requests started/completed, data/inst 1889system.cpu1.itb.walker.walkRequestOrigin_Requested::total 80718 # Table walker requests started/completed, data/inst 1890system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1891system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 57805 # Table walker requests started/completed, data/inst 1892system.cpu1.itb.walker.walkRequestOrigin_Completed::total 57805 # Table walker requests started/completed, data/inst 1893system.cpu1.itb.walker.walkRequestOrigin::total 138523 # Table walker requests started/completed, data/inst 1894system.cpu1.itb.inst_hits 264777096 # ITB inst hits 1895system.cpu1.itb.inst_misses 80718 # ITB inst misses 1896system.cpu1.itb.read_hits 0 # DTB read hits 1897system.cpu1.itb.read_misses 0 # DTB read misses 1898system.cpu1.itb.write_hits 0 # DTB write hits 1899system.cpu1.itb.write_misses 0 # DTB write misses 1900system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1901system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1902system.cpu1.itb.flush_tlb_mva_asid 44490 # Number of times TLB was flushed by MVA & ASID 1903system.cpu1.itb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID 1904system.cpu1.itb.flush_entries 24684 # Number of entries that have been flushed from TLB 1905system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1906system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1907system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1908system.cpu1.itb.perms_faults 195163 # Number of TLB faults due to permissions restrictions 1909system.cpu1.itb.read_accesses 0 # DTB read accesses 1910system.cpu1.itb.write_accesses 0 # DTB write accesses 1911system.cpu1.itb.inst_accesses 264857814 # ITB inst accesses 1912system.cpu1.itb.hits 264777096 # DTB hits 1913system.cpu1.itb.misses 80718 # DTB misses 1914system.cpu1.itb.accesses 264857814 # DTB accesses 1915system.cpu1.numPwrStateTransitions 9670 # Number of power state transitions 1916system.cpu1.pwrStateClkGateDist::samples 4835 # Distribution of time spent in the clock gated state 1917system.cpu1.pwrStateClkGateDist::mean 9724953244.725336 # Distribution of time spent in the clock gated state 1918system.cpu1.pwrStateClkGateDist::stdev 147881742434.863098 # Distribution of time spent in the clock gated state 1919system.cpu1.pwrStateClkGateDist::underflows 3183 65.83% 65.83% # Distribution of time spent in the clock gated state 1920system.cpu1.pwrStateClkGateDist::1000-5e+10 1626 33.63% 99.46% # Distribution of time spent in the clock gated state 1921system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.04% 99.50% # Distribution of time spent in the clock gated state 1922system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 5 0.10% 99.61% # Distribution of time spent in the clock gated state 1923system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 2 0.04% 99.65% # Distribution of time spent in the clock gated state 1924system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11 1 0.02% 99.67% # Distribution of time spent in the clock gated state 1925system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.02% 99.69% # Distribution of time spent in the clock gated state 1926system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.02% 99.71% # Distribution of time spent in the clock gated state 1927system.cpu1.pwrStateClkGateDist::overflows 14 0.29% 100.00% # Distribution of time spent in the clock gated state 1928system.cpu1.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state 1929system.cpu1.pwrStateClkGateDist::max_value 7390881470984 # Distribution of time spent in the clock gated state 1930system.cpu1.pwrStateClkGateDist::total 4835 # Distribution of time spent in the clock gated state 1931system.cpu1.pwrStateResidencyTicks::ON 364202361753 # Cumulative time (in ticks) in various power states 1932system.cpu1.pwrStateResidencyTicks::CLK_GATED 47020148938247 # Cumulative time (in ticks) in various power states 1933system.cpu1.numCycles 728406370 # number of cpu cycles simulated 1934system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1935system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1936system.cpu1.fetch.icacheStallCycles 83192103 # Number of cycles fetch is stalled on an Icache miss 1937system.cpu1.fetch.Insts 724269312 # Number of instructions fetch has processed 1938system.cpu1.fetch.Branches 194671556 # Number of branches that fetch encountered 1939system.cpu1.fetch.predictedBranches 107565789 # Number of branches that fetch has predicted taken 1940system.cpu1.fetch.Cycles 610871186 # Number of cycles fetch has run and was not squashing or blocked 1941system.cpu1.fetch.SquashCycles 13439122 # Number of cycles fetch has spent squashing 1942system.cpu1.fetch.TlbCycles 1719504 # Number of cycles fetch has spent waiting for tlb 1943system.cpu1.fetch.MiscStallCycles 273339 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1944system.cpu1.fetch.PendingTrapStallCycles 5608482 # Number of stall cycles due to pending traps 1945system.cpu1.fetch.PendingQuiesceStallCycles 704978 # Number of stall cycles due to pending quiesce instructions 1946system.cpu1.fetch.IcacheWaitRetryStallCycles 774415 # Number of stall cycles due to full MSHR 1947system.cpu1.fetch.CacheLines 264561727 # Number of cache lines fetched 1948system.cpu1.fetch.IcacheSquashes 1602178 # Number of outstanding Icache misses that were squashed 1949system.cpu1.fetch.ItlbSquashes 26700 # Number of outstanding ITLB misses that were squashed 1950system.cpu1.fetch.rateDist::samples 709863568 # Number of instructions fetched each cycle (Total) 1951system.cpu1.fetch.rateDist::mean 1.153991 # Number of instructions fetched each cycle (Total) 1952system.cpu1.fetch.rateDist::stdev 1.257090 # Number of instructions fetched each cycle (Total) 1953system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1954system.cpu1.fetch.rateDist::0 331851103 46.75% 46.75% # Number of instructions fetched each cycle (Total) 1955system.cpu1.fetch.rateDist::1 119648081 16.86% 63.60% # Number of instructions fetched each cycle (Total) 1956system.cpu1.fetch.rateDist::2 75565351 10.65% 74.25% # Number of instructions fetched each cycle (Total) 1957system.cpu1.fetch.rateDist::3 182799033 25.75% 100.00% # Number of instructions fetched each cycle (Total) 1958system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1959system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1960system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 1961system.cpu1.fetch.rateDist::total 709863568 # Number of instructions fetched each cycle (Total) 1962system.cpu1.fetch.branchRate 0.267257 # Number of branch fetches per cycle 1963system.cpu1.fetch.rate 0.994320 # Number of inst fetches per cycle 1964system.cpu1.decode.IdleCycles 98062054 # Number of cycles decode is idle 1965system.cpu1.decode.BlockedCycles 297890044 # Number of cycles decode is blocked 1966system.cpu1.decode.RunCycles 275618841 # Number of cycles decode is running 1967system.cpu1.decode.UnblockCycles 33512378 # Number of cycles decode is unblocking 1968system.cpu1.decode.SquashCycles 4780251 # Number of cycles decode is squashing 1969system.cpu1.decode.BranchResolved 17247911 # Number of times decode resolved a branch 1970system.cpu1.decode.BranchMispred 1977266 # Number of times decode detected a branch misprediction 1971system.cpu1.decode.DecodedInsts 743961992 # Number of instructions handled by decode 1972system.cpu1.decode.SquashedInsts 21656856 # Number of squashed instructions handled by decode 1973system.cpu1.rename.SquashCycles 4780251 # Number of cycles rename is squashing 1974system.cpu1.rename.IdleCycles 130238128 # Number of cycles rename is idle 1975system.cpu1.rename.BlockCycles 40363481 # Number of cycles rename is blocking 1976system.cpu1.rename.serializeStallCycles 204147620 # count of cycles rename stalled for serializing inst 1977system.cpu1.rename.RunCycles 276602035 # Number of cycles rename is running 1978system.cpu1.rename.UnblockCycles 53732053 # Number of cycles rename is unblocking 1979system.cpu1.rename.RenamedInsts 728176206 # Number of instructions processed by rename 1980system.cpu1.rename.SquashedInsts 5626727 # Number of squashed instructions processed by rename 1981system.cpu1.rename.ROBFullEvents 9082967 # Number of times rename has blocked due to ROB full 1982system.cpu1.rename.IQFullEvents 240191 # Number of times rename has blocked due to IQ full 1983system.cpu1.rename.LQFullEvents 268836 # Number of times rename has blocked due to LQ full 1984system.cpu1.rename.SQFullEvents 22296515 # Number of times rename has blocked due to SQ full 1985system.cpu1.rename.FullRegisterEvents 11543 # Number of times there has been no free registers 1986system.cpu1.rename.RenamedOperands 630286495 # Number of destination operands rename has renamed 1987system.cpu1.rename.RenameLookups 1024905330 # Number of register rename lookups that rename has made 1988system.cpu1.rename.int_rename_lookups 827525539 # Number of integer rename lookups 1989system.cpu1.rename.fp_rename_lookups 801877 # Number of floating rename lookups 1990system.cpu1.rename.CommittedMaps 577128327 # Number of HB maps that are committed 1991system.cpu1.rename.UndoneMaps 53158158 # Number of HB maps that are undone due to squashing 1992system.cpu1.rename.serializingInsts 14384532 # count of serializing insts renamed 1993system.cpu1.rename.tempSerializingInsts 12638476 # count of temporary serializing insts renamed 1994system.cpu1.rename.skidInsts 67737488 # count of insts added to the skid buffer 1995system.cpu1.memDep0.insertedLoads 162372694 # Number of loads inserted to the mem dependence unit. 1996system.cpu1.memDep0.insertedStores 77181222 # Number of stores inserted to the mem dependence unit. 1997system.cpu1.memDep0.conflictingLoads 8520193 # Number of conflicting loads. 1998system.cpu1.memDep0.conflictingStores 7294637 # Number of conflicting stores. 1999system.cpu1.iq.iqInstsAdded 707349171 # Number of instructions added to the IQ (excludes non-spec) 2000system.cpu1.iq.iqNonSpecInstsAdded 14663402 # Number of non-speculative instructions added to the IQ 2001system.cpu1.iq.iqInstsIssued 711466322 # Number of instructions issued 2002system.cpu1.iq.iqSquashedInstsIssued 2509310 # Number of squashed instructions issued 2003system.cpu1.iq.iqSquashedInstsExamined 50084332 # Number of squashed instructions iterated over during squash; mainly for profiling 2004system.cpu1.iq.iqSquashedOperandsExamined 32217686 # Number of squashed operands that are examined and possibly removed from graph 2005system.cpu1.iq.iqSquashedNonSpecRemoved 252969 # Number of squashed non-spec instructions that were removed 2006system.cpu1.iq.issued_per_cycle::samples 709863568 # Number of insts issued each cycle 2007system.cpu1.iq.issued_per_cycle::mean 1.002258 # Number of insts issued each cycle 2008system.cpu1.iq.issued_per_cycle::stdev 1.141899 # Number of insts issued each cycle 2009system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 2010system.cpu1.iq.issued_per_cycle::0 346424684 48.80% 48.80% # Number of insts issued each cycle 2011system.cpu1.iq.issued_per_cycle::1 123916139 17.46% 66.26% # Number of insts issued each cycle 2012system.cpu1.iq.issued_per_cycle::2 138092978 19.45% 85.71% # Number of insts issued each cycle 2013system.cpu1.iq.issued_per_cycle::3 94358537 13.29% 99.00% # Number of insts issued each cycle 2014system.cpu1.iq.issued_per_cycle::4 7067534 1.00% 100.00% # Number of insts issued each cycle 2015system.cpu1.iq.issued_per_cycle::5 3696 0.00% 100.00% # Number of insts issued each cycle 2016system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 2017system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 2018system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 2019system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 2020system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 2021system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 2022system.cpu1.iq.issued_per_cycle::total 709863568 # Number of insts issued each cycle 2023system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 2024system.cpu1.iq.fu_full::IntAlu 53419887 27.72% 27.72% # attempts to use FU when none available 2025system.cpu1.iq.fu_full::IntMult 53191 0.03% 27.75% # attempts to use FU when none available 2026system.cpu1.iq.fu_full::IntDiv 19037 0.01% 27.76% # attempts to use FU when none available 2027system.cpu1.iq.fu_full::FloatAdd 0 0.00% 27.76% # attempts to use FU when none available 2028system.cpu1.iq.fu_full::FloatCmp 0 0.00% 27.76% # attempts to use FU when none available 2029system.cpu1.iq.fu_full::FloatCvt 0 0.00% 27.76% # attempts to use FU when none available 2030system.cpu1.iq.fu_full::FloatMult 0 0.00% 27.76% # attempts to use FU when none available 2031system.cpu1.iq.fu_full::FloatDiv 0 0.00% 27.76% # attempts to use FU when none available 2032system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 27.76% # attempts to use FU when none available 2033system.cpu1.iq.fu_full::SimdAdd 0 0.00% 27.76% # attempts to use FU when none available 2034system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 27.76% # attempts to use FU when none available 2035system.cpu1.iq.fu_full::SimdAlu 0 0.00% 27.76% # attempts to use FU when none available 2036system.cpu1.iq.fu_full::SimdCmp 0 0.00% 27.76% # attempts to use FU when none available 2037system.cpu1.iq.fu_full::SimdCvt 0 0.00% 27.76% # attempts to use FU when none available 2038system.cpu1.iq.fu_full::SimdMisc 0 0.00% 27.76% # attempts to use FU when none available 2039system.cpu1.iq.fu_full::SimdMult 0 0.00% 27.76% # attempts to use FU when none available 2040system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 27.76% # attempts to use FU when none available 2041system.cpu1.iq.fu_full::SimdShift 0 0.00% 27.76% # attempts to use FU when none available 2042system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 27.76% # attempts to use FU when none available 2043system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 27.76% # attempts to use FU when none available 2044system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 27.76% # attempts to use FU when none available 2045system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 27.76% # attempts to use FU when none available 2046system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 27.76% # attempts to use FU when none available 2047system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 27.76% # attempts to use FU when none available 2048system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 27.76% # attempts to use FU when none available 2049system.cpu1.iq.fu_full::SimdFloatMisc 15 0.00% 27.76% # attempts to use FU when none available 2050system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 27.76% # attempts to use FU when none available 2051system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.76% # attempts to use FU when none available 2052system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 27.76% # attempts to use FU when none available 2053system.cpu1.iq.fu_full::MemRead 103986379 53.96% 81.72% # attempts to use FU when none available 2054system.cpu1.iq.fu_full::MemWrite 35231745 18.28% 100.00% # attempts to use FU when none available 2055system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 2056system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 2057system.cpu1.iq.FU_type_0::No_OpClass 25 0.00% 0.00% # Type of FU issued 2058system.cpu1.iq.FU_type_0::IntAlu 469996066 66.06% 66.06% # Type of FU issued 2059system.cpu1.iq.FU_type_0::IntMult 1210560 0.17% 66.23% # Type of FU issued 2060system.cpu1.iq.FU_type_0::IntDiv 70927 0.01% 66.24% # Type of FU issued 2061system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 66.24% # Type of FU issued 2062system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.24% # Type of FU issued 2063system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.24% # Type of FU issued 2064system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.24% # Type of FU issued 2065system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.24% # Type of FU issued 2066system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.24% # Type of FU issued 2067system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.24% # Type of FU issued 2068system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.24% # Type of FU issued 2069system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.24% # Type of FU issued 2070system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.24% # Type of FU issued 2071system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.24% # Type of FU issued 2072system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.24% # Type of FU issued 2073system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.24% # Type of FU issued 2074system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.24% # Type of FU issued 2075system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.24% # Type of FU issued 2076system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.24% # Type of FU issued 2077system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.24% # Type of FU issued 2078system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 66.24% # Type of FU issued 2079system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.24% # Type of FU issued 2080system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 66.24% # Type of FU issued 2081system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 66.24% # Type of FU issued 2082system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.24% # Type of FU issued 2083system.cpu1.iq.FU_type_0::SimdFloatMisc 81598 0.01% 66.25% # Type of FU issued 2084system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.25% # Type of FU issued 2085system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.25% # Type of FU issued 2086system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.25% # Type of FU issued 2087system.cpu1.iq.FU_type_0::MemRead 164776620 23.16% 89.41% # Type of FU issued 2088system.cpu1.iq.FU_type_0::MemWrite 75330478 10.59% 100.00% # Type of FU issued 2089system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2090system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 2091system.cpu1.iq.FU_type_0::total 711466322 # Type of FU issued 2092system.cpu1.iq.rate 0.976744 # Inst issue rate 2093system.cpu1.iq.fu_busy_cnt 192710254 # FU busy when requested 2094system.cpu1.iq.fu_busy_rate 0.270863 # FU busy rate (busy events/executed inst) 2095system.cpu1.iq.int_inst_queue_reads 2326678945 # Number of integer instruction queue reads 2096system.cpu1.iq.int_inst_queue_writes 771690256 # Number of integer instruction queue writes 2097system.cpu1.iq.int_inst_queue_wakeup_accesses 695698465 # Number of integer instruction queue wakeup accesses 2098system.cpu1.iq.fp_inst_queue_reads 1336829 # Number of floating instruction queue reads 2099system.cpu1.iq.fp_inst_queue_writes 536159 # Number of floating instruction queue writes 2100system.cpu1.iq.fp_inst_queue_wakeup_accesses 497637 # Number of floating instruction queue wakeup accesses 2101system.cpu1.iq.int_alu_accesses 903350253 # Number of integer alu accesses 2102system.cpu1.iq.fp_alu_accesses 826298 # Number of floating point alu accesses 2103system.cpu1.iew.lsq.thread0.forwLoads 2394067 # Number of loads that had data forwarded from stores 2104system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2105system.cpu1.iew.lsq.thread0.squashedLoads 11654320 # Number of loads squashed 2106system.cpu1.iew.lsq.thread0.ignoredResponses 15948 # Number of memory responses ignored because the instruction is squashed 2107system.cpu1.iew.lsq.thread0.memOrderViolation 130447 # Number of memory ordering violations 2108system.cpu1.iew.lsq.thread0.squashedStores 5130974 # Number of stores squashed 2109system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2110system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2111system.cpu1.iew.lsq.thread0.rescheduledLoads 2399995 # Number of loads that were rescheduled 2112system.cpu1.iew.lsq.thread0.cacheBlocked 3738162 # Number of times an access to memory failed due to the cache being blocked 2113system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2114system.cpu1.iew.iewSquashCycles 4780251 # Number of cycles IEW is squashing 2115system.cpu1.iew.iewBlockCycles 5901245 # Number of cycles IEW is blocking 2116system.cpu1.iew.iewUnblockCycles 1355404 # Number of cycles IEW is unblocking 2117system.cpu1.iew.iewDispatchedInsts 722138785 # Number of instructions dispatched to IQ 2118system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 2119system.cpu1.iew.iewDispLoadInsts 162372694 # Number of dispatched load instructions 2120system.cpu1.iew.iewDispStoreInsts 77181222 # Number of dispatched store instructions 2121system.cpu1.iew.iewDispNonSpecInsts 12419825 # Number of dispatched non-speculative instructions 2122system.cpu1.iew.iewIQFullEvents 58724 # Number of times the IQ has become full, causing a stall 2123system.cpu1.iew.iewLSQFullEvents 1239916 # Number of times the LSQ has become full, causing a stall 2124system.cpu1.iew.memOrderViolationEvents 130447 # Number of memory order violations 2125system.cpu1.iew.predictedTakenIncorrect 1767111 # Number of branches that were predicted taken incorrectly 2126system.cpu1.iew.predictedNotTakenIncorrect 2862185 # Number of branches that were predicted not taken incorrectly 2127system.cpu1.iew.branchMispredicts 4629296 # Number of branch mispredicts detected at execute 2128system.cpu1.iew.iewExecutedInsts 704121990 # Number of executed instructions 2129system.cpu1.iew.iewExecLoadInsts 161840669 # Number of load instructions executed 2130system.cpu1.iew.iewExecSquashedInsts 6820718 # Number of squashed instructions skipped in execute 2131system.cpu1.iew.exec_swp 0 # number of swp insts executed 2132system.cpu1.iew.exec_nop 126212 # number of nop insts executed 2133system.cpu1.iew.exec_refs 236024480 # number of memory reference insts executed 2134system.cpu1.iew.exec_branches 169760384 # Number of branches executed 2135system.cpu1.iew.exec_stores 74183811 # Number of stores executed 2136system.cpu1.iew.exec_rate 0.966661 # Inst execution rate 2137system.cpu1.iew.wb_sent 696881354 # cumulative count of insts sent to commit 2138system.cpu1.iew.wb_count 696196102 # cumulative count of insts written-back 2139system.cpu1.iew.wb_producers 357262878 # num instructions producing a value 2140system.cpu1.iew.wb_consumers 517340824 # num instructions consuming a value 2141system.cpu1.iew.wb_rate 0.955780 # insts written-back per cycle 2142system.cpu1.iew.wb_fanout 0.690575 # average fanout of values written-back 2143system.cpu1.commit.commitSquashedInsts 43732145 # The number of squashed insts skipped by commit 2144system.cpu1.commit.commitNonSpecStalls 14410433 # The number of times commit has been forced to stall to communicate backwards 2145system.cpu1.commit.branchMispredicts 4314978 # The number of times a branch was mispredicted 2146system.cpu1.commit.committed_per_cycle::samples 701540457 # Number of insts commited each cycle 2147system.cpu1.commit.committed_per_cycle::mean 0.957790 # Number of insts commited each cycle 2148system.cpu1.commit.committed_per_cycle::stdev 1.589997 # Number of insts commited each cycle 2149system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2150system.cpu1.commit.committed_per_cycle::0 413092247 58.88% 58.88% # Number of insts commited each cycle 2151system.cpu1.commit.committed_per_cycle::1 113176092 16.13% 75.02% # Number of insts commited each cycle 2152system.cpu1.commit.committed_per_cycle::2 83530992 11.91% 86.92% # Number of insts commited each cycle 2153system.cpu1.commit.committed_per_cycle::3 51841229 7.39% 94.31% # Number of insts commited each cycle 2154system.cpu1.commit.committed_per_cycle::4 11508500 1.64% 95.95% # Number of insts commited each cycle 2155system.cpu1.commit.committed_per_cycle::5 7726725 1.10% 97.05% # Number of insts commited each cycle 2156system.cpu1.commit.committed_per_cycle::6 5343630 0.76% 97.82% # Number of insts commited each cycle 2157system.cpu1.commit.committed_per_cycle::7 3131269 0.45% 98.26% # Number of insts commited each cycle 2158system.cpu1.commit.committed_per_cycle::8 12189773 1.74% 100.00% # Number of insts commited each cycle 2159system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2160system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2161system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 2162system.cpu1.commit.committed_per_cycle::total 701540457 # Number of insts commited each cycle 2163system.cpu1.commit.committedInsts 597176554 # Number of instructions committed 2164system.cpu1.commit.committedOps 671928235 # Number of ops (including micro ops) committed 2165system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 2166system.cpu1.commit.refs 222768619 # Number of memory references committed 2167system.cpu1.commit.loads 150718371 # Number of loads committed 2168system.cpu1.commit.membars 39196572 # Number of memory barriers committed 2169system.cpu1.commit.branches 164739467 # Number of branches committed 2170system.cpu1.commit.fp_insts 488627 # Number of committed floating point instructions. 2171system.cpu1.commit.int_insts 631392614 # Number of committed integer instructions. 2172system.cpu1.commit.function_calls 12167965 # Number of function calls committed. 2173system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 2174system.cpu1.commit.op_class_0::IntAlu 448043617 66.68% 66.68% # Class of committed instruction 2175system.cpu1.commit.op_class_0::IntMult 985154 0.15% 66.83% # Class of committed instruction 2176system.cpu1.commit.op_class_0::IntDiv 56630 0.01% 66.84% # Class of committed instruction 2177system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 66.84% # Class of committed instruction 2178system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 66.84% # Class of committed instruction 2179system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 66.84% # Class of committed instruction 2180system.cpu1.commit.op_class_0::FloatMult 0 0.00% 66.84% # Class of committed instruction 2181system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 66.84% # Class of committed instruction 2182system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 66.84% # Class of committed instruction 2183system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 66.84% # Class of committed instruction 2184system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 66.84% # Class of committed instruction 2185system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 66.84% # Class of committed instruction 2186system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 66.84% # Class of committed instruction 2187system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 66.84% # Class of committed instruction 2188system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 66.84% # Class of committed instruction 2189system.cpu1.commit.op_class_0::SimdMult 0 0.00% 66.84% # Class of committed instruction 2190system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 66.84% # Class of committed instruction 2191system.cpu1.commit.op_class_0::SimdShift 0 0.00% 66.84% # Class of committed instruction 2192system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 66.84% # Class of committed instruction 2193system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 66.84% # Class of committed instruction 2194system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 66.84% # Class of committed instruction 2195system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 66.84% # Class of committed instruction 2196system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 66.84% # Class of committed instruction 2197system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 66.84% # Class of committed instruction 2198system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 66.84% # Class of committed instruction 2199system.cpu1.commit.op_class_0::SimdFloatMisc 74173 0.01% 66.85% # Class of committed instruction 2200system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 66.85% # Class of committed instruction 2201system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.85% # Class of committed instruction 2202system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.85% # Class of committed instruction 2203system.cpu1.commit.op_class_0::MemRead 150718371 22.43% 89.28% # Class of committed instruction 2204system.cpu1.commit.op_class_0::MemWrite 72050248 10.72% 100.00% # Class of committed instruction 2205system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2206system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 2207system.cpu1.commit.op_class_0::total 671928235 # Class of committed instruction 2208system.cpu1.commit.bw_lim_events 12189773 # number cycles where commit BW limit reached 2209system.cpu1.rob.rob_reads 1401264531 # The number of ROB reads 2210system.cpu1.rob.rob_writes 1439606443 # The number of ROB writes 2211system.cpu1.timesIdled 902579 # Number of times that the entire CPU went into an idle state and unscheduled itself 2212system.cpu1.idleCycles 18542802 # Total number of cycles that the CPU has spent unscheduled due to idling 2213system.cpu1.quiesceCycles 94040296263 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2214system.cpu1.committedInsts 597176554 # Number of Instructions Simulated 2215system.cpu1.committedOps 671928235 # Number of Ops (including micro ops) Simulated 2216system.cpu1.cpi 1.219750 # CPI: Cycles Per Instruction 2217system.cpu1.cpi_total 1.219750 # CPI: Total CPI of All Threads 2218system.cpu1.ipc 0.819840 # IPC: Instructions Per Cycle 2219system.cpu1.ipc_total 0.819840 # IPC: Total IPC of All Threads 2220system.cpu1.int_regfile_reads 799341399 # number of integer regfile reads 2221system.cpu1.int_regfile_writes 475575163 # number of integer regfile writes 2222system.cpu1.fp_regfile_reads 787030 # number of floating regfile reads 2223system.cpu1.fp_regfile_writes 454812 # number of floating regfile writes 2224system.cpu1.cc_regfile_reads 112918659 # number of cc regfile reads 2225system.cpu1.cc_regfile_writes 113685571 # number of cc regfile writes 2226system.cpu1.misc_regfile_reads 1436513215 # number of misc regfile reads 2227system.cpu1.misc_regfile_writes 14489141 # number of misc regfile writes 2228system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 2229system.cpu1.dcache.tags.replacements 5047432 # number of replacements 2230system.cpu1.dcache.tags.tagsinuse 457.905792 # Cycle average of tags in use 2231system.cpu1.dcache.tags.total_refs 212666270 # Total number of references to valid blocks. 2232system.cpu1.dcache.tags.sampled_refs 5047943 # Sample count of references to valid blocks. 2233system.cpu1.dcache.tags.avg_refs 42.129293 # Average number of references to valid blocks. 2234system.cpu1.dcache.tags.warmup_cycle 8477400492000 # Cycle when the warmup percentage was hit. 2235system.cpu1.dcache.tags.occ_blocks::cpu1.data 457.905792 # Average occupied blocks per requestor 2236system.cpu1.dcache.tags.occ_percent::cpu1.data 0.894347 # Average percentage of cache occupancy 2237system.cpu1.dcache.tags.occ_percent::total 0.894347 # Average percentage of cache occupancy 2238system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 2239system.cpu1.dcache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id 2240system.cpu1.dcache.tags.age_task_id_blocks_1024::1 323 # Occupied blocks per task id 2241system.cpu1.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id 2242system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 2243system.cpu1.dcache.tags.tag_accesses 457080025 # Number of tag accesses 2244system.cpu1.dcache.tags.data_accesses 457080025 # Number of data accesses 2245system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 2246system.cpu1.dcache.ReadReq_hits::cpu1.data 145190780 # number of ReadReq hits 2247system.cpu1.dcache.ReadReq_hits::total 145190780 # number of ReadReq hits 2248system.cpu1.dcache.WriteReq_hits::cpu1.data 62993534 # number of WriteReq hits 2249system.cpu1.dcache.WriteReq_hits::total 62993534 # number of WriteReq hits 2250system.cpu1.dcache.SoftPFReq_hits::cpu1.data 167629 # number of SoftPFReq hits 2251system.cpu1.dcache.SoftPFReq_hits::total 167629 # number of SoftPFReq hits 2252system.cpu1.dcache.WriteLineReq_hits::cpu1.data 116242 # number of WriteLineReq hits 2253system.cpu1.dcache.WriteLineReq_hits::total 116242 # number of WriteLineReq hits 2254system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1721505 # number of LoadLockedReq hits 2255system.cpu1.dcache.LoadLockedReq_hits::total 1721505 # number of LoadLockedReq hits 2256system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1728884 # number of StoreCondReq hits 2257system.cpu1.dcache.StoreCondReq_hits::total 1728884 # number of StoreCondReq hits 2258system.cpu1.dcache.demand_hits::cpu1.data 208300556 # number of demand (read+write) hits 2259system.cpu1.dcache.demand_hits::total 208300556 # number of demand (read+write) hits 2260system.cpu1.dcache.overall_hits::cpu1.data 208468185 # number of overall hits 2261system.cpu1.dcache.overall_hits::total 208468185 # number of overall hits 2262system.cpu1.dcache.ReadReq_misses::cpu1.data 5993321 # number of ReadReq misses 2263system.cpu1.dcache.ReadReq_misses::total 5993321 # number of ReadReq misses 2264system.cpu1.dcache.WriteReq_misses::cpu1.data 6604202 # number of WriteReq misses 2265system.cpu1.dcache.WriteReq_misses::total 6604202 # number of WriteReq misses 2266system.cpu1.dcache.SoftPFReq_misses::cpu1.data 607895 # number of SoftPFReq misses 2267system.cpu1.dcache.SoftPFReq_misses::total 607895 # number of SoftPFReq misses 2268system.cpu1.dcache.WriteLineReq_misses::cpu1.data 421696 # number of WriteLineReq misses 2269system.cpu1.dcache.WriteLineReq_misses::total 421696 # number of WriteLineReq misses 2270system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 237246 # number of LoadLockedReq misses 2271system.cpu1.dcache.LoadLockedReq_misses::total 237246 # number of LoadLockedReq misses 2272system.cpu1.dcache.StoreCondReq_misses::cpu1.data 187668 # number of StoreCondReq misses 2273system.cpu1.dcache.StoreCondReq_misses::total 187668 # number of StoreCondReq misses 2274system.cpu1.dcache.demand_misses::cpu1.data 13019219 # number of demand (read+write) misses 2275system.cpu1.dcache.demand_misses::total 13019219 # number of demand (read+write) misses 2276system.cpu1.dcache.overall_misses::cpu1.data 13627114 # number of overall misses 2277system.cpu1.dcache.overall_misses::total 13627114 # number of overall misses 2278system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 89379669000 # number of ReadReq miss cycles 2279system.cpu1.dcache.ReadReq_miss_latency::total 89379669000 # number of ReadReq miss cycles 2280system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 119695443135 # number of WriteReq miss cycles 2281system.cpu1.dcache.WriteReq_miss_latency::total 119695443135 # number of WriteReq miss cycles 2282system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10488678921 # number of WriteLineReq miss cycles 2283system.cpu1.dcache.WriteLineReq_miss_latency::total 10488678921 # number of WriteLineReq miss cycles 2284system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3322992000 # number of LoadLockedReq miss cycles 2285system.cpu1.dcache.LoadLockedReq_miss_latency::total 3322992000 # number of LoadLockedReq miss cycles 2286system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4669078500 # number of StoreCondReq miss cycles 2287system.cpu1.dcache.StoreCondReq_miss_latency::total 4669078500 # number of StoreCondReq miss cycles 2288system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3521000 # number of StoreCondFailReq miss cycles 2289system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3521000 # number of StoreCondFailReq miss cycles 2290system.cpu1.dcache.demand_miss_latency::cpu1.data 219563791056 # number of demand (read+write) miss cycles 2291system.cpu1.dcache.demand_miss_latency::total 219563791056 # number of demand (read+write) miss cycles 2292system.cpu1.dcache.overall_miss_latency::cpu1.data 219563791056 # number of overall miss cycles 2293system.cpu1.dcache.overall_miss_latency::total 219563791056 # number of overall miss cycles 2294system.cpu1.dcache.ReadReq_accesses::cpu1.data 151184101 # number of ReadReq accesses(hits+misses) 2295system.cpu1.dcache.ReadReq_accesses::total 151184101 # number of ReadReq accesses(hits+misses) 2296system.cpu1.dcache.WriteReq_accesses::cpu1.data 69597736 # number of WriteReq accesses(hits+misses) 2297system.cpu1.dcache.WriteReq_accesses::total 69597736 # number of WriteReq accesses(hits+misses) 2298system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 775524 # number of SoftPFReq accesses(hits+misses) 2299system.cpu1.dcache.SoftPFReq_accesses::total 775524 # number of SoftPFReq accesses(hits+misses) 2300system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 537938 # number of WriteLineReq accesses(hits+misses) 2301system.cpu1.dcache.WriteLineReq_accesses::total 537938 # number of WriteLineReq accesses(hits+misses) 2302system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1958751 # number of LoadLockedReq accesses(hits+misses) 2303system.cpu1.dcache.LoadLockedReq_accesses::total 1958751 # number of LoadLockedReq accesses(hits+misses) 2304system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1916552 # number of StoreCondReq accesses(hits+misses) 2305system.cpu1.dcache.StoreCondReq_accesses::total 1916552 # number of StoreCondReq accesses(hits+misses) 2306system.cpu1.dcache.demand_accesses::cpu1.data 221319775 # number of demand (read+write) accesses 2307system.cpu1.dcache.demand_accesses::total 221319775 # number of demand (read+write) accesses 2308system.cpu1.dcache.overall_accesses::cpu1.data 222095299 # number of overall (read+write) accesses 2309system.cpu1.dcache.overall_accesses::total 222095299 # number of overall (read+write) accesses 2310system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.039643 # miss rate for ReadReq accesses 2311system.cpu1.dcache.ReadReq_miss_rate::total 0.039643 # miss rate for ReadReq accesses 2312system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.094891 # miss rate for WriteReq accesses 2313system.cpu1.dcache.WriteReq_miss_rate::total 0.094891 # miss rate for WriteReq accesses 2314system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.783851 # miss rate for SoftPFReq accesses 2315system.cpu1.dcache.SoftPFReq_miss_rate::total 0.783851 # miss rate for SoftPFReq accesses 2316system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.783912 # miss rate for WriteLineReq accesses 2317system.cpu1.dcache.WriteLineReq_miss_rate::total 0.783912 # miss rate for WriteLineReq accesses 2318system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.121121 # miss rate for LoadLockedReq accesses 2319system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.121121 # miss rate for LoadLockedReq accesses 2320system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097920 # miss rate for StoreCondReq accesses 2321system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097920 # miss rate for StoreCondReq accesses 2322system.cpu1.dcache.demand_miss_rate::cpu1.data 0.058825 # miss rate for demand accesses 2323system.cpu1.dcache.demand_miss_rate::total 0.058825 # miss rate for demand accesses 2324system.cpu1.dcache.overall_miss_rate::cpu1.data 0.061357 # miss rate for overall accesses 2325system.cpu1.dcache.overall_miss_rate::total 0.061357 # miss rate for overall accesses 2326system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14913.212391 # average ReadReq miss latency 2327system.cpu1.dcache.ReadReq_avg_miss_latency::total 14913.212391 # average ReadReq miss latency 2328system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18124.134170 # average WriteReq miss latency 2329system.cpu1.dcache.WriteReq_avg_miss_latency::total 18124.134170 # average WriteReq miss latency 2330system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24872.607094 # average WriteLineReq miss latency 2331system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24872.607094 # average WriteLineReq miss latency 2332system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14006.524873 # average LoadLockedReq miss latency 2333system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14006.524873 # average LoadLockedReq miss latency 2334system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24879.460004 # average StoreCondReq miss latency 2335system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24879.460004 # average StoreCondReq miss latency 2336system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 2337system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 2338system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16864.590038 # average overall miss latency 2339system.cpu1.dcache.demand_avg_miss_latency::total 16864.590038 # average overall miss latency 2340system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16112.273740 # average overall miss latency 2341system.cpu1.dcache.overall_avg_miss_latency::total 16112.273740 # average overall miss latency 2342system.cpu1.dcache.blocked_cycles::no_mshrs 2706631 # number of cycles access was blocked 2343system.cpu1.dcache.blocked_cycles::no_targets 18960106 # number of cycles access was blocked 2344system.cpu1.dcache.blocked::no_mshrs 351175 # number of cycles access was blocked 2345system.cpu1.dcache.blocked::no_targets 660083 # number of cycles access was blocked 2346system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.707357 # average number of cycles each access was blocked 2347system.cpu1.dcache.avg_blocked_cycles::no_targets 28.723821 # average number of cycles each access was blocked 2348system.cpu1.dcache.writebacks::writebacks 5047462 # number of writebacks 2349system.cpu1.dcache.writebacks::total 5047462 # number of writebacks 2350system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3052290 # number of ReadReq MSHR hits 2351system.cpu1.dcache.ReadReq_mshr_hits::total 3052290 # number of ReadReq MSHR hits 2352system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5325465 # number of WriteReq MSHR hits 2353system.cpu1.dcache.WriteReq_mshr_hits::total 5325465 # number of WriteReq MSHR hits 2354system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3276 # number of WriteLineReq MSHR hits 2355system.cpu1.dcache.WriteLineReq_mshr_hits::total 3276 # number of WriteLineReq MSHR hits 2356system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 122610 # number of LoadLockedReq MSHR hits 2357system.cpu1.dcache.LoadLockedReq_mshr_hits::total 122610 # number of LoadLockedReq MSHR hits 2358system.cpu1.dcache.demand_mshr_hits::cpu1.data 8381031 # number of demand (read+write) MSHR hits 2359system.cpu1.dcache.demand_mshr_hits::total 8381031 # number of demand (read+write) MSHR hits 2360system.cpu1.dcache.overall_mshr_hits::cpu1.data 8381031 # number of overall MSHR hits 2361system.cpu1.dcache.overall_mshr_hits::total 8381031 # number of overall MSHR hits 2362system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2941031 # number of ReadReq MSHR misses 2363system.cpu1.dcache.ReadReq_mshr_misses::total 2941031 # number of ReadReq MSHR misses 2364system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1278737 # number of WriteReq MSHR misses 2365system.cpu1.dcache.WriteReq_mshr_misses::total 1278737 # number of WriteReq MSHR misses 2366system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 607807 # number of SoftPFReq MSHR misses 2367system.cpu1.dcache.SoftPFReq_mshr_misses::total 607807 # number of SoftPFReq MSHR misses 2368system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 418420 # number of WriteLineReq MSHR misses 2369system.cpu1.dcache.WriteLineReq_mshr_misses::total 418420 # number of WriteLineReq MSHR misses 2370system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 114636 # number of LoadLockedReq MSHR misses 2371system.cpu1.dcache.LoadLockedReq_mshr_misses::total 114636 # number of LoadLockedReq MSHR misses 2372system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 187667 # number of StoreCondReq MSHR misses 2373system.cpu1.dcache.StoreCondReq_mshr_misses::total 187667 # number of StoreCondReq MSHR misses 2374system.cpu1.dcache.demand_mshr_misses::cpu1.data 4638188 # number of demand (read+write) MSHR misses 2375system.cpu1.dcache.demand_mshr_misses::total 4638188 # number of demand (read+write) MSHR misses 2376system.cpu1.dcache.overall_mshr_misses::cpu1.data 5245995 # number of overall MSHR misses 2377system.cpu1.dcache.overall_mshr_misses::total 5245995 # number of overall MSHR misses 2378system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 7218 # number of ReadReq MSHR uncacheable 2379system.cpu1.dcache.ReadReq_mshr_uncacheable::total 7218 # number of ReadReq MSHR uncacheable 2380system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7480 # number of WriteReq MSHR uncacheable 2381system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7480 # number of WriteReq MSHR uncacheable 2382system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14698 # number of overall MSHR uncacheable misses 2383system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14698 # number of overall MSHR uncacheable misses 2384system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 39704145500 # number of ReadReq MSHR miss cycles 2385system.cpu1.dcache.ReadReq_mshr_miss_latency::total 39704145500 # number of ReadReq MSHR miss cycles 2386system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24666220214 # number of WriteReq MSHR miss cycles 2387system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24666220214 # number of WriteReq MSHR miss cycles 2388system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14600377000 # number of SoftPFReq MSHR miss cycles 2389system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14600377000 # number of SoftPFReq MSHR miss cycles 2390system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9957787421 # number of WriteLineReq MSHR miss cycles 2391system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9957787421 # number of WriteLineReq MSHR miss cycles 2392system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1521960000 # number of LoadLockedReq MSHR miss cycles 2393system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1521960000 # number of LoadLockedReq MSHR miss cycles 2394system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4481476500 # number of StoreCondReq MSHR miss cycles 2395system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4481476500 # number of StoreCondReq MSHR miss cycles 2396system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3456000 # number of StoreCondFailReq MSHR miss cycles 2397system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3456000 # number of StoreCondFailReq MSHR miss cycles 2398system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 74328153135 # number of demand (read+write) MSHR miss cycles 2399system.cpu1.dcache.demand_mshr_miss_latency::total 74328153135 # number of demand (read+write) MSHR miss cycles 2400system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 88928530135 # number of overall MSHR miss cycles 2401system.cpu1.dcache.overall_mshr_miss_latency::total 88928530135 # number of overall MSHR miss cycles 2402system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 880126000 # number of ReadReq MSHR uncacheable cycles 2403system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 880126000 # number of ReadReq MSHR uncacheable cycles 2404system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 880126000 # number of overall MSHR uncacheable cycles 2405system.cpu1.dcache.overall_mshr_uncacheable_latency::total 880126000 # number of overall MSHR uncacheable cycles 2406system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.019453 # mshr miss rate for ReadReq accesses 2407system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.019453 # mshr miss rate for ReadReq accesses 2408system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018373 # mshr miss rate for WriteReq accesses 2409system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018373 # mshr miss rate for WriteReq accesses 2410system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.783737 # mshr miss rate for SoftPFReq accesses 2411system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.783737 # mshr miss rate for SoftPFReq accesses 2412system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.777822 # mshr miss rate for WriteLineReq accesses 2413system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.777822 # mshr miss rate for WriteLineReq accesses 2414system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058525 # mshr miss rate for LoadLockedReq accesses 2415system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.058525 # mshr miss rate for LoadLockedReq accesses 2416system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097919 # mshr miss rate for StoreCondReq accesses 2417system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097919 # mshr miss rate for StoreCondReq accesses 2418system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.020957 # mshr miss rate for demand accesses 2419system.cpu1.dcache.demand_mshr_miss_rate::total 0.020957 # mshr miss rate for demand accesses 2420system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.023620 # mshr miss rate for overall accesses 2421system.cpu1.dcache.overall_mshr_miss_rate::total 0.023620 # mshr miss rate for overall accesses 2422system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13500.077184 # average ReadReq mshr miss latency 2423system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13500.077184 # average ReadReq mshr miss latency 2424system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19289.517871 # average WriteReq mshr miss latency 2425system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19289.517871 # average WriteReq mshr miss latency 2426system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24021.403176 # average SoftPFReq mshr miss latency 2427system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24021.403176 # average SoftPFReq mshr miss latency 2428system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23798.545531 # average WriteLineReq mshr miss latency 2429system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23798.545531 # average WriteLineReq mshr miss latency 2430system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13276.457657 # average LoadLockedReq mshr miss latency 2431system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13276.457657 # average LoadLockedReq mshr miss latency 2432system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23879.938934 # average StoreCondReq mshr miss latency 2433system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23879.938934 # average StoreCondReq mshr miss latency 2434system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2435system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 2436system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16025.256659 # average overall mshr miss latency 2437system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16025.256659 # average overall mshr miss latency 2438system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16951.699370 # average overall mshr miss latency 2439system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16951.699370 # average overall mshr miss latency 2440system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 121934.885010 # average ReadReq mshr uncacheable latency 2441system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 121934.885010 # average ReadReq mshr uncacheable latency 2442system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 59880.664036 # average overall mshr uncacheable latency 2443system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 59880.664036 # average overall mshr uncacheable latency 2444system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 2445system.cpu1.icache.tags.replacements 5706197 # number of replacements 2446system.cpu1.icache.tags.tagsinuse 501.707809 # Cycle average of tags in use 2447system.cpu1.icache.tags.total_refs 258521982 # Total number of references to valid blocks. 2448system.cpu1.icache.tags.sampled_refs 5706709 # Sample count of references to valid blocks. 2449system.cpu1.icache.tags.avg_refs 45.301413 # Average number of references to valid blocks. 2450system.cpu1.icache.tags.warmup_cycle 8517122288000 # Cycle when the warmup percentage was hit. 2451system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.707809 # Average occupied blocks per requestor 2452system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979898 # Average percentage of cache occupancy 2453system.cpu1.icache.tags.occ_percent::total 0.979898 # Average percentage of cache occupancy 2454system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2455system.cpu1.icache.tags.age_task_id_blocks_1024::0 307 # Occupied blocks per task id 2456system.cpu1.icache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id 2457system.cpu1.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id 2458system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2459system.cpu1.icache.tags.tag_accesses 534817167 # Number of tag accesses 2460system.cpu1.icache.tags.data_accesses 534817167 # Number of data accesses 2461system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 2462system.cpu1.icache.ReadReq_hits::cpu1.inst 258521982 # number of ReadReq hits 2463system.cpu1.icache.ReadReq_hits::total 258521982 # number of ReadReq hits 2464system.cpu1.icache.demand_hits::cpu1.inst 258521982 # number of demand (read+write) hits 2465system.cpu1.icache.demand_hits::total 258521982 # number of demand (read+write) hits 2466system.cpu1.icache.overall_hits::cpu1.inst 258521982 # number of overall hits 2467system.cpu1.icache.overall_hits::total 258521982 # number of overall hits 2468system.cpu1.icache.ReadReq_misses::cpu1.inst 6033199 # number of ReadReq misses 2469system.cpu1.icache.ReadReq_misses::total 6033199 # number of ReadReq misses 2470system.cpu1.icache.demand_misses::cpu1.inst 6033199 # number of demand (read+write) misses 2471system.cpu1.icache.demand_misses::total 6033199 # number of demand (read+write) misses 2472system.cpu1.icache.overall_misses::cpu1.inst 6033199 # number of overall misses 2473system.cpu1.icache.overall_misses::total 6033199 # number of overall misses 2474system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 64071626251 # number of ReadReq miss cycles 2475system.cpu1.icache.ReadReq_miss_latency::total 64071626251 # number of ReadReq miss cycles 2476system.cpu1.icache.demand_miss_latency::cpu1.inst 64071626251 # number of demand (read+write) miss cycles 2477system.cpu1.icache.demand_miss_latency::total 64071626251 # number of demand (read+write) miss cycles 2478system.cpu1.icache.overall_miss_latency::cpu1.inst 64071626251 # number of overall miss cycles 2479system.cpu1.icache.overall_miss_latency::total 64071626251 # number of overall miss cycles 2480system.cpu1.icache.ReadReq_accesses::cpu1.inst 264555181 # number of ReadReq accesses(hits+misses) 2481system.cpu1.icache.ReadReq_accesses::total 264555181 # number of ReadReq accesses(hits+misses) 2482system.cpu1.icache.demand_accesses::cpu1.inst 264555181 # number of demand (read+write) accesses 2483system.cpu1.icache.demand_accesses::total 264555181 # number of demand (read+write) accesses 2484system.cpu1.icache.overall_accesses::cpu1.inst 264555181 # number of overall (read+write) accesses 2485system.cpu1.icache.overall_accesses::total 264555181 # number of overall (read+write) accesses 2486system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022805 # miss rate for ReadReq accesses 2487system.cpu1.icache.ReadReq_miss_rate::total 0.022805 # miss rate for ReadReq accesses 2488system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022805 # miss rate for demand accesses 2489system.cpu1.icache.demand_miss_rate::total 0.022805 # miss rate for demand accesses 2490system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022805 # miss rate for overall accesses 2491system.cpu1.icache.overall_miss_rate::total 0.022805 # miss rate for overall accesses 2492system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10619.843014 # average ReadReq miss latency 2493system.cpu1.icache.ReadReq_avg_miss_latency::total 10619.843014 # average ReadReq miss latency 2494system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10619.843014 # average overall miss latency 2495system.cpu1.icache.demand_avg_miss_latency::total 10619.843014 # average overall miss latency 2496system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10619.843014 # average overall miss latency 2497system.cpu1.icache.overall_avg_miss_latency::total 10619.843014 # average overall miss latency 2498system.cpu1.icache.blocked_cycles::no_mshrs 9429094 # number of cycles access was blocked 2499system.cpu1.icache.blocked_cycles::no_targets 244 # number of cycles access was blocked 2500system.cpu1.icache.blocked::no_mshrs 708482 # number of cycles access was blocked 2501system.cpu1.icache.blocked::no_targets 4 # number of cycles access was blocked 2502system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.308869 # average number of cycles each access was blocked 2503system.cpu1.icache.avg_blocked_cycles::no_targets 61 # average number of cycles each access was blocked 2504system.cpu1.icache.writebacks::writebacks 5706197 # number of writebacks 2505system.cpu1.icache.writebacks::total 5706197 # number of writebacks 2506system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 326394 # number of ReadReq MSHR hits 2507system.cpu1.icache.ReadReq_mshr_hits::total 326394 # number of ReadReq MSHR hits 2508system.cpu1.icache.demand_mshr_hits::cpu1.inst 326394 # number of demand (read+write) MSHR hits 2509system.cpu1.icache.demand_mshr_hits::total 326394 # number of demand (read+write) MSHR hits 2510system.cpu1.icache.overall_mshr_hits::cpu1.inst 326394 # number of overall MSHR hits 2511system.cpu1.icache.overall_mshr_hits::total 326394 # number of overall MSHR hits 2512system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5706805 # number of ReadReq MSHR misses 2513system.cpu1.icache.ReadReq_mshr_misses::total 5706805 # number of ReadReq MSHR misses 2514system.cpu1.icache.demand_mshr_misses::cpu1.inst 5706805 # number of demand (read+write) MSHR misses 2515system.cpu1.icache.demand_mshr_misses::total 5706805 # number of demand (read+write) MSHR misses 2516system.cpu1.icache.overall_mshr_misses::cpu1.inst 5706805 # number of overall MSHR misses 2517system.cpu1.icache.overall_mshr_misses::total 5706805 # number of overall MSHR misses 2518system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable 2519system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable 2520system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses 2521system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses 2522system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 58058775330 # number of ReadReq MSHR miss cycles 2523system.cpu1.icache.ReadReq_mshr_miss_latency::total 58058775330 # number of ReadReq MSHR miss cycles 2524system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 58058775330 # number of demand (read+write) MSHR miss cycles 2525system.cpu1.icache.demand_mshr_miss_latency::total 58058775330 # number of demand (read+write) MSHR miss cycles 2526system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 58058775330 # number of overall MSHR miss cycles 2527system.cpu1.icache.overall_mshr_miss_latency::total 58058775330 # number of overall MSHR miss cycles 2528system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6679498 # number of ReadReq MSHR uncacheable cycles 2529system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6679498 # number of ReadReq MSHR uncacheable cycles 2530system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6679498 # number of overall MSHR uncacheable cycles 2531system.cpu1.icache.overall_mshr_uncacheable_latency::total 6679498 # number of overall MSHR uncacheable cycles 2532system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.021571 # mshr miss rate for ReadReq accesses 2533system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.021571 # mshr miss rate for ReadReq accesses 2534system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.021571 # mshr miss rate for demand accesses 2535system.cpu1.icache.demand_mshr_miss_rate::total 0.021571 # mshr miss rate for demand accesses 2536system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.021571 # mshr miss rate for overall accesses 2537system.cpu1.icache.overall_mshr_miss_rate::total 0.021571 # mshr miss rate for overall accesses 2538system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10173.604202 # average ReadReq mshr miss latency 2539system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10173.604202 # average ReadReq mshr miss latency 2540system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10173.604202 # average overall mshr miss latency 2541system.cpu1.icache.demand_avg_mshr_miss_latency::total 10173.604202 # average overall mshr miss latency 2542system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10173.604202 # average overall mshr miss latency 2543system.cpu1.icache.overall_avg_mshr_miss_latency::total 10173.604202 # average overall mshr miss latency 2544system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 99694 # average ReadReq mshr uncacheable latency 2545system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 99694 # average ReadReq mshr uncacheable latency 2546system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 99694 # average overall mshr uncacheable latency 2547system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 99694 # average overall mshr uncacheable latency 2548system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 2549system.cpu1.l2cache.prefetcher.num_hwpf_issued 6901811 # number of hwpf issued 2550system.cpu1.l2cache.prefetcher.pfIdentified 6907587 # number of prefetch candidates identified 2551system.cpu1.l2cache.prefetcher.pfBufferHit 5314 # number of redundant prefetches already in prefetch queue 2552system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 2553system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 2554system.cpu1.l2cache.prefetcher.pfSpanPage 821749 # number of prefetches not generated due to page crossing 2555system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 2556system.cpu1.l2cache.tags.replacements 2026075 # number of replacements 2557system.cpu1.l2cache.tags.tagsinuse 13356.542127 # Cycle average of tags in use 2558system.cpu1.l2cache.tags.total_refs 16274118 # Total number of references to valid blocks. 2559system.cpu1.l2cache.tags.sampled_refs 2041771 # Sample count of references to valid blocks. 2560system.cpu1.l2cache.tags.avg_refs 7.970589 # Average number of references to valid blocks. 2561system.cpu1.l2cache.tags.warmup_cycle 9992426830500 # Cycle when the warmup percentage was hit. 2562system.cpu1.l2cache.tags.occ_blocks::writebacks 12440.422172 # Average occupied blocks per requestor 2563system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 43.172118 # Average occupied blocks per requestor 2564system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 33.879322 # Average occupied blocks per requestor 2565system.cpu1.l2cache.tags.occ_blocks::cpu1.data 0.000015 # Average occupied blocks per requestor 2566system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 839.068499 # Average occupied blocks per requestor 2567system.cpu1.l2cache.tags.occ_percent::writebacks 0.759303 # Average percentage of cache occupancy 2568system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002635 # Average percentage of cache occupancy 2569system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.002068 # Average percentage of cache occupancy 2570system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.000000 # Average percentage of cache occupancy 2571system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.051213 # Average percentage of cache occupancy 2572system.cpu1.l2cache.tags.occ_percent::total 0.815219 # Average percentage of cache occupancy 2573system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1386 # Occupied blocks per task id 2574system.cpu1.l2cache.tags.occ_task_id_blocks::1023 96 # Occupied blocks per task id 2575system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14214 # Occupied blocks per task id 2576system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 75 # Occupied blocks per task id 2577system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 230 # Occupied blocks per task id 2578system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 627 # Occupied blocks per task id 2579system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 454 # Occupied blocks per task id 2580system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id 2581system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 79 # Occupied blocks per task id 2582system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id 2583system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id 2584system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 211 # Occupied blocks per task id 2585system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 797 # Occupied blocks per task id 2586system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4633 # Occupied blocks per task id 2587system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4798 # Occupied blocks per task id 2588system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3775 # Occupied blocks per task id 2589system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.084595 # Percentage of cache occupancy per task id 2590system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005859 # Percentage of cache occupancy per task id 2591system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.867554 # Percentage of cache occupancy per task id 2592system.cpu1.l2cache.tags.tag_accesses 369100514 # Number of tag accesses 2593system.cpu1.l2cache.tags.data_accesses 369100514 # Number of data accesses 2594system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 2595system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 546957 # number of ReadReq hits 2596system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 179929 # number of ReadReq hits 2597system.cpu1.l2cache.ReadReq_hits::total 726886 # number of ReadReq hits 2598system.cpu1.l2cache.WritebackDirty_hits::writebacks 3170558 # number of WritebackDirty hits 2599system.cpu1.l2cache.WritebackDirty_hits::total 3170558 # number of WritebackDirty hits 2600system.cpu1.l2cache.WritebackClean_hits::writebacks 7581614 # number of WritebackClean hits 2601system.cpu1.l2cache.WritebackClean_hits::total 7581614 # number of WritebackClean hits 2602system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 544 # number of UpgradeReq hits 2603system.cpu1.l2cache.UpgradeReq_hits::total 544 # number of UpgradeReq hits 2604system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 2 # number of SCUpgradeReq hits 2605system.cpu1.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits 2606system.cpu1.l2cache.ReadExReq_hits::cpu1.data 815108 # number of ReadExReq hits 2607system.cpu1.l2cache.ReadExReq_hits::total 815108 # number of ReadExReq hits 2608system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5173102 # number of ReadCleanReq hits 2609system.cpu1.l2cache.ReadCleanReq_hits::total 5173102 # number of ReadCleanReq hits 2610system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2742764 # number of ReadSharedReq hits 2611system.cpu1.l2cache.ReadSharedReq_hits::total 2742764 # number of ReadSharedReq hits 2612system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 184198 # number of InvalidateReq hits 2613system.cpu1.l2cache.InvalidateReq_hits::total 184198 # number of InvalidateReq hits 2614system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 546957 # number of demand (read+write) hits 2615system.cpu1.l2cache.demand_hits::cpu1.itb.walker 179929 # number of demand (read+write) hits 2616system.cpu1.l2cache.demand_hits::cpu1.inst 5173102 # number of demand (read+write) hits 2617system.cpu1.l2cache.demand_hits::cpu1.data 3557872 # number of demand (read+write) hits 2618system.cpu1.l2cache.demand_hits::total 9457860 # number of demand (read+write) hits 2619system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 546957 # number of overall hits 2620system.cpu1.l2cache.overall_hits::cpu1.itb.walker 179929 # number of overall hits 2621system.cpu1.l2cache.overall_hits::cpu1.inst 5173102 # number of overall hits 2622system.cpu1.l2cache.overall_hits::cpu1.data 3557872 # number of overall hits 2623system.cpu1.l2cache.overall_hits::total 9457860 # number of overall hits 2624system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11826 # number of ReadReq misses 2625system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8080 # number of ReadReq misses 2626system.cpu1.l2cache.ReadReq_misses::total 19906 # number of ReadReq misses 2627system.cpu1.l2cache.WritebackDirty_misses::writebacks 4 # number of WritebackDirty misses 2628system.cpu1.l2cache.WritebackDirty_misses::total 4 # number of WritebackDirty misses 2629system.cpu1.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses 2630system.cpu1.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses 2631system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 224180 # number of UpgradeReq misses 2632system.cpu1.l2cache.UpgradeReq_misses::total 224180 # number of UpgradeReq misses 2633system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 187653 # number of SCUpgradeReq misses 2634system.cpu1.l2cache.SCUpgradeReq_misses::total 187653 # number of SCUpgradeReq misses 2635system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 12 # number of SCUpgradeFailReq misses 2636system.cpu1.l2cache.SCUpgradeFailReq_misses::total 12 # number of SCUpgradeFailReq misses 2637system.cpu1.l2cache.ReadExReq_misses::cpu1.data 246832 # number of ReadExReq misses 2638system.cpu1.l2cache.ReadExReq_misses::total 246832 # number of ReadExReq misses 2639system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 533612 # number of ReadCleanReq misses 2640system.cpu1.l2cache.ReadCleanReq_misses::total 533612 # number of ReadCleanReq misses 2641system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 917456 # number of ReadSharedReq misses 2642system.cpu1.l2cache.ReadSharedReq_misses::total 917456 # number of ReadSharedReq misses 2643system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 232409 # number of InvalidateReq misses 2644system.cpu1.l2cache.InvalidateReq_misses::total 232409 # number of InvalidateReq misses 2645system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11826 # number of demand (read+write) misses 2646system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8080 # number of demand (read+write) misses 2647system.cpu1.l2cache.demand_misses::cpu1.inst 533612 # number of demand (read+write) misses 2648system.cpu1.l2cache.demand_misses::cpu1.data 1164288 # number of demand (read+write) misses 2649system.cpu1.l2cache.demand_misses::total 1717806 # number of demand (read+write) misses 2650system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11826 # number of overall misses 2651system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8080 # number of overall misses 2652system.cpu1.l2cache.overall_misses::cpu1.inst 533612 # number of overall misses 2653system.cpu1.l2cache.overall_misses::cpu1.data 1164288 # number of overall misses 2654system.cpu1.l2cache.overall_misses::total 1717806 # number of overall misses 2655system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 438373000 # number of ReadReq miss cycles 2656system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 291991000 # number of ReadReq miss cycles 2657system.cpu1.l2cache.ReadReq_miss_latency::total 730364000 # number of ReadReq miss cycles 2658system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2034074000 # number of UpgradeReq miss cycles 2659system.cpu1.l2cache.UpgradeReq_miss_latency::total 2034074000 # number of UpgradeReq miss cycles 2660system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1455556000 # number of SCUpgradeReq miss cycles 2661system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1455556000 # number of SCUpgradeReq miss cycles 2662system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3356498 # number of SCUpgradeFailReq miss cycles 2663system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3356498 # number of SCUpgradeFailReq miss cycles 2664system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10810838997 # number of ReadExReq miss cycles 2665system.cpu1.l2cache.ReadExReq_miss_latency::total 10810838997 # number of ReadExReq miss cycles 2666system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 18150969000 # number of ReadCleanReq miss cycles 2667system.cpu1.l2cache.ReadCleanReq_miss_latency::total 18150969000 # number of ReadCleanReq miss cycles 2668system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 32024307483 # number of ReadSharedReq miss cycles 2669system.cpu1.l2cache.ReadSharedReq_miss_latency::total 32024307483 # number of ReadSharedReq miss cycles 2670system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 362347000 # number of InvalidateReq miss cycles 2671system.cpu1.l2cache.InvalidateReq_miss_latency::total 362347000 # number of InvalidateReq miss cycles 2672system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 438373000 # number of demand (read+write) miss cycles 2673system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 291991000 # number of demand (read+write) miss cycles 2674system.cpu1.l2cache.demand_miss_latency::cpu1.inst 18150969000 # number of demand (read+write) miss cycles 2675system.cpu1.l2cache.demand_miss_latency::cpu1.data 42835146480 # number of demand (read+write) miss cycles 2676system.cpu1.l2cache.demand_miss_latency::total 61716479480 # number of demand (read+write) miss cycles 2677system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 438373000 # number of overall miss cycles 2678system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 291991000 # number of overall miss cycles 2679system.cpu1.l2cache.overall_miss_latency::cpu1.inst 18150969000 # number of overall miss cycles 2680system.cpu1.l2cache.overall_miss_latency::cpu1.data 42835146480 # number of overall miss cycles 2681system.cpu1.l2cache.overall_miss_latency::total 61716479480 # number of overall miss cycles 2682system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 558783 # number of ReadReq accesses(hits+misses) 2683system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 188009 # number of ReadReq accesses(hits+misses) 2684system.cpu1.l2cache.ReadReq_accesses::total 746792 # number of ReadReq accesses(hits+misses) 2685system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3170562 # number of WritebackDirty accesses(hits+misses) 2686system.cpu1.l2cache.WritebackDirty_accesses::total 3170562 # number of WritebackDirty accesses(hits+misses) 2687system.cpu1.l2cache.WritebackClean_accesses::writebacks 7581615 # number of WritebackClean accesses(hits+misses) 2688system.cpu1.l2cache.WritebackClean_accesses::total 7581615 # number of WritebackClean accesses(hits+misses) 2689system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 224724 # number of UpgradeReq accesses(hits+misses) 2690system.cpu1.l2cache.UpgradeReq_accesses::total 224724 # number of UpgradeReq accesses(hits+misses) 2691system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 187655 # number of SCUpgradeReq accesses(hits+misses) 2692system.cpu1.l2cache.SCUpgradeReq_accesses::total 187655 # number of SCUpgradeReq accesses(hits+misses) 2693system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 12 # number of SCUpgradeFailReq accesses(hits+misses) 2694system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 12 # number of SCUpgradeFailReq accesses(hits+misses) 2695system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1061940 # number of ReadExReq accesses(hits+misses) 2696system.cpu1.l2cache.ReadExReq_accesses::total 1061940 # number of ReadExReq accesses(hits+misses) 2697system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5706714 # number of ReadCleanReq accesses(hits+misses) 2698system.cpu1.l2cache.ReadCleanReq_accesses::total 5706714 # number of ReadCleanReq accesses(hits+misses) 2699system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3660220 # number of ReadSharedReq accesses(hits+misses) 2700system.cpu1.l2cache.ReadSharedReq_accesses::total 3660220 # number of ReadSharedReq accesses(hits+misses) 2701system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 416607 # number of InvalidateReq accesses(hits+misses) 2702system.cpu1.l2cache.InvalidateReq_accesses::total 416607 # number of InvalidateReq accesses(hits+misses) 2703system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 558783 # number of demand (read+write) accesses 2704system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 188009 # number of demand (read+write) accesses 2705system.cpu1.l2cache.demand_accesses::cpu1.inst 5706714 # number of demand (read+write) accesses 2706system.cpu1.l2cache.demand_accesses::cpu1.data 4722160 # number of demand (read+write) accesses 2707system.cpu1.l2cache.demand_accesses::total 11175666 # number of demand (read+write) accesses 2708system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 558783 # number of overall (read+write) accesses 2709system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 188009 # number of overall (read+write) accesses 2710system.cpu1.l2cache.overall_accesses::cpu1.inst 5706714 # number of overall (read+write) accesses 2711system.cpu1.l2cache.overall_accesses::cpu1.data 4722160 # number of overall (read+write) accesses 2712system.cpu1.l2cache.overall_accesses::total 11175666 # number of overall (read+write) accesses 2713system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021164 # miss rate for ReadReq accesses 2714system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.042977 # miss rate for ReadReq accesses 2715system.cpu1.l2cache.ReadReq_miss_rate::total 0.026655 # miss rate for ReadReq accesses 2716system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses 2717system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses 2718system.cpu1.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses 2719system.cpu1.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses 2720system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.997579 # miss rate for UpgradeReq accesses 2721system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.997579 # miss rate for UpgradeReq accesses 2722system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.999989 # miss rate for SCUpgradeReq accesses 2723system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.999989 # miss rate for SCUpgradeReq accesses 2724system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2725system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2726system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.232435 # miss rate for ReadExReq accesses 2727system.cpu1.l2cache.ReadExReq_miss_rate::total 0.232435 # miss rate for ReadExReq accesses 2728system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.093506 # miss rate for ReadCleanReq accesses 2729system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.093506 # miss rate for ReadCleanReq accesses 2730system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.250656 # miss rate for ReadSharedReq accesses 2731system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.250656 # miss rate for ReadSharedReq accesses 2732system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.557861 # miss rate for InvalidateReq accesses 2733system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.557861 # miss rate for InvalidateReq accesses 2734system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021164 # miss rate for demand accesses 2735system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.042977 # miss rate for demand accesses 2736system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.093506 # miss rate for demand accesses 2737system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.246558 # miss rate for demand accesses 2738system.cpu1.l2cache.demand_miss_rate::total 0.153709 # miss rate for demand accesses 2739system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021164 # miss rate for overall accesses 2740system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.042977 # miss rate for overall accesses 2741system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.093506 # miss rate for overall accesses 2742system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.246558 # miss rate for overall accesses 2743system.cpu1.l2cache.overall_miss_rate::total 0.153709 # miss rate for overall accesses 2744system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 37068.577710 # average ReadReq miss latency 2745system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 36137.500000 # average ReadReq miss latency 2746system.cpu1.l2cache.ReadReq_avg_miss_latency::total 36690.646036 # average ReadReq miss latency 2747system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 9073.396378 # average UpgradeReq miss latency 2748system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 9073.396378 # average UpgradeReq miss latency 2749system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 7756.635918 # average SCUpgradeReq miss latency 2750system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 7756.635918 # average SCUpgradeReq miss latency 2751system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 279708.166667 # average SCUpgradeFailReq miss latency 2752system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 279708.166667 # average SCUpgradeFailReq miss latency 2753system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43798.368919 # average ReadExReq miss latency 2754system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43798.368919 # average ReadExReq miss latency 2755system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 34015.293884 # average ReadCleanReq miss latency 2756system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 34015.293884 # average ReadCleanReq miss latency 2757system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 34905.551310 # average ReadSharedReq miss latency 2758system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 34905.551310 # average ReadSharedReq miss latency 2759system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1559.091946 # average InvalidateReq miss latency 2760system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1559.091946 # average InvalidateReq miss latency 2761system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 37068.577710 # average overall miss latency 2762system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 36137.500000 # average overall miss latency 2763system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34015.293884 # average overall miss latency 2764system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 36790.851130 # average overall miss latency 2765system.cpu1.l2cache.demand_avg_miss_latency::total 35927.502570 # average overall miss latency 2766system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 37068.577710 # average overall miss latency 2767system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 36137.500000 # average overall miss latency 2768system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34015.293884 # average overall miss latency 2769system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 36790.851130 # average overall miss latency 2770system.cpu1.l2cache.overall_avg_miss_latency::total 35927.502570 # average overall miss latency 2771system.cpu1.l2cache.blocked_cycles::no_mshrs 264 # number of cycles access was blocked 2772system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2773system.cpu1.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked 2774system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2775system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 52.800000 # average number of cycles each access was blocked 2776system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2777system.cpu1.l2cache.unused_prefetches 40814 # number of HardPF blocks evicted w/o reference 2778system.cpu1.l2cache.writebacks::writebacks 1038265 # number of writebacks 2779system.cpu1.l2cache.writebacks::total 1038265 # number of writebacks 2780system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 3 # number of ReadReq MSHR hits 2781system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 8 # number of ReadReq MSHR hits 2782system.cpu1.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits 2783system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 9551 # number of ReadExReq MSHR hits 2784system.cpu1.l2cache.ReadExReq_mshr_hits::total 9551 # number of ReadExReq MSHR hits 2785system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 1 # number of ReadCleanReq MSHR hits 2786system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 2787system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 4369 # number of ReadSharedReq MSHR hits 2788system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 4369 # number of ReadSharedReq MSHR hits 2789system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 3 # number of demand (read+write) MSHR hits 2790system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 8 # number of demand (read+write) MSHR hits 2791system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits 2792system.cpu1.l2cache.demand_mshr_hits::cpu1.data 13920 # number of demand (read+write) MSHR hits 2793system.cpu1.l2cache.demand_mshr_hits::total 13932 # number of demand (read+write) MSHR hits 2794system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 3 # number of overall MSHR hits 2795system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 8 # number of overall MSHR hits 2796system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits 2797system.cpu1.l2cache.overall_mshr_hits::cpu1.data 13920 # number of overall MSHR hits 2798system.cpu1.l2cache.overall_mshr_hits::total 13932 # number of overall MSHR hits 2799system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 11823 # number of ReadReq MSHR misses 2800system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8072 # number of ReadReq MSHR misses 2801system.cpu1.l2cache.ReadReq_mshr_misses::total 19895 # number of ReadReq MSHR misses 2802system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 4 # number of WritebackDirty MSHR misses 2803system.cpu1.l2cache.WritebackDirty_mshr_misses::total 4 # number of WritebackDirty MSHR misses 2804system.cpu1.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses 2805system.cpu1.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses 2806system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 718321 # number of HardPFReq MSHR misses 2807system.cpu1.l2cache.HardPFReq_mshr_misses::total 718321 # number of HardPFReq MSHR misses 2808system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 224180 # number of UpgradeReq MSHR misses 2809system.cpu1.l2cache.UpgradeReq_mshr_misses::total 224180 # number of UpgradeReq MSHR misses 2810system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 187653 # number of SCUpgradeReq MSHR misses 2811system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 187653 # number of SCUpgradeReq MSHR misses 2812system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 12 # number of SCUpgradeFailReq MSHR misses 2813system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 12 # number of SCUpgradeFailReq MSHR misses 2814system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 237281 # number of ReadExReq MSHR misses 2815system.cpu1.l2cache.ReadExReq_mshr_misses::total 237281 # number of ReadExReq MSHR misses 2816system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 533611 # number of ReadCleanReq MSHR misses 2817system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 533611 # number of ReadCleanReq MSHR misses 2818system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 913087 # number of ReadSharedReq MSHR misses 2819system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 913087 # number of ReadSharedReq MSHR misses 2820system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 232409 # number of InvalidateReq MSHR misses 2821system.cpu1.l2cache.InvalidateReq_mshr_misses::total 232409 # number of InvalidateReq MSHR misses 2822system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 11823 # number of demand (read+write) MSHR misses 2823system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8072 # number of demand (read+write) MSHR misses 2824system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 533611 # number of demand (read+write) MSHR misses 2825system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1150368 # number of demand (read+write) MSHR misses 2826system.cpu1.l2cache.demand_mshr_misses::total 1703874 # number of demand (read+write) MSHR misses 2827system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 11823 # number of overall MSHR misses 2828system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8072 # number of overall MSHR misses 2829system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 533611 # number of overall MSHR misses 2830system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1150368 # number of overall MSHR misses 2831system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 718321 # number of overall MSHR misses 2832system.cpu1.l2cache.overall_mshr_misses::total 2422195 # number of overall MSHR misses 2833system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable 2834system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 7218 # number of ReadReq MSHR uncacheable 2835system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 7285 # number of ReadReq MSHR uncacheable 2836system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 7480 # number of WriteReq MSHR uncacheable 2837system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 7480 # number of WriteReq MSHR uncacheable 2838system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses 2839system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 14698 # number of overall MSHR uncacheable misses 2840system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 14765 # number of overall MSHR uncacheable misses 2841system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 367372500 # number of ReadReq MSHR miss cycles 2842system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 243371500 # number of ReadReq MSHR miss cycles 2843system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 610744000 # number of ReadReq MSHR miss cycles 2844system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 32165766903 # number of HardPFReq MSHR miss cycles 2845system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 32165766903 # number of HardPFReq MSHR miss cycles 2846system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4735558998 # number of UpgradeReq MSHR miss cycles 2847system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4735558998 # number of UpgradeReq MSHR miss cycles 2848system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3071141498 # number of SCUpgradeReq MSHR miss cycles 2849system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3071141498 # number of SCUpgradeReq MSHR miss cycles 2850system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2966498 # number of SCUpgradeFailReq MSHR miss cycles 2851system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2966498 # number of SCUpgradeFailReq MSHR miss cycles 2852system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8013535997 # number of ReadExReq MSHR miss cycles 2853system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8013535997 # number of ReadExReq MSHR miss cycles 2854system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 14949290000 # number of ReadCleanReq MSHR miss cycles 2855system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 14949290000 # number of ReadCleanReq MSHR miss cycles 2856system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 26287930983 # number of ReadSharedReq MSHR miss cycles 2857system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 26287930983 # number of ReadSharedReq MSHR miss cycles 2858system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6248930499 # number of InvalidateReq MSHR miss cycles 2859system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6248930499 # number of InvalidateReq MSHR miss cycles 2860system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 367372500 # number of demand (read+write) MSHR miss cycles 2861system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 243371500 # number of demand (read+write) MSHR miss cycles 2862system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 14949290000 # number of demand (read+write) MSHR miss cycles 2863system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 34301466980 # number of demand (read+write) MSHR miss cycles 2864system.cpu1.l2cache.demand_mshr_miss_latency::total 49861500980 # number of demand (read+write) MSHR miss cycles 2865system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 367372500 # number of overall MSHR miss cycles 2866system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 243371500 # number of overall MSHR miss cycles 2867system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 14949290000 # number of overall MSHR miss cycles 2868system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 34301466980 # number of overall MSHR miss cycles 2869system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 32165766903 # number of overall MSHR miss cycles 2870system.cpu1.l2cache.overall_mshr_miss_latency::total 82027267883 # number of overall MSHR miss cycles 2871system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6176000 # number of ReadReq MSHR uncacheable cycles 2872system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 822175500 # number of ReadReq MSHR uncacheable cycles 2873system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 828351500 # number of ReadReq MSHR uncacheable cycles 2874system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 6176000 # number of overall MSHR uncacheable cycles 2875system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 822175500 # number of overall MSHR uncacheable cycles 2876system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 828351500 # number of overall MSHR uncacheable cycles 2877system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021158 # mshr miss rate for ReadReq accesses 2878system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.042934 # mshr miss rate for ReadReq accesses 2879system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.026641 # mshr miss rate for ReadReq accesses 2880system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses 2881system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses 2882system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses 2883system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses 2884system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2885system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2886system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997579 # mshr miss rate for UpgradeReq accesses 2887system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997579 # mshr miss rate for UpgradeReq accesses 2888system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999989 # mshr miss rate for SCUpgradeReq accesses 2889system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999989 # mshr miss rate for SCUpgradeReq accesses 2890system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2891system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2892system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.223441 # mshr miss rate for ReadExReq accesses 2893system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.223441 # mshr miss rate for ReadExReq accesses 2894system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.093506 # mshr miss rate for ReadCleanReq accesses 2895system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.093506 # mshr miss rate for ReadCleanReq accesses 2896system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.249462 # mshr miss rate for ReadSharedReq accesses 2897system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249462 # mshr miss rate for ReadSharedReq accesses 2898system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.557861 # mshr miss rate for InvalidateReq accesses 2899system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.557861 # mshr miss rate for InvalidateReq accesses 2900system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021158 # mshr miss rate for demand accesses 2901system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.042934 # mshr miss rate for demand accesses 2902system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.093506 # mshr miss rate for demand accesses 2903system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.243611 # mshr miss rate for demand accesses 2904system.cpu1.l2cache.demand_mshr_miss_rate::total 0.152463 # mshr miss rate for demand accesses 2905system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021158 # mshr miss rate for overall accesses 2906system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.042934 # mshr miss rate for overall accesses 2907system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.093506 # mshr miss rate for overall accesses 2908system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.243611 # mshr miss rate for overall accesses 2909system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2910system.cpu1.l2cache.overall_mshr_miss_rate::total 0.216738 # mshr miss rate for overall accesses 2911system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31072.697285 # average ReadReq mshr miss latency 2912system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 30150.086720 # average ReadReq mshr miss latency 2913system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30698.366424 # average ReadReq mshr miss latency 2914system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44779.098624 # average HardPFReq mshr miss latency 2915system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 44779.098624 # average HardPFReq mshr miss latency 2916system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21123.913810 # average UpgradeReq mshr miss latency 2917system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21123.913810 # average UpgradeReq mshr miss latency 2918system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16366.066612 # average SCUpgradeReq mshr miss latency 2919system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16366.066612 # average SCUpgradeReq mshr miss latency 2920system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 247208.166667 # average SCUpgradeFailReq mshr miss latency 2921system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 247208.166667 # average SCUpgradeFailReq mshr miss latency 2922system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33772.345856 # average ReadExReq mshr miss latency 2923system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33772.345856 # average ReadExReq mshr miss latency 2924system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 28015.333267 # average ReadCleanReq mshr miss latency 2925system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28015.333267 # average ReadCleanReq mshr miss latency 2926system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28790.171126 # average ReadSharedReq mshr miss latency 2927system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28790.171126 # average ReadSharedReq mshr miss latency 2928system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26887.644192 # average InvalidateReq mshr miss latency 2929system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26887.644192 # average InvalidateReq mshr miss latency 2930system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31072.697285 # average overall mshr miss latency 2931system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 30150.086720 # average overall mshr miss latency 2932system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28015.333267 # average overall mshr miss latency 2933system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 29817.820889 # average overall mshr miss latency 2934system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29263.608095 # average overall mshr miss latency 2935system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31072.697285 # average overall mshr miss latency 2936system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 30150.086720 # average overall mshr miss latency 2937system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28015.333267 # average overall mshr miss latency 2938system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 29817.820889 # average overall mshr miss latency 2939system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44779.098624 # average overall mshr miss latency 2940system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33864.848983 # average overall mshr miss latency 2941system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92179.104478 # average ReadReq mshr uncacheable latency 2942system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 113906.275977 # average ReadReq mshr uncacheable latency 2943system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 113706.451613 # average ReadReq mshr uncacheable latency 2944system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92179.104478 # average overall mshr uncacheable latency 2945system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 55937.916723 # average overall mshr uncacheable latency 2946system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 56102.370471 # average overall mshr uncacheable latency 2947system.cpu1.toL2Bus.snoop_filter.tot_requests 22350657 # Total number of requests made to the snoop filter. 2948system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11505244 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2949system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1543 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2950system.cpu1.toL2Bus.snoop_filter.tot_snoops 1883368 # Total number of snoops made to the snoop filter. 2951system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1883027 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2952system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 341 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2953system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 2954system.cpu1.toL2Bus.trans_dist::ReadReq 842183 # Transaction distribution 2955system.cpu1.toL2Bus.trans_dist::ReadResp 10302833 # Transaction distribution 2956system.cpu1.toL2Bus.trans_dist::WriteReq 7480 # Transaction distribution 2957system.cpu1.toL2Bus.trans_dist::WriteResp 7480 # Transaction distribution 2958system.cpu1.toL2Bus.trans_dist::WritebackDirty 4215889 # Transaction distribution 2959system.cpu1.toL2Bus.trans_dist::WritebackClean 7583095 # Transaction distribution 2960system.cpu1.toL2Bus.trans_dist::CleanEvict 2514473 # Transaction distribution 2961system.cpu1.toL2Bus.trans_dist::HardPFReq 909607 # Transaction distribution 2962system.cpu1.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution 2963system.cpu1.toL2Bus.trans_dist::UpgradeReq 430035 # Transaction distribution 2964system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 341692 # Transaction distribution 2965system.cpu1.toL2Bus.trans_dist::UpgradeResp 476439 # Transaction distribution 2966system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 71 # Transaction distribution 2967system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 124 # Transaction distribution 2968system.cpu1.toL2Bus.trans_dist::ReadExReq 1090279 # Transaction distribution 2969system.cpu1.toL2Bus.trans_dist::ReadExResp 1068076 # Transaction distribution 2970system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5706805 # Transaction distribution 2971system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4656106 # Transaction distribution 2972system.cpu1.toL2Bus.trans_dist::InvalidateReq 474602 # Transaction distribution 2973system.cpu1.toL2Bus.trans_dist::InvalidateResp 416607 # Transaction distribution 2974system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17119850 # Packet count per connected master and slave (bytes) 2975system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16343111 # Packet count per connected master and slave (bytes) 2976system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 395526 # Packet count per connected master and slave (bytes) 2977system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1186164 # Packet count per connected master and slave (bytes) 2978system.cpu1.toL2Bus.pkt_count::total 35044651 # Packet count per connected master and slave (bytes) 2979system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 730427376 # Cumulative packet size per connected master and slave (bytes) 2980system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 631688689 # Cumulative packet size per connected master and slave (bytes) 2981system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1504072 # Cumulative packet size per connected master and slave (bytes) 2982system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4470264 # Cumulative packet size per connected master and slave (bytes) 2983system.cpu1.toL2Bus.pkt_size::total 1368090401 # Cumulative packet size per connected master and slave (bytes) 2984system.cpu1.toL2Bus.snoops 6163170 # Total snoops (count) 2985system.cpu1.toL2Bus.snoopTraffic 73999248 # Total snoop traffic (bytes) 2986system.cpu1.toL2Bus.snoop_fanout::samples 18018661 # Request fanout histogram 2987system.cpu1.toL2Bus.snoop_fanout::mean 0.123449 # Request fanout histogram 2988system.cpu1.toL2Bus.snoop_fanout::stdev 0.329009 # Request fanout histogram 2989system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2990system.cpu1.toL2Bus.snoop_fanout::0 15794619 87.66% 87.66% # Request fanout histogram 2991system.cpu1.toL2Bus.snoop_fanout::1 2223701 12.34% 100.00% # Request fanout histogram 2992system.cpu1.toL2Bus.snoop_fanout::2 341 0.00% 100.00% # Request fanout histogram 2993system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2994system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2995system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2996system.cpu1.toL2Bus.snoop_fanout::total 18018661 # Request fanout histogram 2997system.cpu1.toL2Bus.reqLayer0.occupancy 22188055468 # Layer occupancy (ticks) 2998system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2999system.cpu1.toL2Bus.snoopLayer0.occupancy 182014003 # Layer occupancy (ticks) 3000system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3001system.cpu1.toL2Bus.respLayer0.occupancy 8566090793 # Layer occupancy (ticks) 3002system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3003system.cpu1.toL2Bus.respLayer1.occupancy 7517136176 # Layer occupancy (ticks) 3004system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3005system.cpu1.toL2Bus.respLayer2.occupancy 207825380 # Layer occupancy (ticks) 3006system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 3007system.cpu1.toL2Bus.respLayer3.occupancy 628033176 # Layer occupancy (ticks) 3008system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 3009system.iobus.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 3010system.iobus.trans_dist::ReadReq 40328 # Transaction distribution 3011system.iobus.trans_dist::ReadResp 40328 # Transaction distribution 3012system.iobus.trans_dist::WriteReq 136631 # Transaction distribution 3013system.iobus.trans_dist::WriteResp 136631 # Transaction distribution 3014system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47646 # Packet count per connected master and slave (bytes) 3015system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 3016system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 3017system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 3018system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 3019system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 3020system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 3021system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 3022system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 3023system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 3024system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 3025system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 3026system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 3027system.iobus.pkt_count_system.bridge.master::total 122580 # Packet count per connected master and slave (bytes) 3028system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231258 # Packet count per connected master and slave (bytes) 3029system.iobus.pkt_count_system.realview.ide.dma::total 231258 # Packet count per connected master and slave (bytes) 3030system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 3031system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 3032system.iobus.pkt_count::total 353918 # Packet count per connected master and slave (bytes) 3033system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47666 # Cumulative packet size per connected master and slave (bytes) 3034system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 3035system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 3036system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 3037system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 3038system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 3039system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3040system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3041system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3042system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 3043system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3044system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 3045system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 3046system.iobus.pkt_size_system.bridge.master::total 155687 # Cumulative packet size per connected master and slave (bytes) 3047system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339048 # Cumulative packet size per connected master and slave (bytes) 3048system.iobus.pkt_size_system.realview.ide.dma::total 7339048 # Cumulative packet size per connected master and slave (bytes) 3049system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 3050system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 3051system.iobus.pkt_size::total 7496821 # Cumulative packet size per connected master and slave (bytes) 3052system.iobus.reqLayer0.occupancy 36938002 # Layer occupancy (ticks) 3053system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 3054system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) 3055system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 3056system.iobus.reqLayer2.occupancy 332000 # Layer occupancy (ticks) 3057system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 3058system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) 3059system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 3060system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) 3061system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 3062system.iobus.reqLayer10.occupancy 10500 # Layer occupancy (ticks) 3063system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 3064system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) 3065system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 3066system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) 3067system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 3068system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) 3069system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 3070system.iobus.reqLayer16.occupancy 13500 # Layer occupancy (ticks) 3071system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 3072system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 3073system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 3074system.iobus.reqLayer23.occupancy 24205503 # Layer occupancy (ticks) 3075system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 3076system.iobus.reqLayer24.occupancy 36443500 # Layer occupancy (ticks) 3077system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 3078system.iobus.reqLayer25.occupancy 569408550 # Layer occupancy (ticks) 3079system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 3080system.iobus.respLayer0.occupancy 92680000 # Layer occupancy (ticks) 3081system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 3082system.iobus.respLayer3.occupancy 147954000 # Layer occupancy (ticks) 3083system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 3084system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 3085system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 3086system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 3087system.iocache.tags.replacements 115626 # number of replacements 3088system.iocache.tags.tagsinuse 11.305309 # Cycle average of tags in use 3089system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 3090system.iocache.tags.sampled_refs 115642 # Sample count of references to valid blocks. 3091system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 3092system.iocache.tags.warmup_cycle 9115830406000 # Cycle when the warmup percentage was hit. 3093system.iocache.tags.occ_blocks::realview.ethernet 7.413187 # Average occupied blocks per requestor 3094system.iocache.tags.occ_blocks::realview.ide 3.892123 # Average occupied blocks per requestor 3095system.iocache.tags.occ_percent::realview.ethernet 0.463324 # Average percentage of cache occupancy 3096system.iocache.tags.occ_percent::realview.ide 0.243258 # Average percentage of cache occupancy 3097system.iocache.tags.occ_percent::total 0.706582 # Average percentage of cache occupancy 3098system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 3099system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 3100system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 3101system.iocache.tags.tag_accesses 1041018 # Number of tag accesses 3102system.iocache.tags.data_accesses 1041018 # Number of data accesses 3103system.iocache.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 3104system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 3105system.iocache.ReadReq_misses::realview.ide 8901 # number of ReadReq misses 3106system.iocache.ReadReq_misses::total 8938 # number of ReadReq misses 3107system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 3108system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 3109system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 3110system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 3111system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 3112system.iocache.demand_misses::realview.ide 115629 # number of demand (read+write) misses 3113system.iocache.demand_misses::total 115669 # number of demand (read+write) misses 3114system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 3115system.iocache.overall_misses::realview.ide 115629 # number of overall misses 3116system.iocache.overall_misses::total 115669 # number of overall misses 3117system.iocache.ReadReq_miss_latency::realview.ethernet 5198500 # number of ReadReq miss cycles 3118system.iocache.ReadReq_miss_latency::realview.ide 1667264523 # number of ReadReq miss cycles 3119system.iocache.ReadReq_miss_latency::total 1672463023 # number of ReadReq miss cycles 3120system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 3121system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 3122system.iocache.WriteLineReq_miss_latency::realview.ide 12925157527 # number of WriteLineReq miss cycles 3123system.iocache.WriteLineReq_miss_latency::total 12925157527 # number of WriteLineReq miss cycles 3124system.iocache.demand_miss_latency::realview.ethernet 5567500 # number of demand (read+write) miss cycles 3125system.iocache.demand_miss_latency::realview.ide 14592422050 # number of demand (read+write) miss cycles 3126system.iocache.demand_miss_latency::total 14597989550 # number of demand (read+write) miss cycles 3127system.iocache.overall_miss_latency::realview.ethernet 5567500 # number of overall miss cycles 3128system.iocache.overall_miss_latency::realview.ide 14592422050 # number of overall miss cycles 3129system.iocache.overall_miss_latency::total 14597989550 # number of overall miss cycles 3130system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 3131system.iocache.ReadReq_accesses::realview.ide 8901 # number of ReadReq accesses(hits+misses) 3132system.iocache.ReadReq_accesses::total 8938 # number of ReadReq accesses(hits+misses) 3133system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 3134system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 3135system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 3136system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 3137system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 3138system.iocache.demand_accesses::realview.ide 115629 # number of demand (read+write) accesses 3139system.iocache.demand_accesses::total 115669 # number of demand (read+write) accesses 3140system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 3141system.iocache.overall_accesses::realview.ide 115629 # number of overall (read+write) accesses 3142system.iocache.overall_accesses::total 115669 # number of overall (read+write) accesses 3143system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 3144system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 3145system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 3146system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 3147system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 3148system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 3149system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 3150system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 3151system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 3152system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 3153system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 3154system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 3155system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 3156system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140500 # average ReadReq miss latency 3157system.iocache.ReadReq_avg_miss_latency::realview.ide 187312.046175 # average ReadReq miss latency 3158system.iocache.ReadReq_avg_miss_latency::total 187118.261692 # average ReadReq miss latency 3159system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 3160system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 3161system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121103.717178 # average WriteLineReq miss latency 3162system.iocache.WriteLineReq_avg_miss_latency::total 121103.717178 # average WriteLineReq miss latency 3163system.iocache.demand_avg_miss_latency::realview.ethernet 139187.500000 # average overall miss latency 3164system.iocache.demand_avg_miss_latency::realview.ide 126200.365393 # average overall miss latency 3165system.iocache.demand_avg_miss_latency::total 126204.856530 # average overall miss latency 3166system.iocache.overall_avg_miss_latency::realview.ethernet 139187.500000 # average overall miss latency 3167system.iocache.overall_avg_miss_latency::realview.ide 126200.365393 # average overall miss latency 3168system.iocache.overall_avg_miss_latency::total 126204.856530 # average overall miss latency 3169system.iocache.blocked_cycles::no_mshrs 33241 # number of cycles access was blocked 3170system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3171system.iocache.blocked::no_mshrs 3524 # number of cycles access was blocked 3172system.iocache.blocked::no_targets 0 # number of cycles access was blocked 3173system.iocache.avg_blocked_cycles::no_mshrs 9.432747 # average number of cycles each access was blocked 3174system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3175system.iocache.writebacks::writebacks 106695 # number of writebacks 3176system.iocache.writebacks::total 106695 # number of writebacks 3177system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 3178system.iocache.ReadReq_mshr_misses::realview.ide 8901 # number of ReadReq MSHR misses 3179system.iocache.ReadReq_mshr_misses::total 8938 # number of ReadReq MSHR misses 3180system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 3181system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 3182system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 3183system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 3184system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 3185system.iocache.demand_mshr_misses::realview.ide 115629 # number of demand (read+write) MSHR misses 3186system.iocache.demand_mshr_misses::total 115669 # number of demand (read+write) MSHR misses 3187system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 3188system.iocache.overall_mshr_misses::realview.ide 115629 # number of overall MSHR misses 3189system.iocache.overall_mshr_misses::total 115669 # number of overall MSHR misses 3190system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348500 # number of ReadReq MSHR miss cycles 3191system.iocache.ReadReq_mshr_miss_latency::realview.ide 1222214523 # number of ReadReq MSHR miss cycles 3192system.iocache.ReadReq_mshr_miss_latency::total 1225563023 # number of ReadReq MSHR miss cycles 3193system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 3194system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 3195system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7580015931 # number of WriteLineReq MSHR miss cycles 3196system.iocache.WriteLineReq_mshr_miss_latency::total 7580015931 # number of WriteLineReq MSHR miss cycles 3197system.iocache.demand_mshr_miss_latency::realview.ethernet 3567500 # number of demand (read+write) MSHR miss cycles 3198system.iocache.demand_mshr_miss_latency::realview.ide 8802230454 # number of demand (read+write) MSHR miss cycles 3199system.iocache.demand_mshr_miss_latency::total 8805797954 # number of demand (read+write) MSHR miss cycles 3200system.iocache.overall_mshr_miss_latency::realview.ethernet 3567500 # number of overall MSHR miss cycles 3201system.iocache.overall_mshr_miss_latency::realview.ide 8802230454 # number of overall MSHR miss cycles 3202system.iocache.overall_mshr_miss_latency::total 8805797954 # number of overall MSHR miss cycles 3203system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 3204system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 3205system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 3206system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 3207system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 3208system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 3209system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 3210system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 3211system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 3212system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 3213system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 3214system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 3215system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 3216system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90500 # average ReadReq mshr miss latency 3217system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137312.046175 # average ReadReq mshr miss latency 3218system.iocache.ReadReq_avg_mshr_miss_latency::total 137118.261692 # average ReadReq mshr miss latency 3219system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 3220system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 3221system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 71021.811811 # average WriteLineReq mshr miss latency 3222system.iocache.WriteLineReq_avg_mshr_miss_latency::total 71021.811811 # average WriteLineReq mshr miss latency 3223system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89187.500000 # average overall mshr miss latency 3224system.iocache.demand_avg_mshr_miss_latency::realview.ide 76124.765016 # average overall mshr miss latency 3225system.iocache.demand_avg_mshr_miss_latency::total 76129.282297 # average overall mshr miss latency 3226system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89187.500000 # average overall mshr miss latency 3227system.iocache.overall_avg_mshr_miss_latency::realview.ide 76124.765016 # average overall mshr miss latency 3228system.iocache.overall_avg_mshr_miss_latency::total 76129.282297 # average overall mshr miss latency 3229system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 3230system.l2c.tags.replacements 1557710 # number of replacements 3231system.l2c.tags.tagsinuse 63573.891854 # Cycle average of tags in use 3232system.l2c.tags.total_refs 6243665 # Total number of references to valid blocks. 3233system.l2c.tags.sampled_refs 1617388 # Sample count of references to valid blocks. 3234system.l2c.tags.avg_refs 3.860338 # Average number of references to valid blocks. 3235system.l2c.tags.warmup_cycle 3022937500 # Cycle when the warmup percentage was hit. 3236system.l2c.tags.occ_blocks::writebacks 21119.731437 # Average occupied blocks per requestor 3237system.l2c.tags.occ_blocks::cpu0.dtb.walker 317.083055 # Average occupied blocks per requestor 3238system.l2c.tags.occ_blocks::cpu0.itb.walker 501.157048 # Average occupied blocks per requestor 3239system.l2c.tags.occ_blocks::cpu0.inst 4189.705266 # Average occupied blocks per requestor 3240system.l2c.tags.occ_blocks::cpu0.data 12756.928607 # Average occupied blocks per requestor 3241system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 18825.078792 # Average occupied blocks per requestor 3242system.l2c.tags.occ_blocks::cpu1.dtb.walker 29.382680 # Average occupied blocks per requestor 3243system.l2c.tags.occ_blocks::cpu1.itb.walker 33.853586 # Average occupied blocks per requestor 3244system.l2c.tags.occ_blocks::cpu1.inst 2676.679680 # Average occupied blocks per requestor 3245system.l2c.tags.occ_blocks::cpu1.data 1884.367858 # Average occupied blocks per requestor 3246system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1239.923843 # Average occupied blocks per requestor 3247system.l2c.tags.occ_percent::writebacks 0.322262 # Average percentage of cache occupancy 3248system.l2c.tags.occ_percent::cpu0.dtb.walker 0.004838 # Average percentage of cache occupancy 3249system.l2c.tags.occ_percent::cpu0.itb.walker 0.007647 # Average percentage of cache occupancy 3250system.l2c.tags.occ_percent::cpu0.inst 0.063930 # Average percentage of cache occupancy 3251system.l2c.tags.occ_percent::cpu0.data 0.194655 # Average percentage of cache occupancy 3252system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.287248 # Average percentage of cache occupancy 3253system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000448 # Average percentage of cache occupancy 3254system.l2c.tags.occ_percent::cpu1.itb.walker 0.000517 # Average percentage of cache occupancy 3255system.l2c.tags.occ_percent::cpu1.inst 0.040843 # Average percentage of cache occupancy 3256system.l2c.tags.occ_percent::cpu1.data 0.028753 # Average percentage of cache occupancy 3257system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.018920 # Average percentage of cache occupancy 3258system.l2c.tags.occ_percent::total 0.970061 # Average percentage of cache occupancy 3259system.l2c.tags.occ_task_id_blocks::1022 11464 # Occupied blocks per task id 3260system.l2c.tags.occ_task_id_blocks::1023 277 # Occupied blocks per task id 3261system.l2c.tags.occ_task_id_blocks::1024 47937 # Occupied blocks per task id 3262system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id 3263system.l2c.tags.age_task_id_blocks_1022::2 1377 # Occupied blocks per task id 3264system.l2c.tags.age_task_id_blocks_1022::3 337 # Occupied blocks per task id 3265system.l2c.tags.age_task_id_blocks_1022::4 9749 # Occupied blocks per task id 3266system.l2c.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id 3267system.l2c.tags.age_task_id_blocks_1023::4 272 # Occupied blocks per task id 3268system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 3269system.l2c.tags.age_task_id_blocks_1024::1 349 # Occupied blocks per task id 3270system.l2c.tags.age_task_id_blocks_1024::2 3074 # Occupied blocks per task id 3271system.l2c.tags.age_task_id_blocks_1024::3 5518 # Occupied blocks per task id 3272system.l2c.tags.age_task_id_blocks_1024::4 38948 # Occupied blocks per task id 3273system.l2c.tags.occ_task_id_percent::1022 0.174927 # Percentage of cache occupancy per task id 3274system.l2c.tags.occ_task_id_percent::1023 0.004227 # Percentage of cache occupancy per task id 3275system.l2c.tags.occ_task_id_percent::1024 0.731461 # Percentage of cache occupancy per task id 3276system.l2c.tags.tag_accesses 79574133 # Number of tag accesses 3277system.l2c.tags.data_accesses 79574133 # Number of data accesses 3278system.l2c.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 3279system.l2c.WritebackDirty_hits::writebacks 2888931 # number of WritebackDirty hits 3280system.l2c.WritebackDirty_hits::total 2888931 # number of WritebackDirty hits 3281system.l2c.WritebackClean_hits::writebacks 1 # number of WritebackClean hits 3282system.l2c.WritebackClean_hits::total 1 # number of WritebackClean hits 3283system.l2c.UpgradeReq_hits::cpu0.data 180891 # number of UpgradeReq hits 3284system.l2c.UpgradeReq_hits::cpu1.data 129539 # number of UpgradeReq hits 3285system.l2c.UpgradeReq_hits::total 310430 # number of UpgradeReq hits 3286system.l2c.SCUpgradeReq_hits::cpu0.data 43976 # number of SCUpgradeReq hits 3287system.l2c.SCUpgradeReq_hits::cpu1.data 36797 # number of SCUpgradeReq hits 3288system.l2c.SCUpgradeReq_hits::total 80773 # number of SCUpgradeReq hits 3289system.l2c.ReadExReq_hits::cpu0.data 55787 # number of ReadExReq hits 3290system.l2c.ReadExReq_hits::cpu1.data 50048 # number of ReadExReq hits 3291system.l2c.ReadExReq_hits::total 105835 # number of ReadExReq hits 3292system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6797 # number of ReadSharedReq hits 3293system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4576 # number of ReadSharedReq hits 3294system.l2c.ReadSharedReq_hits::cpu0.inst 551177 # number of ReadSharedReq hits 3295system.l2c.ReadSharedReq_hits::cpu0.data 671308 # number of ReadSharedReq hits 3296system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 325157 # number of ReadSharedReq hits 3297system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6401 # number of ReadSharedReq hits 3298system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4256 # number of ReadSharedReq hits 3299system.l2c.ReadSharedReq_hits::cpu1.inst 484948 # number of ReadSharedReq hits 3300system.l2c.ReadSharedReq_hits::cpu1.data 535287 # number of ReadSharedReq hits 3301system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 285618 # number of ReadSharedReq hits 3302system.l2c.ReadSharedReq_hits::total 2875525 # number of ReadSharedReq hits 3303system.l2c.InvalidateReq_hits::cpu0.data 132882 # number of InvalidateReq hits 3304system.l2c.InvalidateReq_hits::cpu1.data 123273 # number of InvalidateReq hits 3305system.l2c.InvalidateReq_hits::total 256155 # number of InvalidateReq hits 3306system.l2c.demand_hits::cpu0.dtb.walker 6797 # number of demand (read+write) hits 3307system.l2c.demand_hits::cpu0.itb.walker 4576 # number of demand (read+write) hits 3308system.l2c.demand_hits::cpu0.inst 551177 # number of demand (read+write) hits 3309system.l2c.demand_hits::cpu0.data 727095 # number of demand (read+write) hits 3310system.l2c.demand_hits::cpu0.l2cache.prefetcher 325157 # number of demand (read+write) hits 3311system.l2c.demand_hits::cpu1.dtb.walker 6401 # number of demand (read+write) hits 3312system.l2c.demand_hits::cpu1.itb.walker 4256 # number of demand (read+write) hits 3313system.l2c.demand_hits::cpu1.inst 484948 # number of demand (read+write) hits 3314system.l2c.demand_hits::cpu1.data 585335 # number of demand (read+write) hits 3315system.l2c.demand_hits::cpu1.l2cache.prefetcher 285618 # number of demand (read+write) hits 3316system.l2c.demand_hits::total 2981360 # number of demand (read+write) hits 3317system.l2c.overall_hits::cpu0.dtb.walker 6797 # number of overall hits 3318system.l2c.overall_hits::cpu0.itb.walker 4576 # number of overall hits 3319system.l2c.overall_hits::cpu0.inst 551177 # number of overall hits 3320system.l2c.overall_hits::cpu0.data 727095 # number of overall hits 3321system.l2c.overall_hits::cpu0.l2cache.prefetcher 325157 # number of overall hits 3322system.l2c.overall_hits::cpu1.dtb.walker 6401 # number of overall hits 3323system.l2c.overall_hits::cpu1.itb.walker 4256 # number of overall hits 3324system.l2c.overall_hits::cpu1.inst 484948 # number of overall hits 3325system.l2c.overall_hits::cpu1.data 585335 # number of overall hits 3326system.l2c.overall_hits::cpu1.l2cache.prefetcher 285618 # number of overall hits 3327system.l2c.overall_hits::total 2981360 # number of overall hits 3328system.l2c.UpgradeReq_misses::cpu0.data 62870 # number of UpgradeReq misses 3329system.l2c.UpgradeReq_misses::cpu1.data 65353 # number of UpgradeReq misses 3330system.l2c.UpgradeReq_misses::total 128223 # number of UpgradeReq misses 3331system.l2c.SCUpgradeReq_misses::cpu0.data 13472 # number of SCUpgradeReq misses 3332system.l2c.SCUpgradeReq_misses::cpu1.data 11956 # number of SCUpgradeReq misses 3333system.l2c.SCUpgradeReq_misses::total 25428 # number of SCUpgradeReq misses 3334system.l2c.ReadExReq_misses::cpu0.data 91907 # number of ReadExReq misses 3335system.l2c.ReadExReq_misses::cpu1.data 48160 # number of ReadExReq misses 3336system.l2c.ReadExReq_misses::total 140067 # number of ReadExReq misses 3337system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 3207 # number of ReadSharedReq misses 3338system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3170 # number of ReadSharedReq misses 3339system.l2c.ReadSharedReq_misses::cpu0.inst 61507 # number of ReadSharedReq misses 3340system.l2c.ReadSharedReq_misses::cpu0.data 173115 # number of ReadSharedReq misses 3341system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 339604 # number of ReadSharedReq misses 3342system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1937 # number of ReadSharedReq misses 3343system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1306 # number of ReadSharedReq misses 3344system.l2c.ReadSharedReq_misses::cpu1.inst 48662 # number of ReadSharedReq misses 3345system.l2c.ReadSharedReq_misses::cpu1.data 111561 # number of ReadSharedReq misses 3346system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 193805 # number of ReadSharedReq misses 3347system.l2c.ReadSharedReq_misses::total 937874 # number of ReadSharedReq misses 3348system.l2c.InvalidateReq_misses::cpu0.data 497642 # number of InvalidateReq misses 3349system.l2c.InvalidateReq_misses::cpu1.data 96113 # number of InvalidateReq misses 3350system.l2c.InvalidateReq_misses::total 593755 # number of InvalidateReq misses 3351system.l2c.demand_misses::cpu0.dtb.walker 3207 # number of demand (read+write) misses 3352system.l2c.demand_misses::cpu0.itb.walker 3170 # number of demand (read+write) misses 3353system.l2c.demand_misses::cpu0.inst 61507 # number of demand (read+write) misses 3354system.l2c.demand_misses::cpu0.data 265022 # number of demand (read+write) misses 3355system.l2c.demand_misses::cpu0.l2cache.prefetcher 339604 # number of demand (read+write) misses 3356system.l2c.demand_misses::cpu1.dtb.walker 1937 # number of demand (read+write) misses 3357system.l2c.demand_misses::cpu1.itb.walker 1306 # number of demand (read+write) misses 3358system.l2c.demand_misses::cpu1.inst 48662 # number of demand (read+write) misses 3359system.l2c.demand_misses::cpu1.data 159721 # number of demand (read+write) misses 3360system.l2c.demand_misses::cpu1.l2cache.prefetcher 193805 # number of demand (read+write) misses 3361system.l2c.demand_misses::total 1077941 # number of demand (read+write) misses 3362system.l2c.overall_misses::cpu0.dtb.walker 3207 # number of overall misses 3363system.l2c.overall_misses::cpu0.itb.walker 3170 # number of overall misses 3364system.l2c.overall_misses::cpu0.inst 61507 # number of overall misses 3365system.l2c.overall_misses::cpu0.data 265022 # number of overall misses 3366system.l2c.overall_misses::cpu0.l2cache.prefetcher 339604 # number of overall misses 3367system.l2c.overall_misses::cpu1.dtb.walker 1937 # number of overall misses 3368system.l2c.overall_misses::cpu1.itb.walker 1306 # number of overall misses 3369system.l2c.overall_misses::cpu1.inst 48662 # number of overall misses 3370system.l2c.overall_misses::cpu1.data 159721 # number of overall misses 3371system.l2c.overall_misses::cpu1.l2cache.prefetcher 193805 # number of overall misses 3372system.l2c.overall_misses::total 1077941 # number of overall misses 3373system.l2c.UpgradeReq_miss_latency::cpu0.data 420802000 # number of UpgradeReq miss cycles 3374system.l2c.UpgradeReq_miss_latency::cpu1.data 429972500 # number of UpgradeReq miss cycles 3375system.l2c.UpgradeReq_miss_latency::total 850774500 # number of UpgradeReq miss cycles 3376system.l2c.SCUpgradeReq_miss_latency::cpu0.data 88078000 # number of SCUpgradeReq miss cycles 3377system.l2c.SCUpgradeReq_miss_latency::cpu1.data 80352500 # number of SCUpgradeReq miss cycles 3378system.l2c.SCUpgradeReq_miss_latency::total 168430500 # number of SCUpgradeReq miss cycles 3379system.l2c.ReadExReq_miss_latency::cpu0.data 8572942990 # number of ReadExReq miss cycles 3380system.l2c.ReadExReq_miss_latency::cpu1.data 4240159498 # number of ReadExReq miss cycles 3381system.l2c.ReadExReq_miss_latency::total 12813102488 # number of ReadExReq miss cycles 3382system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 292674000 # number of ReadSharedReq miss cycles 3383system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 283861500 # number of ReadSharedReq miss cycles 3384system.l2c.ReadSharedReq_miss_latency::cpu0.inst 5444535999 # number of ReadSharedReq miss cycles 3385system.l2c.ReadSharedReq_miss_latency::cpu0.data 16594648743 # number of ReadSharedReq miss cycles 3386system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 46635334107 # number of ReadSharedReq miss cycles 3387system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 183709500 # number of ReadSharedReq miss cycles 3388system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 124471000 # number of ReadSharedReq miss cycles 3389system.l2c.ReadSharedReq_miss_latency::cpu1.inst 4269928000 # number of ReadSharedReq miss cycles 3390system.l2c.ReadSharedReq_miss_latency::cpu1.data 11202968996 # number of ReadSharedReq miss cycles 3391system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 26909035721 # number of ReadSharedReq miss cycles 3392system.l2c.ReadSharedReq_miss_latency::total 111941167566 # number of ReadSharedReq miss cycles 3393system.l2c.InvalidateReq_miss_latency::cpu0.data 55164500 # number of InvalidateReq miss cycles 3394system.l2c.InvalidateReq_miss_latency::cpu1.data 62218500 # number of InvalidateReq miss cycles 3395system.l2c.InvalidateReq_miss_latency::total 117383000 # number of InvalidateReq miss cycles 3396system.l2c.demand_miss_latency::cpu0.dtb.walker 292674000 # number of demand (read+write) miss cycles 3397system.l2c.demand_miss_latency::cpu0.itb.walker 283861500 # number of demand (read+write) miss cycles 3398system.l2c.demand_miss_latency::cpu0.inst 5444535999 # number of demand (read+write) miss cycles 3399system.l2c.demand_miss_latency::cpu0.data 25167591733 # number of demand (read+write) miss cycles 3400system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 46635334107 # number of demand (read+write) miss cycles 3401system.l2c.demand_miss_latency::cpu1.dtb.walker 183709500 # number of demand (read+write) miss cycles 3402system.l2c.demand_miss_latency::cpu1.itb.walker 124471000 # number of demand (read+write) miss cycles 3403system.l2c.demand_miss_latency::cpu1.inst 4269928000 # number of demand (read+write) miss cycles 3404system.l2c.demand_miss_latency::cpu1.data 15443128494 # number of demand (read+write) miss cycles 3405system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 26909035721 # number of demand (read+write) miss cycles 3406system.l2c.demand_miss_latency::total 124754270054 # number of demand (read+write) miss cycles 3407system.l2c.overall_miss_latency::cpu0.dtb.walker 292674000 # number of overall miss cycles 3408system.l2c.overall_miss_latency::cpu0.itb.walker 283861500 # number of overall miss cycles 3409system.l2c.overall_miss_latency::cpu0.inst 5444535999 # number of overall miss cycles 3410system.l2c.overall_miss_latency::cpu0.data 25167591733 # number of overall miss cycles 3411system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 46635334107 # number of overall miss cycles 3412system.l2c.overall_miss_latency::cpu1.dtb.walker 183709500 # number of overall miss cycles 3413system.l2c.overall_miss_latency::cpu1.itb.walker 124471000 # number of overall miss cycles 3414system.l2c.overall_miss_latency::cpu1.inst 4269928000 # number of overall miss cycles 3415system.l2c.overall_miss_latency::cpu1.data 15443128494 # number of overall miss cycles 3416system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 26909035721 # number of overall miss cycles 3417system.l2c.overall_miss_latency::total 124754270054 # number of overall miss cycles 3418system.l2c.WritebackDirty_accesses::writebacks 2888931 # number of WritebackDirty accesses(hits+misses) 3419system.l2c.WritebackDirty_accesses::total 2888931 # number of WritebackDirty accesses(hits+misses) 3420system.l2c.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) 3421system.l2c.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) 3422system.l2c.UpgradeReq_accesses::cpu0.data 243761 # number of UpgradeReq accesses(hits+misses) 3423system.l2c.UpgradeReq_accesses::cpu1.data 194892 # number of UpgradeReq accesses(hits+misses) 3424system.l2c.UpgradeReq_accesses::total 438653 # number of UpgradeReq accesses(hits+misses) 3425system.l2c.SCUpgradeReq_accesses::cpu0.data 57448 # number of SCUpgradeReq accesses(hits+misses) 3426system.l2c.SCUpgradeReq_accesses::cpu1.data 48753 # number of SCUpgradeReq accesses(hits+misses) 3427system.l2c.SCUpgradeReq_accesses::total 106201 # number of SCUpgradeReq accesses(hits+misses) 3428system.l2c.ReadExReq_accesses::cpu0.data 147694 # number of ReadExReq accesses(hits+misses) 3429system.l2c.ReadExReq_accesses::cpu1.data 98208 # number of ReadExReq accesses(hits+misses) 3430system.l2c.ReadExReq_accesses::total 245902 # number of ReadExReq accesses(hits+misses) 3431system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 10004 # number of ReadSharedReq accesses(hits+misses) 3432system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7746 # number of ReadSharedReq accesses(hits+misses) 3433system.l2c.ReadSharedReq_accesses::cpu0.inst 612684 # number of ReadSharedReq accesses(hits+misses) 3434system.l2c.ReadSharedReq_accesses::cpu0.data 844423 # number of ReadSharedReq accesses(hits+misses) 3435system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 664761 # number of ReadSharedReq accesses(hits+misses) 3436system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8338 # number of ReadSharedReq accesses(hits+misses) 3437system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 5562 # number of ReadSharedReq accesses(hits+misses) 3438system.l2c.ReadSharedReq_accesses::cpu1.inst 533610 # number of ReadSharedReq accesses(hits+misses) 3439system.l2c.ReadSharedReq_accesses::cpu1.data 646848 # number of ReadSharedReq accesses(hits+misses) 3440system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 479423 # number of ReadSharedReq accesses(hits+misses) 3441system.l2c.ReadSharedReq_accesses::total 3813399 # number of ReadSharedReq accesses(hits+misses) 3442system.l2c.InvalidateReq_accesses::cpu0.data 630524 # number of InvalidateReq accesses(hits+misses) 3443system.l2c.InvalidateReq_accesses::cpu1.data 219386 # number of InvalidateReq accesses(hits+misses) 3444system.l2c.InvalidateReq_accesses::total 849910 # number of InvalidateReq accesses(hits+misses) 3445system.l2c.demand_accesses::cpu0.dtb.walker 10004 # number of demand (read+write) accesses 3446system.l2c.demand_accesses::cpu0.itb.walker 7746 # number of demand (read+write) accesses 3447system.l2c.demand_accesses::cpu0.inst 612684 # number of demand (read+write) accesses 3448system.l2c.demand_accesses::cpu0.data 992117 # number of demand (read+write) accesses 3449system.l2c.demand_accesses::cpu0.l2cache.prefetcher 664761 # number of demand (read+write) accesses 3450system.l2c.demand_accesses::cpu1.dtb.walker 8338 # number of demand (read+write) accesses 3451system.l2c.demand_accesses::cpu1.itb.walker 5562 # number of demand (read+write) accesses 3452system.l2c.demand_accesses::cpu1.inst 533610 # number of demand (read+write) accesses 3453system.l2c.demand_accesses::cpu1.data 745056 # number of demand (read+write) accesses 3454system.l2c.demand_accesses::cpu1.l2cache.prefetcher 479423 # number of demand (read+write) accesses 3455system.l2c.demand_accesses::total 4059301 # number of demand (read+write) accesses 3456system.l2c.overall_accesses::cpu0.dtb.walker 10004 # number of overall (read+write) accesses 3457system.l2c.overall_accesses::cpu0.itb.walker 7746 # number of overall (read+write) accesses 3458system.l2c.overall_accesses::cpu0.inst 612684 # number of overall (read+write) accesses 3459system.l2c.overall_accesses::cpu0.data 992117 # number of overall (read+write) accesses 3460system.l2c.overall_accesses::cpu0.l2cache.prefetcher 664761 # number of overall (read+write) accesses 3461system.l2c.overall_accesses::cpu1.dtb.walker 8338 # number of overall (read+write) accesses 3462system.l2c.overall_accesses::cpu1.itb.walker 5562 # number of overall (read+write) accesses 3463system.l2c.overall_accesses::cpu1.inst 533610 # number of overall (read+write) accesses 3464system.l2c.overall_accesses::cpu1.data 745056 # number of overall (read+write) accesses 3465system.l2c.overall_accesses::cpu1.l2cache.prefetcher 479423 # number of overall (read+write) accesses 3466system.l2c.overall_accesses::total 4059301 # number of overall (read+write) accesses 3467system.l2c.UpgradeReq_miss_rate::cpu0.data 0.257917 # miss rate for UpgradeReq accesses 3468system.l2c.UpgradeReq_miss_rate::cpu1.data 0.335329 # miss rate for UpgradeReq accesses 3469system.l2c.UpgradeReq_miss_rate::total 0.292311 # miss rate for UpgradeReq accesses 3470system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.234508 # miss rate for SCUpgradeReq accesses 3471system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.245236 # miss rate for SCUpgradeReq accesses 3472system.l2c.SCUpgradeReq_miss_rate::total 0.239433 # miss rate for SCUpgradeReq accesses 3473system.l2c.ReadExReq_miss_rate::cpu0.data 0.622280 # miss rate for ReadExReq accesses 3474system.l2c.ReadExReq_miss_rate::cpu1.data 0.490388 # miss rate for ReadExReq accesses 3475system.l2c.ReadExReq_miss_rate::total 0.569605 # miss rate for ReadExReq accesses 3476system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.320572 # miss rate for ReadSharedReq accesses 3477system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.409243 # miss rate for ReadSharedReq accesses 3478system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.100389 # miss rate for ReadSharedReq accesses 3479system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.205010 # miss rate for ReadSharedReq accesses 3480system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.510866 # miss rate for ReadSharedReq accesses 3481system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.232310 # miss rate for ReadSharedReq accesses 3482system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.234808 # miss rate for ReadSharedReq accesses 3483system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.091194 # miss rate for ReadSharedReq accesses 3484system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.172469 # miss rate for ReadSharedReq accesses 3485system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.404246 # miss rate for ReadSharedReq accesses 3486system.l2c.ReadSharedReq_miss_rate::total 0.245942 # miss rate for ReadSharedReq accesses 3487system.l2c.InvalidateReq_miss_rate::cpu0.data 0.789251 # miss rate for InvalidateReq accesses 3488system.l2c.InvalidateReq_miss_rate::cpu1.data 0.438100 # miss rate for InvalidateReq accesses 3489system.l2c.InvalidateReq_miss_rate::total 0.698609 # miss rate for InvalidateReq accesses 3490system.l2c.demand_miss_rate::cpu0.dtb.walker 0.320572 # miss rate for demand accesses 3491system.l2c.demand_miss_rate::cpu0.itb.walker 0.409243 # miss rate for demand accesses 3492system.l2c.demand_miss_rate::cpu0.inst 0.100389 # miss rate for demand accesses 3493system.l2c.demand_miss_rate::cpu0.data 0.267128 # miss rate for demand accesses 3494system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.510866 # miss rate for demand accesses 3495system.l2c.demand_miss_rate::cpu1.dtb.walker 0.232310 # miss rate for demand accesses 3496system.l2c.demand_miss_rate::cpu1.itb.walker 0.234808 # miss rate for demand accesses 3497system.l2c.demand_miss_rate::cpu1.inst 0.091194 # miss rate for demand accesses 3498system.l2c.demand_miss_rate::cpu1.data 0.214374 # miss rate for demand accesses 3499system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.404246 # miss rate for demand accesses 3500system.l2c.demand_miss_rate::total 0.265548 # miss rate for demand accesses 3501system.l2c.overall_miss_rate::cpu0.dtb.walker 0.320572 # miss rate for overall accesses 3502system.l2c.overall_miss_rate::cpu0.itb.walker 0.409243 # miss rate for overall accesses 3503system.l2c.overall_miss_rate::cpu0.inst 0.100389 # miss rate for overall accesses 3504system.l2c.overall_miss_rate::cpu0.data 0.267128 # miss rate for overall accesses 3505system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.510866 # miss rate for overall accesses 3506system.l2c.overall_miss_rate::cpu1.dtb.walker 0.232310 # miss rate for overall accesses 3507system.l2c.overall_miss_rate::cpu1.itb.walker 0.234808 # miss rate for overall accesses 3508system.l2c.overall_miss_rate::cpu1.inst 0.091194 # miss rate for overall accesses 3509system.l2c.overall_miss_rate::cpu1.data 0.214374 # miss rate for overall accesses 3510system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.404246 # miss rate for overall accesses 3511system.l2c.overall_miss_rate::total 0.265548 # miss rate for overall accesses 3512system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6693.208207 # average UpgradeReq miss latency 3513system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6579.231252 # average UpgradeReq miss latency 3514system.l2c.UpgradeReq_avg_miss_latency::total 6635.116165 # average UpgradeReq miss latency 3515system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6537.856295 # average SCUpgradeReq miss latency 3516system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6720.684175 # average SCUpgradeReq miss latency 3517system.l2c.SCUpgradeReq_avg_miss_latency::total 6623.820198 # average SCUpgradeReq miss latency 3518system.l2c.ReadExReq_avg_miss_latency::cpu0.data 93278.455286 # average ReadExReq miss latency 3519system.l2c.ReadExReq_avg_miss_latency::cpu1.data 88043.178945 # average ReadExReq miss latency 3520system.l2c.ReadExReq_avg_miss_latency::total 91478.381689 # average ReadExReq miss latency 3521system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 91260.991581 # average ReadSharedReq miss latency 3522system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 89546.214511 # average ReadSharedReq miss latency 3523system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 88518.965305 # average ReadSharedReq miss latency 3524system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 95859.103735 # average ReadSharedReq miss latency 3525system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 137322.687916 # average ReadSharedReq miss latency 3526system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 94842.281879 # average ReadSharedReq miss latency 3527system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 95307.044410 # average ReadSharedReq miss latency 3528system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 87746.660639 # average ReadSharedReq miss latency 3529system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 100420.119899 # average ReadSharedReq miss latency 3530system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 138845.931328 # average ReadSharedReq miss latency 3531system.l2c.ReadSharedReq_avg_miss_latency::total 119356.296865 # average ReadSharedReq miss latency 3532system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 110.851777 # average InvalidateReq miss latency 3533system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 647.347393 # average InvalidateReq miss latency 3534system.l2c.InvalidateReq_avg_miss_latency::total 197.696019 # average InvalidateReq miss latency 3535system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 91260.991581 # average overall miss latency 3536system.l2c.demand_avg_miss_latency::cpu0.itb.walker 89546.214511 # average overall miss latency 3537system.l2c.demand_avg_miss_latency::cpu0.inst 88518.965305 # average overall miss latency 3538system.l2c.demand_avg_miss_latency::cpu0.data 94964.160458 # average overall miss latency 3539system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 137322.687916 # average overall miss latency 3540system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 94842.281879 # average overall miss latency 3541system.l2c.demand_avg_miss_latency::cpu1.itb.walker 95307.044410 # average overall miss latency 3542system.l2c.demand_avg_miss_latency::cpu1.inst 87746.660639 # average overall miss latency 3543system.l2c.demand_avg_miss_latency::cpu1.data 96688.153054 # average overall miss latency 3544system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 138845.931328 # average overall miss latency 3545system.l2c.demand_avg_miss_latency::total 115733.857469 # average overall miss latency 3546system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 91260.991581 # average overall miss latency 3547system.l2c.overall_avg_miss_latency::cpu0.itb.walker 89546.214511 # average overall miss latency 3548system.l2c.overall_avg_miss_latency::cpu0.inst 88518.965305 # average overall miss latency 3549system.l2c.overall_avg_miss_latency::cpu0.data 94964.160458 # average overall miss latency 3550system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 137322.687916 # average overall miss latency 3551system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 94842.281879 # average overall miss latency 3552system.l2c.overall_avg_miss_latency::cpu1.itb.walker 95307.044410 # average overall miss latency 3553system.l2c.overall_avg_miss_latency::cpu1.inst 87746.660639 # average overall miss latency 3554system.l2c.overall_avg_miss_latency::cpu1.data 96688.153054 # average overall miss latency 3555system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 138845.931328 # average overall miss latency 3556system.l2c.overall_avg_miss_latency::total 115733.857469 # average overall miss latency 3557system.l2c.blocked_cycles::no_mshrs 7857 # number of cycles access was blocked 3558system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 3559system.l2c.blocked::no_mshrs 97 # number of cycles access was blocked 3560system.l2c.blocked::no_targets 0 # number of cycles access was blocked 3561system.l2c.avg_blocked_cycles::no_mshrs 81 # average number of cycles each access was blocked 3562system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3563system.l2c.writebacks::writebacks 1229961 # number of writebacks 3564system.l2c.writebacks::total 1229961 # number of writebacks 3565system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 90 # number of ReadSharedReq MSHR hits 3566system.l2c.ReadSharedReq_mshr_hits::cpu0.data 20 # number of ReadSharedReq MSHR hits 3567system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 89 # number of ReadSharedReq MSHR hits 3568system.l2c.ReadSharedReq_mshr_hits::cpu1.data 22 # number of ReadSharedReq MSHR hits 3569system.l2c.ReadSharedReq_mshr_hits::total 221 # number of ReadSharedReq MSHR hits 3570system.l2c.demand_mshr_hits::cpu0.inst 90 # number of demand (read+write) MSHR hits 3571system.l2c.demand_mshr_hits::cpu0.data 20 # number of demand (read+write) MSHR hits 3572system.l2c.demand_mshr_hits::cpu1.inst 89 # number of demand (read+write) MSHR hits 3573system.l2c.demand_mshr_hits::cpu1.data 22 # number of demand (read+write) MSHR hits 3574system.l2c.demand_mshr_hits::total 221 # number of demand (read+write) MSHR hits 3575system.l2c.overall_mshr_hits::cpu0.inst 90 # number of overall MSHR hits 3576system.l2c.overall_mshr_hits::cpu0.data 20 # number of overall MSHR hits 3577system.l2c.overall_mshr_hits::cpu1.inst 89 # number of overall MSHR hits 3578system.l2c.overall_mshr_hits::cpu1.data 22 # number of overall MSHR hits 3579system.l2c.overall_mshr_hits::total 221 # number of overall MSHR hits 3580system.l2c.CleanEvict_mshr_misses::writebacks 60565 # number of CleanEvict MSHR misses 3581system.l2c.CleanEvict_mshr_misses::total 60565 # number of CleanEvict MSHR misses 3582system.l2c.UpgradeReq_mshr_misses::cpu0.data 62870 # number of UpgradeReq MSHR misses 3583system.l2c.UpgradeReq_mshr_misses::cpu1.data 65353 # number of UpgradeReq MSHR misses 3584system.l2c.UpgradeReq_mshr_misses::total 128223 # number of UpgradeReq MSHR misses 3585system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 13472 # number of SCUpgradeReq MSHR misses 3586system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11956 # number of SCUpgradeReq MSHR misses 3587system.l2c.SCUpgradeReq_mshr_misses::total 25428 # number of SCUpgradeReq MSHR misses 3588system.l2c.ReadExReq_mshr_misses::cpu0.data 91907 # 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number of overall MSHR miss cycles 3682system.l2c.overall_mshr_miss_latency::cpu1.data 13844000664 # number of overall MSHR miss cycles 3683system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 24970706342 # number of overall MSHR miss cycles 3684system.l2c.overall_mshr_miss_latency::total 113957462696 # number of overall MSHR miss cycles 3685system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1342704500 # number of ReadReq MSHR uncacheable cycles 3686system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5248860501 # number of ReadReq MSHR uncacheable cycles 3687system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 4969000 # number of ReadReq MSHR uncacheable cycles 3688system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 692108006 # number of ReadReq MSHR uncacheable cycles 3689system.l2c.ReadReq_mshr_uncacheable_latency::total 7288642007 # number of ReadReq MSHR uncacheable cycles 3690system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1342704500 # number of overall MSHR uncacheable cycles 3691system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5248860501 # number of overall MSHR uncacheable cycles 3692system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4969000 # number of overall MSHR uncacheable cycles 3693system.l2c.overall_mshr_uncacheable_latency::cpu1.data 692108006 # number of overall MSHR uncacheable cycles 3694system.l2c.overall_mshr_uncacheable_latency::total 7288642007 # number of overall MSHR uncacheable cycles 3695system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3696system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 3697system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.257917 # mshr miss rate for UpgradeReq accesses 3698system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.335329 # mshr miss rate for UpgradeReq accesses 3699system.l2c.UpgradeReq_mshr_miss_rate::total 0.292311 # mshr miss rate for UpgradeReq accesses 3700system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.234508 # mshr miss rate for SCUpgradeReq accesses 3701system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.245236 # mshr miss rate for SCUpgradeReq accesses 3702system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.239433 # mshr miss rate for SCUpgradeReq accesses 3703system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.622280 # mshr miss rate for ReadExReq accesses 3704system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.490388 # mshr miss rate for ReadExReq accesses 3705system.l2c.ReadExReq_mshr_miss_rate::total 0.569605 # mshr miss rate for ReadExReq accesses 3706system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.320572 # mshr miss rate for ReadSharedReq accesses 3707system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.409243 # mshr miss rate for ReadSharedReq accesses 3708system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.100243 # mshr miss rate for ReadSharedReq accesses 3709system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.204986 # mshr miss rate for ReadSharedReq accesses 3710system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.510866 # mshr miss rate for ReadSharedReq accesses 3711system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.232310 # mshr miss rate for ReadSharedReq accesses 3712system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.234808 # mshr miss rate for ReadSharedReq accesses 3713system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.091027 # mshr miss rate for ReadSharedReq accesses 3714system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.172435 # mshr miss rate for ReadSharedReq accesses 3715system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.404246 # mshr miss rate for ReadSharedReq accesses 3716system.l2c.ReadSharedReq_mshr_miss_rate::total 0.245884 # mshr miss rate for ReadSharedReq accesses 3717system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.789251 # mshr miss rate for InvalidateReq accesses 3718system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.438100 # mshr miss rate for InvalidateReq accesses 3719system.l2c.InvalidateReq_mshr_miss_rate::total 0.698609 # mshr miss rate for InvalidateReq accesses 3720system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.320572 # mshr miss rate for demand accesses 3721system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.409243 # mshr miss rate for demand accesses 3722system.l2c.demand_mshr_miss_rate::cpu0.inst 0.100243 # mshr miss rate for demand accesses 3723system.l2c.demand_mshr_miss_rate::cpu0.data 0.267108 # mshr miss rate for demand accesses 3724system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.510866 # mshr miss rate for demand accesses 3725system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.232310 # mshr miss rate for demand accesses 3726system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.234808 # mshr miss rate for demand accesses 3727system.l2c.demand_mshr_miss_rate::cpu1.inst 0.091027 # mshr miss rate for demand accesses 3728system.l2c.demand_mshr_miss_rate::cpu1.data 0.214345 # mshr miss rate for demand accesses 3729system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.404246 # mshr miss rate for demand accesses 3730system.l2c.demand_mshr_miss_rate::total 0.265494 # mshr miss rate for demand accesses 3731system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.320572 # mshr miss rate for overall accesses 3732system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.409243 # mshr miss rate for overall accesses 3733system.l2c.overall_mshr_miss_rate::cpu0.inst 0.100243 # mshr miss rate for overall accesses 3734system.l2c.overall_mshr_miss_rate::cpu0.data 0.267108 # mshr miss rate for overall accesses 3735system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.510866 # mshr miss rate for overall accesses 3736system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.232310 # mshr miss rate for overall accesses 3737system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.234808 # mshr miss rate for overall accesses 3738system.l2c.overall_mshr_miss_rate::cpu1.inst 0.091027 # mshr miss rate for overall accesses 3739system.l2c.overall_mshr_miss_rate::cpu1.data 0.214345 # mshr miss rate for overall accesses 3740system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.404246 # mshr miss rate for overall accesses 3741system.l2c.overall_mshr_miss_rate::total 0.265494 # mshr miss rate for overall accesses 3742system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21552.155177 # average UpgradeReq mshr miss latency 3743system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21730.655027 # average UpgradeReq mshr miss latency 3744system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21643.133400 # average UpgradeReq mshr miss latency 3745system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24653.874406 # average SCUpgradeReq mshr miss latency 3746system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24518.317079 # average SCUpgradeReq mshr miss latency 3747system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24590.136660 # average SCUpgradeReq mshr miss latency 3748system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 83276.625632 # average ReadExReq mshr miss latency 3749system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 78040.298609 # average ReadExReq mshr miss latency 3750system.l2c.ReadExReq_avg_mshr_miss_latency::total 81476.190773 # average ReadExReq mshr miss latency 3751system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 81260.835984 # average ReadSharedReq mshr miss latency 3752system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 79545.899685 # average ReadSharedReq mshr miss latency 3753system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 78527.795024 # average ReadSharedReq mshr miss latency 3754system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 85858.003201 # average ReadSharedReq mshr miss latency 3755system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 127321.987159 # average ReadSharedReq mshr miss latency 3756system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 84841.766649 # average ReadSharedReq mshr miss latency 3757system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 85305.516080 # average ReadSharedReq mshr miss latency 3758system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 77758.231343 # average ReadSharedReq mshr miss latency 3759system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 90422.003810 # average ReadSharedReq mshr miss latency 3760system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128844.489781 # average ReadSharedReq mshr miss latency 3761system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 109363.844709 # average ReadSharedReq mshr miss latency 3762system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 24730.353519 # average InvalidateReq mshr miss latency 3763system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 21241.236877 # average InvalidateReq mshr miss latency 3764system.l2c.InvalidateReq_avg_mshr_miss_latency::total 24165.559172 # average InvalidateReq mshr miss latency 3765system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 81260.835984 # average overall mshr miss latency 3766system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79545.899685 # average overall mshr miss latency 3767system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 78527.795024 # average overall mshr miss latency 3768system.l2c.demand_avg_mshr_miss_latency::cpu0.data 84962.739511 # average overall mshr miss latency 3769system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 127321.987159 # average overall mshr miss latency 3770system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 84841.766649 # average overall mshr miss latency 3771system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 85305.516080 # average overall mshr miss latency 3772system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 77758.231343 # average overall mshr miss latency 3773system.l2c.demand_avg_mshr_miss_latency::cpu1.data 86688.086112 # average overall mshr miss latency 3774system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128844.489781 # average overall mshr miss latency 3775system.l2c.demand_avg_mshr_miss_latency::total 105739.396778 # average overall mshr miss latency 3776system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 81260.835984 # average overall mshr miss latency 3777system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79545.899685 # average overall mshr miss latency 3778system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 78527.795024 # average overall mshr miss latency 3779system.l2c.overall_avg_mshr_miss_latency::cpu0.data 84962.739511 # average overall mshr miss latency 3780system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 127321.987159 # average overall mshr miss latency 3781system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 84841.766649 # average overall mshr miss latency 3782system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 85305.516080 # average overall mshr miss latency 3783system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 77758.231343 # average overall mshr miss latency 3784system.l2c.overall_avg_mshr_miss_latency::cpu1.data 86688.086112 # average overall mshr miss latency 3785system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128844.489781 # average overall mshr miss latency 3786system.l2c.overall_avg_mshr_miss_latency::total 105739.396778 # average overall mshr miss latency 3787system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63058.493402 # average ReadReq mshr uncacheable latency 3788system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167775.627329 # average ReadReq mshr uncacheable latency 3789system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 74164.179104 # average ReadReq mshr uncacheable latency 3790system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 95912.972007 # average ReadReq mshr uncacheable latency 3791system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 121759.442826 # average ReadReq mshr uncacheable latency 3792system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63058.493402 # average overall mshr uncacheable latency 3793system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 84328.526919 # average overall mshr uncacheable latency 3794system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 74164.179104 # average overall mshr uncacheable latency 3795system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 47094.992243 # average overall mshr uncacheable latency 3796system.l2c.overall_avg_mshr_uncacheable_latency::total 74147.671970 # average overall mshr uncacheable latency 3797system.membus.snoop_filter.tot_requests 4190264 # Total number of requests made to the snoop filter. 3798system.membus.snoop_filter.hit_single_requests 2528993 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3799system.membus.snoop_filter.hit_multi_requests 3019 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3800system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 3801system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3802system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3803system.membus.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 3804system.membus.trans_dist::ReadReq 59861 # Transaction distribution 3805system.membus.trans_dist::ReadResp 1006452 # Transaction distribution 3806system.membus.trans_dist::WriteReq 38438 # Transaction distribution 3807system.membus.trans_dist::WriteResp 38438 # Transaction distribution 3808system.membus.trans_dist::WritebackDirty 1336656 # Transaction distribution 3809system.membus.trans_dist::CleanEvict 266935 # Transaction distribution 3810system.membus.trans_dist::UpgradeReq 438975 # Transaction distribution 3811system.membus.trans_dist::SCUpgradeReq 302731 # Transaction distribution 3812system.membus.trans_dist::UpgradeResp 22 # Transaction distribution 3813system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution 3814system.membus.trans_dist::ReadExReq 150471 # Transaction distribution 3815system.membus.trans_dist::ReadExResp 135365 # Transaction distribution 3816system.membus.trans_dist::ReadSharedReq 946591 # Transaction distribution 3817system.membus.trans_dist::InvalidateReq 696687 # Transaction distribution 3818system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122580 # Packet count per connected master and slave (bytes) 3819system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) 3820system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26078 # Packet count per connected master and slave (bytes) 3821system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5027920 # Packet count per connected master and slave (bytes) 3822system.membus.pkt_count_system.l2c.mem_side::total 5176654 # Packet count per connected master and slave (bytes) 3823system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238145 # Packet count per connected master and slave (bytes) 3824system.membus.pkt_count_system.iocache.mem_side::total 238145 # Packet count per connected master and slave (bytes) 3825system.membus.pkt_count::total 5414799 # Packet count per connected master and slave (bytes) 3826system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155687 # Cumulative packet size per connected master and slave (bytes) 3827system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes) 3828system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52156 # Cumulative packet size per connected master and slave (bytes) 3829system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 147706944 # Cumulative packet size per connected master and slave (bytes) 3830system.membus.pkt_size_system.l2c.mem_side::total 147915343 # Cumulative packet size per connected master and slave (bytes) 3831system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7266880 # Cumulative packet size per connected master and slave (bytes) 3832system.membus.pkt_size_system.iocache.mem_side::total 7266880 # Cumulative packet size per connected master and slave (bytes) 3833system.membus.pkt_size::total 155182223 # Cumulative packet size per connected master and slave (bytes) 3834system.membus.snoops 597489 # Total snoops (count) 3835system.membus.snoopTraffic 179456 # Total snoop traffic (bytes) 3836system.membus.snoop_fanout::samples 2633759 # Request fanout histogram 3837system.membus.snoop_fanout::mean 0.013061 # Request fanout histogram 3838system.membus.snoop_fanout::stdev 0.113535 # Request fanout histogram 3839system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3840system.membus.snoop_fanout::0 2599360 98.69% 98.69% # Request fanout histogram 3841system.membus.snoop_fanout::1 34399 1.31% 100.00% # Request fanout histogram 3842system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3843system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3844system.membus.snoop_fanout::min_value 0 # Request fanout histogram 3845system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3846system.membus.snoop_fanout::total 2633759 # Request fanout histogram 3847system.membus.reqLayer0.occupancy 98019495 # Layer occupancy (ticks) 3848system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3849system.membus.reqLayer1.occupancy 52000 # Layer occupancy (ticks) 3850system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3851system.membus.reqLayer2.occupancy 21931994 # Layer occupancy (ticks) 3852system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3853system.membus.reqLayer5.occupancy 9377704107 # Layer occupancy (ticks) 3854system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3855system.membus.respLayer2.occupancy 5794716587 # Layer occupancy (ticks) 3856system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3857system.membus.respLayer3.occupancy 45616715 # Layer occupancy (ticks) 3858system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3859system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 3860system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 3861system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 3862system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 3863system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 3864system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 3865system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 3866system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3867system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3868system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3869system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3870system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3871system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3872system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 3873system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 3874system.realview.ethernet.txBytes 966 # Bytes Transmitted 3875system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3876system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3877system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3878system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3879system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3880system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3881system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3882system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3883system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 3884system.realview.ethernet.totPackets 3 # Total Packets 3885system.realview.ethernet.totBytes 966 # Total Bytes 3886system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 3887system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 3888system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 3889system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3890system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 3891system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3892system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3893system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 3894system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3895system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3896system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 3897system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3898system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3899system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 3900system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3901system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3902system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 3903system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3904system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3905system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 3906system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3907system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3908system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3909system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3910system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3911system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3912system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3913system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3914system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3915system.realview.ethernet.droppedPackets 0 # number of packets dropped 3916system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 3917system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 3918system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 3919system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 3920system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 3921system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 3922system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 3923system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3924system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3925system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3926system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3927system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 3928system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 3929system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 3930system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 3931system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 3932system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 3933system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 3934system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 3935system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 3936system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 3937system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 3938system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 3939system.toL2Bus.snoop_filter.tot_requests 12205642 # Total number of requests made to the snoop filter. 3940system.toL2Bus.snoop_filter.hit_single_requests 6628070 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3941system.toL2Bus.snoop_filter.hit_multi_requests 1941255 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3942system.toL2Bus.snoop_filter.tot_snoops 157740 # Total number of snoops made to the snoop filter. 3943system.toL2Bus.snoop_filter.hit_single_snoops 142803 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3944system.toL2Bus.snoop_filter.hit_multi_snoops 14937 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3945system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states 3946system.toL2Bus.trans_dist::ReadReq 59863 # Transaction distribution 3947system.toL2Bus.trans_dist::ReadResp 4654836 # Transaction distribution 3948system.toL2Bus.trans_dist::WriteReq 38438 # Transaction distribution 3949system.toL2Bus.trans_dist::WriteResp 38438 # Transaction distribution 3950system.toL2Bus.trans_dist::WritebackDirty 4118892 # Transaction distribution 3951system.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution 3952system.toL2Bus.trans_dist::CleanEvict 2762121 # Transaction distribution 3953system.toL2Bus.trans_dist::UpgradeReq 740907 # Transaction distribution 3954system.toL2Bus.trans_dist::SCUpgradeReq 383504 # Transaction distribution 3955system.toL2Bus.trans_dist::UpgradeResp 1124411 # Transaction distribution 3956system.toL2Bus.trans_dist::SCUpgradeFailReq 124 # Transaction distribution 3957system.toL2Bus.trans_dist::UpgradeFailResp 124 # Transaction distribution 3958system.toL2Bus.trans_dist::ReadExReq 298356 # Transaction distribution 3959system.toL2Bus.trans_dist::ReadExResp 298356 # Transaction distribution 3960system.toL2Bus.trans_dist::ReadSharedReq 4595571 # Transaction distribution 3961system.toL2Bus.trans_dist::InvalidateReq 881263 # Transaction distribution 3962system.toL2Bus.trans_dist::InvalidateResp 849910 # Transaction distribution 3963system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10458732 # Packet count per connected master and slave (bytes) 3964system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7383011 # Packet count per connected master and slave (bytes) 3965system.toL2Bus.pkt_count::total 17841743 # Packet count per connected master and slave (bytes) 3966system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 265418110 # Cumulative packet size per connected master and slave (bytes) 3967system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 179948433 # Cumulative packet size per connected master and slave (bytes) 3968system.toL2Bus.pkt_size::total 445366543 # Cumulative packet size per connected master and slave (bytes) 3969system.toL2Bus.snoops 3005080 # Total snoops (count) 3970system.toL2Bus.snoopTraffic 132103248 # Total snoop traffic (bytes) 3971system.toL2Bus.snoop_fanout::samples 8556754 # Request fanout histogram 3972system.toL2Bus.snoop_fanout::mean 0.351410 # Request fanout histogram 3973system.toL2Bus.snoop_fanout::stdev 0.481053 # Request fanout histogram 3974system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3975system.toL2Bus.snoop_fanout::0 5564766 65.03% 65.03% # Request fanout histogram 3976system.toL2Bus.snoop_fanout::1 2977051 34.79% 99.83% # Request fanout histogram 3977system.toL2Bus.snoop_fanout::2 14937 0.17% 100.00% # Request fanout histogram 3978system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3979system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3980system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3981system.toL2Bus.snoop_fanout::total 8556754 # Request fanout histogram 3982system.toL2Bus.reqLayer0.occupancy 9506782087 # Layer occupancy (ticks) 3983system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3984system.toL2Bus.snoopLayer0.occupancy 2628899 # Layer occupancy (ticks) 3985system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3986system.toL2Bus.respLayer0.occupancy 4728944566 # Layer occupancy (ticks) 3987system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3988system.toL2Bus.respLayer1.occupancy 3692981173 # Layer occupancy (ticks) 3989system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3990system.cpu0.kern.inst.arm 0 # number of arm instructions executed 3991system.cpu0.kern.inst.quiesce 14084 # number of quiesce instructions executed 3992system.cpu1.kern.inst.arm 0 # number of arm instructions executed 3993system.cpu1.kern.inst.quiesce 4835 # number of quiesce instructions executed 3994 3995---------- End Simulation Statistics ---------- 3996