stats.txt revision 10585:1c9d5d9417b3
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.422278 # Number of seconds simulated 4sim_ticks 47422277747000 # Number of ticks simulated 5final_tick 47422277747000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 91986 # Simulator instruction rate (inst/s) 8host_op_rate 108182 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4717167353 # Simulator tick rate (ticks/s) 10host_mem_usage 870208 # Number of bytes of host memory used 11host_seconds 10053.13 # Real time elapsed on the host 12sim_insts 924745220 # Number of instructions simulated 13sim_ops 1087564829 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 123008 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 83392 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 1145824 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 12461528 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 54523392 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 250240 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 244864 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 679904 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 13804768 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 35481280 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 451200 # Number of bytes read from this memory 27system.physmem.bytes_read::total 119249400 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 1145824 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 679904 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 1825728 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 92428416 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 34system.physmem.bytes_written::total 92449232 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 1922 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 1303 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 33856 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 194733 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 851928 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 3910 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 3826 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 10667 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 215714 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 554395 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 7050 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 1879304 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 1444194 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 50system.physmem.num_writes::total 1446797 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 2594 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 1758 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 24162 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 262778 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 1149742 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 5277 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 5163 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 14337 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 291103 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 748199 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 9515 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 2514628 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 24162 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 14337 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 38499 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 1949051 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::total 1949489 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 1949051 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 2594 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 1758 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 24162 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 263217 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 1149742 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 5277 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 5163 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 14337 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 291103 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 748199 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 9515 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 4464118 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 1879304 # Number of read requests accepted 84system.physmem.writeReqs 1600997 # Number of write requests accepted 85system.physmem.readBursts 1879304 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 1600997 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 120227392 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 48064 # Total number of bytes read from write queue 89system.physmem.bytesWritten 101998144 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 119249400 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 102318032 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 751 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 7249 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 97584 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 111371 # Per bank write bursts 96system.physmem.perBankRdBursts::1 133364 # Per bank write bursts 97system.physmem.perBankRdBursts::2 107237 # Per bank write bursts 98system.physmem.perBankRdBursts::3 129396 # Per bank write bursts 99system.physmem.perBankRdBursts::4 116369 # Per bank write bursts 100system.physmem.perBankRdBursts::5 129089 # Per bank write bursts 101system.physmem.perBankRdBursts::6 116664 # Per bank write bursts 102system.physmem.perBankRdBursts::7 120571 # Per bank write bursts 103system.physmem.perBankRdBursts::8 118226 # Per bank write bursts 104system.physmem.perBankRdBursts::9 133705 # Per bank write bursts 105system.physmem.perBankRdBursts::10 98234 # Per bank write bursts 106system.physmem.perBankRdBursts::11 110272 # Per bank write bursts 107system.physmem.perBankRdBursts::12 110364 # Per bank write bursts 108system.physmem.perBankRdBursts::13 124983 # Per bank write bursts 109system.physmem.perBankRdBursts::14 111960 # Per bank write bursts 110system.physmem.perBankRdBursts::15 106748 # Per bank write bursts 111system.physmem.perBankWrBursts::0 99185 # Per bank write bursts 112system.physmem.perBankWrBursts::1 109011 # Per bank write bursts 113system.physmem.perBankWrBursts::2 97054 # Per bank write bursts 114system.physmem.perBankWrBursts::3 108172 # Per bank write bursts 115system.physmem.perBankWrBursts::4 98286 # Per bank write bursts 116system.physmem.perBankWrBursts::5 106076 # Per bank write bursts 117system.physmem.perBankWrBursts::6 100140 # Per bank write bursts 118system.physmem.perBankWrBursts::7 103851 # Per bank write bursts 119system.physmem.perBankWrBursts::8 98795 # Per bank write bursts 120system.physmem.perBankWrBursts::9 98239 # Per bank write bursts 121system.physmem.perBankWrBursts::10 89198 # Per bank write bursts 122system.physmem.perBankWrBursts::11 97505 # Per bank write bursts 123system.physmem.perBankWrBursts::12 95822 # Per bank write bursts 124system.physmem.perBankWrBursts::13 102116 # Per bank write bursts 125system.physmem.perBankWrBursts::14 95043 # Per bank write bursts 126system.physmem.perBankWrBursts::15 95228 # Per bank write bursts 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 128system.physmem.numWrRetry 6 # Number of times write queue was full causing retry 129system.physmem.totGap 47422276363500 # Total gap between requests 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 0 # Read request sizes (log2) 133system.physmem.readPktSize::3 37 # Read request sizes (log2) 134system.physmem.readPktSize::4 21333 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) 136system.physmem.readPktSize::6 1857934 # Read request sizes (log2) 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 2 # Write request sizes (log2) 140system.physmem.writePktSize::3 2601 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) 143system.physmem.writePktSize::6 1598394 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 506038 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 360780 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 256406 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 156907 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 129304 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 95738 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 81613 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 74114 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 66527 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 41507 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 30519 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 26998 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 23594 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 21466 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 2821 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 2006 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 877 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 672 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 365 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 268 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 2 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 2 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 3 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 1 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 1 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::29 2 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::30 2 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::31 1 # What read queue length does an incoming req see 176system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::15 23051 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 29130 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 37353 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 44982 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 51054 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 59346 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 67111 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 76742 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 83422 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 92810 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 99100 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 107174 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 114191 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 124207 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 117512 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 121939 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 125600 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 118087 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 27656 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 21524 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 15466 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 10008 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 6220 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 4458 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 3377 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 2458 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 1856 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 1380 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 1110 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 875 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 716 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 599 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 528 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 476 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 432 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 384 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 315 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 260 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 216 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 178 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 117 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 93 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 66 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 52 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 37 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 22 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 10 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 975956 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 227.699905 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 133.562466 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 280.517231 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 518192 53.10% 53.10% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 197775 20.26% 73.36% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 73464 7.53% 80.89% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 39205 4.02% 84.91% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 32875 3.37% 88.27% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 20645 2.12% 90.39% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 14690 1.51% 91.89% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 16974 1.74% 93.63% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 62136 6.37% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 975956 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 85700 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 21.919883 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 65.914571 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-511 85693 99.99% 99.99% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::512-1023 4 0.00% 100.00% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::1536-2047 1 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::14848-15359 1 0.00% 100.00% # Reads before turning the bus around for writes 262system.physmem.rdPerTurnAround::total 85700 # Reads before turning the bus around for writes 263system.physmem.wrPerTurnAround::samples 85700 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::mean 18.596511 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::gmean 17.559355 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::stdev 11.221946 # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::16-19 76419 89.17% 89.17% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::20-23 4825 5.63% 94.80% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::24-27 861 1.00% 95.81% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::28-31 776 0.91% 96.71% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::32-35 493 0.58% 97.29% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::36-39 137 0.16% 97.45% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::40-43 117 0.14% 97.58% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::44-47 137 0.16% 97.74% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::48-51 585 0.68% 98.42% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::52-55 72 0.08% 98.51% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::56-59 76 0.09% 98.60% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::60-63 72 0.08% 98.68% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::64-67 110 0.13% 98.81% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::68-71 48 0.06% 98.87% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::72-75 42 0.05% 98.91% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::76-79 81 0.09% 99.01% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::80-83 124 0.14% 99.15% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::84-87 28 0.03% 99.19% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::88-91 35 0.04% 99.23% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::92-95 50 0.06% 99.29% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::96-99 194 0.23% 99.51% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::100-103 14 0.02% 99.53% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::104-107 23 0.03% 99.56% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::108-111 14 0.02% 99.57% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::112-115 54 0.06% 99.63% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::116-119 16 0.02% 99.65% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::120-123 21 0.02% 99.68% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::124-127 26 0.03% 99.71% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::128-131 106 0.12% 99.83% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::132-135 28 0.03% 99.86% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::136-139 8 0.01% 99.87% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::140-143 9 0.01% 99.88% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::144-147 15 0.02% 99.90% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::148-151 15 0.02% 99.92% # Writes before turning the bus around for reads 301system.physmem.wrPerTurnAround::152-155 3 0.00% 99.92% # Writes before turning the bus around for reads 302system.physmem.wrPerTurnAround::156-159 3 0.00% 99.93% # Writes before turning the bus around for reads 303system.physmem.wrPerTurnAround::160-163 11 0.01% 99.94% # Writes before turning the bus around for reads 304system.physmem.wrPerTurnAround::164-167 6 0.01% 99.95% # Writes before turning the bus around for reads 305system.physmem.wrPerTurnAround::168-171 4 0.00% 99.95% # Writes before turning the bus around for reads 306system.physmem.wrPerTurnAround::172-175 2 0.00% 99.95% # Writes before turning the bus around for reads 307system.physmem.wrPerTurnAround::176-179 6 0.01% 99.96% # Writes before turning the bus around for reads 308system.physmem.wrPerTurnAround::180-183 1 0.00% 99.96% # Writes before turning the bus around for reads 309system.physmem.wrPerTurnAround::184-187 2 0.00% 99.96% # Writes before turning the bus around for reads 310system.physmem.wrPerTurnAround::188-191 3 0.00% 99.97% # Writes before turning the bus around for reads 311system.physmem.wrPerTurnAround::192-195 2 0.00% 99.97% # Writes before turning the bus around for reads 312system.physmem.wrPerTurnAround::196-199 2 0.00% 99.97% # Writes before turning the bus around for reads 313system.physmem.wrPerTurnAround::200-203 2 0.00% 99.97% # Writes before turning the bus around for reads 314system.physmem.wrPerTurnAround::204-207 3 0.00% 99.98% # Writes before turning the bus around for reads 315system.physmem.wrPerTurnAround::208-211 2 0.00% 99.98% # Writes before turning the bus around for reads 316system.physmem.wrPerTurnAround::212-215 1 0.00% 99.98% # Writes before turning the bus around for reads 317system.physmem.wrPerTurnAround::216-219 1 0.00% 99.98% # Writes before turning the bus around for reads 318system.physmem.wrPerTurnAround::220-223 5 0.01% 99.99% # Writes before turning the bus around for reads 319system.physmem.wrPerTurnAround::224-227 4 0.00% 99.99% # Writes before turning the bus around for reads 320system.physmem.wrPerTurnAround::228-231 3 0.00% 100.00% # Writes before turning the bus around for reads 321system.physmem.wrPerTurnAround::244-247 2 0.00% 100.00% # Writes before turning the bus around for reads 322system.physmem.wrPerTurnAround::248-251 1 0.00% 100.00% # Writes before turning the bus around for reads 323system.physmem.wrPerTurnAround::total 85700 # Writes before turning the bus around for reads 324system.physmem.totQLat 131185455773 # Total ticks spent queuing 325system.physmem.totMemAccLat 166408324523 # Total ticks spent from burst creation until serviced by the DRAM 326system.physmem.totBusLat 9392765000 # Total ticks spent in databus transfers 327system.physmem.avgQLat 69833.25 # Average queueing delay per DRAM burst 328system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 329system.physmem.avgMemAccLat 88583.25 # Average memory access latency per DRAM burst 330system.physmem.avgRdBW 2.54 # Average DRAM read bandwidth in MiByte/s 331system.physmem.avgWrBW 2.15 # Average achieved write bandwidth in MiByte/s 332system.physmem.avgRdBWSys 2.51 # Average system read bandwidth in MiByte/s 333system.physmem.avgWrBWSys 2.16 # Average system write bandwidth in MiByte/s 334system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 335system.physmem.busUtil 0.04 # Data bus utilization in percentage 336system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 337system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 338system.physmem.avgRdQLen 1.75 # Average read queue length when enqueuing 339system.physmem.avgWrQLen 21.84 # Average write queue length when enqueuing 340system.physmem.readRowHits 1529879 # Number of row buffer hits during reads 341system.physmem.writeRowHits 966437 # Number of row buffer hits during writes 342system.physmem.readRowHitRate 81.44 # Row buffer hit rate for reads 343system.physmem.writeRowHitRate 60.64 # Row buffer hit rate for writes 344system.physmem.avgGap 13625912.35 # Average gap between requests 345system.physmem.pageHitRate 71.89 # Row buffer hit rate, read and write combined 346system.physmem.memoryStateTime::IDLE 45568926392500 # Time in different power states 347system.physmem.memoryStateTime::REF 1583533900000 # Time in different power states 348system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 349system.physmem.memoryStateTime::ACT 269814192000 # Time in different power states 350system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 351system.physmem.actEnergy::0 3837713040 # Energy for activate commands per rank (pJ) 352system.physmem.actEnergy::1 3540506760 # Energy for activate commands per rank (pJ) 353system.physmem.preEnergy::0 2093990250 # Energy for precharge commands per rank (pJ) 354system.physmem.preEnergy::1 1931824125 # Energy for precharge commands per rank (pJ) 355system.physmem.readEnergy::0 7519675800 # Energy for read commands per rank (pJ) 356system.physmem.readEnergy::1 7132967400 # Energy for read commands per rank (pJ) 357system.physmem.writeEnergy::0 5325102000 # Energy for write commands per rank (pJ) 358system.physmem.writeEnergy::1 5002210080 # Energy for write commands per rank (pJ) 359system.physmem.refreshEnergy::0 3097392308400 # Energy for refresh commands per rank (pJ) 360system.physmem.refreshEnergy::1 3097392308400 # Energy for refresh commands per rank (pJ) 361system.physmem.actBackEnergy::0 1175879799405 # Energy for active background per rank (pJ) 362system.physmem.actBackEnergy::1 1172220553305 # Energy for active background per rank (pJ) 363system.physmem.preBackEnergy::0 27421890099000 # Energy for precharge background per rank (pJ) 364system.physmem.preBackEnergy::1 27425099964000 # Energy for precharge background per rank (pJ) 365system.physmem.totalEnergy::0 31713938687895 # Total energy per rank (pJ) 366system.physmem.totalEnergy::1 31712320334070 # Total energy per rank (pJ) 367system.physmem.averagePower::0 668.756196 # Core power per rank (mW) 368system.physmem.averagePower::1 668.722070 # Core power per rank (mW) 369system.realview.nvmem.bytes_read::cpu0.inst 384 # Number of bytes read from this memory 370system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 371system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory 372system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 373system.realview.nvmem.bytes_read::total 572 # Number of bytes read from this memory 374system.realview.nvmem.bytes_inst_read::cpu0.inst 384 # Number of instructions bytes read from this memory 375system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory 376system.realview.nvmem.bytes_inst_read::total 528 # Number of instructions bytes read from this memory 377system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 378system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 379system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory 380system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 381system.realview.nvmem.num_reads::total 39 # Number of read requests responded to by this memory 382system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) 383system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 384system.realview.nvmem.bw_read::cpu1.inst 3 # Total read bandwidth from this memory (bytes/s) 385system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 386system.realview.nvmem.bw_read::total 12 # Total read bandwidth from this memory (bytes/s) 387system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) 388system.realview.nvmem.bw_inst_read::cpu1.inst 3 # Instruction read bandwidth from this memory (bytes/s) 389system.realview.nvmem.bw_inst_read::total 11 # Instruction read bandwidth from this memory (bytes/s) 390system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) 391system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 392system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s) 393system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 394system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s) 395system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 396system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 397system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 398system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 399system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 400system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 401system.cpu0.branchPred.lookups 136692903 # Number of BP lookups 402system.cpu0.branchPred.condPredicted 91051024 # Number of conditional branches predicted 403system.cpu0.branchPred.condIncorrect 6675955 # Number of conditional branches incorrect 404system.cpu0.branchPred.BTBLookups 96641264 # Number of BTB lookups 405system.cpu0.branchPred.BTBHits 62499971 # Number of BTB hits 406system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 407system.cpu0.branchPred.BTBHitPct 64.672137 # BTB Hit Percentage 408system.cpu0.branchPred.usedRAS 18343531 # Number of times the RAS was used to get a target. 409system.cpu0.branchPred.RASInCorrect 188881 # Number of incorrect RAS predictions. 410system.cpu_clk_domain.clock 500 # Clock period in ticks 411system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 412system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 413system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 414system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 415system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 416system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 417system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 418system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 419system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 420system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 421system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 422system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 423system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 424system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 425system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 426system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 427system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 428system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 429system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 430system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 431system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 432system.cpu0.dtb.inst_hits 0 # ITB inst hits 433system.cpu0.dtb.inst_misses 0 # ITB inst misses 434system.cpu0.dtb.read_hits 98285730 # DTB read hits 435system.cpu0.dtb.read_misses 371363 # DTB read misses 436system.cpu0.dtb.write_hits 82429878 # DTB write hits 437system.cpu0.dtb.write_misses 160428 # DTB write misses 438system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 439system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 440system.cpu0.dtb.flush_tlb_mva_asid 44806 # Number of times TLB was flushed by MVA & ASID 441system.cpu0.dtb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID 442system.cpu0.dtb.flush_entries 34259 # Number of entries that have been flushed from TLB 443system.cpu0.dtb.align_faults 107 # Number of TLB faults due to alignment restrictions 444system.cpu0.dtb.prefetch_faults 6211 # Number of TLB faults due to prefetch 445system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 446system.cpu0.dtb.perms_faults 37781 # Number of TLB faults due to permissions restrictions 447system.cpu0.dtb.read_accesses 98657093 # DTB read accesses 448system.cpu0.dtb.write_accesses 82590306 # DTB write accesses 449system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 450system.cpu0.dtb.hits 180715608 # DTB hits 451system.cpu0.dtb.misses 531791 # DTB misses 452system.cpu0.dtb.accesses 181247399 # DTB accesses 453system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 454system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 455system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 456system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 457system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 458system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 459system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 460system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 461system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 462system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 463system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 464system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 465system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 466system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 467system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 468system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 469system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 470system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 471system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 472system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 473system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 474system.cpu0.itb.inst_hits 214588445 # ITB inst hits 475system.cpu0.itb.inst_misses 81035 # ITB inst misses 476system.cpu0.itb.read_hits 0 # DTB read hits 477system.cpu0.itb.read_misses 0 # DTB read misses 478system.cpu0.itb.write_hits 0 # DTB write hits 479system.cpu0.itb.write_misses 0 # DTB write misses 480system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 481system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 482system.cpu0.itb.flush_tlb_mva_asid 44806 # Number of times TLB was flushed by MVA & ASID 483system.cpu0.itb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID 484system.cpu0.itb.flush_entries 24176 # Number of entries that have been flushed from TLB 485system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 486system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 487system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 488system.cpu0.itb.perms_faults 217359 # Number of TLB faults due to permissions restrictions 489system.cpu0.itb.read_accesses 0 # DTB read accesses 490system.cpu0.itb.write_accesses 0 # DTB write accesses 491system.cpu0.itb.inst_accesses 214669480 # ITB inst accesses 492system.cpu0.itb.hits 214588445 # DTB hits 493system.cpu0.itb.misses 81035 # DTB misses 494system.cpu0.itb.accesses 214669480 # DTB accesses 495system.cpu0.numCycles 723605959 # number of cpu cycles simulated 496system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 497system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 498system.cpu0.fetch.icacheStallCycles 84128505 # Number of cycles fetch is stalled on an Icache miss 499system.cpu0.fetch.Insts 603958712 # Number of instructions fetch has processed 500system.cpu0.fetch.Branches 136692903 # Number of branches that fetch encountered 501system.cpu0.fetch.predictedBranches 80843502 # Number of branches that fetch has predicted taken 502system.cpu0.fetch.Cycles 610845531 # Number of cycles fetch has run and was not squashing or blocked 503system.cpu0.fetch.SquashCycles 14389096 # Number of cycles fetch has spent squashing 504system.cpu0.fetch.TlbCycles 1590613 # Number of cycles fetch has spent waiting for tlb 505system.cpu0.fetch.MiscStallCycles 145998 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 506system.cpu0.fetch.PendingTrapStallCycles 6064926 # Number of stall cycles due to pending traps 507system.cpu0.fetch.PendingQuiesceStallCycles 691327 # Number of stall cycles due to pending quiesce instructions 508system.cpu0.fetch.IcacheWaitRetryStallCycles 308415 # Number of stall cycles due to full MSHR 509system.cpu0.fetch.CacheLines 214371554 # Number of cache lines fetched 510system.cpu0.fetch.IcacheSquashes 1629958 # Number of outstanding Icache misses that were squashed 511system.cpu0.fetch.ItlbSquashes 26989 # Number of outstanding ITLB misses that were squashed 512system.cpu0.fetch.rateDist::samples 710969863 # Number of instructions fetched each cycle (Total) 513system.cpu0.fetch.rateDist::mean 0.995603 # Number of instructions fetched each cycle (Total) 514system.cpu0.fetch.rateDist::stdev 1.223531 # Number of instructions fetched each cycle (Total) 515system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 516system.cpu0.fetch.rateDist::0 371943625 52.31% 52.31% # Number of instructions fetched each cycle (Total) 517system.cpu0.fetch.rateDist::1 132005479 18.57% 70.88% # Number of instructions fetched each cycle (Total) 518system.cpu0.fetch.rateDist::2 45223870 6.36% 77.24% # Number of instructions fetched each cycle (Total) 519system.cpu0.fetch.rateDist::3 161796889 22.76% 100.00% # Number of instructions fetched each cycle (Total) 520system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 521system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 522system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 523system.cpu0.fetch.rateDist::total 710969863 # Number of instructions fetched each cycle (Total) 524system.cpu0.fetch.branchRate 0.188905 # Number of branch fetches per cycle 525system.cpu0.fetch.rate 0.834651 # Number of inst fetches per cycle 526system.cpu0.decode.IdleCycles 100859820 # Number of cycles decode is idle 527system.cpu0.decode.BlockedCycles 341670501 # Number of cycles decode is blocked 528system.cpu0.decode.RunCycles 226894689 # Number of cycles decode is running 529system.cpu0.decode.UnblockCycles 36450722 # Number of cycles decode is unblocking 530system.cpu0.decode.SquashCycles 5094131 # Number of cycles decode is squashing 531system.cpu0.decode.BranchResolved 19684552 # Number of times decode resolved a branch 532system.cpu0.decode.BranchMispred 2143149 # Number of times decode detected a branch misprediction 533system.cpu0.decode.DecodedInsts 625299942 # Number of instructions handled by decode 534system.cpu0.decode.SquashedInsts 23465263 # Number of squashed instructions handled by decode 535system.cpu0.rename.SquashCycles 5094131 # Number of cycles rename is squashing 536system.cpu0.rename.IdleCycles 135677386 # Number of cycles rename is idle 537system.cpu0.rename.BlockCycles 49836875 # Number of cycles rename is blocking 538system.cpu0.rename.serializeStallCycles 228336608 # count of cycles rename stalled for serializing inst 539system.cpu0.rename.RunCycles 227963533 # Number of cycles rename is running 540system.cpu0.rename.UnblockCycles 64061330 # Number of cycles rename is unblocking 541system.cpu0.rename.RenamedInsts 608231586 # Number of instructions processed by rename 542system.cpu0.rename.SquashedInsts 5949574 # Number of squashed instructions processed by rename 543system.cpu0.rename.ROBFullEvents 8548374 # Number of times rename has blocked due to ROB full 544system.cpu0.rename.IQFullEvents 231810 # Number of times rename has blocked due to IQ full 545system.cpu0.rename.LQFullEvents 263882 # Number of times rename has blocked due to LQ full 546system.cpu0.rename.SQFullEvents 30185355 # Number of times rename has blocked due to SQ full 547system.cpu0.rename.FullRegisterEvents 12581 # Number of times there has been no free registers 548system.cpu0.rename.RenamedOperands 579905224 # Number of destination operands rename has renamed 549system.cpu0.rename.RenameLookups 937754781 # Number of register rename lookups that rename has made 550system.cpu0.rename.int_rename_lookups 718843517 # Number of integer rename lookups 551system.cpu0.rename.fp_rename_lookups 1013139 # Number of floating rename lookups 552system.cpu0.rename.CommittedMaps 522903039 # Number of HB maps that are committed 553system.cpu0.rename.UndoneMaps 57002179 # Number of HB maps that are undone due to squashing 554system.cpu0.rename.serializingInsts 15055979 # count of serializing insts renamed 555system.cpu0.rename.tempSerializingInsts 13152707 # count of temporary serializing insts renamed 556system.cpu0.rename.skidInsts 73956769 # count of insts added to the skid buffer 557system.cpu0.memDep0.insertedLoads 99026206 # Number of loads inserted to the mem dependence unit. 558system.cpu0.memDep0.insertedStores 85770687 # Number of stores inserted to the mem dependence unit. 559system.cpu0.memDep0.conflictingLoads 8763922 # Number of conflicting loads. 560system.cpu0.memDep0.conflictingStores 7686093 # Number of conflicting stores. 561system.cpu0.iq.iqInstsAdded 586686508 # Number of instructions added to the IQ (excludes non-spec) 562system.cpu0.iq.iqNonSpecInstsAdded 15156086 # Number of non-speculative instructions added to the IQ 563system.cpu0.iq.iqInstsIssued 590156830 # Number of instructions issued 564system.cpu0.iq.iqSquashedInstsIssued 2681738 # Number of squashed instructions issued 565system.cpu0.iq.iqSquashedInstsExamined 50409396 # Number of squashed instructions iterated over during squash; mainly for profiling 566system.cpu0.iq.iqSquashedOperandsExamined 34542071 # Number of squashed operands that are examined and possibly removed from graph 567system.cpu0.iq.iqSquashedNonSpecRemoved 266225 # Number of squashed non-spec instructions that were removed 568system.cpu0.iq.issued_per_cycle::samples 710969863 # Number of insts issued each cycle 569system.cpu0.iq.issued_per_cycle::mean 0.830073 # Number of insts issued each cycle 570system.cpu0.iq.issued_per_cycle::stdev 1.072195 # Number of insts issued each cycle 571system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 572system.cpu0.iq.issued_per_cycle::0 390297771 54.90% 54.90% # Number of insts issued each cycle 573system.cpu0.iq.issued_per_cycle::1 132320625 18.61% 73.51% # Number of insts issued each cycle 574system.cpu0.iq.issued_per_cycle::2 115120103 16.19% 89.70% # Number of insts issued each cycle 575system.cpu0.iq.issued_per_cycle::3 65333726 9.19% 98.89% # Number of insts issued each cycle 576system.cpu0.iq.issued_per_cycle::4 7893369 1.11% 100.00% # Number of insts issued each cycle 577system.cpu0.iq.issued_per_cycle::5 4269 0.00% 100.00% # Number of insts issued each cycle 578system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 579system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 580system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 581system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 582system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 583system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 584system.cpu0.iq.issued_per_cycle::total 710969863 # Number of insts issued each cycle 585system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 586system.cpu0.iq.fu_full::IntAlu 61459839 45.63% 45.63% # attempts to use FU when none available 587system.cpu0.iq.fu_full::IntMult 50531 0.04% 45.66% # attempts to use FU when none available 588system.cpu0.iq.fu_full::IntDiv 24866 0.02% 45.68% # attempts to use FU when none available 589system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.68% # attempts to use FU when none available 590system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.68% # attempts to use FU when none available 591system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.68% # attempts to use FU when none available 592system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.68% # attempts to use FU when none available 593system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.68% # attempts to use FU when none available 594system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.68% # attempts to use FU when none available 595system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.68% # attempts to use FU when none available 596system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.68% # attempts to use FU when none available 597system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.68% # attempts to use FU when none available 598system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.68% # attempts to use FU when none available 599system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.68% # attempts to use FU when none available 600system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.68% # attempts to use FU when none available 601system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.68% # attempts to use FU when none available 602system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.68% # attempts to use FU when none available 603system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.68% # attempts to use FU when none available 604system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.68% # attempts to use FU when none available 605system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.68% # attempts to use FU when none available 606system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.68% # attempts to use FU when none available 607system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.68% # attempts to use FU when none available 608system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.68% # attempts to use FU when none available 609system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.68% # attempts to use FU when none available 610system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.68% # attempts to use FU when none available 611system.cpu0.iq.fu_full::SimdFloatMisc 22 0.00% 45.68% # attempts to use FU when none available 612system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.68% # attempts to use FU when none available 613system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.68% # attempts to use FU when none available 614system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.68% # attempts to use FU when none available 615system.cpu0.iq.fu_full::MemRead 34471783 25.59% 71.27% # attempts to use FU when none available 616system.cpu0.iq.fu_full::MemWrite 38693635 28.73% 100.00% # attempts to use FU when none available 617system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 618system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 619system.cpu0.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued 620system.cpu0.iq.FU_type_0::IntAlu 403696370 68.40% 68.40% # Type of FU issued 621system.cpu0.iq.FU_type_0::IntMult 1373917 0.23% 68.64% # Type of FU issued 622system.cpu0.iq.FU_type_0::IntDiv 72713 0.01% 68.65% # Type of FU issued 623system.cpu0.iq.FU_type_0::FloatAdd 2 0.00% 68.65% # Type of FU issued 624system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.65% # Type of FU issued 625system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.65% # Type of FU issued 626system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.65% # Type of FU issued 627system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.65% # Type of FU issued 628system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.65% # Type of FU issued 629system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.65% # Type of FU issued 630system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.65% # Type of FU issued 631system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.65% # Type of FU issued 632system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.65% # Type of FU issued 633system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.65% # Type of FU issued 634system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.65% # Type of FU issued 635system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.65% # Type of FU issued 636system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.65% # Type of FU issued 637system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.65% # Type of FU issued 638system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.65% # Type of FU issued 639system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.65% # Type of FU issued 640system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.65% # Type of FU issued 641system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.65% # Type of FU issued 642system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.65% # Type of FU issued 643system.cpu0.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.65% # Type of FU issued 644system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.65% # Type of FU issued 645system.cpu0.iq.FU_type_0::SimdFloatMisc 82685 0.01% 68.66% # Type of FU issued 646system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.66% # Type of FU issued 647system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.66% # Type of FU issued 648system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.66% # Type of FU issued 649system.cpu0.iq.FU_type_0::MemRead 101222055 17.15% 85.82% # Type of FU issued 650system.cpu0.iq.FU_type_0::MemWrite 83709039 14.18% 100.00% # Type of FU issued 651system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 652system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 653system.cpu0.iq.FU_type_0::total 590156830 # Type of FU issued 654system.cpu0.iq.rate 0.815578 # Inst issue rate 655system.cpu0.iq.fu_busy_cnt 134700676 # FU busy when requested 656system.cpu0.iq.fu_busy_rate 0.228246 # FU busy rate (busy events/executed inst) 657system.cpu0.iq.int_inst_queue_reads 2027250728 # Number of integer instruction queue reads 658system.cpu0.iq.int_inst_queue_writes 651818194 # Number of integer instruction queue writes 659system.cpu0.iq.int_inst_queue_wakeup_accesses 574107974 # Number of integer instruction queue wakeup accesses 660system.cpu0.iq.fp_inst_queue_reads 1415207 # Number of floating instruction queue reads 661system.cpu0.iq.fp_inst_queue_writes 570288 # Number of floating instruction queue writes 662system.cpu0.iq.fp_inst_queue_wakeup_accesses 525567 # Number of floating instruction queue wakeup accesses 663system.cpu0.iq.int_alu_accesses 723981962 # Number of integer alu accesses 664system.cpu0.iq.fp_alu_accesses 875543 # Number of floating point alu accesses 665system.cpu0.iew.lsq.thread0.forwLoads 2649036 # Number of loads that had data forwarded from stores 666system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 667system.cpu0.iew.lsq.thread0.squashedLoads 12005066 # Number of loads squashed 668system.cpu0.iew.lsq.thread0.ignoredResponses 15997 # Number of memory responses ignored because the instruction is squashed 669system.cpu0.iew.lsq.thread0.memOrderViolation 137574 # Number of memory ordering violations 670system.cpu0.iew.lsq.thread0.squashedStores 5832630 # Number of stores squashed 671system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 672system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 673system.cpu0.iew.lsq.thread0.rescheduledLoads 2633268 # Number of loads that were rescheduled 674system.cpu0.iew.lsq.thread0.cacheBlocked 3783846 # Number of times an access to memory failed due to the cache being blocked 675system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 676system.cpu0.iew.iewSquashCycles 5094131 # Number of cycles IEW is squashing 677system.cpu0.iew.iewBlockCycles 6289107 # Number of cycles IEW is blocking 678system.cpu0.iew.iewUnblockCycles 4809356 # Number of cycles IEW is unblocking 679system.cpu0.iew.iewDispatchedInsts 601961701 # Number of instructions dispatched to IQ 680system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 681system.cpu0.iew.iewDispLoadInsts 99026206 # Number of dispatched load instructions 682system.cpu0.iew.iewDispStoreInsts 85770687 # Number of dispatched store instructions 683system.cpu0.iew.iewDispNonSpecInsts 12881584 # Number of dispatched non-speculative instructions 684system.cpu0.iew.iewIQFullEvents 63147 # Number of times the IQ has become full, causing a stall 685system.cpu0.iew.iewLSQFullEvents 4682481 # Number of times the LSQ has become full, causing a stall 686system.cpu0.iew.memOrderViolationEvents 137574 # Number of memory order violations 687system.cpu0.iew.predictedTakenIncorrect 1984191 # Number of branches that were predicted taken incorrectly 688system.cpu0.iew.predictedNotTakenIncorrect 2898838 # Number of branches that were predicted not taken incorrectly 689system.cpu0.iew.branchMispredicts 4883029 # Number of branch mispredicts detected at execute 690system.cpu0.iew.iewExecutedInsts 582493668 # Number of executed instructions 691system.cpu0.iew.iewExecLoadInsts 98279194 # Number of load instructions executed 692system.cpu0.iew.iewExecSquashedInsts 7144205 # Number of squashed instructions skipped in execute 693system.cpu0.iew.exec_swp 0 # number of swp insts executed 694system.cpu0.iew.exec_nop 119107 # number of nop insts executed 695system.cpu0.iew.exec_refs 180711366 # number of memory reference insts executed 696system.cpu0.iew.exec_branches 110157991 # Number of branches executed 697system.cpu0.iew.exec_stores 82432172 # Number of stores executed 698system.cpu0.iew.exec_rate 0.804987 # Inst execution rate 699system.cpu0.iew.wb_sent 575359382 # cumulative count of insts sent to commit 700system.cpu0.iew.wb_count 574633541 # cumulative count of insts written-back 701system.cpu0.iew.wb_producers 278757047 # num instructions producing a value 702system.cpu0.iew.wb_consumers 457962623 # num instructions consuming a value 703system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 704system.cpu0.iew.wb_rate 0.794125 # insts written-back per cycle 705system.cpu0.iew.wb_fanout 0.608690 # average fanout of values written-back 706system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 707system.cpu0.commit.commitSquashedInsts 46943290 # The number of squashed insts skipped by commit 708system.cpu0.commit.commitNonSpecStalls 14889861 # The number of times commit has been forced to stall to communicate backwards 709system.cpu0.commit.branchMispredicts 4575538 # The number of times a branch was mispredicted 710system.cpu0.commit.committed_per_cycle::samples 702085405 # Number of insts commited each cycle 711system.cpu0.commit.committed_per_cycle::mean 0.780670 # Number of insts commited each cycle 712system.cpu0.commit.committed_per_cycle::stdev 1.579297 # Number of insts commited each cycle 713system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 714system.cpu0.commit.committed_per_cycle::0 463334360 65.99% 65.99% # Number of insts commited each cycle 715system.cpu0.commit.committed_per_cycle::1 122538358 17.45% 83.45% # Number of insts commited each cycle 716system.cpu0.commit.committed_per_cycle::2 53278812 7.59% 91.04% # Number of insts commited each cycle 717system.cpu0.commit.committed_per_cycle::3 18006181 2.56% 93.60% # Number of insts commited each cycle 718system.cpu0.commit.committed_per_cycle::4 13261797 1.89% 95.49% # Number of insts commited each cycle 719system.cpu0.commit.committed_per_cycle::5 8597155 1.22% 96.71% # Number of insts commited each cycle 720system.cpu0.commit.committed_per_cycle::6 5895517 0.84% 97.55% # Number of insts commited each cycle 721system.cpu0.commit.committed_per_cycle::7 3809437 0.54% 98.10% # Number of insts commited each cycle 722system.cpu0.commit.committed_per_cycle::8 13363788 1.90% 100.00% # Number of insts commited each cycle 723system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 724system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 725system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 726system.cpu0.commit.committed_per_cycle::total 702085405 # Number of insts commited each cycle 727system.cpu0.commit.committedInsts 466411686 # Number of instructions committed 728system.cpu0.commit.committedOps 548096953 # Number of ops (including micro ops) committed 729system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 730system.cpu0.commit.refs 166959196 # Number of memory references committed 731system.cpu0.commit.loads 87021139 # Number of loads committed 732system.cpu0.commit.membars 3711025 # Number of memory barriers committed 733system.cpu0.commit.branches 104496556 # Number of branches committed 734system.cpu0.commit.fp_insts 513447 # Number of committed floating point instructions. 735system.cpu0.commit.int_insts 502627891 # Number of committed integer instructions. 736system.cpu0.commit.function_calls 13679873 # Number of function calls committed. 737system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 738system.cpu0.commit.op_class_0::IntAlu 379865208 69.31% 69.31% # Class of committed instruction 739system.cpu0.commit.op_class_0::IntMult 1141082 0.21% 69.51% # Class of committed instruction 740system.cpu0.commit.op_class_0::IntDiv 57492 0.01% 69.52% # Class of committed instruction 741system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.52% # Class of committed instruction 742system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.52% # Class of committed instruction 743system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.52% # Class of committed instruction 744system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.52% # Class of committed instruction 745system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.52% # Class of committed instruction 746system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.52% # Class of committed instruction 747system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.52% # Class of committed instruction 748system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.52% # Class of committed instruction 749system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.52% # Class of committed instruction 750system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.52% # Class of committed instruction 751system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.52% # Class of committed instruction 752system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.52% # Class of committed instruction 753system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.52% # Class of committed instruction 754system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.52% # Class of committed instruction 755system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.52% # Class of committed instruction 756system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.52% # Class of committed instruction 757system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.52% # Class of committed instruction 758system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.52% # Class of committed instruction 759system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.52% # Class of committed instruction 760system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.52% # Class of committed instruction 761system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.52% # Class of committed instruction 762system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.52% # Class of committed instruction 763system.cpu0.commit.op_class_0::SimdFloatMisc 73933 0.01% 69.54% # Class of committed instruction 764system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.54% # Class of committed instruction 765system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.54% # Class of committed instruction 766system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.54% # Class of committed instruction 767system.cpu0.commit.op_class_0::MemRead 87021139 15.88% 85.42% # Class of committed instruction 768system.cpu0.commit.op_class_0::MemWrite 79938057 14.58% 100.00% # Class of committed instruction 769system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 770system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 771system.cpu0.commit.op_class_0::total 548096953 # Class of committed instruction 772system.cpu0.commit.bw_lim_events 13363788 # number cycles where commit BW limit reached 773system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 774system.cpu0.rob.rob_reads 1279505618 # The number of ROB reads 775system.cpu0.rob.rob_writes 1198929363 # The number of ROB writes 776system.cpu0.timesIdled 780048 # Number of times that the entire CPU went into an idle state and unscheduled itself 777system.cpu0.idleCycles 12636096 # Total number of cycles that the CPU has spent unscheduled due to idling 778system.cpu0.quiesceCycles 94120949562 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 779system.cpu0.committedInsts 466411686 # Number of Instructions Simulated 780system.cpu0.committedOps 548096953 # Number of Ops (including micro ops) Simulated 781system.cpu0.cpi 1.551432 # CPI: Cycles Per Instruction 782system.cpu0.cpi_total 1.551432 # CPI: Total CPI of All Threads 783system.cpu0.ipc 0.644566 # IPC: Instructions Per Cycle 784system.cpu0.ipc_total 0.644566 # IPC: Total IPC of All Threads 785system.cpu0.int_regfile_reads 688144011 # number of integer regfile reads 786system.cpu0.int_regfile_writes 408577767 # number of integer regfile writes 787system.cpu0.fp_regfile_reads 842658 # number of floating regfile reads 788system.cpu0.fp_regfile_writes 455584 # number of floating regfile writes 789system.cpu0.cc_regfile_reads 127446024 # number of cc regfile reads 790system.cpu0.cc_regfile_writes 128164594 # number of cc regfile writes 791system.cpu0.misc_regfile_reads 2855519856 # number of misc regfile reads 792system.cpu0.misc_regfile_writes 15107964 # number of misc regfile writes 793system.cpu0.dcache.tags.replacements 5838402 # number of replacements 794system.cpu0.dcache.tags.tagsinuse 504.465464 # Cycle average of tags in use 795system.cpu0.dcache.tags.total_refs 155155227 # Total number of references to valid blocks. 796system.cpu0.dcache.tags.sampled_refs 5838912 # Sample count of references to valid blocks. 797system.cpu0.dcache.tags.avg_refs 26.572626 # Average number of references to valid blocks. 798system.cpu0.dcache.tags.warmup_cycle 1750084500 # Cycle when the warmup percentage was hit. 799system.cpu0.dcache.tags.occ_blocks::cpu0.data 504.465464 # Average occupied blocks per requestor 800system.cpu0.dcache.tags.occ_percent::cpu0.data 0.985284 # Average percentage of cache occupancy 801system.cpu0.dcache.tags.occ_percent::total 0.985284 # Average percentage of cache occupancy 802system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id 803system.cpu0.dcache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id 804system.cpu0.dcache.tags.age_task_id_blocks_1024::1 372 # Occupied blocks per task id 805system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id 806system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id 807system.cpu0.dcache.tags.tag_accesses 346167633 # Number of tag accesses 808system.cpu0.dcache.tags.data_accesses 346167633 # Number of data accesses 809system.cpu0.dcache.ReadReq_hits::cpu0.data 80535549 # number of ReadReq hits 810system.cpu0.dcache.ReadReq_hits::total 80535549 # number of ReadReq hits 811system.cpu0.dcache.WriteReq_hits::cpu0.data 69641264 # number of WriteReq hits 812system.cpu0.dcache.WriteReq_hits::total 69641264 # number of WriteReq hits 813system.cpu0.dcache.SoftPFReq_hits::cpu0.data 207056 # number of SoftPFReq hits 814system.cpu0.dcache.SoftPFReq_hits::total 207056 # number of SoftPFReq hits 815system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 203093 # number of WriteInvalidateReq hits 816system.cpu0.dcache.WriteInvalidateReq_hits::total 203093 # number of WriteInvalidateReq hits 817system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1877400 # number of LoadLockedReq hits 818system.cpu0.dcache.LoadLockedReq_hits::total 1877400 # number of LoadLockedReq hits 819system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1900232 # number of StoreCondReq hits 820system.cpu0.dcache.StoreCondReq_hits::total 1900232 # number of StoreCondReq hits 821system.cpu0.dcache.demand_hits::cpu0.data 150176813 # number of demand (read+write) hits 822system.cpu0.dcache.demand_hits::total 150176813 # number of demand (read+write) hits 823system.cpu0.dcache.overall_hits::cpu0.data 150383869 # number of overall hits 824system.cpu0.dcache.overall_hits::total 150383869 # number of overall hits 825system.cpu0.dcache.ReadReq_misses::cpu0.data 6642832 # number of ReadReq misses 826system.cpu0.dcache.ReadReq_misses::total 6642832 # number of ReadReq misses 827system.cpu0.dcache.WriteReq_misses::cpu0.data 7191098 # number of WriteReq misses 828system.cpu0.dcache.WriteReq_misses::total 7191098 # number of WriteReq misses 829system.cpu0.dcache.SoftPFReq_misses::cpu0.data 692118 # number of SoftPFReq misses 830system.cpu0.dcache.SoftPFReq_misses::total 692118 # number of SoftPFReq misses 831system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 798159 # number of WriteInvalidateReq misses 832system.cpu0.dcache.WriteInvalidateReq_misses::total 798159 # number of WriteInvalidateReq misses 833system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 243998 # number of LoadLockedReq misses 834system.cpu0.dcache.LoadLockedReq_misses::total 243998 # number of LoadLockedReq misses 835system.cpu0.dcache.StoreCondReq_misses::cpu0.data 184133 # number of StoreCondReq misses 836system.cpu0.dcache.StoreCondReq_misses::total 184133 # number of StoreCondReq misses 837system.cpu0.dcache.demand_misses::cpu0.data 13833930 # number of demand (read+write) misses 838system.cpu0.dcache.demand_misses::total 13833930 # number of demand (read+write) misses 839system.cpu0.dcache.overall_misses::cpu0.data 14526048 # number of overall misses 840system.cpu0.dcache.overall_misses::total 14526048 # number of overall misses 841system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 99514286008 # number of ReadReq miss cycles 842system.cpu0.dcache.ReadReq_miss_latency::total 99514286008 # number of ReadReq miss cycles 843system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 115098035706 # number of WriteReq miss cycles 844system.cpu0.dcache.WriteReq_miss_latency::total 115098035706 # number of WriteReq miss cycles 845system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 53560236062 # number of WriteInvalidateReq miss cycles 846system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 53560236062 # number of WriteInvalidateReq miss cycles 847system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3359260407 # number of LoadLockedReq miss cycles 848system.cpu0.dcache.LoadLockedReq_miss_latency::total 3359260407 # number of LoadLockedReq miss cycles 849system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3823760481 # number of StoreCondReq miss cycles 850system.cpu0.dcache.StoreCondReq_miss_latency::total 3823760481 # number of StoreCondReq miss cycles 851system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2172500 # number of StoreCondFailReq miss cycles 852system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2172500 # number of StoreCondFailReq miss cycles 853system.cpu0.dcache.demand_miss_latency::cpu0.data 214612321714 # number of demand (read+write) miss cycles 854system.cpu0.dcache.demand_miss_latency::total 214612321714 # number of demand (read+write) miss cycles 855system.cpu0.dcache.overall_miss_latency::cpu0.data 214612321714 # number of overall miss cycles 856system.cpu0.dcache.overall_miss_latency::total 214612321714 # number of overall miss cycles 857system.cpu0.dcache.ReadReq_accesses::cpu0.data 87178381 # number of ReadReq accesses(hits+misses) 858system.cpu0.dcache.ReadReq_accesses::total 87178381 # number of ReadReq accesses(hits+misses) 859system.cpu0.dcache.WriteReq_accesses::cpu0.data 76832362 # number of WriteReq accesses(hits+misses) 860system.cpu0.dcache.WriteReq_accesses::total 76832362 # number of WriteReq accesses(hits+misses) 861system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 899174 # number of SoftPFReq accesses(hits+misses) 862system.cpu0.dcache.SoftPFReq_accesses::total 899174 # number of SoftPFReq accesses(hits+misses) 863system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1001252 # number of WriteInvalidateReq accesses(hits+misses) 864system.cpu0.dcache.WriteInvalidateReq_accesses::total 1001252 # number of WriteInvalidateReq accesses(hits+misses) 865system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2121398 # number of LoadLockedReq accesses(hits+misses) 866system.cpu0.dcache.LoadLockedReq_accesses::total 2121398 # number of LoadLockedReq accesses(hits+misses) 867system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2084365 # number of StoreCondReq accesses(hits+misses) 868system.cpu0.dcache.StoreCondReq_accesses::total 2084365 # number of StoreCondReq accesses(hits+misses) 869system.cpu0.dcache.demand_accesses::cpu0.data 164010743 # number of demand (read+write) accesses 870system.cpu0.dcache.demand_accesses::total 164010743 # number of demand (read+write) accesses 871system.cpu0.dcache.overall_accesses::cpu0.data 164909917 # number of overall (read+write) accesses 872system.cpu0.dcache.overall_accesses::total 164909917 # number of overall (read+write) accesses 873system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.076198 # miss rate for ReadReq accesses 874system.cpu0.dcache.ReadReq_miss_rate::total 0.076198 # miss rate for ReadReq accesses 875system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.093595 # miss rate for WriteReq accesses 876system.cpu0.dcache.WriteReq_miss_rate::total 0.093595 # miss rate for WriteReq accesses 877system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.769726 # miss rate for SoftPFReq accesses 878system.cpu0.dcache.SoftPFReq_miss_rate::total 0.769726 # miss rate for SoftPFReq accesses 879system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.797161 # miss rate for WriteInvalidateReq accesses 880system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.797161 # miss rate for WriteInvalidateReq accesses 881system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.115018 # miss rate for LoadLockedReq accesses 882system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.115018 # miss rate for LoadLockedReq accesses 883system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.088340 # miss rate for StoreCondReq accesses 884system.cpu0.dcache.StoreCondReq_miss_rate::total 0.088340 # miss rate for StoreCondReq accesses 885system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084348 # miss rate for demand accesses 886system.cpu0.dcache.demand_miss_rate::total 0.084348 # miss rate for demand accesses 887system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088085 # miss rate for overall accesses 888system.cpu0.dcache.overall_miss_rate::total 0.088085 # miss rate for overall accesses 889system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14980.701907 # average ReadReq miss latency 890system.cpu0.dcache.ReadReq_avg_miss_latency::total 14980.701907 # average ReadReq miss latency 891system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 16005.627472 # average WriteReq miss latency 892system.cpu0.dcache.WriteReq_avg_miss_latency::total 16005.627472 # average WriteReq miss latency 893system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 67104.719814 # average WriteInvalidateReq miss latency 894system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 67104.719814 # average WriteInvalidateReq miss latency 895system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13767.573533 # average LoadLockedReq miss latency 896system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13767.573533 # average LoadLockedReq miss latency 897system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 20766.296541 # average StoreCondReq miss latency 898system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20766.296541 # average StoreCondReq miss latency 899system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 900system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 901system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15513.474603 # average overall miss latency 902system.cpu0.dcache.demand_avg_miss_latency::total 15513.474603 # average overall miss latency 903system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14774.309001 # average overall miss latency 904system.cpu0.dcache.overall_avg_miss_latency::total 14774.309001 # average overall miss latency 905system.cpu0.dcache.blocked_cycles::no_mshrs 16118603 # number of cycles access was blocked 906system.cpu0.dcache.blocked_cycles::no_targets 16176348 # number of cycles access was blocked 907system.cpu0.dcache.blocked::no_mshrs 692801 # number of cycles access was blocked 908system.cpu0.dcache.blocked::no_targets 696412 # number of cycles access was blocked 909system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.265848 # average number of cycles each access was blocked 910system.cpu0.dcache.avg_blocked_cycles::no_targets 23.228129 # average number of cycles each access was blocked 911system.cpu0.dcache.fast_writes 0 # number of fast writes performed 912system.cpu0.dcache.cache_copies 0 # number of cache copies performed 913system.cpu0.dcache.writebacks::writebacks 3975125 # number of writebacks 914system.cpu0.dcache.writebacks::total 3975125 # number of writebacks 915system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3497983 # number of ReadReq MSHR hits 916system.cpu0.dcache.ReadReq_mshr_hits::total 3497983 # number of ReadReq MSHR hits 917system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5763188 # number of WriteReq MSHR hits 918system.cpu0.dcache.WriteReq_mshr_hits::total 5763188 # number of WriteReq MSHR hits 919system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 4492 # number of WriteInvalidateReq MSHR hits 920system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 4492 # number of WriteInvalidateReq MSHR hits 921system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 123982 # number of LoadLockedReq MSHR hits 922system.cpu0.dcache.LoadLockedReq_mshr_hits::total 123982 # number of LoadLockedReq MSHR hits 923system.cpu0.dcache.demand_mshr_hits::cpu0.data 9261171 # number of demand (read+write) MSHR hits 924system.cpu0.dcache.demand_mshr_hits::total 9261171 # number of demand (read+write) MSHR hits 925system.cpu0.dcache.overall_mshr_hits::cpu0.data 9261171 # number of overall MSHR hits 926system.cpu0.dcache.overall_mshr_hits::total 9261171 # number of overall MSHR hits 927system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3144849 # number of ReadReq MSHR misses 928system.cpu0.dcache.ReadReq_mshr_misses::total 3144849 # number of ReadReq MSHR misses 929system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1427910 # number of WriteReq MSHR misses 930system.cpu0.dcache.WriteReq_mshr_misses::total 1427910 # number of WriteReq MSHR misses 931system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 685927 # number of SoftPFReq MSHR misses 932system.cpu0.dcache.SoftPFReq_mshr_misses::total 685927 # number of SoftPFReq MSHR misses 933system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 793667 # number of WriteInvalidateReq MSHR misses 934system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 793667 # number of WriteInvalidateReq MSHR misses 935system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 120016 # number of LoadLockedReq MSHR misses 936system.cpu0.dcache.LoadLockedReq_mshr_misses::total 120016 # number of LoadLockedReq MSHR misses 937system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 184129 # number of StoreCondReq MSHR misses 938system.cpu0.dcache.StoreCondReq_mshr_misses::total 184129 # number of StoreCondReq MSHR misses 939system.cpu0.dcache.demand_mshr_misses::cpu0.data 4572759 # number of demand (read+write) MSHR misses 940system.cpu0.dcache.demand_mshr_misses::total 4572759 # number of demand (read+write) MSHR misses 941system.cpu0.dcache.overall_mshr_misses::cpu0.data 5258686 # number of overall MSHR misses 942system.cpu0.dcache.overall_mshr_misses::total 5258686 # number of overall MSHR misses 943system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 40981205496 # number of ReadReq MSHR miss cycles 944system.cpu0.dcache.ReadReq_mshr_miss_latency::total 40981205496 # number of ReadReq MSHR miss cycles 945system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 22755476630 # number of WriteReq MSHR miss cycles 946system.cpu0.dcache.WriteReq_mshr_miss_latency::total 22755476630 # number of WriteReq MSHR miss cycles 947system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17996613568 # number of SoftPFReq MSHR miss cycles 948system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17996613568 # number of SoftPFReq MSHR miss cycles 949system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 51855736982 # number of WriteInvalidateReq MSHR miss cycles 950system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 51855736982 # number of WriteInvalidateReq MSHR miss cycles 951system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1434297417 # number of LoadLockedReq MSHR miss cycles 952system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1434297417 # number of LoadLockedReq MSHR miss cycles 953system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3446370519 # number of StoreCondReq MSHR miss cycles 954system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3446370519 # number of StoreCondReq MSHR miss cycles 955system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2070500 # number of StoreCondFailReq MSHR miss cycles 956system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2070500 # number of StoreCondFailReq MSHR miss cycles 957system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 63736682126 # number of demand (read+write) MSHR miss cycles 958system.cpu0.dcache.demand_mshr_miss_latency::total 63736682126 # number of demand (read+write) MSHR miss cycles 959system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 81733295694 # number of overall MSHR miss cycles 960system.cpu0.dcache.overall_mshr_miss_latency::total 81733295694 # number of overall MSHR miss cycles 961system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5581760391 # number of ReadReq MSHR uncacheable cycles 962system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5581760391 # number of ReadReq MSHR uncacheable cycles 963system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5277895398 # number of WriteReq MSHR uncacheable cycles 964system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5277895398 # number of WriteReq MSHR uncacheable cycles 965system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10859655789 # number of overall MSHR uncacheable cycles 966system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10859655789 # number of overall MSHR uncacheable cycles 967system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036074 # mshr miss rate for ReadReq accesses 968system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036074 # mshr miss rate for ReadReq accesses 969system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018585 # mshr miss rate for WriteReq accesses 970system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018585 # mshr miss rate for WriteReq accesses 971system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.762841 # mshr miss rate for SoftPFReq accesses 972system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.762841 # mshr miss rate for SoftPFReq accesses 973system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.792675 # mshr miss rate for WriteInvalidateReq accesses 974system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.792675 # mshr miss rate for WriteInvalidateReq accesses 975system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056574 # mshr miss rate for LoadLockedReq accesses 976system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056574 # mshr miss rate for LoadLockedReq accesses 977system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.088338 # mshr miss rate for StoreCondReq accesses 978system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.088338 # mshr miss rate for StoreCondReq accesses 979system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027881 # mshr miss rate for demand accesses 980system.cpu0.dcache.demand_mshr_miss_rate::total 0.027881 # mshr miss rate for demand accesses 981system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031888 # mshr miss rate for overall accesses 982system.cpu0.dcache.overall_mshr_miss_rate::total 0.031888 # mshr miss rate for overall accesses 983system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13031.215647 # average ReadReq mshr miss latency 984system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13031.215647 # average ReadReq mshr miss latency 985system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15936.212107 # average WriteReq mshr miss latency 986system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15936.212107 # average WriteReq mshr miss latency 987system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26236.922541 # average SoftPFReq mshr miss latency 988system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26236.922541 # average SoftPFReq mshr miss latency 989system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 65336.894418 # average WriteInvalidateReq mshr miss latency 990system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 65336.894418 # average WriteInvalidateReq mshr miss latency 991system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11950.885024 # average LoadLockedReq mshr miss latency 992system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11950.885024 # average LoadLockedReq mshr miss latency 993system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 18717.152209 # average StoreCondReq mshr miss latency 994system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18717.152209 # average StoreCondReq mshr miss latency 995system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 996system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 997system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13938.342722 # average overall mshr miss latency 998system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13938.342722 # average overall mshr miss latency 999system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15542.532050 # average overall mshr miss latency 1000system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15542.532050 # average overall mshr miss latency 1001system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1002system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1003system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1004system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1005system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1006system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1007system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1008system.cpu0.icache.tags.replacements 6042830 # number of replacements 1009system.cpu0.icache.tags.tagsinuse 511.967320 # Cycle average of tags in use 1010system.cpu0.icache.tags.total_refs 208050611 # Total number of references to valid blocks. 1011system.cpu0.icache.tags.sampled_refs 6043342 # Sample count of references to valid blocks. 1012system.cpu0.icache.tags.avg_refs 34.426417 # Average number of references to valid blocks. 1013system.cpu0.icache.tags.warmup_cycle 11201042000 # Cycle when the warmup percentage was hit. 1014system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.967320 # Average occupied blocks per requestor 1015system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999936 # Average percentage of cache occupancy 1016system.cpu0.icache.tags.occ_percent::total 0.999936 # Average percentage of cache occupancy 1017system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1018system.cpu0.icache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id 1019system.cpu0.icache.tags.age_task_id_blocks_1024::1 331 # Occupied blocks per task id 1020system.cpu0.icache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id 1021system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1022system.cpu0.icache.tags.tag_accesses 434737408 # Number of tag accesses 1023system.cpu0.icache.tags.data_accesses 434737408 # Number of data accesses 1024system.cpu0.icache.ReadReq_hits::cpu0.inst 208050611 # number of ReadReq hits 1025system.cpu0.icache.ReadReq_hits::total 208050611 # number of ReadReq hits 1026system.cpu0.icache.demand_hits::cpu0.inst 208050611 # number of demand (read+write) hits 1027system.cpu0.icache.demand_hits::total 208050611 # number of demand (read+write) hits 1028system.cpu0.icache.overall_hits::cpu0.inst 208050611 # number of overall hits 1029system.cpu0.icache.overall_hits::total 208050611 # number of overall hits 1030system.cpu0.icache.ReadReq_misses::cpu0.inst 6296413 # number of ReadReq misses 1031system.cpu0.icache.ReadReq_misses::total 6296413 # number of ReadReq misses 1032system.cpu0.icache.demand_misses::cpu0.inst 6296413 # number of demand (read+write) misses 1033system.cpu0.icache.demand_misses::total 6296413 # number of demand (read+write) misses 1034system.cpu0.icache.overall_misses::cpu0.inst 6296413 # number of overall misses 1035system.cpu0.icache.overall_misses::total 6296413 # number of overall misses 1036system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 55127710497 # number of ReadReq miss cycles 1037system.cpu0.icache.ReadReq_miss_latency::total 55127710497 # number of ReadReq miss cycles 1038system.cpu0.icache.demand_miss_latency::cpu0.inst 55127710497 # number of demand (read+write) miss cycles 1039system.cpu0.icache.demand_miss_latency::total 55127710497 # number of demand (read+write) miss cycles 1040system.cpu0.icache.overall_miss_latency::cpu0.inst 55127710497 # number of overall miss cycles 1041system.cpu0.icache.overall_miss_latency::total 55127710497 # number of overall miss cycles 1042system.cpu0.icache.ReadReq_accesses::cpu0.inst 214347024 # number of ReadReq accesses(hits+misses) 1043system.cpu0.icache.ReadReq_accesses::total 214347024 # number of ReadReq accesses(hits+misses) 1044system.cpu0.icache.demand_accesses::cpu0.inst 214347024 # number of demand (read+write) accesses 1045system.cpu0.icache.demand_accesses::total 214347024 # number of demand (read+write) accesses 1046system.cpu0.icache.overall_accesses::cpu0.inst 214347024 # number of overall (read+write) accesses 1047system.cpu0.icache.overall_accesses::total 214347024 # number of overall (read+write) accesses 1048system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029375 # miss rate for ReadReq accesses 1049system.cpu0.icache.ReadReq_miss_rate::total 0.029375 # miss rate for ReadReq accesses 1050system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029375 # miss rate for demand accesses 1051system.cpu0.icache.demand_miss_rate::total 0.029375 # miss rate for demand accesses 1052system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029375 # miss rate for overall accesses 1053system.cpu0.icache.overall_miss_rate::total 0.029375 # miss rate for overall accesses 1054system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8755.415265 # average ReadReq miss latency 1055system.cpu0.icache.ReadReq_avg_miss_latency::total 8755.415265 # average ReadReq miss latency 1056system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8755.415265 # average overall miss latency 1057system.cpu0.icache.demand_avg_miss_latency::total 8755.415265 # average overall miss latency 1058system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8755.415265 # average overall miss latency 1059system.cpu0.icache.overall_avg_miss_latency::total 8755.415265 # average overall miss latency 1060system.cpu0.icache.blocked_cycles::no_mshrs 4477144 # number of cycles access was blocked 1061system.cpu0.icache.blocked_cycles::no_targets 62 # number of cycles access was blocked 1062system.cpu0.icache.blocked::no_mshrs 570538 # number of cycles access was blocked 1063system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked 1064system.cpu0.icache.avg_blocked_cycles::no_mshrs 7.847232 # average number of cycles each access was blocked 1065system.cpu0.icache.avg_blocked_cycles::no_targets 62 # average number of cycles each access was blocked 1066system.cpu0.icache.fast_writes 0 # number of fast writes performed 1067system.cpu0.icache.cache_copies 0 # number of cache copies performed 1068system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 253053 # number of ReadReq MSHR hits 1069system.cpu0.icache.ReadReq_mshr_hits::total 253053 # number of ReadReq MSHR hits 1070system.cpu0.icache.demand_mshr_hits::cpu0.inst 253053 # number of demand (read+write) MSHR hits 1071system.cpu0.icache.demand_mshr_hits::total 253053 # number of demand (read+write) MSHR hits 1072system.cpu0.icache.overall_mshr_hits::cpu0.inst 253053 # number of overall MSHR hits 1073system.cpu0.icache.overall_mshr_hits::total 253053 # number of overall MSHR hits 1074system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6043360 # number of ReadReq MSHR misses 1075system.cpu0.icache.ReadReq_mshr_misses::total 6043360 # number of ReadReq MSHR misses 1076system.cpu0.icache.demand_mshr_misses::cpu0.inst 6043360 # number of demand (read+write) MSHR misses 1077system.cpu0.icache.demand_mshr_misses::total 6043360 # number of demand (read+write) MSHR misses 1078system.cpu0.icache.overall_mshr_misses::cpu0.inst 6043360 # number of overall MSHR misses 1079system.cpu0.icache.overall_mshr_misses::total 6043360 # number of overall MSHR misses 1080system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 44707631164 # number of ReadReq MSHR miss cycles 1081system.cpu0.icache.ReadReq_mshr_miss_latency::total 44707631164 # number of ReadReq MSHR miss cycles 1082system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 44707631164 # number of demand (read+write) MSHR miss cycles 1083system.cpu0.icache.demand_mshr_miss_latency::total 44707631164 # number of demand (read+write) MSHR miss cycles 1084system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 44707631164 # number of overall MSHR miss cycles 1085system.cpu0.icache.overall_mshr_miss_latency::total 44707631164 # number of overall MSHR miss cycles 1086system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1699559498 # number of ReadReq MSHR uncacheable cycles 1087system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1699559498 # number of ReadReq MSHR uncacheable cycles 1088system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1699559498 # number of overall MSHR uncacheable cycles 1089system.cpu0.icache.overall_mshr_uncacheable_latency::total 1699559498 # number of overall MSHR uncacheable cycles 1090system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028194 # mshr miss rate for ReadReq accesses 1091system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028194 # mshr miss rate for ReadReq accesses 1092system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028194 # mshr miss rate for demand accesses 1093system.cpu0.icache.demand_mshr_miss_rate::total 0.028194 # mshr miss rate for demand accesses 1094system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028194 # mshr miss rate for overall accesses 1095system.cpu0.icache.overall_mshr_miss_rate::total 0.028194 # mshr miss rate for overall accesses 1096system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7397.810351 # average ReadReq mshr miss latency 1097system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7397.810351 # average ReadReq mshr miss latency 1098system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7397.810351 # average overall mshr miss latency 1099system.cpu0.icache.demand_avg_mshr_miss_latency::total 7397.810351 # average overall mshr miss latency 1100system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7397.810351 # average overall mshr miss latency 1101system.cpu0.icache.overall_avg_mshr_miss_latency::total 7397.810351 # average overall mshr miss latency 1102system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1103system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1104system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1105system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1106system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1107system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 60184765 # number of hwpf identified 1108system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 4393414 # number of hwpf that were already in mshr 1109system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 48808124 # number of hwpf that were already in the cache 1110system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 3087530 # number of hwpf that were already in the prefetch queue 1111system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 1112system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 452633 # number of hwpf removed because MSHR allocated 1113system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 3443064 # number of hwpf issued 1114system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 5114963 # number of hwpf spanning a virtual page 1115system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 1116system.cpu0.l2cache.tags.replacements 4158550 # number of replacements 1117system.cpu0.l2cache.tags.tagsinuse 16214.275256 # Cycle average of tags in use 1118system.cpu0.l2cache.tags.total_refs 12594287 # Total number of references to valid blocks. 1119system.cpu0.l2cache.tags.sampled_refs 4174696 # Sample count of references to valid blocks. 1120system.cpu0.l2cache.tags.avg_refs 3.016815 # Average number of references to valid blocks. 1121system.cpu0.l2cache.tags.warmup_cycle 9944532000 # Cycle when the warmup percentage was hit. 1122system.cpu0.l2cache.tags.occ_blocks::writebacks 3315.303513 # Average occupied blocks per requestor 1123system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 38.862270 # Average occupied blocks per requestor 1124system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 22.140550 # Average occupied blocks per requestor 1125system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 967.067959 # Average occupied blocks per requestor 1126system.cpu0.l2cache.tags.occ_blocks::cpu0.data 2910.372119 # Average occupied blocks per requestor 1127system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 8960.528846 # Average occupied blocks per requestor 1128system.cpu0.l2cache.tags.occ_percent::writebacks 0.202350 # Average percentage of cache occupancy 1129system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002372 # Average percentage of cache occupancy 1130system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001351 # Average percentage of cache occupancy 1131system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.059025 # Average percentage of cache occupancy 1132system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.177635 # Average percentage of cache occupancy 1133system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.546907 # Average percentage of cache occupancy 1134system.cpu0.l2cache.tags.occ_percent::total 0.989641 # Average percentage of cache occupancy 1135system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8340 # Occupied blocks per task id 1136system.cpu0.l2cache.tags.occ_task_id_blocks::1023 78 # Occupied blocks per task id 1137system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7728 # Occupied blocks per task id 1138system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 111 # Occupied blocks per task id 1139system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 951 # Occupied blocks per task id 1140system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 3646 # Occupied blocks per task id 1141system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 2631 # Occupied blocks per task id 1142system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1001 # Occupied blocks per task id 1143system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 51 # Occupied blocks per task id 1144system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id 1145system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id 1146system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id 1147system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1103 # Occupied blocks per task id 1148system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3816 # Occupied blocks per task id 1149system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2122 # Occupied blocks per task id 1150system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 566 # Occupied blocks per task id 1151system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.509033 # Percentage of cache occupancy per task id 1152system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004761 # Percentage of cache occupancy per task id 1153system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.471680 # Percentage of cache occupancy per task id 1154system.cpu0.l2cache.tags.tag_accesses 280330704 # Number of tag accesses 1155system.cpu0.l2cache.tags.data_accesses 280330704 # Number of data accesses 1156system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 522125 # number of ReadReq hits 1157system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 166946 # number of ReadReq hits 1158system.cpu0.l2cache.ReadReq_hits::cpu0.inst 5796903 # number of ReadReq hits 1159system.cpu0.l2cache.ReadReq_hits::cpu0.data 2821623 # number of ReadReq hits 1160system.cpu0.l2cache.ReadReq_hits::total 9307597 # number of ReadReq hits 1161system.cpu0.l2cache.Writeback_hits::writebacks 3975115 # number of Writeback hits 1162system.cpu0.l2cache.Writeback_hits::total 3975115 # number of Writeback hits 1163system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 222232 # number of WriteInvalidateReq hits 1164system.cpu0.l2cache.WriteInvalidateReq_hits::total 222232 # number of WriteInvalidateReq hits 1165system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 121282 # number of UpgradeReq hits 1166system.cpu0.l2cache.UpgradeReq_hits::total 121282 # number of UpgradeReq hits 1167system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 38571 # number of SCUpgradeReq hits 1168system.cpu0.l2cache.SCUpgradeReq_hits::total 38571 # number of SCUpgradeReq hits 1169system.cpu0.l2cache.ReadExReq_hits::cpu0.data 940340 # number of ReadExReq hits 1170system.cpu0.l2cache.ReadExReq_hits::total 940340 # number of ReadExReq hits 1171system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 522125 # number of demand (read+write) hits 1172system.cpu0.l2cache.demand_hits::cpu0.itb.walker 166946 # number of demand (read+write) hits 1173system.cpu0.l2cache.demand_hits::cpu0.inst 5796903 # number of demand (read+write) hits 1174system.cpu0.l2cache.demand_hits::cpu0.data 3761963 # number of demand (read+write) hits 1175system.cpu0.l2cache.demand_hits::total 10247937 # number of demand (read+write) hits 1176system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 522125 # number of overall hits 1177system.cpu0.l2cache.overall_hits::cpu0.itb.walker 166946 # number of overall hits 1178system.cpu0.l2cache.overall_hits::cpu0.inst 5796903 # number of overall hits 1179system.cpu0.l2cache.overall_hits::cpu0.data 3761963 # number of overall hits 1180system.cpu0.l2cache.overall_hits::total 10247937 # number of overall hits 1181system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 13861 # number of ReadReq misses 1182system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9822 # number of ReadReq misses 1183system.cpu0.l2cache.ReadReq_misses::cpu0.inst 246435 # number of ReadReq misses 1184system.cpu0.l2cache.ReadReq_misses::cpu0.data 1125045 # number of ReadReq misses 1185system.cpu0.l2cache.ReadReq_misses::total 1395163 # number of ReadReq misses 1186system.cpu0.l2cache.Writeback_misses::writebacks 7 # number of Writeback misses 1187system.cpu0.l2cache.Writeback_misses::total 7 # number of Writeback misses 1188system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 570059 # number of WriteInvalidateReq misses 1189system.cpu0.l2cache.WriteInvalidateReq_misses::total 570059 # number of WriteInvalidateReq misses 1190system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 122791 # number of UpgradeReq misses 1191system.cpu0.l2cache.UpgradeReq_misses::total 122791 # number of UpgradeReq misses 1192system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 145551 # number of SCUpgradeReq misses 1193system.cpu0.l2cache.SCUpgradeReq_misses::total 145551 # number of SCUpgradeReq misses 1194system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 7 # number of SCUpgradeFailReq misses 1195system.cpu0.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses 1196system.cpu0.l2cache.ReadExReq_misses::cpu0.data 254425 # number of ReadExReq misses 1197system.cpu0.l2cache.ReadExReq_misses::total 254425 # number of ReadExReq misses 1198system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 13861 # number of demand (read+write) misses 1199system.cpu0.l2cache.demand_misses::cpu0.itb.walker 9822 # number of demand (read+write) misses 1200system.cpu0.l2cache.demand_misses::cpu0.inst 246435 # number of demand (read+write) misses 1201system.cpu0.l2cache.demand_misses::cpu0.data 1379470 # number of demand (read+write) misses 1202system.cpu0.l2cache.demand_misses::total 1649588 # number of demand (read+write) misses 1203system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 13861 # number of overall misses 1204system.cpu0.l2cache.overall_misses::cpu0.itb.walker 9822 # number of overall misses 1205system.cpu0.l2cache.overall_misses::cpu0.inst 246435 # number of overall misses 1206system.cpu0.l2cache.overall_misses::cpu0.data 1379470 # number of overall misses 1207system.cpu0.l2cache.overall_misses::total 1649588 # number of overall misses 1208system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 480401321 # number of ReadReq miss cycles 1209system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 335313359 # number of ReadReq miss cycles 1210system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 6760403458 # number of ReadReq miss cycles 1211system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 39140642193 # number of ReadReq miss cycles 1212system.cpu0.l2cache.ReadReq_miss_latency::total 46716760331 # number of ReadReq miss cycles 1213system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 45434423993 # number of WriteInvalidateReq miss cycles 1214system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 45434423993 # number of WriteInvalidateReq miss cycles 1215system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2483631237 # number of UpgradeReq miss cycles 1216system.cpu0.l2cache.UpgradeReq_miss_latency::total 2483631237 # number of UpgradeReq miss cycles 1217system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2949204388 # number of SCUpgradeReq miss cycles 1218system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2949204388 # number of SCUpgradeReq miss cycles 1219system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2019500 # number of SCUpgradeFailReq miss cycles 1220system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2019500 # number of SCUpgradeFailReq miss cycles 1221system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 11373473627 # number of ReadExReq miss cycles 1222system.cpu0.l2cache.ReadExReq_miss_latency::total 11373473627 # number of ReadExReq miss cycles 1223system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 480401321 # number of demand (read+write) miss cycles 1224system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 335313359 # number of demand (read+write) miss cycles 1225system.cpu0.l2cache.demand_miss_latency::cpu0.inst 6760403458 # number of demand (read+write) miss cycles 1226system.cpu0.l2cache.demand_miss_latency::cpu0.data 50514115820 # number of demand (read+write) miss cycles 1227system.cpu0.l2cache.demand_miss_latency::total 58090233958 # number of demand (read+write) miss cycles 1228system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 480401321 # number of overall miss cycles 1229system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 335313359 # number of overall miss cycles 1230system.cpu0.l2cache.overall_miss_latency::cpu0.inst 6760403458 # number of overall miss cycles 1231system.cpu0.l2cache.overall_miss_latency::cpu0.data 50514115820 # number of overall miss cycles 1232system.cpu0.l2cache.overall_miss_latency::total 58090233958 # number of overall miss cycles 1233system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 535986 # number of ReadReq accesses(hits+misses) 1234system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 176768 # number of ReadReq accesses(hits+misses) 1235system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 6043338 # number of ReadReq accesses(hits+misses) 1236system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3946668 # number of ReadReq accesses(hits+misses) 1237system.cpu0.l2cache.ReadReq_accesses::total 10702760 # number of ReadReq accesses(hits+misses) 1238system.cpu0.l2cache.Writeback_accesses::writebacks 3975122 # number of Writeback accesses(hits+misses) 1239system.cpu0.l2cache.Writeback_accesses::total 3975122 # number of Writeback accesses(hits+misses) 1240system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 792291 # number of WriteInvalidateReq accesses(hits+misses) 1241system.cpu0.l2cache.WriteInvalidateReq_accesses::total 792291 # number of WriteInvalidateReq accesses(hits+misses) 1242system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 244073 # number of UpgradeReq accesses(hits+misses) 1243system.cpu0.l2cache.UpgradeReq_accesses::total 244073 # number of UpgradeReq accesses(hits+misses) 1244system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 184122 # number of SCUpgradeReq accesses(hits+misses) 1245system.cpu0.l2cache.SCUpgradeReq_accesses::total 184122 # number of SCUpgradeReq accesses(hits+misses) 1246system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 7 # number of SCUpgradeFailReq accesses(hits+misses) 1247system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses) 1248system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1194765 # number of ReadExReq accesses(hits+misses) 1249system.cpu0.l2cache.ReadExReq_accesses::total 1194765 # number of ReadExReq accesses(hits+misses) 1250system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 535986 # number of demand (read+write) accesses 1251system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 176768 # number of demand (read+write) accesses 1252system.cpu0.l2cache.demand_accesses::cpu0.inst 6043338 # number of demand (read+write) accesses 1253system.cpu0.l2cache.demand_accesses::cpu0.data 5141433 # number of demand (read+write) accesses 1254system.cpu0.l2cache.demand_accesses::total 11897525 # number of demand (read+write) accesses 1255system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 535986 # number of overall (read+write) accesses 1256system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 176768 # number of overall (read+write) accesses 1257system.cpu0.l2cache.overall_accesses::cpu0.inst 6043338 # number of overall (read+write) accesses 1258system.cpu0.l2cache.overall_accesses::cpu0.data 5141433 # number of overall (read+write) accesses 1259system.cpu0.l2cache.overall_accesses::total 11897525 # number of overall (read+write) accesses 1260system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.025861 # miss rate for ReadReq accesses 1261system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.055564 # miss rate for ReadReq accesses 1262system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040778 # miss rate for ReadReq accesses 1263system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.285062 # miss rate for ReadReq accesses 1264system.cpu0.l2cache.ReadReq_miss_rate::total 0.130355 # miss rate for ReadReq accesses 1265system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000002 # miss rate for Writeback accesses 1266system.cpu0.l2cache.Writeback_miss_rate::total 0.000002 # miss rate for Writeback accesses 1267system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.719507 # miss rate for WriteInvalidateReq accesses 1268system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.719507 # miss rate for WriteInvalidateReq accesses 1269system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.503091 # miss rate for UpgradeReq accesses 1270system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.503091 # miss rate for UpgradeReq accesses 1271system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.790514 # miss rate for SCUpgradeReq accesses 1272system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.790514 # miss rate for SCUpgradeReq accesses 1273system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1274system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1275system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.212950 # miss rate for ReadExReq accesses 1276system.cpu0.l2cache.ReadExReq_miss_rate::total 0.212950 # miss rate for ReadExReq accesses 1277system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.025861 # miss rate for demand accesses 1278system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.055564 # miss rate for demand accesses 1279system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040778 # miss rate for demand accesses 1280system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.268305 # miss rate for demand accesses 1281system.cpu0.l2cache.demand_miss_rate::total 0.138650 # miss rate for demand accesses 1282system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.025861 # miss rate for overall accesses 1283system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.055564 # miss rate for overall accesses 1284system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040778 # miss rate for overall accesses 1285system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.268305 # miss rate for overall accesses 1286system.cpu0.l2cache.overall_miss_rate::total 0.138650 # miss rate for overall accesses 1287system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34658.489359 # average ReadReq miss latency 1288system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 34139.010283 # average ReadReq miss latency 1289system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 27432.805640 # average ReadReq miss latency 1290system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 34790.290338 # average ReadReq miss latency 1291system.cpu0.l2cache.ReadReq_avg_miss_latency::total 33484.804522 # average ReadReq miss latency 1292system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 79701.265997 # average WriteInvalidateReq miss latency 1293system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 79701.265997 # average WriteInvalidateReq miss latency 1294system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 20226.492471 # average UpgradeReq miss latency 1295system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 20226.492471 # average UpgradeReq miss latency 1296system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20262.343701 # average SCUpgradeReq miss latency 1297system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20262.343701 # average SCUpgradeReq miss latency 1298system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 288500 # average SCUpgradeFailReq miss latency 1299system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 288500 # average SCUpgradeFailReq miss latency 1300system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 44702.657471 # average ReadExReq miss latency 1301system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 44702.657471 # average ReadExReq miss latency 1302system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34658.489359 # average overall miss latency 1303system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 34139.010283 # average overall miss latency 1304system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 27432.805640 # average overall miss latency 1305system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36618.495379 # average overall miss latency 1306system.cpu0.l2cache.demand_avg_miss_latency::total 35214.995476 # average overall miss latency 1307system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34658.489359 # average overall miss latency 1308system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 34139.010283 # average overall miss latency 1309system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 27432.805640 # average overall miss latency 1310system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36618.495379 # average overall miss latency 1311system.cpu0.l2cache.overall_avg_miss_latency::total 35214.995476 # average overall miss latency 1312system.cpu0.l2cache.blocked_cycles::no_mshrs 289229 # number of cycles access was blocked 1313system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1314system.cpu0.l2cache.blocked::no_mshrs 8029 # number of cycles access was blocked 1315system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1316system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 36.023041 # average number of cycles each access was blocked 1317system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1318system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1319system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1320system.cpu0.l2cache.writebacks::writebacks 1673369 # number of writebacks 1321system.cpu0.l2cache.writebacks::total 1673369 # number of writebacks 1322system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 4 # number of ReadReq MSHR hits 1323system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 192 # number of ReadReq MSHR hits 1324system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 62618 # number of ReadReq MSHR hits 1325system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 25783 # number of ReadReq MSHR hits 1326system.cpu0.l2cache.ReadReq_mshr_hits::total 88597 # number of ReadReq MSHR hits 1327system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.data 467795 # number of WriteInvalidateReq MSHR hits 1328system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total 467795 # number of WriteInvalidateReq MSHR hits 1329system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 32791 # number of ReadExReq MSHR hits 1330system.cpu0.l2cache.ReadExReq_mshr_hits::total 32791 # number of ReadExReq MSHR hits 1331system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 4 # number of demand (read+write) MSHR hits 1332system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 192 # number of demand (read+write) MSHR hits 1333system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 62618 # number of demand (read+write) MSHR hits 1334system.cpu0.l2cache.demand_mshr_hits::cpu0.data 58574 # number of demand (read+write) MSHR hits 1335system.cpu0.l2cache.demand_mshr_hits::total 121388 # number of demand (read+write) MSHR hits 1336system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 4 # number of overall MSHR hits 1337system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 192 # number of overall MSHR hits 1338system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 62618 # number of overall MSHR hits 1339system.cpu0.l2cache.overall_mshr_hits::cpu0.data 58574 # number of overall MSHR hits 1340system.cpu0.l2cache.overall_mshr_hits::total 121388 # number of overall MSHR hits 1341system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 13857 # number of ReadReq MSHR misses 1342system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 9630 # number of ReadReq MSHR misses 1343system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 183817 # number of ReadReq MSHR misses 1344system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 1099262 # number of ReadReq MSHR misses 1345system.cpu0.l2cache.ReadReq_mshr_misses::total 1306566 # number of ReadReq MSHR misses 1346system.cpu0.l2cache.Writeback_mshr_misses::writebacks 7 # number of Writeback MSHR misses 1347system.cpu0.l2cache.Writeback_mshr_misses::total 7 # number of Writeback MSHR misses 1348system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 3442663 # number of HardPFReq MSHR misses 1349system.cpu0.l2cache.HardPFReq_mshr_misses::total 3442663 # number of HardPFReq MSHR misses 1350system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 102264 # number of WriteInvalidateReq MSHR misses 1351system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 102264 # number of WriteInvalidateReq MSHR misses 1352system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 122791 # number of UpgradeReq MSHR misses 1353system.cpu0.l2cache.UpgradeReq_mshr_misses::total 122791 # number of UpgradeReq MSHR misses 1354system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 145551 # number of SCUpgradeReq MSHR misses 1355system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 145551 # number of SCUpgradeReq MSHR misses 1356system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 7 # number of SCUpgradeFailReq MSHR misses 1357system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses 1358system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 221634 # number of ReadExReq MSHR misses 1359system.cpu0.l2cache.ReadExReq_mshr_misses::total 221634 # number of ReadExReq MSHR misses 1360system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 13857 # number of demand (read+write) MSHR misses 1361system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 9630 # number of demand (read+write) MSHR misses 1362system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 183817 # number of demand (read+write) MSHR misses 1363system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1320896 # number of demand (read+write) MSHR misses 1364system.cpu0.l2cache.demand_mshr_misses::total 1528200 # number of demand (read+write) MSHR misses 1365system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 13857 # number of overall MSHR misses 1366system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 9630 # number of overall MSHR misses 1367system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 183817 # number of overall MSHR misses 1368system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1320896 # number of overall MSHR misses 1369system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 3442663 # number of overall MSHR misses 1370system.cpu0.l2cache.overall_mshr_misses::total 4970863 # number of overall MSHR misses 1371system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 382774591 # number of ReadReq MSHR miss cycles 1372system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 260281521 # number of ReadReq MSHR miss cycles 1373system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 4356544455 # number of ReadReq MSHR miss cycles 1374system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 30386877543 # number of ReadReq MSHR miss cycles 1375system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 35386478110 # number of ReadReq MSHR miss cycles 1376system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 191389904056 # number of HardPFReq MSHR miss cycles 1377system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 191389904056 # number of HardPFReq MSHR miss cycles 1378system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 3325777104 # number of WriteInvalidateReq MSHR miss cycles 1379system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 3325777104 # number of WriteInvalidateReq MSHR miss cycles 1380system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2139983924 # number of UpgradeReq MSHR miss cycles 1381system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2139983924 # number of UpgradeReq MSHR miss cycles 1382system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2013011425 # number of SCUpgradeReq MSHR miss cycles 1383system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2013011425 # number of SCUpgradeReq MSHR miss cycles 1384system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1662500 # number of SCUpgradeFailReq MSHR miss cycles 1385system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1662500 # number of SCUpgradeFailReq MSHR miss cycles 1386system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 7397496985 # number of ReadExReq MSHR miss cycles 1387system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 7397496985 # number of ReadExReq MSHR miss cycles 1388system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 382774591 # number of demand (read+write) MSHR miss cycles 1389system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 260281521 # number of demand (read+write) MSHR miss cycles 1390system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 4356544455 # number of demand (read+write) MSHR miss cycles 1391system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 37784374528 # number of demand (read+write) MSHR miss cycles 1392system.cpu0.l2cache.demand_mshr_miss_latency::total 42783975095 # number of demand (read+write) MSHR miss cycles 1393system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 382774591 # number of overall MSHR miss cycles 1394system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 260281521 # number of overall MSHR miss cycles 1395system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 4356544455 # number of overall MSHR miss cycles 1396system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 37784374528 # number of overall MSHR miss cycles 1397system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 191389904056 # number of overall MSHR miss cycles 1398system.cpu0.l2cache.overall_mshr_miss_latency::total 234173879151 # number of overall MSHR miss cycles 1399system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1519173000 # number of ReadReq MSHR uncacheable cycles 1400system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5327096604 # number of ReadReq MSHR uncacheable cycles 1401system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6846269604 # number of ReadReq MSHR uncacheable cycles 1402system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5036994556 # number of WriteReq MSHR uncacheable cycles 1403system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5036994556 # number of WriteReq MSHR uncacheable cycles 1404system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1519173000 # number of overall MSHR uncacheable cycles 1405system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10364091160 # number of overall MSHR uncacheable cycles 1406system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11883264160 # number of overall MSHR uncacheable cycles 1407system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.025853 # mshr miss rate for ReadReq accesses 1408system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.054478 # mshr miss rate for ReadReq accesses 1409system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.030416 # mshr miss rate for ReadReq accesses 1410system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.278529 # mshr miss rate for ReadReq accesses 1411system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.122077 # mshr miss rate for ReadReq accesses 1412system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for Writeback accesses 1413system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000002 # mshr miss rate for Writeback accesses 1414system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1415system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1416system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.129074 # mshr miss rate for WriteInvalidateReq accesses 1417system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.129074 # mshr miss rate for WriteInvalidateReq accesses 1418system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.503091 # mshr miss rate for UpgradeReq accesses 1419system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.503091 # mshr miss rate for UpgradeReq accesses 1420system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.790514 # mshr miss rate for SCUpgradeReq accesses 1421system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.790514 # mshr miss rate for SCUpgradeReq accesses 1422system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1423system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1424system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.185504 # mshr miss rate for ReadExReq accesses 1425system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.185504 # mshr miss rate for ReadExReq accesses 1426system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.025853 # mshr miss rate for demand accesses 1427system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.054478 # mshr miss rate for demand accesses 1428system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.030416 # mshr miss rate for demand accesses 1429system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.256912 # mshr miss rate for demand accesses 1430system.cpu0.l2cache.demand_mshr_miss_rate::total 0.128447 # mshr miss rate for demand accesses 1431system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.025853 # mshr miss rate for overall accesses 1432system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.054478 # mshr miss rate for overall accesses 1433system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.030416 # mshr miss rate for overall accesses 1434system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.256912 # mshr miss rate for overall accesses 1435system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1436system.cpu0.l2cache.overall_mshr_miss_rate::total 0.417806 # mshr miss rate for overall accesses 1437system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27623.193404 # average ReadReq mshr miss latency 1438system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 27028.195327 # average ReadReq mshr miss latency 1439system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23700.443675 # average ReadReq mshr miss latency 1440system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 27642.980057 # average ReadReq mshr miss latency 1441system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27083.574890 # average ReadReq mshr miss latency 1442system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55593.563487 # average HardPFReq mshr miss latency 1443system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55593.563487 # average HardPFReq mshr miss latency 1444system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 32521.484628 # average WriteInvalidateReq mshr miss latency 1445system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32521.484628 # average WriteInvalidateReq mshr miss latency 1446system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17427.856472 # average UpgradeReq mshr miss latency 1447system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17427.856472 # average UpgradeReq mshr miss latency 1448system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13830.282341 # average SCUpgradeReq mshr miss latency 1449system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13830.282341 # average SCUpgradeReq mshr miss latency 1450system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 237500 # average SCUpgradeFailReq mshr miss latency 1451system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 237500 # average SCUpgradeFailReq mshr miss latency 1452system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 33377.085578 # average ReadExReq mshr miss latency 1453system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 33377.085578 # average ReadExReq mshr miss latency 1454system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27623.193404 # average overall mshr miss latency 1455system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 27028.195327 # average overall mshr miss latency 1456system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23700.443675 # average overall mshr miss latency 1457system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28605.109356 # average overall mshr miss latency 1458system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27996.319261 # average overall mshr miss latency 1459system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27623.193404 # average overall mshr miss latency 1460system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 27028.195327 # average overall mshr miss latency 1461system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23700.443675 # average overall mshr miss latency 1462system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28605.109356 # average overall mshr miss latency 1463system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55593.563487 # average overall mshr miss latency 1464system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 47109.300568 # average overall mshr miss latency 1465system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1466system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1467system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1468system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1469system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1470system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1471system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1472system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1473system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1474system.cpu0.toL2Bus.trans_dist::ReadReq 15173335 # Transaction distribution 1475system.cpu0.toL2Bus.trans_dist::ReadResp 11005084 # Transaction distribution 1476system.cpu0.toL2Bus.trans_dist::WriteReq 31316 # Transaction distribution 1477system.cpu0.toL2Bus.trans_dist::WriteResp 31316 # Transaction distribution 1478system.cpu0.toL2Bus.trans_dist::Writeback 3975122 # Transaction distribution 1479system.cpu0.toL2Bus.trans_dist::HardPFReq 5222365 # Transaction distribution 1480system.cpu0.toL2Bus.trans_dist::HardPFResp 14 # Transaction distribution 1481system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 963549 # Transaction distribution 1482system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 792291 # Transaction distribution 1483system.cpu0.toL2Bus.trans_dist::UpgradeReq 491639 # Transaction distribution 1484system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 333223 # Transaction distribution 1485system.cpu0.toL2Bus.trans_dist::UpgradeResp 494297 # Transaction distribution 1486system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 53 # Transaction distribution 1487system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution 1488system.cpu0.toL2Bus.trans_dist::ReadExReq 1332515 # Transaction distribution 1489system.cpu0.toL2Bus.trans_dist::ReadExResp 1202467 # Transaction distribution 1490system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 12129286 # Packet count per connected master and slave (bytes) 1491system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16997895 # Packet count per connected master and slave (bytes) 1492system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 390025 # Packet count per connected master and slave (bytes) 1493system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1185916 # Packet count per connected master and slave (bytes) 1494system.cpu0.toL2Bus.pkt_count::total 30703122 # Packet count per connected master and slave (bytes) 1495system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 387114336 # Cumulative packet size per connected master and slave (bytes) 1496system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 641181457 # Cumulative packet size per connected master and slave (bytes) 1497system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1414144 # Cumulative packet size per connected master and slave (bytes) 1498system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4287888 # Cumulative packet size per connected master and slave (bytes) 1499system.cpu0.toL2Bus.pkt_size::total 1033997825 # Cumulative packet size per connected master and slave (bytes) 1500system.cpu0.toL2Bus.snoops 10518238 # Total snoops (count) 1501system.cpu0.toL2Bus.snoop_fanout::samples 27441081 # Request fanout histogram 1502system.cpu0.toL2Bus.snoop_fanout::mean 5.371527 # Request fanout histogram 1503system.cpu0.toL2Bus.snoop_fanout::stdev 0.483213 # Request fanout histogram 1504system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1505system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1506system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1507system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1508system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1509system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1510system.cpu0.toL2Bus.snoop_fanout::5 17245975 62.85% 62.85% # Request fanout histogram 1511system.cpu0.toL2Bus.snoop_fanout::6 10195106 37.15% 100.00% # Request fanout histogram 1512system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1513system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1514system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1515system.cpu0.toL2Bus.snoop_fanout::total 27441081 # Request fanout histogram 1516system.cpu0.toL2Bus.reqLayer0.occupancy 13452656135 # Layer occupancy (ticks) 1517system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 1518system.cpu0.toL2Bus.snoopLayer0.occupancy 192867736 # Layer occupancy (ticks) 1519system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1520system.cpu0.toL2Bus.respLayer0.occupancy 9099601288 # Layer occupancy (ticks) 1521system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1522system.cpu0.toL2Bus.respLayer1.occupancy 8421572630 # Layer occupancy (ticks) 1523system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1524system.cpu0.toL2Bus.respLayer2.occupancy 213967447 # Layer occupancy (ticks) 1525system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1526system.cpu0.toL2Bus.respLayer3.occupancy 651243914 # Layer occupancy (ticks) 1527system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1528system.cpu1.branchPred.lookups 133961841 # Number of BP lookups 1529system.cpu1.branchPred.condPredicted 89061347 # Number of conditional branches predicted 1530system.cpu1.branchPred.condIncorrect 6618163 # Number of conditional branches incorrect 1531system.cpu1.branchPred.BTBLookups 94585757 # Number of BTB lookups 1532system.cpu1.branchPred.BTBHits 62217505 # Number of BTB hits 1533system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1534system.cpu1.branchPred.BTBHitPct 65.778936 # BTB Hit Percentage 1535system.cpu1.branchPred.usedRAS 18340774 # Number of times the RAS was used to get a target. 1536system.cpu1.branchPred.RASInCorrect 186545 # Number of incorrect RAS predictions. 1537system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1538system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1539system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1540system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1541system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1542system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1543system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1544system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1545system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1546system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1547system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1548system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1549system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1550system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1551system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1552system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1553system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1554system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1555system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1556system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1557system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1558system.cpu1.dtb.inst_hits 0 # ITB inst hits 1559system.cpu1.dtb.inst_misses 0 # ITB inst misses 1560system.cpu1.dtb.read_hits 98830623 # DTB read hits 1561system.cpu1.dtb.read_misses 443426 # DTB read misses 1562system.cpu1.dtb.write_hits 80619639 # DTB write hits 1563system.cpu1.dtb.write_misses 165440 # DTB write misses 1564system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1565system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1566system.cpu1.dtb.flush_tlb_mva_asid 44806 # Number of times TLB was flushed by MVA & ASID 1567system.cpu1.dtb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID 1568system.cpu1.dtb.flush_entries 44150 # Number of entries that have been flushed from TLB 1569system.cpu1.dtb.align_faults 612 # Number of TLB faults due to alignment restrictions 1570system.cpu1.dtb.prefetch_faults 6848 # Number of TLB faults due to prefetch 1571system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1572system.cpu1.dtb.perms_faults 42554 # Number of TLB faults due to permissions restrictions 1573system.cpu1.dtb.read_accesses 99274049 # DTB read accesses 1574system.cpu1.dtb.write_accesses 80785079 # DTB write accesses 1575system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1576system.cpu1.dtb.hits 179450262 # DTB hits 1577system.cpu1.dtb.misses 608866 # DTB misses 1578system.cpu1.dtb.accesses 180059128 # DTB accesses 1579system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1580system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1581system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1582system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1583system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1584system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1585system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1586system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1587system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1588system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1589system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1590system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1591system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1592system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1593system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1594system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1595system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1596system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1597system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1598system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1599system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1600system.cpu1.itb.inst_hits 211899162 # ITB inst hits 1601system.cpu1.itb.inst_misses 88988 # ITB inst misses 1602system.cpu1.itb.read_hits 0 # DTB read hits 1603system.cpu1.itb.read_misses 0 # DTB read misses 1604system.cpu1.itb.write_hits 0 # DTB write hits 1605system.cpu1.itb.write_misses 0 # DTB write misses 1606system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1607system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1608system.cpu1.itb.flush_tlb_mva_asid 44806 # Number of times TLB was flushed by MVA & ASID 1609system.cpu1.itb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID 1610system.cpu1.itb.flush_entries 32114 # Number of entries that have been flushed from TLB 1611system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1612system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1613system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1614system.cpu1.itb.perms_faults 230833 # Number of TLB faults due to permissions restrictions 1615system.cpu1.itb.read_accesses 0 # DTB read accesses 1616system.cpu1.itb.write_accesses 0 # DTB write accesses 1617system.cpu1.itb.inst_accesses 211988150 # ITB inst accesses 1618system.cpu1.itb.hits 211899162 # DTB hits 1619system.cpu1.itb.misses 88988 # DTB misses 1620system.cpu1.itb.accesses 211988150 # DTB accesses 1621system.cpu1.numCycles 705261968 # number of cpu cycles simulated 1622system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1623system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1624system.cpu1.fetch.icacheStallCycles 81258744 # Number of cycles fetch is stalled on an Icache miss 1625system.cpu1.fetch.Insts 595261780 # Number of instructions fetch has processed 1626system.cpu1.fetch.Branches 133961841 # Number of branches that fetch encountered 1627system.cpu1.fetch.predictedBranches 80558279 # Number of branches that fetch has predicted taken 1628system.cpu1.fetch.Cycles 597026773 # Number of cycles fetch has run and was not squashing or blocked 1629system.cpu1.fetch.SquashCycles 14270848 # Number of cycles fetch has spent squashing 1630system.cpu1.fetch.TlbCycles 1888771 # Number of cycles fetch has spent waiting for tlb 1631system.cpu1.fetch.MiscStallCycles 137791 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1632system.cpu1.fetch.PendingTrapStallCycles 6543938 # Number of stall cycles due to pending traps 1633system.cpu1.fetch.PendingQuiesceStallCycles 793820 # Number of stall cycles due to pending quiesce instructions 1634system.cpu1.fetch.IcacheWaitRetryStallCycles 311963 # Number of stall cycles due to full MSHR 1635system.cpu1.fetch.CacheLines 211646234 # Number of cache lines fetched 1636system.cpu1.fetch.IcacheSquashes 1619349 # Number of outstanding Icache misses that were squashed 1637system.cpu1.fetch.ItlbSquashes 28847 # Number of outstanding ITLB misses that were squashed 1638system.cpu1.fetch.rateDist::samples 695097224 # Number of instructions fetched each cycle (Total) 1639system.cpu1.fetch.rateDist::mean 1.005850 # Number of instructions fetched each cycle (Total) 1640system.cpu1.fetch.rateDist::stdev 1.225976 # Number of instructions fetched each cycle (Total) 1641system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1642system.cpu1.fetch.rateDist::0 360486788 51.86% 51.86% # Number of instructions fetched each cycle (Total) 1643system.cpu1.fetch.rateDist::1 129920524 18.69% 70.55% # Number of instructions fetched each cycle (Total) 1644system.cpu1.fetch.rateDist::2 44826389 6.45% 77.00% # Number of instructions fetched each cycle (Total) 1645system.cpu1.fetch.rateDist::3 159863523 23.00% 100.00% # Number of instructions fetched each cycle (Total) 1646system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1647system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1648system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 1649system.cpu1.fetch.rateDist::total 695097224 # Number of instructions fetched each cycle (Total) 1650system.cpu1.fetch.branchRate 0.189946 # Number of branch fetches per cycle 1651system.cpu1.fetch.rate 0.844029 # Number of inst fetches per cycle 1652system.cpu1.decode.IdleCycles 99752260 # Number of cycles decode is idle 1653system.cpu1.decode.BlockedCycles 332349824 # Number of cycles decode is blocked 1654system.cpu1.decode.RunCycles 219841712 # Number of cycles decode is running 1655system.cpu1.decode.UnblockCycles 38085588 # Number of cycles decode is unblocking 1656system.cpu1.decode.SquashCycles 5067840 # Number of cycles decode is squashing 1657system.cpu1.decode.BranchResolved 18995502 # Number of times decode resolved a branch 1658system.cpu1.decode.BranchMispred 2109796 # Number of times decode detected a branch misprediction 1659system.cpu1.decode.DecodedInsts 616514692 # Number of instructions handled by decode 1660system.cpu1.decode.SquashedInsts 22877728 # Number of squashed instructions handled by decode 1661system.cpu1.rename.SquashCycles 5067840 # Number of cycles rename is squashing 1662system.cpu1.rename.IdleCycles 135033848 # Number of cycles rename is idle 1663system.cpu1.rename.BlockCycles 48639647 # Number of cycles rename is blocking 1664system.cpu1.rename.serializeStallCycles 225189127 # count of cycles rename stalled for serializing inst 1665system.cpu1.rename.RunCycles 222148294 # Number of cycles rename is running 1666system.cpu1.rename.UnblockCycles 59018468 # Number of cycles rename is unblocking 1667system.cpu1.rename.RenamedInsts 599774214 # Number of instructions processed by rename 1668system.cpu1.rename.SquashedInsts 5804898 # Number of squashed instructions processed by rename 1669system.cpu1.rename.ROBFullEvents 8803158 # Number of times rename has blocked due to ROB full 1670system.cpu1.rename.IQFullEvents 361913 # Number of times rename has blocked due to IQ full 1671system.cpu1.rename.LQFullEvents 923044 # Number of times rename has blocked due to LQ full 1672system.cpu1.rename.SQFullEvents 23085631 # Number of times rename has blocked due to SQ full 1673system.cpu1.rename.FullRegisterEvents 14113 # Number of times there has been no free registers 1674system.cpu1.rename.RenamedOperands 571116000 # Number of destination operands rename has renamed 1675system.cpu1.rename.RenameLookups 927515458 # Number of register rename lookups that rename has made 1676system.cpu1.rename.int_rename_lookups 708750961 # Number of integer rename lookups 1677system.cpu1.rename.fp_rename_lookups 721490 # Number of floating rename lookups 1678system.cpu1.rename.CommittedMaps 514023695 # Number of HB maps that are committed 1679system.cpu1.rename.UndoneMaps 57092304 # Number of HB maps that are undone due to squashing 1680system.cpu1.rename.serializingInsts 16265387 # count of serializing insts renamed 1681system.cpu1.rename.tempSerializingInsts 14239236 # count of temporary serializing insts renamed 1682system.cpu1.rename.skidInsts 76589893 # count of insts added to the skid buffer 1683system.cpu1.memDep0.insertedLoads 99537313 # Number of loads inserted to the mem dependence unit. 1684system.cpu1.memDep0.insertedStores 83963206 # Number of stores inserted to the mem dependence unit. 1685system.cpu1.memDep0.conflictingLoads 9607701 # Number of conflicting loads. 1686system.cpu1.memDep0.conflictingStores 8257946 # Number of conflicting stores. 1687system.cpu1.iq.iqInstsAdded 576970515 # Number of instructions added to the IQ (excludes non-spec) 1688system.cpu1.iq.iqNonSpecInstsAdded 16478044 # Number of non-speculative instructions added to the IQ 1689system.cpu1.iq.iqInstsIssued 581773999 # Number of instructions issued 1690system.cpu1.iq.iqSquashedInstsIssued 2685793 # Number of squashed instructions issued 1691system.cpu1.iq.iqSquashedInstsExamined 50643585 # Number of squashed instructions iterated over during squash; mainly for profiling 1692system.cpu1.iq.iqSquashedOperandsExamined 34938077 # Number of squashed operands that are examined and possibly removed from graph 1693system.cpu1.iq.iqSquashedNonSpecRemoved 295595 # Number of squashed non-spec instructions that were removed 1694system.cpu1.iq.issued_per_cycle::samples 695097224 # Number of insts issued each cycle 1695system.cpu1.iq.issued_per_cycle::mean 0.836968 # Number of insts issued each cycle 1696system.cpu1.iq.issued_per_cycle::stdev 1.068825 # Number of insts issued each cycle 1697system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1698system.cpu1.iq.issued_per_cycle::0 375720628 54.05% 54.05% # Number of insts issued each cycle 1699system.cpu1.iq.issued_per_cycle::1 136500819 19.64% 73.69% # Number of insts issued each cycle 1700system.cpu1.iq.issued_per_cycle::2 111041420 15.97% 89.67% # Number of insts issued each cycle 1701system.cpu1.iq.issued_per_cycle::3 64151608 9.23% 98.89% # Number of insts issued each cycle 1702system.cpu1.iq.issued_per_cycle::4 7678235 1.10% 100.00% # Number of insts issued each cycle 1703system.cpu1.iq.issued_per_cycle::5 4508 0.00% 100.00% # Number of insts issued each cycle 1704system.cpu1.iq.issued_per_cycle::6 6 0.00% 100.00% # Number of insts issued each cycle 1705system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 1706system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 1707system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1708system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1709system.cpu1.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle 1710system.cpu1.iq.issued_per_cycle::total 695097224 # Number of insts issued each cycle 1711system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1712system.cpu1.iq.fu_full::IntAlu 58467261 44.14% 44.14% # attempts to use FU when none available 1713system.cpu1.iq.fu_full::IntMult 65736 0.05% 44.19% # attempts to use FU when none available 1714system.cpu1.iq.fu_full::IntDiv 8975 0.01% 44.19% # attempts to use FU when none available 1715system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.19% # attempts to use FU when none available 1716system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.19% # attempts to use FU when none available 1717system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.19% # attempts to use FU when none available 1718system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.19% # attempts to use FU when none available 1719system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.19% # attempts to use FU when none available 1720system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.19% # attempts to use FU when none available 1721system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.19% # attempts to use FU when none available 1722system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.19% # attempts to use FU when none available 1723system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.19% # attempts to use FU when none available 1724system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.19% # attempts to use FU when none available 1725system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.19% # attempts to use FU when none available 1726system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.19% # attempts to use FU when none available 1727system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.19% # attempts to use FU when none available 1728system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.19% # attempts to use FU when none available 1729system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.19% # attempts to use FU when none available 1730system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.19% # attempts to use FU when none available 1731system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.19% # attempts to use FU when none available 1732system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.19% # attempts to use FU when none available 1733system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.19% # attempts to use FU when none available 1734system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.19% # attempts to use FU when none available 1735system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.19% # attempts to use FU when none available 1736system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.19% # attempts to use FU when none available 1737system.cpu1.iq.fu_full::SimdFloatMisc 28 0.00% 44.19% # attempts to use FU when none available 1738system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.19% # attempts to use FU when none available 1739system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.19% # attempts to use FU when none available 1740system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.19% # attempts to use FU when none available 1741system.cpu1.iq.fu_full::MemRead 36077917 27.24% 71.43% # attempts to use FU when none available 1742system.cpu1.iq.fu_full::MemWrite 37847209 28.57% 100.00% # attempts to use FU when none available 1743system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1744system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1745system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 1746system.cpu1.iq.FU_type_0::IntAlu 396486231 68.15% 68.15% # Type of FU issued 1747system.cpu1.iq.FU_type_0::IntMult 1392625 0.24% 68.39% # Type of FU issued 1748system.cpu1.iq.FU_type_0::IntDiv 78812 0.01% 68.40% # Type of FU issued 1749system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.40% # Type of FU issued 1750system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.40% # Type of FU issued 1751system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.40% # Type of FU issued 1752system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.40% # Type of FU issued 1753system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.40% # Type of FU issued 1754system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.40% # Type of FU issued 1755system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.40% # Type of FU issued 1756system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.40% # Type of FU issued 1757system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.40% # Type of FU issued 1758system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.40% # Type of FU issued 1759system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.40% # Type of FU issued 1760system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.40% # Type of FU issued 1761system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.40% # Type of FU issued 1762system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.40% # Type of FU issued 1763system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.40% # Type of FU issued 1764system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.40% # Type of FU issued 1765system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.40% # Type of FU issued 1766system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.40% # Type of FU issued 1767system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.40% # Type of FU issued 1768system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.40% # Type of FU issued 1769system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.40% # Type of FU issued 1770system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.40% # Type of FU issued 1771system.cpu1.iq.FU_type_0::SimdFloatMisc 42928 0.01% 68.41% # Type of FU issued 1772system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.41% # Type of FU issued 1773system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.41% # Type of FU issued 1774system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.41% # Type of FU issued 1775system.cpu1.iq.FU_type_0::MemRead 101899765 17.52% 85.93% # Type of FU issued 1776system.cpu1.iq.FU_type_0::MemWrite 81873638 14.07% 100.00% # Type of FU issued 1777system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1778system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1779system.cpu1.iq.FU_type_0::total 581773999 # Type of FU issued 1780system.cpu1.iq.rate 0.824905 # Inst issue rate 1781system.cpu1.iq.fu_busy_cnt 132467126 # FU busy when requested 1782system.cpu1.iq.fu_busy_rate 0.227695 # FU busy rate (busy events/executed inst) 1783system.cpu1.iq.int_inst_queue_reads 1992741902 # Number of integer instruction queue reads 1784system.cpu1.iq.int_inst_queue_writes 643831652 # Number of integer instruction queue writes 1785system.cpu1.iq.int_inst_queue_wakeup_accesses 565540483 # Number of integer instruction queue wakeup accesses 1786system.cpu1.iq.fp_inst_queue_reads 1056239 # Number of floating instruction queue reads 1787system.cpu1.iq.fp_inst_queue_writes 418449 # Number of floating instruction queue writes 1788system.cpu1.iq.fp_inst_queue_wakeup_accesses 388115 # Number of floating instruction queue wakeup accesses 1789system.cpu1.iq.int_alu_accesses 713583395 # Number of integer alu accesses 1790system.cpu1.iq.fp_alu_accesses 657730 # Number of floating point alu accesses 1791system.cpu1.iew.lsq.thread0.forwLoads 2682619 # Number of loads that had data forwarded from stores 1792system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1793system.cpu1.iew.lsq.thread0.squashedLoads 12570649 # Number of loads squashed 1794system.cpu1.iew.lsq.thread0.ignoredResponses 16823 # Number of memory responses ignored because the instruction is squashed 1795system.cpu1.iew.lsq.thread0.memOrderViolation 158978 # Number of memory ordering violations 1796system.cpu1.iew.lsq.thread0.squashedStores 5834378 # Number of stores squashed 1797system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1798system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1799system.cpu1.iew.lsq.thread0.rescheduledLoads 2724944 # Number of loads that were rescheduled 1800system.cpu1.iew.lsq.thread0.cacheBlocked 3729174 # Number of times an access to memory failed due to the cache being blocked 1801system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1802system.cpu1.iew.iewSquashCycles 5067840 # Number of cycles IEW is squashing 1803system.cpu1.iew.iewBlockCycles 8144414 # Number of cycles IEW is blocking 1804system.cpu1.iew.iewUnblockCycles 2028582 # Number of cycles IEW is unblocking 1805system.cpu1.iew.iewDispatchedInsts 593577386 # Number of instructions dispatched to IQ 1806system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 1807system.cpu1.iew.iewDispLoadInsts 99537313 # Number of dispatched load instructions 1808system.cpu1.iew.iewDispStoreInsts 83963206 # Number of dispatched store instructions 1809system.cpu1.iew.iewDispNonSpecInsts 14010879 # Number of dispatched non-speculative instructions 1810system.cpu1.iew.iewIQFullEvents 57965 # Number of times the IQ has become full, causing a stall 1811system.cpu1.iew.iewLSQFullEvents 1901764 # Number of times the LSQ has become full, causing a stall 1812system.cpu1.iew.memOrderViolationEvents 158978 # Number of memory order violations 1813system.cpu1.iew.predictedTakenIncorrect 2040667 # Number of branches that were predicted taken incorrectly 1814system.cpu1.iew.predictedNotTakenIncorrect 2820650 # Number of branches that were predicted not taken incorrectly 1815system.cpu1.iew.branchMispredicts 4861317 # Number of branch mispredicts detected at execute 1816system.cpu1.iew.iewExecutedInsts 574179310 # Number of executed instructions 1817system.cpu1.iew.iewExecLoadInsts 98827451 # Number of load instructions executed 1818system.cpu1.iew.iewExecSquashedInsts 6993764 # Number of squashed instructions skipped in execute 1819system.cpu1.iew.exec_swp 0 # number of swp insts executed 1820system.cpu1.iew.exec_nop 128827 # number of nop insts executed 1821system.cpu1.iew.exec_refs 179445358 # number of memory reference insts executed 1822system.cpu1.iew.exec_branches 107524158 # Number of branches executed 1823system.cpu1.iew.exec_stores 80617907 # Number of stores executed 1824system.cpu1.iew.exec_rate 0.814136 # Inst execution rate 1825system.cpu1.iew.wb_sent 566651750 # cumulative count of insts sent to commit 1826system.cpu1.iew.wb_count 565928598 # cumulative count of insts written-back 1827system.cpu1.iew.wb_producers 274900610 # num instructions producing a value 1828system.cpu1.iew.wb_consumers 450009146 # num instructions consuming a value 1829system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1830system.cpu1.iew.wb_rate 0.802437 # insts written-back per cycle 1831system.cpu1.iew.wb_fanout 0.610878 # average fanout of values written-back 1832system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1833system.cpu1.commit.commitSquashedInsts 47337627 # The number of squashed insts skipped by commit 1834system.cpu1.commit.commitNonSpecStalls 16182449 # The number of times commit has been forced to stall to communicate backwards 1835system.cpu1.commit.branchMispredicts 4550579 # The number of times a branch was mispredicted 1836system.cpu1.commit.committed_per_cycle::samples 686146419 # Number of insts commited each cycle 1837system.cpu1.commit.committed_per_cycle::mean 0.786229 # Number of insts commited each cycle 1838system.cpu1.commit.committed_per_cycle::stdev 1.582193 # Number of insts commited each cycle 1839system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1840system.cpu1.commit.committed_per_cycle::0 448874592 65.42% 65.42% # Number of insts commited each cycle 1841system.cpu1.commit.committed_per_cycle::1 124520992 18.15% 83.57% # Number of insts commited each cycle 1842system.cpu1.commit.committed_per_cycle::2 51724584 7.54% 91.11% # Number of insts commited each cycle 1843system.cpu1.commit.committed_per_cycle::3 17115210 2.49% 93.60% # Number of insts commited each cycle 1844system.cpu1.commit.committed_per_cycle::4 12441515 1.81% 95.41% # Number of insts commited each cycle 1845system.cpu1.commit.committed_per_cycle::5 8692682 1.27% 96.68% # Number of insts commited each cycle 1846system.cpu1.commit.committed_per_cycle::6 5812900 0.85% 97.53% # Number of insts commited each cycle 1847system.cpu1.commit.committed_per_cycle::7 3666336 0.53% 98.06% # Number of insts commited each cycle 1848system.cpu1.commit.committed_per_cycle::8 13297608 1.94% 100.00% # Number of insts commited each cycle 1849system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1850system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1851system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1852system.cpu1.commit.committed_per_cycle::total 686146419 # Number of insts commited each cycle 1853system.cpu1.commit.committedInsts 458333534 # Number of instructions committed 1854system.cpu1.commit.committedOps 539467876 # Number of ops (including micro ops) committed 1855system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1856system.cpu1.commit.refs 165095491 # Number of memory references committed 1857system.cpu1.commit.loads 86966664 # Number of loads committed 1858system.cpu1.commit.membars 3858042 # Number of memory barriers committed 1859system.cpu1.commit.branches 101991370 # Number of branches committed 1860system.cpu1.commit.fp_insts 379596 # Number of committed floating point instructions. 1861system.cpu1.commit.int_insts 495494093 # Number of committed integer instructions. 1862system.cpu1.commit.function_calls 13607824 # Number of function calls committed. 1863system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 1864system.cpu1.commit.op_class_0::IntAlu 373132612 69.17% 69.17% # Class of committed instruction 1865system.cpu1.commit.op_class_0::IntMult 1140635 0.21% 69.38% # Class of committed instruction 1866system.cpu1.commit.op_class_0::IntDiv 62088 0.01% 69.39% # Class of committed instruction 1867system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.39% # Class of committed instruction 1868system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.39% # Class of committed instruction 1869system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.39% # Class of committed instruction 1870system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.39% # Class of committed instruction 1871system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.39% # Class of committed instruction 1872system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.39% # Class of committed instruction 1873system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.39% # Class of committed instruction 1874system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.39% # Class of committed instruction 1875system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.39% # Class of committed instruction 1876system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.39% # Class of committed instruction 1877system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.39% # Class of committed instruction 1878system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.39% # Class of committed instruction 1879system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.39% # Class of committed instruction 1880system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.39% # Class of committed instruction 1881system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.39% # Class of committed instruction 1882system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.39% # Class of committed instruction 1883system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.39% # Class of committed instruction 1884system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.39% # Class of committed instruction 1885system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.39% # Class of committed instruction 1886system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.39% # Class of committed instruction 1887system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.39% # Class of committed instruction 1888system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.39% # Class of committed instruction 1889system.cpu1.commit.op_class_0::SimdFloatMisc 37050 0.01% 69.40% # Class of committed instruction 1890system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.40% # Class of committed instruction 1891system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.40% # Class of committed instruction 1892system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.40% # Class of committed instruction 1893system.cpu1.commit.op_class_0::MemRead 86966664 16.12% 85.52% # Class of committed instruction 1894system.cpu1.commit.op_class_0::MemWrite 78128827 14.48% 100.00% # Class of committed instruction 1895system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1896system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1897system.cpu1.commit.op_class_0::total 539467876 # Class of committed instruction 1898system.cpu1.commit.bw_lim_events 13297608 # number cycles where commit BW limit reached 1899system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 1900system.cpu1.rob.rob_reads 1255653176 # The number of ROB reads 1901system.cpu1.rob.rob_writes 1182522736 # The number of ROB writes 1902system.cpu1.timesIdled 784634 # Number of times that the entire CPU went into an idle state and unscheduled itself 1903system.cpu1.idleCycles 10164744 # Total number of cycles that the CPU has spent unscheduled due to idling 1904system.cpu1.quiesceCycles 94139293558 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1905system.cpu1.committedInsts 458333534 # Number of Instructions Simulated 1906system.cpu1.committedOps 539467876 # Number of Ops (including micro ops) Simulated 1907system.cpu1.cpi 1.538753 # CPI: Cycles Per Instruction 1908system.cpu1.cpi_total 1.538753 # CPI: Total CPI of All Threads 1909system.cpu1.ipc 0.649877 # IPC: Instructions Per Cycle 1910system.cpu1.ipc_total 0.649877 # IPC: Total IPC of All Threads 1911system.cpu1.int_regfile_reads 678371688 # number of integer regfile reads 1912system.cpu1.int_regfile_writes 402814905 # number of integer regfile writes 1913system.cpu1.fp_regfile_reads 627803 # number of floating regfile reads 1914system.cpu1.fp_regfile_writes 323588 # number of floating regfile writes 1915system.cpu1.cc_regfile_reads 123299886 # number of cc regfile reads 1916system.cpu1.cc_regfile_writes 123979632 # number of cc regfile writes 1917system.cpu1.misc_regfile_reads 2817640596 # number of misc regfile reads 1918system.cpu1.misc_regfile_writes 16155257 # number of misc regfile writes 1919system.cpu1.dcache.tags.replacements 5719154 # number of replacements 1920system.cpu1.dcache.tags.tagsinuse 428.720007 # Cycle average of tags in use 1921system.cpu1.dcache.tags.total_refs 153241322 # Total number of references to valid blocks. 1922system.cpu1.dcache.tags.sampled_refs 5719665 # Sample count of references to valid blocks. 1923system.cpu1.dcache.tags.avg_refs 26.792010 # Average number of references to valid blocks. 1924system.cpu1.dcache.tags.warmup_cycle 8515430590500 # Cycle when the warmup percentage was hit. 1925system.cpu1.dcache.tags.occ_blocks::cpu1.data 428.720007 # Average occupied blocks per requestor 1926system.cpu1.dcache.tags.occ_percent::cpu1.data 0.837344 # Average percentage of cache occupancy 1927system.cpu1.dcache.tags.occ_percent::total 0.837344 # Average percentage of cache occupancy 1928system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 1929system.cpu1.dcache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id 1930system.cpu1.dcache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id 1931system.cpu1.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id 1932system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 1933system.cpu1.dcache.tags.tag_accesses 342874086 # Number of tag accesses 1934system.cpu1.dcache.tags.data_accesses 342874086 # Number of data accesses 1935system.cpu1.dcache.ReadReq_hits::cpu1.data 80584085 # number of ReadReq hits 1936system.cpu1.dcache.ReadReq_hits::total 80584085 # number of ReadReq hits 1937system.cpu1.dcache.WriteReq_hits::cpu1.data 68058878 # number of WriteReq hits 1938system.cpu1.dcache.WriteReq_hits::total 68058878 # number of WriteReq hits 1939system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187635 # number of SoftPFReq hits 1940system.cpu1.dcache.SoftPFReq_hits::total 187635 # number of SoftPFReq hits 1941system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 112453 # number of WriteInvalidateReq hits 1942system.cpu1.dcache.WriteInvalidateReq_hits::total 112453 # number of WriteInvalidateReq hits 1943system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1764554 # number of LoadLockedReq hits 1944system.cpu1.dcache.LoadLockedReq_hits::total 1764554 # number of LoadLockedReq hits 1945system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1816897 # number of StoreCondReq hits 1946system.cpu1.dcache.StoreCondReq_hits::total 1816897 # number of StoreCondReq hits 1947system.cpu1.dcache.demand_hits::cpu1.data 148642963 # number of demand (read+write) hits 1948system.cpu1.dcache.demand_hits::total 148642963 # number of demand (read+write) hits 1949system.cpu1.dcache.overall_hits::cpu1.data 148830598 # number of overall hits 1950system.cpu1.dcache.overall_hits::total 148830598 # number of overall hits 1951system.cpu1.dcache.ReadReq_misses::cpu1.data 6869643 # number of ReadReq misses 1952system.cpu1.dcache.ReadReq_misses::total 6869643 # number of ReadReq misses 1953system.cpu1.dcache.WriteReq_misses::cpu1.data 7494314 # number of WriteReq misses 1954system.cpu1.dcache.WriteReq_misses::total 7494314 # number of WriteReq misses 1955system.cpu1.dcache.SoftPFReq_misses::cpu1.data 706318 # number of SoftPFReq misses 1956system.cpu1.dcache.SoftPFReq_misses::total 706318 # number of SoftPFReq misses 1957system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 458418 # number of WriteInvalidateReq misses 1958system.cpu1.dcache.WriteInvalidateReq_misses::total 458418 # number of WriteInvalidateReq misses 1959system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 288948 # number of LoadLockedReq misses 1960system.cpu1.dcache.LoadLockedReq_misses::total 288948 # number of LoadLockedReq misses 1961system.cpu1.dcache.StoreCondReq_misses::cpu1.data 190861 # number of StoreCondReq misses 1962system.cpu1.dcache.StoreCondReq_misses::total 190861 # number of StoreCondReq misses 1963system.cpu1.dcache.demand_misses::cpu1.data 14363957 # number of demand (read+write) misses 1964system.cpu1.dcache.demand_misses::total 14363957 # number of demand (read+write) misses 1965system.cpu1.dcache.overall_misses::cpu1.data 15070275 # number of overall misses 1966system.cpu1.dcache.overall_misses::total 15070275 # number of overall misses 1967system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 105402463849 # number of ReadReq miss cycles 1968system.cpu1.dcache.ReadReq_miss_latency::total 105402463849 # number of ReadReq miss cycles 1969system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 121649241613 # number of WriteReq miss cycles 1970system.cpu1.dcache.WriteReq_miss_latency::total 121649241613 # number of WriteReq miss cycles 1971system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 17403154350 # number of WriteInvalidateReq miss cycles 1972system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 17403154350 # number of WriteInvalidateReq miss cycles 1973system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 4078869410 # number of LoadLockedReq miss cycles 1974system.cpu1.dcache.LoadLockedReq_miss_latency::total 4078869410 # number of LoadLockedReq miss cycles 1975system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3937390159 # number of StoreCondReq miss cycles 1976system.cpu1.dcache.StoreCondReq_miss_latency::total 3937390159 # number of StoreCondReq miss cycles 1977system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1956500 # number of StoreCondFailReq miss cycles 1978system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1956500 # number of StoreCondFailReq miss cycles 1979system.cpu1.dcache.demand_miss_latency::cpu1.data 227051705462 # number of demand (read+write) miss cycles 1980system.cpu1.dcache.demand_miss_latency::total 227051705462 # number of demand (read+write) miss cycles 1981system.cpu1.dcache.overall_miss_latency::cpu1.data 227051705462 # number of overall miss cycles 1982system.cpu1.dcache.overall_miss_latency::total 227051705462 # number of overall miss cycles 1983system.cpu1.dcache.ReadReq_accesses::cpu1.data 87453728 # number of ReadReq accesses(hits+misses) 1984system.cpu1.dcache.ReadReq_accesses::total 87453728 # number of ReadReq accesses(hits+misses) 1985system.cpu1.dcache.WriteReq_accesses::cpu1.data 75553192 # number of WriteReq accesses(hits+misses) 1986system.cpu1.dcache.WriteReq_accesses::total 75553192 # number of WriteReq accesses(hits+misses) 1987system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 893953 # number of SoftPFReq accesses(hits+misses) 1988system.cpu1.dcache.SoftPFReq_accesses::total 893953 # number of SoftPFReq accesses(hits+misses) 1989system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 570871 # number of WriteInvalidateReq accesses(hits+misses) 1990system.cpu1.dcache.WriteInvalidateReq_accesses::total 570871 # number of WriteInvalidateReq accesses(hits+misses) 1991system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2053502 # number of LoadLockedReq accesses(hits+misses) 1992system.cpu1.dcache.LoadLockedReq_accesses::total 2053502 # number of LoadLockedReq accesses(hits+misses) 1993system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2007758 # number of StoreCondReq accesses(hits+misses) 1994system.cpu1.dcache.StoreCondReq_accesses::total 2007758 # number of StoreCondReq accesses(hits+misses) 1995system.cpu1.dcache.demand_accesses::cpu1.data 163006920 # number of demand (read+write) accesses 1996system.cpu1.dcache.demand_accesses::total 163006920 # number of demand (read+write) accesses 1997system.cpu1.dcache.overall_accesses::cpu1.data 163900873 # number of overall (read+write) accesses 1998system.cpu1.dcache.overall_accesses::total 163900873 # number of overall (read+write) accesses 1999system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.078552 # miss rate for ReadReq accesses 2000system.cpu1.dcache.ReadReq_miss_rate::total 0.078552 # miss rate for ReadReq accesses 2001system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.099193 # miss rate for WriteReq accesses 2002system.cpu1.dcache.WriteReq_miss_rate::total 0.099193 # miss rate for WriteReq accesses 2003system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.790106 # miss rate for SoftPFReq accesses 2004system.cpu1.dcache.SoftPFReq_miss_rate::total 0.790106 # miss rate for SoftPFReq accesses 2005system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.803015 # miss rate for WriteInvalidateReq accesses 2006system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.803015 # miss rate for WriteInvalidateReq accesses 2007system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.140710 # miss rate for LoadLockedReq accesses 2008system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.140710 # miss rate for LoadLockedReq accesses 2009system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.095062 # miss rate for StoreCondReq accesses 2010system.cpu1.dcache.StoreCondReq_miss_rate::total 0.095062 # miss rate for StoreCondReq accesses 2011system.cpu1.dcache.demand_miss_rate::cpu1.data 0.088119 # miss rate for demand accesses 2012system.cpu1.dcache.demand_miss_rate::total 0.088119 # miss rate for demand accesses 2013system.cpu1.dcache.overall_miss_rate::cpu1.data 0.091947 # miss rate for overall accesses 2014system.cpu1.dcache.overall_miss_rate::total 0.091947 # miss rate for overall accesses 2015system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15343.222908 # average ReadReq miss latency 2016system.cpu1.dcache.ReadReq_avg_miss_latency::total 15343.222908 # average ReadReq miss latency 2017system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16232.205057 # average WriteReq miss latency 2018system.cpu1.dcache.WriteReq_avg_miss_latency::total 16232.205057 # average WriteReq miss latency 2019system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 37963.505687 # average WriteInvalidateReq miss latency 2020system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 37963.505687 # average WriteInvalidateReq miss latency 2021system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14116.274935 # average LoadLockedReq miss latency 2022system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14116.274935 # average LoadLockedReq miss latency 2023system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20629.621342 # average StoreCondReq miss latency 2024system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20629.621342 # average StoreCondReq miss latency 2025system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 2026system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 2027system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15807.044358 # average overall miss latency 2028system.cpu1.dcache.demand_avg_miss_latency::total 15807.044358 # average overall miss latency 2029system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15066.195239 # average overall miss latency 2030system.cpu1.dcache.overall_avg_miss_latency::total 15066.195239 # average overall miss latency 2031system.cpu1.dcache.blocked_cycles::no_mshrs 4622048 # number of cycles access was blocked 2032system.cpu1.dcache.blocked_cycles::no_targets 18188306 # number of cycles access was blocked 2033system.cpu1.dcache.blocked::no_mshrs 368036 # number of cycles access was blocked 2034system.cpu1.dcache.blocked::no_targets 754235 # number of cycles access was blocked 2035system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12.558684 # average number of cycles each access was blocked 2036system.cpu1.dcache.avg_blocked_cycles::no_targets 24.114906 # average number of cycles each access was blocked 2037system.cpu1.dcache.fast_writes 0 # number of fast writes performed 2038system.cpu1.dcache.cache_copies 0 # number of cache copies performed 2039system.cpu1.dcache.writebacks::writebacks 3658567 # number of writebacks 2040system.cpu1.dcache.writebacks::total 3658567 # number of writebacks 2041system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3579229 # number of ReadReq MSHR hits 2042system.cpu1.dcache.ReadReq_mshr_hits::total 3579229 # number of ReadReq MSHR hits 2043system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 6058526 # number of WriteReq MSHR hits 2044system.cpu1.dcache.WriteReq_mshr_hits::total 6058526 # number of WriteReq MSHR hits 2045system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 3270 # number of WriteInvalidateReq MSHR hits 2046system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 3270 # number of WriteInvalidateReq MSHR hits 2047system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 146042 # number of LoadLockedReq MSHR hits 2048system.cpu1.dcache.LoadLockedReq_mshr_hits::total 146042 # number of LoadLockedReq MSHR hits 2049system.cpu1.dcache.demand_mshr_hits::cpu1.data 9637755 # number of demand (read+write) MSHR hits 2050system.cpu1.dcache.demand_mshr_hits::total 9637755 # number of demand (read+write) MSHR hits 2051system.cpu1.dcache.overall_mshr_hits::cpu1.data 9637755 # number of overall MSHR hits 2052system.cpu1.dcache.overall_mshr_hits::total 9637755 # number of overall MSHR hits 2053system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3290414 # number of ReadReq MSHR misses 2054system.cpu1.dcache.ReadReq_mshr_misses::total 3290414 # number of ReadReq MSHR misses 2055system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1435788 # number of WriteReq MSHR misses 2056system.cpu1.dcache.WriteReq_mshr_misses::total 1435788 # number of WriteReq MSHR misses 2057system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 706224 # number of SoftPFReq MSHR misses 2058system.cpu1.dcache.SoftPFReq_mshr_misses::total 706224 # number of SoftPFReq MSHR misses 2059system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 455148 # number of WriteInvalidateReq MSHR misses 2060system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 455148 # number of WriteInvalidateReq MSHR misses 2061system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 142906 # number of LoadLockedReq MSHR misses 2062system.cpu1.dcache.LoadLockedReq_mshr_misses::total 142906 # number of LoadLockedReq MSHR misses 2063system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 190858 # number of StoreCondReq MSHR misses 2064system.cpu1.dcache.StoreCondReq_mshr_misses::total 190858 # number of StoreCondReq MSHR misses 2065system.cpu1.dcache.demand_mshr_misses::cpu1.data 4726202 # number of demand (read+write) MSHR misses 2066system.cpu1.dcache.demand_mshr_misses::total 4726202 # number of demand (read+write) MSHR misses 2067system.cpu1.dcache.overall_mshr_misses::cpu1.data 5432426 # number of overall MSHR misses 2068system.cpu1.dcache.overall_mshr_misses::total 5432426 # number of overall MSHR misses 2069system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 44800014998 # number of ReadReq MSHR miss cycles 2070system.cpu1.dcache.ReadReq_mshr_miss_latency::total 44800014998 # number of ReadReq MSHR miss cycles 2071system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23381887855 # number of WriteReq MSHR miss cycles 2072system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23381887855 # number of WriteReq MSHR miss cycles 2073system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 16359112476 # number of SoftPFReq MSHR miss cycles 2074system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 16359112476 # number of SoftPFReq MSHR miss cycles 2075system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 16414544257 # number of WriteInvalidateReq MSHR miss cycles 2076system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 16414544257 # number of WriteInvalidateReq MSHR miss cycles 2077system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1722097666 # number of LoadLockedReq MSHR miss cycles 2078system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1722097666 # number of LoadLockedReq MSHR miss cycles 2079system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3546227841 # number of StoreCondReq MSHR miss cycles 2080system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3546227841 # number of StoreCondReq MSHR miss cycles 2081system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1864500 # number of StoreCondFailReq MSHR miss cycles 2082system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1864500 # number of StoreCondFailReq MSHR miss cycles 2083system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 68181902853 # number of demand (read+write) MSHR miss cycles 2084system.cpu1.dcache.demand_mshr_miss_latency::total 68181902853 # number of demand (read+write) MSHR miss cycles 2085system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 84541015329 # number of overall MSHR miss cycles 2086system.cpu1.dcache.overall_mshr_miss_latency::total 84541015329 # number of overall MSHR miss cycles 2087system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 790979694 # number of ReadReq MSHR uncacheable cycles 2088system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 790979694 # number of ReadReq MSHR uncacheable cycles 2089system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 944680456 # number of WriteReq MSHR uncacheable cycles 2090system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 944680456 # number of WriteReq MSHR uncacheable cycles 2091system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1735660150 # number of overall MSHR uncacheable cycles 2092system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1735660150 # number of overall MSHR uncacheable cycles 2093system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037625 # mshr miss rate for ReadReq accesses 2094system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037625 # mshr miss rate for ReadReq accesses 2095system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019004 # mshr miss rate for WriteReq accesses 2096system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019004 # mshr miss rate for WriteReq accesses 2097system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.790001 # mshr miss rate for SoftPFReq accesses 2098system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.790001 # mshr miss rate for SoftPFReq accesses 2099system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.797287 # mshr miss rate for WriteInvalidateReq accesses 2100system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.797287 # mshr miss rate for WriteInvalidateReq accesses 2101system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.069591 # mshr miss rate for LoadLockedReq accesses 2102system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.069591 # mshr miss rate for LoadLockedReq accesses 2103system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.095060 # mshr miss rate for StoreCondReq accesses 2104system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.095060 # mshr miss rate for StoreCondReq accesses 2105system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028994 # mshr miss rate for demand accesses 2106system.cpu1.dcache.demand_mshr_miss_rate::total 0.028994 # mshr miss rate for demand accesses 2107system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033145 # mshr miss rate for overall accesses 2108system.cpu1.dcache.overall_mshr_miss_rate::total 0.033145 # mshr miss rate for overall accesses 2109system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13615.312541 # average ReadReq mshr miss latency 2110system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13615.312541 # average ReadReq mshr miss latency 2111system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16285.055910 # average WriteReq mshr miss latency 2112system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16285.055910 # average WriteReq mshr miss latency 2113system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23164.197869 # average SoftPFReq mshr miss latency 2114system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23164.197869 # average SoftPFReq mshr miss latency 2115system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 36064.190674 # average WriteInvalidateReq mshr miss latency 2116system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 36064.190674 # average WriteInvalidateReq mshr miss latency 2117system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12050.562370 # average LoadLockedReq mshr miss latency 2118system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12050.562370 # average LoadLockedReq mshr miss latency 2119system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 18580.451650 # average StoreCondReq mshr miss latency 2120system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18580.451650 # average StoreCondReq mshr miss latency 2121system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2122system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 2123system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14426.362405 # average overall mshr miss latency 2124system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14426.362405 # average overall mshr miss latency 2125system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15562.294881 # average overall mshr miss latency 2126system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15562.294881 # average overall mshr miss latency 2127system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2128system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2129system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2130system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2131system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2132system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2133system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2134system.cpu1.icache.tags.replacements 5881686 # number of replacements 2135system.cpu1.icache.tags.tagsinuse 501.904324 # Cycle average of tags in use 2136system.cpu1.icache.tags.total_refs 205507195 # Total number of references to valid blocks. 2137system.cpu1.icache.tags.sampled_refs 5882198 # Sample count of references to valid blocks. 2138system.cpu1.icache.tags.avg_refs 34.937143 # Average number of references to valid blocks. 2139system.cpu1.icache.tags.warmup_cycle 8555135625500 # Cycle when the warmup percentage was hit. 2140system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.904324 # Average occupied blocks per requestor 2141system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980282 # Average percentage of cache occupancy 2142system.cpu1.icache.tags.occ_percent::total 0.980282 # Average percentage of cache occupancy 2143system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2144system.cpu1.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id 2145system.cpu1.icache.tags.age_task_id_blocks_1024::1 371 # Occupied blocks per task id 2146system.cpu1.icache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id 2147system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2148system.cpu1.icache.tags.tag_accesses 429168724 # Number of tag accesses 2149system.cpu1.icache.tags.data_accesses 429168724 # Number of data accesses 2150system.cpu1.icache.ReadReq_hits::cpu1.inst 205507195 # number of ReadReq hits 2151system.cpu1.icache.ReadReq_hits::total 205507195 # number of ReadReq hits 2152system.cpu1.icache.demand_hits::cpu1.inst 205507195 # number of demand (read+write) hits 2153system.cpu1.icache.demand_hits::total 205507195 # number of demand (read+write) hits 2154system.cpu1.icache.overall_hits::cpu1.inst 205507195 # number of overall hits 2155system.cpu1.icache.overall_hits::total 205507195 # number of overall hits 2156system.cpu1.icache.ReadReq_misses::cpu1.inst 6136058 # number of ReadReq misses 2157system.cpu1.icache.ReadReq_misses::total 6136058 # number of ReadReq misses 2158system.cpu1.icache.demand_misses::cpu1.inst 6136058 # number of demand (read+write) misses 2159system.cpu1.icache.demand_misses::total 6136058 # number of demand (read+write) misses 2160system.cpu1.icache.overall_misses::cpu1.inst 6136058 # number of overall misses 2161system.cpu1.icache.overall_misses::total 6136058 # number of overall misses 2162system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 53889413624 # number of ReadReq miss cycles 2163system.cpu1.icache.ReadReq_miss_latency::total 53889413624 # number of ReadReq miss cycles 2164system.cpu1.icache.demand_miss_latency::cpu1.inst 53889413624 # number of demand (read+write) miss cycles 2165system.cpu1.icache.demand_miss_latency::total 53889413624 # number of demand (read+write) miss cycles 2166system.cpu1.icache.overall_miss_latency::cpu1.inst 53889413624 # number of overall miss cycles 2167system.cpu1.icache.overall_miss_latency::total 53889413624 # number of overall miss cycles 2168system.cpu1.icache.ReadReq_accesses::cpu1.inst 211643253 # number of ReadReq accesses(hits+misses) 2169system.cpu1.icache.ReadReq_accesses::total 211643253 # number of ReadReq accesses(hits+misses) 2170system.cpu1.icache.demand_accesses::cpu1.inst 211643253 # number of demand (read+write) accesses 2171system.cpu1.icache.demand_accesses::total 211643253 # number of demand (read+write) accesses 2172system.cpu1.icache.overall_accesses::cpu1.inst 211643253 # number of overall (read+write) accesses 2173system.cpu1.icache.overall_accesses::total 211643253 # number of overall (read+write) accesses 2174system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.028992 # miss rate for ReadReq accesses 2175system.cpu1.icache.ReadReq_miss_rate::total 0.028992 # miss rate for ReadReq accesses 2176system.cpu1.icache.demand_miss_rate::cpu1.inst 0.028992 # miss rate for demand accesses 2177system.cpu1.icache.demand_miss_rate::total 0.028992 # miss rate for demand accesses 2178system.cpu1.icache.overall_miss_rate::cpu1.inst 0.028992 # miss rate for overall accesses 2179system.cpu1.icache.overall_miss_rate::total 0.028992 # miss rate for overall accesses 2180system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8782.415946 # average ReadReq miss latency 2181system.cpu1.icache.ReadReq_avg_miss_latency::total 8782.415946 # average ReadReq miss latency 2182system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8782.415946 # average overall miss latency 2183system.cpu1.icache.demand_avg_miss_latency::total 8782.415946 # average overall miss latency 2184system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8782.415946 # average overall miss latency 2185system.cpu1.icache.overall_avg_miss_latency::total 8782.415946 # average overall miss latency 2186system.cpu1.icache.blocked_cycles::no_mshrs 4496430 # number of cycles access was blocked 2187system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2188system.cpu1.icache.blocked::no_mshrs 574651 # number of cycles access was blocked 2189system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 2190system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.824627 # average number of cycles each access was blocked 2191system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2192system.cpu1.icache.fast_writes 0 # number of fast writes performed 2193system.cpu1.icache.cache_copies 0 # number of cache copies performed 2194system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 253840 # number of ReadReq MSHR hits 2195system.cpu1.icache.ReadReq_mshr_hits::total 253840 # number of ReadReq MSHR hits 2196system.cpu1.icache.demand_mshr_hits::cpu1.inst 253840 # number of demand (read+write) MSHR hits 2197system.cpu1.icache.demand_mshr_hits::total 253840 # number of demand (read+write) MSHR hits 2198system.cpu1.icache.overall_mshr_hits::cpu1.inst 253840 # number of overall MSHR hits 2199system.cpu1.icache.overall_mshr_hits::total 253840 # number of overall MSHR hits 2200system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5882218 # number of ReadReq MSHR misses 2201system.cpu1.icache.ReadReq_mshr_misses::total 5882218 # number of ReadReq MSHR misses 2202system.cpu1.icache.demand_mshr_misses::cpu1.inst 5882218 # number of demand (read+write) MSHR misses 2203system.cpu1.icache.demand_mshr_misses::total 5882218 # number of demand (read+write) MSHR misses 2204system.cpu1.icache.overall_mshr_misses::cpu1.inst 5882218 # number of overall MSHR misses 2205system.cpu1.icache.overall_mshr_misses::total 5882218 # number of overall MSHR misses 2206system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 43727434357 # number of ReadReq MSHR miss cycles 2207system.cpu1.icache.ReadReq_mshr_miss_latency::total 43727434357 # number of ReadReq MSHR miss cycles 2208system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 43727434357 # number of demand (read+write) MSHR miss cycles 2209system.cpu1.icache.demand_mshr_miss_latency::total 43727434357 # number of demand (read+write) MSHR miss cycles 2210system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 43727434357 # number of overall MSHR miss cycles 2211system.cpu1.icache.overall_mshr_miss_latency::total 43727434357 # number of overall MSHR miss cycles 2212system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6637997 # number of ReadReq MSHR uncacheable cycles 2213system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6637997 # number of ReadReq MSHR uncacheable cycles 2214system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6637997 # number of overall MSHR uncacheable cycles 2215system.cpu1.icache.overall_mshr_uncacheable_latency::total 6637997 # number of overall MSHR uncacheable cycles 2216system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027793 # mshr miss rate for ReadReq accesses 2217system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027793 # mshr miss rate for ReadReq accesses 2218system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027793 # mshr miss rate for demand accesses 2219system.cpu1.icache.demand_mshr_miss_rate::total 0.027793 # mshr miss rate for demand accesses 2220system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027793 # mshr miss rate for overall accesses 2221system.cpu1.icache.overall_mshr_miss_rate::total 0.027793 # mshr miss rate for overall accesses 2222system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7433.834373 # average ReadReq mshr miss latency 2223system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7433.834373 # average ReadReq mshr miss latency 2224system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7433.834373 # average overall mshr miss latency 2225system.cpu1.icache.demand_avg_mshr_miss_latency::total 7433.834373 # average overall mshr miss latency 2226system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7433.834373 # average overall mshr miss latency 2227system.cpu1.icache.overall_avg_mshr_miss_latency::total 7433.834373 # average overall mshr miss latency 2228system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2229system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2230system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2231system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2232system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2233system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 56932742 # number of hwpf identified 2234system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 2823095 # number of hwpf that were already in mshr 2235system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 47812216 # number of hwpf that were already in the cache 2236system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 2677811 # number of hwpf that were already in the prefetch queue 2237system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 2238system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 382726 # number of hwpf removed because MSHR allocated 2239system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 3236886 # number of hwpf issued 2240system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 4916498 # number of hwpf spanning a virtual page 2241system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 2242system.cpu1.l2cache.tags.replacements 4092617 # number of replacements 2243system.cpu1.l2cache.tags.tagsinuse 13780.930785 # Cycle average of tags in use 2244system.cpu1.l2cache.tags.total_refs 12621619 # Total number of references to valid blocks. 2245system.cpu1.l2cache.tags.sampled_refs 4108487 # Sample count of references to valid blocks. 2246system.cpu1.l2cache.tags.avg_refs 3.072084 # Average number of references to valid blocks. 2247system.cpu1.l2cache.tags.warmup_cycle 9637211064000 # Cycle when the warmup percentage was hit. 2248system.cpu1.l2cache.tags.occ_blocks::writebacks 3757.362843 # Average occupied blocks per requestor 2249system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 62.809020 # Average occupied blocks per requestor 2250system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 56.863279 # Average occupied blocks per requestor 2251system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 599.057552 # Average occupied blocks per requestor 2252system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3491.075179 # Average occupied blocks per requestor 2253system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 5813.762913 # Average occupied blocks per requestor 2254system.cpu1.l2cache.tags.occ_percent::writebacks 0.229331 # Average percentage of cache occupancy 2255system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003834 # Average percentage of cache occupancy 2256system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003471 # Average percentage of cache occupancy 2257system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.036564 # Average percentage of cache occupancy 2258system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.213078 # Average percentage of cache occupancy 2259system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.354844 # Average percentage of cache occupancy 2260system.cpu1.l2cache.tags.occ_percent::total 0.841121 # Average percentage of cache occupancy 2261system.cpu1.l2cache.tags.occ_task_id_blocks::1022 8933 # Occupied blocks per task id 2262system.cpu1.l2cache.tags.occ_task_id_blocks::1023 84 # Occupied blocks per task id 2263system.cpu1.l2cache.tags.occ_task_id_blocks::1024 6853 # Occupied blocks per task id 2264system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 68 # Occupied blocks per task id 2265system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 777 # Occupied blocks per task id 2266system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 3625 # Occupied blocks per task id 2267system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 2921 # Occupied blocks per task id 2268system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1542 # Occupied blocks per task id 2269system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 9 # Occupied blocks per task id 2270system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 64 # Occupied blocks per task id 2271system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 2272system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id 2273system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id 2274system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 856 # Occupied blocks per task id 2275system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 3137 # Occupied blocks per task id 2276system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2007 # Occupied blocks per task id 2277system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 750 # Occupied blocks per task id 2278system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.545227 # Percentage of cache occupancy per task id 2279system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005127 # Percentage of cache occupancy per task id 2280system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.418274 # Percentage of cache occupancy per task id 2281system.cpu1.l2cache.tags.tag_accesses 271640392 # Number of tag accesses 2282system.cpu1.l2cache.tags.data_accesses 271640392 # Number of data accesses 2283system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 596119 # number of ReadReq hits 2284system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 184681 # number of ReadReq hits 2285system.cpu1.l2cache.ReadReq_hits::cpu1.inst 5616426 # number of ReadReq hits 2286system.cpu1.l2cache.ReadReq_hits::cpu1.data 2971260 # number of ReadReq hits 2287system.cpu1.l2cache.ReadReq_hits::total 9368486 # number of ReadReq hits 2288system.cpu1.l2cache.Writeback_hits::writebacks 3658557 # number of Writeback hits 2289system.cpu1.l2cache.Writeback_hits::total 3658557 # number of Writeback hits 2290system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 182266 # number of WriteInvalidateReq hits 2291system.cpu1.l2cache.WriteInvalidateReq_hits::total 182266 # number of WriteInvalidateReq hits 2292system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 95807 # number of UpgradeReq hits 2293system.cpu1.l2cache.UpgradeReq_hits::total 95807 # number of UpgradeReq hits 2294system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 41710 # number of SCUpgradeReq hits 2295system.cpu1.l2cache.SCUpgradeReq_hits::total 41710 # number of SCUpgradeReq hits 2296system.cpu1.l2cache.ReadExReq_hits::cpu1.data 960995 # number of ReadExReq hits 2297system.cpu1.l2cache.ReadExReq_hits::total 960995 # number of ReadExReq hits 2298system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 596119 # number of demand (read+write) hits 2299system.cpu1.l2cache.demand_hits::cpu1.itb.walker 184681 # number of demand (read+write) hits 2300system.cpu1.l2cache.demand_hits::cpu1.inst 5616426 # number of demand (read+write) hits 2301system.cpu1.l2cache.demand_hits::cpu1.data 3932255 # number of demand (read+write) hits 2302system.cpu1.l2cache.demand_hits::total 10329481 # number of demand (read+write) hits 2303system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 596119 # number of overall hits 2304system.cpu1.l2cache.overall_hits::cpu1.itb.walker 184681 # number of overall hits 2305system.cpu1.l2cache.overall_hits::cpu1.inst 5616426 # number of overall hits 2306system.cpu1.l2cache.overall_hits::cpu1.data 3932255 # number of overall hits 2307system.cpu1.l2cache.overall_hits::total 10329481 # number of overall hits 2308system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 16104 # number of ReadReq misses 2309system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 12169 # number of ReadReq misses 2310system.cpu1.l2cache.ReadReq_misses::cpu1.inst 265788 # number of ReadReq misses 2311system.cpu1.l2cache.ReadReq_misses::cpu1.data 1166045 # number of ReadReq misses 2312system.cpu1.l2cache.ReadReq_misses::total 1460106 # number of ReadReq misses 2313system.cpu1.l2cache.Writeback_misses::writebacks 9 # number of Writeback misses 2314system.cpu1.l2cache.Writeback_misses::total 9 # number of Writeback misses 2315system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 271820 # number of WriteInvalidateReq misses 2316system.cpu1.l2cache.WriteInvalidateReq_misses::total 271820 # number of WriteInvalidateReq misses 2317system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 129531 # number of UpgradeReq misses 2318system.cpu1.l2cache.UpgradeReq_misses::total 129531 # number of UpgradeReq misses 2319system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 149141 # number of SCUpgradeReq misses 2320system.cpu1.l2cache.SCUpgradeReq_misses::total 149141 # number of SCUpgradeReq misses 2321system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 7 # number of SCUpgradeFailReq misses 2322system.cpu1.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses 2323system.cpu1.l2cache.ReadExReq_misses::cpu1.data 255657 # number of ReadExReq misses 2324system.cpu1.l2cache.ReadExReq_misses::total 255657 # number of ReadExReq misses 2325system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 16104 # number of demand (read+write) misses 2326system.cpu1.l2cache.demand_misses::cpu1.itb.walker 12169 # number of demand (read+write) misses 2327system.cpu1.l2cache.demand_misses::cpu1.inst 265788 # number of demand (read+write) misses 2328system.cpu1.l2cache.demand_misses::cpu1.data 1421702 # number of demand (read+write) misses 2329system.cpu1.l2cache.demand_misses::total 1715763 # number of demand (read+write) misses 2330system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 16104 # number of overall misses 2331system.cpu1.l2cache.overall_misses::cpu1.itb.walker 12169 # number of overall misses 2332system.cpu1.l2cache.overall_misses::cpu1.inst 265788 # number of overall misses 2333system.cpu1.l2cache.overall_misses::cpu1.data 1421702 # number of overall misses 2334system.cpu1.l2cache.overall_misses::total 1715763 # number of overall misses 2335system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 666484538 # number of ReadReq miss cycles 2336system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 571688851 # number of ReadReq miss cycles 2337system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 6944017926 # number of ReadReq miss cycles 2338system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 40559833009 # number of ReadReq miss cycles 2339system.cpu1.l2cache.ReadReq_miss_latency::total 48742024324 # number of ReadReq miss cycles 2340system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 11677447356 # number of WriteInvalidateReq miss cycles 2341system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 11677447356 # number of WriteInvalidateReq miss cycles 2342system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2603211060 # number of UpgradeReq miss cycles 2343system.cpu1.l2cache.UpgradeReq_miss_latency::total 2603211060 # number of UpgradeReq miss cycles 2344system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3027794367 # number of SCUpgradeReq miss cycles 2345system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3027794367 # number of SCUpgradeReq miss cycles 2346system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1818500 # number of SCUpgradeFailReq miss cycles 2347system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1818500 # number of SCUpgradeFailReq miss cycles 2348system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11891425269 # number of ReadExReq miss cycles 2349system.cpu1.l2cache.ReadExReq_miss_latency::total 11891425269 # number of ReadExReq miss cycles 2350system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 666484538 # number of demand (read+write) miss cycles 2351system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 571688851 # number of demand (read+write) miss cycles 2352system.cpu1.l2cache.demand_miss_latency::cpu1.inst 6944017926 # number of demand (read+write) miss cycles 2353system.cpu1.l2cache.demand_miss_latency::cpu1.data 52451258278 # number of demand (read+write) miss cycles 2354system.cpu1.l2cache.demand_miss_latency::total 60633449593 # number of demand (read+write) miss cycles 2355system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 666484538 # number of overall miss cycles 2356system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 571688851 # number of overall miss cycles 2357system.cpu1.l2cache.overall_miss_latency::cpu1.inst 6944017926 # number of overall miss cycles 2358system.cpu1.l2cache.overall_miss_latency::cpu1.data 52451258278 # number of overall miss cycles 2359system.cpu1.l2cache.overall_miss_latency::total 60633449593 # number of overall miss cycles 2360system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 612223 # number of ReadReq accesses(hits+misses) 2361system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 196850 # number of ReadReq accesses(hits+misses) 2362system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 5882214 # number of ReadReq accesses(hits+misses) 2363system.cpu1.l2cache.ReadReq_accesses::cpu1.data 4137305 # number of ReadReq accesses(hits+misses) 2364system.cpu1.l2cache.ReadReq_accesses::total 10828592 # number of ReadReq accesses(hits+misses) 2365system.cpu1.l2cache.Writeback_accesses::writebacks 3658566 # number of Writeback accesses(hits+misses) 2366system.cpu1.l2cache.Writeback_accesses::total 3658566 # number of Writeback accesses(hits+misses) 2367system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 454086 # number of WriteInvalidateReq accesses(hits+misses) 2368system.cpu1.l2cache.WriteInvalidateReq_accesses::total 454086 # number of WriteInvalidateReq accesses(hits+misses) 2369system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 225338 # number of UpgradeReq accesses(hits+misses) 2370system.cpu1.l2cache.UpgradeReq_accesses::total 225338 # number of UpgradeReq accesses(hits+misses) 2371system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 190851 # number of SCUpgradeReq accesses(hits+misses) 2372system.cpu1.l2cache.SCUpgradeReq_accesses::total 190851 # number of SCUpgradeReq accesses(hits+misses) 2373system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 7 # number of SCUpgradeFailReq accesses(hits+misses) 2374system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses) 2375system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1216652 # number of ReadExReq accesses(hits+misses) 2376system.cpu1.l2cache.ReadExReq_accesses::total 1216652 # number of ReadExReq accesses(hits+misses) 2377system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 612223 # number of demand (read+write) accesses 2378system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 196850 # number of demand (read+write) accesses 2379system.cpu1.l2cache.demand_accesses::cpu1.inst 5882214 # number of demand (read+write) accesses 2380system.cpu1.l2cache.demand_accesses::cpu1.data 5353957 # number of demand (read+write) accesses 2381system.cpu1.l2cache.demand_accesses::total 12045244 # number of demand (read+write) accesses 2382system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 612223 # number of overall (read+write) accesses 2383system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 196850 # number of overall (read+write) accesses 2384system.cpu1.l2cache.overall_accesses::cpu1.inst 5882214 # number of overall (read+write) accesses 2385system.cpu1.l2cache.overall_accesses::cpu1.data 5353957 # number of overall (read+write) accesses 2386system.cpu1.l2cache.overall_accesses::total 12045244 # number of overall (read+write) accesses 2387system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.026304 # miss rate for ReadReq accesses 2388system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.061819 # miss rate for ReadReq accesses 2389system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.045185 # miss rate for ReadReq accesses 2390system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.281837 # miss rate for ReadReq accesses 2391system.cpu1.l2cache.ReadReq_miss_rate::total 0.134838 # miss rate for ReadReq accesses 2392system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000002 # miss rate for Writeback accesses 2393system.cpu1.l2cache.Writeback_miss_rate::total 0.000002 # miss rate for Writeback accesses 2394system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.598609 # miss rate for WriteInvalidateReq accesses 2395system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.598609 # miss rate for WriteInvalidateReq accesses 2396system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.574830 # miss rate for UpgradeReq accesses 2397system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.574830 # miss rate for UpgradeReq accesses 2398system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.781453 # miss rate for SCUpgradeReq accesses 2399system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.781453 # miss rate for SCUpgradeReq accesses 2400system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2401system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2402system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.210132 # miss rate for ReadExReq accesses 2403system.cpu1.l2cache.ReadExReq_miss_rate::total 0.210132 # miss rate for ReadExReq accesses 2404system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.026304 # miss rate for demand accesses 2405system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.061819 # miss rate for demand accesses 2406system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.045185 # miss rate for demand accesses 2407system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.265542 # miss rate for demand accesses 2408system.cpu1.l2cache.demand_miss_rate::total 0.142443 # miss rate for demand accesses 2409system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.026304 # miss rate for overall accesses 2410system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.061819 # miss rate for overall accesses 2411system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.045185 # miss rate for overall accesses 2412system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.265542 # miss rate for overall accesses 2413system.cpu1.l2cache.overall_miss_rate::total 0.142443 # miss rate for overall accesses 2414system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 41386.272851 # average ReadReq miss latency 2415system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 46979.115046 # average ReadReq miss latency 2416system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 26126.152896 # average ReadReq miss latency 2417system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 34784.106110 # average ReadReq miss latency 2418system.cpu1.l2cache.ReadReq_avg_miss_latency::total 33382.524504 # average ReadReq miss latency 2419system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 42960.221308 # average WriteInvalidateReq miss latency 2420system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 42960.221308 # average WriteInvalidateReq miss latency 2421system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 20097.204993 # average UpgradeReq miss latency 2422system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 20097.204993 # average UpgradeReq miss latency 2423system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20301.556024 # average SCUpgradeReq miss latency 2424system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20301.556024 # average SCUpgradeReq miss latency 2425system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 259785.714286 # average SCUpgradeFailReq miss latency 2426system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 259785.714286 # average SCUpgradeFailReq miss latency 2427system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 46513.200378 # average ReadExReq miss latency 2428system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 46513.200378 # average ReadExReq miss latency 2429system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 41386.272851 # average overall miss latency 2430system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 46979.115046 # average overall miss latency 2431system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 26126.152896 # average overall miss latency 2432system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 36893.285849 # average overall miss latency 2433system.cpu1.l2cache.demand_avg_miss_latency::total 35339.058829 # average overall miss latency 2434system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 41386.272851 # average overall miss latency 2435system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 46979.115046 # average overall miss latency 2436system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 26126.152896 # average overall miss latency 2437system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 36893.285849 # average overall miss latency 2438system.cpu1.l2cache.overall_avg_miss_latency::total 35339.058829 # average overall miss latency 2439system.cpu1.l2cache.blocked_cycles::no_mshrs 176494 # number of cycles access was blocked 2440system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2441system.cpu1.l2cache.blocked::no_mshrs 8388 # number of cycles access was blocked 2442system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2443system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 21.041249 # average number of cycles each access was blocked 2444system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2445system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2446system.cpu1.l2cache.cache_copies 0 # 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number of ReadExReq MSHR hits 2458system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 3 # number of demand (read+write) MSHR hits 2459system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 164 # number of demand (read+write) MSHR hits 2460system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 69245 # number of demand (read+write) MSHR hits 2461system.cpu1.l2cache.demand_mshr_hits::cpu1.data 45167 # number of demand (read+write) MSHR hits 2462system.cpu1.l2cache.demand_mshr_hits::total 114579 # number of demand (read+write) MSHR hits 2463system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 3 # number of overall MSHR hits 2464system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 164 # number of overall MSHR hits 2465system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 69245 # number of overall MSHR hits 2466system.cpu1.l2cache.overall_mshr_hits::cpu1.data 45167 # number of overall MSHR hits 2467system.cpu1.l2cache.overall_mshr_hits::total 114579 # number of overall MSHR hits 2468system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 16101 # 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number of ReadReq MSHR miss cycles 2500system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 4373003012 # number of ReadReq MSHR miss cycles 2501system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 32056735781 # number of ReadReq MSHR miss cycles 2502system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 37461079918 # number of ReadReq MSHR miss cycles 2503system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 119200504380 # number of HardPFReq MSHR miss cycles 2504system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 119200504380 # number of HardPFReq MSHR miss cycles 2505system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 2795660291 # number of WriteInvalidateReq MSHR miss cycles 2506system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 2795660291 # number of WriteInvalidateReq MSHR miss cycles 2507system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2211789154 # number of UpgradeReq MSHR miss cycles 2508system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2211789154 # 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number of demand (read+write) MSHR miss cycles 2518system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 39351297895 # number of demand (read+write) MSHR miss cycles 2519system.cpu1.l2cache.demand_mshr_miss_latency::total 44755642032 # number of demand (read+write) MSHR miss cycles 2520system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 552512324 # number of overall MSHR miss cycles 2521system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 478828801 # number of overall MSHR miss cycles 2522system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 4373003012 # number of overall MSHR miss cycles 2523system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 39351297895 # number of overall MSHR miss cycles 2524system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 119200504380 # number of overall MSHR miss cycles 2525system.cpu1.l2cache.overall_mshr_miss_latency::total 163956146412 # number of overall MSHR miss cycles 2526system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6077501 # number of ReadReq MSHR uncacheable cycles 2527system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 736923302 # number of ReadReq MSHR uncacheable cycles 2528system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 743000803 # number of ReadReq MSHR uncacheable cycles 2529system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 890555024 # number of WriteReq MSHR uncacheable cycles 2530system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 890555024 # number of WriteReq MSHR uncacheable cycles 2531system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 6077501 # number of overall MSHR uncacheable cycles 2532system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1627478326 # number of overall MSHR uncacheable cycles 2533system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1633555827 # number of overall MSHR uncacheable cycles 2534system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.026299 # mshr miss rate for ReadReq accesses 2535system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.060986 # mshr miss rate for ReadReq accesses 2536system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.033413 # mshr miss rate for ReadReq accesses 2537system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.279663 # mshr miss rate for ReadReq accesses 2538system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.127597 # mshr miss rate for ReadReq accesses 2539system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for Writeback accesses 2540system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000002 # mshr miss rate for Writeback accesses 2541system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2542system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2543system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.198134 # mshr miss rate for WriteInvalidateReq accesses 2544system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.198134 # mshr miss rate for WriteInvalidateReq accesses 2545system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.574830 # mshr miss rate for UpgradeReq accesses 2546system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.574830 # mshr miss rate for UpgradeReq accesses 2547system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.781453 # mshr miss rate for SCUpgradeReq accesses 2548system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.781453 # mshr miss rate for SCUpgradeReq accesses 2549system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2550system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2551system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.180399 # mshr miss rate for ReadExReq accesses 2552system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.180399 # mshr miss rate for ReadExReq accesses 2553system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.026299 # mshr miss rate for demand accesses 2554system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.060986 # mshr miss rate for demand accesses 2555system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.033413 # mshr miss rate for demand accesses 2556system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.257106 # mshr miss rate for demand accesses 2557system.cpu1.l2cache.demand_mshr_miss_rate::total 0.132931 # mshr miss rate for demand accesses 2558system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.026299 # mshr miss rate for overall accesses 2559system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.060986 # mshr miss rate for overall accesses 2560system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.033413 # mshr miss rate for overall accesses 2561system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.257106 # mshr miss rate for overall accesses 2562system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2563system.cpu1.l2cache.overall_mshr_miss_rate::total 0.401623 # mshr miss rate for overall accesses 2564system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 34315.404261 # average ReadReq mshr miss latency 2565system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 39885.781008 # average ReadReq mshr miss latency 2566system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22249.599385 # average ReadReq mshr miss latency 2567system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 27705.527306 # average ReadReq mshr miss latency 2568system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 27112.291240 # average ReadReq mshr miss latency 2569system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36830.440224 # average HardPFReq mshr miss latency 2570system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36830.440224 # average HardPFReq mshr miss latency 2571system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31073.249872 # average WriteInvalidateReq mshr miss latency 2572system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 31073.249872 # average WriteInvalidateReq mshr miss latency 2573system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17075.365387 # average UpgradeReq mshr miss latency 2574system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17075.365387 # average UpgradeReq mshr miss latency 2575system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13826.798875 # average SCUpgradeReq mshr miss latency 2576system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13826.798875 # average SCUpgradeReq mshr miss latency 2577system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 213785.714286 # average SCUpgradeFailReq mshr miss latency 2578system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 213785.714286 # average SCUpgradeFailReq mshr miss latency 2579system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33235.203246 # average ReadExReq mshr miss latency 2580system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33235.203246 # average ReadExReq mshr miss latency 2581system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 34315.404261 # average overall mshr miss latency 2582system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 39885.781008 # average overall mshr miss latency 2583system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22249.599385 # average overall mshr miss latency 2584system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28587.212018 # average overall mshr miss latency 2585system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27951.592092 # average overall mshr miss latency 2586system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 34315.404261 # average overall mshr miss latency 2587system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 39885.781008 # average overall mshr miss latency 2588system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22249.599385 # average overall mshr miss latency 2589system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28587.212018 # average overall mshr miss latency 2590system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36830.440224 # average overall mshr miss latency 2591system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33891.685533 # average overall mshr miss latency 2592system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2593system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2594system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2595system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2596system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2597system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2598system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2599system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2600system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2601system.cpu1.toL2Bus.trans_dist::ReadReq 15325840 # Transaction distribution 2602system.cpu1.toL2Bus.trans_dist::ReadResp 11081361 # Transaction distribution 2603system.cpu1.toL2Bus.trans_dist::WriteReq 7210 # Transaction distribution 2604system.cpu1.toL2Bus.trans_dist::WriteResp 7210 # Transaction distribution 2605system.cpu1.toL2Bus.trans_dist::Writeback 3658566 # Transaction distribution 2606system.cpu1.toL2Bus.trans_dist::HardPFReq 4807205 # Transaction distribution 2607system.cpu1.toL2Bus.trans_dist::HardPFResp 18 # Transaction distribution 2608system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 637593 # Transaction distribution 2609system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 454086 # Transaction distribution 2610system.cpu1.toL2Bus.trans_dist::UpgradeReq 471082 # Transaction distribution 2611system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 336358 # Transaction distribution 2612system.cpu1.toL2Bus.trans_dist::UpgradeResp 477965 # Transaction distribution 2613system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 58 # Transaction distribution 2614system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution 2615system.cpu1.toL2Bus.trans_dist::ReadExReq 1352070 # Transaction distribution 2616system.cpu1.toL2Bus.trans_dist::ReadExResp 1222067 # Transaction distribution 2617system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11764566 # Packet count per connected master and slave (bytes) 2618system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16293479 # Packet count per connected master and slave (bytes) 2619system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 431287 # Packet count per connected master and slave (bytes) 2620system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1341589 # Packet count per connected master and slave (bytes) 2621system.cpu1.toL2Bus.pkt_count::total 29830921 # Packet count per connected master and slave (bytes) 2622system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 376462768 # Cumulative packet size per connected master and slave (bytes) 2623system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 612089908 # Cumulative packet size per connected master and slave (bytes) 2624system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1574800 # Cumulative packet size per connected master and slave (bytes) 2625system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4897784 # Cumulative packet size per connected master and slave (bytes) 2626system.cpu1.toL2Bus.pkt_size::total 995025260 # Cumulative packet size per connected master and slave (bytes) 2627system.cpu1.toL2Bus.snoops 10166385 # Total snoops (count) 2628system.cpu1.toL2Bus.snoop_fanout::samples 26584709 # Request fanout histogram 2629system.cpu1.toL2Bus.snoop_fanout::mean 5.370632 # Request fanout histogram 2630system.cpu1.toL2Bus.snoop_fanout::stdev 0.482974 # Request fanout histogram 2631system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2632system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2633system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 2634system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 2635system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 2636system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 2637system.cpu1.toL2Bus.snoop_fanout::5 16731578 62.94% 62.94% # Request fanout histogram 2638system.cpu1.toL2Bus.snoop_fanout::6 9853131 37.06% 100.00% # Request fanout histogram 2639system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2640system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 2641system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 2642system.cpu1.toL2Bus.snoop_fanout::total 26584709 # Request fanout histogram 2643system.cpu1.toL2Bus.reqLayer0.occupancy 12493291014 # Layer occupancy (ticks) 2644system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2645system.cpu1.toL2Bus.snoopLayer0.occupancy 175961487 # Layer occupancy (ticks) 2646system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2647system.cpu1.toL2Bus.respLayer0.occupancy 8832336643 # Layer occupancy (ticks) 2648system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2649system.cpu1.toL2Bus.respLayer1.occupancy 8528127192 # Layer occupancy (ticks) 2650system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2651system.cpu1.toL2Bus.respLayer2.occupancy 235484276 # Layer occupancy (ticks) 2652system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2653system.cpu1.toL2Bus.respLayer3.occupancy 730977975 # Layer occupancy (ticks) 2654system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2655system.iobus.trans_dist::ReadReq 40396 # Transaction distribution 2656system.iobus.trans_dist::ReadResp 40396 # Transaction distribution 2657system.iobus.trans_dist::WriteReq 136775 # Transaction distribution 2658system.iobus.trans_dist::WriteResp 30047 # Transaction distribution 2659system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution 2660system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48128 # Packet count per connected master and slave (bytes) 2661system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2662system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2663system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2664system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2665system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2666system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2667system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2668system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2669system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2670system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 2671system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2672system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 2673system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2674system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 2675system.iobus.pkt_count_system.bridge.master::total 123062 # Packet count per connected master and slave (bytes) 2676system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231200 # Packet count per connected master and slave (bytes) 2677system.iobus.pkt_count_system.realview.ide.dma::total 231200 # Packet count per connected master and slave (bytes) 2678system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2679system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 2680system.iobus.pkt_count::total 354342 # Packet count per connected master and slave (bytes) 2681system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48148 # Cumulative packet size per connected master and slave (bytes) 2682system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2683system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2684system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2685system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2686system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2687system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2688system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2689system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2690system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2691system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 2692system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 2693system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 2694system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 2695system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 2696system.iobus.pkt_size_system.bridge.master::total 156169 # Cumulative packet size per connected master and slave (bytes) 2697system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338816 # Cumulative packet size per connected master and slave (bytes) 2698system.iobus.pkt_size_system.realview.ide.dma::total 7338816 # Cumulative packet size per connected master and slave (bytes) 2699system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2700system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 2701system.iobus.pkt_size::total 7497071 # Cumulative packet size per connected master and slave (bytes) 2702system.iobus.reqLayer0.occupancy 36581000 # Layer occupancy (ticks) 2703system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2704system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 2705system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2706system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 2707system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2708system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 2709system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2710system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 2711system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2712system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 2713system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2714system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 2715system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2716system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 2717system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2718system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 2719system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2720system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 2721system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2722system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks) 2723system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2724system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 2725system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2726system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 2727system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2728system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 2729system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 2730system.iobus.reqLayer27.occupancy 1043032876 # Layer occupancy (ticks) 2731system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2732system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2733system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 2734system.iobus.respLayer0.occupancy 93018000 # Layer occupancy (ticks) 2735system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2736system.iobus.respLayer3.occupancy 179190812 # Layer occupancy (ticks) 2737system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2738system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) 2739system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 2740system.iocache.tags.replacements 115581 # number of replacements 2741system.iocache.tags.tagsinuse 11.295325 # Cycle average of tags in use 2742system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 2743system.iocache.tags.sampled_refs 115597 # Sample count of references to valid blocks. 2744system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 2745system.iocache.tags.warmup_cycle 9153631711000 # Cycle when the warmup percentage was hit. 2746system.iocache.tags.occ_blocks::realview.ethernet 3.835501 # Average occupied blocks per requestor 2747system.iocache.tags.occ_blocks::realview.ide 7.459825 # Average occupied blocks per requestor 2748system.iocache.tags.occ_percent::realview.ethernet 0.239719 # Average percentage of cache occupancy 2749system.iocache.tags.occ_percent::realview.ide 0.466239 # Average percentage of cache occupancy 2750system.iocache.tags.occ_percent::total 0.705958 # Average percentage of cache occupancy 2751system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2752system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2753system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2754system.iocache.tags.tag_accesses 1040757 # Number of tag accesses 2755system.iocache.tags.data_accesses 1040757 # Number of data accesses 2756system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2757system.iocache.ReadReq_misses::realview.ide 8872 # number of ReadReq misses 2758system.iocache.ReadReq_misses::total 8909 # number of ReadReq misses 2759system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2760system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2761system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses 2762system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses 2763system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 2764system.iocache.demand_misses::realview.ide 8872 # number of demand (read+write) misses 2765system.iocache.demand_misses::total 8912 # number of demand (read+write) misses 2766system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 2767system.iocache.overall_misses::realview.ide 8872 # number of overall misses 2768system.iocache.overall_misses::total 8912 # number of overall misses 2769system.iocache.ReadReq_miss_latency::realview.ethernet 5707000 # number of ReadReq miss cycles 2770system.iocache.ReadReq_miss_latency::realview.ide 1960529318 # number of ReadReq miss cycles 2771system.iocache.ReadReq_miss_latency::total 1966236318 # number of ReadReq miss cycles 2772system.iocache.WriteReq_miss_latency::realview.ethernet 365000 # number of WriteReq miss cycles 2773system.iocache.WriteReq_miss_latency::total 365000 # number of WriteReq miss cycles 2774system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28841569746 # number of WriteInvalidateReq miss cycles 2775system.iocache.WriteInvalidateReq_miss_latency::total 28841569746 # number of WriteInvalidateReq miss cycles 2776system.iocache.demand_miss_latency::realview.ethernet 6072000 # number of demand (read+write) miss cycles 2777system.iocache.demand_miss_latency::realview.ide 1960529318 # number of demand (read+write) miss cycles 2778system.iocache.demand_miss_latency::total 1966601318 # number of demand (read+write) miss cycles 2779system.iocache.overall_miss_latency::realview.ethernet 6072000 # number of overall miss cycles 2780system.iocache.overall_miss_latency::realview.ide 1960529318 # number of overall miss cycles 2781system.iocache.overall_miss_latency::total 1966601318 # number of overall miss cycles 2782system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 2783system.iocache.ReadReq_accesses::realview.ide 8872 # number of ReadReq accesses(hits+misses) 2784system.iocache.ReadReq_accesses::total 8909 # number of ReadReq accesses(hits+misses) 2785system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2786system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2787system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) 2788system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) 2789system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 2790system.iocache.demand_accesses::realview.ide 8872 # number of demand (read+write) accesses 2791system.iocache.demand_accesses::total 8912 # number of demand (read+write) accesses 2792system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 2793system.iocache.overall_accesses::realview.ide 8872 # number of overall (read+write) accesses 2794system.iocache.overall_accesses::total 8912 # number of overall (read+write) accesses 2795system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2796system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2797system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2798system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2799system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2800system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 2801system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 2802system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2803system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2804system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2805system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2806system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2807system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2808system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243 # average ReadReq miss latency 2809system.iocache.ReadReq_avg_miss_latency::realview.ide 220979.409152 # average ReadReq miss latency 2810system.iocache.ReadReq_avg_miss_latency::total 220702.246941 # average ReadReq miss latency 2811system.iocache.WriteReq_avg_miss_latency::realview.ethernet 121666.666667 # average WriteReq miss latency 2812system.iocache.WriteReq_avg_miss_latency::total 121666.666667 # average WriteReq miss latency 2813system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270234.331628 # average WriteInvalidateReq miss latency 2814system.iocache.WriteInvalidateReq_avg_miss_latency::total 270234.331628 # average WriteInvalidateReq miss latency 2815system.iocache.demand_avg_miss_latency::realview.ethernet 151800 # average overall miss latency 2816system.iocache.demand_avg_miss_latency::realview.ide 220979.409152 # average overall miss latency 2817system.iocache.demand_avg_miss_latency::total 220668.909111 # average overall miss latency 2818system.iocache.overall_avg_miss_latency::realview.ethernet 151800 # average overall miss latency 2819system.iocache.overall_avg_miss_latency::realview.ide 220979.409152 # average overall miss latency 2820system.iocache.overall_avg_miss_latency::total 220668.909111 # average overall miss latency 2821system.iocache.blocked_cycles::no_mshrs 224453 # number of cycles access was blocked 2822system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2823system.iocache.blocked::no_mshrs 27297 # number of cycles access was blocked 2824system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2825system.iocache.avg_blocked_cycles::no_mshrs 8.222625 # average number of cycles each access was blocked 2826system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2827system.iocache.fast_writes 0 # number of fast writes performed 2828system.iocache.cache_copies 0 # number of cache copies performed 2829system.iocache.writebacks::writebacks 106694 # number of writebacks 2830system.iocache.writebacks::total 106694 # number of writebacks 2831system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 2832system.iocache.ReadReq_mshr_misses::realview.ide 8872 # number of ReadReq MSHR misses 2833system.iocache.ReadReq_mshr_misses::total 8909 # number of ReadReq MSHR misses 2834system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2835system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2836system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses 2837system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses 2838system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 2839system.iocache.demand_mshr_misses::realview.ide 8872 # number of demand (read+write) MSHR misses 2840system.iocache.demand_mshr_misses::total 8912 # number of demand (read+write) MSHR misses 2841system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 2842system.iocache.overall_mshr_misses::realview.ide 8872 # number of overall MSHR misses 2843system.iocache.overall_mshr_misses::total 8912 # number of overall MSHR misses 2844system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3783000 # number of ReadReq MSHR miss cycles 2845system.iocache.ReadReq_mshr_miss_latency::realview.ide 1499010380 # number of ReadReq MSHR miss cycles 2846system.iocache.ReadReq_mshr_miss_latency::total 1502793380 # number of ReadReq MSHR miss cycles 2847system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 209000 # number of WriteReq MSHR miss cycles 2848system.iocache.WriteReq_mshr_miss_latency::total 209000 # number of WriteReq MSHR miss cycles 2849system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23291152308 # number of WriteInvalidateReq MSHR miss cycles 2850system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23291152308 # number of WriteInvalidateReq MSHR miss cycles 2851system.iocache.demand_mshr_miss_latency::realview.ethernet 3992000 # number of demand (read+write) MSHR miss cycles 2852system.iocache.demand_mshr_miss_latency::realview.ide 1499010380 # number of demand (read+write) MSHR miss cycles 2853system.iocache.demand_mshr_miss_latency::total 1503002380 # number of demand (read+write) MSHR miss cycles 2854system.iocache.overall_mshr_miss_latency::realview.ethernet 3992000 # number of overall MSHR miss cycles 2855system.iocache.overall_mshr_miss_latency::realview.ide 1499010380 # number of overall MSHR miss cycles 2856system.iocache.overall_mshr_miss_latency::total 1503002380 # number of overall MSHR miss cycles 2857system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2858system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2859system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2860system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2861system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2862system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 2863system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 2864system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 2865system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2866system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2867system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 2868system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2869system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2870system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243 # average ReadReq mshr miss latency 2871system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 168959.691163 # average ReadReq mshr miss latency 2872system.iocache.ReadReq_avg_mshr_miss_latency::total 168682.610843 # average ReadReq mshr miss latency 2873system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 69666.666667 # average WriteReq mshr miss latency 2874system.iocache.WriteReq_avg_mshr_miss_latency::total 69666.666667 # average WriteReq mshr miss latency 2875system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218229.071172 # average WriteInvalidateReq mshr miss latency 2876system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218229.071172 # average WriteInvalidateReq mshr miss latency 2877system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99800 # average overall mshr miss latency 2878system.iocache.demand_avg_mshr_miss_latency::realview.ide 168959.691163 # average overall mshr miss latency 2879system.iocache.demand_avg_mshr_miss_latency::total 168649.279623 # average overall mshr miss latency 2880system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99800 # average overall mshr miss latency 2881system.iocache.overall_avg_mshr_miss_latency::realview.ide 168959.691163 # average overall mshr miss latency 2882system.iocache.overall_avg_mshr_miss_latency::total 168649.279623 # average overall mshr miss latency 2883system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2884system.l2c.tags.replacements 1916125 # number of replacements 2885system.l2c.tags.tagsinuse 64884.880884 # Cycle average of tags in use 2886system.l2c.tags.total_refs 8755676 # Total number of references to valid blocks. 2887system.l2c.tags.sampled_refs 1978999 # Sample count of references to valid blocks. 2888system.l2c.tags.avg_refs 4.424295 # Average number of references to valid blocks. 2889system.l2c.tags.warmup_cycle 3437261500 # Cycle when the warmup percentage was hit. 2890system.l2c.tags.occ_blocks::writebacks 8337.656958 # Average occupied blocks per requestor 2891system.l2c.tags.occ_blocks::cpu0.dtb.walker 17.346754 # Average occupied blocks per requestor 2892system.l2c.tags.occ_blocks::cpu0.itb.walker 14.129416 # Average occupied blocks per requestor 2893system.l2c.tags.occ_blocks::cpu0.inst 627.039592 # Average occupied blocks per requestor 2894system.l2c.tags.occ_blocks::cpu0.data 3445.654069 # Average occupied blocks per requestor 2895system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 15412.309931 # Average occupied blocks per requestor 2896system.l2c.tags.occ_blocks::cpu1.dtb.walker 351.392171 # Average occupied blocks per requestor 2897system.l2c.tags.occ_blocks::cpu1.itb.walker 435.207962 # Average occupied blocks per requestor 2898system.l2c.tags.occ_blocks::cpu1.inst 621.389971 # Average occupied blocks per requestor 2899system.l2c.tags.occ_blocks::cpu1.data 11403.863316 # Average occupied blocks per requestor 2900system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 24218.890744 # Average occupied blocks per requestor 2901system.l2c.tags.occ_percent::writebacks 0.127223 # Average percentage of cache occupancy 2902system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000265 # Average percentage of cache occupancy 2903system.l2c.tags.occ_percent::cpu0.itb.walker 0.000216 # Average percentage of cache occupancy 2904system.l2c.tags.occ_percent::cpu0.inst 0.009568 # Average percentage of cache occupancy 2905system.l2c.tags.occ_percent::cpu0.data 0.052577 # Average percentage of cache occupancy 2906system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.235173 # Average percentage of cache occupancy 2907system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005362 # Average percentage of cache occupancy 2908system.l2c.tags.occ_percent::cpu1.itb.walker 0.006641 # Average percentage of cache occupancy 2909system.l2c.tags.occ_percent::cpu1.inst 0.009482 # Average percentage of cache occupancy 2910system.l2c.tags.occ_percent::cpu1.data 0.174009 # Average percentage of cache occupancy 2911system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.369551 # Average percentage of cache occupancy 2912system.l2c.tags.occ_percent::total 0.990065 # Average percentage of cache occupancy 2913system.l2c.tags.occ_task_id_blocks::1022 38428 # Occupied blocks per task id 2914system.l2c.tags.occ_task_id_blocks::1023 201 # Occupied blocks per task id 2915system.l2c.tags.occ_task_id_blocks::1024 24245 # Occupied blocks per task id 2916system.l2c.tags.age_task_id_blocks_1022::0 10 # Occupied blocks per task id 2917system.l2c.tags.age_task_id_blocks_1022::1 143 # Occupied blocks per task id 2918system.l2c.tags.age_task_id_blocks_1022::2 2926 # Occupied blocks per task id 2919system.l2c.tags.age_task_id_blocks_1022::3 6291 # Occupied blocks per task id 2920system.l2c.tags.age_task_id_blocks_1022::4 29058 # Occupied blocks per task id 2921system.l2c.tags.age_task_id_blocks_1023::2 14 # Occupied blocks per task id 2922system.l2c.tags.age_task_id_blocks_1023::4 187 # Occupied blocks per task id 2923system.l2c.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id 2924system.l2c.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id 2925system.l2c.tags.age_task_id_blocks_1024::2 1447 # Occupied blocks per task id 2926system.l2c.tags.age_task_id_blocks_1024::3 2670 # Occupied blocks per task id 2927system.l2c.tags.age_task_id_blocks_1024::4 19923 # Occupied blocks per task id 2928system.l2c.tags.occ_task_id_percent::1022 0.586365 # Percentage of cache occupancy per task id 2929system.l2c.tags.occ_task_id_percent::1023 0.003067 # Percentage of cache occupancy per task id 2930system.l2c.tags.occ_task_id_percent::1024 0.369949 # Percentage of cache occupancy per task id 2931system.l2c.tags.tag_accesses 93004482 # Number of tag accesses 2932system.l2c.tags.data_accesses 93004482 # Number of data accesses 2933system.l2c.ReadReq_hits::cpu0.dtb.walker 9030 # number of ReadReq hits 2934system.l2c.ReadReq_hits::cpu0.itb.walker 6306 # number of ReadReq hits 2935system.l2c.ReadReq_hits::cpu0.inst 171973 # number of ReadReq hits 2936system.l2c.ReadReq_hits::cpu0.data 713080 # number of ReadReq hits 2937system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 1991967 # number of ReadReq hits 2938system.l2c.ReadReq_hits::cpu1.dtb.walker 8819 # number of ReadReq hits 2939system.l2c.ReadReq_hits::cpu1.itb.walker 5864 # number of ReadReq hits 2940system.l2c.ReadReq_hits::cpu1.inst 186687 # number of ReadReq hits 2941system.l2c.ReadReq_hits::cpu1.data 740221 # number of ReadReq hits 2942system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 2136612 # number of ReadReq hits 2943system.l2c.ReadReq_hits::total 5970559 # number of ReadReq hits 2944system.l2c.Writeback_hits::writebacks 3063024 # number of Writeback hits 2945system.l2c.Writeback_hits::total 3063024 # number of Writeback hits 2946system.l2c.WriteInvalidateReq_hits::cpu0.data 47241 # number of WriteInvalidateReq hits 2947system.l2c.WriteInvalidateReq_hits::cpu1.data 45742 # number of WriteInvalidateReq hits 2948system.l2c.WriteInvalidateReq_hits::total 92983 # number of WriteInvalidateReq hits 2949system.l2c.UpgradeReq_hits::cpu0.data 33885 # number of UpgradeReq hits 2950system.l2c.UpgradeReq_hits::cpu1.data 29324 # number of UpgradeReq hits 2951system.l2c.UpgradeReq_hits::total 63209 # number of UpgradeReq hits 2952system.l2c.SCUpgradeReq_hits::cpu0.data 7714 # number of SCUpgradeReq hits 2953system.l2c.SCUpgradeReq_hits::cpu1.data 7828 # number of SCUpgradeReq hits 2954system.l2c.SCUpgradeReq_hits::total 15542 # number of SCUpgradeReq hits 2955system.l2c.ReadExReq_hits::cpu0.data 60878 # number of ReadExReq hits 2956system.l2c.ReadExReq_hits::cpu1.data 59021 # number of ReadExReq hits 2957system.l2c.ReadExReq_hits::total 119899 # number of ReadExReq hits 2958system.l2c.demand_hits::cpu0.dtb.walker 9030 # number of demand (read+write) hits 2959system.l2c.demand_hits::cpu0.itb.walker 6306 # number of demand (read+write) hits 2960system.l2c.demand_hits::cpu0.inst 171973 # number of demand (read+write) hits 2961system.l2c.demand_hits::cpu0.data 773958 # number of demand (read+write) hits 2962system.l2c.demand_hits::cpu0.l2cache.prefetcher 1991967 # number of demand (read+write) hits 2963system.l2c.demand_hits::cpu1.dtb.walker 8819 # number of demand (read+write) hits 2964system.l2c.demand_hits::cpu1.itb.walker 5864 # number of demand (read+write) hits 2965system.l2c.demand_hits::cpu1.inst 186687 # number of demand (read+write) hits 2966system.l2c.demand_hits::cpu1.data 799242 # number of demand (read+write) hits 2967system.l2c.demand_hits::cpu1.l2cache.prefetcher 2136612 # number of demand (read+write) hits 2968system.l2c.demand_hits::total 6090458 # number of demand (read+write) hits 2969system.l2c.overall_hits::cpu0.dtb.walker 9030 # number of overall hits 2970system.l2c.overall_hits::cpu0.itb.walker 6306 # number of overall hits 2971system.l2c.overall_hits::cpu0.inst 171973 # number of overall hits 2972system.l2c.overall_hits::cpu0.data 773958 # number of overall hits 2973system.l2c.overall_hits::cpu0.l2cache.prefetcher 1991967 # number of overall hits 2974system.l2c.overall_hits::cpu1.dtb.walker 8819 # number of overall hits 2975system.l2c.overall_hits::cpu1.itb.walker 5864 # number of overall hits 2976system.l2c.overall_hits::cpu1.inst 186687 # number of overall hits 2977system.l2c.overall_hits::cpu1.data 799242 # number of overall hits 2978system.l2c.overall_hits::cpu1.l2cache.prefetcher 2136612 # number of overall hits 2979system.l2c.overall_hits::total 6090458 # number of overall hits 2980system.l2c.ReadReq_misses::cpu0.dtb.walker 1923 # number of ReadReq misses 2981system.l2c.ReadReq_misses::cpu0.itb.walker 1303 # number of ReadReq misses 2982system.l2c.ReadReq_misses::cpu0.inst 12603 # number of ReadReq misses 2983system.l2c.ReadReq_misses::cpu0.data 144091 # number of ReadReq misses 2984system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 852232 # number of ReadReq misses 2985system.l2c.ReadReq_misses::cpu1.dtb.walker 3910 # number of ReadReq misses 2986system.l2c.ReadReq_misses::cpu1.itb.walker 3826 # number of ReadReq misses 2987system.l2c.ReadReq_misses::cpu1.inst 10632 # number of ReadReq misses 2988system.l2c.ReadReq_misses::cpu1.data 164104 # number of ReadReq misses 2989system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 554912 # number of ReadReq misses 2990system.l2c.ReadReq_misses::total 1749536 # number of ReadReq misses 2991system.l2c.WriteInvalidateReq_misses::cpu0.data 29537 # number of WriteInvalidateReq misses 2992system.l2c.WriteInvalidateReq_misses::cpu1.data 18781 # number of WriteInvalidateReq misses 2993system.l2c.WriteInvalidateReq_misses::total 48318 # number of WriteInvalidateReq misses 2994system.l2c.UpgradeReq_misses::cpu0.data 37338 # number of UpgradeReq misses 2995system.l2c.UpgradeReq_misses::cpu1.data 36221 # number of UpgradeReq misses 2996system.l2c.UpgradeReq_misses::total 73559 # number of UpgradeReq misses 2997system.l2c.SCUpgradeReq_misses::cpu0.data 9578 # number of SCUpgradeReq misses 2998system.l2c.SCUpgradeReq_misses::cpu1.data 9902 # number of SCUpgradeReq misses 2999system.l2c.SCUpgradeReq_misses::total 19480 # number of SCUpgradeReq misses 3000system.l2c.ReadExReq_misses::cpu0.data 52901 # number of ReadExReq misses 3001system.l2c.ReadExReq_misses::cpu1.data 53544 # number of ReadExReq misses 3002system.l2c.ReadExReq_misses::total 106445 # number of ReadExReq misses 3003system.l2c.demand_misses::cpu0.dtb.walker 1923 # number of demand (read+write) misses 3004system.l2c.demand_misses::cpu0.itb.walker 1303 # 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number of overall miss cycles 3062system.l2c.overall_miss_latency::cpu0.data 18259375538 # number of overall miss cycles 3063system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 153097994602 # number of overall miss cycles 3064system.l2c.overall_miss_latency::cpu1.dtb.walker 331865247 # number of overall miss cycles 3065system.l2c.overall_miss_latency::cpu1.itb.walker 326979750 # number of overall miss cycles 3066system.l2c.overall_miss_latency::cpu1.inst 1012532239 # number of overall miss cycles 3067system.l2c.overall_miss_latency::cpu1.data 19262995193 # number of overall miss cycles 3068system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 79345151118 # number of overall miss cycles 3069system.l2c.overall_miss_latency::total 273172050672 # number of overall miss cycles 3070system.l2c.ReadReq_accesses::cpu0.dtb.walker 10953 # number of ReadReq accesses(hits+misses) 3071system.l2c.ReadReq_accesses::cpu0.itb.walker 7609 # number of ReadReq accesses(hits+misses) 3072system.l2c.ReadReq_accesses::cpu0.inst 184576 # number of ReadReq accesses(hits+misses) 3073system.l2c.ReadReq_accesses::cpu0.data 857171 # number of ReadReq accesses(hits+misses) 3074system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 2844199 # number of ReadReq accesses(hits+misses) 3075system.l2c.ReadReq_accesses::cpu1.dtb.walker 12729 # number of ReadReq accesses(hits+misses) 3076system.l2c.ReadReq_accesses::cpu1.itb.walker 9690 # number of ReadReq accesses(hits+misses) 3077system.l2c.ReadReq_accesses::cpu1.inst 197319 # number of ReadReq accesses(hits+misses) 3078system.l2c.ReadReq_accesses::cpu1.data 904325 # number of ReadReq accesses(hits+misses) 3079system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 2691524 # number of ReadReq accesses(hits+misses) 3080system.l2c.ReadReq_accesses::total 7720095 # number of ReadReq accesses(hits+misses) 3081system.l2c.Writeback_accesses::writebacks 3063024 # number of Writeback accesses(hits+misses) 3082system.l2c.Writeback_accesses::total 3063024 # number of Writeback accesses(hits+misses) 3083system.l2c.WriteInvalidateReq_accesses::cpu0.data 76778 # number of WriteInvalidateReq accesses(hits+misses) 3084system.l2c.WriteInvalidateReq_accesses::cpu1.data 64523 # number of WriteInvalidateReq accesses(hits+misses) 3085system.l2c.WriteInvalidateReq_accesses::total 141301 # number of WriteInvalidateReq accesses(hits+misses) 3086system.l2c.UpgradeReq_accesses::cpu0.data 71223 # number of UpgradeReq accesses(hits+misses) 3087system.l2c.UpgradeReq_accesses::cpu1.data 65545 # number of UpgradeReq accesses(hits+misses) 3088system.l2c.UpgradeReq_accesses::total 136768 # number of UpgradeReq accesses(hits+misses) 3089system.l2c.SCUpgradeReq_accesses::cpu0.data 17292 # number of SCUpgradeReq accesses(hits+misses) 3090system.l2c.SCUpgradeReq_accesses::cpu1.data 17730 # number of SCUpgradeReq accesses(hits+misses) 3091system.l2c.SCUpgradeReq_accesses::total 35022 # number of SCUpgradeReq accesses(hits+misses) 3092system.l2c.ReadExReq_accesses::cpu0.data 113779 # number of ReadExReq accesses(hits+misses) 3093system.l2c.ReadExReq_accesses::cpu1.data 112565 # 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number of demand (read+write) accesses 3105system.l2c.demand_accesses::total 7946439 # number of demand (read+write) accesses 3106system.l2c.overall_accesses::cpu0.dtb.walker 10953 # number of overall (read+write) accesses 3107system.l2c.overall_accesses::cpu0.itb.walker 7609 # number of overall (read+write) accesses 3108system.l2c.overall_accesses::cpu0.inst 184576 # number of overall (read+write) accesses 3109system.l2c.overall_accesses::cpu0.data 970950 # number of overall (read+write) accesses 3110system.l2c.overall_accesses::cpu0.l2cache.prefetcher 2844199 # number of overall (read+write) accesses 3111system.l2c.overall_accesses::cpu1.dtb.walker 12729 # number of overall (read+write) accesses 3112system.l2c.overall_accesses::cpu1.itb.walker 9690 # number of overall (read+write) accesses 3113system.l2c.overall_accesses::cpu1.inst 197319 # number of overall (read+write) accesses 3114system.l2c.overall_accesses::cpu1.data 1016890 # number of overall (read+write) accesses 3115system.l2c.overall_accesses::cpu1.l2cache.prefetcher 2691524 # number of overall (read+write) accesses 3116system.l2c.overall_accesses::total 7946439 # number of overall (read+write) accesses 3117system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.175568 # miss rate for ReadReq accesses 3118system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.171245 # miss rate for ReadReq accesses 3119system.l2c.ReadReq_miss_rate::cpu0.inst 0.068281 # miss rate for ReadReq accesses 3120system.l2c.ReadReq_miss_rate::cpu0.data 0.168101 # miss rate for ReadReq accesses 3121system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.299639 # miss rate for ReadReq accesses 3122system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.307173 # miss rate for ReadReq accesses 3123system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.394840 # miss rate for ReadReq accesses 3124system.l2c.ReadReq_miss_rate::cpu1.inst 0.053882 # miss rate for ReadReq accesses 3125system.l2c.ReadReq_miss_rate::cpu1.data 0.181466 # miss rate for ReadReq accesses 3126system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.206170 # miss rate for ReadReq accesses 3127system.l2c.ReadReq_miss_rate::total 0.226621 # miss rate for ReadReq accesses 3128system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.384707 # miss rate for WriteInvalidateReq accesses 3129system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.291075 # miss rate for WriteInvalidateReq accesses 3130system.l2c.WriteInvalidateReq_miss_rate::total 0.341951 # miss rate for WriteInvalidateReq accesses 3131system.l2c.UpgradeReq_miss_rate::cpu0.data 0.524241 # miss rate for UpgradeReq accesses 3132system.l2c.UpgradeReq_miss_rate::cpu1.data 0.552613 # miss rate for UpgradeReq accesses 3133system.l2c.UpgradeReq_miss_rate::total 0.537838 # miss rate for UpgradeReq accesses 3134system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.553898 # miss rate for SCUpgradeReq accesses 3135system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.558488 # miss rate for SCUpgradeReq accesses 3136system.l2c.SCUpgradeReq_miss_rate::total 0.556222 # miss rate for SCUpgradeReq accesses 3137system.l2c.ReadExReq_miss_rate::cpu0.data 0.464945 # miss rate for ReadExReq accesses 3138system.l2c.ReadExReq_miss_rate::cpu1.data 0.475672 # miss rate for ReadExReq accesses 3139system.l2c.ReadExReq_miss_rate::total 0.470280 # miss rate for ReadExReq accesses 3140system.l2c.demand_miss_rate::cpu0.dtb.walker 0.175568 # miss rate for demand accesses 3141system.l2c.demand_miss_rate::cpu0.itb.walker 0.171245 # miss rate for demand accesses 3142system.l2c.demand_miss_rate::cpu0.inst 0.068281 # miss rate for demand accesses 3143system.l2c.demand_miss_rate::cpu0.data 0.202886 # miss rate for demand accesses 3144system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.299639 # miss rate for demand accesses 3145system.l2c.demand_miss_rate::cpu1.dtb.walker 0.307173 # miss rate for demand accesses 3146system.l2c.demand_miss_rate::cpu1.itb.walker 0.394840 # miss rate for demand accesses 3147system.l2c.demand_miss_rate::cpu1.inst 0.053882 # miss rate for demand accesses 3148system.l2c.demand_miss_rate::cpu1.data 0.214033 # miss rate for demand accesses 3149system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.206170 # miss rate for demand accesses 3150system.l2c.demand_miss_rate::total 0.233561 # miss rate for demand accesses 3151system.l2c.overall_miss_rate::cpu0.dtb.walker 0.175568 # miss rate for overall accesses 3152system.l2c.overall_miss_rate::cpu0.itb.walker 0.171245 # miss rate for overall accesses 3153system.l2c.overall_miss_rate::cpu0.inst 0.068281 # miss rate for overall accesses 3154system.l2c.overall_miss_rate::cpu0.data 0.202886 # miss rate for overall accesses 3155system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.299639 # miss rate for overall accesses 3156system.l2c.overall_miss_rate::cpu1.dtb.walker 0.307173 # miss rate for overall accesses 3157system.l2c.overall_miss_rate::cpu1.itb.walker 0.394840 # miss rate for overall accesses 3158system.l2c.overall_miss_rate::cpu1.inst 0.053882 # miss rate for overall accesses 3159system.l2c.overall_miss_rate::cpu1.data 0.214033 # miss rate for overall accesses 3160system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.206170 # miss rate for overall accesses 3161system.l2c.overall_miss_rate::total 0.233561 # miss rate for overall accesses 3162system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 92057.071243 # average ReadReq miss latency 3163system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 91801.993860 # average ReadReq miss latency 3164system.l2c.ReadReq_avg_miss_latency::cpu0.inst 98271.303579 # average ReadReq miss latency 3165system.l2c.ReadReq_avg_miss_latency::cpu0.data 96013.027038 # average ReadReq miss latency 3166system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 179643.564900 # average ReadReq miss latency 3167system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 84876.022251 # average ReadReq miss latency 3168system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 85462.558808 # average ReadReq miss latency 3169system.l2c.ReadReq_avg_miss_latency::cpu1.inst 95234.409236 # average ReadReq miss latency 3170system.l2c.ReadReq_avg_miss_latency::cpu1.data 90710.394841 # average ReadReq miss latency 3171system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 142986.908047 # average ReadReq miss latency 3172system.l2c.ReadReq_avg_miss_latency::total 151108.769214 # average ReadReq miss latency 3173system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 340.069404 # average WriteInvalidateReq miss latency 3174system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 556.818966 # average WriteInvalidateReq miss latency 3175system.l2c.WriteInvalidateReq_avg_miss_latency::total 424.319032 # average WriteInvalidateReq miss latency 3176system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 4696.419332 # average UpgradeReq miss latency 3177system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4581.201154 # average UpgradeReq miss latency 3178system.l2c.UpgradeReq_avg_miss_latency::total 4639.685042 # average UpgradeReq miss latency 3179system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5084.462518 # average SCUpgradeReq miss latency 3180system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5571.975964 # average SCUpgradeReq miss latency 3181system.l2c.SCUpgradeReq_avg_miss_latency::total 5332.273511 # average SCUpgradeReq miss latency 3182system.l2c.ReadExReq_avg_miss_latency::cpu0.data 83642.321676 # average ReadExReq miss latency 3183system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81746.910167 # average ReadExReq miss latency 3184system.l2c.ReadExReq_avg_miss_latency::total 82688.891136 # average ReadExReq miss latency 3185system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 92057.071243 # average overall miss latency 3186system.l2c.demand_avg_miss_latency::cpu0.itb.walker 91801.993860 # average overall miss latency 3187system.l2c.demand_avg_miss_latency::cpu0.inst 98271.303579 # average overall miss latency 3188system.l2c.demand_avg_miss_latency::cpu0.data 92690.949572 # average overall miss latency 3189system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 179643.564900 # average overall miss latency 3190system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 84876.022251 # average overall miss latency 3191system.l2c.demand_avg_miss_latency::cpu1.itb.walker 85462.558808 # average overall miss latency 3192system.l2c.demand_avg_miss_latency::cpu1.inst 95234.409236 # average overall miss latency 3193system.l2c.demand_avg_miss_latency::cpu1.data 88505.270864 # average overall miss latency 3194system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 142986.908047 # average overall miss latency 3195system.l2c.demand_avg_miss_latency::total 147184.723697 # average overall miss latency 3196system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 92057.071243 # average overall miss latency 3197system.l2c.overall_avg_miss_latency::cpu0.itb.walker 91801.993860 # average overall miss latency 3198system.l2c.overall_avg_miss_latency::cpu0.inst 98271.303579 # average overall miss latency 3199system.l2c.overall_avg_miss_latency::cpu0.data 92690.949572 # average overall miss latency 3200system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 179643.564900 # average overall miss latency 3201system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 84876.022251 # average overall miss latency 3202system.l2c.overall_avg_miss_latency::cpu1.itb.walker 85462.558808 # average overall miss latency 3203system.l2c.overall_avg_miss_latency::cpu1.inst 95234.409236 # average overall miss latency 3204system.l2c.overall_avg_miss_latency::cpu1.data 88505.270864 # average overall miss latency 3205system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 142986.908047 # average overall miss latency 3206system.l2c.overall_avg_miss_latency::total 147184.723697 # average overall miss latency 3207system.l2c.blocked_cycles::no_mshrs 89319 # number of cycles access was blocked 3208system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 3209system.l2c.blocked::no_mshrs 3582 # number of cycles access was blocked 3210system.l2c.blocked::no_targets 0 # number of cycles access was blocked 3211system.l2c.avg_blocked_cycles::no_mshrs 24.935511 # average number of cycles each access was blocked 3212system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3213system.l2c.fast_writes 0 # number of fast writes performed 3214system.l2c.cache_copies 0 # number of cache copies performed 3215system.l2c.writebacks::writebacks 1337500 # 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number of demand (read+write) MSHR hits 3229system.l2c.demand_mshr_hits::cpu1.inst 23 # number of demand (read+write) MSHR hits 3230system.l2c.demand_mshr_hits::cpu1.data 31 # number of demand (read+write) MSHR hits 3231system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 305 # number of demand (read+write) MSHR hits 3232system.l2c.demand_mshr_hits::total 654 # number of demand (read+write) MSHR hits 3233system.l2c.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits 3234system.l2c.overall_mshr_hits::cpu0.inst 17 # number of overall MSHR hits 3235system.l2c.overall_mshr_hits::cpu0.data 30 # number of overall MSHR hits 3236system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 247 # number of overall MSHR hits 3237system.l2c.overall_mshr_hits::cpu1.inst 23 # number of overall MSHR hits 3238system.l2c.overall_mshr_hits::cpu1.data 31 # number of overall MSHR hits 3239system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 305 # number of overall MSHR hits 3240system.l2c.overall_mshr_hits::total 654 # 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number of demand (read+write) MSHR misses 3275system.l2c.overall_mshr_misses::cpu0.dtb.walker 1922 # number of overall MSHR misses 3276system.l2c.overall_mshr_misses::cpu0.itb.walker 1303 # number of overall MSHR misses 3277system.l2c.overall_mshr_misses::cpu0.inst 12586 # number of overall MSHR misses 3278system.l2c.overall_mshr_misses::cpu0.data 196962 # number of overall MSHR misses 3279system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 851985 # number of overall MSHR misses 3280system.l2c.overall_mshr_misses::cpu1.dtb.walker 3910 # number of overall MSHR misses 3281system.l2c.overall_mshr_misses::cpu1.itb.walker 3826 # number of overall MSHR misses 3282system.l2c.overall_mshr_misses::cpu1.inst 10609 # number of overall MSHR misses 3283system.l2c.overall_mshr_misses::cpu1.data 217617 # number of overall MSHR misses 3284system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 554607 # number of overall MSHR misses 3285system.l2c.overall_mshr_misses::total 1855327 # number of overall MSHR misses 3286system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 153132498 # 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number of ReadReq MSHR miss cycles 3297system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 796481871 # number of WriteInvalidateReq MSHR miss cycles 3298system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 524588616 # number of WriteInvalidateReq MSHR miss cycles 3299system.l2c.WriteInvalidateReq_mshr_miss_latency::total 1321070487 # number of WriteInvalidateReq MSHR miss cycles 3300system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 384680247 # number of UpgradeReq MSHR miss cycles 3301system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 371145409 # number of UpgradeReq MSHR miss cycles 3302system.l2c.UpgradeReq_mshr_miss_latency::total 755825656 # number of UpgradeReq MSHR miss cycles 3303system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 98663909 # number of SCUpgradeReq MSHR miss cycles 3304system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 101839213 # number of SCUpgradeReq MSHR miss cycles 3305system.l2c.SCUpgradeReq_mshr_miss_latency::total 200503122 # number of SCUpgradeReq MSHR miss cycles 3306system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3765456447 # 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number of demand (read+write) MSHR miss cycles 3316system.l2c.demand_mshr_miss_latency::cpu1.inst 879069489 # number of demand (read+write) MSHR miss cycles 3317system.l2c.demand_mshr_miss_latency::cpu1.data 16556979239 # number of demand (read+write) MSHR miss cycles 3318system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 72582930119 # number of demand (read+write) MSHR miss cycles 3319system.l2c.demand_mshr_miss_latency::total 250500278615 # number of demand (read+write) MSHR miss cycles 3320system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 153132498 # number of overall MSHR miss cycles 3321system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 103417998 # number of overall MSHR miss cycles 3322system.l2c.overall_mshr_miss_latency::cpu0.inst 1081620491 # number of overall MSHR miss cycles 3323system.l2c.overall_mshr_miss_latency::cpu0.data 15810969380 # number of overall MSHR miss cycles 3324system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 142769903404 # number of overall MSHR miss cycles 3325system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 283035747 # number of overall MSHR miss cycles 3326system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 279220250 # number of overall MSHR miss cycles 3327system.l2c.overall_mshr_miss_latency::cpu1.inst 879069489 # number of overall MSHR miss cycles 3328system.l2c.overall_mshr_miss_latency::cpu1.data 16556979239 # number of overall MSHR miss cycles 3329system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 72582930119 # number of overall MSHR miss cycles 3330system.l2c.overall_mshr_miss_latency::total 250500278615 # number of overall MSHR miss cycles 3331system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1103207000 # number of ReadReq MSHR uncacheable cycles 3332system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4751952495 # number of ReadReq MSHR uncacheable cycles 3333system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 4753250 # number of ReadReq MSHR uncacheable cycles 3334system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 613999250 # number of ReadReq MSHR uncacheable cycles 3335system.l2c.ReadReq_mshr_uncacheable_latency::total 6473911995 # number of ReadReq MSHR uncacheable cycles 3336system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4501573998 # number of WriteReq MSHR uncacheable cycles 3337system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 766793502 # number of WriteReq MSHR uncacheable cycles 3338system.l2c.WriteReq_mshr_uncacheable_latency::total 5268367500 # number of WriteReq MSHR uncacheable cycles 3339system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1103207000 # number of overall MSHR uncacheable cycles 3340system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9253526493 # number of overall MSHR uncacheable cycles 3341system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4753250 # number of overall MSHR uncacheable cycles 3342system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1380792752 # number of overall MSHR uncacheable cycles 3343system.l2c.overall_mshr_uncacheable_latency::total 11742279495 # number of overall MSHR uncacheable cycles 3344system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.175477 # mshr miss rate for ReadReq accesses 3345system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.171245 # mshr miss rate for ReadReq accesses 3346system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.068189 # mshr miss rate for ReadReq accesses 3347system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.168066 # mshr miss rate for ReadReq accesses 3348system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.299552 # mshr miss rate for ReadReq accesses 3349system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.307173 # mshr miss rate for ReadReq accesses 3350system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.394840 # mshr miss rate for ReadReq accesses 3351system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.053766 # mshr miss rate for ReadReq accesses 3352system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.181431 # mshr miss rate for ReadReq accesses 3353system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.206057 # mshr miss rate for ReadReq accesses 3354system.l2c.ReadReq_mshr_miss_rate::total 0.226536 # mshr miss rate for ReadReq accesses 3355system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.384707 # mshr miss rate for WriteInvalidateReq accesses 3356system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.291075 # mshr miss rate for WriteInvalidateReq accesses 3357system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.341951 # mshr miss rate for WriteInvalidateReq accesses 3358system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.524241 # mshr miss rate for UpgradeReq accesses 3359system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.552613 # mshr miss rate for UpgradeReq accesses 3360system.l2c.UpgradeReq_mshr_miss_rate::total 0.537838 # mshr miss rate for UpgradeReq accesses 3361system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.553898 # mshr miss rate for SCUpgradeReq accesses 3362system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.558488 # mshr miss rate for SCUpgradeReq accesses 3363system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.556222 # mshr miss rate for SCUpgradeReq accesses 3364system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.464945 # mshr miss rate for ReadExReq accesses 3365system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.475672 # mshr miss rate for ReadExReq accesses 3366system.l2c.ReadExReq_mshr_miss_rate::total 0.470280 # mshr miss rate for ReadExReq accesses 3367system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.175477 # mshr miss rate for demand accesses 3368system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.171245 # mshr miss rate for demand accesses 3369system.l2c.demand_mshr_miss_rate::cpu0.inst 0.068189 # mshr miss rate for demand accesses 3370system.l2c.demand_mshr_miss_rate::cpu0.data 0.202855 # mshr miss rate for demand accesses 3371system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.299552 # mshr miss rate for demand accesses 3372system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.307173 # mshr miss rate for demand accesses 3373system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.394840 # mshr miss rate for demand accesses 3374system.l2c.demand_mshr_miss_rate::cpu1.inst 0.053766 # mshr miss rate for demand accesses 3375system.l2c.demand_mshr_miss_rate::cpu1.data 0.214002 # mshr miss rate for demand accesses 3376system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.206057 # mshr miss rate for demand accesses 3377system.l2c.demand_mshr_miss_rate::total 0.233479 # mshr miss rate for demand accesses 3378system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.175477 # mshr miss rate for overall accesses 3379system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.171245 # mshr miss rate for overall accesses 3380system.l2c.overall_mshr_miss_rate::cpu0.inst 0.068189 # mshr miss rate for overall accesses 3381system.l2c.overall_mshr_miss_rate::cpu0.data 0.202855 # mshr miss rate for overall accesses 3382system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.299552 # mshr miss rate for overall accesses 3383system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.307173 # mshr miss rate for overall accesses 3384system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.394840 # mshr miss rate for overall accesses 3385system.l2c.overall_mshr_miss_rate::cpu1.inst 0.053766 # mshr miss rate for overall accesses 3386system.l2c.overall_mshr_miss_rate::cpu1.data 0.214002 # mshr miss rate for overall accesses 3387system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.206057 # mshr miss rate for overall accesses 3388system.l2c.overall_mshr_miss_rate::total 0.233479 # mshr miss rate for overall accesses 3389system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 79673.516129 # average ReadReq mshr miss latency 3390system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 79369.146585 # average ReadReq mshr miss latency 3391system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 85938.383204 # average ReadReq mshr miss latency 3392system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 83613.975559 # average ReadReq mshr miss latency 3393system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 167573.259393 # average ReadReq mshr miss latency 3394system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 72387.659079 # average ReadReq mshr miss latency 3395system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 72979.678515 # average ReadReq mshr miss latency 3396system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 82860.730418 # average ReadReq mshr miss latency 3397system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 78300.094379 # average ReadReq mshr miss latency 3398system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130872.726307 # average ReadReq mshr miss latency 3399system.l2c.ReadReq_avg_mshr_miss_latency::total 138960.075245 # average ReadReq mshr miss latency 3400system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 26965.564241 # average WriteInvalidateReq mshr miss latency 3401system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 27931.878814 # average WriteInvalidateReq mshr miss latency 3402system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 27341.166584 # average WriteInvalidateReq mshr miss latency 3403system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10302.647357 # average UpgradeReq mshr miss latency 3404system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10246.691394 # average UpgradeReq mshr miss latency 3405system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10275.094224 # average UpgradeReq mshr miss latency 3406system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10301.097202 # average SCUpgradeReq mshr miss latency 3407system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10284.711472 # average SCUpgradeReq mshr miss latency 3408system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10292.768070 # average SCUpgradeReq mshr miss latency 3409system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 71179.305627 # average ReadExReq mshr miss latency 3410system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69289.702936 # average ReadExReq mshr miss latency 3411system.l2c.ReadExReq_avg_mshr_miss_latency::total 70228.797041 # average ReadExReq mshr miss latency 3412system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79673.516129 # average overall mshr miss latency 3413system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79369.146585 # average overall mshr miss latency 3414system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 85938.383204 # average overall mshr miss latency 3415system.l2c.demand_avg_mshr_miss_latency::cpu0.data 80274.212183 # average overall mshr miss latency 3416system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 167573.259393 # average overall mshr miss latency 3417system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 72387.659079 # average overall mshr miss latency 3418system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 72979.678515 # average overall mshr miss latency 3419system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 82860.730418 # average overall mshr miss latency 3420system.l2c.demand_avg_mshr_miss_latency::cpu1.data 76083.115009 # average overall mshr miss latency 3421system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130872.726307 # average overall mshr miss latency 3422system.l2c.demand_avg_mshr_miss_latency::total 135016.780662 # average overall mshr miss latency 3423system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79673.516129 # average overall mshr miss latency 3424system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79369.146585 # average overall mshr miss latency 3425system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 85938.383204 # average overall mshr miss latency 3426system.l2c.overall_avg_mshr_miss_latency::cpu0.data 80274.212183 # average overall mshr miss latency 3427system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 167573.259393 # average overall mshr miss latency 3428system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 72387.659079 # average overall mshr miss latency 3429system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 72979.678515 # average overall mshr miss latency 3430system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 82860.730418 # average overall mshr miss latency 3431system.l2c.overall_avg_mshr_miss_latency::cpu1.data 76083.115009 # average overall mshr miss latency 3432system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130872.726307 # average overall mshr miss latency 3433system.l2c.overall_avg_mshr_miss_latency::total 135016.780662 # average overall mshr miss latency 3434system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 3435system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 3436system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 3437system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 3438system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 3439system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 3440system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 3441system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 3442system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 3443system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 3444system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 3445system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 3446system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 3447system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 3448system.membus.trans_dist::ReadReq 1817706 # Transaction distribution 3449system.membus.trans_dist::ReadResp 1817706 # Transaction distribution 3450system.membus.trans_dist::WriteReq 38526 # Transaction distribution 3451system.membus.trans_dist::WriteResp 38526 # Transaction distribution 3452system.membus.trans_dist::Writeback 1444194 # Transaction distribution 3453system.membus.trans_dist::WriteInvalidateReq 154200 # Transaction distribution 3454system.membus.trans_dist::WriteInvalidateResp 154200 # Transaction distribution 3455system.membus.trans_dist::UpgradeReq 434662 # Transaction distribution 3456system.membus.trans_dist::SCUpgradeReq 279066 # Transaction distribution 3457system.membus.trans_dist::UpgradeResp 97607 # Transaction distribution 3458system.membus.trans_dist::ReadExReq 117028 # Transaction distribution 3459system.membus.trans_dist::ReadExResp 102726 # Transaction distribution 3460system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123062 # Packet count per connected master and slave (bytes) 3461system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) 3462system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25796 # Packet count per connected master and slave (bytes) 3463system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6008493 # Packet count per connected master and slave (bytes) 3464system.membus.pkt_count_system.l2c.mem_side::total 6157429 # Packet count per connected master and slave (bytes) 3465system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336112 # Packet count per connected master and slave (bytes) 3466system.membus.pkt_count_system.iocache.mem_side::total 336112 # Packet count per connected master and slave (bytes) 3467system.membus.pkt_count::total 6493541 # Packet count per connected master and slave (bytes) 3468system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156169 # Cumulative packet size per connected master and slave (bytes) 3469system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 572 # Cumulative packet size per connected master and slave (bytes) 3470system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51592 # Cumulative packet size per connected master and slave (bytes) 3471system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 207457224 # Cumulative packet size per connected master and slave (bytes) 3472system.membus.pkt_size_system.l2c.mem_side::total 207665557 # Cumulative packet size per connected master and slave (bytes) 3473system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14110208 # Cumulative packet size per connected master and slave (bytes) 3474system.membus.pkt_size_system.iocache.mem_side::total 14110208 # Cumulative packet size per connected master and slave (bytes) 3475system.membus.pkt_size::total 221775765 # Cumulative packet size per connected master and slave (bytes) 3476system.membus.snoops 633029 # Total snoops (count) 3477system.membus.snoop_fanout::samples 4186947 # Request fanout histogram 3478system.membus.snoop_fanout::mean 1 # Request fanout histogram 3479system.membus.snoop_fanout::stdev 0 # Request fanout histogram 3480system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3481system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3482system.membus.snoop_fanout::1 4186947 100.00% 100.00% # Request fanout histogram 3483system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3484system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3485system.membus.snoop_fanout::min_value 1 # Request fanout histogram 3486system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3487system.membus.snoop_fanout::total 4186947 # Request fanout histogram 3488system.membus.reqLayer0.occupancy 98514469 # Layer occupancy (ticks) 3489system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3490system.membus.reqLayer1.occupancy 45500 # Layer occupancy (ticks) 3491system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3492system.membus.reqLayer2.occupancy 21244987 # Layer occupancy (ticks) 3493system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3494system.membus.reqLayer5.occupancy 16738053981 # Layer occupancy (ticks) 3495system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3496system.membus.respLayer2.occupancy 17312327015 # Layer occupancy (ticks) 3497system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3498system.membus.respLayer3.occupancy 187280188 # Layer occupancy (ticks) 3499system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3500system.realview.ethernet.txBytes 966 # Bytes Transmitted 3501system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3502system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3503system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3504system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3505system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3506system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3507system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3508system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3509system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 3510system.realview.ethernet.totPackets 3 # Total Packets 3511system.realview.ethernet.totBytes 966 # Total Bytes 3512system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 3513system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 3514system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 3515system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3516system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 3517system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3518system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3519system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 3520system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3521system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3522system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 3523system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3524system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3525system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 3526system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3527system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3528system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 3529system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3530system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3531system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 3532system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3533system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3534system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3535system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3536system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3537system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3538system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3539system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3540system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3541system.realview.ethernet.droppedPackets 0 # number of packets dropped 3542system.toL2Bus.trans_dist::ReadReq 8653355 # Transaction distribution 3543system.toL2Bus.trans_dist::ReadResp 8646086 # Transaction distribution 3544system.toL2Bus.trans_dist::WriteReq 38526 # Transaction distribution 3545system.toL2Bus.trans_dist::WriteResp 38526 # Transaction distribution 3546system.toL2Bus.trans_dist::Writeback 3063024 # Transaction distribution 3547system.toL2Bus.trans_dist::WriteInvalidateReq 248029 # Transaction distribution 3548system.toL2Bus.trans_dist::WriteInvalidateResp 141301 # Transaction distribution 3549system.toL2Bus.trans_dist::UpgradeReq 493306 # Transaction distribution 3550system.toL2Bus.trans_dist::SCUpgradeReq 294608 # Transaction distribution 3551system.toL2Bus.trans_dist::UpgradeResp 787914 # Transaction distribution 3552system.toL2Bus.trans_dist::SCUpgradeFailReq 97 # Transaction distribution 3553system.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution 3554system.toL2Bus.trans_dist::ReadExReq 273153 # Transaction distribution 3555system.toL2Bus.trans_dist::ReadExResp 273153 # Transaction distribution 3556system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10956928 # Packet count per connected master and slave (bytes) 3557system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10351144 # Packet count per connected master and slave (bytes) 3558system.toL2Bus.pkt_count::total 21308072 # Packet count per connected master and slave (bytes) 3559system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 369780529 # Cumulative packet size per connected master and slave (bytes) 3560system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 344544100 # Cumulative packet size per connected master and slave (bytes) 3561system.toL2Bus.pkt_size::total 714324629 # Cumulative packet size per connected master and slave (bytes) 3562system.toL2Bus.snoops 1644746 # Total snoops (count) 3563system.toL2Bus.snoop_fanout::samples 12968411 # Request fanout histogram 3564system.toL2Bus.snoop_fanout::mean 1.008917 # Request fanout histogram 3565system.toL2Bus.snoop_fanout::stdev 0.094008 # Request fanout histogram 3566system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3567system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3568system.toL2Bus.snoop_fanout::1 12852771 99.11% 99.11% # Request fanout histogram 3569system.toL2Bus.snoop_fanout::2 115640 0.89% 100.00% # Request fanout histogram 3570system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3571system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 3572system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3573system.toL2Bus.snoop_fanout::total 12968411 # Request fanout histogram 3574system.toL2Bus.reqLayer0.occupancy 19352517195 # Layer occupancy (ticks) 3575system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3576system.toL2Bus.snoopLayer0.occupancy 7381500 # Layer occupancy (ticks) 3577system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3578system.toL2Bus.respLayer0.occupancy 20456793572 # Layer occupancy (ticks) 3579system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3580system.toL2Bus.respLayer1.occupancy 20083133002 # Layer occupancy (ticks) 3581system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3582system.cpu0.kern.inst.arm 0 # number of arm instructions executed 3583system.cpu0.kern.inst.quiesce 13518 # number of quiesce instructions executed 3584system.cpu1.kern.inst.arm 0 # number of arm instructions executed 3585system.cpu1.kern.inst.quiesce 5604 # number of quiesce instructions executed 3586 3587---------- End Simulation Statistics ---------- 3588