110515SAli.Saidi@ARM.com 210515SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 311860Sandreas.hansson@arm.comsim_seconds 47.341923 # Number of seconds simulated 411860Sandreas.hansson@arm.comsim_ticks 47341923254000 # Number of ticks simulated 511860Sandreas.hansson@arm.comfinal_tick 47341923254000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 711860Sandreas.hansson@arm.comhost_inst_rate 198941 # Simulator instruction rate (inst/s) 811860Sandreas.hansson@arm.comhost_op_rate 237233 # Simulator op (including micro ops) rate (op/s) 911860Sandreas.hansson@arm.comhost_tick_rate 10723675807 # Simulator tick rate (ticks/s) 1011860Sandreas.hansson@arm.comhost_mem_usage 786956 # Number of bytes of host memory used 1111860Sandreas.hansson@arm.comhost_seconds 4414.71 # Real time elapsed on the host 1211860Sandreas.hansson@arm.comsim_insts 878265186 # Number of instructions simulated 1311860Sandreas.hansson@arm.comsim_ops 1047316960 # Number of ops (including micro ops) simulated 1410515SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611860Sandreas.hansson@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 1711860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 242176 # Number of bytes read from this memory 1811860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 233728 # Number of bytes read from this memory 1911860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 4193568 # Number of bytes read from this memory 2011860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 18888648 # Number of bytes read from this memory 2111860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.l2cache.prefetcher 25252160 # Number of bytes read from this memory 2211860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 159808 # Number of bytes read from this memory 2311860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.itb.walker 110720 # Number of bytes read from this memory 2411860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 3691360 # Number of bytes read from this memory 2511860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 11578384 # Number of bytes read from this memory 2611860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.l2cache.prefetcher 16897024 # Number of bytes read from this memory 2711860Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 434368 # Number of bytes read from this memory 2811860Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 81681944 # Number of bytes read from this memory 2911860Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 4193568 # Number of instructions bytes read from this memory 3011860Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 3691360 # Number of instructions bytes read from this memory 3111860Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 7884928 # Number of instructions bytes read from this memory 3211860Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 97721664 # Number of bytes written to this memory 3310827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 3410585Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3511860Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 97742248 # Number of bytes written to this memory 3611860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 3784 # Number of read requests responded to by this memory 3711860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.itb.walker 3652 # Number of read requests responded to by this memory 3811860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 67077 # Number of read requests responded to by this memory 3911860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 295148 # Number of read requests responded to by this memory 4011860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.l2cache.prefetcher 394565 # Number of read requests responded to by this memory 4111860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 2497 # Number of read requests responded to by this memory 4211860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.itb.walker 1730 # Number of read requests responded to by this memory 4311860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 57721 # Number of read requests responded to by this memory 4411860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 180925 # Number of read requests responded to by this memory 4511860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.l2cache.prefetcher 264016 # Number of read requests responded to by this memory 4611860Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 6787 # Number of read requests responded to by this memory 4711860Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1277902 # Number of read requests responded to by this memory 4811860Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 1526901 # Number of write requests responded to by this memory 4910827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 5010585Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 5111860Sandreas.hansson@arm.comsystem.physmem.num_writes::total 1529475 # Number of write requests responded to by this memory 5211860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 5115 # Total read bandwidth from this memory (bytes/s) 5311860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.itb.walker 4937 # Total read bandwidth from this memory (bytes/s) 5411860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 88580 # Total read bandwidth from this memory (bytes/s) 5511860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 398984 # Total read bandwidth from this memory (bytes/s) 5611860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.l2cache.prefetcher 533400 # Total read bandwidth from this memory (bytes/s) 5711860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 3376 # Total read bandwidth from this memory (bytes/s) 5811860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.itb.walker 2339 # Total read bandwidth from this memory (bytes/s) 5911860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 77972 # Total read bandwidth from this memory (bytes/s) 6011860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 244569 # Total read bandwidth from this memory (bytes/s) 6111860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.l2cache.prefetcher 356915 # Total read bandwidth from this memory (bytes/s) 6211860Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 9175 # Total read bandwidth from this memory (bytes/s) 6311860Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1725362 # Total read bandwidth from this memory (bytes/s) 6411860Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 88580 # Instruction read bandwidth from this memory (bytes/s) 6511860Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 77972 # Instruction read bandwidth from this memory (bytes/s) 6611860Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 166553 # Instruction read bandwidth from this memory (bytes/s) 6711860Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 2064168 # Write bandwidth from this memory (bytes/s) 6811860Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) 6910585Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 7011860Sandreas.hansson@arm.comsystem.physmem.bw_write::total 2064602 # Write bandwidth from this memory (bytes/s) 7111860Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 2064168 # Total bandwidth to/from this memory (bytes/s) 7211860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 5115 # Total bandwidth to/from this memory (bytes/s) 7311860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.itb.walker 4937 # Total bandwidth to/from this memory (bytes/s) 7411860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 88580 # Total bandwidth to/from this memory (bytes/s) 7511860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 399418 # Total bandwidth to/from this memory (bytes/s) 7611860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.l2cache.prefetcher 533400 # Total bandwidth to/from this memory (bytes/s) 7711860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 3376 # Total bandwidth to/from this memory (bytes/s) 7811860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.itb.walker 2339 # Total bandwidth to/from this memory (bytes/s) 7911860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 77972 # Total bandwidth to/from this memory (bytes/s) 8011860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 244569 # Total bandwidth to/from this memory (bytes/s) 8111860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.l2cache.prefetcher 356915 # Total bandwidth to/from this memory (bytes/s) 8211860Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 9175 # Total bandwidth to/from this memory (bytes/s) 8311860Sandreas.hansson@arm.comsystem.physmem.bw_total::total 3789964 # Total bandwidth to/from this memory (bytes/s) 8411860Sandreas.hansson@arm.comsystem.physmem.readReqs 1277902 # Number of read requests accepted 8511860Sandreas.hansson@arm.comsystem.physmem.writeReqs 1529475 # Number of write requests accepted 8611860Sandreas.hansson@arm.comsystem.physmem.readBursts 1277902 # Number of DRAM read bursts, including those serviced by the write queue 8711860Sandreas.hansson@arm.comsystem.physmem.writeBursts 1529475 # Number of DRAM write bursts, including those merged in the write queue 8811860Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 81759232 # Total number of bytes read from DRAM 8911860Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 26496 # Total number of bytes read from write queue 9011860Sandreas.hansson@arm.comsystem.physmem.bytesWritten 97740224 # Total number of bytes written to DRAM 9111860Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 81681944 # Total read bytes from the system interface side 9211860Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 97742248 # Total written bytes from the system interface side 9311860Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 414 # Number of DRAM read bursts serviced by the write queue 9411860Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 2256 # Number of DRAM write bursts merged with an existing one 9511336Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 9611860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 74308 # Per bank write bursts 9711860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 87985 # Per bank write bursts 9811860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 79775 # Per bank write bursts 9911860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 80704 # Per bank write bursts 10011860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 79279 # Per bank write bursts 10111860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 87661 # Per bank write bursts 10211860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 78349 # Per bank write bursts 10311860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 78833 # Per bank write bursts 10411860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 69442 # Per bank write bursts 10511860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 78370 # Per bank write bursts 10611860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 69793 # Per bank write bursts 10711860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 81996 # Per bank write bursts 10811860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 80451 # Per bank write bursts 10911860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 82396 # Per bank write bursts 11011860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 80116 # Per bank write bursts 11111860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 88030 # Per bank write bursts 11211860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 92185 # Per bank write bursts 11311860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 101129 # Per bank write bursts 11411860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 94103 # Per bank write bursts 11511860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 97328 # Per bank write bursts 11611860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 94264 # Per bank write bursts 11711860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 99023 # Per bank write bursts 11811860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 94391 # Per bank write bursts 11911860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 95568 # Per bank write bursts 12011860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 90026 # Per bank write bursts 12111860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 95851 # Per bank write bursts 12211860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 88927 # Per bank write bursts 12311860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 96294 # Per bank write bursts 12411860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 94934 # Per bank write bursts 12511860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 97047 # Per bank write bursts 12611860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 95210 # Per bank write bursts 12711860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 100911 # Per bank write bursts 12810515SAli.Saidi@ARM.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 12911860Sandreas.hansson@arm.comsystem.physmem.numWrRetry 51774 # Number of times write queue was full causing retry 13011860Sandreas.hansson@arm.comsystem.physmem.totGap 47341921675500 # Total gap between requests 13110515SAli.Saidi@ARM.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 13210515SAli.Saidi@ARM.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 13310515SAli.Saidi@ARM.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 13410827Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 25 # Read request sizes (log2) 13511860Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 2133 # Read request sizes (log2) 13610515SAli.Saidi@ARM.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 13711860Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 1275744 # Read request sizes (log2) 13810515SAli.Saidi@ARM.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 13910515SAli.Saidi@ARM.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 14010515SAli.Saidi@ARM.comsystem.physmem.writePktSize::2 2 # Write request sizes (log2) 14110827Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 14210515SAli.Saidi@ARM.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 14310515SAli.Saidi@ARM.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 14411860Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 1526901 # Write request sizes (log2) 14511860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 505708 # What read queue length does an incoming req see 14611860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 298665 # What read queue length does an incoming req see 14711860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 136731 # What read queue length does an incoming req see 14811860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 85460 # What read queue length does an incoming req see 14911860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 55927 # What read queue length does an incoming req see 15011860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 46831 # What read queue length does an incoming req see 15111860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 42547 # What read queue length does an incoming req see 15211860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 39408 # What read queue length does an incoming req see 15311860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 35921 # What read queue length does an incoming req see 15411860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 11095 # What read queue length does an incoming req see 15511860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 6380 # What read queue length does an incoming req see 15611860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 3835 # What read queue length does an incoming req see 15711860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 2485 # What read queue length does an incoming req see 15811860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 1956 # What read queue length does an incoming req see 15911860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 1332 # What read queue length does an incoming req see 16011860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 1133 # What read queue length does an incoming req see 16111860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 952 # What read queue length does an incoming req see 16211860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 753 # What read queue length does an incoming req see 16311860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 214 # What read queue length does an incoming req see 16411860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 132 # What read queue length does an incoming req see 16511860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see 16611860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see 16711860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see 16811860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see 16911860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 1 # What read queue length does an incoming req see 17011353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 17110628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 17210628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 17310628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 17410628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 17510628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 17610628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 17710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 17810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 17910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 18010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 18110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 18210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 18310515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 18410515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 18510515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 18610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 18710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 18810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 18910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 19010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 19110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 19211860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 24179 # What write queue length does an incoming req see 19311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 28209 # What write queue length does an incoming req see 19411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 39999 # What write queue length does an incoming req see 19511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 46492 # What write queue length does an incoming req see 19611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 52355 # What write queue length does an incoming req see 19711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 57811 # What write queue length does an incoming req see 19811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 64510 # What write queue length does an incoming req see 19911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 71167 # What write queue length does an incoming req see 20011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 77564 # What write queue length does an incoming req see 20111860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 80217 # What write queue length does an incoming req see 20211860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 85971 # What write queue length does an incoming req see 20311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 89992 # What write queue length does an incoming req see 20411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 89616 # What write queue length does an incoming req see 20511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 91327 # What write queue length does an incoming req see 20611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 98798 # What write queue length does an incoming req see 20711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 107236 # What write queue length does an incoming req see 20811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 96475 # What write queue length does an incoming req see 20911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 90527 # What write queue length does an incoming req see 21011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 10742 # What write queue length does an incoming req see 21111860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 6106 # What write queue length does an incoming req see 21211860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 4571 # What write queue length does an incoming req see 21311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 3497 # What write queue length does an incoming req see 21411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 2697 # What write queue length does an incoming req see 21511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 2502 # What write queue length does an incoming req see 21611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 2142 # What write queue length does an incoming req see 21711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 1954 # What write queue length does an incoming req see 21811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 1797 # What write queue length does an incoming req see 21911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 1675 # What write queue length does an incoming req see 22011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 1702 # What write queue length does an incoming req see 22111860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 1596 # What write queue length does an incoming req see 22211860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 1489 # What write queue length does an incoming req see 22311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 1728 # What write queue length does an incoming req see 22411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 1697 # What write queue length does an incoming req see 22511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 1857 # What write queue length does an incoming req see 22611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 2065 # What write queue length does an incoming req see 22711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 2040 # What write queue length does an incoming req see 22811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 2043 # What write queue length does an incoming req see 22911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 2289 # What write queue length does an incoming req see 23011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 2323 # What write queue length does an incoming req see 23111860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 2551 # What write queue length does an incoming req see 23211860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 2701 # What write queue length does an incoming req see 23311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 3106 # What write queue length does an incoming req see 23411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 3300 # What write queue length does an incoming req see 23511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 3341 # What write queue length does an incoming req see 23611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 3948 # What write queue length does an incoming req see 23711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 4411 # What write queue length does an incoming req see 23811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 6171 # What write queue length does an incoming req see 23911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 25276 # What write queue length does an incoming req see 24011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 121442 # What write queue length does an incoming req see 24111860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 1170396 # Bytes accessed per row activation 24211860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 153.366156 # Bytes accessed per row activation 24311860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 102.854296 # Bytes accessed per row activation 24411860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 197.868960 # Bytes accessed per row activation 24511860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 748847 63.98% 63.98% # Bytes accessed per row activation 24611860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 241823 20.66% 84.64% # Bytes accessed per row activation 24711860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 67607 5.78% 90.42% # Bytes accessed per row activation 24811860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 29756 2.54% 92.96% # Bytes accessed per row activation 24911860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 24374 2.08% 95.05% # Bytes accessed per row activation 25011860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 14066 1.20% 96.25% # Bytes accessed per row activation 25111860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 9299 0.79% 97.04% # Bytes accessed per row activation 25211860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 7338 0.63% 97.67% # Bytes accessed per row activation 25311860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 27286 2.33% 100.00% # Bytes accessed per row activation 25411860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 1170396 # Bytes accessed per row activation 25511860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 74463 # Reads before turning the bus around for writes 25611860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 17.155890 # Reads before turning the bus around for writes 25711860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 20.196232 # Reads before turning the bus around for writes 25811860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-255 74449 99.98% 99.98% # Reads before turning the bus around for writes 25911860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::256-511 8 0.01% 99.99% # Reads before turning the bus around for writes 26011860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::512-767 3 0.00% 100.00% # Reads before turning the bus around for writes 26111860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::768-1023 2 0.00% 100.00% # Reads before turning the bus around for writes 26211860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::4352-4607 1 0.00% 100.00% # Reads before turning the bus around for writes 26311860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 74463 # Reads before turning the bus around for writes 26411860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 74463 # Writes before turning the bus around for reads 26511860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 20.509394 # Writes before turning the bus around for reads 26611860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 17.370303 # Writes before turning the bus around for reads 26711860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 552.030208 # Writes before turning the bus around for reads 26811860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::0-4095 74461 100.00% 100.00% # Writes before turning the bus around for reads 26911754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::40960-45055 1 0.00% 100.00% # Writes before turning the bus around for reads 27011754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::143360-147455 1 0.00% 100.00% # Writes before turning the bus around for reads 27111860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 74463 # Writes before turning the bus around for reads 27211860Sandreas.hansson@arm.comsystem.physmem.totQLat 79629370316 # Total ticks spent queuing 27311860Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 103582270316 # Total ticks spent from burst creation until serviced by the DRAM 27411860Sandreas.hansson@arm.comsystem.physmem.totBusLat 6387440000 # Total ticks spent in databus transfers 27511860Sandreas.hansson@arm.comsystem.physmem.avgQLat 62332.77 # Average queueing delay per DRAM burst 27610515SAli.Saidi@ARM.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 27711860Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 81082.77 # Average memory access latency per DRAM burst 27811860Sandreas.hansson@arm.comsystem.physmem.avgRdBW 1.73 # Average DRAM read bandwidth in MiByte/s 27911860Sandreas.hansson@arm.comsystem.physmem.avgWrBW 2.06 # Average achieved write bandwidth in MiByte/s 28011860Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 1.73 # Average system read bandwidth in MiByte/s 28111860Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 2.06 # Average system write bandwidth in MiByte/s 28210515SAli.Saidi@ARM.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 28311754Sandreas.hansson@arm.comsystem.physmem.busUtil 0.03 # Data bus utilization in percentage 28411353Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 28511860Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 28611860Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing 28711754Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 25.79 # Average write queue length when enqueuing 28811860Sandreas.hansson@arm.comsystem.physmem.readRowHits 958718 # Number of row buffer hits during reads 28911860Sandreas.hansson@arm.comsystem.physmem.writeRowHits 675564 # Number of row buffer hits during writes 29011860Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 75.05 # Row buffer hit rate for reads 29111860Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 44.23 # Row buffer hit rate for writes 29211860Sandreas.hansson@arm.comsystem.physmem.avgGap 16863400.13 # Average gap between requests 29311860Sandreas.hansson@arm.comsystem.physmem.pageHitRate 58.27 # Row buffer hit rate, read and write combined 29411860Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 4260723600 # Energy for activate commands per rank (pJ) 29511860Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 2264628300 # Energy for precharge commands per rank (pJ) 29611860Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 4618823160 # Energy for read commands per rank (pJ) 29711860Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 4008913020 # Energy for write commands per rank (pJ) 29811860Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 30164687280.000008 # Energy for refresh commands per rank (pJ) 29911860Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 41855751510 # Energy for active background per rank (pJ) 30011860Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 1419463680 # Energy for precharge background per rank (pJ) 30111860Sandreas.hansson@arm.comsystem.physmem_0.actPowerDownEnergy 63813765750 # Energy for active power-down per rank (pJ) 30211860Sandreas.hansson@arm.comsystem.physmem_0.prePowerDownEnergy 36794590560 # Energy for precharge power-down per rank (pJ) 30311860Sandreas.hansson@arm.comsystem.physmem_0.selfRefreshEnergy 11286440815140 # Energy for self refresh per rank (pJ) 30411860Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 11475654576000 # Total energy per rank (pJ) 30511860Sandreas.hansson@arm.comsystem.physmem_0.averagePower 242.399417 # Core power per rank (mW) 30611860Sandreas.hansson@arm.comsystem.physmem_0.totalIdleTime 47246408217619 # Total Idle time Per DRAM Rank 30711860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 2341242543 # Time in different power states 30811860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 12803196000 # Time in different power states 30911860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::SREF 47010648524500 # Time in different power states 31011860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 95818811721 # Time in different power states 31111860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 80368685838 # Time in different power states 31211860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 139942793398 # Time in different power states 31311860Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 4095910980 # Energy for activate commands per rank (pJ) 31411860Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 2177024520 # Energy for precharge commands per rank (pJ) 31511860Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 4502441160 # Energy for read commands per rank (pJ) 31611860Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 3963024000 # Energy for write commands per rank (pJ) 31711860Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 30680370240.000008 # Energy for refresh commands per rank (pJ) 31811860Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 42163353720 # Energy for active background per rank (pJ) 31911860Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 1422051360 # Energy for precharge background per rank (pJ) 32011860Sandreas.hansson@arm.comsystem.physmem_1.actPowerDownEnergy 64060335210 # Energy for active power-down per rank (pJ) 32111860Sandreas.hansson@arm.comsystem.physmem_1.prePowerDownEnergy 38109219360 # Energy for precharge power-down per rank (pJ) 32211860Sandreas.hansson@arm.comsystem.physmem_1.selfRefreshEnergy 11285470021935 # Energy for self refresh per rank (pJ) 32311860Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 11476656465255 # Total energy per rank (pJ) 32411860Sandreas.hansson@arm.comsystem.physmem_1.averagePower 242.420579 # Core power per rank (mW) 32511860Sandreas.hansson@arm.comsystem.physmem_1.totalIdleTime 47245728134436 # Total Idle time Per DRAM Rank 32611860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 2323672783 # Time in different power states 32711860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 13022950000 # Time in different power states 32811860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::SREF 47006002235750 # Time in different power states 32911860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 99242546502 # Time in different power states 33011860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 80848444531 # Time in different power states 33111860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 140483404434 # Time in different power states 33211860Sandreas.hansson@arm.comsystem.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 33311201Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory 33410576Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 33510576Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory 33610576Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 33711201Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::total 556 # Number of bytes read from this memory 33811201Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_inst_read::cpu0.inst 368 # Number of instructions bytes read from this memory 33910576Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory 34011201Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory 34111201Sandreas.hansson@arm.comsystem.realview.nvmem.num_reads::cpu0.inst 23 # Number of read requests responded to by this memory 34210576Sandreas.hansson@arm.comsystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 34310576Sandreas.hansson@arm.comsystem.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory 34410576Sandreas.hansson@arm.comsystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 34511201Sandreas.hansson@arm.comsystem.realview.nvmem.num_reads::total 38 # Number of read requests responded to by this memory 34610576Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) 34710576Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 34810576Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::cpu1.inst 3 # Total read bandwidth from this memory (bytes/s) 34910576Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 35010576Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::total 12 # Total read bandwidth from this memory (bytes/s) 35110576Sandreas.hansson@arm.comsystem.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) 35210576Sandreas.hansson@arm.comsystem.realview.nvmem.bw_inst_read::cpu1.inst 3 # Instruction read bandwidth from this memory (bytes/s) 35310576Sandreas.hansson@arm.comsystem.realview.nvmem.bw_inst_read::total 11 # Instruction read bandwidth from this memory (bytes/s) 35410576Sandreas.hansson@arm.comsystem.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) 35510576Sandreas.hansson@arm.comsystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 35610576Sandreas.hansson@arm.comsystem.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s) 35710576Sandreas.hansson@arm.comsystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 35810576Sandreas.hansson@arm.comsystem.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s) 35911860Sandreas.hansson@arm.comsystem.realview.vram.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 36011860Sandreas.hansson@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 36111860Sandreas.hansson@arm.comsystem.bridge.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 36210576Sandreas.hansson@arm.comsystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 36310576Sandreas.hansson@arm.comsystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 36410576Sandreas.hansson@arm.comsystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 36510576Sandreas.hansson@arm.comsystem.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 36610576Sandreas.hansson@arm.comsystem.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 36710576Sandreas.hansson@arm.comsystem.cf0.dma_write_txs 1670 # Number of DMA write transactions. 36811860Sandreas.hansson@arm.comsystem.cpu0.branchPred.lookups 135771616 # Number of BP lookups 36911860Sandreas.hansson@arm.comsystem.cpu0.branchPred.condPredicted 86347947 # Number of conditional branches predicted 37011860Sandreas.hansson@arm.comsystem.cpu0.branchPred.condIncorrect 6838936 # Number of conditional branches incorrect 37111860Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBLookups 91129477 # Number of BTB lookups 37211860Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBHits 54316721 # Number of BTB hits 37310576Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 37411860Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBHitPct 59.603899 # BTB Hit Percentage 37511860Sandreas.hansson@arm.comsystem.cpu0.branchPred.usedRAS 20002366 # Number of times the RAS was used to get a target. 37611860Sandreas.hansson@arm.comsystem.cpu0.branchPred.RASInCorrect 187416 # Number of incorrect RAS predictions. 37711860Sandreas.hansson@arm.comsystem.cpu0.branchPred.indirectLookups 4394152 # Number of indirect predictor lookups. 37811860Sandreas.hansson@arm.comsystem.cpu0.branchPred.indirectHits 2878401 # Number of indirect target hits. 37911860Sandreas.hansson@arm.comsystem.cpu0.branchPred.indirectMisses 1515751 # Number of indirect misses. 38011860Sandreas.hansson@arm.comsystem.cpu0.branchPredindirectMispredicted 382217 # Number of mispredicted indirect branches. 38110515SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 38211860Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 38310628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 38410628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 38510628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 38610628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 38710628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 38810628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 38910628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 39010628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 39110576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 39210576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 39310576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 39410576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 39510576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 39610576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 39710576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 39810576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 39910576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 40010576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 40110576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 40210576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 40310576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 40410576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 40510576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 40610576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 40710576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 40810576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 40910576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 41010576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 41110576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 41211860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 41311860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walks 656993 # Table walker walks requested 41411860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLong 656993 # Table walker walks initiated with long descriptors 41511860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level2 15295 # Level at which table walker walks with long descriptors terminate 41611860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level3 109934 # Level at which table walker walks with long descriptors terminate 41711860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksSquashedBefore 315620 # Table walks squashed before starting 41811860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 341373 # Table walker wait (enqueue to first request) latency 41911860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::mean 2464.513889 # Table walker wait (enqueue to first request) latency 42011860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::stdev 14057.964276 # Table walker wait (enqueue to first request) latency 42111860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0-65535 338378 99.12% 99.12% # Table walker wait (enqueue to first request) latency 42211860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::65536-131071 2127 0.62% 99.75% # Table walker wait (enqueue to first request) latency 42311860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::131072-196607 591 0.17% 99.92% # Table walker wait (enqueue to first request) latency 42411860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::196608-262143 168 0.05% 99.97% # Table walker wait (enqueue to first request) latency 42511860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::262144-327679 44 0.01% 99.98% # Table walker wait (enqueue to first request) latency 42611860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::327680-393215 50 0.01% 100.00% # Table walker wait (enqueue to first request) latency 42711860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::393216-458751 9 0.00% 100.00% # Table walker wait (enqueue to first request) latency 42811860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 42911860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::589824-655359 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency 43011860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 43111860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 341373 # Table walker wait (enqueue to first request) latency 43211860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::samples 358442 # Table walker service (enqueue to completion) latency 43311860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::mean 21996.103972 # Table walker service (enqueue to completion) latency 43411860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::gmean 18865.832829 # Table walker service (enqueue to completion) latency 43511860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::stdev 18729.819330 # Table walker service (enqueue to completion) latency 43611860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::0-65535 353579 98.64% 98.64% # Table walker service (enqueue to completion) latency 43711860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::65536-131071 3217 0.90% 99.54% # Table walker service (enqueue to completion) latency 43811860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::131072-196607 596 0.17% 99.71% # Table walker service (enqueue to completion) latency 43911860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::196608-262143 697 0.19% 99.90% # Table walker service (enqueue to completion) latency 44011860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::262144-327679 228 0.06% 99.97% # Table walker service (enqueue to completion) latency 44111860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::327680-393215 58 0.02% 99.98% # Table walker service (enqueue to completion) latency 44211860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::393216-458751 45 0.01% 99.99% # Table walker service (enqueue to completion) latency 44311860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::458752-524287 6 0.00% 100.00% # Table walker service (enqueue to completion) latency 44411860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 44511860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::589824-655359 12 0.00% 100.00% # Table walker service (enqueue to completion) latency 44611860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 44711860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::total 358442 # Table walker service (enqueue to completion) latency 44811860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::samples 470936013252 # Table walker pending requests distribution 44911860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::mean 0.670912 # Table walker pending requests distribution 45011860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::stdev 0.545830 # Table walker pending requests distribution 45111860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::0-1 469324214752 99.66% 99.66% # Table walker pending requests distribution 45211860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::2-3 904884000 0.19% 99.85% # Table walker pending requests distribution 45311860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::4-5 330855500 0.07% 99.92% # Table walker pending requests distribution 45411860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::6-7 151555000 0.03% 99.95% # Table walker pending requests distribution 45511860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::8-9 116006500 0.02% 99.98% # Table walker pending requests distribution 45611860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::10-11 57420000 0.01% 99.99% # Table walker pending requests distribution 45711860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::12-13 24613500 0.01% 99.99% # Table walker pending requests distribution 45811860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::14-15 25389500 0.01% 100.00% # Table walker pending requests distribution 45911860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::16-17 1013500 0.00% 100.00% # Table walker pending requests distribution 46011860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::18-19 61000 0.00% 100.00% # Table walker pending requests distribution 46111860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::total 470936013252 # Table walker pending requests distribution 46211860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 109934 87.79% 87.79% # Table walker page sizes translated 46311860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::2M 15295 12.21% 100.00% # Table walker page sizes translated 46411860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 125229 # Table walker page sizes translated 46511860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 656993 # Table walker requests started/completed, data/inst 46610628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 46711860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 656993 # Table walker requests started/completed, data/inst 46811860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 125229 # Table walker requests started/completed, data/inst 46910628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 47011860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 125229 # Table walker requests started/completed, data/inst 47111860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 782222 # Table walker requests started/completed, data/inst 47210576Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_hits 0 # ITB inst hits 47310576Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_misses 0 # ITB inst misses 47411860Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 107772870 # DTB read hits 47511860Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 484010 # DTB read misses 47611860Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 87417439 # DTB write hits 47711860Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 172983 # DTB write misses 47811860Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed 47910576Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 48011860Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 47990 # Number of times TLB was flushed by MVA & ASID 48111860Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_asid 1104 # Number of times TLB was flushed by ASID 48211860Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_entries 44511 # Number of entries that have been flushed from TLB 48311860Sandreas.hansson@arm.comsystem.cpu0.dtb.align_faults 282 # Number of TLB faults due to alignment restrictions 48411860Sandreas.hansson@arm.comsystem.cpu0.dtb.prefetch_faults 7018 # Number of TLB faults due to prefetch 48510576Sandreas.hansson@arm.comsystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 48611860Sandreas.hansson@arm.comsystem.cpu0.dtb.perms_faults 39566 # Number of TLB faults due to permissions restrictions 48711860Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 108256880 # DTB read accesses 48811860Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 87590422 # DTB write accesses 48910576Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 49011860Sandreas.hansson@arm.comsystem.cpu0.dtb.hits 195190309 # DTB hits 49111860Sandreas.hansson@arm.comsystem.cpu0.dtb.misses 656993 # DTB misses 49211860Sandreas.hansson@arm.comsystem.cpu0.dtb.accesses 195847302 # DTB accesses 49311860Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 49410628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 49510628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 49610628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 49710628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 49810628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 49910628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 50010628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 50110628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 50210576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 50310576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 50410576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 50510576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 50610576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 50710576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 50810576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 50910576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 51010576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 51110576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 51210576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 51310576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 51410576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 51510576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 51610576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 51710576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 51810576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 51910576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 52010576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 52110576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 52210576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 52311860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 52411860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walks 88518 # Table walker walks requested 52511860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLong 88518 # Table walker walks initiated with long descriptors 52611860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level2 982 # Level at which table walker walks with long descriptors terminate 52711860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level3 60760 # Level at which table walker walks with long descriptors terminate 52811860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksSquashedBefore 10909 # Table walks squashed before starting 52911860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 77609 # Table walker wait (enqueue to first request) latency 53011860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::mean 1509.006687 # Table walker wait (enqueue to first request) latency 53111860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::stdev 11301.495781 # Table walker wait (enqueue to first request) latency 53211860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::0-65535 77034 99.26% 99.26% # Table walker wait (enqueue to first request) latency 53311860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::65536-131071 519 0.67% 99.93% # Table walker wait (enqueue to first request) latency 53411860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::131072-196607 33 0.04% 99.97% # Table walker wait (enqueue to first request) latency 53511860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::196608-262143 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency 53611860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::262144-327679 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency 53711860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::327680-393215 8 0.01% 100.00% # Table walker wait (enqueue to first request) latency 53811860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 53911860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 54011860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 77609 # Table walker wait (enqueue to first request) latency 54111860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::samples 72651 # Table walker service (enqueue to completion) latency 54211860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::mean 27149.240891 # Table walker service (enqueue to completion) latency 54311860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::gmean 23393.498423 # Table walker service (enqueue to completion) latency 54411860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::stdev 24986.363412 # Table walker service (enqueue to completion) latency 54511860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::0-65535 70103 96.49% 96.49% # Table walker service (enqueue to completion) latency 54611860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::65536-131071 1723 2.37% 98.86% # Table walker service (enqueue to completion) latency 54711860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::131072-196607 517 0.71% 99.58% # Table walker service (enqueue to completion) latency 54811860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::196608-262143 199 0.27% 99.85% # Table walker service (enqueue to completion) latency 54911860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::262144-327679 51 0.07% 99.92% # Table walker service (enqueue to completion) latency 55011860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::327680-393215 35 0.05% 99.97% # Table walker service (enqueue to completion) latency 55111860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.98% # Table walker service (enqueue to completion) latency 55211860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.98% # Table walker service (enqueue to completion) latency 55311860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::524288-589823 7 0.01% 99.99% # Table walker service (enqueue to completion) latency 55411860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::589824-655359 6 0.01% 100.00% # Table walker service (enqueue to completion) latency 55511860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::total 72651 # Table walker service (enqueue to completion) latency 55611860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::samples 367854316648 # Table walker pending requests distribution 55711860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::mean 0.912736 # Table walker pending requests distribution 55811860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::stdev 0.282646 # Table walker pending requests distribution 55911860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::0 32141827252 8.74% 8.74% # Table walker pending requests distribution 56011860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::1 335673383896 91.25% 99.99% # Table walker pending requests distribution 56111860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::2 36841000 0.01% 100.00% # Table walker pending requests distribution 56211860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::3 2085000 0.00% 100.00% # Table walker pending requests distribution 56311860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::4 179500 0.00% 100.00% # Table walker pending requests distribution 56411860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::total 367854316648 # Table walker pending requests distribution 56511860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 60760 98.41% 98.41% # Table walker page sizes translated 56611860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::2M 982 1.59% 100.00% # Table walker page sizes translated 56711860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 61742 # Table walker page sizes translated 56810628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 56911860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 88518 # Table walker requests started/completed, data/inst 57011860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 88518 # Table walker requests started/completed, data/inst 57110628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 57211860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 61742 # Table walker requests started/completed, data/inst 57311860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 61742 # Table walker requests started/completed, data/inst 57411860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 150260 # Table walker requests started/completed, data/inst 57511860Sandreas.hansson@arm.comsystem.cpu0.itb.inst_hits 209275517 # ITB inst hits 57611860Sandreas.hansson@arm.comsystem.cpu0.itb.inst_misses 88518 # ITB inst misses 57710576Sandreas.hansson@arm.comsystem.cpu0.itb.read_hits 0 # DTB read hits 57810576Sandreas.hansson@arm.comsystem.cpu0.itb.read_misses 0 # DTB read misses 57910576Sandreas.hansson@arm.comsystem.cpu0.itb.write_hits 0 # DTB write hits 58010576Sandreas.hansson@arm.comsystem.cpu0.itb.write_misses 0 # DTB write misses 58111860Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed 58210576Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 58311860Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 47990 # Number of times TLB was flushed by MVA & ASID 58411860Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_asid 1104 # Number of times TLB was flushed by ASID 58511860Sandreas.hansson@arm.comsystem.cpu0.itb.flush_entries 31869 # Number of entries that have been flushed from TLB 58610576Sandreas.hansson@arm.comsystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 58710576Sandreas.hansson@arm.comsystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 58810576Sandreas.hansson@arm.comsystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 58911860Sandreas.hansson@arm.comsystem.cpu0.itb.perms_faults 214657 # Number of TLB faults due to permissions restrictions 59010576Sandreas.hansson@arm.comsystem.cpu0.itb.read_accesses 0 # DTB read accesses 59110576Sandreas.hansson@arm.comsystem.cpu0.itb.write_accesses 0 # DTB write accesses 59211860Sandreas.hansson@arm.comsystem.cpu0.itb.inst_accesses 209364035 # ITB inst accesses 59311860Sandreas.hansson@arm.comsystem.cpu0.itb.hits 209275517 # DTB hits 59411860Sandreas.hansson@arm.comsystem.cpu0.itb.misses 88518 # DTB misses 59511860Sandreas.hansson@arm.comsystem.cpu0.itb.accesses 209364035 # DTB accesses 59611860Sandreas.hansson@arm.comsystem.cpu0.numPwrStateTransitions 11060 # Number of power state transitions 59711860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::samples 5530 # Distribution of time spent in the clock gated state 59811860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::mean 8500198165.069259 # Distribution of time spent in the clock gated state 59911860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::stdev 152149510782.295166 # Distribution of time spent in the clock gated state 60011860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::underflows 4198 75.91% 75.91% # Distribution of time spent in the clock gated state 60111860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::1000-5e+10 1307 23.63% 99.55% # Distribution of time spent in the clock gated state 60211860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::5e+10-1e+11 6 0.11% 99.66% # Distribution of time spent in the clock gated state 60311860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.67% # Distribution of time spent in the clock gated state 60411860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 2 0.04% 99.71% # Distribution of time spent in the clock gated state 60511860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.02% 99.73% # Distribution of time spent in the clock gated state 60611860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 1 0.02% 99.75% # Distribution of time spent in the clock gated state 60711860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.02% 99.76% # Distribution of time spent in the clock gated state 60811860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.02% 99.78% # Distribution of time spent in the clock gated state 60911860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::overflows 12 0.22% 100.00% # Distribution of time spent in the clock gated state 61011860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state 61111860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::max_value 6914082541000 # Distribution of time spent in the clock gated state 61211860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::total 5530 # Distribution of time spent in the clock gated state 61311860Sandreas.hansson@arm.comsystem.cpu0.pwrStateResidencyTicks::ON 335827401167 # Cumulative time (in ticks) in various power states 61411860Sandreas.hansson@arm.comsystem.cpu0.pwrStateResidencyTicks::CLK_GATED 47006095852833 # Cumulative time (in ticks) in various power states 61511860Sandreas.hansson@arm.comsystem.cpu0.numCycles 671656145 # number of cpu cycles simulated 61610576Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 61710576Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 61811860Sandreas.hansson@arm.comsystem.cpu0.fetch.icacheStallCycles 89746186 # Number of cycles fetch is stalled on an Icache miss 61911860Sandreas.hansson@arm.comsystem.cpu0.fetch.Insts 605326172 # Number of instructions fetch has processed 62011860Sandreas.hansson@arm.comsystem.cpu0.fetch.Branches 135771616 # Number of branches that fetch encountered 62111860Sandreas.hansson@arm.comsystem.cpu0.fetch.predictedBranches 77197488 # Number of branches that fetch has predicted taken 62211860Sandreas.hansson@arm.comsystem.cpu0.fetch.Cycles 539879458 # Number of cycles fetch has run and was not squashing or blocked 62311860Sandreas.hansson@arm.comsystem.cpu0.fetch.SquashCycles 14767666 # Number of cycles fetch has spent squashing 62411860Sandreas.hansson@arm.comsystem.cpu0.fetch.TlbCycles 2125862 # Number of cycles fetch has spent waiting for tlb 62511860Sandreas.hansson@arm.comsystem.cpu0.fetch.MiscStallCycles 314132 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 62611860Sandreas.hansson@arm.comsystem.cpu0.fetch.PendingTrapStallCycles 6298223 # Number of stall cycles due to pending traps 62711860Sandreas.hansson@arm.comsystem.cpu0.fetch.PendingQuiesceStallCycles 772099 # Number of stall cycles due to pending quiesce instructions 62811860Sandreas.hansson@arm.comsystem.cpu0.fetch.IcacheWaitRetryStallCycles 851881 # Number of stall cycles due to full MSHR 62911860Sandreas.hansson@arm.comsystem.cpu0.fetch.CacheLines 209041727 # Number of cache lines fetched 63011860Sandreas.hansson@arm.comsystem.cpu0.fetch.IcacheSquashes 1674502 # Number of outstanding Icache misses that were squashed 63111860Sandreas.hansson@arm.comsystem.cpu0.fetch.ItlbSquashes 29298 # Number of outstanding ITLB misses that were squashed 63211860Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::samples 647371674 # Number of instructions fetched each cycle (Total) 63311860Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::mean 1.105525 # Number of instructions fetched each cycle (Total) 63411860Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::stdev 1.248840 # Number of instructions fetched each cycle (Total) 63510576Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 63611860Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::0 308576951 47.67% 47.67% # Number of instructions fetched each cycle (Total) 63711860Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::1 127594651 19.71% 67.38% # Number of instructions fetched each cycle (Total) 63811860Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::2 45508982 7.03% 74.41% # Number of instructions fetched each cycle (Total) 63911860Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::3 165691090 25.59% 100.00% # Number of instructions fetched each cycle (Total) 64010576Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 64110576Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 64210576Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 64311860Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::total 647371674 # Number of instructions fetched each cycle (Total) 64411860Sandreas.hansson@arm.comsystem.cpu0.fetch.branchRate 0.202145 # Number of branch fetches per cycle 64511860Sandreas.hansson@arm.comsystem.cpu0.fetch.rate 0.901244 # Number of inst fetches per cycle 64611860Sandreas.hansson@arm.comsystem.cpu0.decode.IdleCycles 102332613 # Number of cycles decode is idle 64711860Sandreas.hansson@arm.comsystem.cpu0.decode.BlockedCycles 273941666 # Number of cycles decode is blocked 64811860Sandreas.hansson@arm.comsystem.cpu0.decode.RunCycles 237936691 # Number of cycles decode is running 64911860Sandreas.hansson@arm.comsystem.cpu0.decode.UnblockCycles 27831297 # Number of cycles decode is unblocking 65011860Sandreas.hansson@arm.comsystem.cpu0.decode.SquashCycles 5329407 # Number of cycles decode is squashing 65111860Sandreas.hansson@arm.comsystem.cpu0.decode.BranchResolved 50359670 # Number of times decode resolved a branch 65211860Sandreas.hansson@arm.comsystem.cpu0.decode.BranchMispred 2095113 # Number of times decode detected a branch misprediction 65311860Sandreas.hansson@arm.comsystem.cpu0.decode.DecodedInsts 630187004 # Number of instructions handled by decode 65411860Sandreas.hansson@arm.comsystem.cpu0.decode.SquashedInsts 23557218 # Number of squashed instructions handled by decode 65511860Sandreas.hansson@arm.comsystem.cpu0.rename.SquashCycles 5329407 # Number of cycles rename is squashing 65611860Sandreas.hansson@arm.comsystem.cpu0.rename.IdleCycles 133079950 # Number of cycles rename is idle 65711860Sandreas.hansson@arm.comsystem.cpu0.rename.BlockCycles 61214716 # Number of cycles rename is blocking 65811860Sandreas.hansson@arm.comsystem.cpu0.rename.serializeStallCycles 153180346 # count of cycles rename stalled for serializing inst 65911860Sandreas.hansson@arm.comsystem.cpu0.rename.RunCycles 234286149 # Number of cycles rename is running 66011860Sandreas.hansson@arm.comsystem.cpu0.rename.UnblockCycles 60281106 # Number of cycles rename is unblocking 66111860Sandreas.hansson@arm.comsystem.cpu0.rename.RenamedInsts 612391061 # Number of instructions processed by rename 66211860Sandreas.hansson@arm.comsystem.cpu0.rename.SquashedInsts 6345537 # Number of squashed instructions processed by rename 66311860Sandreas.hansson@arm.comsystem.cpu0.rename.ROBFullEvents 11623022 # Number of times rename has blocked due to ROB full 66411860Sandreas.hansson@arm.comsystem.cpu0.rename.IQFullEvents 442390 # Number of times rename has blocked due to IQ full 66511860Sandreas.hansson@arm.comsystem.cpu0.rename.LQFullEvents 950471 # Number of times rename has blocked due to LQ full 66611860Sandreas.hansson@arm.comsystem.cpu0.rename.SQFullEvents 35105207 # Number of times rename has blocked due to SQ full 66711860Sandreas.hansson@arm.comsystem.cpu0.rename.FullRegisterEvents 13004 # Number of times there has been no free registers 66811860Sandreas.hansson@arm.comsystem.cpu0.rename.RenamedOperands 561787552 # Number of destination operands rename has renamed 66911860Sandreas.hansson@arm.comsystem.cpu0.rename.RenameLookups 866106072 # Number of register rename lookups that rename has made 67011860Sandreas.hansson@arm.comsystem.cpu0.rename.int_rename_lookups 720689595 # Number of integer rename lookups 67111860Sandreas.hansson@arm.comsystem.cpu0.rename.fp_rename_lookups 706575 # Number of floating rename lookups 67211860Sandreas.hansson@arm.comsystem.cpu0.rename.CommittedMaps 502207885 # Number of HB maps that are committed 67311860Sandreas.hansson@arm.comsystem.cpu0.rename.UndoneMaps 59579653 # Number of HB maps that are undone due to squashing 67411860Sandreas.hansson@arm.comsystem.cpu0.rename.serializingInsts 6816633 # count of serializing insts renamed 67511860Sandreas.hansson@arm.comsystem.cpu0.rename.tempSerializingInsts 4684361 # count of temporary serializing insts renamed 67611860Sandreas.hansson@arm.comsystem.cpu0.rename.skidInsts 58564314 # count of insts added to the skid buffer 67711860Sandreas.hansson@arm.comsystem.cpu0.memDep0.insertedLoads 107690406 # Number of loads inserted to the mem dependence unit. 67811860Sandreas.hansson@arm.comsystem.cpu0.memDep0.insertedStores 90791382 # Number of stores inserted to the mem dependence unit. 67911860Sandreas.hansson@arm.comsystem.cpu0.memDep0.conflictingLoads 10221267 # Number of conflicting loads. 68011860Sandreas.hansson@arm.comsystem.cpu0.memDep0.conflictingStores 8541253 # Number of conflicting stores. 68111860Sandreas.hansson@arm.comsystem.cpu0.iq.iqInstsAdded 598417989 # Number of instructions added to the IQ (excludes non-spec) 68211860Sandreas.hansson@arm.comsystem.cpu0.iq.iqNonSpecInstsAdded 7027379 # Number of non-speculative instructions added to the IQ 68311860Sandreas.hansson@arm.comsystem.cpu0.iq.iqInstsIssued 594218555 # Number of instructions issued 68411860Sandreas.hansson@arm.comsystem.cpu0.iq.iqSquashedInstsIssued 2775784 # Number of squashed instructions issued 68511860Sandreas.hansson@arm.comsystem.cpu0.iq.iqSquashedInstsExamined 55969109 # Number of squashed instructions iterated over during squash; mainly for profiling 68611860Sandreas.hansson@arm.comsystem.cpu0.iq.iqSquashedOperandsExamined 36418491 # Number of squashed operands that are examined and possibly removed from graph 68711860Sandreas.hansson@arm.comsystem.cpu0.iq.iqSquashedNonSpecRemoved 281604 # Number of squashed non-spec instructions that were removed 68811860Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::samples 647371674 # Number of insts issued each cycle 68911860Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::mean 0.917894 # Number of insts issued each cycle 69011860Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::stdev 1.123620 # Number of insts issued each cycle 69110576Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 69211860Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::0 341377364 52.73% 52.73% # Number of insts issued each cycle 69311860Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::1 105270736 16.26% 68.99% # Number of insts issued each cycle 69411860Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::2 121758490 18.81% 87.80% # Number of insts issued each cycle 69511860Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::3 70435170 10.88% 98.68% # Number of insts issued each cycle 69611860Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::4 8524242 1.32% 100.00% # Number of insts issued each cycle 69711860Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::5 5671 0.00% 100.00% # Number of insts issued each cycle 69811860Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::6 1 0.00% 100.00% # Number of insts issued each cycle 69910576Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 70010576Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 70110576Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 70210576Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 70311860Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle 70411860Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::total 647371674 # Number of insts issued each cycle 70510576Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 70611860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::IntAlu 65687551 45.22% 45.22% # attempts to use FU when none available 70711860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::IntMult 64582 0.04% 45.27% # attempts to use FU when none available 70811860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::IntDiv 15638 0.01% 45.28% # attempts to use FU when none available 70911860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.28% # attempts to use FU when none available 71011860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.28% # attempts to use FU when none available 71111860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.28% # attempts to use FU when none available 71211860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatMult 0 0.00% 45.28% # attempts to use FU when none available 71311860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 45.28% # attempts to use FU when none available 71411860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.28% # attempts to use FU when none available 71511860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatMisc 12 0.00% 45.28% # attempts to use FU when none available 71611860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.28% # attempts to use FU when none available 71711860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.28% # attempts to use FU when none available 71811860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.28% # attempts to use FU when none available 71911860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.28% # attempts to use FU when none available 72011860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.28% # attempts to use FU when none available 72111860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.28% # attempts to use FU when none available 72211860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.28% # attempts to use FU when none available 72311860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdMult 0 0.00% 45.28% # attempts to use FU when none available 72411860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.28% # attempts to use FU when none available 72511860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdShift 0 0.00% 45.28% # attempts to use FU when none available 72611860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.28% # attempts to use FU when none available 72711860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.28% # attempts to use FU when none available 72811860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.28% # attempts to use FU when none available 72911860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.28% # attempts to use FU when none available 73011860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.28% # attempts to use FU when none available 73111860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.28% # attempts to use FU when none available 73211860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.28% # attempts to use FU when none available 73311860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 45.28% # attempts to use FU when none available 73411860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.28% # attempts to use FU when none available 73511860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.28% # attempts to use FU when none available 73611860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.28% # attempts to use FU when none available 73711860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::MemRead 38738584 26.67% 71.95% # attempts to use FU when none available 73811860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::MemWrite 40389693 27.81% 99.76% # attempts to use FU when none available 73911860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatMemRead 34528 0.02% 99.78% # attempts to use FU when none available 74011860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatMemWrite 315988 0.22% 100.00% # attempts to use FU when none available 74110576Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 74210576Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 74311860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::No_OpClass 70 0.00% 0.00% # Type of FU issued 74411860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::IntAlu 392733469 66.09% 66.09% # Type of FU issued 74511860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::IntMult 1547002 0.26% 66.35% # Type of FU issued 74611860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::IntDiv 82083 0.01% 66.37% # Type of FU issued 74711860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatAdd 53 0.00% 66.37% # Type of FU issued 74811860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatCmp 15 0.00% 66.37% # Type of FU issued 74911860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatCvt 25 0.00% 66.37% # Type of FU issued 75011860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.37% # Type of FU issued 75111860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 66.37% # Type of FU issued 75211860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.37% # Type of FU issued 75311860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatMisc 42153 0.01% 66.37% # Type of FU issued 75411860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.37% # Type of FU issued 75511860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdAdd 2 0.00% 66.37% # Type of FU issued 75611860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.37% # Type of FU issued 75711860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.37% # Type of FU issued 75811860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.37% # Type of FU issued 75911860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.37% # Type of FU issued 76011860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.37% # Type of FU issued 76111860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.37% # Type of FU issued 76211860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.37% # Type of FU issued 76311860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.37% # Type of FU issued 76411860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.37% # Type of FU issued 76511860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.37% # Type of FU issued 76611860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.37% # Type of FU issued 76711860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.37% # Type of FU issued 76811860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.37% # Type of FU issued 76911860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.37% # Type of FU issued 77011860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.37% # Type of FU issued 77111860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.37% # Type of FU issued 77211860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.37% # Type of FU issued 77311860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.37% # Type of FU issued 77411860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.37% # Type of FU issued 77511860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::MemRead 111068257 18.69% 85.07% # Type of FU issued 77611860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::MemWrite 88363067 14.87% 99.94% # Type of FU issued 77711860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatMemRead 53874 0.01% 99.94% # Type of FU issued 77811860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatMemWrite 328485 0.06% 100.00% # Type of FU issued 77910576Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 78010576Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 78111860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::total 594218555 # Type of FU issued 78211860Sandreas.hansson@arm.comsystem.cpu0.iq.rate 0.884706 # Inst issue rate 78311860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_busy_cnt 145246576 # FU busy when requested 78411860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_busy_rate 0.244433 # FU busy rate (busy events/executed inst) 78511860Sandreas.hansson@arm.comsystem.cpu0.iq.int_inst_queue_reads 1982627676 # Number of integer instruction queue reads 78611860Sandreas.hansson@arm.comsystem.cpu0.iq.int_inst_queue_writes 661129837 # Number of integer instruction queue writes 78711860Sandreas.hansson@arm.comsystem.cpu0.iq.int_inst_queue_wakeup_accesses 575942513 # Number of integer instruction queue wakeup accesses 78811860Sandreas.hansson@arm.comsystem.cpu0.iq.fp_inst_queue_reads 1203467 # Number of floating instruction queue reads 78911860Sandreas.hansson@arm.comsystem.cpu0.iq.fp_inst_queue_writes 445947 # Number of floating instruction queue writes 79011860Sandreas.hansson@arm.comsystem.cpu0.iq.fp_inst_queue_wakeup_accesses 420205 # Number of floating instruction queue wakeup accesses 79111860Sandreas.hansson@arm.comsystem.cpu0.iq.int_alu_accesses 738689926 # Number of integer alu accesses 79211860Sandreas.hansson@arm.comsystem.cpu0.iq.fp_alu_accesses 775135 # Number of floating point alu accesses 79311860Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.forwLoads 2992085 # Number of loads that had data forwarded from stores 79410576Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 79511860Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.squashedLoads 13179956 # Number of loads squashed 79611860Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.ignoredResponses 18072 # Number of memory responses ignored because the instruction is squashed 79711860Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.memOrderViolation 162311 # Number of memory ordering violations 79811860Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.squashedStores 5715015 # Number of stores squashed 79910576Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 80010576Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 80111860Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.rescheduledLoads 3005258 # Number of loads that were rescheduled 80211860Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.cacheBlocked 4976098 # Number of times an access to memory failed due to the cache being blocked 80310576Sandreas.hansson@arm.comsystem.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 80411860Sandreas.hansson@arm.comsystem.cpu0.iew.iewSquashCycles 5329407 # Number of cycles IEW is squashing 80511860Sandreas.hansson@arm.comsystem.cpu0.iew.iewBlockCycles 8694006 # Number of cycles IEW is blocking 80611860Sandreas.hansson@arm.comsystem.cpu0.iew.iewUnblockCycles 1907824 # Number of cycles IEW is unblocking 80711860Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispatchedInsts 605581185 # Number of instructions dispatched to IQ 80810576Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 80911860Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispLoadInsts 107690406 # Number of dispatched load instructions 81011860Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispStoreInsts 90791382 # Number of dispatched store instructions 81111860Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispNonSpecInsts 4430701 # Number of dispatched non-speculative instructions 81211860Sandreas.hansson@arm.comsystem.cpu0.iew.iewIQFullEvents 69738 # Number of times the IQ has become full, causing a stall 81311860Sandreas.hansson@arm.comsystem.cpu0.iew.iewLSQFullEvents 1753830 # Number of times the LSQ has become full, causing a stall 81411860Sandreas.hansson@arm.comsystem.cpu0.iew.memOrderViolationEvents 162311 # Number of memory order violations 81511860Sandreas.hansson@arm.comsystem.cpu0.iew.predictedTakenIncorrect 2018069 # Number of branches that were predicted taken incorrectly 81611860Sandreas.hansson@arm.comsystem.cpu0.iew.predictedNotTakenIncorrect 3124602 # Number of branches that were predicted not taken incorrectly 81711860Sandreas.hansson@arm.comsystem.cpu0.iew.branchMispredicts 5142671 # Number of branch mispredicts detected at execute 81811860Sandreas.hansson@arm.comsystem.cpu0.iew.iewExecutedInsts 586012257 # Number of executed instructions 81911860Sandreas.hansson@arm.comsystem.cpu0.iew.iewExecLoadInsts 107766715 # Number of load instructions executed 82011860Sandreas.hansson@arm.comsystem.cpu0.iew.iewExecSquashedInsts 7557397 # Number of squashed instructions skipped in execute 82110576Sandreas.hansson@arm.comsystem.cpu0.iew.exec_swp 0 # number of swp insts executed 82211860Sandreas.hansson@arm.comsystem.cpu0.iew.exec_nop 135817 # number of nop insts executed 82311860Sandreas.hansson@arm.comsystem.cpu0.iew.exec_refs 195183772 # number of memory reference insts executed 82411860Sandreas.hansson@arm.comsystem.cpu0.iew.exec_branches 107644173 # Number of branches executed 82511860Sandreas.hansson@arm.comsystem.cpu0.iew.exec_stores 87417057 # Number of stores executed 82611860Sandreas.hansson@arm.comsystem.cpu0.iew.exec_rate 0.872488 # Inst execution rate 82711860Sandreas.hansson@arm.comsystem.cpu0.iew.wb_sent 577164047 # cumulative count of insts sent to commit 82811860Sandreas.hansson@arm.comsystem.cpu0.iew.wb_count 576362718 # cumulative count of insts written-back 82911860Sandreas.hansson@arm.comsystem.cpu0.iew.wb_producers 283557258 # num instructions producing a value 83011860Sandreas.hansson@arm.comsystem.cpu0.iew.wb_consumers 461921851 # num instructions consuming a value 83111860Sandreas.hansson@arm.comsystem.cpu0.iew.wb_rate 0.858122 # insts written-back per cycle 83211860Sandreas.hansson@arm.comsystem.cpu0.iew.wb_fanout 0.613864 # average fanout of values written-back 83311860Sandreas.hansson@arm.comsystem.cpu0.commit.commitSquashedInsts 48922079 # The number of squashed insts skipped by commit 83411860Sandreas.hansson@arm.comsystem.cpu0.commit.commitNonSpecStalls 6745775 # The number of times commit has been forced to stall to communicate backwards 83511860Sandreas.hansson@arm.comsystem.cpu0.commit.branchMispredicts 4784510 # The number of times a branch was mispredicted 83611860Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::samples 638061728 # Number of insts commited each cycle 83711860Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::mean 0.861165 # Number of insts commited each cycle 83811860Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::stdev 1.699392 # Number of insts commited each cycle 83910576Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 84011860Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::0 421096864 66.00% 66.00% # Number of insts commited each cycle 84111860Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::1 93116977 14.59% 80.59% # Number of insts commited each cycle 84211860Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::2 56739989 8.89% 89.48% # Number of insts commited each cycle 84311860Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::3 18882229 2.96% 92.44% # Number of insts commited each cycle 84411860Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::4 13609968 2.13% 94.57% # Number of insts commited each cycle 84511860Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::5 9457933 1.48% 96.06% # Number of insts commited each cycle 84611860Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::6 6466471 1.01% 97.07% # Number of insts commited each cycle 84711860Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::7 3826133 0.60% 97.67% # Number of insts commited each cycle 84811860Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::8 14865164 2.33% 100.00% # Number of insts commited each cycle 84910576Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 85010576Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 85110576Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 85211860Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::total 638061728 # Number of insts commited each cycle 85311860Sandreas.hansson@arm.comsystem.cpu0.commit.committedInsts 461890383 # Number of instructions committed 85411860Sandreas.hansson@arm.comsystem.cpu0.commit.committedOps 549476248 # Number of ops (including micro ops) committed 85510576Sandreas.hansson@arm.comsystem.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 85611860Sandreas.hansson@arm.comsystem.cpu0.commit.refs 179586814 # Number of memory references committed 85711860Sandreas.hansson@arm.comsystem.cpu0.commit.loads 94510447 # Number of loads committed 85811860Sandreas.hansson@arm.comsystem.cpu0.commit.membars 4189650 # Number of memory barriers committed 85911860Sandreas.hansson@arm.comsystem.cpu0.commit.branches 102007560 # Number of branches committed 86011860Sandreas.hansson@arm.comsystem.cpu0.commit.fp_insts 412941 # Number of committed floating point instructions. 86111860Sandreas.hansson@arm.comsystem.cpu0.commit.int_insts 511246578 # Number of committed integer instructions. 86211860Sandreas.hansson@arm.comsystem.cpu0.commit.function_calls 15004572 # Number of function calls committed. 86310576Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 86411860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::IntAlu 368489017 67.06% 67.06% # Class of committed instruction 86511860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::IntMult 1298564 0.24% 67.30% # Class of committed instruction 86611860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::IntDiv 64848 0.01% 67.31% # Class of committed instruction 86711860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatAdd 8 0.00% 67.31% # Class of committed instruction 86811860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatCmp 13 0.00% 67.31% # Class of committed instruction 86911860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatCvt 21 0.00% 67.31% # Class of committed instruction 87011860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.31% # Class of committed instruction 87111860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 67.31% # Class of committed instruction 87211860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.31% # Class of committed instruction 87311860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatMisc 36963 0.01% 67.32% # Class of committed instruction 87411860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.32% # Class of committed instruction 87511860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.32% # Class of committed instruction 87611860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.32% # Class of committed instruction 87711860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.32% # Class of committed instruction 87811860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.32% # Class of committed instruction 87911860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.32% # Class of committed instruction 88011860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.32% # Class of committed instruction 88111860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.32% # Class of committed instruction 88211860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.32% # Class of committed instruction 88311860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.32% # Class of committed instruction 88411860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.32% # Class of committed instruction 88511860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.32% # Class of committed instruction 88611860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.32% # Class of committed instruction 88711860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.32% # Class of committed instruction 88811860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.32% # Class of committed instruction 88911860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.32% # Class of committed instruction 89011860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.32% # Class of committed instruction 89111860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 67.32% # Class of committed instruction 89211860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.32% # Class of committed instruction 89311860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.32% # Class of committed instruction 89411860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.32% # Class of committed instruction 89511860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::MemRead 94459041 17.19% 84.51% # Class of committed instruction 89611860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::MemWrite 84751837 15.42% 99.93% # Class of committed instruction 89711860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatMemRead 51406 0.01% 99.94% # Class of committed instruction 89811860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatMemWrite 324530 0.06% 100.00% # Class of committed instruction 89910576Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 90010576Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 90111860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::total 549476248 # Class of committed instruction 90211860Sandreas.hansson@arm.comsystem.cpu0.commit.bw_lim_events 14865164 # number cycles where commit BW limit reached 90311860Sandreas.hansson@arm.comsystem.cpu0.rob.rob_reads 1217272285 # The number of ROB reads 90411860Sandreas.hansson@arm.comsystem.cpu0.rob.rob_writes 1206069871 # The number of ROB writes 90511860Sandreas.hansson@arm.comsystem.cpu0.timesIdled 983506 # Number of times that the entire CPU went into an idle state and unscheduled itself 90611860Sandreas.hansson@arm.comsystem.cpu0.idleCycles 24284471 # Total number of cycles that the CPU has spent unscheduled due to idling 90711860Sandreas.hansson@arm.comsystem.cpu0.quiesceCycles 94012190405 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 90811860Sandreas.hansson@arm.comsystem.cpu0.committedInsts 461890383 # Number of Instructions Simulated 90911860Sandreas.hansson@arm.comsystem.cpu0.committedOps 549476248 # Number of Ops (including micro ops) Simulated 91011860Sandreas.hansson@arm.comsystem.cpu0.cpi 1.454146 # CPI: Cycles Per Instruction 91111860Sandreas.hansson@arm.comsystem.cpu0.cpi_total 1.454146 # CPI: Total CPI of All Threads 91211860Sandreas.hansson@arm.comsystem.cpu0.ipc 0.687689 # IPC: Instructions Per Cycle 91311860Sandreas.hansson@arm.comsystem.cpu0.ipc_total 0.687689 # IPC: Total IPC of All Threads 91411860Sandreas.hansson@arm.comsystem.cpu0.int_regfile_reads 689648120 # number of integer regfile reads 91511860Sandreas.hansson@arm.comsystem.cpu0.int_regfile_writes 419367317 # number of integer regfile writes 91611860Sandreas.hansson@arm.comsystem.cpu0.fp_regfile_reads 692130 # number of floating regfile reads 91711860Sandreas.hansson@arm.comsystem.cpu0.fp_regfile_writes 320584 # number of floating regfile writes 91811860Sandreas.hansson@arm.comsystem.cpu0.cc_regfile_reads 105285978 # number of cc regfile reads 91911860Sandreas.hansson@arm.comsystem.cpu0.cc_regfile_writes 105978286 # number of cc regfile writes 92011860Sandreas.hansson@arm.comsystem.cpu0.misc_regfile_reads 1168751660 # number of misc regfile reads 92111860Sandreas.hansson@arm.comsystem.cpu0.misc_regfile_writes 6863582 # number of misc regfile writes 92211860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 92311860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 6620968 # number of replacements 92411860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 481.361219 # Cycle average of tags in use 92511860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 165967454 # Total number of references to valid blocks. 92611860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 6621480 # Sample count of references to valid blocks. 92711860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 25.065009 # Average number of references to valid blocks. 92811860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 204144000 # Cycle when the warmup percentage was hit. 92911860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 481.361219 # Average occupied blocks per requestor 93011860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.940159 # Average percentage of cache occupancy 93111860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.940159 # Average percentage of cache occupancy 93211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 93311860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id 93411860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 433 # Occupied blocks per task id 93511860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id 93611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 93711860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 372530825 # Number of tag accesses 93811860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 372530825 # Number of data accesses 93911860Sandreas.hansson@arm.comsystem.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 94011860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 87044023 # number of ReadReq hits 94111860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 87044023 # number of ReadReq hits 94211860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 73673205 # number of WriteReq hits 94311860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 73673205 # number of WriteReq hits 94411860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 219185 # number of SoftPFReq hits 94511860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 219185 # number of SoftPFReq hits 94611860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::cpu0.data 153997 # number of WriteLineReq hits 94711860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::total 153997 # number of WriteLineReq hits 94811860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2008223 # number of LoadLockedReq hits 94911860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 2008223 # number of LoadLockedReq hits 95011860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 2072988 # number of StoreCondReq hits 95111860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 2072988 # number of StoreCondReq hits 95211860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 160871225 # number of demand (read+write) hits 95311860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 160871225 # number of demand (read+write) hits 95411860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 161090410 # number of overall hits 95511860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 161090410 # number of overall hits 95611860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 7470146 # number of ReadReq misses 95711860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 7470146 # number of ReadReq misses 95811860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 8166848 # number of WriteReq misses 95911860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 8166848 # number of WriteReq misses 96011860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 789396 # number of SoftPFReq misses 96111860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 789396 # number of SoftPFReq misses 96211860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::cpu0.data 800299 # number of WriteLineReq misses 96311860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::total 800299 # number of WriteLineReq misses 96411860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 307874 # number of LoadLockedReq misses 96511860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 307874 # number of LoadLockedReq misses 96611860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 202740 # number of StoreCondReq misses 96711860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 202740 # number of StoreCondReq misses 96811860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 16437293 # number of demand (read+write) misses 96911860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 16437293 # number of demand (read+write) misses 97011860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 17226689 # number of overall misses 97111860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 17226689 # number of overall misses 97211860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 120830384000 # number of ReadReq miss cycles 97311860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 120830384000 # number of ReadReq miss cycles 97411860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 166078687815 # number of WriteReq miss cycles 97511860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 166078687815 # number of WriteReq miss cycles 97611860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 29848601951 # number of WriteLineReq miss cycles 97711860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::total 29848601951 # number of WriteLineReq miss cycles 97811860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4689476000 # number of LoadLockedReq miss cycles 97911860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 4689476000 # number of LoadLockedReq miss cycles 98011860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4883927500 # number of StoreCondReq miss cycles 98111860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 4883927500 # number of StoreCondReq miss cycles 98211860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2141000 # number of StoreCondFailReq miss cycles 98311860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::total 2141000 # number of StoreCondFailReq miss cycles 98411860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::cpu0.data 316757673766 # number of demand (read+write) miss cycles 98511860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::total 316757673766 # number of demand (read+write) miss cycles 98611860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::cpu0.data 316757673766 # number of overall miss cycles 98711860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::total 316757673766 # number of overall miss cycles 98811860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 94514169 # number of ReadReq accesses(hits+misses) 98911860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 94514169 # number of ReadReq accesses(hits+misses) 99011860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 81840053 # number of WriteReq accesses(hits+misses) 99111860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 81840053 # number of WriteReq accesses(hits+misses) 99211860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1008581 # number of SoftPFReq accesses(hits+misses) 99311860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 1008581 # number of SoftPFReq accesses(hits+misses) 99411860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::cpu0.data 954296 # number of WriteLineReq accesses(hits+misses) 99511860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::total 954296 # number of WriteLineReq accesses(hits+misses) 99611860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2316097 # number of LoadLockedReq accesses(hits+misses) 99711860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 2316097 # number of LoadLockedReq accesses(hits+misses) 99811860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2275728 # number of StoreCondReq accesses(hits+misses) 99911860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 2275728 # number of StoreCondReq accesses(hits+misses) 100011860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 177308518 # number of demand (read+write) accesses 100111860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 177308518 # number of demand (read+write) accesses 100211860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 178317099 # number of overall (read+write) accesses 100311860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 178317099 # number of overall (read+write) accesses 100411860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.079037 # miss rate for ReadReq accesses 100511860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.079037 # miss rate for ReadReq accesses 100611860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.099790 # miss rate for WriteReq accesses 100711860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.099790 # miss rate for WriteReq accesses 100811860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.782680 # miss rate for SoftPFReq accesses 100911860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.782680 # miss rate for SoftPFReq accesses 101011860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.838628 # miss rate for WriteLineReq accesses 101111860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::total 0.838628 # miss rate for WriteLineReq accesses 101211860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.132928 # miss rate for LoadLockedReq accesses 101311860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.132928 # miss rate for LoadLockedReq accesses 101411860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.089088 # miss rate for StoreCondReq accesses 101511860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.089088 # miss rate for StoreCondReq accesses 101611860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.092704 # miss rate for demand accesses 101711860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.092704 # miss rate for demand accesses 101811860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.096607 # miss rate for overall accesses 101911860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.096607 # miss rate for overall accesses 102011860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16175.103405 # average ReadReq miss latency 102111860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 16175.103405 # average ReadReq miss latency 102211860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20335.714319 # average WriteReq miss latency 102311860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 20335.714319 # average WriteReq miss latency 102411860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 37296.812755 # average WriteLineReq miss latency 102511860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::total 37296.812755 # average WriteLineReq miss latency 102611860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15231.802621 # average LoadLockedReq miss latency 102711860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15231.802621 # average LoadLockedReq miss latency 102811860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24089.609845 # average StoreCondReq miss latency 102911860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24089.609845 # average StoreCondReq miss latency 103010576Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 103110576Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 103211860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19270.671501 # average overall miss latency 103311860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 19270.671501 # average overall miss latency 103411860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18387.612023 # average overall miss latency 103511860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 18387.612023 # average overall miss latency 103611860Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 9058407 # number of cycles access was blocked 103711860Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 25757393 # number of cycles access was blocked 103811860Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 741437 # number of cycles access was blocked 103911860Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_targets 811492 # number of cycles access was blocked 104011860Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs 12.217366 # average number of cycles each access was blocked 104111860Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets 31.740785 # average number of cycles each access was blocked 104211860Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 6621095 # number of writebacks 104311860Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 6621095 # number of writebacks 104411860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3832878 # number of ReadReq MSHR hits 104511860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 3832878 # number of ReadReq MSHR hits 104611860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6557291 # number of WriteReq MSHR hits 104711860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 6557291 # number of WriteReq MSHR hits 104811860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4455 # number of WriteLineReq MSHR hits 104911860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_hits::total 4455 # number of WriteLineReq MSHR hits 105011860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 156975 # number of LoadLockedReq MSHR hits 105111860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 156975 # number of LoadLockedReq MSHR hits 105211860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::cpu0.data 10394624 # number of demand (read+write) MSHR hits 105311860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::total 10394624 # number of demand (read+write) MSHR hits 105411860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::cpu0.data 10394624 # number of overall MSHR hits 105511860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::total 10394624 # number of overall MSHR hits 105611860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3637268 # number of ReadReq MSHR misses 105711860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 3637268 # number of ReadReq MSHR misses 105811860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1609557 # number of WriteReq MSHR misses 105911860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 1609557 # number of WriteReq MSHR misses 106011860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 782554 # number of SoftPFReq MSHR misses 106111860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::total 782554 # number of SoftPFReq MSHR misses 106211860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 795844 # number of WriteLineReq MSHR misses 106311860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::total 795844 # number of WriteLineReq MSHR misses 106411860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 150899 # number of LoadLockedReq MSHR misses 106511860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 150899 # number of LoadLockedReq MSHR misses 106611860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 202732 # number of StoreCondReq MSHR misses 106711860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 202732 # number of StoreCondReq MSHR misses 106811860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.data 6042669 # number of demand (read+write) MSHR misses 106911860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 6042669 # number of demand (read+write) MSHR misses 107011860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.data 6825223 # number of overall MSHR misses 107111860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 6825223 # number of overall MSHR misses 107211860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15843 # number of ReadReq MSHR uncacheable 107311860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::total 15843 # number of ReadReq MSHR uncacheable 107411860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 17283 # number of WriteReq MSHR uncacheable 107511860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::total 17283 # number of WriteReq MSHR uncacheable 107611860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 33126 # number of overall MSHR uncacheable misses 107711860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::total 33126 # number of overall MSHR uncacheable misses 107811860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 55872486000 # number of ReadReq MSHR miss cycles 107911860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 55872486000 # number of ReadReq MSHR miss cycles 108011860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 35889720367 # number of WriteReq MSHR miss cycles 108111860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 35889720367 # number of WriteReq MSHR miss cycles 108211860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18736140000 # number of SoftPFReq MSHR miss cycles 108311860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18736140000 # number of SoftPFReq MSHR miss cycles 108411860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 28877247951 # number of WriteLineReq MSHR miss cycles 108511860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 28877247951 # number of WriteLineReq MSHR miss cycles 108611860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 2069296000 # number of LoadLockedReq MSHR miss cycles 108711860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2069296000 # number of LoadLockedReq MSHR miss cycles 108811860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4681247500 # number of StoreCondReq MSHR miss cycles 108911860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4681247500 # number of StoreCondReq MSHR miss cycles 109011860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2089000 # number of StoreCondFailReq MSHR miss cycles 109111860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2089000 # number of StoreCondFailReq MSHR miss cycles 109211860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 120639454318 # number of demand (read+write) MSHR miss cycles 109311860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 120639454318 # number of demand (read+write) MSHR miss cycles 109411860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 139375594318 # number of overall MSHR miss cycles 109511860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 139375594318 # number of overall MSHR miss cycles 109611860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2897214000 # number of ReadReq MSHR uncacheable cycles 109711860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2897214000 # number of ReadReq MSHR uncacheable cycles 109811860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2897214000 # number of overall MSHR uncacheable cycles 109911860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 2897214000 # number of overall MSHR uncacheable cycles 110011860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.038484 # mshr miss rate for ReadReq accesses 110111860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.038484 # mshr miss rate for ReadReq accesses 110211860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019667 # mshr miss rate for WriteReq accesses 110311860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019667 # mshr miss rate for WriteReq accesses 110411860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.775896 # mshr miss rate for SoftPFReq accesses 110511860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.775896 # mshr miss rate for SoftPFReq accesses 110611860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.833959 # mshr miss rate for WriteLineReq accesses 110711860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.833959 # mshr miss rate for WriteLineReq accesses 110811860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.065152 # mshr miss rate for LoadLockedReq accesses 110911860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.065152 # mshr miss rate for LoadLockedReq accesses 111011860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.089084 # mshr miss rate for StoreCondReq accesses 111111860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.089084 # mshr miss rate for StoreCondReq accesses 111211860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.034080 # mshr miss rate for demand accesses 111311860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.034080 # mshr miss rate for demand accesses 111411860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.038276 # mshr miss rate for overall accesses 111511860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.038276 # mshr miss rate for overall accesses 111611860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15361.113341 # average ReadReq mshr miss latency 111711860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15361.113341 # average ReadReq mshr miss latency 111811860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22297.887162 # average WriteReq mshr miss latency 111911860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22297.887162 # average WriteReq mshr miss latency 112011860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23942.296634 # average SoftPFReq mshr miss latency 112111860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23942.296634 # average SoftPFReq mshr miss latency 112211860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 36285.060830 # average WriteLineReq mshr miss latency 112311860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 36285.060830 # average WriteLineReq mshr miss latency 112411860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13713.119371 # average LoadLockedReq mshr miss latency 112511860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13713.119371 # average LoadLockedReq mshr miss latency 112611860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23090.816941 # average StoreCondReq mshr miss latency 112711860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23090.816941 # average StoreCondReq mshr miss latency 112810576Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 112910576Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 113011860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19964.597485 # average overall mshr miss latency 113111860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 19964.597485 # average overall mshr miss latency 113211860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20420.665276 # average overall mshr miss latency 113311860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 20420.665276 # average overall mshr miss latency 113411860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182870.289718 # average ReadReq mshr uncacheable latency 113511860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 182870.289718 # average ReadReq mshr uncacheable latency 113611860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87460.423836 # average overall mshr uncacheable latency 113711860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87460.423836 # average overall mshr uncacheable latency 113811860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 113911860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 6024041 # number of replacements 114011860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.980173 # Cycle average of tags in use 114111860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 202652654 # Total number of references to valid blocks. 114211860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 6024553 # Sample count of references to valid blocks. 114311860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 33.637791 # Average number of references to valid blocks. 114411860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 11640760000 # Cycle when the warmup percentage was hit. 114511860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.980173 # Average occupied blocks per requestor 114611860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999961 # Average percentage of cache occupancy 114711860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999961 # Average percentage of cache occupancy 114810576Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 114911860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id 115011860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 418 # Occupied blocks per task id 115111860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id 115210576Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 115311860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 424090067 # Number of tag accesses 115411860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 424090067 # Number of data accesses 115511860Sandreas.hansson@arm.comsystem.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 115611860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 202652654 # number of ReadReq hits 115711860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 202652654 # number of ReadReq hits 115811860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 202652654 # number of demand (read+write) hits 115911860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 202652654 # number of demand (read+write) hits 116011860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 202652654 # number of overall hits 116111860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 202652654 # number of overall hits 116211860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 6379961 # number of ReadReq misses 116311860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 6379961 # number of ReadReq misses 116411860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 6379961 # number of demand (read+write) misses 116511860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 6379961 # number of demand (read+write) misses 116611860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 6379961 # number of overall misses 116711860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 6379961 # number of overall misses 116811860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 71606822648 # number of ReadReq miss cycles 116911860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 71606822648 # number of ReadReq miss cycles 117011860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 71606822648 # number of demand (read+write) miss cycles 117111860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::total 71606822648 # number of demand (read+write) miss cycles 117211860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 71606822648 # number of overall miss cycles 117311860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::total 71606822648 # number of overall miss cycles 117411860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 209032615 # number of ReadReq accesses(hits+misses) 117511860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 209032615 # number of ReadReq accesses(hits+misses) 117611860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 209032615 # number of demand (read+write) accesses 117711860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 209032615 # number of demand (read+write) accesses 117811860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 209032615 # number of overall (read+write) accesses 117911860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 209032615 # number of overall (read+write) accesses 118011860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.030521 # miss rate for ReadReq accesses 118111860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.030521 # miss rate for ReadReq accesses 118211860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.030521 # miss rate for demand accesses 118311860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.030521 # miss rate for demand accesses 118411860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.030521 # miss rate for overall accesses 118511860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.030521 # miss rate for overall accesses 118611860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11223.708522 # average ReadReq miss latency 118711860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 11223.708522 # average ReadReq miss latency 118811860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11223.708522 # average overall miss latency 118911860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 11223.708522 # average overall miss latency 119011860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11223.708522 # average overall miss latency 119111860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 11223.708522 # average overall miss latency 119211860Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 10553176 # number of cycles access was blocked 119311860Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_targets 2682 # number of cycles access was blocked 119411860Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_mshrs 731110 # number of cycles access was blocked 119511860Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_targets 11 # number of cycles access was blocked 119611860Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs 14.434457 # average number of cycles each access was blocked 119711860Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_targets 243.818182 # average number of cycles each access was blocked 119811860Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::writebacks 6024041 # number of writebacks 119911860Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::total 6024041 # number of writebacks 120011860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 355124 # number of ReadReq MSHR hits 120111860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_hits::total 355124 # number of ReadReq MSHR hits 120211860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_hits::cpu0.inst 355124 # number of demand (read+write) MSHR hits 120311860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_hits::total 355124 # number of demand (read+write) MSHR hits 120411860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_hits::cpu0.inst 355124 # number of overall MSHR hits 120511860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_hits::total 355124 # number of overall MSHR hits 120611860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6024837 # number of ReadReq MSHR misses 120711860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 6024837 # number of ReadReq MSHR misses 120811860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 6024837 # number of demand (read+write) MSHR misses 120911860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::total 6024837 # number of demand (read+write) MSHR misses 121011860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 6024837 # number of overall MSHR misses 121111860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::total 6024837 # number of overall MSHR misses 121211860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 2093 # number of ReadReq MSHR uncacheable 121311860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::total 2093 # number of ReadReq MSHR uncacheable 121411860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 2093 # number of overall MSHR uncacheable misses 121511860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::total 2093 # number of overall MSHR uncacheable misses 121611860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 64522792922 # number of ReadReq MSHR miss cycles 121711860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 64522792922 # number of ReadReq MSHR miss cycles 121811860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 64522792922 # number of demand (read+write) MSHR miss cycles 121911860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 64522792922 # number of demand (read+write) MSHR miss cycles 122011860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 64522792922 # number of overall MSHR miss cycles 122111860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 64522792922 # number of overall MSHR miss cycles 122211860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 201228498 # number of ReadReq MSHR uncacheable cycles 122311860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 201228498 # number of ReadReq MSHR uncacheable cycles 122411860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 201228498 # number of overall MSHR uncacheable cycles 122511860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::total 201228498 # number of overall MSHR uncacheable cycles 122611860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028822 # mshr miss rate for ReadReq accesses 122711860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028822 # mshr miss rate for ReadReq accesses 122811860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028822 # mshr miss rate for demand accesses 122911860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.028822 # mshr miss rate for demand accesses 123011860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028822 # mshr miss rate for overall accesses 123111860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.028822 # mshr miss rate for overall accesses 123211860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10709.466982 # average ReadReq mshr miss latency 123311860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10709.466982 # average ReadReq mshr miss latency 123411860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10709.466982 # average overall mshr miss latency 123511860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 10709.466982 # average overall mshr miss latency 123611860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10709.466982 # average overall mshr miss latency 123711860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 10709.466982 # average overall mshr miss latency 123811860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 96143.572862 # average ReadReq mshr uncacheable latency 123911860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 96143.572862 # average ReadReq mshr uncacheable latency 124011860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 96143.572862 # average overall mshr uncacheable latency 124111860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 96143.572862 # average overall mshr uncacheable latency 124211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 124311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.num_hwpf_issued 9077732 # number of hwpf issued 124411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfIdentified 9085476 # number of prefetch candidates identified 124511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfBufferHit 6999 # number of redundant prefetches already in prefetch queue 124610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 124710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 124811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfSpanPage 1224644 # number of prefetches not generated due to page crossing 124911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 125011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.replacements 2885626 # number of replacements 125111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tagsinuse 15865.684381 # Cycle average of tags in use 125211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.total_refs 11160732 # Total number of references to valid blocks. 125311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.sampled_refs 2901096 # Sample count of references to valid blocks. 125411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.avg_refs 3.847074 # Average number of references to valid blocks. 125511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 512573000 # Cycle when the warmup percentage was hit. 125611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 15504.354139 # Average occupied blocks per requestor 125711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 30.001688 # Average occupied blocks per requestor 125811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 17.597153 # Average occupied blocks per requestor 125911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.000007 # Average occupied blocks per requestor 126011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 313.731394 # Average occupied blocks per requestor 126111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.946311 # Average percentage of cache occupancy 126211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001831 # Average percentage of cache occupancy 126311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001074 # Average percentage of cache occupancy 126411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.data 0.000000 # Average percentage of cache occupancy 126511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.019149 # Average percentage of cache occupancy 126611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.968365 # Average percentage of cache occupancy 126711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1022 318 # Occupied blocks per task id 126811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 111 # Occupied blocks per task id 126911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 15041 # Occupied blocks per task id 127011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id 127111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::2 120 # Occupied blocks per task id 127211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::3 81 # Occupied blocks per task id 127311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::4 114 # Occupied blocks per task id 127411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::1 37 # Occupied blocks per task id 127511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 43 # Occupied blocks per task id 127611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id 127711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 26 # Occupied blocks per task id 127811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id 127911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 2178 # Occupied blocks per task id 128011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7928 # Occupied blocks per task id 128111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2613 # Occupied blocks per task id 128211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2218 # Occupied blocks per task id 128311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1022 0.019409 # Percentage of cache occupancy per task id 128411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006775 # Percentage of cache occupancy per task id 128511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.918030 # Percentage of cache occupancy per task id 128611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tag_accesses 441303495 # Number of tag accesses 128711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.data_accesses 441303495 # Number of data accesses 128811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 128911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 661323 # number of ReadReq hits 129011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 192664 # number of ReadReq hits 129111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 853987 # number of ReadReq hits 129211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::writebacks 4337132 # number of WritebackDirty hits 129311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::total 4337132 # number of WritebackDirty hits 129411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_hits::writebacks 8306124 # number of WritebackClean hits 129511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_hits::total 8306124 # number of WritebackClean hits 129611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::cpu0.data 35 # number of UpgradeReq hits 129711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::total 35 # number of UpgradeReq hits 129811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 3 # number of SCUpgradeReq hits 129911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits 130011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 1063752 # number of ReadExReq hits 130111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 1063752 # number of ReadExReq hits 130211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5420251 # number of ReadCleanReq hits 130311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 5420251 # number of ReadCleanReq hits 130411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3451457 # number of ReadSharedReq hits 130511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 3451457 # number of ReadSharedReq hits 130611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::cpu0.data 175529 # number of InvalidateReq hits 130711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::total 175529 # number of InvalidateReq hits 130811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 661323 # number of demand (read+write) hits 130911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 192664 # number of demand (read+write) hits 131011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 5420251 # number of demand (read+write) hits 131111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 4515209 # number of demand (read+write) hits 131211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::total 10789447 # number of demand (read+write) hits 131311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 661323 # number of overall hits 131411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 192664 # number of overall hits 131511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 5420251 # number of overall hits 131611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 4515209 # number of overall hits 131711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::total 10789447 # number of overall hits 131811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 24436 # number of ReadReq misses 131911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 12223 # number of ReadReq misses 132011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 36659 # number of ReadReq misses 132111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses 132211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses 132311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 266353 # number of UpgradeReq misses 132411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 266353 # number of UpgradeReq misses 132511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 202724 # number of SCUpgradeReq misses 132611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 202724 # number of SCUpgradeReq misses 132711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses 132811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses 132911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 288175 # number of ReadExReq misses 133011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 288175 # number of ReadExReq misses 133111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 604135 # number of ReadCleanReq misses 133211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 604135 # number of ReadCleanReq misses 133311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1115532 # number of ReadSharedReq misses 133411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 1115532 # number of ReadSharedReq misses 133511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::cpu0.data 620315 # number of InvalidateReq misses 133611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::total 620315 # number of InvalidateReq misses 133711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 24436 # number of demand (read+write) misses 133811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 12223 # number of demand (read+write) misses 133911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 604135 # number of demand (read+write) misses 134011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 1403707 # number of demand (read+write) misses 134111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::total 2044501 # number of demand (read+write) misses 134211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 24436 # number of overall misses 134311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 12223 # number of overall misses 134411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 604135 # number of overall misses 134511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 1403707 # number of overall misses 134611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::total 2044501 # number of overall misses 134711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 912274000 # number of ReadReq miss cycles 134811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 596923500 # number of ReadReq miss cycles 134911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::total 1509197500 # number of ReadReq miss cycles 135011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 951661000 # number of UpgradeReq miss cycles 135111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::total 951661000 # number of UpgradeReq miss cycles 135211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 365355500 # number of SCUpgradeReq miss cycles 135311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::total 365355500 # number of SCUpgradeReq miss cycles 135411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2010499 # number of SCUpgradeFailReq miss cycles 135511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2010499 # number of SCUpgradeFailReq miss cycles 135611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 19225466000 # number of ReadExReq miss cycles 135711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::total 19225466000 # number of ReadExReq miss cycles 135811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 22664217000 # number of ReadCleanReq miss cycles 135911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::total 22664217000 # number of ReadCleanReq miss cycles 136011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 46789999492 # number of ReadSharedReq miss cycles 136111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::total 46789999492 # number of ReadSharedReq miss cycles 136211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 209000 # number of InvalidateReq miss cycles 136311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::total 209000 # number of InvalidateReq miss cycles 136411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 912274000 # number of demand (read+write) miss cycles 136511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 596923500 # number of demand (read+write) miss cycles 136611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.inst 22664217000 # number of demand (read+write) miss cycles 136711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.data 66015465492 # number of demand (read+write) miss cycles 136811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::total 90188879992 # number of demand (read+write) miss cycles 136911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 912274000 # number of overall miss cycles 137011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 596923500 # number of overall miss cycles 137111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.inst 22664217000 # number of overall miss cycles 137211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.data 66015465492 # number of overall miss cycles 137311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::total 90188879992 # number of overall miss cycles 137411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 685759 # number of ReadReq accesses(hits+misses) 137511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 204887 # number of ReadReq accesses(hits+misses) 137611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 890646 # number of ReadReq accesses(hits+misses) 137711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::writebacks 4337132 # number of WritebackDirty accesses(hits+misses) 137811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::total 4337132 # number of WritebackDirty accesses(hits+misses) 137911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::writebacks 8306125 # number of WritebackClean accesses(hits+misses) 138011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::total 8306125 # number of WritebackClean accesses(hits+misses) 138111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 266388 # number of UpgradeReq accesses(hits+misses) 138211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 266388 # number of UpgradeReq accesses(hits+misses) 138311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 202727 # number of SCUpgradeReq accesses(hits+misses) 138411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 202727 # number of SCUpgradeReq accesses(hits+misses) 138511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses) 138611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) 138711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1351927 # number of ReadExReq accesses(hits+misses) 138811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1351927 # number of ReadExReq accesses(hits+misses) 138911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 6024386 # number of ReadCleanReq accesses(hits+misses) 139011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 6024386 # number of ReadCleanReq accesses(hits+misses) 139111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4566989 # number of ReadSharedReq accesses(hits+misses) 139211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 4566989 # number of ReadSharedReq accesses(hits+misses) 139311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 795844 # number of InvalidateReq accesses(hits+misses) 139411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::total 795844 # number of InvalidateReq accesses(hits+misses) 139511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 685759 # number of demand (read+write) accesses 139611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 204887 # number of demand (read+write) accesses 139711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 6024386 # number of demand (read+write) accesses 139811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 5918916 # number of demand (read+write) accesses 139911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::total 12833948 # number of demand (read+write) accesses 140011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 685759 # number of overall (read+write) accesses 140111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 204887 # number of overall (read+write) accesses 140211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 6024386 # number of overall (read+write) accesses 140311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 5918916 # number of overall (read+write) accesses 140411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::total 12833948 # number of overall (read+write) accesses 140511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.035634 # miss rate for ReadReq accesses 140611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.059657 # miss rate for ReadReq accesses 140711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.041160 # miss rate for ReadReq accesses 140811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses 140911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses 141011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999869 # miss rate for UpgradeReq accesses 141111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999869 # miss rate for UpgradeReq accesses 141211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999985 # miss rate for SCUpgradeReq accesses 141311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999985 # miss rate for SCUpgradeReq accesses 141410576Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 141510576Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 141611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.213159 # miss rate for ReadExReq accesses 141711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.213159 # miss rate for ReadExReq accesses 141811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.100282 # miss rate for ReadCleanReq accesses 141911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.100282 # miss rate for ReadCleanReq accesses 142011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.244260 # miss rate for ReadSharedReq accesses 142111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.244260 # miss rate for ReadSharedReq accesses 142211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.779443 # miss rate for InvalidateReq accesses 142311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::total 0.779443 # miss rate for InvalidateReq accesses 142411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.035634 # miss rate for demand accesses 142511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.059657 # miss rate for demand accesses 142611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.100282 # miss rate for demand accesses 142711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.237156 # miss rate for demand accesses 142811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.159304 # miss rate for demand accesses 142911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.035634 # miss rate for overall accesses 143011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.059657 # miss rate for overall accesses 143111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.100282 # miss rate for overall accesses 143211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.237156 # miss rate for overall accesses 143311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.159304 # miss rate for overall accesses 143411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 37333.196923 # average ReadReq miss latency 143511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 48836.087704 # average ReadReq miss latency 143611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::total 41168.539786 # average ReadReq miss latency 143711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3572.931411 # average UpgradeReq miss latency 143811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3572.931411 # average UpgradeReq miss latency 143911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1802.231112 # average SCUpgradeReq miss latency 144011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1802.231112 # average SCUpgradeReq miss latency 144111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 402099.800000 # average SCUpgradeFailReq miss latency 144211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 402099.800000 # average SCUpgradeFailReq miss latency 144311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 66714.551922 # average ReadExReq miss latency 144411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::total 66714.551922 # average ReadExReq miss latency 144511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 37515.153070 # average ReadCleanReq miss latency 144611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 37515.153070 # average ReadCleanReq miss latency 144711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 41944.112309 # average ReadSharedReq miss latency 144811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 41944.112309 # average ReadSharedReq miss latency 144911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 0.336926 # average InvalidateReq miss latency 145011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 0.336926 # average InvalidateReq miss latency 145111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 37333.196923 # average overall miss latency 145211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 48836.087704 # average overall miss latency 145311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37515.153070 # average overall miss latency 145411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 47029.376851 # average overall miss latency 145511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::total 44112.905786 # average overall miss latency 145611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 37333.196923 # average overall miss latency 145711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 48836.087704 # average overall miss latency 145811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37515.153070 # average overall miss latency 145911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 47029.376851 # average overall miss latency 146011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::total 44112.905786 # average overall miss latency 146111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_mshrs 1145 # number of cycles access was blocked 146210576Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 146311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_mshrs 20 # number of cycles access was blocked 146410576Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 146511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs 57.250000 # average number of cycles each access was blocked 146610576Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 146711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.unused_prefetches 50024 # number of HardPF blocks evicted w/o reference 146811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::writebacks 1896260 # number of writebacks 146911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::total 1896260 # number of writebacks 147011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 178 # number of ReadReq MSHR hits 147111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 367 # number of ReadReq MSHR hits 147211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::total 545 # number of ReadReq MSHR hits 147311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 23776 # number of ReadExReq MSHR hits 147411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::total 23776 # number of ReadExReq MSHR hits 147511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 3 # number of ReadCleanReq MSHR hits 147611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits 147711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 5616 # number of ReadSharedReq MSHR hits 147811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::total 5616 # number of ReadSharedReq MSHR hits 147911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 3 # number of InvalidateReq MSHR hits 148011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits 148111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 178 # number of demand (read+write) MSHR hits 148211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 367 # number of demand (read+write) MSHR hits 148311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits 148411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.data 29392 # number of demand (read+write) MSHR hits 148511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::total 29940 # number of demand (read+write) MSHR hits 148611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 178 # number of overall MSHR hits 148711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 367 # number of overall MSHR hits 148811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits 148911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.data 29392 # number of overall MSHR hits 149011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::total 29940 # number of overall MSHR hits 149111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 24258 # number of ReadReq MSHR misses 149211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 11856 # number of ReadReq MSHR misses 149311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::total 36114 # number of ReadReq MSHR misses 149411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses 149511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses 149611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 950932 # number of HardPFReq MSHR misses 149711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::total 950932 # number of HardPFReq MSHR misses 149811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 266353 # number of UpgradeReq MSHR misses 149911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::total 266353 # number of UpgradeReq MSHR misses 150011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 202724 # number of SCUpgradeReq MSHR misses 150111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 202724 # number of SCUpgradeReq MSHR misses 150211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses 150311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses 150411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 264399 # number of ReadExReq MSHR misses 150511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::total 264399 # number of ReadExReq MSHR misses 150611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 604132 # number of ReadCleanReq MSHR misses 150711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::total 604132 # number of ReadCleanReq MSHR misses 150811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1109916 # number of ReadSharedReq MSHR misses 150911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1109916 # number of ReadSharedReq MSHR misses 151011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 620312 # number of InvalidateReq MSHR misses 151111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::total 620312 # number of InvalidateReq MSHR misses 151211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 24258 # number of demand (read+write) MSHR misses 151311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 11856 # number of demand (read+write) MSHR misses 151411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.inst 604132 # number of demand (read+write) MSHR misses 151511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.data 1374315 # number of demand (read+write) MSHR misses 151611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::total 2014561 # number of demand (read+write) MSHR misses 151711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 24258 # number of overall MSHR misses 151811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 11856 # number of overall MSHR misses 151911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.inst 604132 # number of overall MSHR misses 152011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.data 1374315 # number of overall MSHR misses 152111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 950932 # number of overall MSHR misses 152211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::total 2965493 # number of overall MSHR misses 152311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 2093 # number of ReadReq MSHR uncacheable 152411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 15843 # number of ReadReq MSHR uncacheable 152511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::total 17936 # number of ReadReq MSHR uncacheable 152611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 17283 # number of WriteReq MSHR uncacheable 152711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::total 17283 # number of WriteReq MSHR uncacheable 152811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 2093 # number of overall MSHR uncacheable misses 152911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 33126 # number of overall MSHR uncacheable misses 153011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::total 35219 # number of overall MSHR uncacheable misses 153111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 763418000 # number of ReadReq MSHR miss cycles 153211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 519315500 # number of ReadReq MSHR miss cycles 153311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1282733500 # number of ReadReq MSHR miss cycles 153411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 66266397744 # number of HardPFReq MSHR miss cycles 153511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 66266397744 # number of HardPFReq MSHR miss cycles 153611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4978129498 # number of UpgradeReq MSHR miss cycles 153711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4978129498 # number of UpgradeReq MSHR miss cycles 153811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3157260491 # number of SCUpgradeReq MSHR miss cycles 153911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3157260491 # number of SCUpgradeReq MSHR miss cycles 154011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1698499 # number of SCUpgradeFailReq MSHR miss cycles 154111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1698499 # number of SCUpgradeFailReq MSHR miss cycles 154211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 14042647500 # number of ReadExReq MSHR miss cycles 154311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 14042647500 # number of ReadExReq MSHR miss cycles 154411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 19039385000 # number of ReadCleanReq MSHR miss cycles 154511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 19039385000 # number of ReadCleanReq MSHR miss cycles 154611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 39727406492 # number of ReadSharedReq MSHR miss cycles 154711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 39727406492 # number of ReadSharedReq MSHR miss cycles 154811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 22010835496 # number of InvalidateReq MSHR miss cycles 154911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 22010835496 # number of InvalidateReq MSHR miss cycles 155011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 763418000 # number of demand (read+write) MSHR miss cycles 155111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 519315500 # number of demand (read+write) MSHR miss cycles 155211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 19039385000 # number of demand (read+write) MSHR miss cycles 155311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 53770053992 # number of demand (read+write) MSHR miss cycles 155411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::total 74092172492 # number of demand (read+write) MSHR miss cycles 155511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 763418000 # number of overall MSHR miss cycles 155611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 519315500 # number of overall MSHR miss cycles 155711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 19039385000 # number of overall MSHR miss cycles 155811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 53770053992 # number of overall MSHR miss cycles 155911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 66266397744 # number of overall MSHR miss cycles 156011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::total 140358570236 # number of overall MSHR miss cycles 156111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 185530000 # number of ReadReq MSHR uncacheable cycles 156211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2769951000 # number of ReadReq MSHR uncacheable cycles 156311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 2955481000 # number of ReadReq MSHR uncacheable cycles 156411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 185530000 # number of overall MSHR uncacheable cycles 156511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 2769951000 # number of overall MSHR uncacheable cycles 156611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::total 2955481000 # number of overall MSHR uncacheable cycles 156711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.035374 # mshr miss rate for ReadReq accesses 156811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.057866 # mshr miss rate for ReadReq accesses 156911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.040548 # mshr miss rate for ReadReq accesses 157011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses 157111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses 157210576Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 157310576Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 157411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999869 # mshr miss rate for UpgradeReq accesses 157511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999869 # mshr miss rate for UpgradeReq accesses 157611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999985 # mshr miss rate for SCUpgradeReq accesses 157711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999985 # mshr miss rate for SCUpgradeReq accesses 157810576Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 157910576Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 158011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.195572 # mshr miss rate for ReadExReq accesses 158111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.195572 # mshr miss rate for ReadExReq accesses 158211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.100281 # mshr miss rate for ReadCleanReq accesses 158311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.100281 # mshr miss rate for ReadCleanReq accesses 158411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.243030 # mshr miss rate for ReadSharedReq accesses 158511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.243030 # mshr miss rate for ReadSharedReq accesses 158611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.779439 # mshr miss rate for InvalidateReq accesses 158711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.779439 # mshr miss rate for InvalidateReq accesses 158811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.035374 # mshr miss rate for demand accesses 158911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.057866 # mshr miss rate for demand accesses 159011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.100281 # mshr miss rate for demand accesses 159111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.232190 # mshr miss rate for demand accesses 159211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::total 0.156971 # mshr miss rate for demand accesses 159311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.035374 # mshr miss rate for overall accesses 159411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.057866 # mshr miss rate for overall accesses 159511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.100281 # mshr miss rate for overall accesses 159611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.232190 # mshr miss rate for overall accesses 159710576Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 159811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::total 0.231066 # mshr miss rate for overall accesses 159911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 31470.772529 # average ReadReq mshr miss latency 160011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 43801.914642 # average ReadReq mshr miss latency 160111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 35519.009248 # average ReadReq mshr miss latency 160211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 69685.737512 # average HardPFReq mshr miss latency 160311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 69685.737512 # average HardPFReq mshr miss latency 160411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18689.969694 # average UpgradeReq mshr miss latency 160511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18689.969694 # average UpgradeReq mshr miss latency 160611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15574.182095 # average SCUpgradeReq mshr miss latency 160711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15574.182095 # average SCUpgradeReq mshr miss latency 160811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 339699.800000 # average SCUpgradeFailReq mshr miss latency 160911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 339699.800000 # average SCUpgradeFailReq mshr miss latency 161011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 53111.575687 # average ReadExReq mshr miss latency 161111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 53111.575687 # average ReadExReq mshr miss latency 161211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31515.273152 # average ReadCleanReq mshr miss latency 161311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31515.273152 # average ReadCleanReq mshr miss latency 161411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35793.164971 # average ReadSharedReq mshr miss latency 161511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35793.164971 # average ReadSharedReq mshr miss latency 161611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 35483.491366 # average InvalidateReq mshr miss latency 161711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 35483.491366 # average InvalidateReq mshr miss latency 161811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 31470.772529 # average overall mshr miss latency 161911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 43801.914642 # average overall mshr miss latency 162011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31515.273152 # average overall mshr miss latency 162111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 39124.985169 # average overall mshr miss latency 162211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36778.321675 # average overall mshr miss latency 162311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 31470.772529 # average overall mshr miss latency 162411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 43801.914642 # average overall mshr miss latency 162511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31515.273152 # average overall mshr miss latency 162611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 39124.985169 # average overall mshr miss latency 162711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 69685.737512 # average overall mshr miss latency 162811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::total 47330.602445 # average overall mshr miss latency 162911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88643.096034 # average ReadReq mshr uncacheable latency 163011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174837.530771 # average ReadReq mshr uncacheable latency 163111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164779.270740 # average ReadReq mshr uncacheable latency 163211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88643.096034 # average overall mshr uncacheable latency 163311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 83618.637928 # average overall mshr uncacheable latency 163411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 83917.232176 # average overall mshr uncacheable latency 163511860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_requests 26242800 # Total number of requests made to the snoop filter. 163611860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_requests 13504787 # Number of requests hitting in the snoop filter with a single holder of the requested data. 163711860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_requests 4079 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 163811860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_snoops 709472 # Total number of snoops made to the snoop filter. 163911860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_snoops 709425 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 164011860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 47 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 164111860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 164211860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 1004788 # Transaction distribution 164311860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 11688716 # Transaction distribution 164411860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 17283 # Transaction distribution 164511860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 17283 # Transaction distribution 164611860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackDirty 6246434 # Transaction distribution 164711860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackClean 8308001 # Transaction distribution 164811860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::CleanEvict 1424808 # Transaction distribution 164911860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::HardPFReq 1208828 # Transaction distribution 165011860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::HardPFResp 9 # Transaction distribution 165111860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 455562 # Transaction distribution 165211860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 363537 # Transaction distribution 165311860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 533487 # Transaction distribution 165411860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution 165511860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution 165611860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1384860 # Transaction distribution 165711860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1359346 # Transaction distribution 165811860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 6024837 # Transaction distribution 165911860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 5574197 # Transaction distribution 166011860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateReq 855548 # Transaction distribution 166111860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateResp 797069 # Transaction distribution 166211860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18077450 # Packet count per connected master and slave (bytes) 166311860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 21220350 # Packet count per connected master and slave (bytes) 166411860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 431264 # Packet count per connected master and slave (bytes) 166511860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1446232 # Packet count per connected master and slave (bytes) 166611860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count::total 41175296 # Packet count per connected master and slave (bytes) 166711860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 771132816 # Cumulative packet size per connected master and slave (bytes) 166811860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 809027527 # Cumulative packet size per connected master and slave (bytes) 166911860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1639096 # Cumulative packet size per connected master and slave (bytes) 167011860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5486072 # Cumulative packet size per connected master and slave (bytes) 167111860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size::total 1587285511 # Cumulative packet size per connected master and slave (bytes) 167211860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoops 6254740 # Total snoops (count) 167311860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopTraffic 129367088 # Total snoop traffic (bytes) 167411860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 20223636 # Request fanout histogram 167511860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 0.054517 # Request fanout histogram 167611860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.227045 # Request fanout histogram 167710576Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 167811860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 19121152 94.55% 94.55% # Request fanout histogram 167911860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 1102437 5.45% 100.00% # Request fanout histogram 168011860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 47 0.00% 100.00% # Request fanout histogram 168110576Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 168211138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 168310827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 168411860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 20223636 # Request fanout histogram 168511860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.reqLayer0.occupancy 26091767715 # Layer occupancy (ticks) 168611502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 168711860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopLayer0.occupancy 182386585 # Layer occupancy (ticks) 168810576Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 168911860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer0.occupancy 9045827975 # Layer occupancy (ticks) 169010576Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 169111860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer1.occupancy 9544267214 # Layer occupancy (ticks) 169210576Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 169311860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer2.occupancy 226891962 # Layer occupancy (ticks) 169410576Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 169511860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer3.occupancy 761324284 # Layer occupancy (ticks) 169610576Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 169711860Sandreas.hansson@arm.comsystem.cpu1.branchPred.lookups 124325317 # Number of BP lookups 169811860Sandreas.hansson@arm.comsystem.cpu1.branchPred.condPredicted 79272164 # Number of conditional branches predicted 169911860Sandreas.hansson@arm.comsystem.cpu1.branchPred.condIncorrect 6778632 # Number of conditional branches incorrect 170011860Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBLookups 83479161 # Number of BTB lookups 170111860Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBHits 47841396 # Number of BTB hits 170210576Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 170311860Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBHitPct 57.309388 # BTB Hit Percentage 170411860Sandreas.hansson@arm.comsystem.cpu1.branchPred.usedRAS 17874464 # Number of times the RAS was used to get a target. 170511860Sandreas.hansson@arm.comsystem.cpu1.branchPred.RASInCorrect 195085 # Number of incorrect RAS predictions. 170611860Sandreas.hansson@arm.comsystem.cpu1.branchPred.indirectLookups 4411145 # Number of indirect predictor lookups. 170711860Sandreas.hansson@arm.comsystem.cpu1.branchPred.indirectHits 2666966 # Number of indirect target hits. 170811860Sandreas.hansson@arm.comsystem.cpu1.branchPred.indirectMisses 1744179 # Number of indirect misses. 170911860Sandreas.hansson@arm.comsystem.cpu1.branchPredindirectMispredicted 432386 # Number of mispredicted indirect branches. 171011860Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 171110628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 171210628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 171310628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 171410628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 171510628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 171610628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 171710628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 171810628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 171910576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 172010576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 172110576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 172210576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 172310576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 172410576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 172510576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 172610576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 172710576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 172810576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 172910576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 173010576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 173110576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 173210576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 173310576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 173410576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 173510576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 173610576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 173710576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 173810576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 173910576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 174011860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 174111860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walks 580775 # Table walker walks requested 174211860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLong 580775 # Table walker walks initiated with long descriptors 174311860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level2 12302 # Level at which table walker walks with long descriptors terminate 174411860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level3 93041 # Level at which table walker walks with long descriptors terminate 174511860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksSquashedBefore 266909 # Table walks squashed before starting 174611860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 313866 # Table walker wait (enqueue to first request) latency 174711860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::mean 2454.023373 # Table walker wait (enqueue to first request) latency 174811860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::stdev 13953.006998 # Table walker wait (enqueue to first request) latency 174911860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0-65535 311371 99.21% 99.21% # Table walker wait (enqueue to first request) latency 175011860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::65536-131071 1689 0.54% 99.74% # Table walker wait (enqueue to first request) latency 175111860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::131072-196607 507 0.16% 99.90% # Table walker wait (enqueue to first request) latency 175211860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::196608-262143 189 0.06% 99.96% # Table walker wait (enqueue to first request) latency 175311860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::262144-327679 54 0.02% 99.98% # Table walker wait (enqueue to first request) latency 175411860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::327680-393215 44 0.01% 100.00% # Table walker wait (enqueue to first request) latency 175511860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::393216-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 175611860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::458752-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 175711860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency 175811860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::589824-655359 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 175911860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 313866 # Table walker wait (enqueue to first request) latency 176011860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::samples 295327 # Table walker service (enqueue to completion) latency 176111860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::mean 21717.315044 # Table walker service (enqueue to completion) latency 176211860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::gmean 18678.510143 # Table walker service (enqueue to completion) latency 176311860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::stdev 17673.432878 # Table walker service (enqueue to completion) latency 176411860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::0-65535 292731 99.12% 99.12% # Table walker service (enqueue to completion) latency 176511860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::65536-131071 1780 0.60% 99.72% # Table walker service (enqueue to completion) latency 176611860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::131072-196607 365 0.12% 99.85% # Table walker service (enqueue to completion) latency 176711860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::196608-262143 243 0.08% 99.93% # Table walker service (enqueue to completion) latency 176811860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::262144-327679 59 0.02% 99.95% # Table walker service (enqueue to completion) latency 176911860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::327680-393215 66 0.02% 99.97% # Table walker service (enqueue to completion) latency 177011860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::393216-458751 10 0.00% 99.98% # Table walker service (enqueue to completion) latency 177111860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::458752-524287 14 0.00% 99.98% # Table walker service (enqueue to completion) latency 177211860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::524288-589823 10 0.00% 99.98% # Table walker service (enqueue to completion) latency 177311860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::589824-655359 35 0.01% 100.00% # Table walker service (enqueue to completion) latency 177411860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::655360-720895 14 0.00% 100.00% # Table walker service (enqueue to completion) latency 177511860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::total 295327 # Table walker service (enqueue to completion) latency 177611860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::samples 389340230128 # Table walker pending requests distribution 177711860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::mean 0.666551 # Table walker pending requests distribution 177811860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::stdev 0.555298 # Table walker pending requests distribution 177911860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::0-1 388038620628 99.67% 99.67% # Table walker pending requests distribution 178011860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::2-3 674944000 0.17% 99.84% # Table walker pending requests distribution 178111860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::4-5 273419500 0.07% 99.91% # Table walker pending requests distribution 178211860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::6-7 140502000 0.04% 99.95% # Table walker pending requests distribution 178311860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::8-9 100194000 0.03% 99.97% # Table walker pending requests distribution 178411860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::10-11 59021000 0.02% 99.99% # Table walker pending requests distribution 178511860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::12-13 22755500 0.01% 99.99% # Table walker pending requests distribution 178611860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::14-15 30241000 0.01% 100.00% # Table walker pending requests distribution 178711860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::16-17 482500 0.00% 100.00% # Table walker pending requests distribution 178811860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::18-19 50000 0.00% 100.00% # Table walker pending requests distribution 178911860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::total 389340230128 # Table walker pending requests distribution 179011860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 93042 88.32% 88.32% # Table walker page sizes translated 179111860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::2M 12302 11.68% 100.00% # Table walker page sizes translated 179211860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 105344 # Table walker page sizes translated 179311860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 580775 # Table walker requests started/completed, data/inst 179410628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 179511860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 580775 # Table walker requests started/completed, data/inst 179611860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 105344 # Table walker requests started/completed, data/inst 179710628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 179811860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 105344 # Table walker requests started/completed, data/inst 179911860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 686119 # Table walker requests started/completed, data/inst 180010576Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_hits 0 # ITB inst hits 180110576Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_misses 0 # ITB inst misses 180211860Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 97816184 # DTB read hits 180311860Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 397931 # DTB read misses 180411860Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 81264416 # DTB write hits 180511860Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 182844 # DTB write misses 180611860Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed 180710576Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 180811860Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 47990 # Number of times TLB was flushed by MVA & ASID 180911860Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_asid 1104 # Number of times TLB was flushed by ASID 181011860Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_entries 36337 # Number of entries that have been flushed from TLB 181111860Sandreas.hansson@arm.comsystem.cpu1.dtb.align_faults 714 # Number of TLB faults due to alignment restrictions 181211860Sandreas.hansson@arm.comsystem.cpu1.dtb.prefetch_faults 7662 # Number of TLB faults due to prefetch 181310576Sandreas.hansson@arm.comsystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 181411860Sandreas.hansson@arm.comsystem.cpu1.dtb.perms_faults 41901 # Number of TLB faults due to permissions restrictions 181511860Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 98214115 # DTB read accesses 181611860Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 81447260 # DTB write accesses 181710576Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 181811860Sandreas.hansson@arm.comsystem.cpu1.dtb.hits 179080600 # DTB hits 181911860Sandreas.hansson@arm.comsystem.cpu1.dtb.misses 580775 # DTB misses 182011860Sandreas.hansson@arm.comsystem.cpu1.dtb.accesses 179661375 # DTB accesses 182111860Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 182210628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 182310628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 182410628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 182510628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 182610628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 182710628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 182810628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 182910628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 183010576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 183110576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 183210576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 183310576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 183410576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 183510576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 183610576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 183710576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 183810576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 183910576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 184010576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 184110576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 184210576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 184310576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 184410576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 184510576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 184610576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 184710576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 184810576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 184910576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 185010576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 185111860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 185211860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walks 87135 # Table walker walks requested 185311860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLong 87135 # Table walker walks initiated with long descriptors 185411860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level2 1092 # Level at which table walker walks with long descriptors terminate 185511860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level3 62581 # Level at which table walker walks with long descriptors terminate 185611860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksSquashedBefore 10397 # Table walks squashed before starting 185711860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 76738 # Table walker wait (enqueue to first request) latency 185811860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::mean 1034.422320 # Table walker wait (enqueue to first request) latency 185911860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::stdev 9201.232348 # Table walker wait (enqueue to first request) latency 186011860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::0-65535 76494 99.68% 99.68% # Table walker wait (enqueue to first request) latency 186111860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::65536-131071 186 0.24% 99.92% # Table walker wait (enqueue to first request) latency 186211860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::131072-196607 34 0.04% 99.97% # Table walker wait (enqueue to first request) latency 186311860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::196608-262143 9 0.01% 99.98% # Table walker wait (enqueue to first request) latency 186411860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::262144-327679 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency 186511860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::327680-393215 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency 186611860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 186711860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 186811860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 76738 # Table walker wait (enqueue to first request) latency 186911860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::samples 74070 # Table walker service (enqueue to completion) latency 187011860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::mean 25472.262724 # Table walker service (enqueue to completion) latency 187111860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::gmean 22851.948587 # Table walker service (enqueue to completion) latency 187211860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::stdev 20227.385308 # Table walker service (enqueue to completion) latency 187311860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::0-65535 72813 98.30% 98.30% # Table walker service (enqueue to completion) latency 187411860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::65536-131071 775 1.05% 99.35% # Table walker service (enqueue to completion) latency 187511860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::131072-196607 316 0.43% 99.78% # Table walker service (enqueue to completion) latency 187611860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::196608-262143 87 0.12% 99.89% # Table walker service (enqueue to completion) latency 187711860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::262144-327679 33 0.04% 99.94% # Table walker service (enqueue to completion) latency 187811860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::327680-393215 20 0.03% 99.96% # Table walker service (enqueue to completion) latency 187911860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.98% # Table walker service (enqueue to completion) latency 188011860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.98% # Table walker service (enqueue to completion) latency 188111860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::589824-655359 17 0.02% 100.00% # Table walker service (enqueue to completion) latency 188211860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::total 74070 # Table walker service (enqueue to completion) latency 188311860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::samples 329207699984 # Table walker pending requests distribution 188411860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::mean 0.888226 # Table walker pending requests distribution 188511860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::stdev 0.315322 # Table walker pending requests distribution 188611860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::0 36820179964 11.18% 11.18% # Table walker pending requests distribution 188711860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::1 292365319520 88.81% 99.99% # Table walker pending requests distribution 188811860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::2 21267000 0.01% 100.00% # Table walker pending requests distribution 188911860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::3 903500 0.00% 100.00% # Table walker pending requests distribution 189011860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::4 30000 0.00% 100.00% # Table walker pending requests distribution 189111860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::total 329207699984 # Table walker pending requests distribution 189211860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 62581 98.28% 98.28% # Table walker page sizes translated 189311860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::2M 1092 1.72% 100.00% # Table walker page sizes translated 189411860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 63673 # Table walker page sizes translated 189510628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 189611860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 87135 # Table walker requests started/completed, data/inst 189711860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 87135 # Table walker requests started/completed, data/inst 189810628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 189911860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63673 # Table walker requests started/completed, data/inst 190011860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 63673 # Table walker requests started/completed, data/inst 190111860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 150808 # Table walker requests started/completed, data/inst 190211860Sandreas.hansson@arm.comsystem.cpu1.itb.inst_hits 190777093 # ITB inst hits 190311860Sandreas.hansson@arm.comsystem.cpu1.itb.inst_misses 87135 # ITB inst misses 190410576Sandreas.hansson@arm.comsystem.cpu1.itb.read_hits 0 # DTB read hits 190510576Sandreas.hansson@arm.comsystem.cpu1.itb.read_misses 0 # DTB read misses 190610576Sandreas.hansson@arm.comsystem.cpu1.itb.write_hits 0 # DTB write hits 190710576Sandreas.hansson@arm.comsystem.cpu1.itb.write_misses 0 # DTB write misses 190811860Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed 190910576Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 191011860Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 47990 # Number of times TLB was flushed by MVA & ASID 191111860Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_asid 1104 # Number of times TLB was flushed by ASID 191211860Sandreas.hansson@arm.comsystem.cpu1.itb.flush_entries 25727 # Number of entries that have been flushed from TLB 191310576Sandreas.hansson@arm.comsystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 191410576Sandreas.hansson@arm.comsystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 191510576Sandreas.hansson@arm.comsystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 191611860Sandreas.hansson@arm.comsystem.cpu1.itb.perms_faults 222647 # Number of TLB faults due to permissions restrictions 191710576Sandreas.hansson@arm.comsystem.cpu1.itb.read_accesses 0 # DTB read accesses 191810576Sandreas.hansson@arm.comsystem.cpu1.itb.write_accesses 0 # DTB write accesses 191911860Sandreas.hansson@arm.comsystem.cpu1.itb.inst_accesses 190864228 # ITB inst accesses 192011860Sandreas.hansson@arm.comsystem.cpu1.itb.hits 190777093 # DTB hits 192111860Sandreas.hansson@arm.comsystem.cpu1.itb.misses 87135 # DTB misses 192211860Sandreas.hansson@arm.comsystem.cpu1.itb.accesses 190864228 # DTB accesses 192311860Sandreas.hansson@arm.comsystem.cpu1.numPwrStateTransitions 27368 # Number of power state transitions 192411860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::samples 13684 # Distribution of time spent in the clock gated state 192511860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::mean 3437541610.585575 # Distribution of time spent in the clock gated state 192611860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::stdev 87855050570.390015 # Distribution of time spent in the clock gated state 192711860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::underflows 3277 23.95% 23.95% # Distribution of time spent in the clock gated state 192811860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::1000-5e+10 10379 75.85% 99.80% # Distribution of time spent in the clock gated state 192911860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::5e+10-1e+11 4 0.03% 99.82% # Distribution of time spent in the clock gated state 193011860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state 193111860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.02% 99.86% # Distribution of time spent in the clock gated state 193211860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state 193311860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::6.5e+11-7e+11 2 0.01% 99.89% # Distribution of time spent in the clock gated state 193411860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::8.5e+11-9e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state 193511860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state 193611606Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 193711860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::max_value 7351150614736 # Distribution of time spent in the clock gated state 193811860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::total 13684 # Distribution of time spent in the clock gated state 193911860Sandreas.hansson@arm.comsystem.cpu1.pwrStateResidencyTicks::ON 302603854747 # Cumulative time (in ticks) in various power states 194011860Sandreas.hansson@arm.comsystem.cpu1.pwrStateResidencyTicks::CLK_GATED 47039319399253 # Cumulative time (in ticks) in various power states 194111860Sandreas.hansson@arm.comsystem.cpu1.numCycles 605218102 # number of cpu cycles simulated 194210576Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 194310576Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 194411860Sandreas.hansson@arm.comsystem.cpu1.fetch.icacheStallCycles 90677216 # Number of cycles fetch is stalled on an Icache miss 194511860Sandreas.hansson@arm.comsystem.cpu1.fetch.Insts 553360207 # Number of instructions fetch has processed 194611860Sandreas.hansson@arm.comsystem.cpu1.fetch.Branches 124325317 # Number of branches that fetch encountered 194711860Sandreas.hansson@arm.comsystem.cpu1.fetch.predictedBranches 68382826 # Number of branches that fetch has predicted taken 194811860Sandreas.hansson@arm.comsystem.cpu1.fetch.Cycles 474472155 # Number of cycles fetch has run and was not squashing or blocked 194911860Sandreas.hansson@arm.comsystem.cpu1.fetch.SquashCycles 14605284 # Number of cycles fetch has spent squashing 195011860Sandreas.hansson@arm.comsystem.cpu1.fetch.TlbCycles 1912826 # Number of cycles fetch has spent waiting for tlb 195111860Sandreas.hansson@arm.comsystem.cpu1.fetch.MiscStallCycles 316489 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 195211860Sandreas.hansson@arm.comsystem.cpu1.fetch.PendingTrapStallCycles 6235887 # Number of stall cycles due to pending traps 195311860Sandreas.hansson@arm.comsystem.cpu1.fetch.PendingQuiesceStallCycles 776312 # Number of stall cycles due to pending quiesce instructions 195411860Sandreas.hansson@arm.comsystem.cpu1.fetch.IcacheWaitRetryStallCycles 869780 # Number of stall cycles due to full MSHR 195511860Sandreas.hansson@arm.comsystem.cpu1.fetch.CacheLines 190532631 # Number of cache lines fetched 195611860Sandreas.hansson@arm.comsystem.cpu1.fetch.IcacheSquashes 1731041 # Number of outstanding Icache misses that were squashed 195711860Sandreas.hansson@arm.comsystem.cpu1.fetch.ItlbSquashes 28903 # Number of outstanding ITLB misses that were squashed 195811860Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::samples 582563307 # Number of instructions fetched each cycle (Total) 195911860Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::mean 1.126942 # Number of instructions fetched each cycle (Total) 196011860Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::stdev 1.253057 # Number of instructions fetched each cycle (Total) 196110576Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 196211860Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::0 272142185 46.71% 46.71% # Number of instructions fetched each cycle (Total) 196311860Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::1 117259342 20.13% 66.84% # Number of instructions fetched each cycle (Total) 196411860Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::2 40229436 6.91% 73.75% # Number of instructions fetched each cycle (Total) 196511860Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::3 152932344 26.25% 100.00% # Number of instructions fetched each cycle (Total) 196610576Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 196710576Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 196810576Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 196911860Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::total 582563307 # Number of instructions fetched each cycle (Total) 197011860Sandreas.hansson@arm.comsystem.cpu1.fetch.branchRate 0.205422 # Number of branch fetches per cycle 197111860Sandreas.hansson@arm.comsystem.cpu1.fetch.rate 0.914315 # Number of inst fetches per cycle 197211860Sandreas.hansson@arm.comsystem.cpu1.decode.IdleCycles 100710093 # Number of cycles decode is idle 197311860Sandreas.hansson@arm.comsystem.cpu1.decode.BlockedCycles 231252575 # Number of cycles decode is blocked 197411860Sandreas.hansson@arm.comsystem.cpu1.decode.RunCycles 221227930 # Number of cycles decode is running 197511860Sandreas.hansson@arm.comsystem.cpu1.decode.UnblockCycles 24164908 # Number of cycles decode is unblocking 197611860Sandreas.hansson@arm.comsystem.cpu1.decode.SquashCycles 5207801 # Number of cycles decode is squashing 197711860Sandreas.hansson@arm.comsystem.cpu1.decode.BranchResolved 44439760 # Number of times decode resolved a branch 197811860Sandreas.hansson@arm.comsystem.cpu1.decode.BranchMispred 2135059 # Number of times decode detected a branch misprediction 197911860Sandreas.hansson@arm.comsystem.cpu1.decode.DecodedInsts 575305987 # Number of instructions handled by decode 198011860Sandreas.hansson@arm.comsystem.cpu1.decode.SquashedInsts 23412205 # Number of squashed instructions handled by decode 198111860Sandreas.hansson@arm.comsystem.cpu1.rename.SquashCycles 5207801 # Number of cycles rename is squashing 198211860Sandreas.hansson@arm.comsystem.cpu1.rename.IdleCycles 129334574 # Number of cycles rename is idle 198311860Sandreas.hansson@arm.comsystem.cpu1.rename.BlockCycles 47434760 # Number of cycles rename is blocking 198411860Sandreas.hansson@arm.comsystem.cpu1.rename.serializeStallCycles 137391497 # count of cycles rename stalled for serializing inst 198511860Sandreas.hansson@arm.comsystem.cpu1.rename.RunCycles 216168101 # Number of cycles rename is running 198611860Sandreas.hansson@arm.comsystem.cpu1.rename.UnblockCycles 47026574 # Number of cycles rename is unblocking 198711860Sandreas.hansson@arm.comsystem.cpu1.rename.RenamedInsts 558184675 # Number of instructions processed by rename 198811860Sandreas.hansson@arm.comsystem.cpu1.rename.SquashedInsts 6143864 # Number of squashed instructions processed by rename 198911860Sandreas.hansson@arm.comsystem.cpu1.rename.ROBFullEvents 9881225 # Number of times rename has blocked due to ROB full 199011860Sandreas.hansson@arm.comsystem.cpu1.rename.IQFullEvents 309237 # Number of times rename has blocked due to IQ full 199111860Sandreas.hansson@arm.comsystem.cpu1.rename.LQFullEvents 251476 # Number of times rename has blocked due to LQ full 199211860Sandreas.hansson@arm.comsystem.cpu1.rename.SQFullEvents 25589786 # Number of times rename has blocked due to SQ full 199311860Sandreas.hansson@arm.comsystem.cpu1.rename.FullRegisterEvents 13193 # Number of times there has been no free registers 199411860Sandreas.hansson@arm.comsystem.cpu1.rename.RenamedOperands 510403185 # Number of destination operands rename has renamed 199511860Sandreas.hansson@arm.comsystem.cpu1.rename.RenameLookups 786411891 # Number of register rename lookups that rename has made 199611860Sandreas.hansson@arm.comsystem.cpu1.rename.int_rename_lookups 655895321 # Number of integer rename lookups 199711860Sandreas.hansson@arm.comsystem.cpu1.rename.fp_rename_lookups 811726 # Number of floating rename lookups 199811860Sandreas.hansson@arm.comsystem.cpu1.rename.CommittedMaps 453487095 # Number of HB maps that are committed 199911860Sandreas.hansson@arm.comsystem.cpu1.rename.UndoneMaps 56916084 # Number of HB maps that are undone due to squashing 200011860Sandreas.hansson@arm.comsystem.cpu1.rename.serializingInsts 6219044 # count of serializing insts renamed 200111860Sandreas.hansson@arm.comsystem.cpu1.rename.tempSerializingInsts 4304916 # count of temporary serializing insts renamed 200211860Sandreas.hansson@arm.comsystem.cpu1.rename.skidInsts 51458924 # count of insts added to the skid buffer 200311860Sandreas.hansson@arm.comsystem.cpu1.memDep0.insertedLoads 98128925 # Number of loads inserted to the mem dependence unit. 200411860Sandreas.hansson@arm.comsystem.cpu1.memDep0.insertedStores 84474197 # Number of stores inserted to the mem dependence unit. 200511860Sandreas.hansson@arm.comsystem.cpu1.memDep0.conflictingLoads 8967706 # Number of conflicting loads. 200611860Sandreas.hansson@arm.comsystem.cpu1.memDep0.conflictingStores 7764120 # Number of conflicting stores. 200711860Sandreas.hansson@arm.comsystem.cpu1.iq.iqInstsAdded 545083370 # Number of instructions added to the IQ (excludes non-spec) 200811860Sandreas.hansson@arm.comsystem.cpu1.iq.iqNonSpecInstsAdded 6336595 # Number of non-speculative instructions added to the IQ 200911860Sandreas.hansson@arm.comsystem.cpu1.iq.iqInstsIssued 540345314 # Number of instructions issued 201011860Sandreas.hansson@arm.comsystem.cpu1.iq.iqSquashedInstsIssued 2650065 # Number of squashed instructions issued 201111860Sandreas.hansson@arm.comsystem.cpu1.iq.iqSquashedInstsExamined 53579246 # Number of squashed instructions iterated over during squash; mainly for profiling 201211860Sandreas.hansson@arm.comsystem.cpu1.iq.iqSquashedOperandsExamined 34592760 # Number of squashed operands that are examined and possibly removed from graph 201311860Sandreas.hansson@arm.comsystem.cpu1.iq.iqSquashedNonSpecRemoved 257601 # Number of squashed non-spec instructions that were removed 201411860Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::samples 582563307 # Number of insts issued each cycle 201511860Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::mean 0.927531 # Number of insts issued each cycle 201611860Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::stdev 1.122571 # Number of insts issued each cycle 201710576Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 201811860Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::0 303220433 52.05% 52.05% # Number of insts issued each cycle 201911860Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::1 97196070 16.68% 68.73% # Number of insts issued each cycle 202011860Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::2 110913519 19.04% 87.77% # Number of insts issued each cycle 202111860Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::3 63614426 10.92% 98.69% # Number of insts issued each cycle 202211860Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::4 7615367 1.31% 100.00% # Number of insts issued each cycle 202311860Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::5 3492 0.00% 100.00% # Number of insts issued each cycle 202410628Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 202510576Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 202610576Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 202710576Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 202810576Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 202910628Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 203011860Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::total 582563307 # Number of insts issued each cycle 203110576Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 203211860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::IntAlu 57271310 43.60% 43.60% # attempts to use FU when none available 203311860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::IntMult 51119 0.04% 43.64% # attempts to use FU when none available 203411860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::IntDiv 18601 0.01% 43.65% # attempts to use FU when none available 203511860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.65% # attempts to use FU when none available 203611860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.65% # attempts to use FU when none available 203711860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.65% # attempts to use FU when none available 203811860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatMult 0 0.00% 43.65% # attempts to use FU when none available 203911860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 43.65% # attempts to use FU when none available 204011860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.65% # attempts to use FU when none available 204111860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatMisc 112 0.00% 43.65% # attempts to use FU when none available 204211860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.65% # attempts to use FU when none available 204311860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.65% # attempts to use FU when none available 204411860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.65% # attempts to use FU when none available 204511860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.65% # attempts to use FU when none available 204611860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.65% # attempts to use FU when none available 204711860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.65% # attempts to use FU when none available 204811860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.65% # attempts to use FU when none available 204911860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdMult 0 0.00% 43.65% # attempts to use FU when none available 205011860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.65% # attempts to use FU when none available 205111860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdShift 0 0.00% 43.65% # attempts to use FU when none available 205211860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.65% # attempts to use FU when none available 205311860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.65% # attempts to use FU when none available 205411860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.65% # attempts to use FU when none available 205511860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.65% # attempts to use FU when none available 205611860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.65% # attempts to use FU when none available 205711860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.65% # attempts to use FU when none available 205811860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.65% # attempts to use FU when none available 205911860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 43.65% # attempts to use FU when none available 206011860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.65% # attempts to use FU when none available 206111860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.65% # attempts to use FU when none available 206211860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.65% # attempts to use FU when none available 206311860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::MemRead 35025270 26.66% 70.31% # attempts to use FU when none available 206411860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::MemWrite 38581798 29.37% 99.68% # attempts to use FU when none available 206511860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatMemRead 47664 0.04% 99.72% # attempts to use FU when none available 206611860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatMemWrite 368619 0.28% 100.00% # attempts to use FU when none available 206710576Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 206810576Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 206911860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::No_OpClass 76 0.00% 0.00% # Type of FU issued 207011860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::IntAlu 355477037 65.79% 65.79% # Type of FU issued 207111860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::IntMult 1278002 0.24% 66.02% # Type of FU issued 207211860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::IntDiv 69863 0.01% 66.04% # Type of FU issued 207311860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatAdd 8 0.00% 66.04% # Type of FU issued 207411860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.04% # Type of FU issued 207511860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.04% # Type of FU issued 207611860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.04% # Type of FU issued 207711860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 66.04% # Type of FU issued 207811860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.04% # Type of FU issued 207911860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatMisc 79928 0.01% 66.05% # Type of FU issued 208011860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.05% # Type of FU issued 208111860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.05% # Type of FU issued 208211860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.05% # Type of FU issued 208311860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdAlu 1 0.00% 66.05% # Type of FU issued 208411860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.05% # Type of FU issued 208511860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.05% # Type of FU issued 208611860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.05% # Type of FU issued 208711860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.05% # Type of FU issued 208811860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.05% # Type of FU issued 208911860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.05% # Type of FU issued 209011860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.05% # Type of FU issued 209111860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.05% # Type of FU issued 209211860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.05% # Type of FU issued 209311860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.05% # Type of FU issued 209411860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.05% # Type of FU issued 209511860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.05% # Type of FU issued 209611860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.05% # Type of FU issued 209711860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.05% # Type of FU issued 209811860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.05% # Type of FU issued 209911860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.05% # Type of FU issued 210011860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.05% # Type of FU issued 210111860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::MemRead 100880874 18.67% 84.72% # Type of FU issued 210211860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::MemWrite 82125393 15.20% 99.92% # Type of FU issued 210311860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatMemRead 69486 0.01% 99.93% # Type of FU issued 210411860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatMemWrite 364646 0.07% 100.00% # Type of FU issued 210510576Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 210610576Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 210711860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::total 540345314 # Type of FU issued 210811860Sandreas.hansson@arm.comsystem.cpu1.iq.rate 0.892811 # Inst issue rate 210911860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_busy_cnt 131364493 # FU busy when requested 211011860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_busy_rate 0.243112 # FU busy rate (busy events/executed inst) 211111860Sandreas.hansson@arm.comsystem.cpu1.iq.int_inst_queue_reads 1795817951 # Number of integer instruction queue reads 211211860Sandreas.hansson@arm.comsystem.cpu1.iq.int_inst_queue_writes 604594628 # Number of integer instruction queue writes 211311860Sandreas.hansson@arm.comsystem.cpu1.iq.int_inst_queue_wakeup_accesses 523100921 # Number of integer instruction queue wakeup accesses 211411860Sandreas.hansson@arm.comsystem.cpu1.iq.fp_inst_queue_reads 1450540 # Number of floating instruction queue reads 211511860Sandreas.hansson@arm.comsystem.cpu1.iq.fp_inst_queue_writes 543567 # Number of floating instruction queue writes 211611860Sandreas.hansson@arm.comsystem.cpu1.iq.fp_inst_queue_wakeup_accesses 507957 # Number of floating instruction queue wakeup accesses 211711860Sandreas.hansson@arm.comsystem.cpu1.iq.int_alu_accesses 670779267 # Number of integer alu accesses 211811860Sandreas.hansson@arm.comsystem.cpu1.iq.fp_alu_accesses 930464 # Number of floating point alu accesses 211911860Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.forwLoads 2614124 # Number of loads that had data forwarded from stores 212010576Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 212111860Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.squashedLoads 12461558 # Number of loads squashed 212211860Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.ignoredResponses 17016 # Number of memory responses ignored because the instruction is squashed 212311860Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.memOrderViolation 140230 # Number of memory ordering violations 212411860Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.squashedStores 5490502 # Number of stores squashed 212510576Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 212610576Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 212711860Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.rescheduledLoads 2570995 # Number of loads that were rescheduled 212811860Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.cacheBlocked 4304841 # Number of times an access to memory failed due to the cache being blocked 212910576Sandreas.hansson@arm.comsystem.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 213011860Sandreas.hansson@arm.comsystem.cpu1.iew.iewSquashCycles 5207801 # Number of cycles IEW is squashing 213111860Sandreas.hansson@arm.comsystem.cpu1.iew.iewBlockCycles 6764064 # Number of cycles IEW is blocking 213211860Sandreas.hansson@arm.comsystem.cpu1.iew.iewUnblockCycles 1538743 # Number of cycles IEW is unblocking 213311860Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispatchedInsts 551558167 # Number of instructions dispatched to IQ 213410576Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 213511860Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispLoadInsts 98128925 # Number of dispatched load instructions 213611860Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispStoreInsts 84474197 # Number of dispatched store instructions 213711860Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispNonSpecInsts 4043182 # Number of dispatched non-speculative instructions 213811860Sandreas.hansson@arm.comsystem.cpu1.iew.iewIQFullEvents 70701 # Number of times the IQ has become full, causing a stall 213911860Sandreas.hansson@arm.comsystem.cpu1.iew.iewLSQFullEvents 1397089 # Number of times the LSQ has become full, causing a stall 214011860Sandreas.hansson@arm.comsystem.cpu1.iew.memOrderViolationEvents 140230 # Number of memory order violations 214111860Sandreas.hansson@arm.comsystem.cpu1.iew.predictedTakenIncorrect 1929682 # Number of branches that were predicted taken incorrectly 214211860Sandreas.hansson@arm.comsystem.cpu1.iew.predictedNotTakenIncorrect 3114694 # Number of branches that were predicted not taken incorrectly 214311860Sandreas.hansson@arm.comsystem.cpu1.iew.branchMispredicts 5044376 # Number of branch mispredicts detected at execute 214411860Sandreas.hansson@arm.comsystem.cpu1.iew.iewExecutedInsts 532413736 # Number of executed instructions 214511860Sandreas.hansson@arm.comsystem.cpu1.iew.iewExecLoadInsts 97811900 # Number of load instructions executed 214611860Sandreas.hansson@arm.comsystem.cpu1.iew.iewExecSquashedInsts 7363284 # Number of squashed instructions skipped in execute 214710576Sandreas.hansson@arm.comsystem.cpu1.iew.exec_swp 0 # number of swp insts executed 214811860Sandreas.hansson@arm.comsystem.cpu1.iew.exec_nop 138202 # number of nop insts executed 214911860Sandreas.hansson@arm.comsystem.cpu1.iew.exec_refs 179076621 # number of memory reference insts executed 215011860Sandreas.hansson@arm.comsystem.cpu1.iew.exec_branches 97312103 # Number of branches executed 215111860Sandreas.hansson@arm.comsystem.cpu1.iew.exec_stores 81264721 # Number of stores executed 215211860Sandreas.hansson@arm.comsystem.cpu1.iew.exec_rate 0.879706 # Inst execution rate 215311860Sandreas.hansson@arm.comsystem.cpu1.iew.wb_sent 524373694 # cumulative count of insts sent to commit 215411860Sandreas.hansson@arm.comsystem.cpu1.iew.wb_count 523608878 # cumulative count of insts written-back 215511860Sandreas.hansson@arm.comsystem.cpu1.iew.wb_producers 254758095 # num instructions producing a value 215611860Sandreas.hansson@arm.comsystem.cpu1.iew.wb_consumers 415275761 # num instructions consuming a value 215711860Sandreas.hansson@arm.comsystem.cpu1.iew.wb_rate 0.865157 # insts written-back per cycle 215811860Sandreas.hansson@arm.comsystem.cpu1.iew.wb_fanout 0.613467 # average fanout of values written-back 215911860Sandreas.hansson@arm.comsystem.cpu1.commit.commitSquashedInsts 46732947 # The number of squashed insts skipped by commit 216011860Sandreas.hansson@arm.comsystem.cpu1.commit.commitNonSpecStalls 6078994 # The number of times commit has been forced to stall to communicate backwards 216111860Sandreas.hansson@arm.comsystem.cpu1.commit.branchMispredicts 4683791 # The number of times a branch was mispredicted 216211860Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::samples 573586803 # Number of insts commited each cycle 216311860Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::mean 0.867943 # Number of insts commited each cycle 216411860Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::stdev 1.693393 # Number of insts commited each cycle 216510576Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 216611860Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::0 375218582 65.42% 65.42% # Number of insts commited each cycle 216711860Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::1 85397429 14.89% 80.30% # Number of insts commited each cycle 216811860Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::2 52348334 9.13% 89.43% # Number of insts commited each cycle 216911860Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::3 17503204 3.05% 92.48% # Number of insts commited each cycle 217011860Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::4 12415456 2.16% 94.65% # Number of insts commited each cycle 217111860Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::5 8370820 1.46% 96.11% # Number of insts commited each cycle 217211860Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::6 5748485 1.00% 97.11% # Number of insts commited each cycle 217311860Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::7 3445775 0.60% 97.71% # Number of insts commited each cycle 217411860Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::8 13138718 2.29% 100.00% # Number of insts commited each cycle 217510576Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 217610576Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 217710576Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 217811860Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::total 573586803 # Number of insts commited each cycle 217911860Sandreas.hansson@arm.comsystem.cpu1.commit.committedInsts 416374803 # Number of instructions committed 218011860Sandreas.hansson@arm.comsystem.cpu1.commit.committedOps 497840712 # Number of ops (including micro ops) committed 218110576Sandreas.hansson@arm.comsystem.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 218211860Sandreas.hansson@arm.comsystem.cpu1.commit.refs 164651061 # Number of memory references committed 218311860Sandreas.hansson@arm.comsystem.cpu1.commit.loads 85667366 # Number of loads committed 218411860Sandreas.hansson@arm.comsystem.cpu1.commit.membars 3698541 # Number of memory barriers committed 218511860Sandreas.hansson@arm.comsystem.cpu1.commit.branches 91988554 # Number of branches committed 218611860Sandreas.hansson@arm.comsystem.cpu1.commit.fp_insts 499479 # Number of committed floating point instructions. 218711860Sandreas.hansson@arm.comsystem.cpu1.commit.int_insts 463071817 # Number of committed integer instructions. 218811860Sandreas.hansson@arm.comsystem.cpu1.commit.function_calls 13152854 # Number of function calls committed. 218910576Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 219011860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::IntAlu 332017365 66.69% 66.69% # Class of committed instruction 219111860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::IntMult 1043826 0.21% 66.90% # Class of committed instruction 219211860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::IntDiv 55377 0.01% 66.91% # Class of committed instruction 219311860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatAdd 0 0.00% 66.91% # Class of committed instruction 219411860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatCmp 0 0.00% 66.91% # Class of committed instruction 219511860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatCvt 0 0.00% 66.91% # Class of committed instruction 219611860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatMult 0 0.00% 66.91% # Class of committed instruction 219711860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 66.91% # Class of committed instruction 219811860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatDiv 0 0.00% 66.91% # Class of committed instruction 219911860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatMisc 73083 0.01% 66.93% # Class of committed instruction 220011860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 66.93% # Class of committed instruction 220111860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdAdd 0 0.00% 66.93% # Class of committed instruction 220211860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 66.93% # Class of committed instruction 220311860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdAlu 0 0.00% 66.93% # Class of committed instruction 220411860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdCmp 0 0.00% 66.93% # Class of committed instruction 220511860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdCvt 0 0.00% 66.93% # Class of committed instruction 220611860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdMisc 0 0.00% 66.93% # Class of committed instruction 220711860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdMult 0 0.00% 66.93% # Class of committed instruction 220811860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 66.93% # Class of committed instruction 220911860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdShift 0 0.00% 66.93% # Class of committed instruction 221011860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 66.93% # Class of committed instruction 221111860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 66.93% # Class of committed instruction 221211860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 66.93% # Class of committed instruction 221311860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 66.93% # Class of committed instruction 221411860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 66.93% # Class of committed instruction 221511860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 66.93% # Class of committed instruction 221611860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 66.93% # Class of committed instruction 221711860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 66.93% # Class of committed instruction 221811860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 66.93% # Class of committed instruction 221911860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.93% # Class of committed instruction 222011860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.93% # Class of committed instruction 222111860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::MemRead 85601974 17.19% 84.12% # Class of committed instruction 222211860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::MemWrite 78622691 15.79% 99.91% # Class of committed instruction 222311860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatMemRead 65392 0.01% 99.93% # Class of committed instruction 222411860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatMemWrite 361004 0.07% 100.00% # Class of committed instruction 222510576Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 222610576Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 222711860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::total 497840712 # Class of committed instruction 222811860Sandreas.hansson@arm.comsystem.cpu1.commit.bw_lim_events 13138718 # number cycles where commit BW limit reached 222911860Sandreas.hansson@arm.comsystem.cpu1.rob.rob_reads 1100782906 # The number of ROB reads 223011860Sandreas.hansson@arm.comsystem.cpu1.rob.rob_writes 1098088032 # The number of ROB writes 223111860Sandreas.hansson@arm.comsystem.cpu1.timesIdled 993023 # Number of times that the entire CPU went into an idle state and unscheduled itself 223211860Sandreas.hansson@arm.comsystem.cpu1.idleCycles 22654795 # Total number of cycles that the CPU has spent unscheduled due to idling 223311860Sandreas.hansson@arm.comsystem.cpu1.quiesceCycles 94078628435 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 223411860Sandreas.hansson@arm.comsystem.cpu1.committedInsts 416374803 # Number of Instructions Simulated 223511860Sandreas.hansson@arm.comsystem.cpu1.committedOps 497840712 # Number of Ops (including micro ops) Simulated 223611860Sandreas.hansson@arm.comsystem.cpu1.cpi 1.453542 # CPI: Cycles Per Instruction 223711860Sandreas.hansson@arm.comsystem.cpu1.cpi_total 1.453542 # CPI: Total CPI of All Threads 223811860Sandreas.hansson@arm.comsystem.cpu1.ipc 0.687975 # IPC: Instructions Per Cycle 223911860Sandreas.hansson@arm.comsystem.cpu1.ipc_total 0.687975 # IPC: Total IPC of All Threads 224011860Sandreas.hansson@arm.comsystem.cpu1.int_regfile_reads 625781479 # number of integer regfile reads 224111860Sandreas.hansson@arm.comsystem.cpu1.int_regfile_writes 379830432 # number of integer regfile writes 224211860Sandreas.hansson@arm.comsystem.cpu1.fp_regfile_reads 798661 # number of floating regfile reads 224311860Sandreas.hansson@arm.comsystem.cpu1.fp_regfile_writes 473896 # number of floating regfile writes 224411860Sandreas.hansson@arm.comsystem.cpu1.cc_regfile_reads 94918566 # number of cc regfile reads 224511860Sandreas.hansson@arm.comsystem.cpu1.cc_regfile_writes 95638413 # number of cc regfile writes 224611860Sandreas.hansson@arm.comsystem.cpu1.misc_regfile_reads 1053266822 # number of misc regfile reads 224711860Sandreas.hansson@arm.comsystem.cpu1.misc_regfile_writes 6252018 # number of misc regfile writes 224811860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 224911860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 5530000 # number of replacements 225011860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 456.074004 # Cycle average of tags in use 225111860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 153151228 # Total number of references to valid blocks. 225211860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 5530512 # Sample count of references to valid blocks. 225311860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 27.692052 # Average number of references to valid blocks. 225411860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 8516003368500 # Cycle when the warmup percentage was hit. 225511860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 456.074004 # Average occupied blocks per requestor 225611860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.890770 # Average percentage of cache occupancy 225711860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.890770 # Average percentage of cache occupancy 225811754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 225911860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id 226011860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 402 # Occupied blocks per task id 226111860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id 226211754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 226311860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 341526918 # Number of tag accesses 226411860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 341526918 # Number of data accesses 226511860Sandreas.hansson@arm.comsystem.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 226611860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 79602961 # number of ReadReq hits 226711860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 79602961 # number of ReadReq hits 226811860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 68799990 # number of WriteReq hits 226911860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 68799990 # number of WriteReq hits 227011860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 187687 # number of SoftPFReq hits 227111860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 187687 # number of SoftPFReq hits 227211860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::cpu1.data 159948 # number of WriteLineReq hits 227311860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::total 159948 # number of WriteLineReq hits 227411860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1827869 # number of LoadLockedReq hits 227511860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 1827869 # number of LoadLockedReq hits 227611860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 1836377 # number of StoreCondReq hits 227711860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 1836377 # number of StoreCondReq hits 227811860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 148562899 # number of demand (read+write) hits 227911860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 148562899 # number of demand (read+write) hits 228011860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 148750586 # number of overall hits 228111860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 148750586 # number of overall hits 228211860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 6412648 # number of ReadReq misses 228311860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 6412648 # number of ReadReq misses 228411860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 7514708 # number of WriteReq misses 228511860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 7514708 # number of WriteReq misses 228611860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 707982 # number of SoftPFReq misses 228711860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 707982 # number of SoftPFReq misses 228811860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::cpu1.data 465981 # number of WriteLineReq misses 228911860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::total 465981 # number of WriteLineReq misses 229011860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 246351 # number of LoadLockedReq misses 229111860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 246351 # number of LoadLockedReq misses 229211860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 195484 # number of StoreCondReq misses 229311860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 195484 # number of StoreCondReq misses 229411860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 14393337 # number of demand (read+write) misses 229511860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 14393337 # number of demand (read+write) misses 229611860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 15101319 # number of overall misses 229711860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 15101319 # number of overall misses 229811860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 101710324000 # number of ReadReq miss cycles 229911860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 101710324000 # number of ReadReq miss cycles 230011860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 138164152559 # number of WriteReq miss cycles 230111860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 138164152559 # number of WriteReq miss cycles 230211860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10841403957 # number of WriteLineReq miss cycles 230311860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::total 10841403957 # number of WriteLineReq miss cycles 230411860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3505750500 # number of LoadLockedReq miss cycles 230511860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 3505750500 # number of LoadLockedReq miss cycles 230611860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4668207500 # number of StoreCondReq miss cycles 230711860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 4668207500 # number of StoreCondReq miss cycles 230811860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2827500 # number of StoreCondFailReq miss cycles 230911860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::total 2827500 # number of StoreCondFailReq miss cycles 231011860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::cpu1.data 250715880516 # number of demand (read+write) miss cycles 231111860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::total 250715880516 # number of demand (read+write) miss cycles 231211860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::cpu1.data 250715880516 # number of overall miss cycles 231311860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::total 250715880516 # number of overall miss cycles 231411860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 86015609 # number of ReadReq accesses(hits+misses) 231511860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 86015609 # number of ReadReq accesses(hits+misses) 231611860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 76314698 # number of WriteReq accesses(hits+misses) 231711860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 76314698 # number of WriteReq accesses(hits+misses) 231811860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 895669 # number of SoftPFReq accesses(hits+misses) 231911860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 895669 # number of SoftPFReq accesses(hits+misses) 232011860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::cpu1.data 625929 # number of WriteLineReq accesses(hits+misses) 232111860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::total 625929 # number of WriteLineReq accesses(hits+misses) 232211860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2074220 # number of LoadLockedReq accesses(hits+misses) 232311860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 2074220 # number of LoadLockedReq accesses(hits+misses) 232411860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2031861 # number of StoreCondReq accesses(hits+misses) 232511860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 2031861 # number of StoreCondReq accesses(hits+misses) 232611860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 162956236 # number of demand (read+write) accesses 232711860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 162956236 # number of demand (read+write) accesses 232811860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 163851905 # number of overall (read+write) accesses 232911860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 163851905 # number of overall (read+write) accesses 233011860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.074552 # miss rate for ReadReq accesses 233111860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.074552 # miss rate for ReadReq accesses 233211860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.098470 # miss rate for WriteReq accesses 233311860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.098470 # miss rate for WriteReq accesses 233411860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.790450 # miss rate for SoftPFReq accesses 233511860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.790450 # miss rate for SoftPFReq accesses 233611860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.744463 # miss rate for WriteLineReq accesses 233711860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::total 0.744463 # miss rate for WriteLineReq accesses 233811860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.118768 # miss rate for LoadLockedReq accesses 233911860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.118768 # miss rate for LoadLockedReq accesses 234011860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.096209 # miss rate for StoreCondReq accesses 234111860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.096209 # miss rate for StoreCondReq accesses 234211860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.088326 # miss rate for demand accesses 234311860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.088326 # miss rate for demand accesses 234411860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.092164 # miss rate for overall accesses 234511860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.092164 # miss rate for overall accesses 234611860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15860.893035 # average ReadReq miss latency 234711860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 15860.893035 # average ReadReq miss latency 234811860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18385.831167 # average WriteReq miss latency 234911860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 18385.831167 # average WriteReq miss latency 235011860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23265.763962 # average WriteLineReq miss latency 235111860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23265.763962 # average WriteLineReq miss latency 235211860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14230.713494 # average LoadLockedReq miss latency 235311860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14230.713494 # average LoadLockedReq miss latency 235411860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23880.253627 # average StoreCondReq miss latency 235511860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23880.253627 # average StoreCondReq miss latency 235610576Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 235710576Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 235811860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17418.884899 # average overall miss latency 235911860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 17418.884899 # average overall miss latency 236011860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16602.250473 # average overall miss latency 236111860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 16602.250473 # average overall miss latency 236211860Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 2802154 # number of cycles access was blocked 236311860Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_targets 21903502 # number of cycles access was blocked 236411860Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_mshrs 386416 # number of cycles access was blocked 236511860Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_targets 756136 # number of cycles access was blocked 236611860Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.251651 # average number of cycles each access was blocked 236711860Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_targets 28.967675 # average number of cycles each access was blocked 236811860Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 5530029 # number of writebacks 236911860Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 5530029 # number of writebacks 237011860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3294839 # number of ReadReq MSHR hits 237111860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 3294839 # number of ReadReq MSHR hits 237211860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 6084278 # number of WriteReq MSHR hits 237311860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 6084278 # number of WriteReq MSHR hits 237411860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3511 # number of WriteLineReq MSHR hits 237511860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_hits::total 3511 # number of WriteLineReq MSHR hits 237611860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 126189 # number of LoadLockedReq MSHR hits 237711860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 126189 # number of LoadLockedReq MSHR hits 237811860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::cpu1.data 9382628 # number of demand (read+write) MSHR hits 237911860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::total 9382628 # number of demand (read+write) MSHR hits 238011860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::cpu1.data 9382628 # number of overall MSHR hits 238111860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::total 9382628 # number of overall MSHR hits 238211860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3117809 # number of ReadReq MSHR misses 238311860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 3117809 # number of ReadReq MSHR misses 238411860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1430430 # number of WriteReq MSHR misses 238511860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 1430430 # number of WriteReq MSHR misses 238611860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 707901 # number of SoftPFReq MSHR misses 238711860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::total 707901 # number of SoftPFReq MSHR misses 238811860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 462470 # number of WriteLineReq MSHR misses 238911860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::total 462470 # number of WriteLineReq MSHR misses 239011860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 120162 # number of LoadLockedReq MSHR misses 239111860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 120162 # number of LoadLockedReq MSHR misses 239211860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 195479 # number of StoreCondReq MSHR misses 239311860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 195479 # number of StoreCondReq MSHR misses 239411860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.data 5010709 # number of demand (read+write) MSHR misses 239511860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 5010709 # number of demand (read+write) MSHR misses 239611860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.data 5718610 # number of overall MSHR misses 239711860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 5718610 # number of overall MSHR misses 239811860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 22964 # number of ReadReq MSHR uncacheable 239911860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::total 22964 # number of ReadReq MSHR uncacheable 240011860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 21406 # number of WriteReq MSHR uncacheable 240111860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::total 21406 # number of WriteReq MSHR uncacheable 240211860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 44370 # number of overall MSHR uncacheable misses 240311860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::total 44370 # number of overall MSHR uncacheable misses 240411860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 44191154500 # number of ReadReq MSHR miss cycles 240511860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 44191154500 # number of ReadReq MSHR miss cycles 240611860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 27737660597 # number of WriteReq MSHR miss cycles 240711860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 27737660597 # number of WriteReq MSHR miss cycles 240811860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 17972389000 # number of SoftPFReq MSHR miss cycles 240911860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 17972389000 # number of SoftPFReq MSHR miss cycles 241011860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10263027957 # number of WriteLineReq MSHR miss cycles 241111860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10263027957 # number of WriteLineReq MSHR miss cycles 241211860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1602495500 # number of LoadLockedReq MSHR miss cycles 241311860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1602495500 # number of LoadLockedReq MSHR miss cycles 241411860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4472798500 # number of StoreCondReq MSHR miss cycles 241511860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4472798500 # number of StoreCondReq MSHR miss cycles 241611860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2757500 # number of StoreCondFailReq MSHR miss cycles 241711860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2757500 # number of StoreCondFailReq MSHR miss cycles 241811860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 82191843054 # number of demand (read+write) MSHR miss cycles 241911860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 82191843054 # number of demand (read+write) MSHR miss cycles 242011860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 100164232054 # number of overall MSHR miss cycles 242111860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 100164232054 # number of overall MSHR miss cycles 242211860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4057567500 # number of ReadReq MSHR uncacheable cycles 242311860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4057567500 # number of ReadReq MSHR uncacheable cycles 242411860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4057567500 # number of overall MSHR uncacheable cycles 242511860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 4057567500 # number of overall MSHR uncacheable cycles 242611860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036247 # mshr miss rate for ReadReq accesses 242711860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036247 # mshr miss rate for ReadReq accesses 242811860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018744 # mshr miss rate for WriteReq accesses 242911860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018744 # mshr miss rate for WriteReq accesses 243011860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.790360 # mshr miss rate for SoftPFReq accesses 243111860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.790360 # mshr miss rate for SoftPFReq accesses 243211860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.738854 # mshr miss rate for WriteLineReq accesses 243311860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.738854 # mshr miss rate for WriteLineReq accesses 243411860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.057931 # mshr miss rate for LoadLockedReq accesses 243511860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.057931 # mshr miss rate for LoadLockedReq accesses 243611860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.096207 # mshr miss rate for StoreCondReq accesses 243711860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.096207 # mshr miss rate for StoreCondReq accesses 243811860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030749 # mshr miss rate for demand accesses 243911860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.030749 # mshr miss rate for demand accesses 244011860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034901 # mshr miss rate for overall accesses 244111860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.034901 # mshr miss rate for overall accesses 244211860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14173.785020 # average ReadReq mshr miss latency 244311860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14173.785020 # average ReadReq mshr miss latency 244411860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19391.134552 # average WriteReq mshr miss latency 244511860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19391.134552 # average WriteReq mshr miss latency 244611860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 25388.280282 # average SoftPFReq mshr miss latency 244711860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 25388.280282 # average SoftPFReq mshr miss latency 244811860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22191.770184 # average WriteLineReq mshr miss latency 244911860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22191.770184 # average WriteLineReq mshr miss latency 245011860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13336.125397 # average LoadLockedReq mshr miss latency 245111860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13336.125397 # average LoadLockedReq mshr miss latency 245211860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22881.222535 # average StoreCondReq mshr miss latency 245311860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22881.222535 # average StoreCondReq mshr miss latency 245410576Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 245510576Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 245611860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16403.236160 # average overall mshr miss latency 245711860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 16403.236160 # average overall mshr miss latency 245811860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17515.485766 # average overall mshr miss latency 245911860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 17515.485766 # average overall mshr miss latency 246011860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176692.540498 # average ReadReq mshr uncacheable latency 246111860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 176692.540498 # average ReadReq mshr uncacheable latency 246211860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 91448.444895 # average overall mshr uncacheable latency 246311860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 91448.444895 # average overall mshr uncacheable latency 246411860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 246511860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 6156366 # number of replacements 246611860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 501.025645 # Cycle average of tags in use 246711860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 184011394 # Total number of references to valid blocks. 246811860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 6156878 # Sample count of references to valid blocks. 246911860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 29.887127 # Average number of references to valid blocks. 247011860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 8516343949500 # Cycle when the warmup percentage was hit. 247111860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 501.025645 # Average occupied blocks per requestor 247211860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.978566 # Average percentage of cache occupancy 247311860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.978566 # Average percentage of cache occupancy 247410576Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 247511860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id 247611860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id 247711860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id 247810576Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 247911860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 387206970 # Number of tag accesses 248011860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 387206970 # Number of data accesses 248111860Sandreas.hansson@arm.comsystem.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 248211860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 184011394 # number of ReadReq hits 248311860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 184011394 # number of ReadReq hits 248411860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 184011394 # number of demand (read+write) hits 248511860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 184011394 # number of demand (read+write) hits 248611860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 184011394 # number of overall hits 248711860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 184011394 # number of overall hits 248811860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 6513585 # number of ReadReq misses 248911860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 6513585 # number of ReadReq misses 249011860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 6513585 # number of demand (read+write) misses 249111860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 6513585 # number of demand (read+write) misses 249211860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 6513585 # number of overall misses 249311860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 6513585 # number of overall misses 249411860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 71534475691 # number of ReadReq miss cycles 249511860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 71534475691 # number of ReadReq miss cycles 249611860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 71534475691 # number of demand (read+write) miss cycles 249711860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::total 71534475691 # number of demand (read+write) miss cycles 249811860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 71534475691 # number of overall miss cycles 249911860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::total 71534475691 # number of overall miss cycles 250011860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 190524979 # number of ReadReq accesses(hits+misses) 250111860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 190524979 # number of ReadReq accesses(hits+misses) 250211860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 190524979 # number of demand (read+write) accesses 250311860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 190524979 # number of demand (read+write) accesses 250411860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 190524979 # number of overall (read+write) accesses 250511860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 190524979 # number of overall (read+write) accesses 250611860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.034188 # miss rate for ReadReq accesses 250711860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.034188 # miss rate for ReadReq accesses 250811860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.034188 # miss rate for demand accesses 250911860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.034188 # miss rate for demand accesses 251011860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.034188 # miss rate for overall accesses 251111860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.034188 # miss rate for overall accesses 251211860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10982.350839 # average ReadReq miss latency 251311860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 10982.350839 # average ReadReq miss latency 251411860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10982.350839 # average overall miss latency 251511860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 10982.350839 # average overall miss latency 251611860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10982.350839 # average overall miss latency 251711860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 10982.350839 # average overall miss latency 251811860Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 10659560 # number of cycles access was blocked 251911860Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 1026 # number of cycles access was blocked 252011860Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_mshrs 770474 # number of cycles access was blocked 252111860Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_targets 4 # number of cycles access was blocked 252211860Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs 13.835068 # average number of cycles each access was blocked 252311860Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets 256.500000 # average number of cycles each access was blocked 252411860Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::writebacks 6156366 # number of writebacks 252511860Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::total 6156366 # number of writebacks 252611860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 356573 # number of ReadReq MSHR hits 252711860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_hits::total 356573 # number of ReadReq MSHR hits 252811860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_hits::cpu1.inst 356573 # number of demand (read+write) MSHR hits 252911860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_hits::total 356573 # number of demand (read+write) MSHR hits 253011860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_hits::cpu1.inst 356573 # number of overall MSHR hits 253111860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_hits::total 356573 # number of overall MSHR hits 253211860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 6157012 # number of ReadReq MSHR misses 253311860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 6157012 # number of ReadReq MSHR misses 253411860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 6157012 # number of demand (read+write) MSHR misses 253511860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::total 6157012 # number of demand (read+write) MSHR misses 253611860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 6157012 # number of overall MSHR misses 253711860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::total 6157012 # number of overall MSHR misses 253811680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable 253911680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable 254011680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses 254111680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses 254211860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 64558641440 # number of ReadReq MSHR miss cycles 254311860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 64558641440 # number of ReadReq MSHR miss cycles 254411860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 64558641440 # number of demand (read+write) MSHR miss cycles 254511860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 64558641440 # number of demand (read+write) MSHR miss cycles 254611860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 64558641440 # number of overall MSHR miss cycles 254711860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 64558641440 # number of overall MSHR miss cycles 254811860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7017998 # number of ReadReq MSHR uncacheable cycles 254911860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7017998 # number of ReadReq MSHR uncacheable cycles 255011860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7017998 # number of overall MSHR uncacheable cycles 255111860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::total 7017998 # number of overall MSHR uncacheable cycles 255211860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.032316 # mshr miss rate for ReadReq accesses 255311860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.032316 # mshr miss rate for ReadReq accesses 255411860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.032316 # mshr miss rate for demand accesses 255511860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.032316 # mshr miss rate for demand accesses 255611860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.032316 # mshr miss rate for overall accesses 255711860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.032316 # mshr miss rate for overall accesses 255811860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10485.385028 # average ReadReq mshr miss latency 255911860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10485.385028 # average ReadReq mshr miss latency 256011860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10485.385028 # average overall mshr miss latency 256111860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 10485.385028 # average overall mshr miss latency 256211860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10485.385028 # average overall mshr miss latency 256311860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 10485.385028 # average overall mshr miss latency 256411860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 104746.238806 # average ReadReq mshr uncacheable latency 256511860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 104746.238806 # average ReadReq mshr uncacheable latency 256611860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 104746.238806 # average overall mshr uncacheable latency 256711860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 104746.238806 # average overall mshr uncacheable latency 256811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 256911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.num_hwpf_issued 7532579 # number of hwpf issued 257011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfIdentified 7540263 # number of prefetch candidates identified 257111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfBufferHit 6914 # number of redundant prefetches already in prefetch queue 257210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 257310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 257411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfSpanPage 905745 # number of prefetches not generated due to page crossing 257511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 257611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.replacements 2237289 # number of replacements 257711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tagsinuse 12906.637296 # Cycle average of tags in use 257811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.total_refs 10683229 # Total number of references to valid blocks. 257911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.sampled_refs 2253034 # Sample count of references to valid blocks. 258011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.avg_refs 4.741708 # Average number of references to valid blocks. 258111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 258211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 12598.343747 # Average occupied blocks per requestor 258311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 34.232851 # Average occupied blocks per requestor 258411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 25.792432 # Average occupied blocks per requestor 258511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 248.268266 # Average occupied blocks per requestor 258611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.768942 # Average percentage of cache occupancy 258711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002089 # Average percentage of cache occupancy 258811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001574 # Average percentage of cache occupancy 258911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.015153 # Average percentage of cache occupancy 259011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.787759 # Average percentage of cache occupancy 259111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1022 360 # Occupied blocks per task id 259211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 61 # Occupied blocks per task id 259311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 15324 # Occupied blocks per task id 259411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::0 6 # Occupied blocks per task id 259511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::1 16 # Occupied blocks per task id 259611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::2 163 # Occupied blocks per task id 259711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::3 96 # Occupied blocks per task id 259811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::4 79 # Occupied blocks per task id 259911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 260011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 44 # Occupied blocks per task id 260111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id 260211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id 260311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 223 # Occupied blocks per task id 260411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 2395 # Occupied blocks per task id 260511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 7644 # Occupied blocks per task id 260611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2882 # Occupied blocks per task id 260711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2180 # Occupied blocks per task id 260811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1022 0.021973 # Percentage of cache occupancy per task id 260911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003723 # Percentage of cache occupancy per task id 261011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.935303 # Percentage of cache occupancy per task id 261111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tag_accesses 407515579 # Number of tag accesses 261211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.data_accesses 407515579 # Number of data accesses 261311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 261411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 593172 # number of ReadReq hits 261511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 194279 # number of ReadReq hits 261611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 787451 # number of ReadReq hits 261711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::writebacks 3518569 # number of WritebackDirty hits 261811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::total 3518569 # number of WritebackDirty hits 261911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_hits::writebacks 8164233 # number of WritebackClean hits 262011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_hits::total 8164233 # number of WritebackClean hits 262111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::cpu1.data 105 # number of UpgradeReq hits 262211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::total 105 # number of UpgradeReq hits 262311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1 # number of SCUpgradeReq hits 262411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits 262511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 954506 # number of ReadExReq hits 262611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 954506 # number of ReadExReq hits 262711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5573390 # number of ReadCleanReq hits 262811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 5573390 # number of ReadCleanReq hits 262911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2940198 # number of ReadSharedReq hits 263011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 2940198 # number of ReadSharedReq hits 263111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::cpu1.data 209295 # number of InvalidateReq hits 263211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::total 209295 # number of InvalidateReq hits 263311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 593172 # number of demand (read+write) hits 263411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 194279 # number of demand (read+write) hits 263511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 5573390 # number of demand (read+write) hits 263611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 3894704 # number of demand (read+write) hits 263711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::total 10255545 # number of demand (read+write) hits 263811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 593172 # number of overall hits 263911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 194279 # number of overall hits 264011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 5573390 # number of overall hits 264111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 3894704 # number of overall hits 264211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::total 10255545 # number of overall hits 264311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 23430 # number of ReadReq misses 264411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10710 # number of ReadReq misses 264511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 34140 # number of ReadReq misses 264611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 228701 # number of UpgradeReq misses 264711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 228701 # number of UpgradeReq misses 264811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 195469 # number of SCUpgradeReq misses 264911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 195469 # number of SCUpgradeReq misses 265011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 9 # number of SCUpgradeFailReq misses 265111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::total 9 # number of SCUpgradeFailReq misses 265211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 254871 # number of ReadExReq misses 265311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 254871 # number of ReadExReq misses 265411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 583583 # number of ReadCleanReq misses 265511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 583583 # number of ReadCleanReq misses 265611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1000824 # number of ReadSharedReq misses 265711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 1000824 # number of ReadSharedReq misses 265811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::cpu1.data 253175 # number of InvalidateReq misses 265911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::total 253175 # number of InvalidateReq misses 266011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 23430 # number of demand (read+write) misses 266111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 10710 # number of demand (read+write) misses 266211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 583583 # number of demand (read+write) misses 266311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 1255695 # number of demand (read+write) misses 266411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::total 1873418 # number of demand (read+write) misses 266511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 23430 # number of overall misses 266611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 10710 # number of overall misses 266711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 583583 # number of overall misses 266811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 1255695 # number of overall misses 266911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::total 1873418 # number of overall misses 267011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 794453000 # number of ReadReq miss cycles 267111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 411582000 # number of ReadReq miss cycles 267211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::total 1206035000 # number of ReadReq miss cycles 267311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 885247000 # number of UpgradeReq miss cycles 267411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::total 885247000 # number of UpgradeReq miss cycles 267511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 309725000 # number of SCUpgradeReq miss cycles 267611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::total 309725000 # number of SCUpgradeReq miss cycles 267711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2651498 # number of SCUpgradeFailReq miss cycles 267811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2651498 # number of SCUpgradeFailReq miss cycles 267911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 13048454496 # number of ReadExReq miss cycles 268011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::total 13048454496 # number of ReadExReq miss cycles 268111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 21566356000 # number of ReadCleanReq miss cycles 268211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::total 21566356000 # number of ReadCleanReq miss cycles 268311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 38197437985 # number of ReadSharedReq miss cycles 268411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::total 38197437985 # number of ReadSharedReq miss cycles 268511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 1037000 # number of InvalidateReq miss cycles 268611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::total 1037000 # number of InvalidateReq miss cycles 268711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 794453000 # number of demand (read+write) miss cycles 268811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 411582000 # number of demand (read+write) miss cycles 268911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.inst 21566356000 # number of demand (read+write) miss cycles 269011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.data 51245892481 # number of demand (read+write) miss cycles 269111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::total 74018283481 # number of demand (read+write) miss cycles 269211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 794453000 # number of overall miss cycles 269311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 411582000 # number of overall miss cycles 269411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.inst 21566356000 # number of overall miss cycles 269511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.data 51245892481 # number of overall miss cycles 269611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::total 74018283481 # number of overall miss cycles 269711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 616602 # number of ReadReq accesses(hits+misses) 269811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 204989 # number of ReadReq accesses(hits+misses) 269911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 821591 # number of ReadReq accesses(hits+misses) 270011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::writebacks 3518569 # number of WritebackDirty accesses(hits+misses) 270111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::total 3518569 # number of WritebackDirty accesses(hits+misses) 270211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::writebacks 8164233 # number of WritebackClean accesses(hits+misses) 270311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::total 8164233 # number of WritebackClean accesses(hits+misses) 270411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 228806 # number of UpgradeReq accesses(hits+misses) 270511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 228806 # number of UpgradeReq accesses(hits+misses) 270611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 195470 # number of SCUpgradeReq accesses(hits+misses) 270711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 195470 # number of SCUpgradeReq accesses(hits+misses) 270811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 9 # number of SCUpgradeFailReq accesses(hits+misses) 270911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::total 9 # number of SCUpgradeFailReq accesses(hits+misses) 271011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1209377 # number of ReadExReq accesses(hits+misses) 271111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 1209377 # number of ReadExReq accesses(hits+misses) 271211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 6156973 # number of ReadCleanReq accesses(hits+misses) 271311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 6156973 # number of ReadCleanReq accesses(hits+misses) 271411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3941022 # number of ReadSharedReq accesses(hits+misses) 271511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 3941022 # number of ReadSharedReq accesses(hits+misses) 271611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 462470 # number of InvalidateReq accesses(hits+misses) 271711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::total 462470 # number of InvalidateReq accesses(hits+misses) 271811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 616602 # number of demand (read+write) accesses 271911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 204989 # number of demand (read+write) accesses 272011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 6156973 # number of demand (read+write) accesses 272111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 5150399 # number of demand (read+write) accesses 272211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::total 12128963 # number of demand (read+write) accesses 272311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 616602 # number of overall (read+write) accesses 272411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 204989 # number of overall (read+write) accesses 272511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 6156973 # number of overall (read+write) accesses 272611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 5150399 # number of overall (read+write) accesses 272711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::total 12128963 # number of overall (read+write) accesses 272811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.037999 # miss rate for ReadReq accesses 272911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.052247 # miss rate for ReadReq accesses 273011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.041554 # miss rate for ReadReq accesses 273111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999541 # miss rate for UpgradeReq accesses 273211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999541 # miss rate for UpgradeReq accesses 273311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.999995 # miss rate for SCUpgradeReq accesses 273411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.999995 # miss rate for SCUpgradeReq accesses 273510576Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 273610576Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 273711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.210746 # miss rate for ReadExReq accesses 273811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.210746 # miss rate for ReadExReq accesses 273911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.094784 # miss rate for ReadCleanReq accesses 274011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.094784 # miss rate for ReadCleanReq accesses 274111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.253950 # miss rate for ReadSharedReq accesses 274211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.253950 # miss rate for ReadSharedReq accesses 274311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.547441 # miss rate for InvalidateReq accesses 274411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::total 0.547441 # miss rate for InvalidateReq accesses 274511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.037999 # miss rate for demand accesses 274611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.052247 # miss rate for demand accesses 274711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.094784 # miss rate for demand accesses 274811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.243805 # miss rate for demand accesses 274911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.154458 # miss rate for demand accesses 275011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.037999 # miss rate for overall accesses 275111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.052247 # miss rate for overall accesses 275211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.094784 # miss rate for overall accesses 275311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.243805 # miss rate for overall accesses 275411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.154458 # miss rate for overall accesses 275511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 33907.511737 # average ReadReq miss latency 275611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 38429.691877 # average ReadReq miss latency 275711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::total 35326.157001 # average ReadReq miss latency 275811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 3870.761387 # average UpgradeReq miss latency 275911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 3870.761387 # average UpgradeReq miss latency 276011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1584.522354 # average SCUpgradeReq miss latency 276111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1584.522354 # average SCUpgradeReq miss latency 276211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 294610.888889 # average SCUpgradeFailReq miss latency 276311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 294610.888889 # average SCUpgradeFailReq miss latency 276411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 51196.309098 # average ReadExReq miss latency 276511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::total 51196.309098 # average ReadExReq miss latency 276611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36955.079226 # average ReadCleanReq miss latency 276711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36955.079226 # average ReadCleanReq miss latency 276811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 38165.989210 # average ReadSharedReq miss latency 276911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 38165.989210 # average ReadSharedReq miss latency 277011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 4.095981 # average InvalidateReq miss latency 277111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 4.095981 # average InvalidateReq miss latency 277211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 33907.511737 # average overall miss latency 277311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 38429.691877 # average overall miss latency 277411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36955.079226 # average overall miss latency 277511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 40810.780071 # average overall miss latency 277611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::total 39509.753553 # average overall miss latency 277711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 33907.511737 # average overall miss latency 277811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 38429.691877 # average overall miss latency 277911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36955.079226 # average overall miss latency 278011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 40810.780071 # average overall miss latency 278111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::total 39509.753553 # average overall miss latency 278211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_mshrs 273 # number of cycles access was blocked 278310576Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 278411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_mshrs 6 # number of cycles access was blocked 278510576Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 278611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs 45.500000 # average number of cycles each access was blocked 278710576Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 278811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.unused_prefetches 45092 # number of HardPF blocks evicted w/o reference 278911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::writebacks 1265703 # number of writebacks 279011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::total 1265703 # number of writebacks 279111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 89 # number of ReadReq MSHR hits 279211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 277 # number of ReadReq MSHR hits 279311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::total 366 # number of ReadReq MSHR hits 279411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 14520 # number of ReadExReq MSHR hits 279511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::total 14520 # number of ReadExReq MSHR hits 279611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 6 # number of ReadCleanReq MSHR hits 279711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_hits::total 6 # number of ReadCleanReq MSHR hits 279811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 4370 # number of ReadSharedReq MSHR hits 279911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::total 4370 # number of ReadSharedReq MSHR hits 280011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 4 # number of InvalidateReq MSHR hits 280111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_hits::total 4 # number of InvalidateReq MSHR hits 280211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 89 # number of demand (read+write) MSHR hits 280311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 277 # number of demand (read+write) MSHR hits 280411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits 280511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.data 18890 # number of demand (read+write) MSHR hits 280611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::total 19262 # number of demand (read+write) MSHR hits 280711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 89 # number of overall MSHR hits 280811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 277 # number of overall MSHR hits 280911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits 281011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.data 18890 # number of overall MSHR hits 281111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::total 19262 # number of overall MSHR hits 281211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 23341 # number of ReadReq MSHR misses 281311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 10433 # number of ReadReq MSHR misses 281411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::total 33774 # number of ReadReq MSHR misses 281511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 793498 # number of HardPFReq MSHR misses 281611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::total 793498 # number of HardPFReq MSHR misses 281711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 228701 # number of UpgradeReq MSHR misses 281811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::total 228701 # number of UpgradeReq MSHR misses 281911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 195469 # number of SCUpgradeReq MSHR misses 282011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 195469 # number of SCUpgradeReq MSHR misses 282111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 9 # number of SCUpgradeFailReq MSHR misses 282211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 9 # number of SCUpgradeFailReq MSHR misses 282311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 240351 # number of ReadExReq MSHR misses 282411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::total 240351 # number of ReadExReq MSHR misses 282511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 583577 # number of ReadCleanReq MSHR misses 282611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::total 583577 # number of ReadCleanReq MSHR misses 282711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 996454 # number of ReadSharedReq MSHR misses 282811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::total 996454 # number of ReadSharedReq MSHR misses 282911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 253171 # number of InvalidateReq MSHR misses 283011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::total 253171 # number of InvalidateReq MSHR misses 283111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 23341 # number of demand (read+write) MSHR misses 283211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 10433 # number of demand (read+write) MSHR misses 283311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.inst 583577 # number of demand (read+write) MSHR misses 283411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.data 1236805 # number of demand (read+write) MSHR misses 283511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::total 1854156 # number of demand (read+write) MSHR misses 283611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 23341 # number of overall MSHR misses 283711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 10433 # number of overall MSHR misses 283811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.inst 583577 # number of overall MSHR misses 283911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.data 1236805 # number of overall MSHR misses 284011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 793498 # number of overall MSHR misses 284111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::total 2647654 # number of overall MSHR misses 284211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable 284311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 22964 # number of ReadReq MSHR uncacheable 284411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::total 23031 # number of ReadReq MSHR uncacheable 284511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 21406 # number of WriteReq MSHR uncacheable 284611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::total 21406 # number of WriteReq MSHR uncacheable 284711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses 284811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 44370 # number of overall MSHR uncacheable misses 284911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::total 44437 # number of overall MSHR uncacheable misses 285011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 652898000 # number of ReadReq MSHR miss cycles 285111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 343913500 # number of ReadReq MSHR miss cycles 285211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::total 996811500 # number of ReadReq MSHR miss cycles 285311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 46156066571 # number of HardPFReq MSHR miss cycles 285411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 46156066571 # number of HardPFReq MSHR miss cycles 285511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4295864494 # number of UpgradeReq MSHR miss cycles 285611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4295864494 # number of UpgradeReq MSHR miss cycles 285711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3003825995 # number of SCUpgradeReq MSHR miss cycles 285811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3003825995 # number of SCUpgradeReq MSHR miss cycles 285911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2231498 # number of SCUpgradeFailReq MSHR miss cycles 286011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2231498 # number of SCUpgradeFailReq MSHR miss cycles 286111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 9417872000 # number of ReadExReq MSHR miss cycles 286211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 9417872000 # number of ReadExReq MSHR miss cycles 286311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 18064709000 # number of ReadCleanReq MSHR miss cycles 286411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 18064709000 # number of ReadCleanReq MSHR miss cycles 286511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 31901371985 # number of ReadSharedReq MSHR miss cycles 286611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 31901371985 # number of ReadSharedReq MSHR miss cycles 286711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6217720498 # number of InvalidateReq MSHR miss cycles 286811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6217720498 # number of InvalidateReq MSHR miss cycles 286911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 652898000 # number of demand (read+write) MSHR miss cycles 287011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 343913500 # number of demand (read+write) MSHR miss cycles 287111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 18064709000 # number of demand (read+write) MSHR miss cycles 287211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 41319243985 # number of demand (read+write) MSHR miss cycles 287311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::total 60380764485 # number of demand (read+write) MSHR miss cycles 287411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 652898000 # number of overall MSHR miss cycles 287511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 343913500 # number of overall MSHR miss cycles 287611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 18064709000 # number of overall MSHR miss cycles 287711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 41319243985 # number of overall MSHR miss cycles 287811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 46156066571 # number of overall MSHR miss cycles 287911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::total 106536831056 # number of overall MSHR miss cycles 288011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6514500 # number of ReadReq MSHR uncacheable cycles 288111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3873635500 # number of ReadReq MSHR uncacheable cycles 288211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3880150000 # number of ReadReq MSHR uncacheable cycles 288311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 6514500 # number of overall MSHR uncacheable cycles 288411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3873635500 # number of overall MSHR uncacheable cycles 288511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3880150000 # number of overall MSHR uncacheable cycles 288611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.037854 # mshr miss rate for ReadReq accesses 288711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.050895 # mshr miss rate for ReadReq accesses 288811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.041108 # mshr miss rate for ReadReq accesses 288910576Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 289010576Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 289111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.999541 # mshr miss rate for UpgradeReq accesses 289211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.999541 # mshr miss rate for UpgradeReq accesses 289311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999995 # mshr miss rate for SCUpgradeReq accesses 289411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999995 # mshr miss rate for SCUpgradeReq accesses 289510576Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 289610576Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 289711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.198740 # mshr miss rate for ReadExReq accesses 289811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.198740 # mshr miss rate for ReadExReq accesses 289911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.094783 # mshr miss rate for ReadCleanReq accesses 290011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.094783 # mshr miss rate for ReadCleanReq accesses 290111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.252842 # mshr miss rate for ReadSharedReq accesses 290211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.252842 # mshr miss rate for ReadSharedReq accesses 290311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.547432 # mshr miss rate for InvalidateReq accesses 290411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.547432 # mshr miss rate for InvalidateReq accesses 290511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.037854 # mshr miss rate for demand accesses 290611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.050895 # mshr miss rate for demand accesses 290711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.094783 # mshr miss rate for demand accesses 290811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.240138 # mshr miss rate for demand accesses 290911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::total 0.152870 # mshr miss rate for demand accesses 291011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.037854 # mshr miss rate for overall accesses 291111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050895 # mshr miss rate for overall accesses 291211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.094783 # mshr miss rate for overall accesses 291311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.240138 # mshr miss rate for overall accesses 291410576Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 291511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::total 0.218292 # mshr miss rate for overall accesses 291611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 27972.152007 # average ReadReq mshr miss latency 291711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 32964.008435 # average ReadReq mshr miss latency 291811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 29514.167703 # average ReadReq mshr miss latency 291911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58167.842352 # average HardPFReq mshr miss latency 292011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 58167.842352 # average HardPFReq mshr miss latency 292111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18783.759118 # average UpgradeReq mshr miss latency 292211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18783.759118 # average UpgradeReq mshr miss latency 292311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15367.275604 # average SCUpgradeReq mshr miss latency 292411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15367.275604 # average SCUpgradeReq mshr miss latency 292511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 247944.222222 # average SCUpgradeFailReq mshr miss latency 292611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 247944.222222 # average SCUpgradeFailReq mshr miss latency 292711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 39183.826986 # average ReadExReq mshr miss latency 292811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 39183.826986 # average ReadExReq mshr miss latency 292911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30955.142166 # average ReadCleanReq mshr miss latency 293011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30955.142166 # average ReadCleanReq mshr miss latency 293111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 32014.896809 # average ReadSharedReq mshr miss latency 293211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32014.896809 # average ReadSharedReq mshr miss latency 293311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 24559.370931 # average InvalidateReq mshr miss latency 293411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 24559.370931 # average InvalidateReq mshr miss latency 293511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 27972.152007 # average overall mshr miss latency 293611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 32964.008435 # average overall mshr miss latency 293711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30955.142166 # average overall mshr miss latency 293811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 33408.050570 # average overall mshr miss latency 293911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32565.094029 # average overall mshr miss latency 294011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 27972.152007 # average overall mshr miss latency 294111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 32964.008435 # average overall mshr miss latency 294211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30955.142166 # average overall mshr miss latency 294311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 33408.050570 # average overall mshr miss latency 294411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58167.842352 # average overall mshr miss latency 294511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::total 40238.199952 # average overall mshr miss latency 294611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 97231.343284 # average ReadReq mshr uncacheable latency 294711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 168682.960286 # average ReadReq mshr uncacheable latency 294811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 168475.098780 # average ReadReq mshr uncacheable latency 294911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 97231.343284 # average overall mshr uncacheable latency 295011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 87303.031327 # average overall mshr uncacheable latency 295111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 87318.000765 # average overall mshr uncacheable latency 295211860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_requests 24247915 # Total number of requests made to the snoop filter. 295311860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_requests 12479959 # Number of requests hitting in the snoop filter with a single holder of the requested data. 295411860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_requests 8015 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 295511860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_snoops 603053 # Total number of snoops made to the snoop filter. 295611860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_snoops 602834 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 295711860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 219 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 295811860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 295911860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 936644 # Transaction distribution 296011860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 11117136 # Transaction distribution 296111860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 21406 # Transaction distribution 296211860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 21406 # Transaction distribution 296311860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackDirty 4809330 # Transaction distribution 296411860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackClean 8167824 # Transaction distribution 296511860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::CleanEvict 1368728 # Transaction distribution 296611860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFReq 1012133 # Transaction distribution 296711860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFResp 9 # Transaction distribution 296811860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 404751 # Transaction distribution 296911860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 355876 # Transaction distribution 297011860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 480511 # Transaction distribution 297111860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution 297211860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution 297311860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 1238980 # Transaction distribution 297411860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 1214897 # Transaction distribution 297511860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 6157012 # Transaction distribution 297611860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 4940216 # Transaction distribution 297711860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateReq 522762 # Transaction distribution 297811860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateResp 463422 # Transaction distribution 297911860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18470485 # Packet count per connected master and slave (bytes) 298011860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17838362 # Packet count per connected master and slave (bytes) 298111860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 429531 # Packet count per connected master and slave (bytes) 298211860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1305673 # Packet count per connected master and slave (bytes) 298311860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count::total 38044051 # Packet count per connected master and slave (bytes) 298411860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 788054768 # Cumulative packet size per connected master and slave (bytes) 298511860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 689328153 # Cumulative packet size per connected master and slave (bytes) 298611860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1639912 # Cumulative packet size per connected master and slave (bytes) 298711860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4932816 # Cumulative packet size per connected master and slave (bytes) 298811860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size::total 1483955649 # Cumulative packet size per connected master and slave (bytes) 298911860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoops 5334462 # Total snoops (count) 299011860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopTraffic 88980784 # Total snoop traffic (bytes) 299111860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 18249337 # Request fanout histogram 299211860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 0.053626 # Request fanout histogram 299311860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.225332 # Request fanout histogram 299410576Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 299511860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 17270909 94.64% 94.64% # Request fanout histogram 299611860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 978209 5.36% 100.00% # Request fanout histogram 299711860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 219 0.00% 100.00% # Request fanout histogram 299810576Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 299911138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 300010827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 300111860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 18249337 # Request fanout histogram 300211860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.reqLayer0.occupancy 24116423481 # Layer occupancy (ticks) 300311860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 300411860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopLayer0.occupancy 160883108 # Layer occupancy (ticks) 300510576Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 300611860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer0.occupancy 9241921761 # Layer occupancy (ticks) 300710576Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 300811860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer1.occupancy 8211674528 # Layer occupancy (ticks) 300910576Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 301011860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer2.occupancy 224968642 # Layer occupancy (ticks) 301110576Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 301211860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer3.occupancy 690043535 # Layer occupancy (ticks) 301310576Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 301411860Sandreas.hansson@arm.comsystem.iobus.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 301511860Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 40285 # Transaction distribution 301611860Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 40285 # Transaction distribution 301711860Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 136579 # Transaction distribution 301811860Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 136579 # Transaction distribution 301911860Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47524 # Packet count per connected master and slave (bytes) 302010576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 302111245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 302210576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 302310576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 302410576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 302510576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 302610576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 302710576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 302810576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 302910576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 303011860Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 303110576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 303211860Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122406 # Packet count per connected master and slave (bytes) 303311860Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231242 # Packet count per connected master and slave (bytes) 303411860Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231242 # Packet count per connected master and slave (bytes) 303510576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 303610576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 303711860Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 353728 # Packet count per connected master and slave (bytes) 303811860Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47544 # Cumulative packet size per connected master and slave (bytes) 303910576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 304011245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 304110576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 304210576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 304310576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 304410576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 304510576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 304610576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 304710576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 304810576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 304911860Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 305010576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 305111860Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 155536 # Cumulative packet size per connected master and slave (bytes) 305211860Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338984 # Cumulative packet size per connected master and slave (bytes) 305311860Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7338984 # Cumulative packet size per connected master and slave (bytes) 305410576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 305510576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 305611860Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 7496606 # Cumulative packet size per connected master and slave (bytes) 305711860Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 36861002 # Layer occupancy (ticks) 305810576Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 305911860Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) 306010576Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 306111860Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 327000 # Layer occupancy (ticks) 306210576Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 306311860Sandreas.hansson@arm.comsystem.iobus.reqLayer3.occupancy 10500 # Layer occupancy (ticks) 306410576Sandreas.hansson@arm.comsystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 306511502SCurtis.Dunham@arm.comsystem.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) 306611245Sandreas.sandberg@arm.comsystem.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 306711353Sandreas.hansson@arm.comsystem.iobus.reqLayer10.occupancy 10500 # Layer occupancy (ticks) 306810576Sandreas.hansson@arm.comsystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 306911754Sandreas.hansson@arm.comsystem.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) 307010576Sandreas.hansson@arm.comsystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 307111754Sandreas.hansson@arm.comsystem.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) 307210576Sandreas.hansson@arm.comsystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 307311860Sandreas.hansson@arm.comsystem.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) 307410576Sandreas.hansson@arm.comsystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 307511860Sandreas.hansson@arm.comsystem.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks) 307610576Sandreas.hansson@arm.comsystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 307711860Sandreas.hansson@arm.comsystem.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks) 307810576Sandreas.hansson@arm.comsystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 307911860Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 24160506 # Layer occupancy (ticks) 308010576Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 308111860Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 36392501 # Layer occupancy (ticks) 308210576Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 308311860Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 570209840 # Layer occupancy (ticks) 308410576Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 308511860Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 92558000 # Layer occupancy (ticks) 308610576Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 308711860Sandreas.hansson@arm.comsystem.iobus.respLayer3.occupancy 147938000 # Layer occupancy (ticks) 308810576Sandreas.hansson@arm.comsystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 308910892Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 309010576Sandreas.hansson@arm.comsystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 309111860Sandreas.hansson@arm.comsystem.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 309211860Sandreas.hansson@arm.comsystem.iocache.tags.replacements 115633 # number of replacements 309311860Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 11.369333 # Cycle average of tags in use 309411245Sandreas.sandberg@arm.comsystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 309511860Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 115649 # Sample count of references to valid blocks. 309611245Sandreas.sandberg@arm.comsystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 309711860Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 9154282048000 # Cycle when the warmup percentage was hit. 309811860Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 7.419555 # Average occupied blocks per requestor 309911860Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 3.949778 # Average occupied blocks per requestor 310011860Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.463722 # Average percentage of cache occupancy 310111860Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.246861 # Average percentage of cache occupancy 310211860Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.710583 # Average percentage of cache occupancy 310310576Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 310410576Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 310510576Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 310611860Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 1040946 # Number of tag accesses 310711860Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 1040946 # Number of data accesses 310811860Sandreas.hansson@arm.comsystem.iocache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 310910576Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 311011860Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ide 8893 # number of ReadReq misses 311111860Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 8930 # number of ReadReq misses 311210576Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 311310576Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 311410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 311510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 311610576Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 311711860Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ide 115621 # number of demand (read+write) misses 311811860Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 115661 # number of demand (read+write) misses 311910576Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 312011860Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ide 115621 # number of overall misses 312111860Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 115661 # number of overall misses 312211860Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5192500 # number of ReadReq miss cycles 312311860Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ide 1787370736 # number of ReadReq miss cycles 312411860Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 1792563236 # number of ReadReq miss cycles 312511860Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 312611860Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 312711860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::realview.ide 12950575604 # number of WriteLineReq miss cycles 312811860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::total 12950575604 # number of WriteLineReq miss cycles 312911860Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ethernet 5561500 # number of demand (read+write) miss cycles 313011860Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ide 14737946340 # number of demand (read+write) miss cycles 313111860Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 14743507840 # number of demand (read+write) miss cycles 313211860Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ethernet 5561500 # number of overall miss cycles 313311860Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ide 14737946340 # number of overall miss cycles 313411860Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 14743507840 # number of overall miss cycles 313510576Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 313611860Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8893 # number of ReadReq accesses(hits+misses) 313711860Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 8930 # number of ReadReq accesses(hits+misses) 313810576Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 313910576Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 314010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 314110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 314210576Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 314311860Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ide 115621 # number of demand (read+write) accesses 314411860Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 115661 # number of demand (read+write) accesses 314510576Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 314611860Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 115621 # number of overall (read+write) accesses 314711860Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 115661 # number of overall (read+write) accesses 314810576Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 314910576Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 315010576Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 315110576Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 315210576Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 315310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 315410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 315510576Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 315610576Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 315710576Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 315810576Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 315910576Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 316010576Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 316111860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 140337.837838 # average ReadReq miss latency 316211860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 200986.251659 # average ReadReq miss latency 316311860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 200734.964838 # average ReadReq miss latency 316411860Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 316511860Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 316611860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::realview.ide 121341.874710 # average WriteLineReq miss latency 316711860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 121341.874710 # average WriteLineReq miss latency 316811860Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 139037.500000 # average overall miss latency 316911860Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ide 127467.729392 # average overall miss latency 317011860Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 127471.730661 # average overall miss latency 317111860Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 139037.500000 # average overall miss latency 317211860Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ide 127467.729392 # average overall miss latency 317311860Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 127471.730661 # average overall miss latency 317411860Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 39227 # number of cycles access was blocked 317510576Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 317611860Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 3536 # number of cycles access was blocked 317710576Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 317811860Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 11.093609 # average number of cycles each access was blocked 317910576Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 318011860Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 106710 # number of writebacks 318111860Sandreas.hansson@arm.comsystem.iocache.writebacks::total 106710 # number of writebacks 318210576Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 318311860Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8893 # number of ReadReq MSHR misses 318411860Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::total 8930 # number of ReadReq MSHR misses 318510576Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 318610576Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 318710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 318810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 318910576Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 319011860Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ide 115621 # number of demand (read+write) MSHR misses 319111860Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::total 115661 # number of demand (read+write) MSHR misses 319210576Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 319311860Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ide 115621 # number of overall MSHR misses 319411860Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::total 115661 # number of overall MSHR misses 319511860Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3342500 # number of ReadReq MSHR miss cycles 319611860Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1342720736 # number of ReadReq MSHR miss cycles 319711860Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 1346063236 # number of ReadReq MSHR miss cycles 319811860Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 319911860Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 320011860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7608008190 # number of WriteLineReq MSHR miss cycles 320111860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 7608008190 # number of WriteLineReq MSHR miss cycles 320211860Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3561500 # number of demand (read+write) MSHR miss cycles 320311860Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ide 8950728926 # number of demand (read+write) MSHR miss cycles 320411860Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 8954290426 # number of demand (read+write) MSHR miss cycles 320511860Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3561500 # number of overall MSHR miss cycles 320611860Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ide 8950728926 # number of overall MSHR miss cycles 320711860Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 8954290426 # number of overall MSHR miss cycles 320810576Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 320910576Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 321010576Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 321110576Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 321210576Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 321310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 321410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 321510576Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 321610576Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 321710576Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 321810576Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 321910576Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 322010576Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 322111860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90337.837838 # average ReadReq mshr miss latency 322211860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 150986.251659 # average ReadReq mshr miss latency 322311860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 150734.964838 # average ReadReq mshr miss latency 322411860Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 322511860Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 322611860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 71284.088430 # average WriteLineReq mshr miss latency 322711860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 71284.088430 # average WriteLineReq mshr miss latency 322811860Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89037.500000 # average overall mshr miss latency 322911860Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 77414.387750 # average overall mshr miss latency 323011860Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 77418.407467 # average overall mshr miss latency 323111860Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89037.500000 # average overall mshr miss latency 323211860Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 77414.387750 # average overall mshr miss latency 323311860Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 77418.407467 # average overall mshr miss latency 323411860Sandreas.hansson@arm.comsystem.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 323511860Sandreas.hansson@arm.comsystem.l2c.tags.replacements 1858608 # number of replacements 323611860Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 65222.891140 # Cycle average of tags in use 323711860Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 7355255 # Total number of references to valid blocks. 323811860Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 1920213 # Sample count of references to valid blocks. 323911860Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 3.830437 # Average number of references to valid blocks. 324011860Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 1229429500 # Cycle when the warmup percentage was hit. 324111860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 10209.698759 # Average occupied blocks per requestor 324211860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 401.592309 # Average occupied blocks per requestor 324311860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 445.016269 # Average occupied blocks per requestor 324411860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 3734.616961 # Average occupied blocks per requestor 324511860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 21322.764244 # Average occupied blocks per requestor 324611860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 18260.159461 # Average occupied blocks per requestor 324711860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 76.119212 # Average occupied blocks per requestor 324811860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 86.745152 # Average occupied blocks per requestor 324911860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 3160.425498 # Average occupied blocks per requestor 325011860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 4267.065632 # Average occupied blocks per requestor 325111860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3258.687641 # Average occupied blocks per requestor 325211860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.155788 # Average percentage of cache occupancy 325311860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.006128 # Average percentage of cache occupancy 325411860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.006790 # Average percentage of cache occupancy 325511860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.056986 # Average percentage of cache occupancy 325611860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.325360 # Average percentage of cache occupancy 325711860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.278628 # Average percentage of cache occupancy 325811860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.001161 # Average percentage of cache occupancy 325911860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.001324 # Average percentage of cache occupancy 326011860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.048224 # Average percentage of cache occupancy 326111860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.065110 # Average percentage of cache occupancy 326211860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.049724 # Average percentage of cache occupancy 326311860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.995222 # Average percentage of cache occupancy 326411860Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1022 11759 # Occupied blocks per task id 326511860Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 304 # Occupied blocks per task id 326611860Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 49542 # Occupied blocks per task id 326711860Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id 326811860Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::2 196 # Occupied blocks per task id 326911860Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::3 891 # Occupied blocks per task id 327011860Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::4 10670 # Occupied blocks per task id 327111860Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::1 12 # Occupied blocks per task id 327211860Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 292 # Occupied blocks per task id 327311860Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 327411860Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 367 # Occupied blocks per task id 327511860Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 2478 # Occupied blocks per task id 327611860Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 2877 # Occupied blocks per task id 327711860Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 43809 # Occupied blocks per task id 327811860Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1022 0.179428 # Percentage of cache occupancy per task id 327911860Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.004639 # Percentage of cache occupancy per task id 328011860Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.755951 # Percentage of cache occupancy per task id 328111860Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 84121444 # Number of tag accesses 328211860Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 84121444 # Number of data accesses 328311860Sandreas.hansson@arm.comsystem.l2c.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 328411860Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::writebacks 3161961 # number of WritebackDirty hits 328511860Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::total 3161961 # number of WritebackDirty hits 328611860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 218473 # number of UpgradeReq hits 328711860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 178227 # number of UpgradeReq hits 328811860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 396700 # number of UpgradeReq hits 328911860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 60416 # number of SCUpgradeReq hits 329011860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 50161 # number of SCUpgradeReq hits 329111860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 110577 # number of SCUpgradeReq hits 329211860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 54320 # number of ReadExReq hits 329311860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 59150 # number of ReadExReq hits 329411860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 113470 # number of ReadExReq hits 329511860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 13417 # number of ReadSharedReq hits 329611860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 5017 # number of ReadSharedReq hits 329711860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 539007 # number of ReadSharedReq hits 329811860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 668528 # number of ReadSharedReq hits 329911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 293105 # number of ReadSharedReq hits 330011860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 15148 # number of ReadSharedReq hits 330111860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 6130 # number of ReadSharedReq hits 330211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 525725 # number of ReadSharedReq hits 330311860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 626529 # number of ReadSharedReq hits 330411860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 298432 # number of ReadSharedReq hits 330511860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::total 2991038 # number of ReadSharedReq hits 330611860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_hits::cpu0.data 122623 # number of InvalidateReq hits 330711860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_hits::cpu1.data 121091 # number of InvalidateReq hits 330811860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_hits::total 243714 # number of InvalidateReq hits 330911860Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 13417 # number of demand (read+write) hits 331011860Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 5017 # number of demand (read+write) hits 331111860Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 539007 # number of demand (read+write) hits 331211860Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 722848 # number of demand (read+write) hits 331311860Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.l2cache.prefetcher 293105 # number of demand (read+write) hits 331411860Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 15148 # number of demand (read+write) hits 331511860Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 6130 # number of demand (read+write) hits 331611860Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 525725 # number of demand (read+write) hits 331711860Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 685679 # number of demand (read+write) hits 331811860Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.l2cache.prefetcher 298432 # number of demand (read+write) hits 331911860Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 3104508 # number of demand (read+write) hits 332011860Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 13417 # number of overall hits 332111860Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 5017 # number of overall hits 332211860Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 539007 # number of overall hits 332311860Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 722848 # number of overall hits 332411860Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.l2cache.prefetcher 293105 # number of overall hits 332511860Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 15148 # number of overall hits 332611860Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 6130 # number of overall hits 332711860Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 525725 # number of overall hits 332811860Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 685679 # number of overall hits 332911860Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.l2cache.prefetcher 298432 # number of overall hits 333011860Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 3104508 # number of overall hits 333111860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 21614 # number of UpgradeReq misses 333211860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 22773 # number of UpgradeReq misses 333311860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 44387 # number of UpgradeReq misses 333411860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 1033 # number of SCUpgradeReq misses 333511860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 1052 # number of SCUpgradeReq misses 333611860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 2085 # number of SCUpgradeReq misses 333711860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 96389 # number of ReadExReq misses 333811860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 53149 # number of ReadExReq misses 333911860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 149538 # number of ReadExReq misses 334011860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 3784 # number of ReadSharedReq misses 334111860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 3652 # number of ReadSharedReq misses 334211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 65121 # number of ReadSharedReq misses 334311860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 199292 # number of ReadSharedReq misses 334411860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 394602 # number of ReadSharedReq misses 334511860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2497 # number of ReadSharedReq misses 334611860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.itb.walker 1730 # number of ReadSharedReq misses 334711860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 57847 # number of ReadSharedReq misses 334811860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 128371 # number of ReadSharedReq misses 334911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 264210 # number of ReadSharedReq misses 335011860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::total 1121106 # number of ReadSharedReq misses 335111860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_misses::cpu0.data 461443 # number of InvalidateReq misses 335211860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_misses::cpu1.data 96191 # number of InvalidateReq misses 335311860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_misses::total 557634 # number of InvalidateReq misses 335411860Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 3784 # number of demand (read+write) misses 335511860Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 3652 # number of demand (read+write) misses 335611860Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 65121 # number of demand (read+write) misses 335711860Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 295681 # number of demand (read+write) misses 335811860Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.l2cache.prefetcher 394602 # number of demand (read+write) misses 335911860Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 2497 # number of demand (read+write) misses 336011860Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.itb.walker 1730 # number of demand (read+write) misses 336111860Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 57847 # number of demand (read+write) misses 336211860Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 181520 # number of demand (read+write) misses 336311860Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.l2cache.prefetcher 264210 # number of demand (read+write) misses 336411860Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 1270644 # number of demand (read+write) misses 336511860Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 3784 # number of overall misses 336611860Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 3652 # number of overall misses 336711860Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 65121 # number of overall misses 336811860Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 295681 # number of overall misses 336911860Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.l2cache.prefetcher 394602 # number of overall misses 337011860Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 2497 # number of overall misses 337111860Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.itb.walker 1730 # number of overall misses 337211860Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 57847 # number of overall misses 337311860Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 181520 # number of overall misses 337411860Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.l2cache.prefetcher 264210 # number of overall misses 337511860Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 1270644 # number of overall misses 337611860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu0.data 151083000 # number of UpgradeReq miss cycles 337711860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu1.data 144162500 # number of UpgradeReq miss cycles 337811860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::total 295245500 # number of UpgradeReq miss cycles 337911860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu0.data 9029500 # number of SCUpgradeReq miss cycles 338011860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu1.data 10650000 # number of SCUpgradeReq miss cycles 338111860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::total 19679500 # number of SCUpgradeReq miss cycles 338211860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu0.data 10395447993 # number of ReadExReq miss cycles 338311860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu1.data 5744671997 # number of ReadExReq miss cycles 338411860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::total 16140119990 # number of ReadExReq miss cycles 338511860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 381693500 # number of ReadSharedReq miss cycles 338611860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 359292500 # number of ReadSharedReq miss cycles 338711860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.inst 7105700999 # number of ReadSharedReq miss cycles 338811860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.data 21857572496 # number of ReadSharedReq miss cycles 338911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 60806343315 # number of ReadSharedReq miss cycles 339011860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 266793000 # number of ReadSharedReq miss cycles 339111860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 185648500 # number of ReadSharedReq miss cycles 339211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.inst 6445588500 # number of ReadSharedReq miss cycles 339311860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.data 15192688491 # number of ReadSharedReq miss cycles 339411860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 40621267426 # number of ReadSharedReq miss cycles 339511860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::total 153222588727 # number of ReadSharedReq miss cycles 339611860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.dtb.walker 381693500 # number of demand (read+write) miss cycles 339711860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.itb.walker 359292500 # number of demand (read+write) miss cycles 339811860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.inst 7105700999 # number of demand (read+write) miss cycles 339911860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.data 32253020489 # number of demand (read+write) miss cycles 340011860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 60806343315 # number of demand (read+write) miss cycles 340111860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.dtb.walker 266793000 # number of demand (read+write) miss cycles 340211860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.itb.walker 185648500 # number of demand (read+write) miss cycles 340311860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.inst 6445588500 # number of demand (read+write) miss cycles 340411860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.data 20937360488 # number of demand (read+write) miss cycles 340511860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 40621267426 # number of demand (read+write) miss cycles 340611860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::total 169362708717 # number of demand (read+write) miss cycles 340711860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.dtb.walker 381693500 # number of overall miss cycles 340811860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.itb.walker 359292500 # number of overall miss cycles 340911860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.inst 7105700999 # number of overall miss cycles 341011860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.data 32253020489 # number of overall miss cycles 341111860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 60806343315 # number of overall miss cycles 341211860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.dtb.walker 266793000 # number of overall miss cycles 341311860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.itb.walker 185648500 # number of overall miss cycles 341411860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.inst 6445588500 # number of overall miss cycles 341511860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.data 20937360488 # number of overall miss cycles 341611860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 40621267426 # number of overall miss cycles 341711860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::total 169362708717 # number of overall miss cycles 341811860Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 3161961 # number of WritebackDirty accesses(hits+misses) 341911860Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::total 3161961 # number of WritebackDirty accesses(hits+misses) 342011860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 240087 # number of UpgradeReq accesses(hits+misses) 342111860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 201000 # number of UpgradeReq accesses(hits+misses) 342211860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 441087 # number of UpgradeReq accesses(hits+misses) 342311860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 61449 # number of SCUpgradeReq accesses(hits+misses) 342411860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 51213 # number of SCUpgradeReq accesses(hits+misses) 342511860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 112662 # number of SCUpgradeReq accesses(hits+misses) 342611860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 150709 # number of ReadExReq accesses(hits+misses) 342711860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 112299 # number of ReadExReq accesses(hits+misses) 342811860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 263008 # number of ReadExReq accesses(hits+misses) 342911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 17201 # number of ReadSharedReq accesses(hits+misses) 343011860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 8669 # number of ReadSharedReq accesses(hits+misses) 343111860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 604128 # number of ReadSharedReq accesses(hits+misses) 343211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 867820 # number of ReadSharedReq accesses(hits+misses) 343311860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 687707 # number of ReadSharedReq accesses(hits+misses) 343411860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 17645 # number of ReadSharedReq accesses(hits+misses) 343511860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7860 # number of ReadSharedReq accesses(hits+misses) 343611860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 583572 # number of ReadSharedReq accesses(hits+misses) 343711860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 754900 # number of ReadSharedReq accesses(hits+misses) 343811860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 562642 # number of ReadSharedReq accesses(hits+misses) 343911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::total 4112144 # number of ReadSharedReq accesses(hits+misses) 344011860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_accesses::cpu0.data 584066 # number of InvalidateReq accesses(hits+misses) 344111860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_accesses::cpu1.data 217282 # number of InvalidateReq accesses(hits+misses) 344211860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_accesses::total 801348 # number of InvalidateReq accesses(hits+misses) 344311860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 17201 # number of demand (read+write) accesses 344411860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 8669 # number of demand (read+write) accesses 344511860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 604128 # number of demand (read+write) accesses 344611860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 1018529 # number of demand (read+write) accesses 344711860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.l2cache.prefetcher 687707 # number of demand (read+write) accesses 344811860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 17645 # number of demand (read+write) accesses 344911860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 7860 # number of demand (read+write) accesses 345011860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 583572 # number of demand (read+write) accesses 345111860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 867199 # number of demand (read+write) accesses 345211860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.l2cache.prefetcher 562642 # number of demand (read+write) accesses 345311860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 4375152 # number of demand (read+write) accesses 345411860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 17201 # number of overall (read+write) accesses 345511860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 8669 # number of overall (read+write) accesses 345611860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 604128 # number of overall (read+write) accesses 345711860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 1018529 # number of overall (read+write) accesses 345811860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.l2cache.prefetcher 687707 # number of overall (read+write) accesses 345911860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 17645 # number of overall (read+write) accesses 346011860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 7860 # number of overall (read+write) accesses 346111860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 583572 # number of overall (read+write) accesses 346211860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 867199 # number of overall (read+write) accesses 346311860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.l2cache.prefetcher 562642 # number of overall (read+write) accesses 346411860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 4375152 # number of overall (read+write) accesses 346511860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.090026 # miss rate for UpgradeReq accesses 346611860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.113299 # miss rate for UpgradeReq accesses 346711860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.100631 # miss rate for UpgradeReq accesses 346811860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.016811 # miss rate for SCUpgradeReq accesses 346911860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.020542 # miss rate for SCUpgradeReq accesses 347011860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.018507 # miss rate for SCUpgradeReq accesses 347111860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.639570 # miss rate for ReadExReq accesses 347211860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.473281 # miss rate for ReadExReq accesses 347311860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.568568 # miss rate for ReadExReq accesses 347411860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.219987 # miss rate for ReadSharedReq accesses 347511860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.421271 # miss rate for ReadSharedReq accesses 347611860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.107793 # miss rate for ReadSharedReq accesses 347711860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.229647 # miss rate for ReadSharedReq accesses 347811860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.573794 # miss rate for ReadSharedReq accesses 347911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.141513 # miss rate for ReadSharedReq accesses 348011860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.220102 # miss rate for ReadSharedReq accesses 348111860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.099126 # miss rate for ReadSharedReq accesses 348211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.170050 # miss rate for ReadSharedReq accesses 348311860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.469588 # miss rate for ReadSharedReq accesses 348411860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.272633 # miss rate for ReadSharedReq accesses 348511860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu0.data 0.790053 # miss rate for InvalidateReq accesses 348611860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu1.data 0.442701 # miss rate for InvalidateReq accesses 348711860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_miss_rate::total 0.695870 # miss rate for InvalidateReq accesses 348811860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.219987 # miss rate for demand accesses 348911860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.421271 # miss rate for demand accesses 349011860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.107793 # miss rate for demand accesses 349111860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.290302 # miss rate for demand accesses 349211860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.573794 # miss rate for demand accesses 349311860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.141513 # miss rate for demand accesses 349411860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.220102 # miss rate for demand accesses 349511860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.099126 # miss rate for demand accesses 349611860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.209318 # miss rate for demand accesses 349711860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.469588 # miss rate for demand accesses 349811860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.290423 # miss rate for demand accesses 349911860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.219987 # miss rate for overall accesses 350011860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.421271 # miss rate for overall accesses 350111860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.107793 # miss rate for overall accesses 350211860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.290302 # miss rate for overall accesses 350311860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.573794 # miss rate for overall accesses 350411860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.141513 # miss rate for overall accesses 350511860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.220102 # miss rate for overall accesses 350611860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.099126 # miss rate for overall accesses 350711860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.209318 # miss rate for overall accesses 350811860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.469588 # miss rate for overall accesses 350911860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.290423 # miss rate for overall accesses 351011860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6990.052744 # average UpgradeReq miss latency 351111860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6330.413209 # average UpgradeReq miss latency 351211860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::total 6651.620970 # average UpgradeReq miss latency 351311860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 8741.045499 # average SCUpgradeReq miss latency 351411860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 10123.574144 # average SCUpgradeReq miss latency 351511860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::total 9438.609113 # average SCUpgradeReq miss latency 351611860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu0.data 107848.903848 # average ReadExReq miss latency 351711860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu1.data 108086.172778 # average ReadExReq miss latency 351811860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::total 107933.234295 # average ReadExReq miss latency 351911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 100870.375264 # average ReadSharedReq miss latency 352011860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 98382.393209 # average ReadSharedReq miss latency 352111860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 109115.354479 # average ReadSharedReq miss latency 352211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 109676.115930 # average ReadSharedReq miss latency 352311860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 154095.375378 # average ReadSharedReq miss latency 352411860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 106845.414497 # average ReadSharedReq miss latency 352511860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 107311.271676 # average ReadSharedReq miss latency 352611860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 111424.767058 # average ReadSharedReq miss latency 352711860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 118349.849195 # average ReadSharedReq miss latency 352811860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 153746.139154 # average ReadSharedReq miss latency 352911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::total 136670.920258 # average ReadSharedReq miss latency 353011860Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.dtb.walker 100870.375264 # average overall miss latency 353111860Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.itb.walker 98382.393209 # average overall miss latency 353211860Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.inst 109115.354479 # average overall miss latency 353311860Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.data 109080.463368 # average overall miss latency 353411860Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 154095.375378 # average overall miss latency 353511860Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.dtb.walker 106845.414497 # average overall miss latency 353611860Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.itb.walker 107311.271676 # average overall miss latency 353711860Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.inst 111424.767058 # average overall miss latency 353811860Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.data 115344.647907 # average overall miss latency 353911860Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 153746.139154 # average overall miss latency 354011860Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::total 133288.874553 # average overall miss latency 354111860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.dtb.walker 100870.375264 # average overall miss latency 354211860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.itb.walker 98382.393209 # average overall miss latency 354311860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.inst 109115.354479 # average overall miss latency 354411860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.data 109080.463368 # average overall miss latency 354511860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 154095.375378 # average overall miss latency 354611860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.dtb.walker 106845.414497 # average overall miss latency 354711860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.itb.walker 107311.271676 # average overall miss latency 354811860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.inst 111424.767058 # average overall miss latency 354911860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.data 115344.647907 # average overall miss latency 355011860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 153746.139154 # average overall miss latency 355111860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::total 133288.874553 # average overall miss latency 355211860Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_mshrs 15677 # number of cycles access was blocked 355310515SAli.Saidi@ARM.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 355411860Sandreas.hansson@arm.comsystem.l2c.blocked::no_mshrs 153 # number of cycles access was blocked 355510515SAli.Saidi@ARM.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 355611860Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs 102.464052 # average number of cycles each access was blocked 355710515SAli.Saidi@ARM.comsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 355811860Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 1420191 # number of writebacks 355911860Sandreas.hansson@arm.comsystem.l2c.writebacks::total 1420191 # number of writebacks 356011860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.inst 100 # number of ReadSharedReq MSHR hits 356111860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.data 8 # number of ReadSharedReq MSHR hits 356211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.l2cache.prefetcher 1 # number of ReadSharedReq MSHR hits 356311860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.inst 184 # number of ReadSharedReq MSHR hits 356411860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.data 35 # number of ReadSharedReq MSHR hits 356511860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::total 328 # number of ReadSharedReq MSHR hits 356611860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu0.inst 100 # number of demand (read+write) MSHR hits 356711860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu0.data 8 # number of demand (read+write) MSHR hits 356811860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits 356911860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.inst 184 # number of demand (read+write) MSHR hits 357011860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.data 35 # number of demand (read+write) MSHR hits 357111860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::total 328 # number of demand (read+write) MSHR hits 357211860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu0.inst 100 # number of overall MSHR hits 357311860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu0.data 8 # number of overall MSHR hits 357411860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 1 # number of overall MSHR hits 357511860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.inst 184 # number of overall MSHR hits 357611860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.data 35 # number of overall MSHR hits 357711860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::total 328 # number of overall MSHR hits 357811860Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_misses::writebacks 84488 # number of CleanEvict MSHR misses 357911860Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_misses::total 84488 # number of CleanEvict MSHR misses 358011860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu0.data 21614 # number of UpgradeReq MSHR misses 358111860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu1.data 22773 # number of UpgradeReq MSHR misses 358211860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::total 44387 # number of UpgradeReq MSHR misses 358311860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1033 # number of SCUpgradeReq MSHR misses 358411860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1052 # number of SCUpgradeReq MSHR misses 358511860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::total 2085 # number of SCUpgradeReq MSHR misses 358611860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu0.data 96389 # number of ReadExReq MSHR misses 358711860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu1.data 53149 # number of ReadExReq MSHR misses 358811860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::total 149538 # number of ReadExReq MSHR misses 358911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 3784 # number of ReadSharedReq MSHR misses 359011860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3652 # number of ReadSharedReq MSHR misses 359111860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.inst 65021 # number of ReadSharedReq MSHR misses 359211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.data 199284 # number of ReadSharedReq MSHR misses 359311860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 394601 # number of ReadSharedReq MSHR misses 359411860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2497 # number of ReadSharedReq MSHR misses 359511860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1730 # number of ReadSharedReq MSHR misses 359611860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.inst 57663 # number of ReadSharedReq MSHR misses 359711860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.data 128336 # number of ReadSharedReq MSHR misses 359811860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 264210 # number of ReadSharedReq MSHR misses 359911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::total 1120778 # number of ReadSharedReq MSHR misses 360011860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_misses::cpu0.data 461443 # number of InvalidateReq MSHR misses 360111860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_misses::cpu1.data 96191 # number of InvalidateReq MSHR misses 360211860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_misses::total 557634 # number of InvalidateReq MSHR misses 360311860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.dtb.walker 3784 # number of demand (read+write) MSHR misses 360411860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.itb.walker 3652 # number of demand (read+write) MSHR misses 360511860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.inst 65021 # number of demand (read+write) MSHR misses 360611860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.data 295673 # number of demand (read+write) MSHR misses 360711860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 394601 # number of demand (read+write) MSHR misses 360811860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.dtb.walker 2497 # number of demand (read+write) MSHR misses 360911860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.itb.walker 1730 # number of demand (read+write) MSHR misses 361011860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.inst 57663 # number of demand (read+write) MSHR misses 361111860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.data 181485 # number of demand (read+write) MSHR misses 361211860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 264210 # number of demand (read+write) MSHR misses 361311860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::total 1270316 # number of demand (read+write) MSHR misses 361411860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.dtb.walker 3784 # number of overall MSHR misses 361511860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.itb.walker 3652 # number of overall MSHR misses 361611860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.inst 65021 # number of overall MSHR misses 361711860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.data 295673 # number of overall MSHR misses 361811860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 394601 # number of overall MSHR misses 361911860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.dtb.walker 2497 # number of overall MSHR misses 362011860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.itb.walker 1730 # number of overall MSHR misses 362111860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.inst 57663 # number of overall MSHR misses 362211860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.data 181485 # number of overall MSHR misses 362311860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 264210 # number of overall MSHR misses 362411860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::total 1270316 # number of overall MSHR misses 362511860Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu0.inst 2093 # number of ReadReq MSHR uncacheable 362611860Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu0.data 15843 # number of ReadReq MSHR uncacheable 362711680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable 362811860Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu1.data 22962 # number of ReadReq MSHR uncacheable 362911860Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::total 40965 # number of ReadReq MSHR uncacheable 363011860Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable::cpu0.data 17283 # number of WriteReq MSHR uncacheable 363111860Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable::cpu1.data 21406 # number of WriteReq MSHR uncacheable 363211860Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable::total 38689 # number of WriteReq MSHR uncacheable 363311860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu0.inst 2093 # number of overall MSHR uncacheable misses 363411860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu0.data 33126 # number of overall MSHR uncacheable misses 363511680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses 363611860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu1.data 44368 # number of overall MSHR uncacheable misses 363711860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::total 79654 # number of overall MSHR uncacheable misses 363811860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 437927500 # number of UpgradeReq MSHR miss cycles 363911860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 473487498 # number of UpgradeReq MSHR miss cycles 364011860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::total 911414998 # number of UpgradeReq MSHR miss cycles 364111860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 24955000 # number of SCUpgradeReq MSHR miss cycles 364211860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 25870500 # number of SCUpgradeReq MSHR miss cycles 364311860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::total 50825500 # number of SCUpgradeReq MSHR miss cycles 364411860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu0.data 9431397842 # number of ReadExReq MSHR miss cycles 364511860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5212978417 # number of ReadExReq MSHR miss cycles 364611860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::total 14644376259 # number of ReadExReq MSHR miss cycles 364711860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 343853001 # number of ReadSharedReq MSHR miss cycles 364811860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 322772001 # number of ReadSharedReq MSHR miss cycles 364911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 6445445567 # number of ReadSharedReq MSHR miss cycles 365011860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 19863990276 # number of ReadSharedReq MSHR miss cycles 365111860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 56859943438 # number of ReadSharedReq MSHR miss cycles 365211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 241821503 # number of ReadSharedReq MSHR miss cycles 365311860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 168348500 # number of ReadSharedReq MSHR miss cycles 365411860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 5850563554 # number of ReadSharedReq MSHR miss cycles 365511860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 13904670289 # number of ReadSharedReq MSHR miss cycles 365611860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 37978912479 # number of ReadSharedReq MSHR miss cycles 365711860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::total 141980320608 # number of ReadSharedReq MSHR miss cycles 365811860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 11387571771 # number of InvalidateReq MSHR miss cycles 365911860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1886134001 # number of InvalidateReq MSHR miss cycles 366011860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_miss_latency::total 13273705772 # number of InvalidateReq MSHR miss cycles 366111860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 343853001 # number of demand (read+write) MSHR miss cycles 366211860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.itb.walker 322772001 # number of demand (read+write) MSHR miss cycles 366311860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.inst 6445445567 # number of demand (read+write) MSHR miss cycles 366411860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.data 29295388118 # number of demand (read+write) MSHR miss cycles 366511860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 56859943438 # number of demand (read+write) MSHR miss cycles 366611860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 241821503 # number of demand (read+write) MSHR miss cycles 366711860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.itb.walker 168348500 # number of demand (read+write) MSHR miss cycles 366811860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.inst 5850563554 # number of demand (read+write) MSHR miss cycles 366911860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.data 19117648706 # number of demand (read+write) MSHR miss cycles 367011860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 37978912479 # number of demand (read+write) MSHR miss cycles 367111860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::total 156624696867 # number of demand (read+write) MSHR miss cycles 367211860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 343853001 # number of overall MSHR miss cycles 367311860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.itb.walker 322772001 # number of overall MSHR miss cycles 367411860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.inst 6445445567 # number of overall MSHR miss cycles 367511860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.data 29295388118 # number of overall MSHR miss cycles 367611860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 56859943438 # number of overall MSHR miss cycles 367711860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 241821503 # number of overall MSHR miss cycles 367811860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.itb.walker 168348500 # number of overall MSHR miss cycles 367911860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.inst 5850563554 # number of overall MSHR miss cycles 368011860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.data 19117648706 # number of overall MSHR miss cycles 368111860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 37978912479 # number of overall MSHR miss cycles 368211860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::total 156624696867 # number of overall MSHR miss cycles 368311860Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 147855500 # number of ReadReq MSHR uncacheable cycles 368411860Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2484594002 # number of ReadReq MSHR uncacheable cycles 368511860Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5308000 # number of ReadReq MSHR uncacheable cycles 368611860Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3460097504 # number of ReadReq MSHR uncacheable cycles 368711860Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::total 6097855006 # number of ReadReq MSHR uncacheable cycles 368811860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.inst 147855500 # number of overall MSHR uncacheable cycles 368911860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.data 2484594002 # number of overall MSHR uncacheable cycles 369011860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5308000 # number of overall MSHR uncacheable cycles 369111860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.data 3460097504 # number of overall MSHR uncacheable cycles 369211860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::total 6097855006 # number of overall MSHR uncacheable cycles 369310892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 369410892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 369511860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.090026 # mshr miss rate for UpgradeReq accesses 369611860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.113299 # mshr miss rate for UpgradeReq accesses 369711860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::total 0.100631 # mshr miss rate for UpgradeReq accesses 369811860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.016811 # mshr miss rate for SCUpgradeReq accesses 369911860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.020542 # mshr miss rate for SCUpgradeReq accesses 370011860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::total 0.018507 # mshr miss rate for SCUpgradeReq accesses 370111860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.639570 # mshr miss rate for ReadExReq accesses 370211860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.473281 # mshr miss rate for ReadExReq accesses 370311860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::total 0.568568 # mshr miss rate for ReadExReq accesses 370411860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.219987 # mshr miss rate for ReadSharedReq accesses 370511860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.421271 # mshr miss rate for ReadSharedReq accesses 370611860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.107628 # mshr miss rate for ReadSharedReq accesses 370711860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.229637 # mshr miss rate for ReadSharedReq accesses 370811860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.573792 # mshr miss rate for ReadSharedReq accesses 370911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.141513 # mshr miss rate for ReadSharedReq accesses 371011860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.220102 # mshr miss rate for ReadSharedReq accesses 371111860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.098810 # mshr miss rate for ReadSharedReq accesses 371211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.170004 # mshr miss rate for ReadSharedReq accesses 371311860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.469588 # mshr miss rate for ReadSharedReq accesses 371411860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::total 0.272553 # mshr miss rate for ReadSharedReq accesses 371511860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.790053 # mshr miss rate for InvalidateReq accesses 371611860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.442701 # mshr miss rate for InvalidateReq accesses 371711860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::total 0.695870 # mshr miss rate for InvalidateReq accesses 371811860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.219987 # mshr miss rate for demand accesses 371911860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.421271 # mshr miss rate for demand accesses 372011860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.107628 # mshr miss rate for demand accesses 372111860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.data 0.290294 # mshr miss rate for demand accesses 372211860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.573792 # mshr miss rate for demand accesses 372311860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.141513 # mshr miss rate for demand accesses 372411860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.220102 # mshr miss rate for demand accesses 372511860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.098810 # mshr miss rate for demand accesses 372611860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.data 0.209277 # mshr miss rate for demand accesses 372711860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.469588 # mshr miss rate for demand accesses 372811860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::total 0.290348 # mshr miss rate for demand accesses 372911860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.219987 # mshr miss rate for overall accesses 373011860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.421271 # mshr miss rate for overall accesses 373111860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.107628 # mshr miss rate for overall accesses 373211860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.data 0.290294 # mshr miss rate for overall accesses 373311860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.573792 # mshr miss rate for overall accesses 373411860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.141513 # mshr miss rate for overall accesses 373511860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.220102 # mshr miss rate for overall accesses 373611860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.098810 # mshr miss rate for overall accesses 373711860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.data 0.209277 # mshr miss rate for overall accesses 373811860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.469588 # mshr miss rate for overall accesses 373911860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::total 0.290348 # mshr miss rate for overall accesses 374011860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20261.288979 # average UpgradeReq mshr miss latency 374111860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20791.617178 # average UpgradeReq mshr miss latency 374211860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 20533.376845 # average UpgradeReq mshr miss latency 374311860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24157.792836 # average SCUpgradeReq mshr miss latency 374411860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24591.730038 # average SCUpgradeReq mshr miss latency 374511860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24376.738609 # average SCUpgradeReq mshr miss latency 374611860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 97847.242341 # average ReadExReq mshr miss latency 374711860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 98082.342415 # average ReadExReq mshr miss latency 374811860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 97930.801930 # average ReadExReq mshr miss latency 374911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 90870.243393 # average ReadSharedReq mshr miss latency 375011860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 88382.256572 # average ReadSharedReq mshr miss latency 375111860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 99128.674844 # average ReadSharedReq mshr miss latency 375211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 99676.794304 # average ReadSharedReq mshr miss latency 375311860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 144094.777859 # average ReadSharedReq mshr miss latency 375411860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 96844.814978 # average ReadSharedReq mshr miss latency 375511860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 97311.271676 # average ReadSharedReq mshr miss latency 375611860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 101461.310615 # average ReadSharedReq mshr miss latency 375711860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 108345.828832 # average ReadSharedReq mshr miss latency 375811860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143745.174214 # average ReadSharedReq mshr miss latency 375911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126680.145941 # average ReadSharedReq mshr miss latency 376011860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 24678.176440 # average InvalidateReq mshr miss latency 376111860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19608.216995 # average InvalidateReq mshr miss latency 376211860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::total 23803.616300 # average InvalidateReq mshr miss latency 376311860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 90870.243393 # average overall mshr miss latency 376411860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 88382.256572 # average overall mshr miss latency 376511860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 99128.674844 # average overall mshr miss latency 376611860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 99080.362827 # average overall mshr miss latency 376711860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 144094.777859 # average overall mshr miss latency 376811860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 96844.814978 # average overall mshr miss latency 376911860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 97311.271676 # average overall mshr miss latency 377011860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 101461.310615 # average overall mshr miss latency 377111860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 105340.103623 # average overall mshr miss latency 377211860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143745.174214 # average overall mshr miss latency 377311860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 123295.854628 # average overall mshr miss latency 377411860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 90870.243393 # average overall mshr miss latency 377511860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 88382.256572 # average overall mshr miss latency 377611860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 99128.674844 # average overall mshr miss latency 377711860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 99080.362827 # average overall mshr miss latency 377811860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 144094.777859 # average overall mshr miss latency 377911860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 96844.814978 # average overall mshr miss latency 378011860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 97311.271676 # average overall mshr miss latency 378111860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 101461.310615 # average overall mshr miss latency 378211860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 105340.103623 # average overall mshr miss latency 378311860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143745.174214 # average overall mshr miss latency 378411860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 123295.854628 # average overall mshr miss latency 378511860Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70642.857143 # average ReadReq mshr uncacheable latency 378611860Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 156825.980054 # average ReadReq mshr uncacheable latency 378711860Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 79223.880597 # average ReadReq mshr uncacheable latency 378811860Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150687.984670 # average ReadReq mshr uncacheable latency 378911860Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total 148855.242426 # average ReadReq mshr uncacheable latency 379011860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70642.857143 # average overall mshr uncacheable latency 379111860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 75004.347099 # average overall mshr uncacheable latency 379211860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 79223.880597 # average overall mshr uncacheable latency 379311860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 77986.330328 # average overall mshr uncacheable latency 379411860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::total 76554.284857 # average overall mshr uncacheable latency 379511860Sandreas.hansson@arm.comsystem.membus.snoop_filter.tot_requests 4427188 # Total number of requests made to the snoop filter. 379611860Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_single_requests 2544778 # Number of requests hitting in the snoop filter with a single holder of the requested data. 379711860Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_multi_requests 3484 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 379811502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 379911502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 380011502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 380111860Sandreas.hansson@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 380211860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 40965 # Transaction distribution 380311860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 1170673 # Transaction distribution 380411860Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 38689 # Transaction distribution 380511860Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 38689 # Transaction distribution 380611860Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty 1526901 # Transaction distribution 380711860Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 301973 # Transaction distribution 380811860Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 291943 # Transaction distribution 380911860Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 287508 # Transaction distribution 381011860Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 8 # Transaction distribution 381111860Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution 381211860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 162891 # Transaction distribution 381311860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 148894 # Transaction distribution 381411860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 1129708 # Transaction distribution 381511860Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 674487 # Transaction distribution 381611860Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 26345 # Transaction distribution 381711860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122406 # Packet count per connected master and slave (bytes) 381811201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) 381911860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27362 # Packet count per connected master and slave (bytes) 382011860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5422541 # Packet count per connected master and slave (bytes) 382111860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 5572385 # Packet count per connected master and slave (bytes) 382211860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238081 # Packet count per connected master and slave (bytes) 382311860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 238081 # Packet count per connected master and slave (bytes) 382411860Sandreas.hansson@arm.comsystem.membus.pkt_count::total 5810466 # Packet count per connected master and slave (bytes) 382511860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155536 # Cumulative packet size per connected master and slave (bytes) 382611201Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes) 382711860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54724 # Cumulative packet size per connected master and slave (bytes) 382811860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 172160384 # Cumulative packet size per connected master and slave (bytes) 382911860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 172371200 # Cumulative packet size per connected master and slave (bytes) 383011860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7263808 # Cumulative packet size per connected master and slave (bytes) 383111860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7263808 # Cumulative packet size per connected master and slave (bytes) 383211860Sandreas.hansson@arm.comsystem.membus.pkt_size::total 179635008 # Cumulative packet size per connected master and slave (bytes) 383311860Sandreas.hansson@arm.comsystem.membus.snoops 585668 # Total snoops (count) 383411860Sandreas.hansson@arm.comsystem.membus.snoopTraffic 182912 # Total snoop traffic (bytes) 383511860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 2626196 # Request fanout histogram 383611860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0.011361 # Request fanout histogram 383711860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0.105982 # Request fanout histogram 383810576Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 383911860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 2596359 98.86% 98.86% # Request fanout histogram 384011860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 29837 1.14% 100.00% # Request fanout histogram 384110576Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 384210576Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 384311502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 384410576Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 384511860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 2626196 # Request fanout histogram 384611860Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 97843991 # Layer occupancy (ticks) 384710576Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 384811441Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 52000 # Layer occupancy (ticks) 384910576Sandreas.hansson@arm.comsystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 385011860Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 22899493 # Layer occupancy (ticks) 385110576Sandreas.hansson@arm.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 385211860Sandreas.hansson@arm.comsystem.membus.reqLayer5.occupancy 10387724889 # Layer occupancy (ticks) 385310585Sandreas.hansson@arm.comsystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 385411860Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 6773203746 # Layer occupancy (ticks) 385510576Sandreas.hansson@arm.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 385611860Sandreas.hansson@arm.comsystem.membus.respLayer3.occupancy 76561844 # Layer occupancy (ticks) 385710576Sandreas.hansson@arm.comsystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 385811860Sandreas.hansson@arm.comsystem.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 385911860Sandreas.hansson@arm.comsystem.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 386011860Sandreas.hansson@arm.comsystem.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 386111860Sandreas.hansson@arm.comsystem.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 386211860Sandreas.hansson@arm.comsystem.realview.gic.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 386311860Sandreas.hansson@arm.comsystem.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 386411860Sandreas.hansson@arm.comsystem.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 386511239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 386611239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 386711239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 386811239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 386911239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 387011239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 387111860Sandreas.hansson@arm.comsystem.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 387211860Sandreas.hansson@arm.comsystem.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 387310515SAli.Saidi@ARM.comsystem.realview.ethernet.txBytes 966 # Bytes Transmitted 387410515SAli.Saidi@ARM.comsystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 387510515SAli.Saidi@ARM.comsystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 387610515SAli.Saidi@ARM.comsystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 387710515SAli.Saidi@ARM.comsystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 387810515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 387910515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 388010515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 388110515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 388210515SAli.Saidi@ARM.comsystem.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 388310515SAli.Saidi@ARM.comsystem.realview.ethernet.totPackets 3 # Total Packets 388410515SAli.Saidi@ARM.comsystem.realview.ethernet.totBytes 966 # Total Bytes 388510515SAli.Saidi@ARM.comsystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 388610515SAli.Saidi@ARM.comsystem.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 388710515SAli.Saidi@ARM.comsystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 388810515SAli.Saidi@ARM.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 388910515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 389010515SAli.Saidi@ARM.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 389110515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 389210515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 389310515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 389410515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 389510515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 389610515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 389710515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 389810515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 389910515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 390010515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 390110515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 390210515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 390310515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 390410515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 390510515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 390610515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 390710515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 390810515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 390910515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 391010515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 391110515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 391210515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 391310515SAli.Saidi@ARM.comsystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 391410515SAli.Saidi@ARM.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 391511860Sandreas.hansson@arm.comsystem.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 391611860Sandreas.hansson@arm.comsystem.realview.ide.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 391711860Sandreas.hansson@arm.comsystem.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 391811860Sandreas.hansson@arm.comsystem.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 391911860Sandreas.hansson@arm.comsystem.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 392011860Sandreas.hansson@arm.comsystem.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 392111860Sandreas.hansson@arm.comsystem.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 392211239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 392311239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 392411239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 392511239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 392611860Sandreas.hansson@arm.comsystem.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 392711860Sandreas.hansson@arm.comsystem.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 392811860Sandreas.hansson@arm.comsystem.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 392911860Sandreas.hansson@arm.comsystem.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 393011860Sandreas.hansson@arm.comsystem.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 393111860Sandreas.hansson@arm.comsystem.realview.uart.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 393211860Sandreas.hansson@arm.comsystem.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 393311860Sandreas.hansson@arm.comsystem.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 393411860Sandreas.hansson@arm.comsystem.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 393511860Sandreas.hansson@arm.comsystem.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 393611860Sandreas.hansson@arm.comsystem.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 393711860Sandreas.hansson@arm.comsystem.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 393811860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_requests 12840687 # Total number of requests made to the snoop filter. 393911860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 6804210 # Number of requests hitting in the snoop filter with a single holder of the requested data. 394011860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 2233432 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 394111860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 286650 # Total number of snoops made to the snoop filter. 394211860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 259465 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 394311860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 27185 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 394411860Sandreas.hansson@arm.comsystem.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 394511860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 40967 # Transaction distribution 394611860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 4895074 # Transaction distribution 394711860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 38689 # Transaction distribution 394811860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 38689 # Transaction distribution 394911860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 4582152 # Transaction distribution 395011860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution 395111860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::CleanEvict 2976886 # Transaction distribution 395211860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 687999 # Transaction distribution 395311860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 398085 # Transaction distribution 395411860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 1086084 # Transaction distribution 395511860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeFailReq 122 # Transaction distribution 395611860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution 395711860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 311857 # Transaction distribution 395811860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 311857 # Transaction distribution 395911860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 4854758 # Transaction distribution 396011860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::InvalidateReq 900244 # Transaction distribution 396111860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::InvalidateResp 885499 # Transaction distribution 396211860Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10402586 # Packet count per connected master and slave (bytes) 396311860Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8325072 # Packet count per connected master and slave (bytes) 396411860Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 18727658 # Packet count per connected master and slave (bytes) 396511860Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 271068295 # Cumulative packet size per connected master and slave (bytes) 396611860Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 211681017 # Cumulative packet size per connected master and slave (bytes) 396711860Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 482749312 # Cumulative packet size per connected master and slave (bytes) 396811860Sandreas.hansson@arm.comsystem.toL2Bus.snoops 3295138 # Total snoops (count) 396911860Sandreas.hansson@arm.comsystem.toL2Bus.snoopTraffic 141512016 # Total snoop traffic (bytes) 397011860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 9092383 # Request fanout histogram 397111860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 0.348495 # Request fanout histogram 397211860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.482728 # Request fanout histogram 397310515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 397411860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::0 5950920 65.45% 65.45% # Request fanout histogram 397511860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 3114278 34.25% 99.70% # Request fanout histogram 397611860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 27185 0.30% 100.00% # Request fanout histogram 397710515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 397811138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 397910515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 398011860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 9092383 # Request fanout histogram 398111860Sandreas.hansson@arm.comsystem.toL2Bus.reqLayer0.occupancy 10118543300 # Layer occupancy (ticks) 398210515SAli.Saidi@ARM.comsystem.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 398311860Sandreas.hansson@arm.comsystem.toL2Bus.snoopLayer0.occupancy 8937131 # Layer occupancy (ticks) 398410515SAli.Saidi@ARM.comsystem.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 398511860Sandreas.hansson@arm.comsystem.toL2Bus.respLayer0.occupancy 4714839859 # Layer occupancy (ticks) 398610515SAli.Saidi@ARM.comsystem.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 398711860Sandreas.hansson@arm.comsystem.toL2Bus.respLayer1.occupancy 4090244927 # Layer occupancy (ticks) 398810515SAli.Saidi@ARM.comsystem.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 398910515SAli.Saidi@ARM.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 399011860Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 5530 # number of quiesce instructions executed 399110515SAli.Saidi@ARM.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 399211860Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 13684 # number of quiesce instructions executed 399310515SAli.Saidi@ARM.com 399410515SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 3995