stats.txt revision 11547:dd6dfd38b6c2
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.355903 # Number of seconds simulated 4sim_ticks 47355903328000 # Number of ticks simulated 5final_tick 47355903328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 170836 # Simulator instruction rate (inst/s) 8host_op_rate 200933 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9157476763 # Simulator tick rate (ticks/s) 10host_mem_usage 772600 # Number of bytes of host memory used 11host_seconds 5171.28 # Real time elapsed on the host 12sim_insts 883443630 # Number of instructions simulated 13sim_ops 1039082168 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 131584 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 123776 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 7567040 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 14160840 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 16409728 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 122112 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.itb.walker 100992 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.inst 3330560 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.data 9705936 # Number of bytes read from this memory 26system.physmem.bytes_read::cpu1.l2cache.prefetcher 10452736 # Number of bytes read from this memory 27system.physmem.bytes_read::realview.ide 444224 # Number of bytes read from this memory 28system.physmem.bytes_read::total 62549528 # Number of bytes read from this memory 29system.physmem.bytes_inst_read::cpu0.inst 7567040 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::cpu1.inst 3330560 # Number of instructions bytes read from this memory 31system.physmem.bytes_inst_read::total 10897600 # Number of instructions bytes read from this memory 32system.physmem.bytes_written::writebacks 75633728 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 34system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 35system.physmem.bytes_written::total 75654312 # Number of bytes written to this memory 36system.physmem.num_reads::cpu0.dtb.walker 2056 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.itb.walker 1934 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.inst 118235 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.data 221276 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu0.l2cache.prefetcher 256402 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.dtb.walker 1908 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.itb.walker 1578 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.inst 52040 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.data 151668 # Number of read requests responded to by this memory 45system.physmem.num_reads::cpu1.l2cache.prefetcher 163324 # Number of read requests responded to by this memory 46system.physmem.num_reads::realview.ide 6941 # Number of read requests responded to by this memory 47system.physmem.num_reads::total 977362 # Number of read requests responded to by this memory 48system.physmem.num_writes::writebacks 1181777 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 50system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 51system.physmem.num_writes::total 1184351 # Number of write requests responded to by this memory 52system.physmem.bw_read::cpu0.dtb.walker 2779 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.itb.walker 2614 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.inst 159791 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.data 299030 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu0.l2cache.prefetcher 346519 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.dtb.walker 2579 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.itb.walker 2133 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.inst 70330 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.data 204957 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::cpu1.l2cache.prefetcher 220727 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::realview.ide 9381 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_read::total 1320839 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu0.inst 159791 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::cpu1.inst 70330 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_inst_read::total 230121 # Instruction read bandwidth from this memory (bytes/s) 67system.physmem.bw_write::writebacks 1597134 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_write::total 1597569 # Write bandwidth from this memory (bytes/s) 71system.physmem.bw_total::writebacks 1597134 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.dtb.walker 2779 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.itb.walker 2614 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.inst 159791 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.data 299465 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu0.l2cache.prefetcher 346519 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.dtb.walker 2579 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.itb.walker 2133 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.inst 70330 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.data 204957 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::cpu1.l2cache.prefetcher 220727 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::realview.ide 9381 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::total 2918408 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.readReqs 977362 # Number of read requests accepted 85system.physmem.writeReqs 1184351 # Number of write requests accepted 86system.physmem.readBursts 977362 # Number of DRAM read bursts, including those serviced by the write queue 87system.physmem.writeBursts 1184351 # Number of DRAM write bursts, including those merged in the write queue 88system.physmem.bytesReadDRAM 62527296 # Total number of bytes read from DRAM 89system.physmem.bytesReadWrQ 23872 # Total number of bytes read from write queue 90system.physmem.bytesWritten 75653504 # Total number of bytes written to DRAM 91system.physmem.bytesReadSys 62549528 # Total read bytes from the system interface side 92system.physmem.bytesWrittenSys 75654312 # Total written bytes from the system interface side 93system.physmem.servicedByWrQ 373 # Number of DRAM read bursts serviced by the write queue 94system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one 95system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 96system.physmem.perBankRdBursts::0 54912 # Per bank write bursts 97system.physmem.perBankRdBursts::1 56908 # Per bank write bursts 98system.physmem.perBankRdBursts::2 51582 # Per bank write bursts 99system.physmem.perBankRdBursts::3 63469 # Per bank write bursts 100system.physmem.perBankRdBursts::4 61411 # Per bank write bursts 101system.physmem.perBankRdBursts::5 61841 # Per bank write bursts 102system.physmem.perBankRdBursts::6 57272 # Per bank write bursts 103system.physmem.perBankRdBursts::7 62841 # Per bank write bursts 104system.physmem.perBankRdBursts::8 51834 # Per bank write bursts 105system.physmem.perBankRdBursts::9 112088 # Per bank write bursts 106system.physmem.perBankRdBursts::10 55237 # Per bank write bursts 107system.physmem.perBankRdBursts::11 58857 # Per bank write bursts 108system.physmem.perBankRdBursts::12 56745 # Per bank write bursts 109system.physmem.perBankRdBursts::13 58205 # Per bank write bursts 110system.physmem.perBankRdBursts::14 53859 # Per bank write bursts 111system.physmem.perBankRdBursts::15 59928 # Per bank write bursts 112system.physmem.perBankWrBursts::0 69820 # Per bank write bursts 113system.physmem.perBankWrBursts::1 73385 # Per bank write bursts 114system.physmem.perBankWrBursts::2 70846 # Per bank write bursts 115system.physmem.perBankWrBursts::3 76844 # Per bank write bursts 116system.physmem.perBankWrBursts::4 76655 # Per bank write bursts 117system.physmem.perBankWrBursts::5 78828 # Per bank write bursts 118system.physmem.perBankWrBursts::6 72793 # Per bank write bursts 119system.physmem.perBankWrBursts::7 76848 # Per bank write bursts 120system.physmem.perBankWrBursts::8 69899 # Per bank write bursts 121system.physmem.perBankWrBursts::9 74878 # Per bank write bursts 122system.physmem.perBankWrBursts::10 69893 # Per bank write bursts 123system.physmem.perBankWrBursts::11 73658 # Per bank write bursts 124system.physmem.perBankWrBursts::12 73258 # Per bank write bursts 125system.physmem.perBankWrBursts::13 76164 # Per bank write bursts 126system.physmem.perBankWrBursts::14 72361 # Per bank write bursts 127system.physmem.perBankWrBursts::15 75956 # Per bank write bursts 128system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 129system.physmem.numWrRetry 28 # Number of times write queue was full causing retry 130system.physmem.totGap 47355901307500 # Total gap between requests 131system.physmem.readPktSize::0 0 # Read request sizes (log2) 132system.physmem.readPktSize::1 0 # Read request sizes (log2) 133system.physmem.readPktSize::2 0 # Read request sizes (log2) 134system.physmem.readPktSize::3 25 # Read request sizes (log2) 135system.physmem.readPktSize::4 5 # Read request sizes (log2) 136system.physmem.readPktSize::5 0 # Read request sizes (log2) 137system.physmem.readPktSize::6 977332 # Read request sizes (log2) 138system.physmem.writePktSize::0 0 # Write request sizes (log2) 139system.physmem.writePktSize::1 0 # Write request sizes (log2) 140system.physmem.writePktSize::2 2 # Write request sizes (log2) 141system.physmem.writePktSize::3 2572 # Write request sizes (log2) 142system.physmem.writePktSize::4 0 # Write request sizes (log2) 143system.physmem.writePktSize::5 0 # Write request sizes (log2) 144system.physmem.writePktSize::6 1181777 # Write request sizes (log2) 145system.physmem.rdQLenPdf::0 653624 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::1 118392 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::2 43298 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::3 33441 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::4 28719 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::5 26608 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::6 24389 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::7 21172 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::8 19081 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::9 3369 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::10 1474 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::11 993 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::12 791 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::13 539 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::14 292 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::15 238 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::16 217 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::17 181 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::18 95 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::19 68 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 176system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 177system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::15 26534 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::16 34947 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::17 50320 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::18 57992 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::19 63163 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::20 65860 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::21 68534 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::22 70437 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::23 72935 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::24 73131 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::25 75636 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::26 78760 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::27 75174 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::28 74381 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::29 78953 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::30 69890 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::31 64098 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::32 61316 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::33 3117 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::34 2352 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::35 1927 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::36 1425 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::37 1156 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::38 977 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::39 837 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::40 699 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::41 531 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::42 599 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::43 547 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::44 500 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::45 401 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::46 502 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::47 396 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::48 357 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::49 372 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::50 385 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::51 328 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::52 331 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::53 310 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::54 300 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::55 259 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::56 273 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::57 241 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::58 225 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::59 168 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::60 172 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::61 147 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::62 94 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::63 102 # What write queue length does an incoming req see 241system.physmem.bytesPerActivate::samples 973522 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::mean 141.938602 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::gmean 96.538228 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::stdev 191.263762 # Bytes accessed per row activation 245system.physmem.bytesPerActivate::0-127 662821 68.08% 68.08% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::128-255 188353 19.35% 87.43% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::256-383 43865 4.51% 91.94% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::384-511 19742 2.03% 93.97% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::512-639 14303 1.47% 95.44% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::640-767 9443 0.97% 96.41% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::768-895 6391 0.66% 97.06% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::896-1023 5216 0.54% 97.60% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::1024-1151 23388 2.40% 100.00% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::total 973522 # Bytes accessed per row activation 255system.physmem.rdPerTurnAround::samples 57494 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::mean 16.992747 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::stdev 164.605284 # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::0-1023 57491 99.99% 99.99% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes 262system.physmem.rdPerTurnAround::total 57494 # Reads before turning the bus around for writes 263system.physmem.wrPerTurnAround::samples 57494 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::mean 20.560163 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::gmean 18.793170 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::stdev 13.728131 # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::16-19 49230 85.63% 85.63% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::20-23 2347 4.08% 89.71% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::24-27 805 1.40% 91.11% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::28-31 601 1.05% 92.15% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::32-35 998 1.74% 93.89% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::36-39 486 0.85% 94.74% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::40-43 329 0.57% 95.31% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::44-47 263 0.46% 95.76% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::48-51 216 0.38% 96.14% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::52-55 180 0.31% 96.45% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::56-59 129 0.22% 96.68% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::60-63 154 0.27% 96.95% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::64-67 478 0.83% 97.78% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::68-71 131 0.23% 98.01% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::72-75 143 0.25% 98.25% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::76-79 111 0.19% 98.45% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::80-83 107 0.19% 98.63% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::84-87 71 0.12% 98.76% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::88-91 85 0.15% 98.90% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::92-95 71 0.12% 99.03% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::96-99 101 0.18% 99.20% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::100-103 73 0.13% 99.33% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::104-107 62 0.11% 99.44% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::108-111 52 0.09% 99.53% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::112-115 38 0.07% 99.59% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::116-119 47 0.08% 99.68% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::120-123 26 0.05% 99.72% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::124-127 37 0.06% 99.79% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::128-131 49 0.09% 99.87% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::132-135 22 0.04% 99.91% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::136-139 8 0.01% 99.92% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::140-143 12 0.02% 99.94% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::144-147 6 0.01% 99.95% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::148-151 5 0.01% 99.96% # Writes before turning the bus around for reads 301system.physmem.wrPerTurnAround::152-155 2 0.00% 99.97% # Writes before turning the bus around for reads 302system.physmem.wrPerTurnAround::160-163 6 0.01% 99.98% # Writes before turning the bus around for reads 303system.physmem.wrPerTurnAround::172-175 4 0.01% 99.98% # Writes before turning the bus around for reads 304system.physmem.wrPerTurnAround::176-179 1 0.00% 99.99% # Writes before turning the bus around for reads 305system.physmem.wrPerTurnAround::184-187 1 0.00% 99.99% # Writes before turning the bus around for reads 306system.physmem.wrPerTurnAround::188-191 2 0.00% 99.99% # Writes before turning the bus around for reads 307system.physmem.wrPerTurnAround::192-195 3 0.01% 100.00% # Writes before turning the bus around for reads 308system.physmem.wrPerTurnAround::220-223 1 0.00% 100.00% # Writes before turning the bus around for reads 309system.physmem.wrPerTurnAround::236-239 1 0.00% 100.00% # Writes before turning the bus around for reads 310system.physmem.wrPerTurnAround::total 57494 # Writes before turning the bus around for reads 311system.physmem.totQLat 32578317305 # Total ticks spent queuing 312system.physmem.totMemAccLat 50896861055 # Total ticks spent from burst creation until serviced by the DRAM 313system.physmem.totBusLat 4884945000 # Total ticks spent in databus transfers 314system.physmem.avgQLat 33345.63 # Average queueing delay per DRAM burst 315system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 316system.physmem.avgMemAccLat 52095.63 # Average memory access latency per DRAM burst 317system.physmem.avgRdBW 1.32 # Average DRAM read bandwidth in MiByte/s 318system.physmem.avgWrBW 1.60 # Average achieved write bandwidth in MiByte/s 319system.physmem.avgRdBWSys 1.32 # Average system read bandwidth in MiByte/s 320system.physmem.avgWrBWSys 1.60 # Average system write bandwidth in MiByte/s 321system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 322system.physmem.busUtil 0.02 # Data bus utilization in percentage 323system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 324system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 325system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing 326system.physmem.avgWrQLen 22.69 # Average write queue length when enqueuing 327system.physmem.readRowHits 734277 # Number of row buffer hits during reads 328system.physmem.writeRowHits 451275 # Number of row buffer hits during writes 329system.physmem.readRowHitRate 75.16 # Row buffer hit rate for reads 330system.physmem.writeRowHitRate 38.18 # Row buffer hit rate for writes 331system.physmem.avgGap 21906655.19 # Average gap between requests 332system.physmem.pageHitRate 54.91 # Row buffer hit rate, read and write combined 333system.physmem_0.actEnergy 3752269920 # Energy for activate commands per rank (pJ) 334system.physmem_0.preEnergy 2047369500 # Energy for precharge commands per rank (pJ) 335system.physmem_0.readEnergy 3667786200 # Energy for read commands per rank (pJ) 336system.physmem_0.writeEnergy 3862203120 # Energy for write commands per rank (pJ) 337system.physmem_0.refreshEnergy 3093057342960 # Energy for refresh commands per rank (pJ) 338system.physmem_0.actBackEnergy 1180767055500 # Energy for active background per rank (pJ) 339system.physmem_0.preBackEnergy 27377781027000 # Energy for precharge background per rank (pJ) 340system.physmem_0.totalEnergy 31664935054200 # Total energy per rank (pJ) 341system.physmem_0.averagePower 668.658673 # Core power per rank (mW) 342system.physmem_0.memoryStateTime::IDLE 45545161867023 # Time in different power states 343system.physmem_0.memoryStateTime::REF 1581317660000 # Time in different power states 344system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 345system.physmem_0.memoryStateTime::ACT 229423166977 # Time in different power states 346system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 347system.physmem_1.actEnergy 3607556400 # Energy for activate commands per rank (pJ) 348system.physmem_1.preEnergy 1968408750 # Energy for precharge commands per rank (pJ) 349system.physmem_1.readEnergy 3952673400 # Energy for read commands per rank (pJ) 350system.physmem_1.writeEnergy 3797714160 # Energy for write commands per rank (pJ) 351system.physmem_1.refreshEnergy 3093057342960 # Energy for refresh commands per rank (pJ) 352system.physmem_1.actBackEnergy 1177905490200 # Energy for active background per rank (pJ) 353system.physmem_1.preBackEnergy 27380291180250 # Energy for precharge background per rank (pJ) 354system.physmem_1.totalEnergy 31664580366120 # Total energy per rank (pJ) 355system.physmem_1.averagePower 668.651183 # Core power per rank (mW) 356system.physmem_1.memoryStateTime::IDLE 45549316476567 # Time in different power states 357system.physmem_1.memoryStateTime::REF 1581317660000 # Time in different power states 358system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 359system.physmem_1.memoryStateTime::ACT 225268560933 # Time in different power states 360system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 361system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 362system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory 363system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 364system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory 365system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 366system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory 367system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory 368system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory 369system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory 370system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory 371system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 372system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory 373system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 374system.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory 375system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) 376system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 377system.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s) 378system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 379system.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s) 380system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) 381system.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s) 382system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) 383system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) 384system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 385system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s) 386system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 387system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) 388system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 389system.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 390system.bridge.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 391system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 392system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 393system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 394system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 395system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 396system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 397system.cpu0.branchPred.lookups 145452632 # Number of BP lookups 398system.cpu0.branchPred.condPredicted 102233764 # Number of conditional branches predicted 399system.cpu0.branchPred.condIncorrect 6537956 # Number of conditional branches incorrect 400system.cpu0.branchPred.BTBLookups 107843095 # Number of BTB lookups 401system.cpu0.branchPred.BTBHits 75495824 # Number of BTB hits 402system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 403system.cpu0.branchPred.BTBHitPct 70.005246 # BTB Hit Percentage 404system.cpu0.branchPred.usedRAS 17327542 # Number of times the RAS was used to get a target. 405system.cpu0.branchPred.RASInCorrect 1162135 # Number of incorrect RAS predictions. 406system.cpu0.branchPred.indirectLookups 3835403 # Number of indirect predictor lookups. 407system.cpu0.branchPred.indirectHits 2658726 # Number of indirect target hits. 408system.cpu0.branchPred.indirectMisses 1176677 # Number of indirect misses. 409system.cpu0.branchPredindirectMispredicted 420775 # Number of mispredicted indirect branches. 410system.cpu_clk_domain.clock 500 # Clock period in ticks 411system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 412system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 413system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 414system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 415system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 416system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 417system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 418system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 419system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 420system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 421system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 422system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 423system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 424system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 425system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 426system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 427system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 428system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 429system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 430system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 431system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 432system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 433system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 434system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 435system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 436system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 437system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 438system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 439system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 440system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 441system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 442system.cpu0.dtb.walker.walks 298304 # Table walker walks requested 443system.cpu0.dtb.walker.walksLong 298304 # Table walker walks initiated with long descriptors 444system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10716 # Level at which table walker walks with long descriptors terminate 445system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 85635 # Level at which table walker walks with long descriptors terminate 446system.cpu0.dtb.walker.walkWaitTime::samples 298304 # Table walker wait (enqueue to first request) latency 447system.cpu0.dtb.walker.walkWaitTime::0 298304 100.00% 100.00% # Table walker wait (enqueue to first request) latency 448system.cpu0.dtb.walker.walkWaitTime::total 298304 # Table walker wait (enqueue to first request) latency 449system.cpu0.dtb.walker.walkCompletionTime::samples 96351 # Table walker service (enqueue to completion) latency 450system.cpu0.dtb.walker.walkCompletionTime::mean 22754.257870 # Table walker service (enqueue to completion) latency 451system.cpu0.dtb.walker.walkCompletionTime::gmean 21300.315388 # Table walker service (enqueue to completion) latency 452system.cpu0.dtb.walker.walkCompletionTime::stdev 14215.969550 # Table walker service (enqueue to completion) latency 453system.cpu0.dtb.walker.walkCompletionTime::0-65535 95122 98.72% 98.72% # Table walker service (enqueue to completion) latency 454system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1073 1.11% 99.84% # Table walker service (enqueue to completion) latency 455system.cpu0.dtb.walker.walkCompletionTime::131072-196607 26 0.03% 99.87% # Table walker service (enqueue to completion) latency 456system.cpu0.dtb.walker.walkCompletionTime::196608-262143 56 0.06% 99.92% # Table walker service (enqueue to completion) latency 457system.cpu0.dtb.walker.walkCompletionTime::262144-327679 56 0.06% 99.98% # Table walker service (enqueue to completion) latency 458system.cpu0.dtb.walker.walkCompletionTime::327680-393215 10 0.01% 99.99% # Table walker service (enqueue to completion) latency 459system.cpu0.dtb.walker.walkCompletionTime::393216-458751 6 0.01% 100.00% # Table walker service (enqueue to completion) latency 460system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 461system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 462system.cpu0.dtb.walker.walkCompletionTime::total 96351 # Table walker service (enqueue to completion) latency 463system.cpu0.dtb.walker.walksPending::samples 734209704 # Table walker pending requests distribution 464system.cpu0.dtb.walker.walksPending::0 734209704 100.00% 100.00% # Table walker pending requests distribution 465system.cpu0.dtb.walker.walksPending::total 734209704 # Table walker pending requests distribution 466system.cpu0.dtb.walker.walkPageSizes::4K 85635 88.88% 88.88% # Table walker page sizes translated 467system.cpu0.dtb.walker.walkPageSizes::2M 10716 11.12% 100.00% # Table walker page sizes translated 468system.cpu0.dtb.walker.walkPageSizes::total 96351 # Table walker page sizes translated 469system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 298304 # Table walker requests started/completed, data/inst 470system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 471system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 298304 # Table walker requests started/completed, data/inst 472system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 96351 # Table walker requests started/completed, data/inst 473system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 474system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 96351 # Table walker requests started/completed, data/inst 475system.cpu0.dtb.walker.walkRequestOrigin::total 394655 # Table walker requests started/completed, data/inst 476system.cpu0.dtb.inst_hits 0 # ITB inst hits 477system.cpu0.dtb.inst_misses 0 # ITB inst misses 478system.cpu0.dtb.read_hits 93899745 # DTB read hits 479system.cpu0.dtb.read_misses 250404 # DTB read misses 480system.cpu0.dtb.write_hits 82108561 # DTB write hits 481system.cpu0.dtb.write_misses 47900 # DTB write misses 482system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 483system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 484system.cpu0.dtb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID 485system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 486system.cpu0.dtb.flush_entries 39092 # Number of entries that have been flushed from TLB 487system.cpu0.dtb.align_faults 2185 # Number of TLB faults due to alignment restrictions 488system.cpu0.dtb.prefetch_faults 10307 # Number of TLB faults due to prefetch 489system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 490system.cpu0.dtb.perms_faults 10956 # Number of TLB faults due to permissions restrictions 491system.cpu0.dtb.read_accesses 94150149 # DTB read accesses 492system.cpu0.dtb.write_accesses 82156461 # DTB write accesses 493system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 494system.cpu0.dtb.hits 176008306 # DTB hits 495system.cpu0.dtb.misses 298304 # DTB misses 496system.cpu0.dtb.accesses 176306610 # DTB accesses 497system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 498system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 499system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 500system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 501system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 502system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 503system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 504system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 505system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 506system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 507system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 508system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 509system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 510system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 511system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 512system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 513system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 514system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 515system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 516system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 517system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 518system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 519system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 520system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 521system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 522system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 523system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 524system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 525system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 526system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 527system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 528system.cpu0.itb.walker.walks 65048 # Table walker walks requested 529system.cpu0.itb.walker.walksLong 65048 # Table walker walks initiated with long descriptors 530system.cpu0.itb.walker.walksLongTerminationLevel::Level2 515 # Level at which table walker walks with long descriptors terminate 531system.cpu0.itb.walker.walksLongTerminationLevel::Level3 52970 # Level at which table walker walks with long descriptors terminate 532system.cpu0.itb.walker.walkWaitTime::samples 65048 # Table walker wait (enqueue to first request) latency 533system.cpu0.itb.walker.walkWaitTime::0 65048 100.00% 100.00% # Table walker wait (enqueue to first request) latency 534system.cpu0.itb.walker.walkWaitTime::total 65048 # Table walker wait (enqueue to first request) latency 535system.cpu0.itb.walker.walkCompletionTime::samples 53485 # Table walker service (enqueue to completion) latency 536system.cpu0.itb.walker.walkCompletionTime::mean 25497.494625 # Table walker service (enqueue to completion) latency 537system.cpu0.itb.walker.walkCompletionTime::gmean 23453.450778 # Table walker service (enqueue to completion) latency 538system.cpu0.itb.walker.walkCompletionTime::stdev 17328.133028 # Table walker service (enqueue to completion) latency 539system.cpu0.itb.walker.walkCompletionTime::0-32767 49469 92.49% 92.49% # Table walker service (enqueue to completion) latency 540system.cpu0.itb.walker.walkCompletionTime::32768-65535 2789 5.21% 97.71% # Table walker service (enqueue to completion) latency 541system.cpu0.itb.walker.walkCompletionTime::65536-98303 9 0.02% 97.72% # Table walker service (enqueue to completion) latency 542system.cpu0.itb.walker.walkCompletionTime::98304-131071 1088 2.03% 99.76% # Table walker service (enqueue to completion) latency 543system.cpu0.itb.walker.walkCompletionTime::131072-163839 21 0.04% 99.80% # Table walker service (enqueue to completion) latency 544system.cpu0.itb.walker.walkCompletionTime::163840-196607 14 0.03% 99.82% # Table walker service (enqueue to completion) latency 545system.cpu0.itb.walker.walkCompletionTime::196608-229375 47 0.09% 99.91% # Table walker service (enqueue to completion) latency 546system.cpu0.itb.walker.walkCompletionTime::229376-262143 18 0.03% 99.94% # Table walker service (enqueue to completion) latency 547system.cpu0.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.96% # Table walker service (enqueue to completion) latency 548system.cpu0.itb.walker.walkCompletionTime::294912-327679 8 0.01% 99.97% # Table walker service (enqueue to completion) latency 549system.cpu0.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.98% # Table walker service (enqueue to completion) latency 550system.cpu0.itb.walker.walkCompletionTime::360448-393215 8 0.01% 99.99% # Table walker service (enqueue to completion) latency 551system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 552system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 553system.cpu0.itb.walker.walkCompletionTime::total 53485 # Table walker service (enqueue to completion) latency 554system.cpu0.itb.walker.walksPending::samples 733487204 # Table walker pending requests distribution 555system.cpu0.itb.walker.walksPending::0 733487204 100.00% 100.00% # Table walker pending requests distribution 556system.cpu0.itb.walker.walksPending::total 733487204 # Table walker pending requests distribution 557system.cpu0.itb.walker.walkPageSizes::4K 52970 99.04% 99.04% # Table walker page sizes translated 558system.cpu0.itb.walker.walkPageSizes::2M 515 0.96% 100.00% # Table walker page sizes translated 559system.cpu0.itb.walker.walkPageSizes::total 53485 # Table walker page sizes translated 560system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 561system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 65048 # Table walker requests started/completed, data/inst 562system.cpu0.itb.walker.walkRequestOrigin_Requested::total 65048 # Table walker requests started/completed, data/inst 563system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 564system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 53485 # Table walker requests started/completed, data/inst 565system.cpu0.itb.walker.walkRequestOrigin_Completed::total 53485 # Table walker requests started/completed, data/inst 566system.cpu0.itb.walker.walkRequestOrigin::total 118533 # Table walker requests started/completed, data/inst 567system.cpu0.itb.inst_hits 259203584 # ITB inst hits 568system.cpu0.itb.inst_misses 65048 # ITB inst misses 569system.cpu0.itb.read_hits 0 # DTB read hits 570system.cpu0.itb.read_misses 0 # DTB read misses 571system.cpu0.itb.write_hits 0 # DTB write hits 572system.cpu0.itb.write_misses 0 # DTB write misses 573system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 574system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 575system.cpu0.itb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID 576system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 577system.cpu0.itb.flush_entries 28269 # Number of entries that have been flushed from TLB 578system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 579system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 580system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 581system.cpu0.itb.perms_faults 171713 # Number of TLB faults due to permissions restrictions 582system.cpu0.itb.read_accesses 0 # DTB read accesses 583system.cpu0.itb.write_accesses 0 # DTB write accesses 584system.cpu0.itb.inst_accesses 259268632 # ITB inst accesses 585system.cpu0.itb.hits 259203584 # DTB hits 586system.cpu0.itb.misses 65048 # DTB misses 587system.cpu0.itb.accesses 259268632 # DTB accesses 588system.cpu0.numPwrStateTransitions 26040 # Number of power state transitions 589system.cpu0.pwrStateClkGateDist::samples 13020 # Distribution of time spent in the clock gated state 590system.cpu0.pwrStateClkGateDist::mean 3597852748.702535 # Distribution of time spent in the clock gated state 591system.cpu0.pwrStateClkGateDist::stdev 96451622625.318069 # Distribution of time spent in the clock gated state 592system.cpu0.pwrStateClkGateDist::underflows 3172 24.36% 24.36% # Distribution of time spent in the clock gated state 593system.cpu0.pwrStateClkGateDist::1000-5e+10 9818 75.41% 99.77% # Distribution of time spent in the clock gated state 594system.cpu0.pwrStateClkGateDist::5e+10-1e+11 12 0.09% 99.86% # Distribution of time spent in the clock gated state 595system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state 596system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 597system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 598system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 599system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state 600system.cpu0.pwrStateClkGateDist::overflows 13 0.10% 100.00% # Distribution of time spent in the clock gated state 601system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 602system.cpu0.pwrStateClkGateDist::max_value 7033291450000 # Distribution of time spent in the clock gated state 603system.cpu0.pwrStateClkGateDist::total 13020 # Distribution of time spent in the clock gated state 604system.cpu0.pwrStateResidencyTicks::ON 511860539893 # Cumulative time (in ticks) in various power states 605system.cpu0.pwrStateResidencyTicks::CLK_GATED 46844042788107 # Cumulative time (in ticks) in various power states 606system.cpu0.numCycles 1023758481 # number of cpu cycles simulated 607system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 608system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 609system.cpu0.committedInsts 483101155 # Number of instructions committed 610system.cpu0.committedOps 567019823 # Number of ops (including micro ops) committed 611system.cpu0.discardedOps 47457065 # Number of ops (including micro ops) which were discarded before commit 612system.cpu0.numFetchSuspends 4178 # Number of times Execute suspended instruction fetching 613system.cpu0.quiesceCycles 93688785177 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 614system.cpu0.cpi 2.119139 # CPI: cycles per instruction 615system.cpu0.ipc 0.471890 # IPC: instructions per cycle 616system.cpu0.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction 617system.cpu0.op_class_0::IntAlu 393333975 69.37% 69.37% # Class of committed instruction 618system.cpu0.op_class_0::IntMult 1298911 0.23% 69.60% # Class of committed instruction 619system.cpu0.op_class_0::IntDiv 62117 0.01% 69.61% # Class of committed instruction 620system.cpu0.op_class_0::FloatAdd 0 0.00% 69.61% # Class of committed instruction 621system.cpu0.op_class_0::FloatCmp 0 0.00% 69.61% # Class of committed instruction 622system.cpu0.op_class_0::FloatCvt 0 0.00% 69.61% # Class of committed instruction 623system.cpu0.op_class_0::FloatMult 0 0.00% 69.61% # Class of committed instruction 624system.cpu0.op_class_0::FloatDiv 0 0.00% 69.61% # Class of committed instruction 625system.cpu0.op_class_0::FloatSqrt 0 0.00% 69.61% # Class of committed instruction 626system.cpu0.op_class_0::SimdAdd 0 0.00% 69.61% # Class of committed instruction 627system.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.61% # Class of committed instruction 628system.cpu0.op_class_0::SimdAlu 0 0.00% 69.61% # Class of committed instruction 629system.cpu0.op_class_0::SimdCmp 0 0.00% 69.61% # Class of committed instruction 630system.cpu0.op_class_0::SimdCvt 0 0.00% 69.61% # Class of committed instruction 631system.cpu0.op_class_0::SimdMisc 0 0.00% 69.61% # Class of committed instruction 632system.cpu0.op_class_0::SimdMult 0 0.00% 69.61% # Class of committed instruction 633system.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.61% # Class of committed instruction 634system.cpu0.op_class_0::SimdShift 0 0.00% 69.61% # Class of committed instruction 635system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.61% # Class of committed instruction 636system.cpu0.op_class_0::SimdSqrt 0 0.00% 69.61% # Class of committed instruction 637system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 69.61% # Class of committed instruction 638system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.61% # Class of committed instruction 639system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 69.61% # Class of committed instruction 640system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 69.61% # Class of committed instruction 641system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.61% # Class of committed instruction 642system.cpu0.op_class_0::SimdFloatMisc 39633 0.01% 69.62% # Class of committed instruction 643system.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.62% # Class of committed instruction 644system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.62% # Class of committed instruction 645system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.62% # Class of committed instruction 646system.cpu0.op_class_0::MemRead 90520623 15.96% 85.58% # Class of committed instruction 647system.cpu0.op_class_0::MemWrite 81764563 14.42% 100.00% # Class of committed instruction 648system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 649system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 650system.cpu0.op_class_0::total 567019823 # Class of committed instruction 651system.cpu0.kern.inst.arm 0 # number of arm instructions executed 652system.cpu0.kern.inst.quiesce 13020 # number of quiesce instructions executed 653system.cpu0.tickCycles 768761843 # Number of cycles that the object actually ticked 654system.cpu0.idleCycles 254996638 # Total number of cycles that the object has spent stopped 655system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 656system.cpu0.dcache.tags.replacements 6026209 # number of replacements 657system.cpu0.dcache.tags.tagsinuse 478.505782 # Cycle average of tags in use 658system.cpu0.dcache.tags.total_refs 166971566 # Total number of references to valid blocks. 659system.cpu0.dcache.tags.sampled_refs 6026721 # Sample count of references to valid blocks. 660system.cpu0.dcache.tags.avg_refs 27.705209 # Average number of references to valid blocks. 661system.cpu0.dcache.tags.warmup_cycle 5039130000 # Cycle when the warmup percentage was hit. 662system.cpu0.dcache.tags.occ_blocks::cpu0.data 478.505782 # Average occupied blocks per requestor 663system.cpu0.dcache.tags.occ_percent::cpu0.data 0.934582 # Average percentage of cache occupancy 664system.cpu0.dcache.tags.occ_percent::total 0.934582 # Average percentage of cache occupancy 665system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 666system.cpu0.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id 667system.cpu0.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id 668system.cpu0.dcache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id 669system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 670system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 671system.cpu0.dcache.tags.tag_accesses 355154483 # Number of tag accesses 672system.cpu0.dcache.tags.data_accesses 355154483 # Number of data accesses 673system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 674system.cpu0.dcache.ReadReq_hits::cpu0.data 85976696 # number of ReadReq hits 675system.cpu0.dcache.ReadReq_hits::total 85976696 # number of ReadReq hits 676system.cpu0.dcache.WriteReq_hits::cpu0.data 76051356 # number of WriteReq hits 677system.cpu0.dcache.WriteReq_hits::total 76051356 # number of WriteReq hits 678system.cpu0.dcache.SoftPFReq_hits::cpu0.data 300861 # number of SoftPFReq hits 679system.cpu0.dcache.SoftPFReq_hits::total 300861 # number of SoftPFReq hits 680system.cpu0.dcache.WriteLineReq_hits::cpu0.data 281214 # number of WriteLineReq hits 681system.cpu0.dcache.WriteLineReq_hits::total 281214 # number of WriteLineReq hits 682system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1915398 # number of LoadLockedReq hits 683system.cpu0.dcache.LoadLockedReq_hits::total 1915398 # number of LoadLockedReq hits 684system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1894723 # number of StoreCondReq hits 685system.cpu0.dcache.StoreCondReq_hits::total 1894723 # number of StoreCondReq hits 686system.cpu0.dcache.demand_hits::cpu0.data 162309266 # number of demand (read+write) hits 687system.cpu0.dcache.demand_hits::total 162309266 # number of demand (read+write) hits 688system.cpu0.dcache.overall_hits::cpu0.data 162610127 # number of overall hits 689system.cpu0.dcache.overall_hits::total 162610127 # number of overall hits 690system.cpu0.dcache.ReadReq_misses::cpu0.data 3729679 # number of ReadReq misses 691system.cpu0.dcache.ReadReq_misses::total 3729679 # number of ReadReq misses 692system.cpu0.dcache.WriteReq_misses::cpu0.data 2481919 # number of WriteReq misses 693system.cpu0.dcache.WriteReq_misses::total 2481919 # number of WriteReq misses 694system.cpu0.dcache.SoftPFReq_misses::cpu0.data 681303 # number of SoftPFReq misses 695system.cpu0.dcache.SoftPFReq_misses::total 681303 # number of SoftPFReq misses 696system.cpu0.dcache.WriteLineReq_misses::cpu0.data 827220 # number of WriteLineReq misses 697system.cpu0.dcache.WriteLineReq_misses::total 827220 # number of WriteLineReq misses 698system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 176003 # number of LoadLockedReq misses 699system.cpu0.dcache.LoadLockedReq_misses::total 176003 # number of LoadLockedReq misses 700system.cpu0.dcache.StoreCondReq_misses::cpu0.data 195484 # number of StoreCondReq misses 701system.cpu0.dcache.StoreCondReq_misses::total 195484 # number of StoreCondReq misses 702system.cpu0.dcache.demand_misses::cpu0.data 7038818 # number of demand (read+write) misses 703system.cpu0.dcache.demand_misses::total 7038818 # number of demand (read+write) misses 704system.cpu0.dcache.overall_misses::cpu0.data 7720121 # number of overall misses 705system.cpu0.dcache.overall_misses::total 7720121 # number of overall misses 706system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 57503024000 # number of ReadReq miss cycles 707system.cpu0.dcache.ReadReq_miss_latency::total 57503024000 # number of ReadReq miss cycles 708system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 50806938500 # number of WriteReq miss cycles 709system.cpu0.dcache.WriteReq_miss_latency::total 50806938500 # number of WriteReq miss cycles 710system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 27591387500 # number of WriteLineReq miss cycles 711system.cpu0.dcache.WriteLineReq_miss_latency::total 27591387500 # number of WriteLineReq miss cycles 712system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2577956500 # number of LoadLockedReq miss cycles 713system.cpu0.dcache.LoadLockedReq_miss_latency::total 2577956500 # number of LoadLockedReq miss cycles 714system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4885048500 # number of StoreCondReq miss cycles 715system.cpu0.dcache.StoreCondReq_miss_latency::total 4885048500 # number of StoreCondReq miss cycles 716system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3405000 # number of StoreCondFailReq miss cycles 717system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3405000 # number of StoreCondFailReq miss cycles 718system.cpu0.dcache.demand_miss_latency::cpu0.data 135901350000 # number of demand (read+write) miss cycles 719system.cpu0.dcache.demand_miss_latency::total 135901350000 # number of demand (read+write) miss cycles 720system.cpu0.dcache.overall_miss_latency::cpu0.data 135901350000 # number of overall miss cycles 721system.cpu0.dcache.overall_miss_latency::total 135901350000 # number of overall miss cycles 722system.cpu0.dcache.ReadReq_accesses::cpu0.data 89706375 # number of ReadReq accesses(hits+misses) 723system.cpu0.dcache.ReadReq_accesses::total 89706375 # number of ReadReq accesses(hits+misses) 724system.cpu0.dcache.WriteReq_accesses::cpu0.data 78533275 # number of WriteReq accesses(hits+misses) 725system.cpu0.dcache.WriteReq_accesses::total 78533275 # number of WriteReq accesses(hits+misses) 726system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 982164 # number of SoftPFReq accesses(hits+misses) 727system.cpu0.dcache.SoftPFReq_accesses::total 982164 # number of SoftPFReq accesses(hits+misses) 728system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1108434 # number of WriteLineReq accesses(hits+misses) 729system.cpu0.dcache.WriteLineReq_accesses::total 1108434 # number of WriteLineReq accesses(hits+misses) 730system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2091401 # number of LoadLockedReq accesses(hits+misses) 731system.cpu0.dcache.LoadLockedReq_accesses::total 2091401 # number of LoadLockedReq accesses(hits+misses) 732system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2090207 # number of StoreCondReq accesses(hits+misses) 733system.cpu0.dcache.StoreCondReq_accesses::total 2090207 # number of StoreCondReq accesses(hits+misses) 734system.cpu0.dcache.demand_accesses::cpu0.data 169348084 # number of demand (read+write) accesses 735system.cpu0.dcache.demand_accesses::total 169348084 # number of demand (read+write) accesses 736system.cpu0.dcache.overall_accesses::cpu0.data 170330248 # number of overall (read+write) accesses 737system.cpu0.dcache.overall_accesses::total 170330248 # number of overall (read+write) accesses 738system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041577 # miss rate for ReadReq accesses 739system.cpu0.dcache.ReadReq_miss_rate::total 0.041577 # miss rate for ReadReq accesses 740system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031603 # miss rate for WriteReq accesses 741system.cpu0.dcache.WriteReq_miss_rate::total 0.031603 # miss rate for WriteReq accesses 742system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.693675 # miss rate for SoftPFReq accesses 743system.cpu0.dcache.SoftPFReq_miss_rate::total 0.693675 # miss rate for SoftPFReq accesses 744system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.746296 # miss rate for WriteLineReq accesses 745system.cpu0.dcache.WriteLineReq_miss_rate::total 0.746296 # miss rate for WriteLineReq accesses 746system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.084156 # miss rate for LoadLockedReq accesses 747system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.084156 # miss rate for LoadLockedReq accesses 748system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.093524 # miss rate for StoreCondReq accesses 749system.cpu0.dcache.StoreCondReq_miss_rate::total 0.093524 # miss rate for StoreCondReq accesses 750system.cpu0.dcache.demand_miss_rate::cpu0.data 0.041564 # miss rate for demand accesses 751system.cpu0.dcache.demand_miss_rate::total 0.041564 # miss rate for demand accesses 752system.cpu0.dcache.overall_miss_rate::cpu0.data 0.045324 # miss rate for overall accesses 753system.cpu0.dcache.overall_miss_rate::total 0.045324 # miss rate for overall accesses 754system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15417.687152 # average ReadReq miss latency 755system.cpu0.dcache.ReadReq_avg_miss_latency::total 15417.687152 # average ReadReq miss latency 756system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20470.828621 # average WriteReq miss latency 757system.cpu0.dcache.WriteReq_avg_miss_latency::total 20470.828621 # average WriteReq miss latency 758system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 33354.352530 # average WriteLineReq miss latency 759system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 33354.352530 # average WriteLineReq miss latency 760system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14647.230445 # average LoadLockedReq miss latency 761system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14647.230445 # average LoadLockedReq miss latency 762system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24989.505535 # average StoreCondReq miss latency 763system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24989.505535 # average StoreCondReq miss latency 764system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 765system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 766system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19307.410704 # average overall miss latency 767system.cpu0.dcache.demand_avg_miss_latency::total 19307.410704 # average overall miss latency 768system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17603.525903 # average overall miss latency 769system.cpu0.dcache.overall_avg_miss_latency::total 17603.525903 # average overall miss latency 770system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 771system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 772system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 773system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 774system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 775system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 776system.cpu0.dcache.writebacks::writebacks 6026220 # number of writebacks 777system.cpu0.dcache.writebacks::total 6026220 # number of writebacks 778system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 447326 # number of ReadReq MSHR hits 779system.cpu0.dcache.ReadReq_mshr_hits::total 447326 # number of ReadReq MSHR hits 780system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1020420 # number of WriteReq MSHR hits 781system.cpu0.dcache.WriteReq_mshr_hits::total 1020420 # number of WriteReq MSHR hits 782system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 73 # number of WriteLineReq MSHR hits 783system.cpu0.dcache.WriteLineReq_mshr_hits::total 73 # number of WriteLineReq MSHR hits 784system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44988 # number of LoadLockedReq MSHR hits 785system.cpu0.dcache.LoadLockedReq_mshr_hits::total 44988 # number of LoadLockedReq MSHR hits 786system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 67 # number of StoreCondReq MSHR hits 787system.cpu0.dcache.StoreCondReq_mshr_hits::total 67 # number of StoreCondReq MSHR hits 788system.cpu0.dcache.demand_mshr_hits::cpu0.data 1467819 # number of demand (read+write) MSHR hits 789system.cpu0.dcache.demand_mshr_hits::total 1467819 # number of demand (read+write) MSHR hits 790system.cpu0.dcache.overall_mshr_hits::cpu0.data 1467819 # number of overall MSHR hits 791system.cpu0.dcache.overall_mshr_hits::total 1467819 # number of overall MSHR hits 792system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3282353 # number of ReadReq MSHR misses 793system.cpu0.dcache.ReadReq_mshr_misses::total 3282353 # number of ReadReq MSHR misses 794system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1461499 # number of WriteReq MSHR misses 795system.cpu0.dcache.WriteReq_mshr_misses::total 1461499 # number of WriteReq MSHR misses 796system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 679841 # number of SoftPFReq MSHR misses 797system.cpu0.dcache.SoftPFReq_mshr_misses::total 679841 # number of SoftPFReq MSHR misses 798system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 827147 # number of WriteLineReq MSHR misses 799system.cpu0.dcache.WriteLineReq_mshr_misses::total 827147 # number of WriteLineReq MSHR misses 800system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 131015 # number of LoadLockedReq MSHR misses 801system.cpu0.dcache.LoadLockedReq_mshr_misses::total 131015 # number of LoadLockedReq MSHR misses 802system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 195417 # number of StoreCondReq MSHR misses 803system.cpu0.dcache.StoreCondReq_mshr_misses::total 195417 # number of StoreCondReq MSHR misses 804system.cpu0.dcache.demand_mshr_misses::cpu0.data 5570999 # number of demand (read+write) MSHR misses 805system.cpu0.dcache.demand_mshr_misses::total 5570999 # number of demand (read+write) MSHR misses 806system.cpu0.dcache.overall_mshr_misses::cpu0.data 6250840 # number of overall MSHR misses 807system.cpu0.dcache.overall_mshr_misses::total 6250840 # number of overall MSHR misses 808system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31702 # number of ReadReq MSHR uncacheable 809system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31702 # number of ReadReq MSHR uncacheable 810system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31225 # number of WriteReq MSHR uncacheable 811system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31225 # number of WriteReq MSHR uncacheable 812system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 62927 # number of overall MSHR uncacheable misses 813system.cpu0.dcache.overall_mshr_uncacheable_misses::total 62927 # number of overall MSHR uncacheable misses 814system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 45702695000 # number of ReadReq MSHR miss cycles 815system.cpu0.dcache.ReadReq_mshr_miss_latency::total 45702695000 # number of ReadReq MSHR miss cycles 816system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 29281044500 # number of WriteReq MSHR miss cycles 817system.cpu0.dcache.WriteReq_mshr_miss_latency::total 29281044500 # number of WriteReq MSHR miss cycles 818system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14665959000 # number of SoftPFReq MSHR miss cycles 819system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14665959000 # number of SoftPFReq MSHR miss cycles 820system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 26759895500 # number of WriteLineReq MSHR miss cycles 821system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 26759895500 # number of WriteLineReq MSHR miss cycles 822system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1703041500 # number of LoadLockedReq MSHR miss cycles 823system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1703041500 # number of LoadLockedReq MSHR miss cycles 824system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4687173500 # number of StoreCondReq MSHR miss cycles 825system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4687173500 # number of StoreCondReq MSHR miss cycles 826system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3267500 # number of StoreCondFailReq MSHR miss cycles 827system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3267500 # number of StoreCondFailReq MSHR miss cycles 828system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 101743635000 # number of demand (read+write) MSHR miss cycles 829system.cpu0.dcache.demand_mshr_miss_latency::total 101743635000 # number of demand (read+write) MSHR miss cycles 830system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 116409594000 # number of overall MSHR miss cycles 831system.cpu0.dcache.overall_mshr_miss_latency::total 116409594000 # number of overall MSHR miss cycles 832system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6136923000 # number of ReadReq MSHR uncacheable cycles 833system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6136923000 # number of ReadReq MSHR uncacheable cycles 834system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6136923000 # number of overall MSHR uncacheable cycles 835system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6136923000 # number of overall MSHR uncacheable cycles 836system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036590 # mshr miss rate for ReadReq accesses 837system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036590 # mshr miss rate for ReadReq accesses 838system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018610 # mshr miss rate for WriteReq accesses 839system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018610 # mshr miss rate for WriteReq accesses 840system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.692187 # mshr miss rate for SoftPFReq accesses 841system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.692187 # mshr miss rate for SoftPFReq accesses 842system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.746230 # mshr miss rate for WriteLineReq accesses 843system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.746230 # mshr miss rate for WriteLineReq accesses 844system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062645 # mshr miss rate for LoadLockedReq accesses 845system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062645 # mshr miss rate for LoadLockedReq accesses 846system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.093492 # mshr miss rate for StoreCondReq accesses 847system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.093492 # mshr miss rate for StoreCondReq accesses 848system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032897 # mshr miss rate for demand accesses 849system.cpu0.dcache.demand_mshr_miss_rate::total 0.032897 # mshr miss rate for demand accesses 850system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036698 # mshr miss rate for overall accesses 851system.cpu0.dcache.overall_mshr_miss_rate::total 0.036698 # mshr miss rate for overall accesses 852system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13923.759876 # average ReadReq mshr miss latency 853system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13923.759876 # average ReadReq mshr miss latency 854system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20034.939812 # average WriteReq mshr miss latency 855system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20034.939812 # average WriteReq mshr miss latency 856system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21572.630953 # average SoftPFReq mshr miss latency 857system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21572.630953 # average SoftPFReq mshr miss latency 858system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 32352.043228 # average WriteLineReq mshr miss latency 859system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 32352.043228 # average WriteLineReq mshr miss latency 860system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12998.828378 # average LoadLockedReq mshr miss latency 861system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12998.828378 # average LoadLockedReq mshr miss latency 862system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23985.495121 # average StoreCondReq mshr miss latency 863system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23985.495121 # average StoreCondReq mshr miss latency 864system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 865system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 866system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18263.086208 # average overall mshr miss latency 867system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18263.086208 # average overall mshr miss latency 868system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18623.032104 # average overall mshr miss latency 869system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18623.032104 # average overall mshr miss latency 870system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193581.572141 # average ReadReq mshr uncacheable latency 871system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193581.572141 # average ReadReq mshr uncacheable latency 872system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97524.480748 # average overall mshr uncacheable latency 873system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 97524.480748 # average overall mshr uncacheable latency 874system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 875system.cpu0.icache.tags.replacements 9817579 # number of replacements 876system.cpu0.icache.tags.tagsinuse 511.932451 # Cycle average of tags in use 877system.cpu0.icache.tags.total_refs 249208397 # Total number of references to valid blocks. 878system.cpu0.icache.tags.sampled_refs 9818091 # Sample count of references to valid blocks. 879system.cpu0.icache.tags.avg_refs 25.382572 # Average number of references to valid blocks. 880system.cpu0.icache.tags.warmup_cycle 22021065000 # Cycle when the warmup percentage was hit. 881system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.932451 # Average occupied blocks per requestor 882system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999868 # Average percentage of cache occupancy 883system.cpu0.icache.tags.occ_percent::total 0.999868 # Average percentage of cache occupancy 884system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 885system.cpu0.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id 886system.cpu0.icache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id 887system.cpu0.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id 888system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 889system.cpu0.icache.tags.tag_accesses 527871096 # Number of tag accesses 890system.cpu0.icache.tags.data_accesses 527871096 # Number of data accesses 891system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 892system.cpu0.icache.ReadReq_hits::cpu0.inst 249208397 # number of ReadReq hits 893system.cpu0.icache.ReadReq_hits::total 249208397 # number of ReadReq hits 894system.cpu0.icache.demand_hits::cpu0.inst 249208397 # number of demand (read+write) hits 895system.cpu0.icache.demand_hits::total 249208397 # number of demand (read+write) hits 896system.cpu0.icache.overall_hits::cpu0.inst 249208397 # number of overall hits 897system.cpu0.icache.overall_hits::total 249208397 # number of overall hits 898system.cpu0.icache.ReadReq_misses::cpu0.inst 9818101 # number of ReadReq misses 899system.cpu0.icache.ReadReq_misses::total 9818101 # number of ReadReq misses 900system.cpu0.icache.demand_misses::cpu0.inst 9818101 # number of demand (read+write) misses 901system.cpu0.icache.demand_misses::total 9818101 # number of demand (read+write) misses 902system.cpu0.icache.overall_misses::cpu0.inst 9818101 # number of overall misses 903system.cpu0.icache.overall_misses::total 9818101 # number of overall misses 904system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 99002118000 # number of ReadReq miss cycles 905system.cpu0.icache.ReadReq_miss_latency::total 99002118000 # number of ReadReq miss cycles 906system.cpu0.icache.demand_miss_latency::cpu0.inst 99002118000 # number of demand (read+write) miss cycles 907system.cpu0.icache.demand_miss_latency::total 99002118000 # number of demand (read+write) miss cycles 908system.cpu0.icache.overall_miss_latency::cpu0.inst 99002118000 # number of overall miss cycles 909system.cpu0.icache.overall_miss_latency::total 99002118000 # number of overall miss cycles 910system.cpu0.icache.ReadReq_accesses::cpu0.inst 259026498 # number of ReadReq accesses(hits+misses) 911system.cpu0.icache.ReadReq_accesses::total 259026498 # number of ReadReq accesses(hits+misses) 912system.cpu0.icache.demand_accesses::cpu0.inst 259026498 # number of demand (read+write) accesses 913system.cpu0.icache.demand_accesses::total 259026498 # number of demand (read+write) accesses 914system.cpu0.icache.overall_accesses::cpu0.inst 259026498 # number of overall (read+write) accesses 915system.cpu0.icache.overall_accesses::total 259026498 # number of overall (read+write) accesses 916system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.037904 # miss rate for ReadReq accesses 917system.cpu0.icache.ReadReq_miss_rate::total 0.037904 # miss rate for ReadReq accesses 918system.cpu0.icache.demand_miss_rate::cpu0.inst 0.037904 # miss rate for demand accesses 919system.cpu0.icache.demand_miss_rate::total 0.037904 # miss rate for demand accesses 920system.cpu0.icache.overall_miss_rate::cpu0.inst 0.037904 # miss rate for overall accesses 921system.cpu0.icache.overall_miss_rate::total 0.037904 # miss rate for overall accesses 922system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10083.632059 # average ReadReq miss latency 923system.cpu0.icache.ReadReq_avg_miss_latency::total 10083.632059 # average ReadReq miss latency 924system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10083.632059 # average overall miss latency 925system.cpu0.icache.demand_avg_miss_latency::total 10083.632059 # average overall miss latency 926system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10083.632059 # average overall miss latency 927system.cpu0.icache.overall_avg_miss_latency::total 10083.632059 # average overall miss latency 928system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 929system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 930system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 931system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 932system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 933system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 934system.cpu0.icache.writebacks::writebacks 9817579 # number of writebacks 935system.cpu0.icache.writebacks::total 9817579 # number of writebacks 936system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9818101 # number of ReadReq MSHR misses 937system.cpu0.icache.ReadReq_mshr_misses::total 9818101 # number of ReadReq MSHR misses 938system.cpu0.icache.demand_mshr_misses::cpu0.inst 9818101 # number of demand (read+write) MSHR misses 939system.cpu0.icache.demand_mshr_misses::total 9818101 # number of demand (read+write) MSHR misses 940system.cpu0.icache.overall_mshr_misses::cpu0.inst 9818101 # number of overall MSHR misses 941system.cpu0.icache.overall_mshr_misses::total 9818101 # number of overall MSHR misses 942system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52299 # number of ReadReq MSHR uncacheable 943system.cpu0.icache.ReadReq_mshr_uncacheable::total 52299 # number of ReadReq MSHR uncacheable 944system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52299 # number of overall MSHR uncacheable misses 945system.cpu0.icache.overall_mshr_uncacheable_misses::total 52299 # number of overall MSHR uncacheable misses 946system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 94093068000 # number of ReadReq MSHR miss cycles 947system.cpu0.icache.ReadReq_mshr_miss_latency::total 94093068000 # number of ReadReq MSHR miss cycles 948system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 94093068000 # number of demand (read+write) MSHR miss cycles 949system.cpu0.icache.demand_mshr_miss_latency::total 94093068000 # number of demand (read+write) MSHR miss cycles 950system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 94093068000 # number of overall MSHR miss cycles 951system.cpu0.icache.overall_mshr_miss_latency::total 94093068000 # number of overall MSHR miss cycles 952system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4837195500 # number of ReadReq MSHR uncacheable cycles 953system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4837195500 # number of ReadReq MSHR uncacheable cycles 954system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4837195500 # number of overall MSHR uncacheable cycles 955system.cpu0.icache.overall_mshr_uncacheable_latency::total 4837195500 # number of overall MSHR uncacheable cycles 956system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.037904 # mshr miss rate for ReadReq accesses 957system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.037904 # mshr miss rate for ReadReq accesses 958system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.037904 # mshr miss rate for demand accesses 959system.cpu0.icache.demand_mshr_miss_rate::total 0.037904 # mshr miss rate for demand accesses 960system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.037904 # mshr miss rate for overall accesses 961system.cpu0.icache.overall_mshr_miss_rate::total 0.037904 # mshr miss rate for overall accesses 962system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9583.632110 # average ReadReq mshr miss latency 963system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9583.632110 # average ReadReq mshr miss latency 964system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9583.632110 # average overall mshr miss latency 965system.cpu0.icache.demand_avg_mshr_miss_latency::total 9583.632110 # average overall mshr miss latency 966system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9583.632110 # average overall mshr miss latency 967system.cpu0.icache.overall_avg_mshr_miss_latency::total 9583.632110 # average overall mshr miss latency 968system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92491.166179 # average ReadReq mshr uncacheable latency 969system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92491.166179 # average ReadReq mshr uncacheable latency 970system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92491.166179 # average overall mshr uncacheable latency 971system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92491.166179 # average overall mshr uncacheable latency 972system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 973system.cpu0.l2cache.prefetcher.num_hwpf_issued 8242304 # number of hwpf issued 974system.cpu0.l2cache.prefetcher.pfIdentified 8243665 # number of prefetch candidates identified 975system.cpu0.l2cache.prefetcher.pfBufferHit 1198 # number of redundant prefetches already in prefetch queue 976system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 977system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 978system.cpu0.l2cache.prefetcher.pfSpanPage 1073071 # number of prefetches not generated due to page crossing 979system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 980system.cpu0.l2cache.tags.replacements 2829183 # number of replacements 981system.cpu0.l2cache.tags.tagsinuse 16163.343057 # Cycle average of tags in use 982system.cpu0.l2cache.tags.total_refs 24764914 # Total number of references to valid blocks. 983system.cpu0.l2cache.tags.sampled_refs 2845343 # Sample count of references to valid blocks. 984system.cpu0.l2cache.tags.avg_refs 8.703666 # Average number of references to valid blocks. 985system.cpu0.l2cache.tags.warmup_cycle 5659477500 # Cycle when the warmup percentage was hit. 986system.cpu0.l2cache.tags.occ_blocks::writebacks 15257.249232 # Average occupied blocks per requestor 987system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 57.561913 # Average occupied blocks per requestor 988system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 60.708141 # Average occupied blocks per requestor 989system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 787.823770 # Average occupied blocks per requestor 990system.cpu0.l2cache.tags.occ_percent::writebacks 0.931229 # Average percentage of cache occupancy 991system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003513 # Average percentage of cache occupancy 992system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003705 # Average percentage of cache occupancy 993system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.048085 # Average percentage of cache occupancy 994system.cpu0.l2cache.tags.occ_percent::total 0.986532 # Average percentage of cache occupancy 995system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1356 # Occupied blocks per task id 996system.cpu0.l2cache.tags.occ_task_id_blocks::1023 56 # Occupied blocks per task id 997system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14748 # Occupied blocks per task id 998system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 16 # Occupied blocks per task id 999system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 123 # Occupied blocks per task id 1000system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 574 # Occupied blocks per task id 1001system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 643 # Occupied blocks per task id 1002system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 23 # Occupied blocks per task id 1003system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 22 # Occupied blocks per task id 1004system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id 1005system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id 1006system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1176 # Occupied blocks per task id 1007system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2616 # Occupied blocks per task id 1008system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5298 # Occupied blocks per task id 1009system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 5548 # Occupied blocks per task id 1010system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.082764 # Percentage of cache occupancy per task id 1011system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003418 # Percentage of cache occupancy per task id 1012system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.900146 # Percentage of cache occupancy per task id 1013system.cpu0.l2cache.tags.tag_accesses 533961635 # Number of tag accesses 1014system.cpu0.l2cache.tags.data_accesses 533961635 # Number of data accesses 1015system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 1016system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 561309 # number of ReadReq hits 1017system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 167224 # number of ReadReq hits 1018system.cpu0.l2cache.ReadReq_hits::total 728533 # number of ReadReq hits 1019system.cpu0.l2cache.WritebackDirty_hits::writebacks 3942058 # number of WritebackDirty hits 1020system.cpu0.l2cache.WritebackDirty_hits::total 3942058 # number of WritebackDirty hits 1021system.cpu0.l2cache.WritebackClean_hits::writebacks 11898812 # number of WritebackClean hits 1022system.cpu0.l2cache.WritebackClean_hits::total 11898812 # number of WritebackClean hits 1023system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 611 # number of UpgradeReq hits 1024system.cpu0.l2cache.UpgradeReq_hits::total 611 # number of UpgradeReq hits 1025system.cpu0.l2cache.ReadExReq_hits::cpu0.data 933174 # number of ReadExReq hits 1026system.cpu0.l2cache.ReadExReq_hits::total 933174 # number of ReadExReq hits 1027system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 9093916 # number of ReadCleanReq hits 1028system.cpu0.l2cache.ReadCleanReq_hits::total 9093916 # number of ReadCleanReq hits 1029system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3073539 # number of ReadSharedReq hits 1030system.cpu0.l2cache.ReadSharedReq_hits::total 3073539 # number of ReadSharedReq hits 1031system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 216814 # number of InvalidateReq hits 1032system.cpu0.l2cache.InvalidateReq_hits::total 216814 # number of InvalidateReq hits 1033system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 561309 # number of demand (read+write) hits 1034system.cpu0.l2cache.demand_hits::cpu0.itb.walker 167224 # number of demand (read+write) hits 1035system.cpu0.l2cache.demand_hits::cpu0.inst 9093916 # number of demand (read+write) hits 1036system.cpu0.l2cache.demand_hits::cpu0.data 4006713 # number of demand (read+write) hits 1037system.cpu0.l2cache.demand_hits::total 13829162 # number of demand (read+write) hits 1038system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 561309 # number of overall hits 1039system.cpu0.l2cache.overall_hits::cpu0.itb.walker 167224 # number of overall hits 1040system.cpu0.l2cache.overall_hits::cpu0.inst 9093916 # number of overall hits 1041system.cpu0.l2cache.overall_hits::cpu0.data 4006713 # number of overall hits 1042system.cpu0.l2cache.overall_hits::total 13829162 # number of overall hits 1043system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12299 # number of ReadReq misses 1044system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8468 # number of ReadReq misses 1045system.cpu0.l2cache.ReadReq_misses::total 20767 # number of ReadReq misses 1046system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 256901 # number of UpgradeReq misses 1047system.cpu0.l2cache.UpgradeReq_misses::total 256901 # number of UpgradeReq misses 1048system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 195411 # number of SCUpgradeReq misses 1049system.cpu0.l2cache.SCUpgradeReq_misses::total 195411 # number of SCUpgradeReq misses 1050system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 6 # number of SCUpgradeFailReq misses 1051system.cpu0.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses 1052system.cpu0.l2cache.ReadExReq_misses::cpu0.data 279617 # number of ReadExReq misses 1053system.cpu0.l2cache.ReadExReq_misses::total 279617 # number of ReadExReq misses 1054system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 724184 # number of ReadCleanReq misses 1055system.cpu0.l2cache.ReadCleanReq_misses::total 724184 # number of ReadCleanReq misses 1056system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1019232 # number of ReadSharedReq misses 1057system.cpu0.l2cache.ReadSharedReq_misses::total 1019232 # number of ReadSharedReq misses 1058system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 608335 # number of InvalidateReq misses 1059system.cpu0.l2cache.InvalidateReq_misses::total 608335 # number of InvalidateReq misses 1060system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12299 # number of demand (read+write) misses 1061system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8468 # number of demand (read+write) misses 1062system.cpu0.l2cache.demand_misses::cpu0.inst 724184 # number of demand (read+write) misses 1063system.cpu0.l2cache.demand_misses::cpu0.data 1298849 # number of demand (read+write) misses 1064system.cpu0.l2cache.demand_misses::total 2043800 # number of demand (read+write) misses 1065system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12299 # number of overall misses 1066system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8468 # number of overall misses 1067system.cpu0.l2cache.overall_misses::cpu0.inst 724184 # number of overall misses 1068system.cpu0.l2cache.overall_misses::cpu0.data 1298849 # number of overall misses 1069system.cpu0.l2cache.overall_misses::total 2043800 # number of overall misses 1070system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 444586500 # number of ReadReq miss cycles 1071system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 341709500 # number of ReadReq miss cycles 1072system.cpu0.l2cache.ReadReq_miss_latency::total 786296000 # number of ReadReq miss cycles 1073system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2032659000 # number of UpgradeReq miss cycles 1074system.cpu0.l2cache.UpgradeReq_miss_latency::total 2032659000 # number of UpgradeReq miss cycles 1075system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1558169000 # number of SCUpgradeReq miss cycles 1076system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1558169000 # number of SCUpgradeReq miss cycles 1077system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 3166000 # number of SCUpgradeFailReq miss cycles 1078system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 3166000 # number of SCUpgradeFailReq miss cycles 1079system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 14018472997 # number of ReadExReq miss cycles 1080system.cpu0.l2cache.ReadExReq_miss_latency::total 14018472997 # number of ReadExReq miss cycles 1081system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 24426242000 # number of ReadCleanReq miss cycles 1082system.cpu0.l2cache.ReadCleanReq_miss_latency::total 24426242000 # number of ReadCleanReq miss cycles 1083system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 35646536993 # number of ReadSharedReq miss cycles 1084system.cpu0.l2cache.ReadSharedReq_miss_latency::total 35646536993 # number of ReadSharedReq miss cycles 1085system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 333062000 # number of InvalidateReq miss cycles 1086system.cpu0.l2cache.InvalidateReq_miss_latency::total 333062000 # number of InvalidateReq miss cycles 1087system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 444586500 # number of demand (read+write) miss cycles 1088system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 341709500 # number of demand (read+write) miss cycles 1089system.cpu0.l2cache.demand_miss_latency::cpu0.inst 24426242000 # number of demand (read+write) miss cycles 1090system.cpu0.l2cache.demand_miss_latency::cpu0.data 49665009990 # number of demand (read+write) miss cycles 1091system.cpu0.l2cache.demand_miss_latency::total 74877547990 # number of demand (read+write) miss cycles 1092system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 444586500 # number of overall miss cycles 1093system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 341709500 # number of overall miss cycles 1094system.cpu0.l2cache.overall_miss_latency::cpu0.inst 24426242000 # number of overall miss cycles 1095system.cpu0.l2cache.overall_miss_latency::cpu0.data 49665009990 # number of overall miss cycles 1096system.cpu0.l2cache.overall_miss_latency::total 74877547990 # number of overall miss cycles 1097system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 573608 # number of ReadReq accesses(hits+misses) 1098system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 175692 # number of ReadReq accesses(hits+misses) 1099system.cpu0.l2cache.ReadReq_accesses::total 749300 # number of ReadReq accesses(hits+misses) 1100system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3942058 # number of WritebackDirty accesses(hits+misses) 1101system.cpu0.l2cache.WritebackDirty_accesses::total 3942058 # number of WritebackDirty accesses(hits+misses) 1102system.cpu0.l2cache.WritebackClean_accesses::writebacks 11898812 # number of WritebackClean accesses(hits+misses) 1103system.cpu0.l2cache.WritebackClean_accesses::total 11898812 # number of WritebackClean accesses(hits+misses) 1104system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 257512 # number of UpgradeReq accesses(hits+misses) 1105system.cpu0.l2cache.UpgradeReq_accesses::total 257512 # number of UpgradeReq accesses(hits+misses) 1106system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 195411 # number of SCUpgradeReq accesses(hits+misses) 1107system.cpu0.l2cache.SCUpgradeReq_accesses::total 195411 # number of SCUpgradeReq accesses(hits+misses) 1108system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 6 # number of SCUpgradeFailReq accesses(hits+misses) 1109system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) 1110system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1212791 # number of ReadExReq accesses(hits+misses) 1111system.cpu0.l2cache.ReadExReq_accesses::total 1212791 # number of ReadExReq accesses(hits+misses) 1112system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9818100 # number of ReadCleanReq accesses(hits+misses) 1113system.cpu0.l2cache.ReadCleanReq_accesses::total 9818100 # number of ReadCleanReq accesses(hits+misses) 1114system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4092771 # number of ReadSharedReq accesses(hits+misses) 1115system.cpu0.l2cache.ReadSharedReq_accesses::total 4092771 # number of ReadSharedReq accesses(hits+misses) 1116system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 825149 # number of InvalidateReq accesses(hits+misses) 1117system.cpu0.l2cache.InvalidateReq_accesses::total 825149 # number of InvalidateReq accesses(hits+misses) 1118system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 573608 # number of demand (read+write) accesses 1119system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 175692 # number of demand (read+write) accesses 1120system.cpu0.l2cache.demand_accesses::cpu0.inst 9818100 # number of demand (read+write) accesses 1121system.cpu0.l2cache.demand_accesses::cpu0.data 5305562 # number of demand (read+write) accesses 1122system.cpu0.l2cache.demand_accesses::total 15872962 # number of demand (read+write) accesses 1123system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 573608 # number of overall (read+write) accesses 1124system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 175692 # number of overall (read+write) accesses 1125system.cpu0.l2cache.overall_accesses::cpu0.inst 9818100 # number of overall (read+write) accesses 1126system.cpu0.l2cache.overall_accesses::cpu0.data 5305562 # number of overall (read+write) accesses 1127system.cpu0.l2cache.overall_accesses::total 15872962 # number of overall (read+write) accesses 1128system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.021441 # miss rate for ReadReq accesses 1129system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.048198 # miss rate for ReadReq accesses 1130system.cpu0.l2cache.ReadReq_miss_rate::total 0.027715 # miss rate for ReadReq accesses 1131system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.997627 # miss rate for UpgradeReq accesses 1132system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.997627 # miss rate for UpgradeReq accesses 1133system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1134system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1135system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1136system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1137system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.230557 # miss rate for ReadExReq accesses 1138system.cpu0.l2cache.ReadExReq_miss_rate::total 0.230557 # miss rate for ReadExReq accesses 1139system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.073760 # miss rate for ReadCleanReq accesses 1140system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.073760 # miss rate for ReadCleanReq accesses 1141system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.249032 # miss rate for ReadSharedReq accesses 1142system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.249032 # miss rate for ReadSharedReq accesses 1143system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.737243 # miss rate for InvalidateReq accesses 1144system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.737243 # miss rate for InvalidateReq accesses 1145system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.021441 # miss rate for demand accesses 1146system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.048198 # miss rate for demand accesses 1147system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.073760 # miss rate for demand accesses 1148system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.244809 # miss rate for demand accesses 1149system.cpu0.l2cache.demand_miss_rate::total 0.128760 # miss rate for demand accesses 1150system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.021441 # miss rate for overall accesses 1151system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.048198 # miss rate for overall accesses 1152system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.073760 # miss rate for overall accesses 1153system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.244809 # miss rate for overall accesses 1154system.cpu0.l2cache.overall_miss_rate::total 0.128760 # miss rate for overall accesses 1155system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 36148.182779 # average ReadReq miss latency 1156system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 40353.034955 # average ReadReq miss latency 1157system.cpu0.l2cache.ReadReq_avg_miss_latency::total 37862.763038 # average ReadReq miss latency 1158system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 7912.226889 # average UpgradeReq miss latency 1159system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 7912.226889 # average UpgradeReq miss latency 1160system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 7973.803931 # average SCUpgradeReq miss latency 1161system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 7973.803931 # average SCUpgradeReq miss latency 1162system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 527666.666667 # average SCUpgradeFailReq miss latency 1163system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 527666.666667 # average SCUpgradeFailReq miss latency 1164system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50134.551894 # average ReadExReq miss latency 1165system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50134.551894 # average ReadExReq miss latency 1166system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 33729.331220 # average ReadCleanReq miss latency 1167system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 33729.331220 # average ReadCleanReq miss latency 1168system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34973.918591 # average ReadSharedReq miss latency 1169system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34973.918591 # average ReadSharedReq miss latency 1170system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 547.497678 # average InvalidateReq miss latency 1171system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 547.497678 # average InvalidateReq miss latency 1172system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 36148.182779 # average overall miss latency 1173system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 40353.034955 # average overall miss latency 1174system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 33729.331220 # average overall miss latency 1175system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38237.708918 # average overall miss latency 1176system.cpu0.l2cache.demand_avg_miss_latency::total 36636.436046 # average overall miss latency 1177system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 36148.182779 # average overall miss latency 1178system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 40353.034955 # average overall miss latency 1179system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 33729.331220 # average overall miss latency 1180system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38237.708918 # average overall miss latency 1181system.cpu0.l2cache.overall_avg_miss_latency::total 36636.436046 # average overall miss latency 1182system.cpu0.l2cache.blocked_cycles::no_mshrs 90 # number of cycles access was blocked 1183system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1184system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked 1185system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1186system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 90 # average number of cycles each access was blocked 1187system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1188system.cpu0.l2cache.unused_prefetches 48128 # number of HardPF blocks evicted w/o reference 1189system.cpu0.l2cache.writebacks::writebacks 1646117 # number of writebacks 1190system.cpu0.l2cache.writebacks::total 1646117 # number of writebacks 1191system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 3 # number of ReadReq MSHR hits 1192system.cpu0.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits 1193system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 9808 # number of ReadExReq MSHR hits 1194system.cpu0.l2cache.ReadExReq_mshr_hits::total 9808 # number of ReadExReq MSHR hits 1195system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 9 # number of ReadCleanReq MSHR hits 1196system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits 1197system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 898 # number of ReadSharedReq MSHR hits 1198system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 898 # number of ReadSharedReq MSHR hits 1199system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 3 # number of InvalidateReq MSHR hits 1200system.cpu0.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits 1201system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 3 # number of demand (read+write) MSHR hits 1202system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 9 # number of demand (read+write) MSHR hits 1203system.cpu0.l2cache.demand_mshr_hits::cpu0.data 10706 # number of demand (read+write) MSHR hits 1204system.cpu0.l2cache.demand_mshr_hits::total 10718 # number of demand (read+write) MSHR hits 1205system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 3 # number of overall MSHR hits 1206system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 9 # number of overall MSHR hits 1207system.cpu0.l2cache.overall_mshr_hits::cpu0.data 10706 # number of overall MSHR hits 1208system.cpu0.l2cache.overall_mshr_hits::total 10718 # number of overall MSHR hits 1209system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 12299 # number of ReadReq MSHR misses 1210system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8465 # number of ReadReq MSHR misses 1211system.cpu0.l2cache.ReadReq_mshr_misses::total 20764 # number of ReadReq MSHR misses 1212system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 828377 # number of HardPFReq MSHR misses 1213system.cpu0.l2cache.HardPFReq_mshr_misses::total 828377 # number of HardPFReq MSHR misses 1214system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 256901 # number of UpgradeReq MSHR misses 1215system.cpu0.l2cache.UpgradeReq_mshr_misses::total 256901 # number of UpgradeReq MSHR misses 1216system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 195411 # number of SCUpgradeReq MSHR misses 1217system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 195411 # number of SCUpgradeReq MSHR misses 1218system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 6 # number of SCUpgradeFailReq MSHR misses 1219system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses 1220system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 269809 # number of ReadExReq MSHR misses 1221system.cpu0.l2cache.ReadExReq_mshr_misses::total 269809 # number of ReadExReq MSHR misses 1222system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 724175 # number of ReadCleanReq MSHR misses 1223system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 724175 # number of ReadCleanReq MSHR misses 1224system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1018334 # number of ReadSharedReq MSHR misses 1225system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1018334 # number of ReadSharedReq MSHR misses 1226system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 608332 # number of InvalidateReq MSHR misses 1227system.cpu0.l2cache.InvalidateReq_mshr_misses::total 608332 # number of InvalidateReq MSHR misses 1228system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 12299 # number of demand (read+write) MSHR misses 1229system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8465 # number of demand (read+write) MSHR misses 1230system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 724175 # number of demand (read+write) MSHR misses 1231system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1288143 # number of demand (read+write) MSHR misses 1232system.cpu0.l2cache.demand_mshr_misses::total 2033082 # number of demand (read+write) MSHR misses 1233system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 12299 # number of overall MSHR misses 1234system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8465 # number of overall MSHR misses 1235system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 724175 # number of overall MSHR misses 1236system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1288143 # number of overall MSHR misses 1237system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 828377 # number of overall MSHR misses 1238system.cpu0.l2cache.overall_mshr_misses::total 2861459 # number of overall MSHR misses 1239system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52299 # number of ReadReq MSHR uncacheable 1240system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31702 # number of ReadReq MSHR uncacheable 1241system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 84001 # number of ReadReq MSHR uncacheable 1242system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 31225 # number of WriteReq MSHR uncacheable 1243system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 31225 # number of WriteReq MSHR uncacheable 1244system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52299 # number of overall MSHR uncacheable misses 1245system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 62927 # number of overall MSHR uncacheable misses 1246system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 115226 # number of overall MSHR uncacheable misses 1247system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 370792500 # number of ReadReq MSHR miss cycles 1248system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 290829500 # number of ReadReq MSHR miss cycles 1249system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 661622000 # number of ReadReq MSHR miss cycles 1250system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 38426708957 # number of HardPFReq MSHR miss cycles 1251system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 38426708957 # number of HardPFReq MSHR miss cycles 1252system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 5314605493 # number of UpgradeReq MSHR miss cycles 1253system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 5314605493 # number of UpgradeReq MSHR miss cycles 1254system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3216326998 # number of SCUpgradeReq MSHR miss cycles 1255system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3216326998 # number of SCUpgradeReq MSHR miss cycles 1256system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2770000 # number of SCUpgradeFailReq MSHR miss cycles 1257system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2770000 # number of SCUpgradeFailReq MSHR miss cycles 1258system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11196985497 # number of ReadExReq MSHR miss cycles 1259system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11196985497 # number of ReadExReq MSHR miss cycles 1260system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 20080949000 # number of ReadCleanReq MSHR miss cycles 1261system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 20080949000 # number of ReadCleanReq MSHR miss cycles 1262system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 29451947493 # number of ReadSharedReq MSHR miss cycles 1263system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 29451947493 # number of ReadSharedReq MSHR miss cycles 1264system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 20309675000 # number of InvalidateReq MSHR miss cycles 1265system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 20309675000 # number of InvalidateReq MSHR miss cycles 1266system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 370792500 # number of demand (read+write) MSHR miss cycles 1267system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 290829500 # number of demand (read+write) MSHR miss cycles 1268system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 20080949000 # number of demand (read+write) MSHR miss cycles 1269system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 40648932990 # number of demand (read+write) MSHR miss cycles 1270system.cpu0.l2cache.demand_mshr_miss_latency::total 61391503990 # number of demand (read+write) MSHR miss cycles 1271system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 370792500 # number of overall MSHR miss cycles 1272system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 290829500 # number of overall MSHR miss cycles 1273system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 20080949000 # number of overall MSHR miss cycles 1274system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 40648932990 # number of overall MSHR miss cycles 1275system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 38426708957 # number of overall MSHR miss cycles 1276system.cpu0.l2cache.overall_mshr_miss_latency::total 99818212947 # number of overall MSHR miss cycles 1277system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4418803500 # number of ReadReq MSHR uncacheable cycles 1278system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5883144500 # number of ReadReq MSHR uncacheable cycles 1279system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10301948000 # number of ReadReq MSHR uncacheable cycles 1280system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4418803500 # number of overall MSHR uncacheable cycles 1281system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5883144500 # number of overall MSHR uncacheable cycles 1282system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10301948000 # number of overall MSHR uncacheable cycles 1283system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021441 # mshr miss rate for ReadReq accesses 1284system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.048181 # mshr miss rate for ReadReq accesses 1285system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.027711 # mshr miss rate for ReadReq accesses 1286system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1287system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1288system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.997627 # mshr miss rate for UpgradeReq accesses 1289system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.997627 # mshr miss rate for UpgradeReq accesses 1290system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1291system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1292system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1293system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1294system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.222469 # mshr miss rate for ReadExReq accesses 1295system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.222469 # mshr miss rate for ReadExReq accesses 1296system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.073759 # mshr miss rate for ReadCleanReq accesses 1297system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.073759 # mshr miss rate for ReadCleanReq accesses 1298system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.248813 # mshr miss rate for ReadSharedReq accesses 1299system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248813 # mshr miss rate for ReadSharedReq accesses 1300system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.737239 # mshr miss rate for InvalidateReq accesses 1301system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.737239 # mshr miss rate for InvalidateReq accesses 1302system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021441 # mshr miss rate for demand accesses 1303system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.048181 # mshr miss rate for demand accesses 1304system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.073759 # mshr miss rate for demand accesses 1305system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.242791 # mshr miss rate for demand accesses 1306system.cpu0.l2cache.demand_mshr_miss_rate::total 0.128085 # mshr miss rate for demand accesses 1307system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021441 # mshr miss rate for overall accesses 1308system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.048181 # mshr miss rate for overall accesses 1309system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.073759 # mshr miss rate for overall accesses 1310system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.242791 # mshr miss rate for overall accesses 1311system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1312system.cpu0.l2cache.overall_mshr_miss_rate::total 0.180273 # mshr miss rate for overall accesses 1313system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30148.182779 # average ReadReq mshr miss latency 1314system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34356.704076 # average ReadReq mshr miss latency 1315system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 31863.899056 # average ReadReq mshr miss latency 1316system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46387.947706 # average HardPFReq mshr miss latency 1317system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46387.947706 # average HardPFReq mshr miss latency 1318system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20687.367869 # average UpgradeReq mshr miss latency 1319system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20687.367869 # average UpgradeReq mshr miss latency 1320system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16459.293479 # average SCUpgradeReq mshr miss latency 1321system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16459.293479 # average SCUpgradeReq mshr miss latency 1322system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 461666.666667 # average SCUpgradeFailReq mshr miss latency 1323system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 461666.666667 # average SCUpgradeFailReq mshr miss latency 1324system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41499.673832 # average ReadExReq mshr miss latency 1325system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41499.673832 # average ReadExReq mshr miss latency 1326system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 27729.414851 # average ReadCleanReq mshr miss latency 1327system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27729.414851 # average ReadCleanReq mshr miss latency 1328system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28921.697098 # average ReadSharedReq mshr miss latency 1329system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28921.697098 # average ReadSharedReq mshr miss latency 1330system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 33385.840298 # average InvalidateReq mshr miss latency 1331system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 33385.840298 # average InvalidateReq mshr miss latency 1332system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30148.182779 # average overall mshr miss latency 1333system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34356.704076 # average overall mshr miss latency 1334system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 27729.414851 # average overall mshr miss latency 1335system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31556.227057 # average overall mshr miss latency 1336system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30196.275404 # average overall mshr miss latency 1337system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30148.182779 # average overall mshr miss latency 1338system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34356.704076 # average overall mshr miss latency 1339system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 27729.414851 # average overall mshr miss latency 1340system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31556.227057 # average overall mshr miss latency 1341system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46387.947706 # average overall mshr miss latency 1342system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34883.677504 # average overall mshr miss latency 1343system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84491.166179 # average ReadReq mshr uncacheable latency 1344system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185576.446281 # average ReadReq mshr uncacheable latency 1345system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 122640.778086 # average ReadReq mshr uncacheable latency 1346system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84491.166179 # average overall mshr uncacheable latency 1347system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 93491.577542 # average overall mshr uncacheable latency 1348system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 89406.453405 # average overall mshr uncacheable latency 1349system.cpu0.toL2Bus.snoop_filter.tot_requests 32574371 # Total number of requests made to the snoop filter. 1350system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16625689 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1351system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2928 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1352system.cpu0.toL2Bus.snoop_filter.tot_snoops 2229520 # Total number of snoops made to the snoop filter. 1353system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2229086 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1354system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 434 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1355system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 1356system.cpu0.toL2Bus.trans_dist::ReadReq 913111 # Transaction distribution 1357system.cpu0.toL2Bus.trans_dist::ReadResp 14927613 # Transaction distribution 1358system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution 1359system.cpu0.toL2Bus.trans_dist::WriteReq 31225 # Transaction distribution 1360system.cpu0.toL2Bus.trans_dist::WriteResp 31225 # Transaction distribution 1361system.cpu0.toL2Bus.trans_dist::WritebackDirty 5591471 # Transaction distribution 1362system.cpu0.toL2Bus.trans_dist::WritebackClean 11901739 # Transaction distribution 1363system.cpu0.toL2Bus.trans_dist::CleanEvict 2979875 # Transaction distribution 1364system.cpu0.toL2Bus.trans_dist::HardPFReq 1058098 # Transaction distribution 1365system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution 1366system.cpu0.toL2Bus.trans_dist::UpgradeReq 473129 # Transaction distribution 1367system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 352230 # Transaction distribution 1368system.cpu0.toL2Bus.trans_dist::UpgradeResp 525861 # Transaction distribution 1369system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 51 # Transaction distribution 1370system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution 1371system.cpu0.toL2Bus.trans_dist::ReadExReq 1247048 # Transaction distribution 1372system.cpu0.toL2Bus.trans_dist::ReadExResp 1223348 # Transaction distribution 1373system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9818101 # Transaction distribution 1374system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5127973 # Transaction distribution 1375system.cpu0.toL2Bus.trans_dist::InvalidateReq 875849 # Transaction distribution 1376system.cpu0.toL2Bus.trans_dist::InvalidateResp 825149 # Transaction distribution 1377system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 29558377 # Packet count per connected master and slave (bytes) 1378system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19506589 # Packet count per connected master and slave (bytes) 1379system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 370132 # Packet count per connected master and slave (bytes) 1380system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1208276 # Packet count per connected master and slave (bytes) 1381system.cpu0.toL2Bus.pkt_count::total 50643374 # Packet count per connected master and slave (bytes) 1382system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1260030528 # Cumulative packet size per connected master and slave (bytes) 1383system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 732739948 # Cumulative packet size per connected master and slave (bytes) 1384system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1405536 # Cumulative packet size per connected master and slave (bytes) 1385system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4588864 # Cumulative packet size per connected master and slave (bytes) 1386system.cpu0.toL2Bus.pkt_size::total 1998764876 # Cumulative packet size per connected master and slave (bytes) 1387system.cpu0.toL2Bus.snoops 7447074 # Total snoops (count) 1388system.cpu0.toL2Bus.snoop_fanout::samples 24526103 # Request fanout histogram 1389system.cpu0.toL2Bus.snoop_fanout::mean 0.104449 # Request fanout histogram 1390system.cpu0.toL2Bus.snoop_fanout::stdev 0.305900 # Request fanout histogram 1391system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1392system.cpu0.toL2Bus.snoop_fanout::0 21964812 89.56% 89.56% # Request fanout histogram 1393system.cpu0.toL2Bus.snoop_fanout::1 2560857 10.44% 100.00% # Request fanout histogram 1394system.cpu0.toL2Bus.snoop_fanout::2 434 0.00% 100.00% # Request fanout histogram 1395system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1396system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1397system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1398system.cpu0.toL2Bus.snoop_fanout::total 24526103 # Request fanout histogram 1399system.cpu0.toL2Bus.reqLayer0.occupancy 32454354981 # Layer occupancy (ticks) 1400system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1401system.cpu0.toL2Bus.snoopLayer0.occupancy 208052919 # Layer occupancy (ticks) 1402system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1403system.cpu0.toL2Bus.respLayer0.occupancy 14809077024 # Layer occupancy (ticks) 1404system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1405system.cpu0.toL2Bus.respLayer1.occupancy 8648892723 # Layer occupancy (ticks) 1406system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1407system.cpu0.toL2Bus.respLayer2.occupancy 194486906 # Layer occupancy (ticks) 1408system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1409system.cpu0.toL2Bus.respLayer3.occupancy 634782270 # Layer occupancy (ticks) 1410system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1411system.cpu1.branchPred.lookups 123875539 # Number of BP lookups 1412system.cpu1.branchPred.condPredicted 88073767 # Number of conditional branches predicted 1413system.cpu1.branchPred.condIncorrect 5721607 # Number of conditional branches incorrect 1414system.cpu1.branchPred.BTBLookups 93465185 # Number of BTB lookups 1415system.cpu1.branchPred.BTBHits 65276742 # Number of BTB hits 1416system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1417system.cpu1.branchPred.BTBHitPct 69.840703 # BTB Hit Percentage 1418system.cpu1.branchPred.usedRAS 14217829 # Number of times the RAS was used to get a target. 1419system.cpu1.branchPred.RASInCorrect 926540 # Number of incorrect RAS predictions. 1420system.cpu1.branchPred.indirectLookups 3290763 # Number of indirect predictor lookups. 1421system.cpu1.branchPred.indirectHits 2135700 # Number of indirect target hits. 1422system.cpu1.branchPred.indirectMisses 1155063 # Number of indirect misses. 1423system.cpu1.branchPredindirectMispredicted 419705 # Number of mispredicted indirect branches. 1424system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 1425system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1426system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1427system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1428system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1429system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1430system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1431system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1432system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1433system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1434system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1435system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1436system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1437system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1438system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1439system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1440system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1441system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1442system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1443system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1444system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1445system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1446system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1447system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1448system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1449system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1450system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1451system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1452system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1453system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1454system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 1455system.cpu1.dtb.walker.walks 255224 # Table walker walks requested 1456system.cpu1.dtb.walker.walksLong 255224 # Table walker walks initiated with long descriptors 1457system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8861 # Level at which table walker walks with long descriptors terminate 1458system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 76574 # Level at which table walker walks with long descriptors terminate 1459system.cpu1.dtb.walker.walkWaitTime::samples 255224 # Table walker wait (enqueue to first request) latency 1460system.cpu1.dtb.walker.walkWaitTime::0 255224 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1461system.cpu1.dtb.walker.walkWaitTime::total 255224 # Table walker wait (enqueue to first request) latency 1462system.cpu1.dtb.walker.walkCompletionTime::samples 85435 # Table walker service (enqueue to completion) latency 1463system.cpu1.dtb.walker.walkCompletionTime::mean 22815.538128 # Table walker service (enqueue to completion) latency 1464system.cpu1.dtb.walker.walkCompletionTime::gmean 21300.261475 # Table walker service (enqueue to completion) latency 1465system.cpu1.dtb.walker.walkCompletionTime::stdev 14551.493747 # Table walker service (enqueue to completion) latency 1466system.cpu1.dtb.walker.walkCompletionTime::0-65535 84387 98.77% 98.77% # Table walker service (enqueue to completion) latency 1467system.cpu1.dtb.walker.walkCompletionTime::65536-131071 897 1.05% 99.82% # Table walker service (enqueue to completion) latency 1468system.cpu1.dtb.walker.walkCompletionTime::131072-196607 42 0.05% 99.87% # Table walker service (enqueue to completion) latency 1469system.cpu1.dtb.walker.walkCompletionTime::196608-262143 51 0.06% 99.93% # Table walker service (enqueue to completion) latency 1470system.cpu1.dtb.walker.walkCompletionTime::262144-327679 31 0.04% 99.97% # Table walker service (enqueue to completion) latency 1471system.cpu1.dtb.walker.walkCompletionTime::327680-393215 13 0.02% 99.98% # Table walker service (enqueue to completion) latency 1472system.cpu1.dtb.walker.walkCompletionTime::393216-458751 7 0.01% 99.99% # Table walker service (enqueue to completion) latency 1473system.cpu1.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 1474system.cpu1.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 1475system.cpu1.dtb.walker.walkCompletionTime::total 85435 # Table walker service (enqueue to completion) latency 1476system.cpu1.dtb.walker.walksPending::samples -788977056 # Table walker pending requests distribution 1477system.cpu1.dtb.walker.walksPending::0 -788977056 100.00% 100.00% # Table walker pending requests distribution 1478system.cpu1.dtb.walker.walksPending::total -788977056 # Table walker pending requests distribution 1479system.cpu1.dtb.walker.walkPageSizes::4K 76574 89.63% 89.63% # Table walker page sizes translated 1480system.cpu1.dtb.walker.walkPageSizes::2M 8861 10.37% 100.00% # Table walker page sizes translated 1481system.cpu1.dtb.walker.walkPageSizes::total 85435 # Table walker page sizes translated 1482system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 255224 # Table walker requests started/completed, data/inst 1483system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1484system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 255224 # Table walker requests started/completed, data/inst 1485system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 85435 # Table walker requests started/completed, data/inst 1486system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1487system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 85435 # Table walker requests started/completed, data/inst 1488system.cpu1.dtb.walker.walkRequestOrigin::total 340659 # Table walker requests started/completed, data/inst 1489system.cpu1.dtb.inst_hits 0 # ITB inst hits 1490system.cpu1.dtb.inst_misses 0 # ITB inst misses 1491system.cpu1.dtb.read_hits 78594683 # DTB read hits 1492system.cpu1.dtb.read_misses 208094 # DTB read misses 1493system.cpu1.dtb.write_hits 69544419 # DTB write hits 1494system.cpu1.dtb.write_misses 47130 # DTB write misses 1495system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1496system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1497system.cpu1.dtb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID 1498system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 1499system.cpu1.dtb.flush_entries 35782 # Number of entries that have been flushed from TLB 1500system.cpu1.dtb.align_faults 839 # Number of TLB faults due to alignment restrictions 1501system.cpu1.dtb.prefetch_faults 6709 # Number of TLB faults due to prefetch 1502system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1503system.cpu1.dtb.perms_faults 11450 # Number of TLB faults due to permissions restrictions 1504system.cpu1.dtb.read_accesses 78802777 # DTB read accesses 1505system.cpu1.dtb.write_accesses 69591549 # DTB write accesses 1506system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1507system.cpu1.dtb.hits 148139102 # DTB hits 1508system.cpu1.dtb.misses 255224 # DTB misses 1509system.cpu1.dtb.accesses 148394326 # DTB accesses 1510system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 1511system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1512system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1513system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1514system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1515system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1516system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1517system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1518system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1519system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1520system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1521system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1522system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1523system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1524system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1525system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1526system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1527system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1528system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1529system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1530system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1531system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1532system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1533system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1534system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1535system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1536system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1537system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1538system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1539system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1540system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 1541system.cpu1.itb.walker.walks 62177 # Table walker walks requested 1542system.cpu1.itb.walker.walksLong 62177 # Table walker walks initiated with long descriptors 1543system.cpu1.itb.walker.walksLongTerminationLevel::Level2 630 # Level at which table walker walks with long descriptors terminate 1544system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54596 # Level at which table walker walks with long descriptors terminate 1545system.cpu1.itb.walker.walkWaitTime::samples 62177 # Table walker wait (enqueue to first request) latency 1546system.cpu1.itb.walker.walkWaitTime::0 62177 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1547system.cpu1.itb.walker.walkWaitTime::total 62177 # Table walker wait (enqueue to first request) latency 1548system.cpu1.itb.walker.walkCompletionTime::samples 55226 # Table walker service (enqueue to completion) latency 1549system.cpu1.itb.walker.walkCompletionTime::mean 25650.988665 # Table walker service (enqueue to completion) latency 1550system.cpu1.itb.walker.walkCompletionTime::gmean 23787.605646 # Table walker service (enqueue to completion) latency 1551system.cpu1.itb.walker.walkCompletionTime::stdev 16059.408850 # Table walker service (enqueue to completion) latency 1552system.cpu1.itb.walker.walkCompletionTime::0-32767 49961 90.47% 90.47% # Table walker service (enqueue to completion) latency 1553system.cpu1.itb.walker.walkCompletionTime::32768-65535 4236 7.67% 98.14% # Table walker service (enqueue to completion) latency 1554system.cpu1.itb.walker.walkCompletionTime::65536-98303 9 0.02% 98.15% # Table walker service (enqueue to completion) latency 1555system.cpu1.itb.walker.walkCompletionTime::98304-131071 906 1.64% 99.79% # Table walker service (enqueue to completion) latency 1556system.cpu1.itb.walker.walkCompletionTime::131072-163839 24 0.04% 99.84% # Table walker service (enqueue to completion) latency 1557system.cpu1.itb.walker.walkCompletionTime::163840-196607 14 0.03% 99.86% # Table walker service (enqueue to completion) latency 1558system.cpu1.itb.walker.walkCompletionTime::196608-229375 28 0.05% 99.91% # Table walker service (enqueue to completion) latency 1559system.cpu1.itb.walker.walkCompletionTime::229376-262143 21 0.04% 99.95% # Table walker service (enqueue to completion) latency 1560system.cpu1.itb.walker.walkCompletionTime::262144-294911 9 0.02% 99.97% # Table walker service (enqueue to completion) latency 1561system.cpu1.itb.walker.walkCompletionTime::294912-327679 5 0.01% 99.98% # Table walker service (enqueue to completion) latency 1562system.cpu1.itb.walker.walkCompletionTime::327680-360447 3 0.01% 99.98% # Table walker service (enqueue to completion) latency 1563system.cpu1.itb.walker.walkCompletionTime::360448-393215 7 0.01% 99.99% # Table walker service (enqueue to completion) latency 1564system.cpu1.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1565system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1566system.cpu1.itb.walker.walkCompletionTime::total 55226 # Table walker service (enqueue to completion) latency 1567system.cpu1.itb.walker.walksPending::samples -789630556 # Table walker pending requests distribution 1568system.cpu1.itb.walker.walksPending::0 -789630556 100.00% 100.00% # Table walker pending requests distribution 1569system.cpu1.itb.walker.walksPending::total -789630556 # Table walker pending requests distribution 1570system.cpu1.itb.walker.walkPageSizes::4K 54596 98.86% 98.86% # Table walker page sizes translated 1571system.cpu1.itb.walker.walkPageSizes::2M 630 1.14% 100.00% # Table walker page sizes translated 1572system.cpu1.itb.walker.walkPageSizes::total 55226 # Table walker page sizes translated 1573system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1574system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 62177 # Table walker requests started/completed, data/inst 1575system.cpu1.itb.walker.walkRequestOrigin_Requested::total 62177 # Table walker requests started/completed, data/inst 1576system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1577system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55226 # Table walker requests started/completed, data/inst 1578system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55226 # Table walker requests started/completed, data/inst 1579system.cpu1.itb.walker.walkRequestOrigin::total 117403 # Table walker requests started/completed, data/inst 1580system.cpu1.itb.inst_hits 219337574 # ITB inst hits 1581system.cpu1.itb.inst_misses 62177 # ITB inst misses 1582system.cpu1.itb.read_hits 0 # DTB read hits 1583system.cpu1.itb.read_misses 0 # DTB read misses 1584system.cpu1.itb.write_hits 0 # DTB write hits 1585system.cpu1.itb.write_misses 0 # DTB write misses 1586system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1587system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1588system.cpu1.itb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID 1589system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 1590system.cpu1.itb.flush_entries 25319 # Number of entries that have been flushed from TLB 1591system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1592system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1593system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1594system.cpu1.itb.perms_faults 167002 # Number of TLB faults due to permissions restrictions 1595system.cpu1.itb.read_accesses 0 # DTB read accesses 1596system.cpu1.itb.write_accesses 0 # DTB write accesses 1597system.cpu1.itb.inst_accesses 219399751 # ITB inst accesses 1598system.cpu1.itb.hits 219337574 # DTB hits 1599system.cpu1.itb.misses 62177 # DTB misses 1600system.cpu1.itb.accesses 219399751 # DTB accesses 1601system.cpu1.numPwrStateTransitions 10996 # Number of power state transitions 1602system.cpu1.pwrStateClkGateDist::samples 5498 # Distribution of time spent in the clock gated state 1603system.cpu1.pwrStateClkGateDist::mean 8537078490.682248 # Distribution of time spent in the clock gated state 1604system.cpu1.pwrStateClkGateDist::stdev 139542991677.263855 # Distribution of time spent in the clock gated state 1605system.cpu1.pwrStateClkGateDist::underflows 3923 71.35% 71.35% # Distribution of time spent in the clock gated state 1606system.cpu1.pwrStateClkGateDist::1000-5e+10 1550 28.19% 99.55% # Distribution of time spent in the clock gated state 1607system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.02% 99.56% # Distribution of time spent in the clock gated state 1608system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 5 0.09% 99.65% # Distribution of time spent in the clock gated state 1609system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 2 0.04% 99.69% # Distribution of time spent in the clock gated state 1610system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.71% # Distribution of time spent in the clock gated state 1611system.cpu1.pwrStateClkGateDist::6e+11-6.5e+11 1 0.02% 99.73% # Distribution of time spent in the clock gated state 1612system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.02% 99.75% # Distribution of time spent in the clock gated state 1613system.cpu1.pwrStateClkGateDist::overflows 14 0.25% 100.00% # Distribution of time spent in the clock gated state 1614system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 1615system.cpu1.pwrStateClkGateDist::max_value 7470355729396 # Distribution of time spent in the clock gated state 1616system.cpu1.pwrStateClkGateDist::total 5498 # Distribution of time spent in the clock gated state 1617system.cpu1.pwrStateResidencyTicks::ON 419045786229 # Cumulative time (in ticks) in various power states 1618system.cpu1.pwrStateResidencyTicks::CLK_GATED 46936857541771 # Cumulative time (in ticks) in various power states 1619system.cpu1.numCycles 838096745 # number of cpu cycles simulated 1620system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1621system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1622system.cpu1.committedInsts 400342475 # Number of instructions committed 1623system.cpu1.committedOps 472062345 # Number of ops (including micro ops) committed 1624system.cpu1.discardedOps 44700411 # Number of ops (including micro ops) which were discarded before commit 1625system.cpu1.numFetchSuspends 5381 # Number of times Execute suspended instruction fetching 1626system.cpu1.quiesceCycles 93874475142 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1627system.cpu1.cpi 2.093449 # CPI: cycles per instruction 1628system.cpu1.ipc 0.477681 # IPC: instructions per cycle 1629system.cpu1.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 1630system.cpu1.op_class_0::IntAlu 326101667 69.08% 69.08% # Class of committed instruction 1631system.cpu1.op_class_0::IntMult 925373 0.20% 69.28% # Class of committed instruction 1632system.cpu1.op_class_0::IntDiv 54057 0.01% 69.29% # Class of committed instruction 1633system.cpu1.op_class_0::FloatAdd 0 0.00% 69.29% # Class of committed instruction 1634system.cpu1.op_class_0::FloatCmp 0 0.00% 69.29% # Class of committed instruction 1635system.cpu1.op_class_0::FloatCvt 0 0.00% 69.29% # Class of committed instruction 1636system.cpu1.op_class_0::FloatMult 0 0.00% 69.29% # Class of committed instruction 1637system.cpu1.op_class_0::FloatDiv 0 0.00% 69.29% # Class of committed instruction 1638system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.29% # Class of committed instruction 1639system.cpu1.op_class_0::SimdAdd 0 0.00% 69.29% # Class of committed instruction 1640system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.29% # Class of committed instruction 1641system.cpu1.op_class_0::SimdAlu 0 0.00% 69.29% # Class of committed instruction 1642system.cpu1.op_class_0::SimdCmp 0 0.00% 69.29% # Class of committed instruction 1643system.cpu1.op_class_0::SimdCvt 0 0.00% 69.29% # Class of committed instruction 1644system.cpu1.op_class_0::SimdMisc 0 0.00% 69.29% # Class of committed instruction 1645system.cpu1.op_class_0::SimdMult 0 0.00% 69.29% # Class of committed instruction 1646system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.29% # Class of committed instruction 1647system.cpu1.op_class_0::SimdShift 0 0.00% 69.29% # Class of committed instruction 1648system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.29% # Class of committed instruction 1649system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.29% # Class of committed instruction 1650system.cpu1.op_class_0::SimdFloatAdd 8 0.00% 69.29% # Class of committed instruction 1651system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.29% # Class of committed instruction 1652system.cpu1.op_class_0::SimdFloatCmp 13 0.00% 69.29% # Class of committed instruction 1653system.cpu1.op_class_0::SimdFloatCvt 21 0.00% 69.29% # Class of committed instruction 1654system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.29% # Class of committed instruction 1655system.cpu1.op_class_0::SimdFloatMisc 72329 0.02% 69.30% # Class of committed instruction 1656system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.30% # Class of committed instruction 1657system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.30% # Class of committed instruction 1658system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.30% # Class of committed instruction 1659system.cpu1.op_class_0::MemRead 75664367 16.03% 85.33% # Class of committed instruction 1660system.cpu1.op_class_0::MemWrite 69244510 14.67% 100.00% # Class of committed instruction 1661system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1662system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1663system.cpu1.op_class_0::total 472062345 # Class of committed instruction 1664system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1665system.cpu1.kern.inst.quiesce 5498 # number of quiesce instructions executed 1666system.cpu1.tickCycles 657140254 # Number of cycles that the object actually ticked 1667system.cpu1.idleCycles 180956491 # Total number of cycles that the object has spent stopped 1668system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 1669system.cpu1.dcache.tags.replacements 4810857 # number of replacements 1670system.cpu1.dcache.tags.tagsinuse 458.623346 # Cycle average of tags in use 1671system.cpu1.dcache.tags.total_refs 140763490 # Total number of references to valid blocks. 1672system.cpu1.dcache.tags.sampled_refs 4811366 # Sample count of references to valid blocks. 1673system.cpu1.dcache.tags.avg_refs 29.256450 # Average number of references to valid blocks. 1674system.cpu1.dcache.tags.warmup_cycle 8377530544000 # Cycle when the warmup percentage was hit. 1675system.cpu1.dcache.tags.occ_blocks::cpu1.data 458.623346 # Average occupied blocks per requestor 1676system.cpu1.dcache.tags.occ_percent::cpu1.data 0.895749 # Average percentage of cache occupancy 1677system.cpu1.dcache.tags.occ_percent::total 0.895749 # Average percentage of cache occupancy 1678system.cpu1.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id 1679system.cpu1.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 1680system.cpu1.dcache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id 1681system.cpu1.dcache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id 1682system.cpu1.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id 1683system.cpu1.dcache.tags.tag_accesses 298669128 # Number of tag accesses 1684system.cpu1.dcache.tags.data_accesses 298669128 # Number of data accesses 1685system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 1686system.cpu1.dcache.ReadReq_hits::cpu1.data 72030058 # number of ReadReq hits 1687system.cpu1.dcache.ReadReq_hits::total 72030058 # number of ReadReq hits 1688system.cpu1.dcache.WriteReq_hits::cpu1.data 64877267 # number of WriteReq hits 1689system.cpu1.dcache.WriteReq_hits::total 64877267 # number of WriteReq hits 1690system.cpu1.dcache.SoftPFReq_hits::cpu1.data 197389 # number of SoftPFReq hits 1691system.cpu1.dcache.SoftPFReq_hits::total 197389 # number of SoftPFReq hits 1692system.cpu1.dcache.WriteLineReq_hits::cpu1.data 40268 # number of WriteLineReq hits 1693system.cpu1.dcache.WriteLineReq_hits::total 40268 # number of WriteLineReq hits 1694system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1587155 # number of LoadLockedReq hits 1695system.cpu1.dcache.LoadLockedReq_hits::total 1587155 # number of LoadLockedReq hits 1696system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1543611 # number of StoreCondReq hits 1697system.cpu1.dcache.StoreCondReq_hits::total 1543611 # number of StoreCondReq hits 1698system.cpu1.dcache.demand_hits::cpu1.data 136947593 # number of demand (read+write) hits 1699system.cpu1.dcache.demand_hits::total 136947593 # number of demand (read+write) hits 1700system.cpu1.dcache.overall_hits::cpu1.data 137144982 # number of overall hits 1701system.cpu1.dcache.overall_hits::total 137144982 # number of overall hits 1702system.cpu1.dcache.ReadReq_misses::cpu1.data 3077185 # number of ReadReq misses 1703system.cpu1.dcache.ReadReq_misses::total 3077185 # number of ReadReq misses 1704system.cpu1.dcache.WriteReq_misses::cpu1.data 2162319 # number of WriteReq misses 1705system.cpu1.dcache.WriteReq_misses::total 2162319 # number of WriteReq misses 1706system.cpu1.dcache.SoftPFReq_misses::cpu1.data 609138 # number of SoftPFReq misses 1707system.cpu1.dcache.SoftPFReq_misses::total 609138 # number of SoftPFReq misses 1708system.cpu1.dcache.WriteLineReq_misses::cpu1.data 415243 # number of WriteLineReq misses 1709system.cpu1.dcache.WriteLineReq_misses::total 415243 # number of WriteLineReq misses 1710system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 150447 # number of LoadLockedReq misses 1711system.cpu1.dcache.LoadLockedReq_misses::total 150447 # number of LoadLockedReq misses 1712system.cpu1.dcache.StoreCondReq_misses::cpu1.data 192941 # number of StoreCondReq misses 1713system.cpu1.dcache.StoreCondReq_misses::total 192941 # number of StoreCondReq misses 1714system.cpu1.dcache.demand_misses::cpu1.data 5654747 # number of demand (read+write) misses 1715system.cpu1.dcache.demand_misses::total 5654747 # number of demand (read+write) misses 1716system.cpu1.dcache.overall_misses::cpu1.data 6263885 # number of overall misses 1717system.cpu1.dcache.overall_misses::total 6263885 # number of overall misses 1718system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 46366444000 # number of ReadReq miss cycles 1719system.cpu1.dcache.ReadReq_miss_latency::total 46366444000 # number of ReadReq miss cycles 1720system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 40662976500 # number of WriteReq miss cycles 1721system.cpu1.dcache.WriteReq_miss_latency::total 40662976500 # number of WriteReq miss cycles 1722system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10070349000 # number of WriteLineReq miss cycles 1723system.cpu1.dcache.WriteLineReq_miss_latency::total 10070349000 # number of WriteLineReq miss cycles 1724system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2311960000 # number of LoadLockedReq miss cycles 1725system.cpu1.dcache.LoadLockedReq_miss_latency::total 2311960000 # number of LoadLockedReq miss cycles 1726system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4775235000 # number of StoreCondReq miss cycles 1727system.cpu1.dcache.StoreCondReq_miss_latency::total 4775235000 # number of StoreCondReq miss cycles 1728system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2623000 # number of StoreCondFailReq miss cycles 1729system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2623000 # number of StoreCondFailReq miss cycles 1730system.cpu1.dcache.demand_miss_latency::cpu1.data 97099769500 # number of demand (read+write) miss cycles 1731system.cpu1.dcache.demand_miss_latency::total 97099769500 # number of demand (read+write) miss cycles 1732system.cpu1.dcache.overall_miss_latency::cpu1.data 97099769500 # number of overall miss cycles 1733system.cpu1.dcache.overall_miss_latency::total 97099769500 # number of overall miss cycles 1734system.cpu1.dcache.ReadReq_accesses::cpu1.data 75107243 # number of ReadReq accesses(hits+misses) 1735system.cpu1.dcache.ReadReq_accesses::total 75107243 # number of ReadReq accesses(hits+misses) 1736system.cpu1.dcache.WriteReq_accesses::cpu1.data 67039586 # number of WriteReq accesses(hits+misses) 1737system.cpu1.dcache.WriteReq_accesses::total 67039586 # number of WriteReq accesses(hits+misses) 1738system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 806527 # number of SoftPFReq accesses(hits+misses) 1739system.cpu1.dcache.SoftPFReq_accesses::total 806527 # number of SoftPFReq accesses(hits+misses) 1740system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 455511 # number of WriteLineReq accesses(hits+misses) 1741system.cpu1.dcache.WriteLineReq_accesses::total 455511 # number of WriteLineReq accesses(hits+misses) 1742system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1737602 # number of LoadLockedReq accesses(hits+misses) 1743system.cpu1.dcache.LoadLockedReq_accesses::total 1737602 # number of LoadLockedReq accesses(hits+misses) 1744system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1736552 # number of StoreCondReq accesses(hits+misses) 1745system.cpu1.dcache.StoreCondReq_accesses::total 1736552 # number of StoreCondReq accesses(hits+misses) 1746system.cpu1.dcache.demand_accesses::cpu1.data 142602340 # number of demand (read+write) accesses 1747system.cpu1.dcache.demand_accesses::total 142602340 # number of demand (read+write) accesses 1748system.cpu1.dcache.overall_accesses::cpu1.data 143408867 # number of overall (read+write) accesses 1749system.cpu1.dcache.overall_accesses::total 143408867 # number of overall (read+write) accesses 1750system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.040971 # miss rate for ReadReq accesses 1751system.cpu1.dcache.ReadReq_miss_rate::total 0.040971 # miss rate for ReadReq accesses 1752system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032254 # miss rate for WriteReq accesses 1753system.cpu1.dcache.WriteReq_miss_rate::total 0.032254 # miss rate for WriteReq accesses 1754system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.755261 # miss rate for SoftPFReq accesses 1755system.cpu1.dcache.SoftPFReq_miss_rate::total 0.755261 # miss rate for SoftPFReq accesses 1756system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.911598 # miss rate for WriteLineReq accesses 1757system.cpu1.dcache.WriteLineReq_miss_rate::total 0.911598 # miss rate for WriteLineReq accesses 1758system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086583 # miss rate for LoadLockedReq accesses 1759system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086583 # miss rate for LoadLockedReq accesses 1760system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.111106 # miss rate for StoreCondReq accesses 1761system.cpu1.dcache.StoreCondReq_miss_rate::total 0.111106 # miss rate for StoreCondReq accesses 1762system.cpu1.dcache.demand_miss_rate::cpu1.data 0.039654 # miss rate for demand accesses 1763system.cpu1.dcache.demand_miss_rate::total 0.039654 # miss rate for demand accesses 1764system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043679 # miss rate for overall accesses 1765system.cpu1.dcache.overall_miss_rate::total 0.043679 # miss rate for overall accesses 1766system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15067.811653 # average ReadReq miss latency 1767system.cpu1.dcache.ReadReq_avg_miss_latency::total 15067.811653 # average ReadReq miss latency 1768system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18805.262545 # average WriteReq miss latency 1769system.cpu1.dcache.WriteReq_avg_miss_latency::total 18805.262545 # average WriteReq miss latency 1770system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24251.700811 # average WriteLineReq miss latency 1771system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24251.700811 # average WriteLineReq miss latency 1772system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15367.272196 # average LoadLockedReq miss latency 1773system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15367.272196 # average LoadLockedReq miss latency 1774system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24749.716234 # average StoreCondReq miss latency 1775system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24749.716234 # average StoreCondReq miss latency 1776system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1777system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1778system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17171.372919 # average overall miss latency 1779system.cpu1.dcache.demand_avg_miss_latency::total 17171.372919 # average overall miss latency 1780system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15501.524932 # average overall miss latency 1781system.cpu1.dcache.overall_avg_miss_latency::total 15501.524932 # average overall miss latency 1782system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1783system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1784system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1785system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1786system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1787system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1788system.cpu1.dcache.writebacks::writebacks 4810864 # number of writebacks 1789system.cpu1.dcache.writebacks::total 4810864 # number of writebacks 1790system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 357052 # number of ReadReq MSHR hits 1791system.cpu1.dcache.ReadReq_mshr_hits::total 357052 # number of ReadReq MSHR hits 1792system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 892415 # number of WriteReq MSHR hits 1793system.cpu1.dcache.WriteReq_mshr_hits::total 892415 # number of WriteReq MSHR hits 1794system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 74 # number of WriteLineReq MSHR hits 1795system.cpu1.dcache.WriteLineReq_mshr_hits::total 74 # number of WriteLineReq MSHR hits 1796system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 40665 # number of LoadLockedReq MSHR hits 1797system.cpu1.dcache.LoadLockedReq_mshr_hits::total 40665 # number of LoadLockedReq MSHR hits 1798system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 58 # number of StoreCondReq MSHR hits 1799system.cpu1.dcache.StoreCondReq_mshr_hits::total 58 # number of StoreCondReq MSHR hits 1800system.cpu1.dcache.demand_mshr_hits::cpu1.data 1249541 # number of demand (read+write) MSHR hits 1801system.cpu1.dcache.demand_mshr_hits::total 1249541 # number of demand (read+write) MSHR hits 1802system.cpu1.dcache.overall_mshr_hits::cpu1.data 1249541 # number of overall MSHR hits 1803system.cpu1.dcache.overall_mshr_hits::total 1249541 # number of overall MSHR hits 1804system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2720133 # number of ReadReq MSHR misses 1805system.cpu1.dcache.ReadReq_mshr_misses::total 2720133 # number of ReadReq MSHR misses 1806system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1269904 # number of WriteReq MSHR misses 1807system.cpu1.dcache.WriteReq_mshr_misses::total 1269904 # number of WriteReq MSHR misses 1808system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 608760 # number of SoftPFReq MSHR misses 1809system.cpu1.dcache.SoftPFReq_mshr_misses::total 608760 # number of SoftPFReq MSHR misses 1810system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 415169 # number of WriteLineReq MSHR misses 1811system.cpu1.dcache.WriteLineReq_mshr_misses::total 415169 # number of WriteLineReq MSHR misses 1812system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 109782 # number of LoadLockedReq MSHR misses 1813system.cpu1.dcache.LoadLockedReq_mshr_misses::total 109782 # number of LoadLockedReq MSHR misses 1814system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 192883 # number of StoreCondReq MSHR misses 1815system.cpu1.dcache.StoreCondReq_mshr_misses::total 192883 # number of StoreCondReq MSHR misses 1816system.cpu1.dcache.demand_mshr_misses::cpu1.data 4405206 # number of demand (read+write) MSHR misses 1817system.cpu1.dcache.demand_mshr_misses::total 4405206 # number of demand (read+write) MSHR misses 1818system.cpu1.dcache.overall_mshr_misses::cpu1.data 5013966 # number of overall MSHR misses 1819system.cpu1.dcache.overall_mshr_misses::total 5013966 # number of overall MSHR misses 1820system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6941 # number of ReadReq MSHR uncacheable 1821system.cpu1.dcache.ReadReq_mshr_uncacheable::total 6941 # number of ReadReq MSHR uncacheable 1822system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7280 # number of WriteReq MSHR uncacheable 1823system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7280 # number of WriteReq MSHR uncacheable 1824system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14221 # number of overall MSHR uncacheable misses 1825system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14221 # number of overall MSHR uncacheable misses 1826system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 36972803500 # number of ReadReq MSHR miss cycles 1827system.cpu1.dcache.ReadReq_mshr_miss_latency::total 36972803500 # number of ReadReq MSHR miss cycles 1828system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23335803000 # number of WriteReq MSHR miss cycles 1829system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23335803000 # number of WriteReq MSHR miss cycles 1830system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13834846000 # number of SoftPFReq MSHR miss cycles 1831system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13834846000 # number of SoftPFReq MSHR miss cycles 1832system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9650155000 # number of WriteLineReq MSHR miss cycles 1833system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9650155000 # number of WriteLineReq MSHR miss cycles 1834system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1512082000 # number of LoadLockedReq MSHR miss cycles 1835system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1512082000 # number of LoadLockedReq MSHR miss cycles 1836system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4580259000 # number of StoreCondReq MSHR miss cycles 1837system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4580259000 # number of StoreCondReq MSHR miss cycles 1838system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2341500 # number of StoreCondFailReq MSHR miss cycles 1839system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2341500 # number of StoreCondFailReq MSHR miss cycles 1840system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 69958761500 # number of demand (read+write) MSHR miss cycles 1841system.cpu1.dcache.demand_mshr_miss_latency::total 69958761500 # number of demand (read+write) MSHR miss cycles 1842system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 83793607500 # number of overall MSHR miss cycles 1843system.cpu1.dcache.overall_mshr_miss_latency::total 83793607500 # number of overall MSHR miss cycles 1844system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 837242500 # number of ReadReq MSHR uncacheable cycles 1845system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 837242500 # number of ReadReq MSHR uncacheable cycles 1846system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 837242500 # number of overall MSHR uncacheable cycles 1847system.cpu1.dcache.overall_mshr_uncacheable_latency::total 837242500 # number of overall MSHR uncacheable cycles 1848system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036217 # mshr miss rate for ReadReq accesses 1849system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036217 # mshr miss rate for ReadReq accesses 1850system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018943 # mshr miss rate for WriteReq accesses 1851system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018943 # mshr miss rate for WriteReq accesses 1852system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.754792 # mshr miss rate for SoftPFReq accesses 1853system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.754792 # mshr miss rate for SoftPFReq accesses 1854system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.911436 # mshr miss rate for WriteLineReq accesses 1855system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.911436 # mshr miss rate for WriteLineReq accesses 1856system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063180 # mshr miss rate for LoadLockedReq accesses 1857system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063180 # mshr miss rate for LoadLockedReq accesses 1858system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.111072 # mshr miss rate for StoreCondReq accesses 1859system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.111072 # mshr miss rate for StoreCondReq accesses 1860system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030892 # mshr miss rate for demand accesses 1861system.cpu1.dcache.demand_mshr_miss_rate::total 0.030892 # mshr miss rate for demand accesses 1862system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034963 # mshr miss rate for overall accesses 1863system.cpu1.dcache.overall_mshr_miss_rate::total 0.034963 # mshr miss rate for overall accesses 1864system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13592.277841 # average ReadReq mshr miss latency 1865system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13592.277841 # average ReadReq mshr miss latency 1866system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18376.037086 # average WriteReq mshr miss latency 1867system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18376.037086 # average WriteReq mshr miss latency 1868system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22726.273080 # average SoftPFReq mshr miss latency 1869system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22726.273080 # average SoftPFReq mshr miss latency 1870system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23243.919946 # average WriteLineReq mshr miss latency 1871system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23243.919946 # average WriteLineReq mshr miss latency 1872system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13773.496566 # average LoadLockedReq mshr miss latency 1873system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13773.496566 # average LoadLockedReq mshr miss latency 1874system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23746.307347 # average StoreCondReq mshr miss latency 1875system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23746.307347 # average StoreCondReq mshr miss latency 1876system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1877system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1878system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15880.928497 # average overall mshr miss latency 1879system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15880.928497 # average overall mshr miss latency 1880system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16712.041426 # average overall mshr miss latency 1881system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16712.041426 # average overall mshr miss latency 1882system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 120622.748883 # average ReadReq mshr uncacheable latency 1883system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 120622.748883 # average ReadReq mshr uncacheable latency 1884system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 58873.672738 # average overall mshr uncacheable latency 1885system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 58873.672738 # average overall mshr uncacheable latency 1886system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 1887system.cpu1.icache.tags.replacements 8744967 # number of replacements 1888system.cpu1.icache.tags.tagsinuse 507.224680 # Cycle average of tags in use 1889system.cpu1.icache.tags.total_refs 210419103 # Total number of references to valid blocks. 1890system.cpu1.icache.tags.sampled_refs 8745479 # Sample count of references to valid blocks. 1891system.cpu1.icache.tags.avg_refs 24.060329 # Average number of references to valid blocks. 1892system.cpu1.icache.tags.warmup_cycle 8367967785000 # Cycle when the warmup percentage was hit. 1893system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.224680 # Average occupied blocks per requestor 1894system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990673 # Average percentage of cache occupancy 1895system.cpu1.icache.tags.occ_percent::total 0.990673 # Average percentage of cache occupancy 1896system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1897system.cpu1.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 1898system.cpu1.icache.tags.age_task_id_blocks_1024::1 304 # Occupied blocks per task id 1899system.cpu1.icache.tags.age_task_id_blocks_1024::2 162 # Occupied blocks per task id 1900system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1901system.cpu1.icache.tags.tag_accesses 447074643 # Number of tag accesses 1902system.cpu1.icache.tags.data_accesses 447074643 # Number of data accesses 1903system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 1904system.cpu1.icache.ReadReq_hits::cpu1.inst 210419103 # number of ReadReq hits 1905system.cpu1.icache.ReadReq_hits::total 210419103 # number of ReadReq hits 1906system.cpu1.icache.demand_hits::cpu1.inst 210419103 # number of demand (read+write) hits 1907system.cpu1.icache.demand_hits::total 210419103 # number of demand (read+write) hits 1908system.cpu1.icache.overall_hits::cpu1.inst 210419103 # number of overall hits 1909system.cpu1.icache.overall_hits::total 210419103 # number of overall hits 1910system.cpu1.icache.ReadReq_misses::cpu1.inst 8745479 # number of ReadReq misses 1911system.cpu1.icache.ReadReq_misses::total 8745479 # number of ReadReq misses 1912system.cpu1.icache.demand_misses::cpu1.inst 8745479 # number of demand (read+write) misses 1913system.cpu1.icache.demand_misses::total 8745479 # number of demand (read+write) misses 1914system.cpu1.icache.overall_misses::cpu1.inst 8745479 # number of overall misses 1915system.cpu1.icache.overall_misses::total 8745479 # number of overall misses 1916system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 88268174500 # number of ReadReq miss cycles 1917system.cpu1.icache.ReadReq_miss_latency::total 88268174500 # number of ReadReq miss cycles 1918system.cpu1.icache.demand_miss_latency::cpu1.inst 88268174500 # number of demand (read+write) miss cycles 1919system.cpu1.icache.demand_miss_latency::total 88268174500 # number of demand (read+write) miss cycles 1920system.cpu1.icache.overall_miss_latency::cpu1.inst 88268174500 # number of overall miss cycles 1921system.cpu1.icache.overall_miss_latency::total 88268174500 # number of overall miss cycles 1922system.cpu1.icache.ReadReq_accesses::cpu1.inst 219164582 # number of ReadReq accesses(hits+misses) 1923system.cpu1.icache.ReadReq_accesses::total 219164582 # number of ReadReq accesses(hits+misses) 1924system.cpu1.icache.demand_accesses::cpu1.inst 219164582 # number of demand (read+write) accesses 1925system.cpu1.icache.demand_accesses::total 219164582 # number of demand (read+write) accesses 1926system.cpu1.icache.overall_accesses::cpu1.inst 219164582 # number of overall (read+write) accesses 1927system.cpu1.icache.overall_accesses::total 219164582 # number of overall (read+write) accesses 1928system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.039904 # miss rate for ReadReq accesses 1929system.cpu1.icache.ReadReq_miss_rate::total 0.039904 # miss rate for ReadReq accesses 1930system.cpu1.icache.demand_miss_rate::cpu1.inst 0.039904 # miss rate for demand accesses 1931system.cpu1.icache.demand_miss_rate::total 0.039904 # miss rate for demand accesses 1932system.cpu1.icache.overall_miss_rate::cpu1.inst 0.039904 # miss rate for overall accesses 1933system.cpu1.icache.overall_miss_rate::total 0.039904 # miss rate for overall accesses 1934system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10093.006284 # average ReadReq miss latency 1935system.cpu1.icache.ReadReq_avg_miss_latency::total 10093.006284 # average ReadReq miss latency 1936system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10093.006284 # average overall miss latency 1937system.cpu1.icache.demand_avg_miss_latency::total 10093.006284 # average overall miss latency 1938system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10093.006284 # average overall miss latency 1939system.cpu1.icache.overall_avg_miss_latency::total 10093.006284 # average overall miss latency 1940system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1941system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1942system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1943system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1944system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1945system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1946system.cpu1.icache.writebacks::writebacks 8744967 # number of writebacks 1947system.cpu1.icache.writebacks::total 8744967 # number of writebacks 1948system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8745479 # number of ReadReq MSHR misses 1949system.cpu1.icache.ReadReq_mshr_misses::total 8745479 # number of ReadReq MSHR misses 1950system.cpu1.icache.demand_mshr_misses::cpu1.inst 8745479 # number of demand (read+write) MSHR misses 1951system.cpu1.icache.demand_mshr_misses::total 8745479 # number of demand (read+write) MSHR misses 1952system.cpu1.icache.overall_mshr_misses::cpu1.inst 8745479 # number of overall MSHR misses 1953system.cpu1.icache.overall_mshr_misses::total 8745479 # number of overall MSHR misses 1954system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable 1955system.cpu1.icache.ReadReq_mshr_uncacheable::total 93 # number of ReadReq MSHR uncacheable 1956system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses 1957system.cpu1.icache.overall_mshr_uncacheable_misses::total 93 # number of overall MSHR uncacheable misses 1958system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 83895435000 # number of ReadReq MSHR miss cycles 1959system.cpu1.icache.ReadReq_mshr_miss_latency::total 83895435000 # number of ReadReq MSHR miss cycles 1960system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 83895435000 # number of demand (read+write) MSHR miss cycles 1961system.cpu1.icache.demand_mshr_miss_latency::total 83895435000 # number of demand (read+write) MSHR miss cycles 1962system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 83895435000 # number of overall MSHR miss cycles 1963system.cpu1.icache.overall_mshr_miss_latency::total 83895435000 # number of overall MSHR miss cycles 1964system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8450000 # number of ReadReq MSHR uncacheable cycles 1965system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8450000 # number of ReadReq MSHR uncacheable cycles 1966system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8450000 # number of overall MSHR uncacheable cycles 1967system.cpu1.icache.overall_mshr_uncacheable_latency::total 8450000 # number of overall MSHR uncacheable cycles 1968system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.039904 # mshr miss rate for ReadReq accesses 1969system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.039904 # mshr miss rate for ReadReq accesses 1970system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.039904 # mshr miss rate for demand accesses 1971system.cpu1.icache.demand_mshr_miss_rate::total 0.039904 # mshr miss rate for demand accesses 1972system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.039904 # mshr miss rate for overall accesses 1973system.cpu1.icache.overall_mshr_miss_rate::total 0.039904 # mshr miss rate for overall accesses 1974system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9593.006284 # average ReadReq mshr miss latency 1975system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9593.006284 # average ReadReq mshr miss latency 1976system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9593.006284 # average overall mshr miss latency 1977system.cpu1.icache.demand_avg_mshr_miss_latency::total 9593.006284 # average overall mshr miss latency 1978system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9593.006284 # average overall mshr miss latency 1979system.cpu1.icache.overall_avg_mshr_miss_latency::total 9593.006284 # average overall mshr miss latency 1980system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90860.215054 # average ReadReq mshr uncacheable latency 1981system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90860.215054 # average ReadReq mshr uncacheable latency 1982system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90860.215054 # average overall mshr uncacheable latency 1983system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90860.215054 # average overall mshr uncacheable latency 1984system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 1985system.cpu1.l2cache.prefetcher.num_hwpf_issued 6641051 # number of hwpf issued 1986system.cpu1.l2cache.prefetcher.pfIdentified 6641093 # number of prefetch candidates identified 1987system.cpu1.l2cache.prefetcher.pfBufferHit 36 # number of redundant prefetches already in prefetch queue 1988system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1989system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1990system.cpu1.l2cache.prefetcher.pfSpanPage 796339 # number of prefetches not generated due to page crossing 1991system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 1992system.cpu1.l2cache.tags.replacements 2218428 # number of replacements 1993system.cpu1.l2cache.tags.tagsinuse 13419.558556 # Cycle average of tags in use 1994system.cpu1.l2cache.tags.total_refs 21617433 # Total number of references to valid blocks. 1995system.cpu1.l2cache.tags.sampled_refs 2233865 # Sample count of references to valid blocks. 1996system.cpu1.l2cache.tags.avg_refs 9.677144 # Average number of references to valid blocks. 1997system.cpu1.l2cache.tags.warmup_cycle 10005238958500 # Cycle when the warmup percentage was hit. 1998system.cpu1.l2cache.tags.occ_blocks::writebacks 12516.094704 # Average occupied blocks per requestor 1999system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 63.377354 # Average occupied blocks per requestor 2000system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 44.102544 # Average occupied blocks per requestor 2001system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 795.983954 # Average occupied blocks per requestor 2002system.cpu1.l2cache.tags.occ_percent::writebacks 0.763922 # Average percentage of cache occupancy 2003system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003868 # Average percentage of cache occupancy 2004system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.002692 # Average percentage of cache occupancy 2005system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.048583 # Average percentage of cache occupancy 2006system.cpu1.l2cache.tags.occ_percent::total 0.819065 # Average percentage of cache occupancy 2007system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1192 # Occupied blocks per task id 2008system.cpu1.l2cache.tags.occ_task_id_blocks::1023 81 # Occupied blocks per task id 2009system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14164 # Occupied blocks per task id 2010system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 158 # Occupied blocks per task id 2011system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 771 # Occupied blocks per task id 2012system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 263 # Occupied blocks per task id 2013system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id 2014system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 54 # Occupied blocks per task id 2015system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2016system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id 2017system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id 2018system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id 2019system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4872 # Occupied blocks per task id 2020system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6319 # Occupied blocks per task id 2021system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2682 # Occupied blocks per task id 2022system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.072754 # Percentage of cache occupancy per task id 2023system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004944 # Percentage of cache occupancy per task id 2024system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.864502 # Percentage of cache occupancy per task id 2025system.cpu1.l2cache.tags.tag_accesses 457671450 # Number of tag accesses 2026system.cpu1.l2cache.tags.data_accesses 457671450 # Number of data accesses 2027system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 2028system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 494400 # number of ReadReq hits 2029system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 160613 # number of ReadReq hits 2030system.cpu1.l2cache.ReadReq_hits::total 655013 # number of ReadReq hits 2031system.cpu1.l2cache.WritebackDirty_hits::writebacks 3026488 # number of WritebackDirty hits 2032system.cpu1.l2cache.WritebackDirty_hits::total 3026488 # number of WritebackDirty hits 2033system.cpu1.l2cache.WritebackClean_hits::writebacks 10527430 # number of WritebackClean hits 2034system.cpu1.l2cache.WritebackClean_hits::total 10527430 # number of WritebackClean hits 2035system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 434 # number of UpgradeReq hits 2036system.cpu1.l2cache.UpgradeReq_hits::total 434 # number of UpgradeReq hits 2037system.cpu1.l2cache.ReadExReq_hits::cpu1.data 789107 # number of ReadExReq hits 2038system.cpu1.l2cache.ReadExReq_hits::total 789107 # number of ReadExReq hits 2039system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8072877 # number of ReadCleanReq hits 2040system.cpu1.l2cache.ReadCleanReq_hits::total 8072877 # number of ReadCleanReq hits 2041system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2507088 # number of ReadSharedReq hits 2042system.cpu1.l2cache.ReadSharedReq_hits::total 2507088 # number of ReadSharedReq hits 2043system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 171056 # number of InvalidateReq hits 2044system.cpu1.l2cache.InvalidateReq_hits::total 171056 # number of InvalidateReq hits 2045system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 494400 # number of demand (read+write) hits 2046system.cpu1.l2cache.demand_hits::cpu1.itb.walker 160613 # number of demand (read+write) hits 2047system.cpu1.l2cache.demand_hits::cpu1.inst 8072877 # number of demand (read+write) hits 2048system.cpu1.l2cache.demand_hits::cpu1.data 3296195 # number of demand (read+write) hits 2049system.cpu1.l2cache.demand_hits::total 12024085 # number of demand (read+write) hits 2050system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 494400 # number of overall hits 2051system.cpu1.l2cache.overall_hits::cpu1.itb.walker 160613 # number of overall hits 2052system.cpu1.l2cache.overall_hits::cpu1.inst 8072877 # number of overall hits 2053system.cpu1.l2cache.overall_hits::cpu1.data 3296195 # number of overall hits 2054system.cpu1.l2cache.overall_hits::total 12024085 # number of overall hits 2055system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11721 # number of ReadReq misses 2056system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8689 # number of ReadReq misses 2057system.cpu1.l2cache.ReadReq_misses::total 20410 # number of ReadReq misses 2058system.cpu1.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses 2059system.cpu1.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses 2060system.cpu1.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses 2061system.cpu1.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses 2062system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 220631 # number of UpgradeReq misses 2063system.cpu1.l2cache.UpgradeReq_misses::total 220631 # number of UpgradeReq misses 2064system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 192879 # number of SCUpgradeReq misses 2065system.cpu1.l2cache.SCUpgradeReq_misses::total 192879 # number of SCUpgradeReq misses 2066system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 4 # number of SCUpgradeFailReq misses 2067system.cpu1.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses 2068system.cpu1.l2cache.ReadExReq_misses::cpu1.data 261966 # number of ReadExReq misses 2069system.cpu1.l2cache.ReadExReq_misses::total 261966 # number of ReadExReq misses 2070system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 672602 # number of ReadCleanReq misses 2071system.cpu1.l2cache.ReadCleanReq_misses::total 672602 # number of ReadCleanReq misses 2072system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 931427 # number of ReadSharedReq misses 2073system.cpu1.l2cache.ReadSharedReq_misses::total 931427 # number of ReadSharedReq misses 2074system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 242391 # number of InvalidateReq misses 2075system.cpu1.l2cache.InvalidateReq_misses::total 242391 # number of InvalidateReq misses 2076system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11721 # number of demand (read+write) misses 2077system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8689 # number of demand (read+write) misses 2078system.cpu1.l2cache.demand_misses::cpu1.inst 672602 # number of demand (read+write) misses 2079system.cpu1.l2cache.demand_misses::cpu1.data 1193393 # number of demand (read+write) misses 2080system.cpu1.l2cache.demand_misses::total 1886405 # number of demand (read+write) misses 2081system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11721 # number of overall misses 2082system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8689 # number of overall misses 2083system.cpu1.l2cache.overall_misses::cpu1.inst 672602 # number of overall misses 2084system.cpu1.l2cache.overall_misses::cpu1.data 1193393 # number of overall misses 2085system.cpu1.l2cache.overall_misses::total 1886405 # number of overall misses 2086system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 429270500 # number of ReadReq miss cycles 2087system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 326619000 # number of ReadReq miss cycles 2088system.cpu1.l2cache.ReadReq_miss_latency::total 755889500 # number of ReadReq miss cycles 2089system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 1918862500 # number of UpgradeReq miss cycles 2090system.cpu1.l2cache.UpgradeReq_miss_latency::total 1918862500 # number of UpgradeReq miss cycles 2091system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1442678000 # number of SCUpgradeReq miss cycles 2092system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1442678000 # number of SCUpgradeReq miss cycles 2093system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2273499 # number of SCUpgradeFailReq miss cycles 2094system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2273499 # number of SCUpgradeFailReq miss cycles 2095system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10385042497 # number of ReadExReq miss cycles 2096system.cpu1.l2cache.ReadExReq_miss_latency::total 10385042497 # number of ReadExReq miss cycles 2097system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 22017991000 # number of ReadCleanReq miss cycles 2098system.cpu1.l2cache.ReadCleanReq_miss_latency::total 22017991000 # number of ReadCleanReq miss cycles 2099system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 30592821494 # number of ReadSharedReq miss cycles 2100system.cpu1.l2cache.ReadSharedReq_miss_latency::total 30592821494 # number of ReadSharedReq miss cycles 2101system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 352126000 # number of InvalidateReq miss cycles 2102system.cpu1.l2cache.InvalidateReq_miss_latency::total 352126000 # number of InvalidateReq miss cycles 2103system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 429270500 # number of demand (read+write) miss cycles 2104system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 326619000 # number of demand (read+write) miss cycles 2105system.cpu1.l2cache.demand_miss_latency::cpu1.inst 22017991000 # number of demand (read+write) miss cycles 2106system.cpu1.l2cache.demand_miss_latency::cpu1.data 40977863991 # number of demand (read+write) miss cycles 2107system.cpu1.l2cache.demand_miss_latency::total 63751744491 # number of demand (read+write) miss cycles 2108system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 429270500 # number of overall miss cycles 2109system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 326619000 # number of overall miss cycles 2110system.cpu1.l2cache.overall_miss_latency::cpu1.inst 22017991000 # number of overall miss cycles 2111system.cpu1.l2cache.overall_miss_latency::cpu1.data 40977863991 # number of overall miss cycles 2112system.cpu1.l2cache.overall_miss_latency::total 63751744491 # number of overall miss cycles 2113system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 506121 # number of ReadReq accesses(hits+misses) 2114system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 169302 # number of ReadReq accesses(hits+misses) 2115system.cpu1.l2cache.ReadReq_accesses::total 675423 # number of ReadReq accesses(hits+misses) 2116system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3026489 # number of WritebackDirty accesses(hits+misses) 2117system.cpu1.l2cache.WritebackDirty_accesses::total 3026489 # number of WritebackDirty accesses(hits+misses) 2118system.cpu1.l2cache.WritebackClean_accesses::writebacks 10527431 # number of WritebackClean accesses(hits+misses) 2119system.cpu1.l2cache.WritebackClean_accesses::total 10527431 # number of WritebackClean accesses(hits+misses) 2120system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 221065 # number of UpgradeReq accesses(hits+misses) 2121system.cpu1.l2cache.UpgradeReq_accesses::total 221065 # number of UpgradeReq accesses(hits+misses) 2122system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 192879 # number of SCUpgradeReq accesses(hits+misses) 2123system.cpu1.l2cache.SCUpgradeReq_accesses::total 192879 # number of SCUpgradeReq accesses(hits+misses) 2124system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 4 # number of SCUpgradeFailReq accesses(hits+misses) 2125system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) 2126system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1051073 # number of ReadExReq accesses(hits+misses) 2127system.cpu1.l2cache.ReadExReq_accesses::total 1051073 # number of ReadExReq accesses(hits+misses) 2128system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 8745479 # number of ReadCleanReq accesses(hits+misses) 2129system.cpu1.l2cache.ReadCleanReq_accesses::total 8745479 # number of ReadCleanReq accesses(hits+misses) 2130system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3438515 # number of ReadSharedReq accesses(hits+misses) 2131system.cpu1.l2cache.ReadSharedReq_accesses::total 3438515 # number of ReadSharedReq accesses(hits+misses) 2132system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 413447 # number of InvalidateReq accesses(hits+misses) 2133system.cpu1.l2cache.InvalidateReq_accesses::total 413447 # number of InvalidateReq accesses(hits+misses) 2134system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 506121 # number of demand (read+write) accesses 2135system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 169302 # number of demand (read+write) accesses 2136system.cpu1.l2cache.demand_accesses::cpu1.inst 8745479 # number of demand (read+write) accesses 2137system.cpu1.l2cache.demand_accesses::cpu1.data 4489588 # number of demand (read+write) accesses 2138system.cpu1.l2cache.demand_accesses::total 13910490 # number of demand (read+write) accesses 2139system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 506121 # number of overall (read+write) accesses 2140system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 169302 # number of overall (read+write) accesses 2141system.cpu1.l2cache.overall_accesses::cpu1.inst 8745479 # number of overall (read+write) accesses 2142system.cpu1.l2cache.overall_accesses::cpu1.data 4489588 # number of overall (read+write) accesses 2143system.cpu1.l2cache.overall_accesses::total 13910490 # number of overall (read+write) accesses 2144system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.023158 # miss rate for ReadReq accesses 2145system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.051322 # miss rate for ReadReq accesses 2146system.cpu1.l2cache.ReadReq_miss_rate::total 0.030218 # miss rate for ReadReq accesses 2147system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000000 # miss rate for WritebackDirty accesses 2148system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000000 # miss rate for WritebackDirty accesses 2149system.cpu1.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses 2150system.cpu1.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses 2151system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.998037 # miss rate for UpgradeReq accesses 2152system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.998037 # miss rate for UpgradeReq accesses 2153system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2154system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2155system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2156system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2157system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.249237 # miss rate for ReadExReq accesses 2158system.cpu1.l2cache.ReadExReq_miss_rate::total 0.249237 # miss rate for ReadExReq accesses 2159system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.076909 # miss rate for ReadCleanReq accesses 2160system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.076909 # miss rate for ReadCleanReq accesses 2161system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.270881 # miss rate for ReadSharedReq accesses 2162system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.270881 # miss rate for ReadSharedReq accesses 2163system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.586269 # miss rate for InvalidateReq accesses 2164system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.586269 # miss rate for InvalidateReq accesses 2165system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.023158 # miss rate for demand accesses 2166system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.051322 # miss rate for demand accesses 2167system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.076909 # miss rate for demand accesses 2168system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.265813 # miss rate for demand accesses 2169system.cpu1.l2cache.demand_miss_rate::total 0.135610 # miss rate for demand accesses 2170system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.023158 # miss rate for overall accesses 2171system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.051322 # miss rate for overall accesses 2172system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.076909 # miss rate for overall accesses 2173system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.265813 # miss rate for overall accesses 2174system.cpu1.l2cache.overall_miss_rate::total 0.135610 # miss rate for overall accesses 2175system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 36624.050849 # average ReadReq miss latency 2176system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 37589.941305 # average ReadReq miss latency 2177system.cpu1.l2cache.ReadReq_avg_miss_latency::total 37035.252327 # average ReadReq miss latency 2178system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 8697.157244 # average UpgradeReq miss latency 2179system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 8697.157244 # average UpgradeReq miss latency 2180system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 7479.704893 # average SCUpgradeReq miss latency 2181system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 7479.704893 # average SCUpgradeReq miss latency 2182system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 568374.750000 # average SCUpgradeFailReq miss latency 2183system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 568374.750000 # average SCUpgradeFailReq miss latency 2184system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39642.711256 # average ReadExReq miss latency 2185system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39642.711256 # average ReadExReq miss latency 2186system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 32735.541970 # average ReadCleanReq miss latency 2187system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 32735.541970 # average ReadCleanReq miss latency 2188system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 32845.109165 # average ReadSharedReq miss latency 2189system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 32845.109165 # average ReadSharedReq miss latency 2190system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1452.718954 # average InvalidateReq miss latency 2191system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1452.718954 # average InvalidateReq miss latency 2192system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 36624.050849 # average overall miss latency 2193system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 37589.941305 # average overall miss latency 2194system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 32735.541970 # average overall miss latency 2195system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34337.275307 # average overall miss latency 2196system.cpu1.l2cache.demand_avg_miss_latency::total 33795.364458 # average overall miss latency 2197system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 36624.050849 # average overall miss latency 2198system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 37589.941305 # average overall miss latency 2199system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 32735.541970 # average overall miss latency 2200system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34337.275307 # average overall miss latency 2201system.cpu1.l2cache.overall_avg_miss_latency::total 33795.364458 # average overall miss latency 2202system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2203system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2204system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2205system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2206system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2207system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2208system.cpu1.l2cache.unused_prefetches 43661 # number of HardPF blocks evicted w/o reference 2209system.cpu1.l2cache.writebacks::writebacks 1101410 # number of writebacks 2210system.cpu1.l2cache.writebacks::total 1101410 # number of writebacks 2211system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits 2212system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 2 # number of ReadReq MSHR hits 2213system.cpu1.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits 2214system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 4694 # number of ReadExReq MSHR hits 2215system.cpu1.l2cache.ReadExReq_mshr_hits::total 4694 # number of ReadExReq MSHR hits 2216system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 3 # number of ReadCleanReq MSHR hits 2217system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits 2218system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 558 # number of ReadSharedReq MSHR hits 2219system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 558 # number of ReadSharedReq MSHR hits 2220system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits 2221system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 2 # number of demand (read+write) MSHR hits 2222system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits 2223system.cpu1.l2cache.demand_mshr_hits::cpu1.data 5252 # number of demand (read+write) MSHR hits 2224system.cpu1.l2cache.demand_mshr_hits::total 5258 # number of demand (read+write) MSHR hits 2225system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits 2226system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 2 # number of overall MSHR hits 2227system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits 2228system.cpu1.l2cache.overall_mshr_hits::cpu1.data 5252 # number of overall MSHR hits 2229system.cpu1.l2cache.overall_mshr_hits::total 5258 # number of overall MSHR hits 2230system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 11720 # number of ReadReq MSHR misses 2231system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8687 # number of ReadReq MSHR misses 2232system.cpu1.l2cache.ReadReq_mshr_misses::total 20407 # number of ReadReq MSHR misses 2233system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 1 # number of WritebackDirty MSHR misses 2234system.cpu1.l2cache.WritebackDirty_mshr_misses::total 1 # number of WritebackDirty MSHR misses 2235system.cpu1.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses 2236system.cpu1.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses 2237system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 709103 # number of HardPFReq MSHR misses 2238system.cpu1.l2cache.HardPFReq_mshr_misses::total 709103 # number of HardPFReq MSHR misses 2239system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 220631 # number of UpgradeReq MSHR misses 2240system.cpu1.l2cache.UpgradeReq_mshr_misses::total 220631 # number of UpgradeReq MSHR misses 2241system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 192879 # number of SCUpgradeReq MSHR misses 2242system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 192879 # number of SCUpgradeReq MSHR misses 2243system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 4 # number of SCUpgradeFailReq MSHR misses 2244system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses 2245system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 257272 # number of ReadExReq MSHR misses 2246system.cpu1.l2cache.ReadExReq_mshr_misses::total 257272 # number of ReadExReq MSHR misses 2247system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 672599 # number of ReadCleanReq MSHR misses 2248system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 672599 # number of ReadCleanReq MSHR misses 2249system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 930869 # number of ReadSharedReq MSHR misses 2250system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 930869 # number of ReadSharedReq MSHR misses 2251system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 242391 # number of InvalidateReq MSHR misses 2252system.cpu1.l2cache.InvalidateReq_mshr_misses::total 242391 # number of InvalidateReq MSHR misses 2253system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 11720 # number of demand (read+write) MSHR misses 2254system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8687 # number of demand (read+write) MSHR misses 2255system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 672599 # number of demand (read+write) MSHR misses 2256system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1188141 # number of demand (read+write) MSHR misses 2257system.cpu1.l2cache.demand_mshr_misses::total 1881147 # number of demand (read+write) MSHR misses 2258system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 11720 # number of overall MSHR misses 2259system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8687 # number of overall MSHR misses 2260system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 672599 # number of overall MSHR misses 2261system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1188141 # number of overall MSHR misses 2262system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 709103 # number of overall MSHR misses 2263system.cpu1.l2cache.overall_mshr_misses::total 2590250 # number of overall MSHR misses 2264system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable 2265system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 6941 # number of ReadReq MSHR uncacheable 2266system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 7034 # number of ReadReq MSHR uncacheable 2267system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 7280 # number of WriteReq MSHR uncacheable 2268system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 7280 # number of WriteReq MSHR uncacheable 2269system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses 2270system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 14221 # number of overall MSHR uncacheable misses 2271system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 14314 # number of overall MSHR uncacheable misses 2272system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 358927500 # number of ReadReq MSHR miss cycles 2273system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 274457000 # number of ReadReq MSHR miss cycles 2274system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 633384500 # number of ReadReq MSHR miss cycles 2275system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 25470013765 # number of HardPFReq MSHR miss cycles 2276system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 25470013765 # number of HardPFReq MSHR miss cycles 2277system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4591069994 # number of UpgradeReq MSHR miss cycles 2278system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4591069994 # number of UpgradeReq MSHR miss cycles 2279system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3129353001 # number of SCUpgradeReq MSHR miss cycles 2280system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3129353001 # number of SCUpgradeReq MSHR miss cycles 2281system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2003499 # number of SCUpgradeFailReq MSHR miss cycles 2282system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2003499 # number of SCUpgradeFailReq MSHR miss cycles 2283system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8263742497 # number of ReadExReq MSHR miss cycles 2284system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8263742497 # number of ReadExReq MSHR miss cycles 2285system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 17982320500 # number of ReadCleanReq MSHR miss cycles 2286system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 17982320500 # number of ReadCleanReq MSHR miss cycles 2287system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 24961268994 # number of ReadSharedReq MSHR miss cycles 2288system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 24961268994 # number of ReadSharedReq MSHR miss cycles 2289system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6347282500 # number of InvalidateReq MSHR miss cycles 2290system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6347282500 # number of InvalidateReq MSHR miss cycles 2291system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 358927500 # number of demand (read+write) MSHR miss cycles 2292system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 274457000 # number of demand (read+write) MSHR miss cycles 2293system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 17982320500 # number of demand (read+write) MSHR miss cycles 2294system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 33225011491 # number of demand (read+write) MSHR miss cycles 2295system.cpu1.l2cache.demand_mshr_miss_latency::total 51840716491 # number of demand (read+write) MSHR miss cycles 2296system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 358927500 # number of overall MSHR miss cycles 2297system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 274457000 # number of overall MSHR miss cycles 2298system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 17982320500 # number of overall MSHR miss cycles 2299system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 33225011491 # number of overall MSHR miss cycles 2300system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 25470013765 # number of overall MSHR miss cycles 2301system.cpu1.l2cache.overall_mshr_miss_latency::total 77310730256 # number of overall MSHR miss cycles 2302system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7706000 # number of ReadReq MSHR uncacheable cycles 2303system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 781601000 # number of ReadReq MSHR uncacheable cycles 2304system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 789307000 # number of ReadReq MSHR uncacheable cycles 2305system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7706000 # number of overall MSHR uncacheable cycles 2306system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 781601000 # number of overall MSHR uncacheable cycles 2307system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 789307000 # number of overall MSHR uncacheable cycles 2308system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023157 # mshr miss rate for ReadReq accesses 2309system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.051311 # mshr miss rate for ReadReq accesses 2310system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.030214 # mshr miss rate for ReadReq accesses 2311system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackDirty accesses 2312system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackDirty accesses 2313system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses 2314system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses 2315system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2316system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2317system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.998037 # mshr miss rate for UpgradeReq accesses 2318system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.998037 # mshr miss rate for UpgradeReq accesses 2319system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2320system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2321system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2322system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2323system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.244771 # mshr miss rate for ReadExReq accesses 2324system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.244771 # mshr miss rate for ReadExReq accesses 2325system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.076908 # mshr miss rate for ReadCleanReq accesses 2326system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.076908 # mshr miss rate for ReadCleanReq accesses 2327system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.270718 # mshr miss rate for ReadSharedReq accesses 2328system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.270718 # mshr miss rate for ReadSharedReq accesses 2329system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.586269 # mshr miss rate for InvalidateReq accesses 2330system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.586269 # mshr miss rate for InvalidateReq accesses 2331system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023157 # mshr miss rate for demand accesses 2332system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.051311 # mshr miss rate for demand accesses 2333system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.076908 # mshr miss rate for demand accesses 2334system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.264644 # mshr miss rate for demand accesses 2335system.cpu1.l2cache.demand_mshr_miss_rate::total 0.135232 # mshr miss rate for demand accesses 2336system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023157 # mshr miss rate for overall accesses 2337system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.051311 # mshr miss rate for overall accesses 2338system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.076908 # mshr miss rate for overall accesses 2339system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.264644 # mshr miss rate for overall accesses 2340system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2341system.cpu1.l2cache.overall_mshr_miss_rate::total 0.186208 # mshr miss rate for overall accesses 2342system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 30625.213311 # average ReadReq mshr miss latency 2343system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31593.991021 # average ReadReq mshr miss latency 2344system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 31037.609644 # average ReadReq mshr miss latency 2345system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35918.637723 # average HardPFReq mshr miss latency 2346system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35918.637723 # average HardPFReq mshr miss latency 2347system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20808.816504 # average UpgradeReq mshr miss latency 2348system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20808.816504 # average UpgradeReq mshr miss latency 2349system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16224.436051 # average SCUpgradeReq mshr miss latency 2350system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16224.436051 # average SCUpgradeReq mshr miss latency 2351system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 500874.750000 # average SCUpgradeFailReq mshr miss latency 2352system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 500874.750000 # average SCUpgradeFailReq mshr miss latency 2353system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32120.644676 # average ReadExReq mshr miss latency 2354system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32120.644676 # average ReadExReq mshr miss latency 2355system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 26735.574243 # average ReadCleanReq mshr miss latency 2356system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 26735.574243 # average ReadCleanReq mshr miss latency 2357system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 26815.018004 # average ReadSharedReq mshr miss latency 2358system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26815.018004 # average ReadSharedReq mshr miss latency 2359system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26186.131086 # average InvalidateReq mshr miss latency 2360system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26186.131086 # average InvalidateReq mshr miss latency 2361system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 30625.213311 # average overall mshr miss latency 2362system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31593.991021 # average overall mshr miss latency 2363system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26735.574243 # average overall mshr miss latency 2364system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27963.862446 # average overall mshr miss latency 2365system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27558.035864 # average overall mshr miss latency 2366system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 30625.213311 # average overall mshr miss latency 2367system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31593.991021 # average overall mshr miss latency 2368system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26735.574243 # average overall mshr miss latency 2369system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27963.862446 # average overall mshr miss latency 2370system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35918.637723 # average overall mshr miss latency 2371system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29846.821834 # average overall mshr miss latency 2372system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 82860.215054 # average ReadReq mshr uncacheable latency 2373system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 112606.396773 # average ReadReq mshr uncacheable latency 2374system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 112213.107762 # average ReadReq mshr uncacheable latency 2375system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 82860.215054 # average overall mshr uncacheable latency 2376system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 54961.043527 # average overall mshr uncacheable latency 2377system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 55142.308230 # average overall mshr uncacheable latency 2378system.cpu1.toL2Bus.snoop_filter.tot_requests 27911552 # Total number of requests made to the snoop filter. 2379system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14263179 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2380system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1909 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2381system.cpu1.toL2Bus.snoop_filter.tot_snoops 2035614 # Total number of snoops made to the snoop filter. 2382system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2035313 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2383system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 301 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2384system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 2385system.cpu1.toL2Bus.trans_dist::ReadReq 755700 # Transaction distribution 2386system.cpu1.toL2Bus.trans_dist::ReadResp 13030335 # Transaction distribution 2387system.cpu1.toL2Bus.trans_dist::WriteReq 7280 # Transaction distribution 2388system.cpu1.toL2Bus.trans_dist::WriteResp 7280 # Transaction distribution 2389system.cpu1.toL2Bus.trans_dist::WritebackDirty 4134671 # Transaction distribution 2390system.cpu1.toL2Bus.trans_dist::WritebackClean 10529340 # Transaction distribution 2391system.cpu1.toL2Bus.trans_dist::CleanEvict 2783515 # Transaction distribution 2392system.cpu1.toL2Bus.trans_dist::HardPFReq 903944 # Transaction distribution 2393system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 2394system.cpu1.toL2Bus.trans_dist::UpgradeReq 426493 # Transaction distribution 2395system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 348519 # Transaction distribution 2396system.cpu1.toL2Bus.trans_dist::UpgradeResp 477830 # Transaction distribution 2397system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 70 # Transaction distribution 2398system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution 2399system.cpu1.toL2Bus.trans_dist::ReadExReq 1080105 # Transaction distribution 2400system.cpu1.toL2Bus.trans_dist::ReadExResp 1057121 # Transaction distribution 2401system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8745479 # Transaction distribution 2402system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4495606 # Transaction distribution 2403system.cpu1.toL2Bus.trans_dist::InvalidateReq 466229 # Transaction distribution 2404system.cpu1.toL2Bus.trans_dist::InvalidateResp 413447 # Transaction distribution 2405system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 26236111 # Packet count per connected master and slave (bytes) 2406system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15633953 # Packet count per connected master and slave (bytes) 2407system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 355051 # Packet count per connected master and slave (bytes) 2408system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1069038 # Packet count per connected master and slave (bytes) 2409system.cpu1.toL2Bus.pkt_count::total 43294153 # Packet count per connected master and slave (bytes) 2410system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1119394496 # Cumulative packet size per connected master and slave (bytes) 2411system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 601463021 # Cumulative packet size per connected master and slave (bytes) 2412system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1354416 # Cumulative packet size per connected master and slave (bytes) 2413system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4048968 # Cumulative packet size per connected master and slave (bytes) 2414system.cpu1.toL2Bus.pkt_size::total 1726260901 # Cumulative packet size per connected master and slave (bytes) 2415system.cpu1.toL2Bus.snoops 6529606 # Total snoops (count) 2416system.cpu1.toL2Bus.snoop_fanout::samples 21121122 # Request fanout histogram 2417system.cpu1.toL2Bus.snoop_fanout::mean 0.110367 # Request fanout histogram 2418system.cpu1.toL2Bus.snoop_fanout::stdev 0.313393 # Request fanout histogram 2419system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2420system.cpu1.toL2Bus.snoop_fanout::0 18790338 88.96% 88.96% # Request fanout histogram 2421system.cpu1.toL2Bus.snoop_fanout::1 2330483 11.03% 100.00% # Request fanout histogram 2422system.cpu1.toL2Bus.snoop_fanout::2 301 0.00% 100.00% # Request fanout histogram 2423system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2424system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2425system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2426system.cpu1.toL2Bus.snoop_fanout::total 21121122 # Request fanout histogram 2427system.cpu1.toL2Bus.reqLayer0.occupancy 27750114484 # Layer occupancy (ticks) 2428system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2429system.cpu1.toL2Bus.snoopLayer0.occupancy 177306545 # Layer occupancy (ticks) 2430system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2431system.cpu1.toL2Bus.respLayer0.occupancy 13121677843 # Layer occupancy (ticks) 2432system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2433system.cpu1.toL2Bus.respLayer1.occupancy 7163335235 # Layer occupancy (ticks) 2434system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2435system.cpu1.toL2Bus.respLayer2.occupancy 185802393 # Layer occupancy (ticks) 2436system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2437system.cpu1.toL2Bus.respLayer3.occupancy 563017795 # Layer occupancy (ticks) 2438system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2439system.iobus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 2440system.iobus.trans_dist::ReadReq 40337 # Transaction distribution 2441system.iobus.trans_dist::ReadResp 40337 # Transaction distribution 2442system.iobus.trans_dist::WriteReq 136616 # Transaction distribution 2443system.iobus.trans_dist::WriteResp 136616 # Transaction distribution 2444system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47664 # Packet count per connected master and slave (bytes) 2445system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2446system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2447system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2448system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2449system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2450system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2451system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2452system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2453system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2454system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2455system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 2456system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 2457system.iobus.pkt_count_system.bridge.master::total 122598 # Packet count per connected master and slave (bytes) 2458system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231228 # Packet count per connected master and slave (bytes) 2459system.iobus.pkt_count_system.realview.ide.dma::total 231228 # Packet count per connected master and slave (bytes) 2460system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2461system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 2462system.iobus.pkt_count::total 353906 # Packet count per connected master and slave (bytes) 2463system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47684 # Cumulative packet size per connected master and slave (bytes) 2464system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2465system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 2466system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2467system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2468system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2469system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2470system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2471system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2472system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2473system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2474system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 2475system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 2476system.iobus.pkt_size_system.bridge.master::total 155705 # Cumulative packet size per connected master and slave (bytes) 2477system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338928 # Cumulative packet size per connected master and slave (bytes) 2478system.iobus.pkt_size_system.realview.ide.dma::total 7338928 # Cumulative packet size per connected master and slave (bytes) 2479system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2480system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 2481system.iobus.pkt_size::total 7496719 # Cumulative packet size per connected master and slave (bytes) 2482system.iobus.reqLayer0.occupancy 43180502 # Layer occupancy (ticks) 2483system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2484system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) 2485system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2486system.iobus.reqLayer2.occupancy 324000 # Layer occupancy (ticks) 2487system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2488system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 2489system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2490system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks) 2491system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2492system.iobus.reqLayer10.occupancy 9000 # Layer occupancy (ticks) 2493system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2494system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) 2495system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2496system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 2497system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2498system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) 2499system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2500system.iobus.reqLayer16.occupancy 15500 # Layer occupancy (ticks) 2501system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2502system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 2503system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2504system.iobus.reqLayer23.occupancy 25595502 # Layer occupancy (ticks) 2505system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2506system.iobus.reqLayer24.occupancy 36402501 # Layer occupancy (ticks) 2507system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2508system.iobus.reqLayer25.occupancy 569469754 # Layer occupancy (ticks) 2509system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2510system.iobus.respLayer0.occupancy 92713000 # Layer occupancy (ticks) 2511system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2512system.iobus.respLayer3.occupancy 147924000 # Layer occupancy (ticks) 2513system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2514system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 2515system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 2516system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 2517system.iocache.tags.replacements 115611 # number of replacements 2518system.iocache.tags.tagsinuse 11.284790 # Cycle average of tags in use 2519system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 2520system.iocache.tags.sampled_refs 115627 # Sample count of references to valid blocks. 2521system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 2522system.iocache.tags.warmup_cycle 9167417766000 # Cycle when the warmup percentage was hit. 2523system.iocache.tags.occ_blocks::realview.ethernet 7.418888 # Average occupied blocks per requestor 2524system.iocache.tags.occ_blocks::realview.ide 3.865902 # Average occupied blocks per requestor 2525system.iocache.tags.occ_percent::realview.ethernet 0.463681 # Average percentage of cache occupancy 2526system.iocache.tags.occ_percent::realview.ide 0.241619 # Average percentage of cache occupancy 2527system.iocache.tags.occ_percent::total 0.705299 # Average percentage of cache occupancy 2528system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2529system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2530system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2531system.iocache.tags.tag_accesses 1040883 # Number of tag accesses 2532system.iocache.tags.data_accesses 1040883 # Number of data accesses 2533system.iocache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 2534system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2535system.iocache.ReadReq_misses::realview.ide 8886 # number of ReadReq misses 2536system.iocache.ReadReq_misses::total 8923 # number of ReadReq misses 2537system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2538system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2539system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 2540system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 2541system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 2542system.iocache.demand_misses::realview.ide 115614 # number of demand (read+write) misses 2543system.iocache.demand_misses::total 115654 # number of demand (read+write) misses 2544system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 2545system.iocache.overall_misses::realview.ide 115614 # number of overall misses 2546system.iocache.overall_misses::total 115654 # number of overall misses 2547system.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles 2548system.iocache.ReadReq_miss_latency::realview.ide 1668794518 # number of ReadReq miss cycles 2549system.iocache.ReadReq_miss_latency::total 1673992518 # number of ReadReq miss cycles 2550system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 2551system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 2552system.iocache.WriteLineReq_miss_latency::realview.ide 12857701236 # number of WriteLineReq miss cycles 2553system.iocache.WriteLineReq_miss_latency::total 12857701236 # number of WriteLineReq miss cycles 2554system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles 2555system.iocache.demand_miss_latency::realview.ide 14526495754 # number of demand (read+write) miss cycles 2556system.iocache.demand_miss_latency::total 14532062754 # number of demand (read+write) miss cycles 2557system.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles 2558system.iocache.overall_miss_latency::realview.ide 14526495754 # number of overall miss cycles 2559system.iocache.overall_miss_latency::total 14532062754 # number of overall miss cycles 2560system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 2561system.iocache.ReadReq_accesses::realview.ide 8886 # number of ReadReq accesses(hits+misses) 2562system.iocache.ReadReq_accesses::total 8923 # number of ReadReq accesses(hits+misses) 2563system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2564system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2565system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 2566system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 2567system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 2568system.iocache.demand_accesses::realview.ide 115614 # number of demand (read+write) accesses 2569system.iocache.demand_accesses::total 115654 # number of demand (read+write) accesses 2570system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 2571system.iocache.overall_accesses::realview.ide 115614 # number of overall (read+write) accesses 2572system.iocache.overall_accesses::total 115654 # number of overall (read+write) accesses 2573system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2574system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2575system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2576system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2577system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2578system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2579system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2580system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2581system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2582system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2583system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2584system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2585system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2586system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency 2587system.iocache.ReadReq_avg_miss_latency::realview.ide 187800.418411 # average ReadReq miss latency 2588system.iocache.ReadReq_avg_miss_latency::total 187604.227054 # average ReadReq miss latency 2589system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 2590system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 2591system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120471.677873 # average WriteLineReq miss latency 2592system.iocache.WriteLineReq_avg_miss_latency::total 120471.677873 # average WriteLineReq miss latency 2593system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency 2594system.iocache.demand_avg_miss_latency::realview.ide 125646.511270 # average overall miss latency 2595system.iocache.demand_avg_miss_latency::total 125651.190223 # average overall miss latency 2596system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency 2597system.iocache.overall_avg_miss_latency::realview.ide 125646.511270 # average overall miss latency 2598system.iocache.overall_avg_miss_latency::total 125651.190223 # average overall miss latency 2599system.iocache.blocked_cycles::no_mshrs 33480 # number of cycles access was blocked 2600system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2601system.iocache.blocked::no_mshrs 3531 # number of cycles access was blocked 2602system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2603system.iocache.avg_blocked_cycles::no_mshrs 9.481733 # average number of cycles each access was blocked 2604system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2605system.iocache.writebacks::writebacks 106695 # number of writebacks 2606system.iocache.writebacks::total 106695 # number of writebacks 2607system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 2608system.iocache.ReadReq_mshr_misses::realview.ide 8886 # number of ReadReq MSHR misses 2609system.iocache.ReadReq_mshr_misses::total 8923 # number of ReadReq MSHR misses 2610system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2611system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2612system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 2613system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 2614system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 2615system.iocache.demand_mshr_misses::realview.ide 115614 # number of demand (read+write) MSHR misses 2616system.iocache.demand_mshr_misses::total 115654 # number of demand (read+write) MSHR misses 2617system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 2618system.iocache.overall_mshr_misses::realview.ide 115614 # number of overall MSHR misses 2619system.iocache.overall_mshr_misses::total 115654 # number of overall MSHR misses 2620system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles 2621system.iocache.ReadReq_mshr_miss_latency::realview.ide 1224494518 # number of ReadReq MSHR miss cycles 2622system.iocache.ReadReq_mshr_miss_latency::total 1227842518 # number of ReadReq MSHR miss cycles 2623system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 2624system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 2625system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7512769435 # number of WriteLineReq MSHR miss cycles 2626system.iocache.WriteLineReq_mshr_miss_latency::total 7512769435 # number of WriteLineReq MSHR miss cycles 2627system.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles 2628system.iocache.demand_mshr_miss_latency::realview.ide 8737263953 # number of demand (read+write) MSHR miss cycles 2629system.iocache.demand_mshr_miss_latency::total 8740830953 # number of demand (read+write) MSHR miss cycles 2630system.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles 2631system.iocache.overall_mshr_miss_latency::realview.ide 8737263953 # number of overall MSHR miss cycles 2632system.iocache.overall_mshr_miss_latency::total 8740830953 # number of overall MSHR miss cycles 2633system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2634system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2635system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2636system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2637system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2638system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2639system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2640system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 2641system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2642system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2643system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 2644system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2645system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2646system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency 2647system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137800.418411 # average ReadReq mshr miss latency 2648system.iocache.ReadReq_avg_mshr_miss_latency::total 137604.227054 # average ReadReq mshr miss latency 2649system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 2650system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 2651system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70391.738204 # average WriteLineReq mshr miss latency 2652system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70391.738204 # average WriteLineReq mshr miss latency 2653system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency 2654system.iocache.demand_avg_mshr_miss_latency::realview.ide 75572.715701 # average overall mshr miss latency 2655system.iocache.demand_avg_mshr_miss_latency::total 75577.420176 # average overall mshr miss latency 2656system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency 2657system.iocache.overall_avg_mshr_miss_latency::realview.ide 75572.715701 # average overall mshr miss latency 2658system.iocache.overall_avg_mshr_miss_latency::total 75577.420176 # average overall mshr miss latency 2659system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 2660system.l2c.tags.replacements 1371243 # number of replacements 2661system.l2c.tags.tagsinuse 63411.869664 # Cycle average of tags in use 2662system.l2c.tags.total_refs 6460055 # Total number of references to valid blocks. 2663system.l2c.tags.sampled_refs 1430877 # Sample count of references to valid blocks. 2664system.l2c.tags.avg_refs 4.514752 # Average number of references to valid blocks. 2665system.l2c.tags.warmup_cycle 7876910500 # Cycle when the warmup percentage was hit. 2666system.l2c.tags.occ_blocks::writebacks 21329.379338 # Average occupied blocks per requestor 2667system.l2c.tags.occ_blocks::cpu0.dtb.walker 243.549056 # Average occupied blocks per requestor 2668system.l2c.tags.occ_blocks::cpu0.itb.walker 346.213430 # Average occupied blocks per requestor 2669system.l2c.tags.occ_blocks::cpu0.inst 5332.164924 # Average occupied blocks per requestor 2670system.l2c.tags.occ_blocks::cpu0.data 9972.711960 # Average occupied blocks per requestor 2671system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14780.287325 # Average occupied blocks per requestor 2672system.l2c.tags.occ_blocks::cpu1.dtb.walker 85.709675 # Average occupied blocks per requestor 2673system.l2c.tags.occ_blocks::cpu1.itb.walker 92.474711 # Average occupied blocks per requestor 2674system.l2c.tags.occ_blocks::cpu1.inst 3611.694384 # Average occupied blocks per requestor 2675system.l2c.tags.occ_blocks::cpu1.data 3808.494767 # Average occupied blocks per requestor 2676system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3809.190093 # Average occupied blocks per requestor 2677system.l2c.tags.occ_percent::writebacks 0.325461 # Average percentage of cache occupancy 2678system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003716 # Average percentage of cache occupancy 2679system.l2c.tags.occ_percent::cpu0.itb.walker 0.005283 # Average percentage of cache occupancy 2680system.l2c.tags.occ_percent::cpu0.inst 0.081362 # Average percentage of cache occupancy 2681system.l2c.tags.occ_percent::cpu0.data 0.152172 # Average percentage of cache occupancy 2682system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.225529 # Average percentage of cache occupancy 2683system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001308 # Average percentage of cache occupancy 2684system.l2c.tags.occ_percent::cpu1.itb.walker 0.001411 # Average percentage of cache occupancy 2685system.l2c.tags.occ_percent::cpu1.inst 0.055110 # Average percentage of cache occupancy 2686system.l2c.tags.occ_percent::cpu1.data 0.058113 # Average percentage of cache occupancy 2687system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.058124 # Average percentage of cache occupancy 2688system.l2c.tags.occ_percent::total 0.967588 # Average percentage of cache occupancy 2689system.l2c.tags.occ_task_id_blocks::1022 9222 # Occupied blocks per task id 2690system.l2c.tags.occ_task_id_blocks::1023 255 # Occupied blocks per task id 2691system.l2c.tags.occ_task_id_blocks::1024 50157 # Occupied blocks per task id 2692system.l2c.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id 2693system.l2c.tags.age_task_id_blocks_1022::2 98 # Occupied blocks per task id 2694system.l2c.tags.age_task_id_blocks_1022::3 408 # Occupied blocks per task id 2695system.l2c.tags.age_task_id_blocks_1022::4 8708 # Occupied blocks per task id 2696system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 2697system.l2c.tags.age_task_id_blocks_1023::4 254 # Occupied blocks per task id 2698system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id 2699system.l2c.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id 2700system.l2c.tags.age_task_id_blocks_1024::2 1961 # Occupied blocks per task id 2701system.l2c.tags.age_task_id_blocks_1024::3 5894 # Occupied blocks per task id 2702system.l2c.tags.age_task_id_blocks_1024::4 42105 # Occupied blocks per task id 2703system.l2c.tags.occ_task_id_percent::1022 0.140717 # Percentage of cache occupancy per task id 2704system.l2c.tags.occ_task_id_percent::1023 0.003891 # Percentage of cache occupancy per task id 2705system.l2c.tags.occ_task_id_percent::1024 0.765335 # Percentage of cache occupancy per task id 2706system.l2c.tags.tag_accesses 79235647 # Number of tag accesses 2707system.l2c.tags.data_accesses 79235647 # Number of data accesses 2708system.l2c.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 2709system.l2c.WritebackDirty_hits::writebacks 2747527 # number of WritebackDirty hits 2710system.l2c.WritebackDirty_hits::total 2747527 # number of WritebackDirty hits 2711system.l2c.WritebackClean_hits::writebacks 1 # number of WritebackClean hits 2712system.l2c.WritebackClean_hits::total 1 # number of WritebackClean hits 2713system.l2c.UpgradeReq_hits::cpu0.data 170119 # number of UpgradeReq hits 2714system.l2c.UpgradeReq_hits::cpu1.data 132427 # number of UpgradeReq hits 2715system.l2c.UpgradeReq_hits::total 302546 # number of UpgradeReq hits 2716system.l2c.SCUpgradeReq_hits::cpu0.data 41747 # number of SCUpgradeReq hits 2717system.l2c.SCUpgradeReq_hits::cpu1.data 38038 # number of SCUpgradeReq hits 2718system.l2c.SCUpgradeReq_hits::total 79785 # number of SCUpgradeReq hits 2719system.l2c.ReadExReq_hits::cpu0.data 52086 # number of ReadExReq hits 2720system.l2c.ReadExReq_hits::cpu1.data 59057 # number of ReadExReq hits 2721system.l2c.ReadExReq_hits::total 111143 # number of ReadExReq hits 2722system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6348 # number of ReadSharedReq hits 2723system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3788 # number of ReadSharedReq hits 2724system.l2c.ReadSharedReq_hits::cpu0.inst 658119 # number of ReadSharedReq hits 2725system.l2c.ReadSharedReq_hits::cpu0.data 620329 # number of ReadSharedReq hits 2726system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 316694 # number of ReadSharedReq hits 2727system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6918 # number of ReadSharedReq hits 2728system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5196 # number of ReadSharedReq hits 2729system.l2c.ReadSharedReq_hits::cpu1.inst 620556 # number of ReadSharedReq hits 2730system.l2c.ReadSharedReq_hits::cpu1.data 563518 # number of ReadSharedReq hits 2731system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 312616 # number of ReadSharedReq hits 2732system.l2c.ReadSharedReq_hits::total 3114082 # number of ReadSharedReq hits 2733system.l2c.InvalidateReq_hits::cpu0.data 130339 # number of InvalidateReq hits 2734system.l2c.InvalidateReq_hits::cpu1.data 134354 # number of InvalidateReq hits 2735system.l2c.InvalidateReq_hits::total 264693 # number of InvalidateReq hits 2736system.l2c.demand_hits::cpu0.dtb.walker 6348 # number of demand (read+write) hits 2737system.l2c.demand_hits::cpu0.itb.walker 3788 # number of demand (read+write) hits 2738system.l2c.demand_hits::cpu0.inst 658119 # number of demand (read+write) hits 2739system.l2c.demand_hits::cpu0.data 672415 # number of demand (read+write) hits 2740system.l2c.demand_hits::cpu0.l2cache.prefetcher 316694 # number of demand (read+write) hits 2741system.l2c.demand_hits::cpu1.dtb.walker 6918 # number of demand (read+write) hits 2742system.l2c.demand_hits::cpu1.itb.walker 5196 # number of demand (read+write) hits 2743system.l2c.demand_hits::cpu1.inst 620556 # number of demand (read+write) hits 2744system.l2c.demand_hits::cpu1.data 622575 # number of demand (read+write) hits 2745system.l2c.demand_hits::cpu1.l2cache.prefetcher 312616 # number of demand (read+write) hits 2746system.l2c.demand_hits::total 3225225 # number of demand (read+write) hits 2747system.l2c.overall_hits::cpu0.dtb.walker 6348 # number of overall hits 2748system.l2c.overall_hits::cpu0.itb.walker 3788 # number of overall hits 2749system.l2c.overall_hits::cpu0.inst 658119 # number of overall hits 2750system.l2c.overall_hits::cpu0.data 672415 # number of overall hits 2751system.l2c.overall_hits::cpu0.l2cache.prefetcher 316694 # number of overall hits 2752system.l2c.overall_hits::cpu1.dtb.walker 6918 # number of overall hits 2753system.l2c.overall_hits::cpu1.itb.walker 5196 # number of overall hits 2754system.l2c.overall_hits::cpu1.inst 620556 # number of overall hits 2755system.l2c.overall_hits::cpu1.data 622575 # number of overall hits 2756system.l2c.overall_hits::cpu1.l2cache.prefetcher 312616 # number of overall hits 2757system.l2c.overall_hits::total 3225225 # number of overall hits 2758system.l2c.UpgradeReq_misses::cpu0.data 63896 # number of UpgradeReq misses 2759system.l2c.UpgradeReq_misses::cpu1.data 60301 # number of UpgradeReq misses 2760system.l2c.UpgradeReq_misses::total 124197 # number of UpgradeReq misses 2761system.l2c.SCUpgradeReq_misses::cpu0.data 12467 # number of SCUpgradeReq misses 2762system.l2c.SCUpgradeReq_misses::cpu1.data 11210 # number of SCUpgradeReq misses 2763system.l2c.SCUpgradeReq_misses::total 23677 # number of SCUpgradeReq misses 2764system.l2c.ReadExReq_misses::cpu0.data 80795 # number of ReadExReq misses 2765system.l2c.ReadExReq_misses::cpu1.data 51109 # number of ReadExReq misses 2766system.l2c.ReadExReq_misses::total 131904 # number of ReadExReq misses 2767system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2056 # number of ReadSharedReq misses 2768system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1934 # number of ReadSharedReq misses 2769system.l2c.ReadSharedReq_misses::cpu0.inst 66055 # number of ReadSharedReq misses 2770system.l2c.ReadSharedReq_misses::cpu0.data 143274 # number of ReadSharedReq misses 2771system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 256484 # number of ReadSharedReq misses 2772system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1908 # number of ReadSharedReq misses 2773system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1578 # number of ReadSharedReq misses 2774system.l2c.ReadSharedReq_misses::cpu1.inst 52043 # number of ReadSharedReq misses 2775system.l2c.ReadSharedReq_misses::cpu1.data 103878 # number of ReadSharedReq misses 2776system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 163476 # number of ReadSharedReq misses 2777system.l2c.ReadSharedReq_misses::total 792686 # number of ReadSharedReq misses 2778system.l2c.InvalidateReq_misses::cpu0.data 465421 # number of InvalidateReq misses 2779system.l2c.InvalidateReq_misses::cpu1.data 95414 # number of InvalidateReq misses 2780system.l2c.InvalidateReq_misses::total 560835 # number of InvalidateReq misses 2781system.l2c.demand_misses::cpu0.dtb.walker 2056 # number of demand (read+write) misses 2782system.l2c.demand_misses::cpu0.itb.walker 1934 # number of demand (read+write) misses 2783system.l2c.demand_misses::cpu0.inst 66055 # number of demand (read+write) misses 2784system.l2c.demand_misses::cpu0.data 224069 # number of demand (read+write) misses 2785system.l2c.demand_misses::cpu0.l2cache.prefetcher 256484 # number of demand (read+write) misses 2786system.l2c.demand_misses::cpu1.dtb.walker 1908 # number of demand (read+write) misses 2787system.l2c.demand_misses::cpu1.itb.walker 1578 # number of demand (read+write) misses 2788system.l2c.demand_misses::cpu1.inst 52043 # number of demand (read+write) misses 2789system.l2c.demand_misses::cpu1.data 154987 # number of demand (read+write) misses 2790system.l2c.demand_misses::cpu1.l2cache.prefetcher 163476 # number of demand (read+write) misses 2791system.l2c.demand_misses::total 924590 # number of demand (read+write) misses 2792system.l2c.overall_misses::cpu0.dtb.walker 2056 # number of overall misses 2793system.l2c.overall_misses::cpu0.itb.walker 1934 # number of overall misses 2794system.l2c.overall_misses::cpu0.inst 66055 # number of overall misses 2795system.l2c.overall_misses::cpu0.data 224069 # number of overall misses 2796system.l2c.overall_misses::cpu0.l2cache.prefetcher 256484 # number of overall misses 2797system.l2c.overall_misses::cpu1.dtb.walker 1908 # number of overall misses 2798system.l2c.overall_misses::cpu1.itb.walker 1578 # number of overall misses 2799system.l2c.overall_misses::cpu1.inst 52043 # number of overall misses 2800system.l2c.overall_misses::cpu1.data 154987 # number of overall misses 2801system.l2c.overall_misses::cpu1.l2cache.prefetcher 163476 # number of overall misses 2802system.l2c.overall_misses::total 924590 # number of overall misses 2803system.l2c.UpgradeReq_miss_latency::cpu0.data 446027000 # number of UpgradeReq miss cycles 2804system.l2c.UpgradeReq_miss_latency::cpu1.data 423537000 # number of UpgradeReq miss cycles 2805system.l2c.UpgradeReq_miss_latency::total 869564000 # number of UpgradeReq miss cycles 2806system.l2c.SCUpgradeReq_miss_latency::cpu0.data 79642000 # number of SCUpgradeReq miss cycles 2807system.l2c.SCUpgradeReq_miss_latency::cpu1.data 73423000 # number of SCUpgradeReq miss cycles 2808system.l2c.SCUpgradeReq_miss_latency::total 153065000 # number of SCUpgradeReq miss cycles 2809system.l2c.ReadExReq_miss_latency::cpu0.data 7209880999 # number of ReadExReq miss cycles 2810system.l2c.ReadExReq_miss_latency::cpu1.data 4224259500 # number of ReadExReq miss cycles 2811system.l2c.ReadExReq_miss_latency::total 11434140499 # number of ReadExReq miss cycles 2812system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 181168500 # number of ReadSharedReq miss cycles 2813system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 173308500 # number of ReadSharedReq miss cycles 2814system.l2c.ReadSharedReq_miss_latency::cpu0.inst 5614644500 # number of ReadSharedReq miss cycles 2815system.l2c.ReadSharedReq_miss_latency::cpu0.data 12851594000 # number of ReadSharedReq miss cycles 2816system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 32734884574 # number of ReadSharedReq miss cycles 2817system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 174846500 # number of ReadSharedReq miss cycles 2818system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 145724500 # number of ReadSharedReq miss cycles 2819system.l2c.ReadSharedReq_miss_latency::cpu1.inst 4416688500 # number of ReadSharedReq miss cycles 2820system.l2c.ReadSharedReq_miss_latency::cpu1.data 9519600500 # number of ReadSharedReq miss cycles 2821system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 19884865739 # number of ReadSharedReq miss cycles 2822system.l2c.ReadSharedReq_miss_latency::total 85697325813 # number of ReadSharedReq miss cycles 2823system.l2c.InvalidateReq_miss_latency::cpu0.data 65788000 # number of InvalidateReq miss cycles 2824system.l2c.InvalidateReq_miss_latency::cpu1.data 54373000 # number of InvalidateReq miss cycles 2825system.l2c.InvalidateReq_miss_latency::total 120161000 # number of InvalidateReq miss cycles 2826system.l2c.demand_miss_latency::cpu0.dtb.walker 181168500 # number of demand (read+write) miss cycles 2827system.l2c.demand_miss_latency::cpu0.itb.walker 173308500 # number of demand (read+write) miss cycles 2828system.l2c.demand_miss_latency::cpu0.inst 5614644500 # number of demand (read+write) miss cycles 2829system.l2c.demand_miss_latency::cpu0.data 20061474999 # number of demand (read+write) miss cycles 2830system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 32734884574 # number of demand (read+write) miss cycles 2831system.l2c.demand_miss_latency::cpu1.dtb.walker 174846500 # number of demand (read+write) miss cycles 2832system.l2c.demand_miss_latency::cpu1.itb.walker 145724500 # number of demand (read+write) miss cycles 2833system.l2c.demand_miss_latency::cpu1.inst 4416688500 # number of demand (read+write) miss cycles 2834system.l2c.demand_miss_latency::cpu1.data 13743860000 # number of demand (read+write) miss cycles 2835system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 19884865739 # number of demand (read+write) miss cycles 2836system.l2c.demand_miss_latency::total 97131466312 # number of demand (read+write) miss cycles 2837system.l2c.overall_miss_latency::cpu0.dtb.walker 181168500 # number of overall miss cycles 2838system.l2c.overall_miss_latency::cpu0.itb.walker 173308500 # number of overall miss cycles 2839system.l2c.overall_miss_latency::cpu0.inst 5614644500 # number of overall miss cycles 2840system.l2c.overall_miss_latency::cpu0.data 20061474999 # number of overall miss cycles 2841system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 32734884574 # number of overall miss cycles 2842system.l2c.overall_miss_latency::cpu1.dtb.walker 174846500 # number of overall miss cycles 2843system.l2c.overall_miss_latency::cpu1.itb.walker 145724500 # number of overall miss cycles 2844system.l2c.overall_miss_latency::cpu1.inst 4416688500 # number of overall miss cycles 2845system.l2c.overall_miss_latency::cpu1.data 13743860000 # number of overall miss cycles 2846system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 19884865739 # number of overall miss cycles 2847system.l2c.overall_miss_latency::total 97131466312 # number of overall miss cycles 2848system.l2c.WritebackDirty_accesses::writebacks 2747527 # number of WritebackDirty accesses(hits+misses) 2849system.l2c.WritebackDirty_accesses::total 2747527 # number of WritebackDirty accesses(hits+misses) 2850system.l2c.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) 2851system.l2c.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) 2852system.l2c.UpgradeReq_accesses::cpu0.data 234015 # number of UpgradeReq accesses(hits+misses) 2853system.l2c.UpgradeReq_accesses::cpu1.data 192728 # number of UpgradeReq accesses(hits+misses) 2854system.l2c.UpgradeReq_accesses::total 426743 # number of UpgradeReq accesses(hits+misses) 2855system.l2c.SCUpgradeReq_accesses::cpu0.data 54214 # number of SCUpgradeReq accesses(hits+misses) 2856system.l2c.SCUpgradeReq_accesses::cpu1.data 49248 # number of SCUpgradeReq accesses(hits+misses) 2857system.l2c.SCUpgradeReq_accesses::total 103462 # number of SCUpgradeReq accesses(hits+misses) 2858system.l2c.ReadExReq_accesses::cpu0.data 132881 # number of ReadExReq accesses(hits+misses) 2859system.l2c.ReadExReq_accesses::cpu1.data 110166 # number of ReadExReq accesses(hits+misses) 2860system.l2c.ReadExReq_accesses::total 243047 # number of ReadExReq accesses(hits+misses) 2861system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8404 # number of ReadSharedReq accesses(hits+misses) 2862system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5722 # number of ReadSharedReq accesses(hits+misses) 2863system.l2c.ReadSharedReq_accesses::cpu0.inst 724174 # number of ReadSharedReq accesses(hits+misses) 2864system.l2c.ReadSharedReq_accesses::cpu0.data 763603 # number of ReadSharedReq accesses(hits+misses) 2865system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 573178 # number of ReadSharedReq accesses(hits+misses) 2866system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8826 # number of ReadSharedReq accesses(hits+misses) 2867system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6774 # number of ReadSharedReq accesses(hits+misses) 2868system.l2c.ReadSharedReq_accesses::cpu1.inst 672599 # number of ReadSharedReq accesses(hits+misses) 2869system.l2c.ReadSharedReq_accesses::cpu1.data 667396 # number of ReadSharedReq accesses(hits+misses) 2870system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 476092 # number of ReadSharedReq accesses(hits+misses) 2871system.l2c.ReadSharedReq_accesses::total 3906768 # number of ReadSharedReq accesses(hits+misses) 2872system.l2c.InvalidateReq_accesses::cpu0.data 595760 # number of InvalidateReq accesses(hits+misses) 2873system.l2c.InvalidateReq_accesses::cpu1.data 229768 # number of InvalidateReq accesses(hits+misses) 2874system.l2c.InvalidateReq_accesses::total 825528 # number of InvalidateReq accesses(hits+misses) 2875system.l2c.demand_accesses::cpu0.dtb.walker 8404 # number of demand (read+write) accesses 2876system.l2c.demand_accesses::cpu0.itb.walker 5722 # number of demand (read+write) accesses 2877system.l2c.demand_accesses::cpu0.inst 724174 # number of demand (read+write) accesses 2878system.l2c.demand_accesses::cpu0.data 896484 # number of demand (read+write) accesses 2879system.l2c.demand_accesses::cpu0.l2cache.prefetcher 573178 # number of demand (read+write) accesses 2880system.l2c.demand_accesses::cpu1.dtb.walker 8826 # number of demand (read+write) accesses 2881system.l2c.demand_accesses::cpu1.itb.walker 6774 # number of demand (read+write) accesses 2882system.l2c.demand_accesses::cpu1.inst 672599 # number of demand (read+write) accesses 2883system.l2c.demand_accesses::cpu1.data 777562 # number of demand (read+write) accesses 2884system.l2c.demand_accesses::cpu1.l2cache.prefetcher 476092 # number of demand (read+write) accesses 2885system.l2c.demand_accesses::total 4149815 # number of demand (read+write) accesses 2886system.l2c.overall_accesses::cpu0.dtb.walker 8404 # number of overall (read+write) accesses 2887system.l2c.overall_accesses::cpu0.itb.walker 5722 # number of overall (read+write) accesses 2888system.l2c.overall_accesses::cpu0.inst 724174 # number of overall (read+write) accesses 2889system.l2c.overall_accesses::cpu0.data 896484 # number of overall (read+write) accesses 2890system.l2c.overall_accesses::cpu0.l2cache.prefetcher 573178 # number of overall (read+write) accesses 2891system.l2c.overall_accesses::cpu1.dtb.walker 8826 # number of overall (read+write) accesses 2892system.l2c.overall_accesses::cpu1.itb.walker 6774 # number of overall (read+write) accesses 2893system.l2c.overall_accesses::cpu1.inst 672599 # number of overall (read+write) accesses 2894system.l2c.overall_accesses::cpu1.data 777562 # number of overall (read+write) accesses 2895system.l2c.overall_accesses::cpu1.l2cache.prefetcher 476092 # number of overall (read+write) accesses 2896system.l2c.overall_accesses::total 4149815 # number of overall (read+write) accesses 2897system.l2c.UpgradeReq_miss_rate::cpu0.data 0.273042 # miss rate for UpgradeReq accesses 2898system.l2c.UpgradeReq_miss_rate::cpu1.data 0.312881 # miss rate for UpgradeReq accesses 2899system.l2c.UpgradeReq_miss_rate::total 0.291035 # miss rate for UpgradeReq accesses 2900system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.229959 # miss rate for SCUpgradeReq accesses 2901system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.227623 # miss rate for SCUpgradeReq accesses 2902system.l2c.SCUpgradeReq_miss_rate::total 0.228847 # miss rate for SCUpgradeReq accesses 2903system.l2c.ReadExReq_miss_rate::cpu0.data 0.608025 # miss rate for ReadExReq accesses 2904system.l2c.ReadExReq_miss_rate::cpu1.data 0.463927 # miss rate for ReadExReq accesses 2905system.l2c.ReadExReq_miss_rate::total 0.542710 # miss rate for ReadExReq accesses 2906system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.244645 # miss rate for ReadSharedReq accesses 2907system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.337994 # miss rate for ReadSharedReq accesses 2908system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.091214 # miss rate for ReadSharedReq accesses 2909system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.187629 # miss rate for ReadSharedReq accesses 2910system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.447477 # miss rate for ReadSharedReq accesses 2911system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.216179 # miss rate for ReadSharedReq accesses 2912system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.232950 # miss rate for ReadSharedReq accesses 2913system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.077376 # miss rate for ReadSharedReq accesses 2914system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.155647 # miss rate for ReadSharedReq accesses 2915system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.343371 # miss rate for ReadSharedReq accesses 2916system.l2c.ReadSharedReq_miss_rate::total 0.202901 # miss rate for ReadSharedReq accesses 2917system.l2c.InvalidateReq_miss_rate::cpu0.data 0.781222 # miss rate for InvalidateReq accesses 2918system.l2c.InvalidateReq_miss_rate::cpu1.data 0.415262 # miss rate for InvalidateReq accesses 2919system.l2c.InvalidateReq_miss_rate::total 0.679365 # miss rate for InvalidateReq accesses 2920system.l2c.demand_miss_rate::cpu0.dtb.walker 0.244645 # miss rate for demand accesses 2921system.l2c.demand_miss_rate::cpu0.itb.walker 0.337994 # miss rate for demand accesses 2922system.l2c.demand_miss_rate::cpu0.inst 0.091214 # miss rate for demand accesses 2923system.l2c.demand_miss_rate::cpu0.data 0.249942 # miss rate for demand accesses 2924system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.447477 # miss rate for demand accesses 2925system.l2c.demand_miss_rate::cpu1.dtb.walker 0.216179 # miss rate for demand accesses 2926system.l2c.demand_miss_rate::cpu1.itb.walker 0.232950 # miss rate for demand accesses 2927system.l2c.demand_miss_rate::cpu1.inst 0.077376 # miss rate for demand accesses 2928system.l2c.demand_miss_rate::cpu1.data 0.199324 # miss rate for demand accesses 2929system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.343371 # miss rate for demand accesses 2930system.l2c.demand_miss_rate::total 0.222803 # miss rate for demand accesses 2931system.l2c.overall_miss_rate::cpu0.dtb.walker 0.244645 # miss rate for overall accesses 2932system.l2c.overall_miss_rate::cpu0.itb.walker 0.337994 # miss rate for overall accesses 2933system.l2c.overall_miss_rate::cpu0.inst 0.091214 # miss rate for overall accesses 2934system.l2c.overall_miss_rate::cpu0.data 0.249942 # miss rate for overall accesses 2935system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.447477 # miss rate for overall accesses 2936system.l2c.overall_miss_rate::cpu1.dtb.walker 0.216179 # miss rate for overall accesses 2937system.l2c.overall_miss_rate::cpu1.itb.walker 0.232950 # miss rate for overall accesses 2938system.l2c.overall_miss_rate::cpu1.inst 0.077376 # miss rate for overall accesses 2939system.l2c.overall_miss_rate::cpu1.data 0.199324 # miss rate for overall accesses 2940system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.343371 # miss rate for overall accesses 2941system.l2c.overall_miss_rate::total 0.222803 # miss rate for overall accesses 2942system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6980.515212 # average UpgradeReq miss latency 2943system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7023.714366 # average UpgradeReq miss latency 2944system.l2c.UpgradeReq_avg_miss_latency::total 7001.489569 # average UpgradeReq miss latency 2945system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6388.224914 # average SCUpgradeReq miss latency 2946system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6549.776985 # average SCUpgradeReq miss latency 2947system.l2c.SCUpgradeReq_avg_miss_latency::total 6464.712590 # average SCUpgradeReq miss latency 2948system.l2c.ReadExReq_avg_miss_latency::cpu0.data 89236.722557 # average ReadExReq miss latency 2949system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82651.969320 # average ReadExReq miss latency 2950system.l2c.ReadExReq_avg_miss_latency::total 86685.320377 # average ReadExReq miss latency 2951system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 88116.974708 # average ReadSharedReq miss latency 2952system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 89611.427094 # average ReadSharedReq miss latency 2953system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 84999.538264 # average ReadSharedReq miss latency 2954system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 89699.415107 # average ReadSharedReq miss latency 2955system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 127629.343639 # average ReadSharedReq miss latency 2956system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 91638.626834 # average ReadSharedReq miss latency 2957system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 92347.591888 # average ReadSharedReq miss latency 2958system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 84866.139538 # average ReadSharedReq miss latency 2959system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 91642.123453 # average ReadSharedReq miss latency 2960system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 121637.829033 # average ReadSharedReq miss latency 2961system.l2c.ReadSharedReq_avg_miss_latency::total 108110.053430 # average ReadSharedReq miss latency 2962system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 141.351594 # average InvalidateReq miss latency 2963system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 569.863961 # average InvalidateReq miss latency 2964system.l2c.InvalidateReq_avg_miss_latency::total 214.253747 # average InvalidateReq miss latency 2965system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 88116.974708 # average overall miss latency 2966system.l2c.demand_avg_miss_latency::cpu0.itb.walker 89611.427094 # average overall miss latency 2967system.l2c.demand_avg_miss_latency::cpu0.inst 84999.538264 # average overall miss latency 2968system.l2c.demand_avg_miss_latency::cpu0.data 89532.577014 # average overall miss latency 2969system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 127629.343639 # average overall miss latency 2970system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 91638.626834 # average overall miss latency 2971system.l2c.demand_avg_miss_latency::cpu1.itb.walker 92347.591888 # average overall miss latency 2972system.l2c.demand_avg_miss_latency::cpu1.inst 84866.139538 # average overall miss latency 2973system.l2c.demand_avg_miss_latency::cpu1.data 88677.501984 # average overall miss latency 2974system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 121637.829033 # average overall miss latency 2975system.l2c.demand_avg_miss_latency::total 105053.554886 # average overall miss latency 2976system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 88116.974708 # average overall miss latency 2977system.l2c.overall_avg_miss_latency::cpu0.itb.walker 89611.427094 # average overall miss latency 2978system.l2c.overall_avg_miss_latency::cpu0.inst 84999.538264 # average overall miss latency 2979system.l2c.overall_avg_miss_latency::cpu0.data 89532.577014 # average overall miss latency 2980system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 127629.343639 # average overall miss latency 2981system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 91638.626834 # average overall miss latency 2982system.l2c.overall_avg_miss_latency::cpu1.itb.walker 92347.591888 # average overall miss latency 2983system.l2c.overall_avg_miss_latency::cpu1.inst 84866.139538 # average overall miss latency 2984system.l2c.overall_avg_miss_latency::cpu1.data 88677.501984 # average overall miss latency 2985system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 121637.829033 # average overall miss latency 2986system.l2c.overall_avg_miss_latency::total 105053.554886 # average overall miss latency 2987system.l2c.blocked_cycles::no_mshrs 547 # number of cycles access was blocked 2988system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2989system.l2c.blocked::no_mshrs 8 # number of cycles access was blocked 2990system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2991system.l2c.avg_blocked_cycles::no_mshrs 68.375000 # average number of cycles each access was blocked 2992system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2993system.l2c.writebacks::writebacks 1075082 # number of writebacks 2994system.l2c.writebacks::total 1075082 # number of writebacks 2995system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 93 # number of ReadSharedReq MSHR hits 2996system.l2c.ReadSharedReq_mshr_hits::cpu0.data 13 # number of ReadSharedReq MSHR hits 2997system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 87 # number of ReadSharedReq MSHR hits 2998system.l2c.ReadSharedReq_mshr_hits::cpu1.data 17 # number of ReadSharedReq MSHR hits 2999system.l2c.ReadSharedReq_mshr_hits::total 210 # number of ReadSharedReq MSHR hits 3000system.l2c.demand_mshr_hits::cpu0.inst 93 # number of demand (read+write) MSHR hits 3001system.l2c.demand_mshr_hits::cpu0.data 13 # number of demand (read+write) MSHR hits 3002system.l2c.demand_mshr_hits::cpu1.inst 87 # number of demand (read+write) MSHR hits 3003system.l2c.demand_mshr_hits::cpu1.data 17 # number of demand (read+write) MSHR hits 3004system.l2c.demand_mshr_hits::total 210 # number of demand (read+write) MSHR hits 3005system.l2c.overall_mshr_hits::cpu0.inst 93 # number of overall MSHR hits 3006system.l2c.overall_mshr_hits::cpu0.data 13 # number of overall MSHR hits 3007system.l2c.overall_mshr_hits::cpu1.inst 87 # number of overall MSHR hits 3008system.l2c.overall_mshr_hits::cpu1.data 17 # number of overall MSHR hits 3009system.l2c.overall_mshr_hits::total 210 # number of overall MSHR hits 3010system.l2c.CleanEvict_mshr_misses::writebacks 54168 # number of CleanEvict MSHR misses 3011system.l2c.CleanEvict_mshr_misses::total 54168 # number of CleanEvict MSHR misses 3012system.l2c.UpgradeReq_mshr_misses::cpu0.data 63896 # number of UpgradeReq MSHR misses 3013system.l2c.UpgradeReq_mshr_misses::cpu1.data 60301 # number of UpgradeReq MSHR misses 3014system.l2c.UpgradeReq_mshr_misses::total 124197 # number of UpgradeReq MSHR misses 3015system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 12467 # number of SCUpgradeReq MSHR misses 3016system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11210 # number of SCUpgradeReq MSHR misses 3017system.l2c.SCUpgradeReq_mshr_misses::total 23677 # number of SCUpgradeReq MSHR misses 3018system.l2c.ReadExReq_mshr_misses::cpu0.data 80795 # number of ReadExReq MSHR misses 3019system.l2c.ReadExReq_mshr_misses::cpu1.data 51109 # number of ReadExReq MSHR misses 3020system.l2c.ReadExReq_mshr_misses::total 131904 # number of ReadExReq MSHR misses 3021system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 2056 # number of ReadSharedReq MSHR misses 3022system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1934 # number of ReadSharedReq MSHR misses 3023system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 65962 # number of ReadSharedReq MSHR misses 3024system.l2c.ReadSharedReq_mshr_misses::cpu0.data 143261 # number of ReadSharedReq MSHR misses 3025system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 256484 # number of ReadSharedReq MSHR misses 3026system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1908 # number of ReadSharedReq MSHR misses 3027system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1578 # number of ReadSharedReq MSHR misses 3028system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 51956 # number of ReadSharedReq MSHR misses 3029system.l2c.ReadSharedReq_mshr_misses::cpu1.data 103861 # number of ReadSharedReq MSHR misses 3030system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 163476 # number of ReadSharedReq MSHR misses 3031system.l2c.ReadSharedReq_mshr_misses::total 792476 # number of ReadSharedReq MSHR misses 3032system.l2c.InvalidateReq_mshr_misses::cpu0.data 465421 # number of InvalidateReq MSHR misses 3033system.l2c.InvalidateReq_mshr_misses::cpu1.data 95414 # number of InvalidateReq MSHR misses 3034system.l2c.InvalidateReq_mshr_misses::total 560835 # number of InvalidateReq MSHR misses 3035system.l2c.demand_mshr_misses::cpu0.dtb.walker 2056 # number of demand (read+write) MSHR misses 3036system.l2c.demand_mshr_misses::cpu0.itb.walker 1934 # number of demand (read+write) MSHR misses 3037system.l2c.demand_mshr_misses::cpu0.inst 65962 # number of demand (read+write) MSHR misses 3038system.l2c.demand_mshr_misses::cpu0.data 224056 # number of demand (read+write) MSHR misses 3039system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 256484 # number of demand (read+write) MSHR misses 3040system.l2c.demand_mshr_misses::cpu1.dtb.walker 1908 # number of demand (read+write) MSHR misses 3041system.l2c.demand_mshr_misses::cpu1.itb.walker 1578 # number of demand (read+write) MSHR misses 3042system.l2c.demand_mshr_misses::cpu1.inst 51956 # number of demand (read+write) MSHR misses 3043system.l2c.demand_mshr_misses::cpu1.data 154970 # number of demand (read+write) MSHR misses 3044system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 163476 # number of demand (read+write) MSHR misses 3045system.l2c.demand_mshr_misses::total 924380 # number of demand (read+write) MSHR misses 3046system.l2c.overall_mshr_misses::cpu0.dtb.walker 2056 # number of overall MSHR misses 3047system.l2c.overall_mshr_misses::cpu0.itb.walker 1934 # number of overall MSHR misses 3048system.l2c.overall_mshr_misses::cpu0.inst 65962 # number of overall MSHR misses 3049system.l2c.overall_mshr_misses::cpu0.data 224056 # number of overall MSHR misses 3050system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 256484 # number of overall MSHR misses 3051system.l2c.overall_mshr_misses::cpu1.dtb.walker 1908 # number of overall MSHR misses 3052system.l2c.overall_mshr_misses::cpu1.itb.walker 1578 # number of overall MSHR misses 3053system.l2c.overall_mshr_misses::cpu1.inst 51956 # number of overall MSHR misses 3054system.l2c.overall_mshr_misses::cpu1.data 154970 # number of overall MSHR misses 3055system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 163476 # number of overall MSHR misses 3056system.l2c.overall_mshr_misses::total 924380 # number of overall MSHR misses 3057system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 52299 # number of ReadReq MSHR uncacheable 3058system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31702 # number of ReadReq MSHR uncacheable 3059system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable 3060system.l2c.ReadReq_mshr_uncacheable::cpu1.data 6939 # number of ReadReq MSHR uncacheable 3061system.l2c.ReadReq_mshr_uncacheable::total 91033 # number of ReadReq MSHR uncacheable 3062system.l2c.WriteReq_mshr_uncacheable::cpu0.data 31225 # number of WriteReq MSHR uncacheable 3063system.l2c.WriteReq_mshr_uncacheable::cpu1.data 7280 # number of WriteReq MSHR uncacheable 3064system.l2c.WriteReq_mshr_uncacheable::total 38505 # number of WriteReq MSHR uncacheable 3065system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 52299 # number of overall MSHR uncacheable misses 3066system.l2c.overall_mshr_uncacheable_misses::cpu0.data 62927 # number of overall MSHR uncacheable misses 3067system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses 3068system.l2c.overall_mshr_uncacheable_misses::cpu1.data 14219 # number of overall MSHR uncacheable misses 3069system.l2c.overall_mshr_uncacheable_misses::total 129538 # number of overall MSHR uncacheable misses 3070system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1380806993 # number of UpgradeReq MSHR miss cycles 3071system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 1305380495 # number of UpgradeReq MSHR miss cycles 3072system.l2c.UpgradeReq_mshr_miss_latency::total 2686187488 # number of UpgradeReq MSHR miss cycles 3073system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 306900998 # number of SCUpgradeReq MSHR miss cycles 3074system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 275849499 # number of SCUpgradeReq MSHR miss cycles 3075system.l2c.SCUpgradeReq_mshr_miss_latency::total 582750497 # number of SCUpgradeReq MSHR miss cycles 3076system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6401900063 # number of ReadExReq MSHR miss cycles 3077system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3713131578 # number of ReadExReq MSHR miss cycles 3078system.l2c.ReadExReq_mshr_miss_latency::total 10115031641 # number of ReadExReq MSHR miss cycles 3079system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 160608500 # number of ReadSharedReq MSHR miss cycles 3080system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 153968500 # number of ReadSharedReq MSHR miss cycles 3081system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 4948095074 # number of ReadSharedReq MSHR miss cycles 3082system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 11417870701 # number of ReadSharedReq MSHR miss cycles 3083system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 30169861471 # number of ReadSharedReq MSHR miss cycles 3084system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 155763506 # number of ReadSharedReq MSHR miss cycles 3085system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 129943003 # number of ReadSharedReq MSHR miss cycles 3086system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 3891093570 # number of ReadSharedReq MSHR miss cycles 3087system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 8479584227 # number of ReadSharedReq MSHR miss cycles 3088system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 18249884712 # number of ReadSharedReq MSHR miss cycles 3089system.l2c.ReadSharedReq_mshr_miss_latency::total 77756673264 # number of ReadSharedReq MSHR miss cycles 3090system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 9735980999 # number of InvalidateReq MSHR miss cycles 3091system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1980875000 # number of InvalidateReq MSHR miss cycles 3092system.l2c.InvalidateReq_mshr_miss_latency::total 11716855999 # number of InvalidateReq MSHR miss cycles 3093system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 160608500 # number of demand (read+write) MSHR miss cycles 3094system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 153968500 # number of demand (read+write) MSHR miss cycles 3095system.l2c.demand_mshr_miss_latency::cpu0.inst 4948095074 # number of demand (read+write) MSHR miss cycles 3096system.l2c.demand_mshr_miss_latency::cpu0.data 17819770764 # number of demand (read+write) MSHR miss cycles 3097system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 30169861471 # number of demand (read+write) MSHR miss cycles 3098system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 155763506 # number of demand (read+write) MSHR miss cycles 3099system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 129943003 # number of demand (read+write) MSHR miss cycles 3100system.l2c.demand_mshr_miss_latency::cpu1.inst 3891093570 # number of demand (read+write) MSHR miss cycles 3101system.l2c.demand_mshr_miss_latency::cpu1.data 12192715805 # number of demand (read+write) MSHR miss cycles 3102system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 18249884712 # number of demand (read+write) MSHR miss cycles 3103system.l2c.demand_mshr_miss_latency::total 87871704905 # number of demand (read+write) MSHR miss cycles 3104system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 160608500 # number of overall MSHR miss cycles 3105system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 153968500 # number of overall MSHR miss cycles 3106system.l2c.overall_mshr_miss_latency::cpu0.inst 4948095074 # number of overall MSHR miss cycles 3107system.l2c.overall_mshr_miss_latency::cpu0.data 17819770764 # number of overall MSHR miss cycles 3108system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 30169861471 # number of overall MSHR miss cycles 3109system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 155763506 # number of overall MSHR miss cycles 3110system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 129943003 # number of overall MSHR miss cycles 3111system.l2c.overall_mshr_miss_latency::cpu1.inst 3891093570 # number of overall MSHR miss cycles 3112system.l2c.overall_mshr_miss_latency::cpu1.data 12192715805 # number of overall MSHR miss cycles 3113system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 18249884712 # number of overall MSHR miss cycles 3114system.l2c.overall_mshr_miss_latency::total 87871704905 # number of overall MSHR miss cycles 3115system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3320524500 # number of ReadReq MSHR uncacheable cycles 3116system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5312322505 # number of ReadReq MSHR uncacheable cycles 3117system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5752000 # number of ReadReq MSHR uncacheable cycles 3118system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 656593502 # number of ReadReq MSHR uncacheable cycles 3119system.l2c.ReadReq_mshr_uncacheable_latency::total 9295192507 # number of ReadReq MSHR uncacheable cycles 3120system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3320524500 # number of overall MSHR uncacheable cycles 3121system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5312322505 # number of overall MSHR uncacheable cycles 3122system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5752000 # number of overall MSHR uncacheable cycles 3123system.l2c.overall_mshr_uncacheable_latency::cpu1.data 656593502 # number of overall MSHR uncacheable cycles 3124system.l2c.overall_mshr_uncacheable_latency::total 9295192507 # number of overall MSHR uncacheable cycles 3125system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3126system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 3127system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.273042 # mshr miss rate for UpgradeReq accesses 3128system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.312881 # mshr miss rate for UpgradeReq accesses 3129system.l2c.UpgradeReq_mshr_miss_rate::total 0.291035 # mshr miss rate for UpgradeReq accesses 3130system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.229959 # mshr miss rate for SCUpgradeReq accesses 3131system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.227623 # mshr miss rate for SCUpgradeReq accesses 3132system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.228847 # mshr miss rate for SCUpgradeReq accesses 3133system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.608025 # mshr miss rate for ReadExReq accesses 3134system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.463927 # mshr miss rate for ReadExReq accesses 3135system.l2c.ReadExReq_mshr_miss_rate::total 0.542710 # mshr miss rate for ReadExReq accesses 3136system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.244645 # mshr miss rate for ReadSharedReq accesses 3137system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.337994 # mshr miss rate for ReadSharedReq accesses 3138system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.091086 # mshr miss rate for ReadSharedReq accesses 3139system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.187612 # mshr miss rate for ReadSharedReq accesses 3140system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447477 # mshr miss rate for ReadSharedReq accesses 3141system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.216179 # mshr miss rate for ReadSharedReq accesses 3142system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.232950 # mshr miss rate for ReadSharedReq accesses 3143system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.077247 # mshr miss rate for ReadSharedReq accesses 3144system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.155621 # mshr miss rate for ReadSharedReq accesses 3145system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.343371 # mshr miss rate for ReadSharedReq accesses 3146system.l2c.ReadSharedReq_mshr_miss_rate::total 0.202847 # mshr miss rate for ReadSharedReq accesses 3147system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.781222 # mshr miss rate for InvalidateReq accesses 3148system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.415262 # mshr miss rate for InvalidateReq accesses 3149system.l2c.InvalidateReq_mshr_miss_rate::total 0.679365 # mshr miss rate for InvalidateReq accesses 3150system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.244645 # mshr miss rate for demand accesses 3151system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.337994 # mshr miss rate for demand accesses 3152system.l2c.demand_mshr_miss_rate::cpu0.inst 0.091086 # mshr miss rate for demand accesses 3153system.l2c.demand_mshr_miss_rate::cpu0.data 0.249927 # mshr miss rate for demand accesses 3154system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447477 # mshr miss rate for demand accesses 3155system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.216179 # mshr miss rate for demand accesses 3156system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.232950 # mshr miss rate for demand accesses 3157system.l2c.demand_mshr_miss_rate::cpu1.inst 0.077247 # mshr miss rate for demand accesses 3158system.l2c.demand_mshr_miss_rate::cpu1.data 0.199302 # mshr miss rate for demand accesses 3159system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.343371 # mshr miss rate for demand accesses 3160system.l2c.demand_mshr_miss_rate::total 0.222752 # mshr miss rate for demand accesses 3161system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.244645 # mshr miss rate for overall accesses 3162system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.337994 # mshr miss rate for overall accesses 3163system.l2c.overall_mshr_miss_rate::cpu0.inst 0.091086 # mshr miss rate for overall accesses 3164system.l2c.overall_mshr_miss_rate::cpu0.data 0.249927 # mshr miss rate for overall accesses 3165system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447477 # mshr miss rate for overall accesses 3166system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.216179 # mshr miss rate for overall accesses 3167system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.232950 # mshr miss rate for overall accesses 3168system.l2c.overall_mshr_miss_rate::cpu1.inst 0.077247 # mshr miss rate for overall accesses 3169system.l2c.overall_mshr_miss_rate::cpu1.data 0.199302 # mshr miss rate for overall accesses 3170system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.343371 # mshr miss rate for overall accesses 3171system.l2c.overall_mshr_miss_rate::total 0.222752 # mshr miss rate for overall accesses 3172system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21610.225883 # average UpgradeReq mshr miss latency 3173system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21647.742077 # average UpgradeReq mshr miss latency 3174system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21628.441009 # average UpgradeReq mshr miss latency 3175system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24617.068902 # average SCUpgradeReq mshr miss latency 3176system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24607.448617 # average SCUpgradeReq mshr miss latency 3177system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24612.514128 # average SCUpgradeReq mshr miss latency 3178system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79236.339662 # average ReadExReq mshr miss latency 3179system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72651.227338 # average ReadExReq mshr miss latency 3180system.l2c.ReadExReq_avg_mshr_miss_latency::total 76684.798346 # average ReadExReq mshr miss latency 3181system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 78116.974708 # average ReadSharedReq mshr miss latency 3182system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 79611.427094 # average ReadSharedReq mshr miss latency 3183system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75014.327552 # average ReadSharedReq mshr miss latency 3184system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 79699.783619 # average ReadSharedReq mshr miss latency 3185system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117628.629743 # average ReadSharedReq mshr miss latency 3186system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 81637.057652 # average ReadSharedReq mshr miss latency 3187system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 82346.643219 # average ReadSharedReq mshr miss latency 3188system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 74892.092732 # average ReadSharedReq mshr miss latency 3189system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 81643.583511 # average ReadSharedReq mshr miss latency 3190system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111636.476987 # average ReadSharedReq mshr miss latency 3191system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 98118.647459 # average ReadSharedReq mshr miss latency 3192system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20918.654291 # average InvalidateReq mshr miss latency 3193system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20760.842224 # average InvalidateReq mshr miss latency 3194system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20891.805966 # average InvalidateReq mshr miss latency 3195system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78116.974708 # average overall mshr miss latency 3196system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79611.427094 # average overall mshr miss latency 3197system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75014.327552 # average overall mshr miss latency 3198system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79532.664887 # average overall mshr miss latency 3199system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117628.629743 # average overall mshr miss latency 3200system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 81637.057652 # average overall mshr miss latency 3201system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 82346.643219 # average overall mshr miss latency 3202system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74892.092732 # average overall mshr miss latency 3203system.l2c.demand_avg_mshr_miss_latency::cpu1.data 78677.910596 # average overall mshr miss latency 3204system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111636.476987 # average overall mshr miss latency 3205system.l2c.demand_avg_mshr_miss_latency::total 95060.153730 # average overall mshr miss latency 3206system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78116.974708 # average overall mshr miss latency 3207system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79611.427094 # average overall mshr miss latency 3208system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75014.327552 # average overall mshr miss latency 3209system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79532.664887 # average overall mshr miss latency 3210system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117628.629743 # average overall mshr miss latency 3211system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 81637.057652 # average overall mshr miss latency 3212system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 82346.643219 # average overall mshr miss latency 3213system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74892.092732 # average overall mshr miss latency 3214system.l2c.overall_avg_mshr_miss_latency::cpu1.data 78677.910596 # average overall mshr miss latency 3215system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111636.476987 # average overall mshr miss latency 3216system.l2c.overall_avg_mshr_miss_latency::total 95060.153730 # average overall mshr miss latency 3217system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63491.166179 # average ReadReq mshr uncacheable latency 3218system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167570.579301 # average ReadReq mshr uncacheable latency 3219system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 61849.462366 # average ReadReq mshr uncacheable latency 3220system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 94623.649229 # average ReadReq mshr uncacheable latency 3221system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 102107.944449 # average ReadReq mshr uncacheable latency 3222system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63491.166179 # average overall mshr uncacheable latency 3223system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 84420.399908 # average overall mshr uncacheable latency 3224system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 61849.462366 # average overall mshr uncacheable latency 3225system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 46177.192630 # average overall mshr uncacheable latency 3226system.l2c.overall_avg_mshr_uncacheable_latency::total 71756.492357 # average overall mshr uncacheable latency 3227system.membus.snoop_filter.tot_requests 3789204 # Total number of requests made to the snoop filter. 3228system.membus.snoop_filter.hit_single_requests 2296931 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3229system.membus.snoop_filter.hit_multi_requests 2908 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3230system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 3231system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3232system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3233system.membus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3234system.membus.trans_dist::ReadReq 91033 # Transaction distribution 3235system.membus.trans_dist::ReadResp 892432 # Transaction distribution 3236system.membus.trans_dist::WriteReq 38505 # Transaction distribution 3237system.membus.trans_dist::WriteResp 38505 # Transaction distribution 3238system.membus.trans_dist::WritebackDirty 1181777 # Transaction distribution 3239system.membus.trans_dist::CleanEvict 252869 # Transaction distribution 3240system.membus.trans_dist::UpgradeReq 437143 # Transaction distribution 3241system.membus.trans_dist::SCUpgradeReq 308404 # Transaction distribution 3242system.membus.trans_dist::UpgradeResp 22 # Transaction distribution 3243system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution 3244system.membus.trans_dist::ReadExReq 143945 # Transaction distribution 3245system.membus.trans_dist::ReadExResp 126263 # Transaction distribution 3246system.membus.trans_dist::ReadSharedReq 801399 # Transaction distribution 3247system.membus.trans_dist::InvalidateReq 663637 # Transaction distribution 3248system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122598 # Packet count per connected master and slave (bytes) 3249system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) 3250system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26474 # Packet count per connected master and slave (bytes) 3251system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4585882 # Packet count per connected master and slave (bytes) 3252system.membus.pkt_count_system.l2c.mem_side::total 4735006 # Packet count per connected master and slave (bytes) 3253system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238206 # Packet count per connected master and slave (bytes) 3254system.membus.pkt_count_system.iocache.mem_side::total 238206 # Packet count per connected master and slave (bytes) 3255system.membus.pkt_count::total 4973212 # Packet count per connected master and slave (bytes) 3256system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155705 # Cumulative packet size per connected master and slave (bytes) 3257system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) 3258system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52948 # Cumulative packet size per connected master and slave (bytes) 3259system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 130931136 # Cumulative packet size per connected master and slave (bytes) 3260system.membus.pkt_size_system.l2c.mem_side::total 131141113 # Cumulative packet size per connected master and slave (bytes) 3261system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7272704 # Cumulative packet size per connected master and slave (bytes) 3262system.membus.pkt_size_system.iocache.mem_side::total 7272704 # Cumulative packet size per connected master and slave (bytes) 3263system.membus.pkt_size::total 138413817 # Cumulative packet size per connected master and slave (bytes) 3264system.membus.snoops 608511 # Total snoops (count) 3265system.membus.snoop_fanout::samples 2484071 # Request fanout histogram 3266system.membus.snoop_fanout::mean 0.012278 # Request fanout histogram 3267system.membus.snoop_fanout::stdev 0.110125 # Request fanout histogram 3268system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3269system.membus.snoop_fanout::0 2453571 98.77% 98.77% # Request fanout histogram 3270system.membus.snoop_fanout::1 30500 1.23% 100.00% # Request fanout histogram 3271system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3272system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3273system.membus.snoop_fanout::min_value 0 # Request fanout histogram 3274system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3275system.membus.snoop_fanout::total 2484071 # Request fanout histogram 3276system.membus.reqLayer0.occupancy 105594995 # Layer occupancy (ticks) 3277system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3278system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks) 3279system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3280system.membus.reqLayer2.occupancy 22316500 # Layer occupancy (ticks) 3281system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3282system.membus.reqLayer5.occupancy 8304045809 # Layer occupancy (ticks) 3283system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3284system.membus.respLayer2.occupancy 5231778477 # Layer occupancy (ticks) 3285system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3286system.membus.respLayer3.occupancy 45499333 # Layer occupancy (ticks) 3287system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3288system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3289system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3290system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3291system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3292system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3293system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3294system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3295system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3296system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3297system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3298system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3299system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3300system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3301system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3302system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3303system.realview.ethernet.txBytes 966 # Bytes Transmitted 3304system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3305system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3306system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3307system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3308system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3309system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3310system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3311system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3312system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 3313system.realview.ethernet.totPackets 3 # Total Packets 3314system.realview.ethernet.totBytes 966 # Total Bytes 3315system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 3316system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 3317system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 3318system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3319system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 3320system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3321system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3322system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 3323system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3324system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3325system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 3326system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3327system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3328system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 3329system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3330system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3331system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 3332system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3333system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3334system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 3335system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3336system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3337system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3338system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3339system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3340system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3341system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3342system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3343system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3344system.realview.ethernet.droppedPackets 0 # number of packets dropped 3345system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3346system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3347system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3348system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3349system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3350system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3351system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3352system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3353system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3354system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3355system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3356system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3357system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3358system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3359system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3360system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3361system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3362system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3363system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3364system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3365system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3366system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3367system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3368system.toL2Bus.snoop_filter.tot_requests 12326432 # Total number of requests made to the snoop filter. 3369system.toL2Bus.snoop_filter.hit_single_requests 6670511 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3370system.toL2Bus.snoop_filter.hit_multi_requests 2086069 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3371system.toL2Bus.snoop_filter.tot_snoops 130580 # Total number of snoops made to the snoop filter. 3372system.toL2Bus.snoop_filter.hit_single_snoops 118652 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3373system.toL2Bus.snoop_filter.hit_multi_snoops 11928 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3374system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3375system.toL2Bus.trans_dist::ReadReq 91035 # Transaction distribution 3376system.toL2Bus.trans_dist::ReadResp 4782322 # Transaction distribution 3377system.toL2Bus.trans_dist::WriteReq 38505 # Transaction distribution 3378system.toL2Bus.trans_dist::WriteResp 38505 # Transaction distribution 3379system.toL2Bus.trans_dist::WritebackDirty 3822609 # Transaction distribution 3380system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution 3381system.toL2Bus.trans_dist::CleanEvict 2941580 # Transaction distribution 3382system.toL2Bus.trans_dist::UpgradeReq 730122 # Transaction distribution 3383system.toL2Bus.trans_dist::SCUpgradeReq 388189 # Transaction distribution 3384system.toL2Bus.trans_dist::UpgradeResp 1118311 # Transaction distribution 3385system.toL2Bus.trans_dist::SCUpgradeFailReq 111 # Transaction distribution 3386system.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution 3387system.toL2Bus.trans_dist::ReadExReq 299700 # Transaction distribution 3388system.toL2Bus.trans_dist::ReadExResp 299700 # Transaction distribution 3389system.toL2Bus.trans_dist::ReadSharedReq 4691812 # Transaction distribution 3390system.toL2Bus.trans_dist::InvalidateReq 853093 # Transaction distribution 3391system.toL2Bus.trans_dist::InvalidateResp 825528 # Transaction distribution 3392system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10130133 # Packet count per connected master and slave (bytes) 3393system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7962376 # Packet count per connected master and slave (bytes) 3394system.toL2Bus.pkt_count::total 18092509 # Packet count per connected master and slave (bytes) 3395system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 250257116 # Cumulative packet size per connected master and slave (bytes) 3396system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 194861853 # Cumulative packet size per connected master and slave (bytes) 3397system.toL2Bus.pkt_size::total 445118969 # Cumulative packet size per connected master and slave (bytes) 3398system.toL2Bus.snoops 2830390 # Total snoops (count) 3399system.toL2Bus.snoop_fanout::samples 8463866 # Request fanout histogram 3400system.toL2Bus.snoop_fanout::mean 0.368667 # Request fanout histogram 3401system.toL2Bus.snoop_fanout::stdev 0.485356 # Request fanout histogram 3402system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3403system.toL2Bus.snoop_fanout::0 5355444 63.27% 63.27% # Request fanout histogram 3404system.toL2Bus.snoop_fanout::1 3096494 36.58% 99.86% # Request fanout histogram 3405system.toL2Bus.snoop_fanout::2 11928 0.14% 100.00% # Request fanout histogram 3406system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3407system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3408system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3409system.toL2Bus.snoop_fanout::total 8463866 # Request fanout histogram 3410system.toL2Bus.reqLayer0.occupancy 9400124055 # Layer occupancy (ticks) 3411system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3412system.toL2Bus.snoopLayer0.occupancy 2566916 # Layer occupancy (ticks) 3413system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3414system.toL2Bus.respLayer0.occupancy 4651836575 # Layer occupancy (ticks) 3415system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3416system.toL2Bus.respLayer1.occupancy 3960751843 # Layer occupancy (ticks) 3417system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3418 3419---------- End Simulation Statistics ---------- 3420