stats.txt revision 10944
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.411962 # Number of seconds simulated 4sim_ticks 47411962285000 # Number of ticks simulated 5final_tick 47411962285000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 170497 # Simulator instruction rate (inst/s) 8host_op_rate 200546 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9509503550 # Simulator tick rate (ticks/s) 10host_mem_usage 769500 # Number of bytes of host memory used 11host_seconds 4985.75 # Real time elapsed on the host 12sim_insts 850056300 # Number of instructions simulated 13sim_ops 999871495 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 75328 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 71168 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 7498816 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 38111304 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 10728384 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 51264 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 47808 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 2878784 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 12174608 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 7747264 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 431104 # Number of bytes read from this memory 27system.physmem.bytes_read::total 79815832 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 7498816 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 2878784 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 10377600 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 62807296 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 34system.physmem.bytes_written::total 62827880 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 1177 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 1112 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 117169 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 595502 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 167631 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 801 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 747 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 44981 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 190241 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 121051 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 6736 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 1247148 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 981364 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 50system.physmem.num_writes::total 983938 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 1589 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 1501 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 158163 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 803833 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 226280 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 1081 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 1008 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 60719 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 256783 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 163403 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 9093 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 1683453 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 158163 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 60719 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 218881 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 1324714 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::total 1325148 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 1324714 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 1589 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 1501 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 158163 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 804267 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 226280 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 1081 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 1008 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 60719 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 256784 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 163403 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 9093 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 3008602 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 1247148 # Number of read requests accepted 84system.physmem.writeReqs 983938 # Number of write requests accepted 85system.physmem.readBursts 1247148 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 983938 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 79775360 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 42112 # Total number of bytes read from write queue 89system.physmem.bytesWritten 62826240 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 79815832 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 62827880 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 658 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 218244 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 71187 # Per bank write bursts 96system.physmem.perBankRdBursts::1 77028 # Per bank write bursts 97system.physmem.perBankRdBursts::2 72273 # Per bank write bursts 98system.physmem.perBankRdBursts::3 78219 # Per bank write bursts 99system.physmem.perBankRdBursts::4 70385 # Per bank write bursts 100system.physmem.perBankRdBursts::5 81119 # Per bank write bursts 101system.physmem.perBankRdBursts::6 72267 # Per bank write bursts 102system.physmem.perBankRdBursts::7 76746 # Per bank write bursts 103system.physmem.perBankRdBursts::8 71370 # Per bank write bursts 104system.physmem.perBankRdBursts::9 123762 # Per bank write bursts 105system.physmem.perBankRdBursts::10 72044 # Per bank write bursts 106system.physmem.perBankRdBursts::11 80747 # Per bank write bursts 107system.physmem.perBankRdBursts::12 73100 # Per bank write bursts 108system.physmem.perBankRdBursts::13 79351 # Per bank write bursts 109system.physmem.perBankRdBursts::14 74612 # Per bank write bursts 110system.physmem.perBankRdBursts::15 72280 # Per bank write bursts 111system.physmem.perBankWrBursts::0 58860 # Per bank write bursts 112system.physmem.perBankWrBursts::1 62909 # Per bank write bursts 113system.physmem.perBankWrBursts::2 59749 # Per bank write bursts 114system.physmem.perBankWrBursts::3 64358 # Per bank write bursts 115system.physmem.perBankWrBursts::4 59245 # Per bank write bursts 116system.physmem.perBankWrBursts::5 66477 # Per bank write bursts 117system.physmem.perBankWrBursts::6 59553 # Per bank write bursts 118system.physmem.perBankWrBursts::7 62082 # Per bank write bursts 119system.physmem.perBankWrBursts::8 58790 # Per bank write bursts 120system.physmem.perBankWrBursts::9 60994 # Per bank write bursts 121system.physmem.perBankWrBursts::10 60508 # Per bank write bursts 122system.physmem.perBankWrBursts::11 63849 # Per bank write bursts 123system.physmem.perBankWrBursts::12 60193 # Per bank write bursts 124system.physmem.perBankWrBursts::13 63756 # Per bank write bursts 125system.physmem.perBankWrBursts::14 60310 # Per bank write bursts 126system.physmem.perBankWrBursts::15 60027 # Per bank write bursts 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 128system.physmem.numWrRetry 30 # Number of times write queue was full causing retry 129system.physmem.totGap 47411960356500 # Total gap between requests 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 0 # Read request sizes (log2) 133system.physmem.readPktSize::3 25 # Read request sizes (log2) 134system.physmem.readPktSize::4 5 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) 136system.physmem.readPktSize::6 1247118 # Read request sizes (log2) 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 2 # Write request sizes (log2) 140system.physmem.writePktSize::3 2572 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) 143system.physmem.writePktSize::6 981364 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 795503 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 313068 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 30154 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 22514 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 19326 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 17861 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 16010 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 13834 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 11987 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 2659 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 1157 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 695 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 515 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 367 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 206 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 171 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 146 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 131 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 98 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 69 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 176system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::15 14920 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 17590 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 38389 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 48185 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 52683 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 54849 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 56160 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 59815 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 60639 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 63775 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 62891 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 64447 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 62663 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 63620 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 68672 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 63414 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 59849 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 57038 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 1401 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 972 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 930 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 645 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 537 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 549 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 489 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 454 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 550 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 413 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 377 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 350 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 279 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 406 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 433 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 383 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 292 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 288 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 333 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 315 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 273 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 211 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 286 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 168 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 147 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 136 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 123 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 112 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 80 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 59 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 86 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 737647 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 193.317834 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 117.156586 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 253.851861 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 435526 59.04% 59.04% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 146539 19.87% 78.91% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 49058 6.65% 85.56% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 25178 3.41% 88.97% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 15871 2.15% 91.12% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 10341 1.40% 92.53% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 7959 1.08% 93.60% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 8404 1.14% 94.74% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 38771 5.26% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 737647 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 55115 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 22.615186 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 363.032286 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-4095 55112 99.99% 99.99% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::77824-81919 1 0.00% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::total 55115 # Reads before turning the bus around for writes 262system.physmem.wrPerTurnAround::samples 55115 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::mean 17.811122 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::gmean 17.212895 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::stdev 7.489514 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::16-23 52725 95.66% 95.66% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::24-31 682 1.24% 96.90% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::32-39 764 1.39% 98.29% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::40-47 154 0.28% 98.57% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::48-55 76 0.14% 98.70% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::56-63 61 0.11% 98.82% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::64-71 472 0.86% 99.67% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::72-79 111 0.20% 99.87% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::80-87 10 0.02% 99.89% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::88-95 1 0.00% 99.89% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::96-103 8 0.01% 99.91% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::112-119 1 0.00% 99.91% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::120-127 1 0.00% 99.91% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::128-135 31 0.06% 99.97% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::136-143 2 0.00% 99.97% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::144-151 7 0.01% 99.98% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::160-167 4 0.01% 99.99% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::176-183 3 0.01% 100.00% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::264-271 2 0.00% 100.00% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::total 55115 # Writes before turning the bus around for reads 286system.physmem.totQLat 32865022462 # Total ticks spent queuing 287system.physmem.totMemAccLat 56236709962 # Total ticks spent from burst creation until serviced by the DRAM 288system.physmem.totBusLat 6232450000 # Total ticks spent in databus transfers 289system.physmem.avgQLat 26366.05 # Average queueing delay per DRAM burst 290system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 291system.physmem.avgMemAccLat 45116.05 # Average memory access latency per DRAM burst 292system.physmem.avgRdBW 1.68 # Average DRAM read bandwidth in MiByte/s 293system.physmem.avgWrBW 1.33 # Average achieved write bandwidth in MiByte/s 294system.physmem.avgRdBWSys 1.68 # Average system read bandwidth in MiByte/s 295system.physmem.avgWrBWSys 1.33 # Average system write bandwidth in MiByte/s 296system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 297system.physmem.busUtil 0.02 # Data bus utilization in percentage 298system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 299system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 300system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing 301system.physmem.avgWrQLen 23.59 # Average write queue length when enqueuing 302system.physmem.readRowHits 1009662 # Number of row buffer hits during reads 303system.physmem.writeRowHits 480836 # Number of row buffer hits during writes 304system.physmem.readRowHitRate 81.00 # Row buffer hit rate for reads 305system.physmem.writeRowHitRate 48.98 # Row buffer hit rate for writes 306system.physmem.avgGap 21250619.81 # Average gap between requests 307system.physmem.pageHitRate 66.89 # Row buffer hit rate, read and write combined 308system.physmem_0.actEnergy 2808479520 # Energy for activate commands per rank (pJ) 309system.physmem_0.preEnergy 1532404500 # Energy for precharge commands per rank (pJ) 310system.physmem_0.readEnergy 4673861400 # Energy for read commands per rank (pJ) 311system.physmem_0.writeEnergy 3196149840 # Energy for write commands per rank (pJ) 312system.physmem_0.refreshEnergy 3096718466400 # Energy for refresh commands per rank (pJ) 313system.physmem_0.actBackEnergy 1173181763970 # Energy for active background per rank (pJ) 314system.physmem_0.preBackEnergy 27418066728000 # Energy for precharge background per rank (pJ) 315system.physmem_0.totalEnergy 31700177853630 # Total energy per rank (pJ) 316system.physmem_0.averagePower 668.611477 # Core power per rank (mW) 317system.physmem_0.memoryStateTime::IDLE 45611956984095 # Time in different power states 318system.physmem_0.memoryStateTime::REF 1583189400000 # Time in different power states 319system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 320system.physmem_0.memoryStateTime::ACT 216810169905 # Time in different power states 321system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 322system.physmem_1.actEnergy 2768124240 # Energy for activate commands per rank (pJ) 323system.physmem_1.preEnergy 1510385250 # Energy for precharge commands per rank (pJ) 324system.physmem_1.readEnergy 5048596800 # Energy for read commands per rank (pJ) 325system.physmem_1.writeEnergy 3165006960 # Energy for write commands per rank (pJ) 326system.physmem_1.refreshEnergy 3096718466400 # Energy for refresh commands per rank (pJ) 327system.physmem_1.actBackEnergy 1175060323800 # Energy for active background per rank (pJ) 328system.physmem_1.preBackEnergy 27416418868500 # Energy for precharge background per rank (pJ) 329system.physmem_1.totalEnergy 31700689771950 # Total energy per rank (pJ) 330system.physmem_1.averagePower 668.622274 # Core power per rank (mW) 331system.physmem_1.memoryStateTime::IDLE 45609169557313 # Time in different power states 332system.physmem_1.memoryStateTime::REF 1583189400000 # Time in different power states 333system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 334system.physmem_1.memoryStateTime::ACT 219597434187 # Time in different power states 335system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 336system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory 337system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 338system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory 339system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 340system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory 341system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory 342system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory 343system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory 344system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory 345system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 346system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory 347system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 348system.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory 349system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) 350system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 351system.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s) 352system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 353system.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s) 354system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) 355system.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s) 356system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) 357system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) 358system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 359system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s) 360system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 361system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) 362system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 363system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 364system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 365system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. 366system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. 367system.cf0.dma_write_txs 1674 # Number of DMA write transactions. 368system.cpu0.branchPred.lookups 130279608 # Number of BP lookups 369system.cpu0.branchPred.condPredicted 91518189 # Number of conditional branches predicted 370system.cpu0.branchPred.condIncorrect 6235368 # Number of conditional branches incorrect 371system.cpu0.branchPred.BTBLookups 97695080 # Number of BTB lookups 372system.cpu0.branchPred.BTBHits 70156250 # Number of BTB hits 373system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 374system.cpu0.branchPred.BTBHitPct 71.811446 # BTB Hit Percentage 375system.cpu0.branchPred.usedRAS 15568853 # Number of times the RAS was used to get a target. 376system.cpu0.branchPred.RASInCorrect 1041049 # Number of incorrect RAS predictions. 377system.cpu_clk_domain.clock 500 # Clock period in ticks 378system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 379system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 380system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 381system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 382system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 383system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 384system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 385system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 386system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 387system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 388system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 389system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 390system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 391system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 392system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 393system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 394system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 395system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 396system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 397system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 398system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 399system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 400system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 401system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 402system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 403system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 404system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 405system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 406system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 407system.cpu0.dtb.walker.walks 272738 # Table walker walks requested 408system.cpu0.dtb.walker.walksLong 272738 # Table walker walks initiated with long descriptors 409system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8357 # Level at which table walker walks with long descriptors terminate 410system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 77299 # Level at which table walker walks with long descriptors terminate 411system.cpu0.dtb.walker.walkWaitTime::samples 272738 # Table walker wait (enqueue to first request) latency 412system.cpu0.dtb.walker.walkWaitTime::0 272738 100.00% 100.00% # Table walker wait (enqueue to first request) latency 413system.cpu0.dtb.walker.walkWaitTime::total 272738 # Table walker wait (enqueue to first request) latency 414system.cpu0.dtb.walker.walkCompletionTime::samples 85656 # Table walker service (enqueue to completion) latency 415system.cpu0.dtb.walker.walkCompletionTime::mean 20319.907537 # Table walker service (enqueue to completion) latency 416system.cpu0.dtb.walker.walkCompletionTime::gmean 18687.643521 # Table walker service (enqueue to completion) latency 417system.cpu0.dtb.walker.walkCompletionTime::stdev 12933.686898 # Table walker service (enqueue to completion) latency 418system.cpu0.dtb.walker.walkCompletionTime::0-65535 84887 99.10% 99.10% # Table walker service (enqueue to completion) latency 419system.cpu0.dtb.walker.walkCompletionTime::65536-131071 657 0.77% 99.87% # Table walker service (enqueue to completion) latency 420system.cpu0.dtb.walker.walkCompletionTime::131072-196607 28 0.03% 99.90% # Table walker service (enqueue to completion) latency 421system.cpu0.dtb.walker.walkCompletionTime::196608-262143 42 0.05% 99.95% # Table walker service (enqueue to completion) latency 422system.cpu0.dtb.walker.walkCompletionTime::262144-327679 27 0.03% 99.98% # Table walker service (enqueue to completion) latency 423system.cpu0.dtb.walker.walkCompletionTime::327680-393215 12 0.01% 100.00% # Table walker service (enqueue to completion) latency 424system.cpu0.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 425system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 426system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 427system.cpu0.dtb.walker.walkCompletionTime::total 85656 # Table walker service (enqueue to completion) latency 428system.cpu0.dtb.walker.walksPending::samples 669754704 # Table walker pending requests distribution 429system.cpu0.dtb.walker.walksPending::0 669754704 100.00% 100.00% # Table walker pending requests distribution 430system.cpu0.dtb.walker.walksPending::total 669754704 # Table walker pending requests distribution 431system.cpu0.dtb.walker.walkPageSizes::4K 77299 90.24% 90.24% # Table walker page sizes translated 432system.cpu0.dtb.walker.walkPageSizes::2M 8357 9.76% 100.00% # Table walker page sizes translated 433system.cpu0.dtb.walker.walkPageSizes::total 85656 # Table walker page sizes translated 434system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 272738 # Table walker requests started/completed, data/inst 435system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 436system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 272738 # Table walker requests started/completed, data/inst 437system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85656 # Table walker requests started/completed, data/inst 438system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 439system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85656 # Table walker requests started/completed, data/inst 440system.cpu0.dtb.walker.walkRequestOrigin::total 358394 # Table walker requests started/completed, data/inst 441system.cpu0.dtb.inst_hits 0 # ITB inst hits 442system.cpu0.dtb.inst_misses 0 # ITB inst misses 443system.cpu0.dtb.read_hits 83911764 # DTB read hits 444system.cpu0.dtb.read_misses 226051 # DTB read misses 445system.cpu0.dtb.write_hits 74892635 # DTB write hits 446system.cpu0.dtb.write_misses 46687 # DTB write misses 447system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 448system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 449system.cpu0.dtb.flush_tlb_mva_asid 38178 # Number of times TLB was flushed by MVA & ASID 450system.cpu0.dtb.flush_tlb_asid 1015 # Number of times TLB was flushed by ASID 451system.cpu0.dtb.flush_entries 35474 # Number of entries that have been flushed from TLB 452system.cpu0.dtb.align_faults 1932 # Number of TLB faults due to alignment restrictions 453system.cpu0.dtb.prefetch_faults 8858 # Number of TLB faults due to prefetch 454system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 455system.cpu0.dtb.perms_faults 11487 # Number of TLB faults due to permissions restrictions 456system.cpu0.dtb.read_accesses 84137815 # DTB read accesses 457system.cpu0.dtb.write_accesses 74939322 # DTB write accesses 458system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 459system.cpu0.dtb.hits 158804399 # DTB hits 460system.cpu0.dtb.misses 272738 # DTB misses 461system.cpu0.dtb.accesses 159077137 # DTB accesses 462system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 463system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 464system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 465system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 466system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 467system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 468system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 469system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 470system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 471system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 472system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 473system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 474system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 475system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 476system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 477system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 478system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 479system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 480system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 481system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 482system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 483system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 484system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 485system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 486system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 487system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 488system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 489system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 490system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 491system.cpu0.itb.walker.walks 68078 # Table walker walks requested 492system.cpu0.itb.walker.walksLong 68078 # Table walker walks initiated with long descriptors 493system.cpu0.itb.walker.walksLongTerminationLevel::Level2 722 # Level at which table walker walks with long descriptors terminate 494system.cpu0.itb.walker.walksLongTerminationLevel::Level3 61066 # Level at which table walker walks with long descriptors terminate 495system.cpu0.itb.walker.walkWaitTime::samples 68078 # Table walker wait (enqueue to first request) latency 496system.cpu0.itb.walker.walkWaitTime::0 68078 100.00% 100.00% # Table walker wait (enqueue to first request) latency 497system.cpu0.itb.walker.walkWaitTime::total 68078 # Table walker wait (enqueue to first request) latency 498system.cpu0.itb.walker.walkCompletionTime::samples 61788 # Table walker service (enqueue to completion) latency 499system.cpu0.itb.walker.walkCompletionTime::mean 22737.489480 # Table walker service (enqueue to completion) latency 500system.cpu0.itb.walker.walkCompletionTime::gmean 21008.732396 # Table walker service (enqueue to completion) latency 501system.cpu0.itb.walker.walkCompletionTime::stdev 13692.086470 # Table walker service (enqueue to completion) latency 502system.cpu0.itb.walker.walkCompletionTime::0-32767 57025 92.29% 92.29% # Table walker service (enqueue to completion) latency 503system.cpu0.itb.walker.walkCompletionTime::32768-65535 3907 6.32% 98.61% # Table walker service (enqueue to completion) latency 504system.cpu0.itb.walker.walkCompletionTime::65536-98303 284 0.46% 99.07% # Table walker service (enqueue to completion) latency 505system.cpu0.itb.walker.walkCompletionTime::98304-131071 503 0.81% 99.89% # Table walker service (enqueue to completion) latency 506system.cpu0.itb.walker.walkCompletionTime::131072-163839 12 0.02% 99.91% # Table walker service (enqueue to completion) latency 507system.cpu0.itb.walker.walkCompletionTime::163840-196607 9 0.01% 99.92% # Table walker service (enqueue to completion) latency 508system.cpu0.itb.walker.walkCompletionTime::196608-229375 25 0.04% 99.96% # Table walker service (enqueue to completion) latency 509system.cpu0.itb.walker.walkCompletionTime::229376-262143 7 0.01% 99.97% # Table walker service (enqueue to completion) latency 510system.cpu0.itb.walker.walkCompletionTime::262144-294911 3 0.00% 99.98% # Table walker service (enqueue to completion) latency 511system.cpu0.itb.walker.walkCompletionTime::294912-327679 6 0.01% 99.99% # Table walker service (enqueue to completion) latency 512system.cpu0.itb.walker.walkCompletionTime::327680-360447 2 0.00% 99.99% # Table walker service (enqueue to completion) latency 513system.cpu0.itb.walker.walkCompletionTime::360448-393215 5 0.01% 100.00% # Table walker service (enqueue to completion) latency 514system.cpu0.itb.walker.walkCompletionTime::total 61788 # Table walker service (enqueue to completion) latency 515system.cpu0.itb.walker.walksPending::samples 669040204 # Table walker pending requests distribution 516system.cpu0.itb.walker.walksPending::0 669040204 100.00% 100.00% # Table walker pending requests distribution 517system.cpu0.itb.walker.walksPending::total 669040204 # Table walker pending requests distribution 518system.cpu0.itb.walker.walkPageSizes::4K 61066 98.83% 98.83% # Table walker page sizes translated 519system.cpu0.itb.walker.walkPageSizes::2M 722 1.17% 100.00% # Table walker page sizes translated 520system.cpu0.itb.walker.walkPageSizes::total 61788 # Table walker page sizes translated 521system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 522system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 68078 # Table walker requests started/completed, data/inst 523system.cpu0.itb.walker.walkRequestOrigin_Requested::total 68078 # Table walker requests started/completed, data/inst 524system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 525system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 61788 # Table walker requests started/completed, data/inst 526system.cpu0.itb.walker.walkRequestOrigin_Completed::total 61788 # Table walker requests started/completed, data/inst 527system.cpu0.itb.walker.walkRequestOrigin::total 129866 # Table walker requests started/completed, data/inst 528system.cpu0.itb.inst_hits 232943519 # ITB inst hits 529system.cpu0.itb.inst_misses 68078 # ITB inst misses 530system.cpu0.itb.read_hits 0 # DTB read hits 531system.cpu0.itb.read_misses 0 # DTB read misses 532system.cpu0.itb.write_hits 0 # DTB write hits 533system.cpu0.itb.write_misses 0 # DTB write misses 534system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 535system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 536system.cpu0.itb.flush_tlb_mva_asid 38178 # Number of times TLB was flushed by MVA & ASID 537system.cpu0.itb.flush_tlb_asid 1015 # Number of times TLB was flushed by ASID 538system.cpu0.itb.flush_entries 25164 # Number of entries that have been flushed from TLB 539system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 540system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 541system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 542system.cpu0.itb.perms_faults 198596 # Number of TLB faults due to permissions restrictions 543system.cpu0.itb.read_accesses 0 # DTB read accesses 544system.cpu0.itb.write_accesses 0 # DTB write accesses 545system.cpu0.itb.inst_accesses 233011597 # ITB inst accesses 546system.cpu0.itb.hits 232943519 # DTB hits 547system.cpu0.itb.misses 68078 # DTB misses 548system.cpu0.itb.accesses 233011597 # DTB accesses 549system.cpu0.numCycles 944358949 # number of cpu cycles simulated 550system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 551system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 552system.cpu0.committedInsts 433389926 # Number of instructions committed 553system.cpu0.committedOps 509312382 # Number of ops (including micro ops) committed 554system.cpu0.discardedOps 43329563 # Number of ops (including micro ops) which were discarded before commit 555system.cpu0.numFetchSuspends 4813 # Number of times Execute suspended instruction fetching 556system.cpu0.quiesceCycles 93880363578 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 557system.cpu0.cpi 2.179005 # CPI: cycles per instruction 558system.cpu0.ipc 0.458925 # IPC: instructions per cycle 559system.cpu0.kern.inst.arm 0 # number of arm instructions executed 560system.cpu0.kern.inst.quiesce 13422 # number of quiesce instructions executed 561system.cpu0.tickCycles 695520331 # Number of cycles that the object actually ticked 562system.cpu0.idleCycles 248838618 # Total number of cycles that the object has spent stopped 563system.cpu0.dcache.tags.replacements 5405789 # number of replacements 564system.cpu0.dcache.tags.tagsinuse 500.914885 # Cycle average of tags in use 565system.cpu0.dcache.tags.total_refs 150600436 # Total number of references to valid blocks. 566system.cpu0.dcache.tags.sampled_refs 5406301 # Sample count of references to valid blocks. 567system.cpu0.dcache.tags.avg_refs 27.856465 # Average number of references to valid blocks. 568system.cpu0.dcache.tags.warmup_cycle 4974406000 # Cycle when the warmup percentage was hit. 569system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.914885 # Average occupied blocks per requestor 570system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978349 # Average percentage of cache occupancy 571system.cpu0.dcache.tags.occ_percent::total 0.978349 # Average percentage of cache occupancy 572system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 573system.cpu0.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id 574system.cpu0.dcache.tags.age_task_id_blocks_1024::1 405 # Occupied blocks per task id 575system.cpu0.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id 576system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 577system.cpu0.dcache.tags.tag_accesses 320300004 # Number of tag accesses 578system.cpu0.dcache.tags.data_accesses 320300004 # Number of data accesses 579system.cpu0.dcache.ReadReq_hits::cpu0.data 77010804 # number of ReadReq hits 580system.cpu0.dcache.ReadReq_hits::total 77010804 # number of ReadReq hits 581system.cpu0.dcache.WriteReq_hits::cpu0.data 69515704 # number of WriteReq hits 582system.cpu0.dcache.WriteReq_hits::total 69515704 # number of WriteReq hits 583system.cpu0.dcache.SoftPFReq_hits::cpu0.data 254236 # number of SoftPFReq hits 584system.cpu0.dcache.SoftPFReq_hits::total 254236 # number of SoftPFReq hits 585system.cpu0.dcache.WriteLineReq_hits::cpu0.data 165535 # number of WriteLineReq hits 586system.cpu0.dcache.WriteLineReq_hits::total 165535 # number of WriteLineReq hits 587system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1598340 # number of LoadLockedReq hits 588system.cpu0.dcache.LoadLockedReq_hits::total 1598340 # number of LoadLockedReq hits 589system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1577518 # number of StoreCondReq hits 590system.cpu0.dcache.StoreCondReq_hits::total 1577518 # number of StoreCondReq hits 591system.cpu0.dcache.demand_hits::cpu0.data 146526508 # number of demand (read+write) hits 592system.cpu0.dcache.demand_hits::total 146526508 # number of demand (read+write) hits 593system.cpu0.dcache.overall_hits::cpu0.data 146780744 # number of overall hits 594system.cpu0.dcache.overall_hits::total 146780744 # number of overall hits 595system.cpu0.dcache.ReadReq_misses::cpu0.data 3243116 # number of ReadReq misses 596system.cpu0.dcache.ReadReq_misses::total 3243116 # number of ReadReq misses 597system.cpu0.dcache.WriteReq_misses::cpu0.data 2266198 # number of WriteReq misses 598system.cpu0.dcache.WriteReq_misses::total 2266198 # number of WriteReq misses 599system.cpu0.dcache.SoftPFReq_misses::cpu0.data 618205 # number of SoftPFReq misses 600system.cpu0.dcache.SoftPFReq_misses::total 618205 # number of SoftPFReq misses 601system.cpu0.dcache.WriteLineReq_misses::cpu0.data 821296 # number of WriteLineReq misses 602system.cpu0.dcache.WriteLineReq_misses::total 821296 # number of WriteLineReq misses 603system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 155401 # number of LoadLockedReq misses 604system.cpu0.dcache.LoadLockedReq_misses::total 155401 # number of LoadLockedReq misses 605system.cpu0.dcache.StoreCondReq_misses::cpu0.data 174722 # number of StoreCondReq misses 606system.cpu0.dcache.StoreCondReq_misses::total 174722 # number of StoreCondReq misses 607system.cpu0.dcache.demand_misses::cpu0.data 5509314 # number of demand (read+write) misses 608system.cpu0.dcache.demand_misses::total 5509314 # number of demand (read+write) misses 609system.cpu0.dcache.overall_misses::cpu0.data 6127519 # number of overall misses 610system.cpu0.dcache.overall_misses::total 6127519 # number of overall misses 611system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 48375468500 # number of ReadReq miss cycles 612system.cpu0.dcache.ReadReq_miss_latency::total 48375468500 # number of ReadReq miss cycles 613system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 42499797000 # number of WriteReq miss cycles 614system.cpu0.dcache.WriteReq_miss_latency::total 42499797000 # number of WriteReq miss cycles 615system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 51670537000 # number of WriteLineReq miss cycles 616system.cpu0.dcache.WriteLineReq_miss_latency::total 51670537000 # number of WriteLineReq miss cycles 617system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2317304500 # number of LoadLockedReq miss cycles 618system.cpu0.dcache.LoadLockedReq_miss_latency::total 2317304500 # number of LoadLockedReq miss cycles 619system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3678685500 # number of StoreCondReq miss cycles 620system.cpu0.dcache.StoreCondReq_miss_latency::total 3678685500 # number of StoreCondReq miss cycles 621system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2406500 # number of StoreCondFailReq miss cycles 622system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2406500 # number of StoreCondFailReq miss cycles 623system.cpu0.dcache.demand_miss_latency::cpu0.data 90875265500 # number of demand (read+write) miss cycles 624system.cpu0.dcache.demand_miss_latency::total 90875265500 # number of demand (read+write) miss cycles 625system.cpu0.dcache.overall_miss_latency::cpu0.data 90875265500 # number of overall miss cycles 626system.cpu0.dcache.overall_miss_latency::total 90875265500 # number of overall miss cycles 627system.cpu0.dcache.ReadReq_accesses::cpu0.data 80253920 # number of ReadReq accesses(hits+misses) 628system.cpu0.dcache.ReadReq_accesses::total 80253920 # number of ReadReq accesses(hits+misses) 629system.cpu0.dcache.WriteReq_accesses::cpu0.data 71781902 # number of WriteReq accesses(hits+misses) 630system.cpu0.dcache.WriteReq_accesses::total 71781902 # number of WriteReq accesses(hits+misses) 631system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 872441 # number of SoftPFReq accesses(hits+misses) 632system.cpu0.dcache.SoftPFReq_accesses::total 872441 # number of SoftPFReq accesses(hits+misses) 633system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 986831 # number of WriteLineReq accesses(hits+misses) 634system.cpu0.dcache.WriteLineReq_accesses::total 986831 # number of WriteLineReq accesses(hits+misses) 635system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1753741 # number of LoadLockedReq accesses(hits+misses) 636system.cpu0.dcache.LoadLockedReq_accesses::total 1753741 # number of LoadLockedReq accesses(hits+misses) 637system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1752240 # number of StoreCondReq accesses(hits+misses) 638system.cpu0.dcache.StoreCondReq_accesses::total 1752240 # number of StoreCondReq accesses(hits+misses) 639system.cpu0.dcache.demand_accesses::cpu0.data 152035822 # number of demand (read+write) accesses 640system.cpu0.dcache.demand_accesses::total 152035822 # number of demand (read+write) accesses 641system.cpu0.dcache.overall_accesses::cpu0.data 152908263 # number of overall (read+write) accesses 642system.cpu0.dcache.overall_accesses::total 152908263 # number of overall (read+write) accesses 643system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040411 # miss rate for ReadReq accesses 644system.cpu0.dcache.ReadReq_miss_rate::total 0.040411 # miss rate for ReadReq accesses 645system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031571 # miss rate for WriteReq accesses 646system.cpu0.dcache.WriteReq_miss_rate::total 0.031571 # miss rate for WriteReq accesses 647system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.708592 # miss rate for SoftPFReq accesses 648system.cpu0.dcache.SoftPFReq_miss_rate::total 0.708592 # miss rate for SoftPFReq accesses 649system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.832256 # miss rate for WriteLineReq accesses 650system.cpu0.dcache.WriteLineReq_miss_rate::total 0.832256 # miss rate for WriteLineReq accesses 651system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088611 # miss rate for LoadLockedReq accesses 652system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088611 # miss rate for LoadLockedReq accesses 653system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.099714 # miss rate for StoreCondReq accesses 654system.cpu0.dcache.StoreCondReq_miss_rate::total 0.099714 # miss rate for StoreCondReq accesses 655system.cpu0.dcache.demand_miss_rate::cpu0.data 0.036237 # miss rate for demand accesses 656system.cpu0.dcache.demand_miss_rate::total 0.036237 # miss rate for demand accesses 657system.cpu0.dcache.overall_miss_rate::cpu0.data 0.040073 # miss rate for overall accesses 658system.cpu0.dcache.overall_miss_rate::total 0.040073 # miss rate for overall accesses 659system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14916.354672 # average ReadReq miss latency 660system.cpu0.dcache.ReadReq_avg_miss_latency::total 14916.354672 # average ReadReq miss latency 661system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18753.788063 # average WriteReq miss latency 662system.cpu0.dcache.WriteReq_avg_miss_latency::total 18753.788063 # average WriteReq miss latency 663system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 62913.416113 # average WriteLineReq miss latency 664system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 62913.416113 # average WriteLineReq miss latency 665system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14911.773412 # average LoadLockedReq miss latency 666system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14911.773412 # average LoadLockedReq miss latency 667system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21054.506588 # average StoreCondReq miss latency 668system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21054.506588 # average StoreCondReq miss latency 669system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 670system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 671system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16494.842280 # average overall miss latency 672system.cpu0.dcache.demand_avg_miss_latency::total 16494.842280 # average overall miss latency 673system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14830.678697 # average overall miss latency 674system.cpu0.dcache.overall_avg_miss_latency::total 14830.678697 # average overall miss latency 675system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 676system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 677system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 678system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 679system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 680system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 681system.cpu0.dcache.fast_writes 0 # number of fast writes performed 682system.cpu0.dcache.cache_copies 0 # number of cache copies performed 683system.cpu0.dcache.writebacks::writebacks 3720174 # number of writebacks 684system.cpu0.dcache.writebacks::total 3720174 # number of writebacks 685system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 395501 # number of ReadReq MSHR hits 686system.cpu0.dcache.ReadReq_mshr_hits::total 395501 # number of ReadReq MSHR hits 687system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 949612 # number of WriteReq MSHR hits 688system.cpu0.dcache.WriteReq_mshr_hits::total 949612 # number of WriteReq MSHR hits 689system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 96 # number of WriteLineReq MSHR hits 690system.cpu0.dcache.WriteLineReq_mshr_hits::total 96 # number of WriteLineReq MSHR hits 691system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 41791 # number of LoadLockedReq MSHR hits 692system.cpu0.dcache.LoadLockedReq_mshr_hits::total 41791 # number of LoadLockedReq MSHR hits 693system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 77 # number of StoreCondReq MSHR hits 694system.cpu0.dcache.StoreCondReq_mshr_hits::total 77 # number of StoreCondReq MSHR hits 695system.cpu0.dcache.demand_mshr_hits::cpu0.data 1345113 # number of demand (read+write) MSHR hits 696system.cpu0.dcache.demand_mshr_hits::total 1345113 # number of demand (read+write) MSHR hits 697system.cpu0.dcache.overall_mshr_hits::cpu0.data 1345113 # number of overall MSHR hits 698system.cpu0.dcache.overall_mshr_hits::total 1345113 # number of overall MSHR hits 699system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2847615 # number of ReadReq MSHR misses 700system.cpu0.dcache.ReadReq_mshr_misses::total 2847615 # number of ReadReq MSHR misses 701system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1316586 # number of WriteReq MSHR misses 702system.cpu0.dcache.WriteReq_mshr_misses::total 1316586 # number of WriteReq MSHR misses 703system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 612491 # number of SoftPFReq MSHR misses 704system.cpu0.dcache.SoftPFReq_mshr_misses::total 612491 # number of SoftPFReq MSHR misses 705system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 821200 # number of WriteLineReq MSHR misses 706system.cpu0.dcache.WriteLineReq_mshr_misses::total 821200 # number of WriteLineReq MSHR misses 707system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 113610 # number of LoadLockedReq MSHR misses 708system.cpu0.dcache.LoadLockedReq_mshr_misses::total 113610 # number of LoadLockedReq MSHR misses 709system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 174645 # number of StoreCondReq MSHR misses 710system.cpu0.dcache.StoreCondReq_mshr_misses::total 174645 # number of StoreCondReq MSHR misses 711system.cpu0.dcache.demand_mshr_misses::cpu0.data 4164201 # number of demand (read+write) MSHR misses 712system.cpu0.dcache.demand_mshr_misses::total 4164201 # number of demand (read+write) MSHR misses 713system.cpu0.dcache.overall_mshr_misses::cpu0.data 4776692 # number of overall MSHR misses 714system.cpu0.dcache.overall_mshr_misses::total 4776692 # number of overall MSHR misses 715system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 30167 # number of ReadReq MSHR uncacheable 716system.cpu0.dcache.ReadReq_mshr_uncacheable::total 30167 # number of ReadReq MSHR uncacheable 717system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 29885 # number of WriteReq MSHR uncacheable 718system.cpu0.dcache.WriteReq_mshr_uncacheable::total 29885 # number of WriteReq MSHR uncacheable 719system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60052 # number of overall MSHR uncacheable misses 720system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60052 # number of overall MSHR uncacheable misses 721system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 38218904500 # number of ReadReq MSHR miss cycles 722system.cpu0.dcache.ReadReq_mshr_miss_latency::total 38218904500 # number of ReadReq MSHR miss cycles 723system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 23577025500 # number of WriteReq MSHR miss cycles 724system.cpu0.dcache.WriteReq_mshr_miss_latency::total 23577025500 # number of WriteReq MSHR miss cycles 725system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13456556000 # number of SoftPFReq MSHR miss cycles 726system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13456556000 # number of SoftPFReq MSHR miss cycles 727system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 50843266000 # number of WriteLineReq MSHR miss cycles 728system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 50843266000 # number of WriteLineReq MSHR miss cycles 729system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1513106500 # number of LoadLockedReq MSHR miss cycles 730system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1513106500 # number of LoadLockedReq MSHR miss cycles 731system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3501575000 # number of StoreCondReq MSHR miss cycles 732system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3501575000 # number of StoreCondReq MSHR miss cycles 733system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2054500 # number of StoreCondFailReq MSHR miss cycles 734system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2054500 # number of StoreCondFailReq MSHR miss cycles 735system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61795930000 # number of demand (read+write) MSHR miss cycles 736system.cpu0.dcache.demand_mshr_miss_latency::total 61795930000 # number of demand (read+write) MSHR miss cycles 737system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 75252486000 # number of overall MSHR miss cycles 738system.cpu0.dcache.overall_mshr_miss_latency::total 75252486000 # number of overall MSHR miss cycles 739system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5426212000 # number of ReadReq MSHR uncacheable cycles 740system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5426212000 # number of ReadReq MSHR uncacheable cycles 741system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5134567500 # number of WriteReq MSHR uncacheable cycles 742system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5134567500 # number of WriteReq MSHR uncacheable cycles 743system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10560779500 # number of overall MSHR uncacheable cycles 744system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10560779500 # number of overall MSHR uncacheable cycles 745system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035483 # mshr miss rate for ReadReq accesses 746system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035483 # mshr miss rate for ReadReq accesses 747system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018341 # mshr miss rate for WriteReq accesses 748system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018341 # mshr miss rate for WriteReq accesses 749system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.702043 # mshr miss rate for SoftPFReq accesses 750system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.702043 # mshr miss rate for SoftPFReq accesses 751system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.832159 # mshr miss rate for WriteLineReq accesses 752system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.832159 # mshr miss rate for WriteLineReq accesses 753system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064782 # mshr miss rate for LoadLockedReq accesses 754system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064782 # mshr miss rate for LoadLockedReq accesses 755system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.099670 # mshr miss rate for StoreCondReq accesses 756system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.099670 # mshr miss rate for StoreCondReq accesses 757system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027390 # mshr miss rate for demand accesses 758system.cpu0.dcache.demand_mshr_miss_rate::total 0.027390 # mshr miss rate for demand accesses 759system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031239 # mshr miss rate for overall accesses 760system.cpu0.dcache.overall_mshr_miss_rate::total 0.031239 # mshr miss rate for overall accesses 761system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13421.373500 # average ReadReq mshr miss latency 762system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13421.373500 # average ReadReq mshr miss latency 763system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17907.698775 # average WriteReq mshr miss latency 764system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17907.698775 # average WriteReq mshr miss latency 765system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21970.210175 # average SoftPFReq mshr miss latency 766system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21970.210175 # average SoftPFReq mshr miss latency 767system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 61913.377983 # average WriteLineReq mshr miss latency 768system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 61913.377983 # average WriteLineReq mshr miss latency 769system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13318.427075 # average LoadLockedReq mshr miss latency 770system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13318.427075 # average LoadLockedReq mshr miss latency 771system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20049.672192 # average StoreCondReq mshr miss latency 772system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20049.672192 # average StoreCondReq mshr miss latency 773system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 774system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 775system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14839.804803 # average overall mshr miss latency 776system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14839.804803 # average overall mshr miss latency 777system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15754.100537 # average overall mshr miss latency 778system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15754.100537 # average overall mshr miss latency 779system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 179872.443398 # average ReadReq mshr uncacheable latency 780system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 179872.443398 # average ReadReq mshr uncacheable latency 781system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171810.858290 # average WriteReq mshr uncacheable latency 782system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171810.858290 # average WriteReq mshr uncacheable latency 783system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 175860.579165 # average overall mshr uncacheable latency 784system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 175860.579165 # average overall mshr uncacheable latency 785system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 786system.cpu0.icache.tags.replacements 9471710 # number of replacements 787system.cpu0.icache.tags.tagsinuse 511.926461 # Cycle average of tags in use 788system.cpu0.icache.tags.total_refs 223265309 # Total number of references to valid blocks. 789system.cpu0.icache.tags.sampled_refs 9472222 # Sample count of references to valid blocks. 790system.cpu0.icache.tags.avg_refs 23.570532 # Average number of references to valid blocks. 791system.cpu0.icache.tags.warmup_cycle 29829927000 # Cycle when the warmup percentage was hit. 792system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.926461 # Average occupied blocks per requestor 793system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999856 # Average percentage of cache occupancy 794system.cpu0.icache.tags.occ_percent::total 0.999856 # Average percentage of cache occupancy 795system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 796system.cpu0.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id 797system.cpu0.icache.tags.age_task_id_blocks_1024::1 346 # Occupied blocks per task id 798system.cpu0.icache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id 799system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 800system.cpu0.icache.tags.tag_accesses 474947313 # Number of tag accesses 801system.cpu0.icache.tags.data_accesses 474947313 # Number of data accesses 802system.cpu0.icache.ReadReq_hits::cpu0.inst 223265309 # number of ReadReq hits 803system.cpu0.icache.ReadReq_hits::total 223265309 # number of ReadReq hits 804system.cpu0.icache.demand_hits::cpu0.inst 223265309 # number of demand (read+write) hits 805system.cpu0.icache.demand_hits::total 223265309 # number of demand (read+write) hits 806system.cpu0.icache.overall_hits::cpu0.inst 223265309 # number of overall hits 807system.cpu0.icache.overall_hits::total 223265309 # number of overall hits 808system.cpu0.icache.ReadReq_misses::cpu0.inst 9472232 # number of ReadReq misses 809system.cpu0.icache.ReadReq_misses::total 9472232 # number of ReadReq misses 810system.cpu0.icache.demand_misses::cpu0.inst 9472232 # number of demand (read+write) misses 811system.cpu0.icache.demand_misses::total 9472232 # number of demand (read+write) misses 812system.cpu0.icache.overall_misses::cpu0.inst 9472232 # number of overall misses 813system.cpu0.icache.overall_misses::total 9472232 # number of overall misses 814system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 93317915500 # number of ReadReq miss cycles 815system.cpu0.icache.ReadReq_miss_latency::total 93317915500 # number of ReadReq miss cycles 816system.cpu0.icache.demand_miss_latency::cpu0.inst 93317915500 # number of demand (read+write) miss cycles 817system.cpu0.icache.demand_miss_latency::total 93317915500 # number of demand (read+write) miss cycles 818system.cpu0.icache.overall_miss_latency::cpu0.inst 93317915500 # number of overall miss cycles 819system.cpu0.icache.overall_miss_latency::total 93317915500 # number of overall miss cycles 820system.cpu0.icache.ReadReq_accesses::cpu0.inst 232737541 # number of ReadReq accesses(hits+misses) 821system.cpu0.icache.ReadReq_accesses::total 232737541 # number of ReadReq accesses(hits+misses) 822system.cpu0.icache.demand_accesses::cpu0.inst 232737541 # number of demand (read+write) accesses 823system.cpu0.icache.demand_accesses::total 232737541 # number of demand (read+write) accesses 824system.cpu0.icache.overall_accesses::cpu0.inst 232737541 # number of overall (read+write) accesses 825system.cpu0.icache.overall_accesses::total 232737541 # number of overall (read+write) accesses 826system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.040699 # miss rate for ReadReq accesses 827system.cpu0.icache.ReadReq_miss_rate::total 0.040699 # miss rate for ReadReq accesses 828system.cpu0.icache.demand_miss_rate::cpu0.inst 0.040699 # miss rate for demand accesses 829system.cpu0.icache.demand_miss_rate::total 0.040699 # miss rate for demand accesses 830system.cpu0.icache.overall_miss_rate::cpu0.inst 0.040699 # miss rate for overall accesses 831system.cpu0.icache.overall_miss_rate::total 0.040699 # miss rate for overall accesses 832system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9851.734575 # average ReadReq miss latency 833system.cpu0.icache.ReadReq_avg_miss_latency::total 9851.734575 # average ReadReq miss latency 834system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9851.734575 # average overall miss latency 835system.cpu0.icache.demand_avg_miss_latency::total 9851.734575 # average overall miss latency 836system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9851.734575 # average overall miss latency 837system.cpu0.icache.overall_avg_miss_latency::total 9851.734575 # average overall miss latency 838system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 839system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 840system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 841system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 842system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 843system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 844system.cpu0.icache.fast_writes 0 # number of fast writes performed 845system.cpu0.icache.cache_copies 0 # number of cache copies performed 846system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9472232 # number of ReadReq MSHR misses 847system.cpu0.icache.ReadReq_mshr_misses::total 9472232 # number of ReadReq MSHR misses 848system.cpu0.icache.demand_mshr_misses::cpu0.inst 9472232 # number of demand (read+write) MSHR misses 849system.cpu0.icache.demand_mshr_misses::total 9472232 # number of demand (read+write) MSHR misses 850system.cpu0.icache.overall_mshr_misses::cpu0.inst 9472232 # number of overall MSHR misses 851system.cpu0.icache.overall_mshr_misses::total 9472232 # number of overall MSHR misses 852system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52292 # number of ReadReq MSHR uncacheable 853system.cpu0.icache.ReadReq_mshr_uncacheable::total 52292 # number of ReadReq MSHR uncacheable 854system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52292 # number of overall MSHR uncacheable misses 855system.cpu0.icache.overall_mshr_uncacheable_misses::total 52292 # number of overall MSHR uncacheable misses 856system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 88581800000 # number of ReadReq MSHR miss cycles 857system.cpu0.icache.ReadReq_mshr_miss_latency::total 88581800000 # number of ReadReq MSHR miss cycles 858system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 88581800000 # number of demand (read+write) MSHR miss cycles 859system.cpu0.icache.demand_mshr_miss_latency::total 88581800000 # number of demand (read+write) MSHR miss cycles 860system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 88581800000 # number of overall MSHR miss cycles 861system.cpu0.icache.overall_mshr_miss_latency::total 88581800000 # number of overall MSHR miss cycles 862system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4777780500 # number of ReadReq MSHR uncacheable cycles 863system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4777780500 # number of ReadReq MSHR uncacheable cycles 864system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4777780500 # number of overall MSHR uncacheable cycles 865system.cpu0.icache.overall_mshr_uncacheable_latency::total 4777780500 # number of overall MSHR uncacheable cycles 866system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.040699 # mshr miss rate for ReadReq accesses 867system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.040699 # mshr miss rate for ReadReq accesses 868system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.040699 # mshr miss rate for demand accesses 869system.cpu0.icache.demand_mshr_miss_rate::total 0.040699 # mshr miss rate for demand accesses 870system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.040699 # mshr miss rate for overall accesses 871system.cpu0.icache.overall_mshr_miss_rate::total 0.040699 # mshr miss rate for overall accesses 872system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9351.734628 # average ReadReq mshr miss latency 873system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9351.734628 # average ReadReq mshr miss latency 874system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9351.734628 # average overall mshr miss latency 875system.cpu0.icache.demand_avg_mshr_miss_latency::total 9351.734628 # average overall mshr miss latency 876system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9351.734628 # average overall mshr miss latency 877system.cpu0.icache.overall_avg_mshr_miss_latency::total 9351.734628 # average overall mshr miss latency 878system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91367.331523 # average ReadReq mshr uncacheable latency 879system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 91367.331523 # average ReadReq mshr uncacheable latency 880system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91367.331523 # average overall mshr uncacheable latency 881system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 91367.331523 # average overall mshr uncacheable latency 882system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 883system.cpu0.l2cache.prefetcher.num_hwpf_issued 7001248 # number of hwpf issued 884system.cpu0.l2cache.prefetcher.pfIdentified 7002240 # number of prefetch candidates identified 885system.cpu0.l2cache.prefetcher.pfBufferHit 870 # number of redundant prefetches already in prefetch queue 886system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 887system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 888system.cpu0.l2cache.prefetcher.pfSpanPage 934040 # number of prefetches not generated due to page crossing 889system.cpu0.l2cache.tags.replacements 2602937 # number of replacements 890system.cpu0.l2cache.tags.tagsinuse 16189.396586 # Cycle average of tags in use 891system.cpu0.l2cache.tags.total_refs 26055882 # Total number of references to valid blocks. 892system.cpu0.l2cache.tags.sampled_refs 2619045 # Sample count of references to valid blocks. 893system.cpu0.l2cache.tags.avg_refs 9.948619 # Average number of references to valid blocks. 894system.cpu0.l2cache.tags.warmup_cycle 27364878000 # Cycle when the warmup percentage was hit. 895system.cpu0.l2cache.tags.occ_blocks::writebacks 6164.786775 # Average occupied blocks per requestor 896system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 75.653187 # Average occupied blocks per requestor 897system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 79.660205 # Average occupied blocks per requestor 898system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5461.877118 # Average occupied blocks per requestor 899system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3523.510222 # Average occupied blocks per requestor 900system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 883.909079 # Average occupied blocks per requestor 901system.cpu0.l2cache.tags.occ_percent::writebacks 0.376269 # Average percentage of cache occupancy 902system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004618 # Average percentage of cache occupancy 903system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004862 # Average percentage of cache occupancy 904system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.333367 # Average percentage of cache occupancy 905system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.215058 # Average percentage of cache occupancy 906system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.053950 # Average percentage of cache occupancy 907system.cpu0.l2cache.tags.occ_percent::total 0.988122 # Average percentage of cache occupancy 908system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1484 # Occupied blocks per task id 909system.cpu0.l2cache.tags.occ_task_id_blocks::1023 72 # Occupied blocks per task id 910system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14552 # Occupied blocks per task id 911system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 26 # Occupied blocks per task id 912system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 652 # Occupied blocks per task id 913system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 737 # Occupied blocks per task id 914system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 69 # Occupied blocks per task id 915system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 15 # Occupied blocks per task id 916system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 56 # Occupied blocks per task id 917system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id 918system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id 919system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1133 # Occupied blocks per task id 920system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5245 # Occupied blocks per task id 921system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7645 # Occupied blocks per task id 922system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 403 # Occupied blocks per task id 923system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.090576 # Percentage of cache occupancy per task id 924system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004395 # Percentage of cache occupancy per task id 925system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.888184 # Percentage of cache occupancy per task id 926system.cpu0.l2cache.tags.tag_accesses 499794711 # Number of tag accesses 927system.cpu0.l2cache.tags.data_accesses 499794711 # Number of data accesses 928system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 477670 # number of ReadReq hits 929system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 164902 # number of ReadReq hits 930system.cpu0.l2cache.ReadReq_hits::total 642572 # number of ReadReq hits 931system.cpu0.l2cache.Writeback_hits::writebacks 3720171 # number of Writeback hits 932system.cpu0.l2cache.Writeback_hits::total 3720171 # number of Writeback hits 933system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 100086 # number of UpgradeReq hits 934system.cpu0.l2cache.UpgradeReq_hits::total 100086 # number of UpgradeReq hits 935system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 33531 # number of SCUpgradeReq hits 936system.cpu0.l2cache.SCUpgradeReq_hits::total 33531 # number of SCUpgradeReq hits 937system.cpu0.l2cache.ReadExReq_hits::cpu0.data 842117 # number of ReadExReq hits 938system.cpu0.l2cache.ReadExReq_hits::total 842117 # number of ReadExReq hits 939system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 8718803 # number of ReadCleanReq hits 940system.cpu0.l2cache.ReadCleanReq_hits::total 8718803 # number of ReadCleanReq hits 941system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2638824 # number of ReadSharedReq hits 942system.cpu0.l2cache.ReadSharedReq_hits::total 2638824 # number of ReadSharedReq hits 943system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 235281 # number of InvalidateReq hits 944system.cpu0.l2cache.InvalidateReq_hits::total 235281 # number of InvalidateReq hits 945system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 477670 # number of demand (read+write) hits 946system.cpu0.l2cache.demand_hits::cpu0.itb.walker 164902 # number of demand (read+write) hits 947system.cpu0.l2cache.demand_hits::cpu0.inst 8718803 # number of demand (read+write) hits 948system.cpu0.l2cache.demand_hits::cpu0.data 3480941 # number of demand (read+write) hits 949system.cpu0.l2cache.demand_hits::total 12842316 # number of demand (read+write) hits 950system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 477670 # number of overall hits 951system.cpu0.l2cache.overall_hits::cpu0.itb.walker 164902 # number of overall hits 952system.cpu0.l2cache.overall_hits::cpu0.inst 8718803 # number of overall hits 953system.cpu0.l2cache.overall_hits::cpu0.data 3480941 # number of overall hits 954system.cpu0.l2cache.overall_hits::total 12842316 # number of overall hits 955system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10606 # number of ReadReq misses 956system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7872 # number of ReadReq misses 957system.cpu0.l2cache.ReadReq_misses::total 18478 # number of ReadReq misses 958system.cpu0.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses 959system.cpu0.l2cache.Writeback_misses::total 1 # number of Writeback misses 960system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 123653 # number of UpgradeReq misses 961system.cpu0.l2cache.UpgradeReq_misses::total 123653 # number of UpgradeReq misses 962system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 141112 # number of SCUpgradeReq misses 963system.cpu0.l2cache.SCUpgradeReq_misses::total 141112 # number of SCUpgradeReq misses 964system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses 965system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses 966system.cpu0.l2cache.ReadExReq_misses::cpu0.data 262527 # number of ReadExReq misses 967system.cpu0.l2cache.ReadExReq_misses::total 262527 # number of ReadExReq misses 968system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 753428 # number of ReadCleanReq misses 969system.cpu0.l2cache.ReadCleanReq_misses::total 753428 # number of ReadCleanReq misses 970system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 934617 # number of ReadSharedReq misses 971system.cpu0.l2cache.ReadSharedReq_misses::total 934617 # number of ReadSharedReq misses 972system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 584428 # number of InvalidateReq misses 973system.cpu0.l2cache.InvalidateReq_misses::total 584428 # number of InvalidateReq misses 974system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10606 # number of demand (read+write) misses 975system.cpu0.l2cache.demand_misses::cpu0.itb.walker 7872 # number of demand (read+write) misses 976system.cpu0.l2cache.demand_misses::cpu0.inst 753428 # number of demand (read+write) misses 977system.cpu0.l2cache.demand_misses::cpu0.data 1197144 # number of demand (read+write) misses 978system.cpu0.l2cache.demand_misses::total 1969050 # number of demand (read+write) misses 979system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10606 # number of overall misses 980system.cpu0.l2cache.overall_misses::cpu0.itb.walker 7872 # number of overall misses 981system.cpu0.l2cache.overall_misses::cpu0.inst 753428 # number of overall misses 982system.cpu0.l2cache.overall_misses::cpu0.data 1197144 # number of overall misses 983system.cpu0.l2cache.overall_misses::total 1969050 # number of overall misses 984system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 328744000 # number of ReadReq miss cycles 985system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 264590000 # number of ReadReq miss cycles 986system.cpu0.l2cache.ReadReq_miss_latency::total 593334000 # number of ReadReq miss cycles 987system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2720179500 # number of UpgradeReq miss cycles 988system.cpu0.l2cache.UpgradeReq_miss_latency::total 2720179500 # number of UpgradeReq miss cycles 989system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2942818999 # number of SCUpgradeReq miss cycles 990system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2942818999 # number of SCUpgradeReq miss cycles 991system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1986000 # number of SCUpgradeFailReq miss cycles 992system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1986000 # number of SCUpgradeFailReq miss cycles 993system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 12019318999 # number of ReadExReq miss cycles 994system.cpu0.l2cache.ReadExReq_miss_latency::total 12019318999 # number of ReadExReq miss cycles 995system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 22377694500 # number of ReadCleanReq miss cycles 996system.cpu0.l2cache.ReadCleanReq_miss_latency::total 22377694500 # number of ReadCleanReq miss cycles 997system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 30534644990 # number of ReadSharedReq miss cycles 998system.cpu0.l2cache.ReadSharedReq_miss_latency::total 30534644990 # number of ReadSharedReq miss cycles 999system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 47939774000 # number of InvalidateReq miss cycles 1000system.cpu0.l2cache.InvalidateReq_miss_latency::total 47939774000 # number of InvalidateReq miss cycles 1001system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 328744000 # number of demand (read+write) miss cycles 1002system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 264590000 # number of demand (read+write) miss cycles 1003system.cpu0.l2cache.demand_miss_latency::cpu0.inst 22377694500 # number of demand (read+write) miss cycles 1004system.cpu0.l2cache.demand_miss_latency::cpu0.data 42553963989 # number of demand (read+write) miss cycles 1005system.cpu0.l2cache.demand_miss_latency::total 65524992489 # number of demand (read+write) miss cycles 1006system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 328744000 # number of overall miss cycles 1007system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 264590000 # number of overall miss cycles 1008system.cpu0.l2cache.overall_miss_latency::cpu0.inst 22377694500 # number of overall miss cycles 1009system.cpu0.l2cache.overall_miss_latency::cpu0.data 42553963989 # number of overall miss cycles 1010system.cpu0.l2cache.overall_miss_latency::total 65524992489 # number of overall miss cycles 1011system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 488276 # number of ReadReq accesses(hits+misses) 1012system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 172774 # number of ReadReq accesses(hits+misses) 1013system.cpu0.l2cache.ReadReq_accesses::total 661050 # number of ReadReq accesses(hits+misses) 1014system.cpu0.l2cache.Writeback_accesses::writebacks 3720172 # number of Writeback accesses(hits+misses) 1015system.cpu0.l2cache.Writeback_accesses::total 3720172 # number of Writeback accesses(hits+misses) 1016system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 223739 # number of UpgradeReq accesses(hits+misses) 1017system.cpu0.l2cache.UpgradeReq_accesses::total 223739 # number of UpgradeReq accesses(hits+misses) 1018system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 174643 # number of SCUpgradeReq accesses(hits+misses) 1019system.cpu0.l2cache.SCUpgradeReq_accesses::total 174643 # number of SCUpgradeReq accesses(hits+misses) 1020system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) 1021system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) 1022system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1104644 # number of ReadExReq accesses(hits+misses) 1023system.cpu0.l2cache.ReadExReq_accesses::total 1104644 # number of ReadExReq accesses(hits+misses) 1024system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9472231 # number of ReadCleanReq accesses(hits+misses) 1025system.cpu0.l2cache.ReadCleanReq_accesses::total 9472231 # number of ReadCleanReq accesses(hits+misses) 1026system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3573441 # number of ReadSharedReq accesses(hits+misses) 1027system.cpu0.l2cache.ReadSharedReq_accesses::total 3573441 # number of ReadSharedReq accesses(hits+misses) 1028system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 819709 # number of InvalidateReq accesses(hits+misses) 1029system.cpu0.l2cache.InvalidateReq_accesses::total 819709 # number of InvalidateReq accesses(hits+misses) 1030system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 488276 # number of demand (read+write) accesses 1031system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 172774 # number of demand (read+write) accesses 1032system.cpu0.l2cache.demand_accesses::cpu0.inst 9472231 # number of demand (read+write) accesses 1033system.cpu0.l2cache.demand_accesses::cpu0.data 4678085 # number of demand (read+write) accesses 1034system.cpu0.l2cache.demand_accesses::total 14811366 # number of demand (read+write) accesses 1035system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 488276 # number of overall (read+write) accesses 1036system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 172774 # number of overall (read+write) accesses 1037system.cpu0.l2cache.overall_accesses::cpu0.inst 9472231 # number of overall (read+write) accesses 1038system.cpu0.l2cache.overall_accesses::cpu0.data 4678085 # number of overall (read+write) accesses 1039system.cpu0.l2cache.overall_accesses::total 14811366 # number of overall (read+write) accesses 1040system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.021721 # miss rate for ReadReq accesses 1041system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.045562 # miss rate for ReadReq accesses 1042system.cpu0.l2cache.ReadReq_miss_rate::total 0.027952 # miss rate for ReadReq accesses 1043system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses 1044system.cpu0.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses 1045system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.552666 # miss rate for UpgradeReq accesses 1046system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.552666 # miss rate for UpgradeReq accesses 1047system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.808003 # miss rate for SCUpgradeReq accesses 1048system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.808003 # miss rate for SCUpgradeReq accesses 1049system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1050system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1051system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.237658 # miss rate for ReadExReq accesses 1052system.cpu0.l2cache.ReadExReq_miss_rate::total 0.237658 # miss rate for ReadExReq accesses 1053system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.079541 # miss rate for ReadCleanReq accesses 1054system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.079541 # miss rate for ReadCleanReq accesses 1055system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.261545 # miss rate for ReadSharedReq accesses 1056system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.261545 # miss rate for ReadSharedReq accesses 1057system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.712970 # miss rate for InvalidateReq accesses 1058system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.712970 # miss rate for InvalidateReq accesses 1059system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.021721 # miss rate for demand accesses 1060system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.045562 # miss rate for demand accesses 1061system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.079541 # miss rate for demand accesses 1062system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.255905 # miss rate for demand accesses 1063system.cpu0.l2cache.demand_miss_rate::total 0.132942 # miss rate for demand accesses 1064system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.021721 # miss rate for overall accesses 1065system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.045562 # miss rate for overall accesses 1066system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.079541 # miss rate for overall accesses 1067system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.255905 # miss rate for overall accesses 1068system.cpu0.l2cache.overall_miss_rate::total 0.132942 # miss rate for overall accesses 1069system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 30996.039977 # average ReadReq miss latency 1070system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 33611.534553 # average ReadReq miss latency 1071system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32110.293322 # average ReadReq miss latency 1072system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21998.491747 # average UpgradeReq miss latency 1073system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21998.491747 # average UpgradeReq miss latency 1074system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20854.491461 # average SCUpgradeReq miss latency 1075system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20854.491461 # average SCUpgradeReq miss latency 1076system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 993000 # average SCUpgradeFailReq miss latency 1077system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 993000 # average SCUpgradeFailReq miss latency 1078system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 45783.172775 # average ReadExReq miss latency 1079system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 45783.172775 # average ReadExReq miss latency 1080system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 29701.171844 # average ReadCleanReq miss latency 1081system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 29701.171844 # average ReadCleanReq miss latency 1082system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32670.757102 # average ReadSharedReq miss latency 1083system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32670.757102 # average ReadSharedReq miss latency 1084system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 82028.537305 # average InvalidateReq miss latency 1085system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 82028.537305 # average InvalidateReq miss latency 1086system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 30996.039977 # average overall miss latency 1087system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 33611.534553 # average overall miss latency 1088system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 29701.171844 # average overall miss latency 1089system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35546.236701 # average overall miss latency 1090system.cpu0.l2cache.demand_avg_miss_latency::total 33277.465016 # average overall miss latency 1091system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 30996.039977 # average overall miss latency 1092system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 33611.534553 # average overall miss latency 1093system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 29701.171844 # average overall miss latency 1094system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35546.236701 # average overall miss latency 1095system.cpu0.l2cache.overall_avg_miss_latency::total 33277.465016 # average overall miss latency 1096system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1097system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1098system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1099system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1100system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1101system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1102system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1103system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1104system.cpu0.l2cache.writebacks::writebacks 1330364 # number of writebacks 1105system.cpu0.l2cache.writebacks::total 1330364 # number of writebacks 1106system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 2 # number of ReadReq MSHR hits 1107system.cpu0.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits 1108system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5123 # number of ReadExReq MSHR hits 1109system.cpu0.l2cache.ReadExReq_mshr_hits::total 5123 # number of ReadExReq MSHR hits 1110system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 12 # number of ReadCleanReq MSHR hits 1111system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 12 # number of ReadCleanReq MSHR hits 1112system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 628 # number of ReadSharedReq MSHR hits 1113system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 628 # number of ReadSharedReq MSHR hits 1114system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 2 # number of InvalidateReq MSHR hits 1115system.cpu0.l2cache.InvalidateReq_mshr_hits::total 2 # number of InvalidateReq MSHR hits 1116system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 2 # number of demand (read+write) MSHR hits 1117system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 12 # number of demand (read+write) MSHR hits 1118system.cpu0.l2cache.demand_mshr_hits::cpu0.data 5751 # number of demand (read+write) MSHR hits 1119system.cpu0.l2cache.demand_mshr_hits::total 5765 # number of demand (read+write) MSHR hits 1120system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 2 # number of overall MSHR hits 1121system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 12 # number of overall MSHR hits 1122system.cpu0.l2cache.overall_mshr_hits::cpu0.data 5751 # number of overall MSHR hits 1123system.cpu0.l2cache.overall_mshr_hits::total 5765 # number of overall MSHR hits 1124system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 10606 # number of ReadReq MSHR misses 1125system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 7870 # number of ReadReq MSHR misses 1126system.cpu0.l2cache.ReadReq_mshr_misses::total 18476 # number of ReadReq MSHR misses 1127system.cpu0.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses 1128system.cpu0.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses 1129system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 106526 # number of CleanEvict MSHR misses 1130system.cpu0.l2cache.CleanEvict_mshr_misses::total 106526 # number of CleanEvict MSHR misses 1131system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 667181 # number of HardPFReq MSHR misses 1132system.cpu0.l2cache.HardPFReq_mshr_misses::total 667181 # number of HardPFReq MSHR misses 1133system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 123653 # number of UpgradeReq MSHR misses 1134system.cpu0.l2cache.UpgradeReq_mshr_misses::total 123653 # number of UpgradeReq MSHR misses 1135system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 141112 # number of SCUpgradeReq MSHR misses 1136system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 141112 # number of SCUpgradeReq MSHR misses 1137system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses 1138system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses 1139system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 257404 # number of ReadExReq MSHR misses 1140system.cpu0.l2cache.ReadExReq_mshr_misses::total 257404 # number of ReadExReq MSHR misses 1141system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 753416 # number of ReadCleanReq MSHR misses 1142system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 753416 # number of ReadCleanReq MSHR misses 1143system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 933989 # number of ReadSharedReq MSHR misses 1144system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 933989 # number of ReadSharedReq MSHR misses 1145system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 584426 # number of InvalidateReq MSHR misses 1146system.cpu0.l2cache.InvalidateReq_mshr_misses::total 584426 # number of InvalidateReq MSHR misses 1147system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 10606 # number of demand (read+write) MSHR misses 1148system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 7870 # number of demand (read+write) MSHR misses 1149system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 753416 # number of demand (read+write) MSHR misses 1150system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1191393 # number of demand (read+write) MSHR misses 1151system.cpu0.l2cache.demand_mshr_misses::total 1963285 # number of demand (read+write) MSHR misses 1152system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 10606 # number of overall MSHR misses 1153system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 7870 # number of overall MSHR misses 1154system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 753416 # number of overall MSHR misses 1155system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1191393 # number of overall MSHR misses 1156system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 667181 # number of overall MSHR misses 1157system.cpu0.l2cache.overall_mshr_misses::total 2630466 # number of overall MSHR misses 1158system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52292 # number of ReadReq MSHR uncacheable 1159system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 30167 # number of ReadReq MSHR uncacheable 1160system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 82459 # number of ReadReq MSHR uncacheable 1161system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 29885 # number of WriteReq MSHR uncacheable 1162system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 29885 # number of WriteReq MSHR uncacheable 1163system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52292 # number of overall MSHR uncacheable misses 1164system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60052 # number of overall MSHR uncacheable misses 1165system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 112344 # number of overall MSHR uncacheable misses 1166system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 265108000 # number of ReadReq MSHR miss cycles 1167system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 217332000 # number of ReadReq MSHR miss cycles 1168system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 482440000 # number of ReadReq MSHR miss cycles 1169system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 24692938914 # number of HardPFReq MSHR miss cycles 1170system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 24692938914 # number of HardPFReq MSHR miss cycles 1171system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2507267996 # number of UpgradeReq MSHR miss cycles 1172system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2507267996 # number of UpgradeReq MSHR miss cycles 1173system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2173502999 # number of SCUpgradeReq MSHR miss cycles 1174system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2173502999 # number of SCUpgradeReq MSHR miss cycles 1175system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1716000 # number of SCUpgradeFailReq MSHR miss cycles 1176system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1716000 # number of SCUpgradeFailReq MSHR miss cycles 1177system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 9909956499 # number of ReadExReq MSHR miss cycles 1178system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 9909956499 # number of ReadExReq MSHR miss cycles 1179system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 17856881500 # number of ReadCleanReq MSHR miss cycles 1180system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 17856881500 # number of ReadCleanReq MSHR miss cycles 1181system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 24870500990 # number of ReadSharedReq MSHR miss cycles 1182system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 24870500990 # number of ReadSharedReq MSHR miss cycles 1183system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 44433114500 # number of InvalidateReq MSHR miss cycles 1184system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 44433114500 # number of InvalidateReq MSHR miss cycles 1185system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 265108000 # number of demand (read+write) MSHR miss cycles 1186system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 217332000 # number of demand (read+write) MSHR miss cycles 1187system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 17856881500 # number of demand (read+write) MSHR miss cycles 1188system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 34780457489 # number of demand (read+write) MSHR miss cycles 1189system.cpu0.l2cache.demand_mshr_miss_latency::total 53119778989 # number of demand (read+write) MSHR miss cycles 1190system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 265108000 # number of overall MSHR miss cycles 1191system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 217332000 # number of overall MSHR miss cycles 1192system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 17856881500 # number of overall MSHR miss cycles 1193system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 34780457489 # number of overall MSHR miss cycles 1194system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 24692938914 # number of overall MSHR miss cycles 1195system.cpu0.l2cache.overall_mshr_miss_latency::total 77812717903 # number of overall MSHR miss cycles 1196system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4359444500 # number of ReadReq MSHR uncacheable cycles 1197system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5184743000 # number of ReadReq MSHR uncacheable cycles 1198system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9544187500 # number of ReadReq MSHR uncacheable cycles 1199system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4910404000 # number of WriteReq MSHR uncacheable cycles 1200system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4910404000 # number of WriteReq MSHR uncacheable cycles 1201system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4359444500 # number of overall MSHR uncacheable cycles 1202system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10095147000 # number of overall MSHR uncacheable cycles 1203system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 14454591500 # number of overall MSHR uncacheable cycles 1204system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021721 # mshr miss rate for ReadReq accesses 1205system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.045551 # mshr miss rate for ReadReq accesses 1206system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.027949 # mshr miss rate for ReadReq accesses 1207system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses 1208system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses 1209system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1210system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1211system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1212system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1213system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.552666 # mshr miss rate for UpgradeReq accesses 1214system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.552666 # mshr miss rate for UpgradeReq accesses 1215system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.808003 # mshr miss rate for SCUpgradeReq accesses 1216system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.808003 # mshr miss rate for SCUpgradeReq accesses 1217system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1218system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1219system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.233020 # mshr miss rate for ReadExReq accesses 1220system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.233020 # mshr miss rate for ReadExReq accesses 1221system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.079539 # mshr miss rate for ReadCleanReq accesses 1222system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.079539 # mshr miss rate for ReadCleanReq accesses 1223system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.261370 # mshr miss rate for ReadSharedReq accesses 1224system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.261370 # mshr miss rate for ReadSharedReq accesses 1225system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.712968 # mshr miss rate for InvalidateReq accesses 1226system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.712968 # mshr miss rate for InvalidateReq accesses 1227system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021721 # mshr miss rate for demand accesses 1228system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.045551 # mshr miss rate for demand accesses 1229system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.079539 # mshr miss rate for demand accesses 1230system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.254675 # mshr miss rate for demand accesses 1231system.cpu0.l2cache.demand_mshr_miss_rate::total 0.132553 # mshr miss rate for demand accesses 1232system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021721 # mshr miss rate for overall accesses 1233system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.045551 # mshr miss rate for overall accesses 1234system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.079539 # mshr miss rate for overall accesses 1235system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.254675 # mshr miss rate for overall accesses 1236system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1237system.cpu0.l2cache.overall_mshr_miss_rate::total 0.177598 # mshr miss rate for overall accesses 1238system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24996.039977 # average ReadReq mshr miss latency 1239system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 27615.247776 # average ReadReq mshr miss latency 1240system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26111.712492 # average ReadReq mshr miss latency 1241system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 37010.854497 # average HardPFReq mshr miss latency 1242system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 37010.854497 # average HardPFReq mshr miss latency 1243system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20276.645096 # average UpgradeReq mshr miss latency 1244system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20276.645096 # average UpgradeReq mshr miss latency 1245system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15402.680134 # average SCUpgradeReq mshr miss latency 1246system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15402.680134 # average SCUpgradeReq mshr miss latency 1247system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 858000 # average SCUpgradeFailReq mshr miss latency 1248system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 858000 # average SCUpgradeFailReq mshr miss latency 1249system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38499.621214 # average ReadExReq mshr miss latency 1250system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38499.621214 # average ReadExReq mshr miss latency 1251system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 23701.224158 # average ReadCleanReq mshr miss latency 1252system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 23701.224158 # average ReadCleanReq mshr miss latency 1253system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26628.258994 # average ReadSharedReq mshr miss latency 1254system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26628.258994 # average ReadSharedReq mshr miss latency 1255system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 76028.640923 # average InvalidateReq mshr miss latency 1256system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 76028.640923 # average InvalidateReq mshr miss latency 1257system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24996.039977 # average overall mshr miss latency 1258system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 27615.247776 # average overall mshr miss latency 1259system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23701.224158 # average overall mshr miss latency 1260system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29193.102099 # average overall mshr miss latency 1261system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27056.580674 # average overall mshr miss latency 1262system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24996.039977 # average overall mshr miss latency 1263system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 27615.247776 # average overall mshr miss latency 1264system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23701.224158 # average overall mshr miss latency 1265system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29193.102099 # average overall mshr miss latency 1266system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 37010.854497 # average overall mshr miss latency 1267system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 29581.343345 # average overall mshr miss latency 1268system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83367.331523 # average ReadReq mshr uncacheable latency 1269system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171868.034607 # average ReadReq mshr uncacheable latency 1270system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 115744.642792 # average ReadReq mshr uncacheable latency 1271system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164309.988288 # average WriteReq mshr uncacheable latency 1272system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164309.988288 # average WriteReq mshr uncacheable latency 1273system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83367.331523 # average overall mshr uncacheable latency 1274system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 168106.757477 # average overall mshr uncacheable latency 1275system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 128663.671402 # average overall mshr uncacheable latency 1276system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1277system.cpu0.toL2Bus.trans_dist::ReadReq 876246 # Transaction distribution 1278system.cpu0.toL2Bus.trans_dist::ReadResp 14005082 # Transaction distribution 1279system.cpu0.toL2Bus.trans_dist::WriteReq 38305 # Transaction distribution 1280system.cpu0.toL2Bus.trans_dist::WriteResp 29885 # Transaction distribution 1281system.cpu0.toL2Bus.trans_dist::Writeback 6885213 # Transaction distribution 1282system.cpu0.toL2Bus.trans_dist::CleanEvict 13979886 # Transaction distribution 1283system.cpu0.toL2Bus.trans_dist::HardPFReq 878417 # Transaction distribution 1284system.cpu0.toL2Bus.trans_dist::UpgradeReq 473566 # Transaction distribution 1285system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 319318 # Transaction distribution 1286system.cpu0.toL2Bus.trans_dist::UpgradeResp 460407 # Transaction distribution 1287system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 62 # Transaction distribution 1288system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 105 # Transaction distribution 1289system.cpu0.toL2Bus.trans_dist::ReadExReq 1465787 # Transaction distribution 1290system.cpu0.toL2Bus.trans_dist::ReadExResp 1113779 # Transaction distribution 1291system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9472232 # Transaction distribution 1292system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5781099 # Transaction distribution 1293system.cpu0.toL2Bus.trans_dist::InvalidateReq 926693 # Transaction distribution 1294system.cpu0.toL2Bus.trans_dist::InvalidateResp 819709 # Transaction distribution 1295system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 28518742 # Packet count per connected master and slave (bytes) 1296system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17480007 # Packet count per connected master and slave (bytes) 1297system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 376075 # Packet count per connected master and slave (bytes) 1298system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1070420 # Packet count per connected master and slave (bytes) 1299system.cpu0.toL2Bus.pkt_count::total 47445244 # Packet count per connected master and slave (bytes) 1300system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 609569408 # Cumulative packet size per connected master and slave (bytes) 1301system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 544120273 # Cumulative packet size per connected master and slave (bytes) 1302system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1382192 # Cumulative packet size per connected master and slave (bytes) 1303system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3906208 # Cumulative packet size per connected master and slave (bytes) 1304system.cpu0.toL2Bus.pkt_size::total 1158978081 # Cumulative packet size per connected master and slave (bytes) 1305system.cpu0.toL2Bus.snoops 10243316 # Total snoops (count) 1306system.cpu0.toL2Bus.snoop_fanout::samples 41099849 # Request fanout histogram 1307system.cpu0.toL2Bus.snoop_fanout::mean 1.261354 # Request fanout histogram 1308system.cpu0.toL2Bus.snoop_fanout::stdev 0.439372 # Request fanout histogram 1309system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1310system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1311system.cpu0.toL2Bus.snoop_fanout::1 30358253 73.86% 73.86% # Request fanout histogram 1312system.cpu0.toL2Bus.snoop_fanout::2 10741596 26.14% 100.00% # Request fanout histogram 1313system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1314system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1315system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1316system.cpu0.toL2Bus.snoop_fanout::total 41099849 # Request fanout histogram 1317system.cpu0.toL2Bus.reqLayer0.occupancy 19306972981 # Layer occupancy (ticks) 1318system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 1319system.cpu0.toL2Bus.snoopLayer0.occupancy 182073987 # Layer occupancy (ticks) 1320system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1321system.cpu0.toL2Bus.respLayer0.occupancy 14288744572 # Layer occupancy (ticks) 1322system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1323system.cpu0.toL2Bus.respLayer1.occupancy 7674112954 # Layer occupancy (ticks) 1324system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1325system.cpu0.toL2Bus.respLayer2.occupancy 203313475 # Layer occupancy (ticks) 1326system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1327system.cpu0.toL2Bus.respLayer3.occupancy 582176435 # Layer occupancy (ticks) 1328system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1329system.cpu1.branchPred.lookups 125904408 # Number of BP lookups 1330system.cpu1.branchPred.condPredicted 89122664 # Number of conditional branches predicted 1331system.cpu1.branchPred.condIncorrect 5902634 # Number of conditional branches incorrect 1332system.cpu1.branchPred.BTBLookups 94266188 # Number of BTB lookups 1333system.cpu1.branchPred.BTBHits 68486701 # Number of BTB hits 1334system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1335system.cpu1.branchPred.BTBHitPct 72.652456 # BTB Hit Percentage 1336system.cpu1.branchPred.usedRAS 15015861 # Number of times the RAS was used to get a target. 1337system.cpu1.branchPred.RASInCorrect 1004863 # Number of incorrect RAS predictions. 1338system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1339system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1340system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1341system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1342system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1343system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1344system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1345system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1346system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1347system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1348system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1349system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1350system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1351system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1352system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1353system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1354system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1355system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1356system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1357system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1358system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1359system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1360system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1361system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1362system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1363system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1364system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1365system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1366system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1367system.cpu1.dtb.walker.walks 261999 # Table walker walks requested 1368system.cpu1.dtb.walker.walksLong 261999 # Table walker walks initiated with long descriptors 1369system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 7478 # Level at which table walker walks with long descriptors terminate 1370system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 69980 # Level at which table walker walks with long descriptors terminate 1371system.cpu1.dtb.walker.walkWaitTime::samples 261999 # Table walker wait (enqueue to first request) latency 1372system.cpu1.dtb.walker.walkWaitTime::0 261999 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1373system.cpu1.dtb.walker.walkWaitTime::total 261999 # Table walker wait (enqueue to first request) latency 1374system.cpu1.dtb.walker.walkCompletionTime::samples 77458 # Table walker service (enqueue to completion) latency 1375system.cpu1.dtb.walker.walkCompletionTime::mean 19301.763536 # Table walker service (enqueue to completion) latency 1376system.cpu1.dtb.walker.walkCompletionTime::gmean 17918.383858 # Table walker service (enqueue to completion) latency 1377system.cpu1.dtb.walker.walkCompletionTime::stdev 10994.886931 # Table walker service (enqueue to completion) latency 1378system.cpu1.dtb.walker.walkCompletionTime::0-32767 74315 95.94% 95.94% # Table walker service (enqueue to completion) latency 1379system.cpu1.dtb.walker.walkCompletionTime::32768-65535 2659 3.43% 99.38% # Table walker service (enqueue to completion) latency 1380system.cpu1.dtb.walker.walkCompletionTime::65536-98303 247 0.32% 99.69% # Table walker service (enqueue to completion) latency 1381system.cpu1.dtb.walker.walkCompletionTime::98304-131071 165 0.21% 99.91% # Table walker service (enqueue to completion) latency 1382system.cpu1.dtb.walker.walkCompletionTime::131072-163839 17 0.02% 99.93% # Table walker service (enqueue to completion) latency 1383system.cpu1.dtb.walker.walkCompletionTime::163840-196607 5 0.01% 99.94% # Table walker service (enqueue to completion) latency 1384system.cpu1.dtb.walker.walkCompletionTime::196608-229375 16 0.02% 99.96% # Table walker service (enqueue to completion) latency 1385system.cpu1.dtb.walker.walkCompletionTime::229376-262143 8 0.01% 99.97% # Table walker service (enqueue to completion) latency 1386system.cpu1.dtb.walker.walkCompletionTime::262144-294911 10 0.01% 99.98% # Table walker service (enqueue to completion) latency 1387system.cpu1.dtb.walker.walkCompletionTime::294912-327679 9 0.01% 99.99% # Table walker service (enqueue to completion) latency 1388system.cpu1.dtb.walker.walkCompletionTime::327680-360447 5 0.01% 100.00% # Table walker service (enqueue to completion) latency 1389system.cpu1.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1390system.cpu1.dtb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1391system.cpu1.dtb.walker.walkCompletionTime::total 77458 # Table walker service (enqueue to completion) latency 1392system.cpu1.dtb.walker.walksPending::samples -1501931648 # Table walker pending requests distribution 1393system.cpu1.dtb.walker.walksPending::0 -1501931648 100.00% 100.00% # Table walker pending requests distribution 1394system.cpu1.dtb.walker.walksPending::total -1501931648 # Table walker pending requests distribution 1395system.cpu1.dtb.walker.walkPageSizes::4K 69980 90.35% 90.35% # Table walker page sizes translated 1396system.cpu1.dtb.walker.walkPageSizes::2M 7478 9.65% 100.00% # Table walker page sizes translated 1397system.cpu1.dtb.walker.walkPageSizes::total 77458 # Table walker page sizes translated 1398system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 261999 # Table walker requests started/completed, data/inst 1399system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1400system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 261999 # Table walker requests started/completed, data/inst 1401system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 77458 # Table walker requests started/completed, data/inst 1402system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1403system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 77458 # Table walker requests started/completed, data/inst 1404system.cpu1.dtb.walker.walkRequestOrigin::total 339457 # Table walker requests started/completed, data/inst 1405system.cpu1.dtb.inst_hits 0 # ITB inst hits 1406system.cpu1.dtb.inst_misses 0 # ITB inst misses 1407system.cpu1.dtb.read_hits 82663207 # DTB read hits 1408system.cpu1.dtb.read_misses 218762 # DTB read misses 1409system.cpu1.dtb.write_hits 71167787 # DTB write hits 1410system.cpu1.dtb.write_misses 43237 # DTB write misses 1411system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1412system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1413system.cpu1.dtb.flush_tlb_mva_asid 38178 # Number of times TLB was flushed by MVA & ASID 1414system.cpu1.dtb.flush_tlb_asid 1015 # Number of times TLB was flushed by ASID 1415system.cpu1.dtb.flush_entries 35788 # Number of entries that have been flushed from TLB 1416system.cpu1.dtb.align_faults 902 # Number of TLB faults due to alignment restrictions 1417system.cpu1.dtb.prefetch_faults 6887 # Number of TLB faults due to prefetch 1418system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1419system.cpu1.dtb.perms_faults 9904 # Number of TLB faults due to permissions restrictions 1420system.cpu1.dtb.read_accesses 82881969 # DTB read accesses 1421system.cpu1.dtb.write_accesses 71211024 # DTB write accesses 1422system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1423system.cpu1.dtb.hits 153830994 # DTB hits 1424system.cpu1.dtb.misses 261999 # DTB misses 1425system.cpu1.dtb.accesses 154092993 # DTB accesses 1426system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1427system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1428system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1429system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1430system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1431system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1432system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1433system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1434system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1435system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1436system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1437system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1438system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1439system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1440system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1441system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1442system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1443system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1444system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1445system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1446system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1447system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1448system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1449system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1450system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1451system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1452system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1453system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1454system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1455system.cpu1.itb.walker.walks 59152 # Table walker walks requested 1456system.cpu1.itb.walker.walksLong 59152 # Table walker walks initiated with long descriptors 1457system.cpu1.itb.walker.walksLongTerminationLevel::Level2 461 # Level at which table walker walks with long descriptors terminate 1458system.cpu1.itb.walker.walksLongTerminationLevel::Level3 48561 # Level at which table walker walks with long descriptors terminate 1459system.cpu1.itb.walker.walkWaitTime::samples 59152 # Table walker wait (enqueue to first request) latency 1460system.cpu1.itb.walker.walkWaitTime::0 59152 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1461system.cpu1.itb.walker.walkWaitTime::total 59152 # Table walker wait (enqueue to first request) latency 1462system.cpu1.itb.walker.walkCompletionTime::samples 49022 # Table walker service (enqueue to completion) latency 1463system.cpu1.itb.walker.walkCompletionTime::mean 21340.612378 # Table walker service (enqueue to completion) latency 1464system.cpu1.itb.walker.walkCompletionTime::gmean 19735.982166 # Table walker service (enqueue to completion) latency 1465system.cpu1.itb.walker.walkCompletionTime::stdev 12453.289543 # Table walker service (enqueue to completion) latency 1466system.cpu1.itb.walker.walkCompletionTime::0-32767 45897 93.63% 93.63% # Table walker service (enqueue to completion) latency 1467system.cpu1.itb.walker.walkCompletionTime::32768-65535 2624 5.35% 98.98% # Table walker service (enqueue to completion) latency 1468system.cpu1.itb.walker.walkCompletionTime::65536-98303 160 0.33% 99.30% # Table walker service (enqueue to completion) latency 1469system.cpu1.itb.walker.walkCompletionTime::98304-131071 295 0.60% 99.91% # Table walker service (enqueue to completion) latency 1470system.cpu1.itb.walker.walkCompletionTime::131072-163839 12 0.02% 99.93% # Table walker service (enqueue to completion) latency 1471system.cpu1.itb.walker.walkCompletionTime::163840-196607 9 0.02% 99.95% # Table walker service (enqueue to completion) latency 1472system.cpu1.itb.walker.walkCompletionTime::196608-229375 10 0.02% 99.97% # Table walker service (enqueue to completion) latency 1473system.cpu1.itb.walker.walkCompletionTime::229376-262143 5 0.01% 99.98% # Table walker service (enqueue to completion) latency 1474system.cpu1.itb.walker.walkCompletionTime::262144-294911 2 0.00% 99.98% # Table walker service (enqueue to completion) latency 1475system.cpu1.itb.walker.walkCompletionTime::294912-327679 3 0.01% 99.99% # Table walker service (enqueue to completion) latency 1476system.cpu1.itb.walker.walkCompletionTime::327680-360447 2 0.00% 99.99% # Table walker service (enqueue to completion) latency 1477system.cpu1.itb.walker.walkCompletionTime::360448-393215 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1478system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1479system.cpu1.itb.walker.walkCompletionTime::total 49022 # Table walker service (enqueue to completion) latency 1480system.cpu1.itb.walker.walksPending::samples -1502514148 # Table walker pending requests distribution 1481system.cpu1.itb.walker.walksPending::0 -1502514148 100.00% 100.00% # Table walker pending requests distribution 1482system.cpu1.itb.walker.walksPending::total -1502514148 # Table walker pending requests distribution 1483system.cpu1.itb.walker.walkPageSizes::4K 48561 99.06% 99.06% # Table walker page sizes translated 1484system.cpu1.itb.walker.walkPageSizes::2M 461 0.94% 100.00% # Table walker page sizes translated 1485system.cpu1.itb.walker.walkPageSizes::total 49022 # Table walker page sizes translated 1486system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1487system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 59152 # Table walker requests started/completed, data/inst 1488system.cpu1.itb.walker.walkRequestOrigin_Requested::total 59152 # Table walker requests started/completed, data/inst 1489system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1490system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 49022 # Table walker requests started/completed, data/inst 1491system.cpu1.itb.walker.walkRequestOrigin_Completed::total 49022 # Table walker requests started/completed, data/inst 1492system.cpu1.itb.walker.walkRequestOrigin::total 108174 # Table walker requests started/completed, data/inst 1493system.cpu1.itb.inst_hits 225695696 # ITB inst hits 1494system.cpu1.itb.inst_misses 59152 # ITB inst misses 1495system.cpu1.itb.read_hits 0 # DTB read hits 1496system.cpu1.itb.read_misses 0 # DTB read misses 1497system.cpu1.itb.write_hits 0 # DTB write hits 1498system.cpu1.itb.write_misses 0 # DTB write misses 1499system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1500system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1501system.cpu1.itb.flush_tlb_mva_asid 38178 # Number of times TLB was flushed by MVA & ASID 1502system.cpu1.itb.flush_tlb_asid 1015 # Number of times TLB was flushed by ASID 1503system.cpu1.itb.flush_entries 25916 # Number of entries that have been flushed from TLB 1504system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1505system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1506system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1507system.cpu1.itb.perms_faults 201769 # Number of TLB faults due to permissions restrictions 1508system.cpu1.itb.read_accesses 0 # DTB read accesses 1509system.cpu1.itb.write_accesses 0 # DTB write accesses 1510system.cpu1.itb.inst_accesses 225754848 # ITB inst accesses 1511system.cpu1.itb.hits 225695696 # DTB hits 1512system.cpu1.itb.misses 59152 # DTB misses 1513system.cpu1.itb.accesses 225754848 # DTB accesses 1514system.cpu1.numCycles 837975509 # number of cpu cycles simulated 1515system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1516system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1517system.cpu1.committedInsts 416666374 # Number of instructions committed 1518system.cpu1.committedOps 490559113 # Number of ops (including micro ops) committed 1519system.cpu1.discardedOps 42698463 # Number of ops (including micro ops) which were discarded before commit 1520system.cpu1.numFetchSuspends 4659 # Number of times Execute suspended instruction fetching 1521system.cpu1.quiesceCycles 93986622085 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1522system.cpu1.cpi 2.011143 # CPI: cycles per instruction 1523system.cpu1.ipc 0.497230 # IPC: instructions per cycle 1524system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1525system.cpu1.kern.inst.quiesce 5009 # number of quiesce instructions executed 1526system.cpu1.tickCycles 670350336 # Number of cycles that the object actually ticked 1527system.cpu1.idleCycles 167625173 # Total number of cycles that the object has spent stopped 1528system.cpu1.dcache.tags.replacements 4806043 # number of replacements 1529system.cpu1.dcache.tags.tagsinuse 444.186980 # Cycle average of tags in use 1530system.cpu1.dcache.tags.total_refs 146495712 # Total number of references to valid blocks. 1531system.cpu1.dcache.tags.sampled_refs 4806555 # Sample count of references to valid blocks. 1532system.cpu1.dcache.tags.avg_refs 30.478318 # Average number of references to valid blocks. 1533system.cpu1.dcache.tags.warmup_cycle 8387638822500 # Cycle when the warmup percentage was hit. 1534system.cpu1.dcache.tags.occ_blocks::cpu1.data 444.186980 # Average occupied blocks per requestor 1535system.cpu1.dcache.tags.occ_percent::cpu1.data 0.867553 # Average percentage of cache occupancy 1536system.cpu1.dcache.tags.occ_percent::total 0.867553 # Average percentage of cache occupancy 1537system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1538system.cpu1.dcache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id 1539system.cpu1.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id 1540system.cpu1.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id 1541system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1542system.cpu1.dcache.tags.tag_accesses 309963007 # Number of tag accesses 1543system.cpu1.dcache.tags.data_accesses 309963007 # Number of data accesses 1544system.cpu1.dcache.ReadReq_hits::cpu1.data 75874550 # number of ReadReq hits 1545system.cpu1.dcache.ReadReq_hits::total 75874550 # number of ReadReq hits 1546system.cpu1.dcache.WriteReq_hits::cpu1.data 66435000 # number of WriteReq hits 1547system.cpu1.dcache.WriteReq_hits::total 66435000 # number of WriteReq hits 1548system.cpu1.dcache.SoftPFReq_hits::cpu1.data 232604 # number of SoftPFReq hits 1549system.cpu1.dcache.SoftPFReq_hits::total 232604 # number of SoftPFReq hits 1550system.cpu1.dcache.WriteLineReq_hits::cpu1.data 157450 # number of WriteLineReq hits 1551system.cpu1.dcache.WriteLineReq_hits::total 157450 # number of WriteLineReq hits 1552system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1693988 # number of LoadLockedReq hits 1553system.cpu1.dcache.LoadLockedReq_hits::total 1693988 # number of LoadLockedReq hits 1554system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1671438 # number of StoreCondReq hits 1555system.cpu1.dcache.StoreCondReq_hits::total 1671438 # number of StoreCondReq hits 1556system.cpu1.dcache.demand_hits::cpu1.data 142309550 # number of demand (read+write) hits 1557system.cpu1.dcache.demand_hits::total 142309550 # number of demand (read+write) hits 1558system.cpu1.dcache.overall_hits::cpu1.data 142542154 # number of overall hits 1559system.cpu1.dcache.overall_hits::total 142542154 # number of overall hits 1560system.cpu1.dcache.ReadReq_misses::cpu1.data 3161753 # number of ReadReq misses 1561system.cpu1.dcache.ReadReq_misses::total 3161753 # number of ReadReq misses 1562system.cpu1.dcache.WriteReq_misses::cpu1.data 1996683 # number of WriteReq misses 1563system.cpu1.dcache.WriteReq_misses::total 1996683 # number of WriteReq misses 1564system.cpu1.dcache.SoftPFReq_misses::cpu1.data 552089 # number of SoftPFReq misses 1565system.cpu1.dcache.SoftPFReq_misses::total 552089 # number of SoftPFReq misses 1566system.cpu1.dcache.WriteLineReq_misses::cpu1.data 421817 # number of WriteLineReq misses 1567system.cpu1.dcache.WriteLineReq_misses::total 421817 # number of WriteLineReq misses 1568system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 158395 # number of LoadLockedReq misses 1569system.cpu1.dcache.LoadLockedReq_misses::total 158395 # number of LoadLockedReq misses 1570system.cpu1.dcache.StoreCondReq_misses::cpu1.data 179133 # number of StoreCondReq misses 1571system.cpu1.dcache.StoreCondReq_misses::total 179133 # number of StoreCondReq misses 1572system.cpu1.dcache.demand_misses::cpu1.data 5158436 # number of demand (read+write) misses 1573system.cpu1.dcache.demand_misses::total 5158436 # number of demand (read+write) misses 1574system.cpu1.dcache.overall_misses::cpu1.data 5710525 # number of overall misses 1575system.cpu1.dcache.overall_misses::total 5710525 # number of overall misses 1576system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 43703345000 # number of ReadReq miss cycles 1577system.cpu1.dcache.ReadReq_miss_latency::total 43703345000 # number of ReadReq miss cycles 1578system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 33230827500 # number of WriteReq miss cycles 1579system.cpu1.dcache.WriteReq_miss_latency::total 33230827500 # number of WriteReq miss cycles 1580system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 13699084500 # number of WriteLineReq miss cycles 1581system.cpu1.dcache.WriteLineReq_miss_latency::total 13699084500 # number of WriteLineReq miss cycles 1582system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2222797000 # number of LoadLockedReq miss cycles 1583system.cpu1.dcache.LoadLockedReq_miss_latency::total 2222797000 # number of LoadLockedReq miss cycles 1584system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3749543500 # number of StoreCondReq miss cycles 1585system.cpu1.dcache.StoreCondReq_miss_latency::total 3749543500 # number of StoreCondReq miss cycles 1586system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3215500 # number of StoreCondFailReq miss cycles 1587system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3215500 # number of StoreCondFailReq miss cycles 1588system.cpu1.dcache.demand_miss_latency::cpu1.data 76934172500 # number of demand (read+write) miss cycles 1589system.cpu1.dcache.demand_miss_latency::total 76934172500 # number of demand (read+write) miss cycles 1590system.cpu1.dcache.overall_miss_latency::cpu1.data 76934172500 # number of overall miss cycles 1591system.cpu1.dcache.overall_miss_latency::total 76934172500 # number of overall miss cycles 1592system.cpu1.dcache.ReadReq_accesses::cpu1.data 79036303 # number of ReadReq accesses(hits+misses) 1593system.cpu1.dcache.ReadReq_accesses::total 79036303 # number of ReadReq accesses(hits+misses) 1594system.cpu1.dcache.WriteReq_accesses::cpu1.data 68431683 # number of WriteReq accesses(hits+misses) 1595system.cpu1.dcache.WriteReq_accesses::total 68431683 # number of WriteReq accesses(hits+misses) 1596system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 784693 # number of SoftPFReq accesses(hits+misses) 1597system.cpu1.dcache.SoftPFReq_accesses::total 784693 # number of SoftPFReq accesses(hits+misses) 1598system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 579267 # number of WriteLineReq accesses(hits+misses) 1599system.cpu1.dcache.WriteLineReq_accesses::total 579267 # number of WriteLineReq accesses(hits+misses) 1600system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1852383 # number of LoadLockedReq accesses(hits+misses) 1601system.cpu1.dcache.LoadLockedReq_accesses::total 1852383 # number of LoadLockedReq accesses(hits+misses) 1602system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1850571 # number of StoreCondReq accesses(hits+misses) 1603system.cpu1.dcache.StoreCondReq_accesses::total 1850571 # number of StoreCondReq accesses(hits+misses) 1604system.cpu1.dcache.demand_accesses::cpu1.data 147467986 # number of demand (read+write) accesses 1605system.cpu1.dcache.demand_accesses::total 147467986 # number of demand (read+write) accesses 1606system.cpu1.dcache.overall_accesses::cpu1.data 148252679 # number of overall (read+write) accesses 1607system.cpu1.dcache.overall_accesses::total 148252679 # number of overall (read+write) accesses 1608system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.040004 # miss rate for ReadReq accesses 1609system.cpu1.dcache.ReadReq_miss_rate::total 0.040004 # miss rate for ReadReq accesses 1610system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029178 # miss rate for WriteReq accesses 1611system.cpu1.dcache.WriteReq_miss_rate::total 0.029178 # miss rate for WriteReq accesses 1612system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.703573 # miss rate for SoftPFReq accesses 1613system.cpu1.dcache.SoftPFReq_miss_rate::total 0.703573 # miss rate for SoftPFReq accesses 1614system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.728191 # miss rate for WriteLineReq accesses 1615system.cpu1.dcache.WriteLineReq_miss_rate::total 0.728191 # miss rate for WriteLineReq accesses 1616system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.085509 # miss rate for LoadLockedReq accesses 1617system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.085509 # miss rate for LoadLockedReq accesses 1618system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.096799 # miss rate for StoreCondReq accesses 1619system.cpu1.dcache.StoreCondReq_miss_rate::total 0.096799 # miss rate for StoreCondReq accesses 1620system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034980 # miss rate for demand accesses 1621system.cpu1.dcache.demand_miss_rate::total 0.034980 # miss rate for demand accesses 1622system.cpu1.dcache.overall_miss_rate::cpu1.data 0.038519 # miss rate for overall accesses 1623system.cpu1.dcache.overall_miss_rate::total 0.038519 # miss rate for overall accesses 1624system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13822.504478 # average ReadReq miss latency 1625system.cpu1.dcache.ReadReq_avg_miss_latency::total 13822.504478 # average ReadReq miss latency 1626system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16643.016192 # average WriteReq miss latency 1627system.cpu1.dcache.WriteReq_avg_miss_latency::total 16643.016192 # average WriteReq miss latency 1628system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 32476.368899 # average WriteLineReq miss latency 1629system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 32476.368899 # average WriteLineReq miss latency 1630system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14033.252312 # average LoadLockedReq miss latency 1631system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14033.252312 # average LoadLockedReq miss latency 1632system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20931.617848 # average StoreCondReq miss latency 1633system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20931.617848 # average StoreCondReq miss latency 1634system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1635system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1636system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14914.243872 # average overall miss latency 1637system.cpu1.dcache.demand_avg_miss_latency::total 14914.243872 # average overall miss latency 1638system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13472.346676 # average overall miss latency 1639system.cpu1.dcache.overall_avg_miss_latency::total 13472.346676 # average overall miss latency 1640system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1641system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1642system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1643system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1644system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1645system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1646system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1647system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1648system.cpu1.dcache.writebacks::writebacks 3028608 # number of writebacks 1649system.cpu1.dcache.writebacks::total 3028608 # number of writebacks 1650system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 352163 # number of ReadReq MSHR hits 1651system.cpu1.dcache.ReadReq_mshr_hits::total 352163 # number of ReadReq MSHR hits 1652system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 814004 # number of WriteReq MSHR hits 1653system.cpu1.dcache.WriteReq_mshr_hits::total 814004 # number of WriteReq MSHR hits 1654system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 58 # number of WriteLineReq MSHR hits 1655system.cpu1.dcache.WriteLineReq_mshr_hits::total 58 # number of WriteLineReq MSHR hits 1656system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 37997 # number of LoadLockedReq MSHR hits 1657system.cpu1.dcache.LoadLockedReq_mshr_hits::total 37997 # number of LoadLockedReq MSHR hits 1658system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 57 # number of StoreCondReq MSHR hits 1659system.cpu1.dcache.StoreCondReq_mshr_hits::total 57 # number of StoreCondReq MSHR hits 1660system.cpu1.dcache.demand_mshr_hits::cpu1.data 1166167 # number of demand (read+write) MSHR hits 1661system.cpu1.dcache.demand_mshr_hits::total 1166167 # number of demand (read+write) MSHR hits 1662system.cpu1.dcache.overall_mshr_hits::cpu1.data 1166167 # number of overall MSHR hits 1663system.cpu1.dcache.overall_mshr_hits::total 1166167 # number of overall MSHR hits 1664system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2809590 # number of ReadReq MSHR misses 1665system.cpu1.dcache.ReadReq_mshr_misses::total 2809590 # number of ReadReq MSHR misses 1666system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1182679 # number of WriteReq MSHR misses 1667system.cpu1.dcache.WriteReq_mshr_misses::total 1182679 # number of WriteReq MSHR misses 1668system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 551754 # number of SoftPFReq MSHR misses 1669system.cpu1.dcache.SoftPFReq_mshr_misses::total 551754 # number of SoftPFReq MSHR misses 1670system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 421759 # number of WriteLineReq MSHR misses 1671system.cpu1.dcache.WriteLineReq_mshr_misses::total 421759 # number of WriteLineReq MSHR misses 1672system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 120398 # number of LoadLockedReq MSHR misses 1673system.cpu1.dcache.LoadLockedReq_mshr_misses::total 120398 # number of LoadLockedReq MSHR misses 1674system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 179076 # number of StoreCondReq MSHR misses 1675system.cpu1.dcache.StoreCondReq_mshr_misses::total 179076 # number of StoreCondReq MSHR misses 1676system.cpu1.dcache.demand_mshr_misses::cpu1.data 3992269 # number of demand (read+write) MSHR misses 1677system.cpu1.dcache.demand_mshr_misses::total 3992269 # number of demand (read+write) MSHR misses 1678system.cpu1.dcache.overall_mshr_misses::cpu1.data 4544023 # number of overall MSHR misses 1679system.cpu1.dcache.overall_mshr_misses::total 4544023 # number of overall MSHR misses 1680system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 8249 # number of ReadReq MSHR uncacheable 1681system.cpu1.dcache.ReadReq_mshr_uncacheable::total 8249 # number of ReadReq MSHR uncacheable 1682system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 8420 # number of WriteReq MSHR uncacheable 1683system.cpu1.dcache.WriteReq_mshr_uncacheable::total 8420 # number of WriteReq MSHR uncacheable 1684system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 16669 # number of overall MSHR uncacheable misses 1685system.cpu1.dcache.overall_mshr_uncacheable_misses::total 16669 # number of overall MSHR uncacheable misses 1686system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 35216853500 # number of ReadReq MSHR miss cycles 1687system.cpu1.dcache.ReadReq_mshr_miss_latency::total 35216853500 # number of ReadReq MSHR miss cycles 1688system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 19067594000 # number of WriteReq MSHR miss cycles 1689system.cpu1.dcache.WriteReq_mshr_miss_latency::total 19067594000 # number of WriteReq MSHR miss cycles 1690system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 11091696000 # number of SoftPFReq MSHR miss cycles 1691system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 11091696000 # number of SoftPFReq MSHR miss cycles 1692system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 13273963000 # number of WriteLineReq MSHR miss cycles 1693system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 13273963000 # number of WriteLineReq MSHR miss cycles 1694system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1514299000 # number of LoadLockedReq MSHR miss cycles 1695system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1514299000 # number of LoadLockedReq MSHR miss cycles 1696system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3568894000 # number of StoreCondReq MSHR miss cycles 1697system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3568894000 # number of StoreCondReq MSHR miss cycles 1698system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2841500 # number of StoreCondFailReq MSHR miss cycles 1699system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2841500 # number of StoreCondFailReq MSHR miss cycles 1700system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 54284447500 # number of demand (read+write) MSHR miss cycles 1701system.cpu1.dcache.demand_mshr_miss_latency::total 54284447500 # number of demand (read+write) MSHR miss cycles 1702system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 65376143500 # number of overall MSHR miss cycles 1703system.cpu1.dcache.overall_mshr_miss_latency::total 65376143500 # number of overall MSHR miss cycles 1704system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1096081500 # number of ReadReq MSHR uncacheable cycles 1705system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1096081500 # number of ReadReq MSHR uncacheable cycles 1706system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1226588000 # number of WriteReq MSHR uncacheable cycles 1707system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1226588000 # number of WriteReq MSHR uncacheable cycles 1708system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2322669500 # number of overall MSHR uncacheable cycles 1709system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2322669500 # number of overall MSHR uncacheable cycles 1710system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035548 # mshr miss rate for ReadReq accesses 1711system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035548 # mshr miss rate for ReadReq accesses 1712system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017283 # mshr miss rate for WriteReq accesses 1713system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017283 # mshr miss rate for WriteReq accesses 1714system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.703146 # mshr miss rate for SoftPFReq accesses 1715system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.703146 # mshr miss rate for SoftPFReq accesses 1716system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.728091 # mshr miss rate for WriteLineReq accesses 1717system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.728091 # mshr miss rate for WriteLineReq accesses 1718system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064996 # mshr miss rate for LoadLockedReq accesses 1719system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064996 # mshr miss rate for LoadLockedReq accesses 1720system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.096768 # mshr miss rate for StoreCondReq accesses 1721system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.096768 # mshr miss rate for StoreCondReq accesses 1722system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027072 # mshr miss rate for demand accesses 1723system.cpu1.dcache.demand_mshr_miss_rate::total 0.027072 # mshr miss rate for demand accesses 1724system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030651 # mshr miss rate for overall accesses 1725system.cpu1.dcache.overall_mshr_miss_rate::total 0.030651 # mshr miss rate for overall accesses 1726system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12534.516958 # average ReadReq mshr miss latency 1727system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12534.516958 # average ReadReq mshr miss latency 1728system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16122.374710 # average WriteReq mshr miss latency 1729system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16122.374710 # average WriteReq mshr miss latency 1730system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20102.610946 # average SoftPFReq mshr miss latency 1731system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20102.610946 # average SoftPFReq mshr miss latency 1732system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 31472.862464 # average WriteLineReq mshr miss latency 1733system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 31472.862464 # average WriteLineReq mshr miss latency 1734system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12577.443147 # average LoadLockedReq mshr miss latency 1735system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12577.443147 # average LoadLockedReq mshr miss latency 1736system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19929.493623 # average StoreCondReq mshr miss latency 1737system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19929.493623 # average StoreCondReq mshr miss latency 1738system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1739system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1740system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13597.392235 # average overall mshr miss latency 1741system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13597.392235 # average overall mshr miss latency 1742system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14387.282701 # average overall mshr miss latency 1743system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14387.282701 # average overall mshr miss latency 1744system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 132874.469633 # average ReadReq mshr uncacheable latency 1745system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 132874.469633 # average ReadReq mshr uncacheable latency 1746system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145675.534442 # average WriteReq mshr uncacheable latency 1747system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 145675.534442 # average WriteReq mshr uncacheable latency 1748system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 139340.662307 # average overall mshr uncacheable latency 1749system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 139340.662307 # average overall mshr uncacheable latency 1750system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1751system.cpu1.icache.tags.replacements 8962341 # number of replacements 1752system.cpu1.icache.tags.tagsinuse 506.974355 # Cycle average of tags in use 1753system.cpu1.icache.tags.total_refs 216525917 # Total number of references to valid blocks. 1754system.cpu1.icache.tags.sampled_refs 8962853 # Sample count of references to valid blocks. 1755system.cpu1.icache.tags.avg_refs 24.158147 # Average number of references to valid blocks. 1756system.cpu1.icache.tags.warmup_cycle 8375817756000 # Cycle when the warmup percentage was hit. 1757system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.974355 # Average occupied blocks per requestor 1758system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990184 # Average percentage of cache occupancy 1759system.cpu1.icache.tags.occ_percent::total 0.990184 # Average percentage of cache occupancy 1760system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1761system.cpu1.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id 1762system.cpu1.icache.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id 1763system.cpu1.icache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id 1764system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1765system.cpu1.icache.tags.tag_accesses 459940393 # Number of tag accesses 1766system.cpu1.icache.tags.data_accesses 459940393 # Number of data accesses 1767system.cpu1.icache.ReadReq_hits::cpu1.inst 216525917 # number of ReadReq hits 1768system.cpu1.icache.ReadReq_hits::total 216525917 # number of ReadReq hits 1769system.cpu1.icache.demand_hits::cpu1.inst 216525917 # number of demand (read+write) hits 1770system.cpu1.icache.demand_hits::total 216525917 # number of demand (read+write) hits 1771system.cpu1.icache.overall_hits::cpu1.inst 216525917 # number of overall hits 1772system.cpu1.icache.overall_hits::total 216525917 # number of overall hits 1773system.cpu1.icache.ReadReq_misses::cpu1.inst 8962853 # number of ReadReq misses 1774system.cpu1.icache.ReadReq_misses::total 8962853 # number of ReadReq misses 1775system.cpu1.icache.demand_misses::cpu1.inst 8962853 # number of demand (read+write) misses 1776system.cpu1.icache.demand_misses::total 8962853 # number of demand (read+write) misses 1777system.cpu1.icache.overall_misses::cpu1.inst 8962853 # number of overall misses 1778system.cpu1.icache.overall_misses::total 8962853 # number of overall misses 1779system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 87475415500 # number of ReadReq miss cycles 1780system.cpu1.icache.ReadReq_miss_latency::total 87475415500 # number of ReadReq miss cycles 1781system.cpu1.icache.demand_miss_latency::cpu1.inst 87475415500 # number of demand (read+write) miss cycles 1782system.cpu1.icache.demand_miss_latency::total 87475415500 # number of demand (read+write) miss cycles 1783system.cpu1.icache.overall_miss_latency::cpu1.inst 87475415500 # number of overall miss cycles 1784system.cpu1.icache.overall_miss_latency::total 87475415500 # number of overall miss cycles 1785system.cpu1.icache.ReadReq_accesses::cpu1.inst 225488770 # number of ReadReq accesses(hits+misses) 1786system.cpu1.icache.ReadReq_accesses::total 225488770 # number of ReadReq accesses(hits+misses) 1787system.cpu1.icache.demand_accesses::cpu1.inst 225488770 # number of demand (read+write) accesses 1788system.cpu1.icache.demand_accesses::total 225488770 # number of demand (read+write) accesses 1789system.cpu1.icache.overall_accesses::cpu1.inst 225488770 # number of overall (read+write) accesses 1790system.cpu1.icache.overall_accesses::total 225488770 # number of overall (read+write) accesses 1791system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.039749 # miss rate for ReadReq accesses 1792system.cpu1.icache.ReadReq_miss_rate::total 0.039749 # miss rate for ReadReq accesses 1793system.cpu1.icache.demand_miss_rate::cpu1.inst 0.039749 # miss rate for demand accesses 1794system.cpu1.icache.demand_miss_rate::total 0.039749 # miss rate for demand accesses 1795system.cpu1.icache.overall_miss_rate::cpu1.inst 0.039749 # miss rate for overall accesses 1796system.cpu1.icache.overall_miss_rate::total 0.039749 # miss rate for overall accesses 1797system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9759.773534 # average ReadReq miss latency 1798system.cpu1.icache.ReadReq_avg_miss_latency::total 9759.773534 # average ReadReq miss latency 1799system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9759.773534 # average overall miss latency 1800system.cpu1.icache.demand_avg_miss_latency::total 9759.773534 # average overall miss latency 1801system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9759.773534 # average overall miss latency 1802system.cpu1.icache.overall_avg_miss_latency::total 9759.773534 # average overall miss latency 1803system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1804system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1805system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1806system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1807system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1808system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1809system.cpu1.icache.fast_writes 0 # number of fast writes performed 1810system.cpu1.icache.cache_copies 0 # number of cache copies performed 1811system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8962853 # number of ReadReq MSHR misses 1812system.cpu1.icache.ReadReq_mshr_misses::total 8962853 # number of ReadReq MSHR misses 1813system.cpu1.icache.demand_mshr_misses::cpu1.inst 8962853 # number of demand (read+write) MSHR misses 1814system.cpu1.icache.demand_mshr_misses::total 8962853 # number of demand (read+write) MSHR misses 1815system.cpu1.icache.overall_mshr_misses::cpu1.inst 8962853 # number of overall MSHR misses 1816system.cpu1.icache.overall_mshr_misses::total 8962853 # number of overall MSHR misses 1817system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable 1818system.cpu1.icache.ReadReq_mshr_uncacheable::total 93 # number of ReadReq MSHR uncacheable 1819system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses 1820system.cpu1.icache.overall_mshr_uncacheable_misses::total 93 # number of overall MSHR uncacheable misses 1821system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 82993989000 # number of ReadReq MSHR miss cycles 1822system.cpu1.icache.ReadReq_mshr_miss_latency::total 82993989000 # number of ReadReq MSHR miss cycles 1823system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 82993989000 # number of demand (read+write) MSHR miss cycles 1824system.cpu1.icache.demand_mshr_miss_latency::total 82993989000 # number of demand (read+write) MSHR miss cycles 1825system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 82993989000 # number of overall MSHR miss cycles 1826system.cpu1.icache.overall_mshr_miss_latency::total 82993989000 # number of overall MSHR miss cycles 1827system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8742000 # number of ReadReq MSHR uncacheable cycles 1828system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8742000 # number of ReadReq MSHR uncacheable cycles 1829system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8742000 # number of overall MSHR uncacheable cycles 1830system.cpu1.icache.overall_mshr_uncacheable_latency::total 8742000 # number of overall MSHR uncacheable cycles 1831system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.039749 # mshr miss rate for ReadReq accesses 1832system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.039749 # mshr miss rate for ReadReq accesses 1833system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.039749 # mshr miss rate for demand accesses 1834system.cpu1.icache.demand_mshr_miss_rate::total 0.039749 # mshr miss rate for demand accesses 1835system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.039749 # mshr miss rate for overall accesses 1836system.cpu1.icache.overall_mshr_miss_rate::total 0.039749 # mshr miss rate for overall accesses 1837system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9259.773534 # average ReadReq mshr miss latency 1838system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9259.773534 # average ReadReq mshr miss latency 1839system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9259.773534 # average overall mshr miss latency 1840system.cpu1.icache.demand_avg_mshr_miss_latency::total 9259.773534 # average overall mshr miss latency 1841system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9259.773534 # average overall mshr miss latency 1842system.cpu1.icache.overall_avg_mshr_miss_latency::total 9259.773534 # average overall mshr miss latency 1843system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 94000 # average ReadReq mshr uncacheable latency 1844system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 94000 # average ReadReq mshr uncacheable latency 1845system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 94000 # average overall mshr uncacheable latency 1846system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 94000 # average overall mshr uncacheable latency 1847system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1848system.cpu1.l2cache.prefetcher.num_hwpf_issued 6768411 # number of hwpf issued 1849system.cpu1.l2cache.prefetcher.pfIdentified 6768469 # number of prefetch candidates identified 1850system.cpu1.l2cache.prefetcher.pfBufferHit 54 # number of redundant prefetches already in prefetch queue 1851system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1852system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1853system.cpu1.l2cache.prefetcher.pfSpanPage 863435 # number of prefetches not generated due to page crossing 1854system.cpu1.l2cache.tags.replacements 2141720 # number of replacements 1855system.cpu1.l2cache.tags.tagsinuse 13540.912612 # Cycle average of tags in use 1856system.cpu1.l2cache.tags.total_refs 24731326 # Total number of references to valid blocks. 1857system.cpu1.l2cache.tags.sampled_refs 2157705 # Sample count of references to valid blocks. 1858system.cpu1.l2cache.tags.avg_refs 11.461866 # Average number of references to valid blocks. 1859system.cpu1.l2cache.tags.warmup_cycle 9851161667500 # Cycle when the warmup percentage was hit. 1860system.cpu1.l2cache.tags.occ_blocks::writebacks 5143.146487 # Average occupied blocks per requestor 1861system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 72.763483 # Average occupied blocks per requestor 1862system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 75.029020 # Average occupied blocks per requestor 1863system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4350.990102 # Average occupied blocks per requestor 1864system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3012.175036 # Average occupied blocks per requestor 1865system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 886.808482 # Average occupied blocks per requestor 1866system.cpu1.l2cache.tags.occ_percent::writebacks 0.313913 # Average percentage of cache occupancy 1867system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004441 # Average percentage of cache occupancy 1868system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004579 # Average percentage of cache occupancy 1869system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.265563 # Average percentage of cache occupancy 1870system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.183849 # Average percentage of cache occupancy 1871system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.054126 # Average percentage of cache occupancy 1872system.cpu1.l2cache.tags.occ_percent::total 0.826472 # Average percentage of cache occupancy 1873system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1213 # Occupied blocks per task id 1874system.cpu1.l2cache.tags.occ_task_id_blocks::1023 83 # Occupied blocks per task id 1875system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14689 # Occupied blocks per task id 1876system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 5 # Occupied blocks per task id 1877system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 25 # Occupied blocks per task id 1878system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 401 # Occupied blocks per task id 1879system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 707 # Occupied blocks per task id 1880system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 75 # Occupied blocks per task id 1881system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id 1882system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 53 # Occupied blocks per task id 1883system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 26 # Occupied blocks per task id 1884system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id 1885system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id 1886system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 662 # Occupied blocks per task id 1887system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5268 # Occupied blocks per task id 1888system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8016 # Occupied blocks per task id 1889system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 626 # Occupied blocks per task id 1890system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.074036 # Percentage of cache occupancy per task id 1891system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005066 # Percentage of cache occupancy per task id 1892system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.896545 # Percentage of cache occupancy per task id 1893system.cpu1.l2cache.tags.tag_accesses 461861904 # Number of tag accesses 1894system.cpu1.l2cache.tags.data_accesses 461861904 # Number of data accesses 1895system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 450787 # number of ReadReq hits 1896system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 134849 # number of ReadReq hits 1897system.cpu1.l2cache.ReadReq_hits::total 585636 # number of ReadReq hits 1898system.cpu1.l2cache.Writeback_hits::writebacks 3028606 # number of Writeback hits 1899system.cpu1.l2cache.Writeback_hits::total 3028606 # number of Writeback hits 1900system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 55878 # number of UpgradeReq hits 1901system.cpu1.l2cache.UpgradeReq_hits::total 55878 # number of UpgradeReq hits 1902system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 34341 # number of SCUpgradeReq hits 1903system.cpu1.l2cache.SCUpgradeReq_hits::total 34341 # number of SCUpgradeReq hits 1904system.cpu1.l2cache.ReadExReq_hits::cpu1.data 766672 # number of ReadExReq hits 1905system.cpu1.l2cache.ReadExReq_hits::total 766672 # number of ReadExReq hits 1906system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8228059 # number of ReadCleanReq hits 1907system.cpu1.l2cache.ReadCleanReq_hits::total 8228059 # number of ReadCleanReq hits 1908system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2592448 # number of ReadSharedReq hits 1909system.cpu1.l2cache.ReadSharedReq_hits::total 2592448 # number of ReadSharedReq hits 1910system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 167873 # number of InvalidateReq hits 1911system.cpu1.l2cache.InvalidateReq_hits::total 167873 # number of InvalidateReq hits 1912system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 450787 # number of demand (read+write) hits 1913system.cpu1.l2cache.demand_hits::cpu1.itb.walker 134849 # number of demand (read+write) hits 1914system.cpu1.l2cache.demand_hits::cpu1.inst 8228059 # number of demand (read+write) hits 1915system.cpu1.l2cache.demand_hits::cpu1.data 3359120 # number of demand (read+write) hits 1916system.cpu1.l2cache.demand_hits::total 12172815 # number of demand (read+write) hits 1917system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 450787 # number of overall hits 1918system.cpu1.l2cache.overall_hits::cpu1.itb.walker 134849 # number of overall hits 1919system.cpu1.l2cache.overall_hits::cpu1.inst 8228059 # number of overall hits 1920system.cpu1.l2cache.overall_hits::cpu1.data 3359120 # number of overall hits 1921system.cpu1.l2cache.overall_hits::total 12172815 # number of overall hits 1922system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 10577 # number of ReadReq misses 1923system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7168 # number of ReadReq misses 1924system.cpu1.l2cache.ReadReq_misses::total 17745 # number of ReadReq misses 1925system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 137373 # number of UpgradeReq misses 1926system.cpu1.l2cache.UpgradeReq_misses::total 137373 # number of UpgradeReq misses 1927system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 144729 # number of SCUpgradeReq misses 1928system.cpu1.l2cache.SCUpgradeReq_misses::total 144729 # number of SCUpgradeReq misses 1929system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses 1930system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses 1931system.cpu1.l2cache.ReadExReq_misses::cpu1.data 224779 # number of ReadExReq misses 1932system.cpu1.l2cache.ReadExReq_misses::total 224779 # number of ReadExReq misses 1933system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 734794 # number of ReadCleanReq misses 1934system.cpu1.l2cache.ReadCleanReq_misses::total 734794 # number of ReadCleanReq misses 1935system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 888888 # number of ReadSharedReq misses 1936system.cpu1.l2cache.ReadSharedReq_misses::total 888888 # number of ReadSharedReq misses 1937system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 252467 # number of InvalidateReq misses 1938system.cpu1.l2cache.InvalidateReq_misses::total 252467 # number of InvalidateReq misses 1939system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 10577 # number of demand (read+write) misses 1940system.cpu1.l2cache.demand_misses::cpu1.itb.walker 7168 # number of demand (read+write) misses 1941system.cpu1.l2cache.demand_misses::cpu1.inst 734794 # number of demand (read+write) misses 1942system.cpu1.l2cache.demand_misses::cpu1.data 1113667 # number of demand (read+write) misses 1943system.cpu1.l2cache.demand_misses::total 1866206 # number of demand (read+write) misses 1944system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 10577 # number of overall misses 1945system.cpu1.l2cache.overall_misses::cpu1.itb.walker 7168 # number of overall misses 1946system.cpu1.l2cache.overall_misses::cpu1.inst 734794 # number of overall misses 1947system.cpu1.l2cache.overall_misses::cpu1.data 1113667 # number of overall misses 1948system.cpu1.l2cache.overall_misses::total 1866206 # number of overall misses 1949system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 295249500 # number of ReadReq miss cycles 1950system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 216312000 # number of ReadReq miss cycles 1951system.cpu1.l2cache.ReadReq_miss_latency::total 511561500 # number of ReadReq miss cycles 1952system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2960853000 # number of UpgradeReq miss cycles 1953system.cpu1.l2cache.UpgradeReq_miss_latency::total 2960853000 # number of UpgradeReq miss cycles 1954system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 2990715499 # number of SCUpgradeReq miss cycles 1955system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 2990715499 # number of SCUpgradeReq miss cycles 1956system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2750499 # number of SCUpgradeFailReq miss cycles 1957system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2750499 # number of SCUpgradeFailReq miss cycles 1958system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 8344875497 # number of ReadExReq miss cycles 1959system.cpu1.l2cache.ReadExReq_miss_latency::total 8344875497 # number of ReadExReq miss cycles 1960system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 20496216000 # number of ReadCleanReq miss cycles 1961system.cpu1.l2cache.ReadCleanReq_miss_latency::total 20496216000 # number of ReadCleanReq miss cycles 1962system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 25619176492 # number of ReadSharedReq miss cycles 1963system.cpu1.l2cache.ReadSharedReq_miss_latency::total 25619176492 # number of ReadSharedReq miss cycles 1964system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 11469563500 # number of InvalidateReq miss cycles 1965system.cpu1.l2cache.InvalidateReq_miss_latency::total 11469563500 # number of InvalidateReq miss cycles 1966system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 295249500 # number of demand (read+write) miss cycles 1967system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 216312000 # number of demand (read+write) miss cycles 1968system.cpu1.l2cache.demand_miss_latency::cpu1.inst 20496216000 # number of demand (read+write) miss cycles 1969system.cpu1.l2cache.demand_miss_latency::cpu1.data 33964051989 # number of demand (read+write) miss cycles 1970system.cpu1.l2cache.demand_miss_latency::total 54971829489 # number of demand (read+write) miss cycles 1971system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 295249500 # number of overall miss cycles 1972system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 216312000 # number of overall miss cycles 1973system.cpu1.l2cache.overall_miss_latency::cpu1.inst 20496216000 # number of overall miss cycles 1974system.cpu1.l2cache.overall_miss_latency::cpu1.data 33964051989 # number of overall miss cycles 1975system.cpu1.l2cache.overall_miss_latency::total 54971829489 # number of overall miss cycles 1976system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 461364 # number of ReadReq accesses(hits+misses) 1977system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 142017 # number of ReadReq accesses(hits+misses) 1978system.cpu1.l2cache.ReadReq_accesses::total 603381 # number of ReadReq accesses(hits+misses) 1979system.cpu1.l2cache.Writeback_accesses::writebacks 3028606 # number of Writeback accesses(hits+misses) 1980system.cpu1.l2cache.Writeback_accesses::total 3028606 # number of Writeback accesses(hits+misses) 1981system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 193251 # number of UpgradeReq accesses(hits+misses) 1982system.cpu1.l2cache.UpgradeReq_accesses::total 193251 # number of UpgradeReq accesses(hits+misses) 1983system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 179070 # number of SCUpgradeReq accesses(hits+misses) 1984system.cpu1.l2cache.SCUpgradeReq_accesses::total 179070 # number of SCUpgradeReq accesses(hits+misses) 1985system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses) 1986system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) 1987system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 991451 # number of ReadExReq accesses(hits+misses) 1988system.cpu1.l2cache.ReadExReq_accesses::total 991451 # number of ReadExReq accesses(hits+misses) 1989system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 8962853 # number of ReadCleanReq accesses(hits+misses) 1990system.cpu1.l2cache.ReadCleanReq_accesses::total 8962853 # number of ReadCleanReq accesses(hits+misses) 1991system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3481336 # number of ReadSharedReq accesses(hits+misses) 1992system.cpu1.l2cache.ReadSharedReq_accesses::total 3481336 # number of ReadSharedReq accesses(hits+misses) 1993system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 420340 # number of InvalidateReq accesses(hits+misses) 1994system.cpu1.l2cache.InvalidateReq_accesses::total 420340 # number of InvalidateReq accesses(hits+misses) 1995system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 461364 # number of demand (read+write) accesses 1996system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 142017 # number of demand (read+write) accesses 1997system.cpu1.l2cache.demand_accesses::cpu1.inst 8962853 # number of demand (read+write) accesses 1998system.cpu1.l2cache.demand_accesses::cpu1.data 4472787 # number of demand (read+write) accesses 1999system.cpu1.l2cache.demand_accesses::total 14039021 # number of demand (read+write) accesses 2000system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 461364 # number of overall (read+write) accesses 2001system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 142017 # number of overall (read+write) accesses 2002system.cpu1.l2cache.overall_accesses::cpu1.inst 8962853 # number of overall (read+write) accesses 2003system.cpu1.l2cache.overall_accesses::cpu1.data 4472787 # number of overall (read+write) accesses 2004system.cpu1.l2cache.overall_accesses::total 14039021 # number of overall (read+write) accesses 2005system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.022925 # miss rate for ReadReq accesses 2006system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.050473 # miss rate for ReadReq accesses 2007system.cpu1.l2cache.ReadReq_miss_rate::total 0.029409 # miss rate for ReadReq accesses 2008system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.710853 # miss rate for UpgradeReq accesses 2009system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.710853 # miss rate for UpgradeReq accesses 2010system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.808226 # miss rate for SCUpgradeReq accesses 2011system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.808226 # miss rate for SCUpgradeReq accesses 2012system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2013system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2014system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.226717 # miss rate for ReadExReq accesses 2015system.cpu1.l2cache.ReadExReq_miss_rate::total 0.226717 # miss rate for ReadExReq accesses 2016system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.081982 # miss rate for ReadCleanReq accesses 2017system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.081982 # miss rate for ReadCleanReq accesses 2018system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.255330 # miss rate for ReadSharedReq accesses 2019system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.255330 # miss rate for ReadSharedReq accesses 2020system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.600626 # miss rate for InvalidateReq accesses 2021system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.600626 # miss rate for InvalidateReq accesses 2022system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.022925 # miss rate for demand accesses 2023system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.050473 # miss rate for demand accesses 2024system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.081982 # miss rate for demand accesses 2025system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.248987 # miss rate for demand accesses 2026system.cpu1.l2cache.demand_miss_rate::total 0.132930 # miss rate for demand accesses 2027system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.022925 # miss rate for overall accesses 2028system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.050473 # miss rate for overall accesses 2029system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.081982 # miss rate for overall accesses 2030system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.248987 # miss rate for overall accesses 2031system.cpu1.l2cache.overall_miss_rate::total 0.132930 # miss rate for overall accesses 2032system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 27914.295169 # average ReadReq miss latency 2033system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 30177.455357 # average ReadReq miss latency 2034system.cpu1.l2cache.ReadReq_avg_miss_latency::total 28828.486898 # average ReadReq miss latency 2035system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21553.383853 # average UpgradeReq miss latency 2036system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21553.383853 # average UpgradeReq miss latency 2037system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20664.244892 # average SCUpgradeReq miss latency 2038system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20664.244892 # average SCUpgradeReq miss latency 2039system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 458416.500000 # average SCUpgradeFailReq miss latency 2040system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 458416.500000 # average SCUpgradeFailReq miss latency 2041system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 37124.800346 # average ReadExReq miss latency 2042system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 37124.800346 # average ReadExReq miss latency 2043system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 27893.826025 # average ReadCleanReq miss latency 2044system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 27893.826025 # average ReadCleanReq miss latency 2045system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 28821.602375 # average ReadSharedReq miss latency 2046system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 28821.602375 # average ReadSharedReq miss latency 2047system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 45429.951241 # average InvalidateReq miss latency 2048system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 45429.951241 # average InvalidateReq miss latency 2049system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 27914.295169 # average overall miss latency 2050system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 30177.455357 # average overall miss latency 2051system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 27893.826025 # average overall miss latency 2052system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 30497.493406 # average overall miss latency 2053system.cpu1.l2cache.demand_avg_miss_latency::total 29456.463804 # average overall miss latency 2054system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 27914.295169 # average overall miss latency 2055system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 30177.455357 # average overall miss latency 2056system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 27893.826025 # average overall miss latency 2057system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 30497.493406 # average overall miss latency 2058system.cpu1.l2cache.overall_avg_miss_latency::total 29456.463804 # average overall miss latency 2059system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2060system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2061system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2062system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2063system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2064system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2065system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2066system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 2067system.cpu1.l2cache.writebacks::writebacks 853283 # number of writebacks 2068system.cpu1.l2cache.writebacks::total 853283 # number of writebacks 2069system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 2 # number of ReadReq MSHR hits 2070system.cpu1.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits 2071system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 3653 # number of ReadExReq MSHR hits 2072system.cpu1.l2cache.ReadExReq_mshr_hits::total 3653 # number of ReadExReq MSHR hits 2073system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 5 # number of ReadCleanReq MSHR hits 2074system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits 2075system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 365 # number of ReadSharedReq MSHR hits 2076system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 365 # number of ReadSharedReq MSHR hits 2077system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 2 # number of demand (read+write) MSHR hits 2078system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 5 # number of demand (read+write) MSHR hits 2079system.cpu1.l2cache.demand_mshr_hits::cpu1.data 4018 # number of demand (read+write) MSHR hits 2080system.cpu1.l2cache.demand_mshr_hits::total 4025 # number of demand (read+write) MSHR hits 2081system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 2 # number of overall MSHR hits 2082system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 5 # number of overall MSHR hits 2083system.cpu1.l2cache.overall_mshr_hits::cpu1.data 4018 # number of overall MSHR hits 2084system.cpu1.l2cache.overall_mshr_hits::total 4025 # number of overall MSHR hits 2085system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 10577 # number of ReadReq MSHR misses 2086system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 7166 # number of ReadReq MSHR misses 2087system.cpu1.l2cache.ReadReq_mshr_misses::total 17743 # number of ReadReq MSHR misses 2088system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 103597 # number of CleanEvict MSHR misses 2089system.cpu1.l2cache.CleanEvict_mshr_misses::total 103597 # number of CleanEvict MSHR misses 2090system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 615258 # number of HardPFReq MSHR misses 2091system.cpu1.l2cache.HardPFReq_mshr_misses::total 615258 # number of HardPFReq MSHR misses 2092system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 137373 # number of UpgradeReq MSHR misses 2093system.cpu1.l2cache.UpgradeReq_mshr_misses::total 137373 # number of UpgradeReq MSHR misses 2094system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 144729 # number of SCUpgradeReq MSHR misses 2095system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 144729 # number of SCUpgradeReq MSHR misses 2096system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 6 # number of SCUpgradeFailReq MSHR misses 2097system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses 2098system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 221126 # number of ReadExReq MSHR misses 2099system.cpu1.l2cache.ReadExReq_mshr_misses::total 221126 # number of ReadExReq MSHR misses 2100system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 734789 # number of ReadCleanReq MSHR misses 2101system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 734789 # number of ReadCleanReq MSHR misses 2102system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 888523 # number of ReadSharedReq MSHR misses 2103system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 888523 # number of ReadSharedReq MSHR misses 2104system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 252467 # number of InvalidateReq MSHR misses 2105system.cpu1.l2cache.InvalidateReq_mshr_misses::total 252467 # number of InvalidateReq MSHR misses 2106system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 10577 # number of demand (read+write) MSHR misses 2107system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 7166 # number of demand (read+write) MSHR misses 2108system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 734789 # number of demand (read+write) MSHR misses 2109system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1109649 # number of demand (read+write) MSHR misses 2110system.cpu1.l2cache.demand_mshr_misses::total 1862181 # number of demand (read+write) MSHR misses 2111system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 10577 # number of overall MSHR misses 2112system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 7166 # number of overall MSHR misses 2113system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 734789 # number of overall MSHR misses 2114system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1109649 # number of overall MSHR misses 2115system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 615258 # number of overall MSHR misses 2116system.cpu1.l2cache.overall_mshr_misses::total 2477439 # number of overall MSHR misses 2117system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable 2118system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 8249 # number of ReadReq MSHR uncacheable 2119system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 8342 # number of ReadReq MSHR uncacheable 2120system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 8420 # number of WriteReq MSHR uncacheable 2121system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 8420 # number of WriteReq MSHR uncacheable 2122system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses 2123system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 16669 # number of overall MSHR uncacheable misses 2124system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 16762 # number of overall MSHR uncacheable misses 2125system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 231787500 # number of ReadReq MSHR miss cycles 2126system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 173284500 # number of ReadReq MSHR miss cycles 2127system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 405072000 # number of ReadReq MSHR miss cycles 2128system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 18848278545 # number of HardPFReq MSHR miss cycles 2129system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 18848278545 # number of HardPFReq MSHR miss cycles 2130system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2780289998 # number of UpgradeReq MSHR miss cycles 2131system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2780289998 # number of UpgradeReq MSHR miss cycles 2132system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2207149499 # number of SCUpgradeReq MSHR miss cycles 2133system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2207149499 # number of SCUpgradeReq MSHR miss cycles 2134system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2390499 # number of SCUpgradeFailReq MSHR miss cycles 2135system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2390499 # number of SCUpgradeFailReq MSHR miss cycles 2136system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 6581571997 # number of ReadExReq MSHR miss cycles 2137system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 6581571997 # number of ReadExReq MSHR miss cycles 2138system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 16087394500 # number of ReadCleanReq MSHR miss cycles 2139system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 16087394500 # number of ReadCleanReq MSHR miss cycles 2140system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 20254649492 # number of ReadSharedReq MSHR miss cycles 2141system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 20254649492 # number of ReadSharedReq MSHR miss cycles 2142system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 9954761500 # number of InvalidateReq MSHR miss cycles 2143system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 9954761500 # number of InvalidateReq MSHR miss cycles 2144system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 231787500 # number of demand (read+write) MSHR miss cycles 2145system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 173284500 # number of demand (read+write) MSHR miss cycles 2146system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 16087394500 # number of demand (read+write) MSHR miss cycles 2147system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 26836221489 # number of demand (read+write) MSHR miss cycles 2148system.cpu1.l2cache.demand_mshr_miss_latency::total 43328687989 # number of demand (read+write) MSHR miss cycles 2149system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 231787500 # number of overall MSHR miss cycles 2150system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 173284500 # number of overall MSHR miss cycles 2151system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 16087394500 # number of overall MSHR miss cycles 2152system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 26836221489 # number of overall MSHR miss cycles 2153system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 18848278545 # number of overall MSHR miss cycles 2154system.cpu1.l2cache.overall_mshr_miss_latency::total 62176966534 # number of overall MSHR miss cycles 2155system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7998000 # number of ReadReq MSHR uncacheable cycles 2156system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1030068000 # number of ReadReq MSHR uncacheable cycles 2157system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1038066000 # number of ReadReq MSHR uncacheable cycles 2158system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1163435000 # number of WriteReq MSHR uncacheable cycles 2159system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1163435000 # number of WriteReq MSHR uncacheable cycles 2160system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7998000 # number of overall MSHR uncacheable cycles 2161system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2193503000 # number of overall MSHR uncacheable cycles 2162system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2201501000 # number of overall MSHR uncacheable cycles 2163system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022925 # mshr miss rate for ReadReq accesses 2164system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.050459 # mshr miss rate for ReadReq accesses 2165system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.029406 # mshr miss rate for ReadReq accesses 2166system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2167system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2168system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2169system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2170system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.710853 # mshr miss rate for UpgradeReq accesses 2171system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.710853 # mshr miss rate for UpgradeReq accesses 2172system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.808226 # mshr miss rate for SCUpgradeReq accesses 2173system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.808226 # mshr miss rate for SCUpgradeReq accesses 2174system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2175system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2176system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.223033 # mshr miss rate for ReadExReq accesses 2177system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.223033 # mshr miss rate for ReadExReq accesses 2178system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.081982 # mshr miss rate for ReadCleanReq accesses 2179system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.081982 # mshr miss rate for ReadCleanReq accesses 2180system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.255225 # mshr miss rate for ReadSharedReq accesses 2181system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.255225 # mshr miss rate for ReadSharedReq accesses 2182system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.600626 # mshr miss rate for InvalidateReq accesses 2183system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.600626 # mshr miss rate for InvalidateReq accesses 2184system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022925 # mshr miss rate for demand accesses 2185system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.050459 # mshr miss rate for demand accesses 2186system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.081982 # mshr miss rate for demand accesses 2187system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.248089 # mshr miss rate for demand accesses 2188system.cpu1.l2cache.demand_mshr_miss_rate::total 0.132643 # mshr miss rate for demand accesses 2189system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022925 # mshr miss rate for overall accesses 2190system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050459 # mshr miss rate for overall accesses 2191system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.081982 # mshr miss rate for overall accesses 2192system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.248089 # mshr miss rate for overall accesses 2193system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2194system.cpu1.l2cache.overall_mshr_miss_rate::total 0.176468 # mshr miss rate for overall accesses 2195system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 21914.295169 # average ReadReq mshr miss latency 2196system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 24181.481998 # average ReadReq mshr miss latency 2197system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 22829.961111 # average ReadReq mshr miss latency 2198system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30634.755737 # average HardPFReq mshr miss latency 2199system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 30634.755737 # average HardPFReq mshr miss latency 2200system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20238.984356 # average UpgradeReq mshr miss latency 2201system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20238.984356 # average UpgradeReq mshr miss latency 2202system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15250.222823 # average SCUpgradeReq mshr miss latency 2203system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15250.222823 # average SCUpgradeReq mshr miss latency 2204system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 398416.500000 # average SCUpgradeFailReq mshr miss latency 2205system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 398416.500000 # average SCUpgradeFailReq mshr miss latency 2206system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29763.899302 # average ReadExReq mshr miss latency 2207system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29763.899302 # average ReadExReq mshr miss latency 2208system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 21893.896751 # average ReadCleanReq mshr miss latency 2209system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 21893.896751 # average ReadCleanReq mshr miss latency 2210system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 22795.864026 # average ReadSharedReq mshr miss latency 2211system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 22795.864026 # average ReadSharedReq mshr miss latency 2212system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 39429.951241 # average InvalidateReq mshr miss latency 2213system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 39429.951241 # average InvalidateReq mshr miss latency 2214system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 21914.295169 # average overall mshr miss latency 2215system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 24181.481998 # average overall mshr miss latency 2216system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21893.896751 # average overall mshr miss latency 2217system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24184.423623 # average overall mshr miss latency 2218system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23267.710276 # average overall mshr miss latency 2219system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 21914.295169 # average overall mshr miss latency 2220system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 24181.481998 # average overall mshr miss latency 2221system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21893.896751 # average overall mshr miss latency 2222system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24184.423623 # average overall mshr miss latency 2223system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30634.755737 # average overall mshr miss latency 2224system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25097.274457 # average overall mshr miss latency 2225system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86000 # average ReadReq mshr uncacheable latency 2226system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 124871.863256 # average ReadReq mshr uncacheable latency 2227system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 124438.503956 # average ReadReq mshr uncacheable latency 2228system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 138175.178147 # average WriteReq mshr uncacheable latency 2229system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 138175.178147 # average WriteReq mshr uncacheable latency 2230system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86000 # average overall mshr uncacheable latency 2231system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 131591.757154 # average overall mshr uncacheable latency 2232system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 131338.802052 # average overall mshr uncacheable latency 2233system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2234system.cpu1.toL2Bus.trans_dist::ReadReq 832335 # Transaction distribution 2235system.cpu1.toL2Bus.trans_dist::ReadResp 13281124 # Transaction distribution 2236system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution 2237system.cpu1.toL2Bus.trans_dist::WriteReq 38305 # Transaction distribution 2238system.cpu1.toL2Bus.trans_dist::WriteResp 8420 # Transaction distribution 2239system.cpu1.toL2Bus.trans_dist::Writeback 6193652 # Transaction distribution 2240system.cpu1.toL2Bus.trans_dist::CleanEvict 13562835 # Transaction distribution 2241system.cpu1.toL2Bus.trans_dist::HardPFReq 802874 # Transaction distribution 2242system.cpu1.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution 2243system.cpu1.toL2Bus.trans_dist::UpgradeReq 426908 # Transaction distribution 2244system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 320139 # Transaction distribution 2245system.cpu1.toL2Bus.trans_dist::UpgradeResp 432313 # Transaction distribution 2246system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 51 # Transaction distribution 2247system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 105 # Transaction distribution 2248system.cpu1.toL2Bus.trans_dist::ReadExReq 1723284 # Transaction distribution 2249system.cpu1.toL2Bus.trans_dist::ReadExResp 998712 # Transaction distribution 2250system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8962853 # Transaction distribution 2251system.cpu1.toL2Bus.trans_dist::ReadSharedReq 5808138 # Transaction distribution 2252system.cpu1.toL2Bus.trans_dist::InvalidateReq 527324 # Transaction distribution 2253system.cpu1.toL2Bus.trans_dist::InvalidateResp 420340 # Transaction distribution 2254system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 26886674 # Packet count per connected master and slave (bytes) 2255system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15523980 # Packet count per connected master and slave (bytes) 2256system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 318688 # Packet count per connected master and slave (bytes) 2257system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1026227 # Packet count per connected master and slave (bytes) 2258system.cpu1.toL2Bus.pkt_count::total 43755569 # Packet count per connected master and slave (bytes) 2259system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 573628544 # Cumulative packet size per connected master and slave (bytes) 2260system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 486175782 # Cumulative packet size per connected master and slave (bytes) 2261system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1136136 # Cumulative packet size per connected master and slave (bytes) 2262system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3690912 # Cumulative packet size per connected master and slave (bytes) 2263system.cpu1.toL2Bus.pkt_size::total 1064631374 # Cumulative packet size per connected master and slave (bytes) 2264system.cpu1.toL2Bus.snoops 10738560 # Total snoops (count) 2265system.cpu1.toL2Bus.snoop_fanout::samples 39200977 # Request fanout histogram 2266system.cpu1.toL2Bus.snoop_fanout::mean 1.285389 # Request fanout histogram 2267system.cpu1.toL2Bus.snoop_fanout::stdev 0.451600 # Request fanout histogram 2268system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2269system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2270system.cpu1.toL2Bus.snoop_fanout::1 28013450 71.46% 71.46% # Request fanout histogram 2271system.cpu1.toL2Bus.snoop_fanout::2 11187527 28.54% 100.00% # Request fanout histogram 2272system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2273system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 2274system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2275system.cpu1.toL2Bus.snoop_fanout::total 39200977 # Request fanout histogram 2276system.cpu1.toL2Bus.reqLayer0.occupancy 17410316483 # Layer occupancy (ticks) 2277system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2278system.cpu1.toL2Bus.snoopLayer0.occupancy 171564976 # Layer occupancy (ticks) 2279system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2280system.cpu1.toL2Bus.respLayer0.occupancy 13446378573 # Layer occupancy (ticks) 2281system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2282system.cpu1.toL2Bus.respLayer1.occupancy 7120820957 # Layer occupancy (ticks) 2283system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2284system.cpu1.toL2Bus.respLayer2.occupancy 176677986 # Layer occupancy (ticks) 2285system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2286system.cpu1.toL2Bus.respLayer3.occupancy 564893937 # Layer occupancy (ticks) 2287system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2288system.iobus.trans_dist::ReadReq 40371 # Transaction distribution 2289system.iobus.trans_dist::ReadResp 40371 # Transaction distribution 2290system.iobus.trans_dist::WriteReq 136979 # Transaction distribution 2291system.iobus.trans_dist::WriteResp 136979 # Transaction distribution 2292system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47802 # Packet count per connected master and slave (bytes) 2293system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2294system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2295system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2296system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2297system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2298system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2299system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2300system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2301system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2302system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) 2303system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2304system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 2305system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2306system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 2307system.iobus.pkt_count_system.bridge.master::total 122944 # Packet count per connected master and slave (bytes) 2308system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231676 # Packet count per connected master and slave (bytes) 2309system.iobus.pkt_count_system.realview.ide.dma::total 231676 # Packet count per connected master and slave (bytes) 2310system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2311system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 2312system.iobus.pkt_count::total 354700 # Packet count per connected master and slave (bytes) 2313system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47822 # Cumulative packet size per connected master and slave (bytes) 2314system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2315system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2316system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2317system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2318system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2319system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2320system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2321system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2322system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2323system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) 2324system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 2325system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 2326system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 2327system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 2328system.iobus.pkt_size_system.bridge.master::total 155959 # Cumulative packet size per connected master and slave (bytes) 2329system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355056 # Cumulative packet size per connected master and slave (bytes) 2330system.iobus.pkt_size_system.realview.ide.dma::total 7355056 # Cumulative packet size per connected master and slave (bytes) 2331system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2332system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 2333system.iobus.pkt_size::total 7513101 # Cumulative packet size per connected master and slave (bytes) 2334system.iobus.reqLayer0.occupancy 36314000 # Layer occupancy (ticks) 2335system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2336system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 2337system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2338system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 2339system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2340system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 2341system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2342system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 2343system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2344system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 2345system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2346system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 2347system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2348system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 2349system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2350system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 2351system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2352system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 2353system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2354system.iobus.reqLayer23.occupancy 22142000 # Layer occupancy (ticks) 2355system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2356system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 2357system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2358system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 2359system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2360system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 2361system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 2362system.iobus.reqLayer27.occupancy 570865133 # Layer occupancy (ticks) 2363system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2364system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2365system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 2366system.iobus.respLayer0.occupancy 92952000 # Layer occupancy (ticks) 2367system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2368system.iobus.respLayer3.occupancy 148116000 # Layer occupancy (ticks) 2369system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2370system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 2371system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 2372system.iocache.tags.replacements 115819 # number of replacements 2373system.iocache.tags.tagsinuse 11.287255 # Cycle average of tags in use 2374system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 2375system.iocache.tags.sampled_refs 115835 # Sample count of references to valid blocks. 2376system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 2377system.iocache.tags.warmup_cycle 9174218723000 # Cycle when the warmup percentage was hit. 2378system.iocache.tags.occ_blocks::realview.ethernet 3.836610 # Average occupied blocks per requestor 2379system.iocache.tags.occ_blocks::realview.ide 7.450645 # Average occupied blocks per requestor 2380system.iocache.tags.occ_percent::realview.ethernet 0.239788 # Average percentage of cache occupancy 2381system.iocache.tags.occ_percent::realview.ide 0.465665 # Average percentage of cache occupancy 2382system.iocache.tags.occ_percent::total 0.705453 # Average percentage of cache occupancy 2383system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2384system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2385system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2386system.iocache.tags.tag_accesses 1042899 # Number of tag accesses 2387system.iocache.tags.data_accesses 1042899 # Number of data accesses 2388system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2389system.iocache.ReadReq_misses::realview.ide 8854 # number of ReadReq misses 2390system.iocache.ReadReq_misses::total 8891 # number of ReadReq misses 2391system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2392system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2393system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses 2394system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses 2395system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 2396system.iocache.demand_misses::realview.ide 8854 # number of demand (read+write) misses 2397system.iocache.demand_misses::total 8894 # number of demand (read+write) misses 2398system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 2399system.iocache.overall_misses::realview.ide 8854 # number of overall misses 2400system.iocache.overall_misses::total 8894 # number of overall misses 2401system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles 2402system.iocache.ReadReq_miss_latency::realview.ide 1658968057 # number of ReadReq miss cycles 2403system.iocache.ReadReq_miss_latency::total 1664163057 # number of ReadReq miss cycles 2404system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 2405system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 2406system.iocache.WriteLineReq_miss_latency::realview.ide 12654105076 # number of WriteLineReq miss cycles 2407system.iocache.WriteLineReq_miss_latency::total 12654105076 # number of WriteLineReq miss cycles 2408system.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles 2409system.iocache.demand_miss_latency::realview.ide 1658968057 # number of demand (read+write) miss cycles 2410system.iocache.demand_miss_latency::total 1664532057 # number of demand (read+write) miss cycles 2411system.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles 2412system.iocache.overall_miss_latency::realview.ide 1658968057 # number of overall miss cycles 2413system.iocache.overall_miss_latency::total 1664532057 # number of overall miss cycles 2414system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 2415system.iocache.ReadReq_accesses::realview.ide 8854 # number of ReadReq accesses(hits+misses) 2416system.iocache.ReadReq_accesses::total 8891 # number of ReadReq accesses(hits+misses) 2417system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2418system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2419system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) 2420system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) 2421system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 2422system.iocache.demand_accesses::realview.ide 8854 # number of demand (read+write) accesses 2423system.iocache.demand_accesses::total 8894 # number of demand (read+write) accesses 2424system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 2425system.iocache.overall_accesses::realview.ide 8854 # number of overall (read+write) accesses 2426system.iocache.overall_accesses::total 8894 # number of overall (read+write) accesses 2427system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2428system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2429system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2430system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2431system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2432system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2433system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2434system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2435system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2436system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2437system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2438system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2439system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2440system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency 2441system.iocache.ReadReq_avg_miss_latency::realview.ide 187369.331037 # average ReadReq miss latency 2442system.iocache.ReadReq_avg_miss_latency::total 187173.890114 # average ReadReq miss latency 2443system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 2444system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 2445system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118280.351043 # average WriteLineReq miss latency 2446system.iocache.WriteLineReq_avg_miss_latency::total 118280.351043 # average WriteLineReq miss latency 2447system.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency 2448system.iocache.demand_avg_miss_latency::realview.ide 187369.331037 # average overall miss latency 2449system.iocache.demand_avg_miss_latency::total 187152.243872 # average overall miss latency 2450system.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency 2451system.iocache.overall_avg_miss_latency::realview.ide 187369.331037 # average overall miss latency 2452system.iocache.overall_avg_miss_latency::total 187152.243872 # average overall miss latency 2453system.iocache.blocked_cycles::no_mshrs 32802 # number of cycles access was blocked 2454system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2455system.iocache.blocked::no_mshrs 3449 # number of cycles access was blocked 2456system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2457system.iocache.avg_blocked_cycles::no_mshrs 9.510583 # average number of cycles each access was blocked 2458system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2459system.iocache.fast_writes 0 # number of fast writes performed 2460system.iocache.cache_copies 0 # number of cache copies performed 2461system.iocache.writebacks::writebacks 106950 # number of writebacks 2462system.iocache.writebacks::total 106950 # number of writebacks 2463system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 2464system.iocache.ReadReq_mshr_misses::realview.ide 8854 # number of ReadReq MSHR misses 2465system.iocache.ReadReq_mshr_misses::total 8891 # number of ReadReq MSHR misses 2466system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2467system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2468system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses 2469system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses 2470system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 2471system.iocache.demand_mshr_misses::realview.ide 8854 # number of demand (read+write) MSHR misses 2472system.iocache.demand_mshr_misses::total 8894 # number of demand (read+write) MSHR misses 2473system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 2474system.iocache.overall_mshr_misses::realview.ide 8854 # number of overall MSHR misses 2475system.iocache.overall_mshr_misses::total 8894 # number of overall MSHR misses 2476system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3345000 # number of ReadReq MSHR miss cycles 2477system.iocache.ReadReq_mshr_miss_latency::realview.ide 1216268057 # number of ReadReq MSHR miss cycles 2478system.iocache.ReadReq_mshr_miss_latency::total 1219613057 # number of ReadReq MSHR miss cycles 2479system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 2480system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 2481system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7304905076 # number of WriteLineReq MSHR miss cycles 2482system.iocache.WriteLineReq_mshr_miss_latency::total 7304905076 # number of WriteLineReq MSHR miss cycles 2483system.iocache.demand_mshr_miss_latency::realview.ethernet 3564000 # number of demand (read+write) MSHR miss cycles 2484system.iocache.demand_mshr_miss_latency::realview.ide 1216268057 # number of demand (read+write) MSHR miss cycles 2485system.iocache.demand_mshr_miss_latency::total 1219832057 # number of demand (read+write) MSHR miss cycles 2486system.iocache.overall_mshr_miss_latency::realview.ethernet 3564000 # number of overall MSHR miss cycles 2487system.iocache.overall_mshr_miss_latency::realview.ide 1216268057 # number of overall MSHR miss cycles 2488system.iocache.overall_mshr_miss_latency::total 1219832057 # number of overall MSHR miss cycles 2489system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2490system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2491system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2492system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2493system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2494system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2495system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2496system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 2497system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2498system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2499system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 2500system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2501system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2502system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency 2503system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137369.331037 # average ReadReq mshr miss latency 2504system.iocache.ReadReq_avg_mshr_miss_latency::total 137173.890114 # average ReadReq mshr miss latency 2505system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 2506system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 2507system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68280.351043 # average WriteLineReq mshr miss latency 2508system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68280.351043 # average WriteLineReq mshr miss latency 2509system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency 2510system.iocache.demand_avg_mshr_miss_latency::realview.ide 137369.331037 # average overall mshr miss latency 2511system.iocache.demand_avg_mshr_miss_latency::total 137152.243872 # average overall mshr miss latency 2512system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency 2513system.iocache.overall_avg_mshr_miss_latency::realview.ide 137369.331037 # average overall mshr miss latency 2514system.iocache.overall_avg_mshr_miss_latency::total 137152.243872 # average overall mshr miss latency 2515system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2516system.l2c.tags.replacements 1146599 # number of replacements 2517system.l2c.tags.tagsinuse 63894.227459 # Cycle average of tags in use 2518system.l2c.tags.total_refs 5787888 # Total number of references to valid blocks. 2519system.l2c.tags.sampled_refs 1208030 # Sample count of references to valid blocks. 2520system.l2c.tags.avg_refs 4.791179 # Average number of references to valid blocks. 2521system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2522system.l2c.tags.occ_blocks::writebacks 20522.379023 # Average occupied blocks per requestor 2523system.l2c.tags.occ_blocks::cpu0.dtb.walker 161.905583 # Average occupied blocks per requestor 2524system.l2c.tags.occ_blocks::cpu0.itb.walker 188.170352 # Average occupied blocks per requestor 2525system.l2c.tags.occ_blocks::cpu0.inst 7049.393840 # Average occupied blocks per requestor 2526system.l2c.tags.occ_blocks::cpu0.data 11329.558347 # Average occupied blocks per requestor 2527system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 10071.994886 # Average occupied blocks per requestor 2528system.l2c.tags.occ_blocks::cpu1.dtb.walker 91.721739 # Average occupied blocks per requestor 2529system.l2c.tags.occ_blocks::cpu1.itb.walker 112.803397 # Average occupied blocks per requestor 2530system.l2c.tags.occ_blocks::cpu1.inst 4897.031985 # Average occupied blocks per requestor 2531system.l2c.tags.occ_blocks::cpu1.data 4344.569454 # Average occupied blocks per requestor 2532system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 5124.698853 # Average occupied blocks per requestor 2533system.l2c.tags.occ_percent::writebacks 0.313147 # Average percentage of cache occupancy 2534system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002470 # Average percentage of cache occupancy 2535system.l2c.tags.occ_percent::cpu0.itb.walker 0.002871 # Average percentage of cache occupancy 2536system.l2c.tags.occ_percent::cpu0.inst 0.107565 # Average percentage of cache occupancy 2537system.l2c.tags.occ_percent::cpu0.data 0.172875 # Average percentage of cache occupancy 2538system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.153686 # Average percentage of cache occupancy 2539system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001400 # Average percentage of cache occupancy 2540system.l2c.tags.occ_percent::cpu1.itb.walker 0.001721 # Average percentage of cache occupancy 2541system.l2c.tags.occ_percent::cpu1.inst 0.074723 # Average percentage of cache occupancy 2542system.l2c.tags.occ_percent::cpu1.data 0.066293 # Average percentage of cache occupancy 2543system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.078197 # Average percentage of cache occupancy 2544system.l2c.tags.occ_percent::total 0.974949 # Average percentage of cache occupancy 2545system.l2c.tags.occ_task_id_blocks::1022 10689 # Occupied blocks per task id 2546system.l2c.tags.occ_task_id_blocks::1023 178 # Occupied blocks per task id 2547system.l2c.tags.occ_task_id_blocks::1024 50564 # Occupied blocks per task id 2548system.l2c.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id 2549system.l2c.tags.age_task_id_blocks_1022::2 577 # Occupied blocks per task id 2550system.l2c.tags.age_task_id_blocks_1022::3 2554 # Occupied blocks per task id 2551system.l2c.tags.age_task_id_blocks_1022::4 7550 # Occupied blocks per task id 2552system.l2c.tags.age_task_id_blocks_1023::3 6 # Occupied blocks per task id 2553system.l2c.tags.age_task_id_blocks_1023::4 172 # Occupied blocks per task id 2554system.l2c.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 2555system.l2c.tags.age_task_id_blocks_1024::1 271 # Occupied blocks per task id 2556system.l2c.tags.age_task_id_blocks_1024::2 1822 # Occupied blocks per task id 2557system.l2c.tags.age_task_id_blocks_1024::3 12846 # Occupied blocks per task id 2558system.l2c.tags.age_task_id_blocks_1024::4 35586 # Occupied blocks per task id 2559system.l2c.tags.occ_task_id_percent::1022 0.163101 # Percentage of cache occupancy per task id 2560system.l2c.tags.occ_task_id_percent::1023 0.002716 # Percentage of cache occupancy per task id 2561system.l2c.tags.occ_task_id_percent::1024 0.771545 # Percentage of cache occupancy per task id 2562system.l2c.tags.tag_accesses 67839853 # Number of tag accesses 2563system.l2c.tags.data_accesses 67839853 # Number of data accesses 2564system.l2c.Writeback_hits::writebacks 2183647 # number of Writeback hits 2565system.l2c.Writeback_hits::total 2183647 # number of Writeback hits 2566system.l2c.UpgradeReq_hits::cpu0.data 31153 # number of UpgradeReq hits 2567system.l2c.UpgradeReq_hits::cpu1.data 25605 # number of UpgradeReq hits 2568system.l2c.UpgradeReq_hits::total 56758 # number of UpgradeReq hits 2569system.l2c.SCUpgradeReq_hits::cpu0.data 6308 # number of SCUpgradeReq hits 2570system.l2c.SCUpgradeReq_hits::cpu1.data 5360 # number of SCUpgradeReq hits 2571system.l2c.SCUpgradeReq_hits::total 11668 # number of SCUpgradeReq hits 2572system.l2c.ReadExReq_hits::cpu0.data 179937 # number of ReadExReq hits 2573system.l2c.ReadExReq_hits::cpu1.data 157833 # number of ReadExReq hits 2574system.l2c.ReadExReq_hits::total 337770 # number of ReadExReq hits 2575system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6619 # number of ReadSharedReq hits 2576system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4994 # number of ReadSharedReq hits 2577system.l2c.ReadSharedReq_hits::cpu0.inst 688403 # number of ReadSharedReq hits 2578system.l2c.ReadSharedReq_hits::cpu0.data 550904 # number of ReadSharedReq hits 2579system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 317834 # number of ReadSharedReq hits 2580system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5630 # number of ReadSharedReq hits 2581system.l2c.ReadSharedReq_hits::cpu1.itb.walker 3645 # number of ReadSharedReq hits 2582system.l2c.ReadSharedReq_hits::cpu1.inst 689738 # number of ReadSharedReq hits 2583system.l2c.ReadSharedReq_hits::cpu1.data 516463 # number of ReadSharedReq hits 2584system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 301818 # number of ReadSharedReq hits 2585system.l2c.ReadSharedReq_hits::total 3086048 # number of ReadSharedReq hits 2586system.l2c.demand_hits::cpu0.dtb.walker 6619 # number of demand (read+write) hits 2587system.l2c.demand_hits::cpu0.itb.walker 4994 # number of demand (read+write) hits 2588system.l2c.demand_hits::cpu0.inst 688403 # number of demand (read+write) hits 2589system.l2c.demand_hits::cpu0.data 730841 # number of demand (read+write) hits 2590system.l2c.demand_hits::cpu0.l2cache.prefetcher 317834 # number of demand (read+write) hits 2591system.l2c.demand_hits::cpu1.dtb.walker 5630 # number of demand (read+write) hits 2592system.l2c.demand_hits::cpu1.itb.walker 3645 # number of demand (read+write) hits 2593system.l2c.demand_hits::cpu1.inst 689738 # number of demand (read+write) hits 2594system.l2c.demand_hits::cpu1.data 674296 # number of demand (read+write) hits 2595system.l2c.demand_hits::cpu1.l2cache.prefetcher 301818 # number of demand (read+write) hits 2596system.l2c.demand_hits::total 3423818 # number of demand (read+write) hits 2597system.l2c.overall_hits::cpu0.dtb.walker 6619 # number of overall hits 2598system.l2c.overall_hits::cpu0.itb.walker 4994 # number of overall hits 2599system.l2c.overall_hits::cpu0.inst 688403 # number of overall hits 2600system.l2c.overall_hits::cpu0.data 730841 # number of overall hits 2601system.l2c.overall_hits::cpu0.l2cache.prefetcher 317834 # number of overall hits 2602system.l2c.overall_hits::cpu1.dtb.walker 5630 # number of overall hits 2603system.l2c.overall_hits::cpu1.itb.walker 3645 # number of overall hits 2604system.l2c.overall_hits::cpu1.inst 689738 # number of overall hits 2605system.l2c.overall_hits::cpu1.data 674296 # number of overall hits 2606system.l2c.overall_hits::cpu1.l2cache.prefetcher 301818 # number of overall hits 2607system.l2c.overall_hits::total 3423818 # number of overall hits 2608system.l2c.UpgradeReq_misses::cpu0.data 42274 # number of UpgradeReq misses 2609system.l2c.UpgradeReq_misses::cpu1.data 44615 # number of UpgradeReq misses 2610system.l2c.UpgradeReq_misses::total 86889 # number of UpgradeReq misses 2611system.l2c.SCUpgradeReq_misses::cpu0.data 8694 # number of SCUpgradeReq misses 2612system.l2c.SCUpgradeReq_misses::cpu1.data 8260 # number of SCUpgradeReq misses 2613system.l2c.SCUpgradeReq_misses::total 16954 # number of SCUpgradeReq misses 2614system.l2c.ReadExReq_misses::cpu0.data 478873 # number of ReadExReq misses 2615system.l2c.ReadExReq_misses::cpu1.data 118092 # number of ReadExReq misses 2616system.l2c.ReadExReq_misses::total 596965 # number of ReadExReq misses 2617system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1177 # number of ReadSharedReq misses 2618system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1112 # number of ReadSharedReq misses 2619system.l2c.ReadSharedReq_misses::cpu0.inst 65012 # number of ReadSharedReq misses 2620system.l2c.ReadSharedReq_misses::cpu0.data 121116 # number of ReadSharedReq misses 2621system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 167688 # number of ReadSharedReq misses 2622system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 801 # number of ReadSharedReq misses 2623system.l2c.ReadSharedReq_misses::cpu1.itb.walker 747 # number of ReadSharedReq misses 2624system.l2c.ReadSharedReq_misses::cpu1.inst 45048 # number of ReadSharedReq misses 2625system.l2c.ReadSharedReq_misses::cpu1.data 75565 # number of ReadSharedReq misses 2626system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 121227 # number of ReadSharedReq misses 2627system.l2c.ReadSharedReq_misses::total 599493 # number of ReadSharedReq misses 2628system.l2c.demand_misses::cpu0.dtb.walker 1177 # number of demand (read+write) misses 2629system.l2c.demand_misses::cpu0.itb.walker 1112 # number of demand (read+write) misses 2630system.l2c.demand_misses::cpu0.inst 65012 # number of demand (read+write) misses 2631system.l2c.demand_misses::cpu0.data 599989 # number of demand (read+write) misses 2632system.l2c.demand_misses::cpu0.l2cache.prefetcher 167688 # number of demand (read+write) misses 2633system.l2c.demand_misses::cpu1.dtb.walker 801 # number of demand (read+write) misses 2634system.l2c.demand_misses::cpu1.itb.walker 747 # number of demand (read+write) misses 2635system.l2c.demand_misses::cpu1.inst 45048 # number of demand (read+write) misses 2636system.l2c.demand_misses::cpu1.data 193657 # number of demand (read+write) misses 2637system.l2c.demand_misses::cpu1.l2cache.prefetcher 121227 # number of demand (read+write) misses 2638system.l2c.demand_misses::total 1196458 # number of demand (read+write) misses 2639system.l2c.overall_misses::cpu0.dtb.walker 1177 # number of overall misses 2640system.l2c.overall_misses::cpu0.itb.walker 1112 # number of overall misses 2641system.l2c.overall_misses::cpu0.inst 65012 # number of overall misses 2642system.l2c.overall_misses::cpu0.data 599989 # number of overall misses 2643system.l2c.overall_misses::cpu0.l2cache.prefetcher 167688 # number of overall misses 2644system.l2c.overall_misses::cpu1.dtb.walker 801 # number of overall misses 2645system.l2c.overall_misses::cpu1.itb.walker 747 # number of overall misses 2646system.l2c.overall_misses::cpu1.inst 45048 # number of overall misses 2647system.l2c.overall_misses::cpu1.data 193657 # number of overall misses 2648system.l2c.overall_misses::cpu1.l2cache.prefetcher 121227 # number of overall misses 2649system.l2c.overall_misses::total 1196458 # number of overall misses 2650system.l2c.UpgradeReq_miss_latency::cpu0.data 285461500 # number of UpgradeReq miss cycles 2651system.l2c.UpgradeReq_miss_latency::cpu1.data 257633000 # number of UpgradeReq miss cycles 2652system.l2c.UpgradeReq_miss_latency::total 543094500 # number of UpgradeReq miss cycles 2653system.l2c.SCUpgradeReq_miss_latency::cpu0.data 50714500 # number of SCUpgradeReq miss cycles 2654system.l2c.SCUpgradeReq_miss_latency::cpu1.data 48938500 # number of SCUpgradeReq miss cycles 2655system.l2c.SCUpgradeReq_miss_latency::total 99653000 # number of SCUpgradeReq miss cycles 2656system.l2c.ReadExReq_miss_latency::cpu0.data 44986860000 # number of ReadExReq miss cycles 2657system.l2c.ReadExReq_miss_latency::cpu1.data 9946118500 # number of ReadExReq miss cycles 2658system.l2c.ReadExReq_miss_latency::total 54932978500 # number of ReadExReq miss cycles 2659system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 102808500 # number of ReadSharedReq miss cycles 2660system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 98262500 # number of ReadSharedReq miss cycles 2661system.l2c.ReadSharedReq_miss_latency::cpu0.inst 5348800500 # number of ReadSharedReq miss cycles 2662system.l2c.ReadSharedReq_miss_latency::cpu0.data 10715307000 # number of ReadSharedReq miss cycles 2663system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 19492330795 # number of ReadSharedReq miss cycles 2664system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 71359500 # number of ReadSharedReq miss cycles 2665system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 66724500 # number of ReadSharedReq miss cycles 2666system.l2c.ReadSharedReq_miss_latency::cpu1.inst 3695471500 # number of ReadSharedReq miss cycles 2667system.l2c.ReadSharedReq_miss_latency::cpu1.data 6552252500 # number of ReadSharedReq miss cycles 2668system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 13803765015 # number of ReadSharedReq miss cycles 2669system.l2c.ReadSharedReq_miss_latency::total 59947082310 # number of ReadSharedReq miss cycles 2670system.l2c.demand_miss_latency::cpu0.dtb.walker 102808500 # number of demand (read+write) miss cycles 2671system.l2c.demand_miss_latency::cpu0.itb.walker 98262500 # number of demand (read+write) miss cycles 2672system.l2c.demand_miss_latency::cpu0.inst 5348800500 # number of demand (read+write) miss cycles 2673system.l2c.demand_miss_latency::cpu0.data 55702167000 # number of demand (read+write) miss cycles 2674system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 19492330795 # number of demand (read+write) miss cycles 2675system.l2c.demand_miss_latency::cpu1.dtb.walker 71359500 # number of demand (read+write) miss cycles 2676system.l2c.demand_miss_latency::cpu1.itb.walker 66724500 # number of demand (read+write) miss cycles 2677system.l2c.demand_miss_latency::cpu1.inst 3695471500 # number of demand (read+write) miss cycles 2678system.l2c.demand_miss_latency::cpu1.data 16498371000 # number of demand (read+write) miss cycles 2679system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 13803765015 # number of demand (read+write) miss cycles 2680system.l2c.demand_miss_latency::total 114880060810 # number of demand (read+write) miss cycles 2681system.l2c.overall_miss_latency::cpu0.dtb.walker 102808500 # number of overall miss cycles 2682system.l2c.overall_miss_latency::cpu0.itb.walker 98262500 # number of overall miss cycles 2683system.l2c.overall_miss_latency::cpu0.inst 5348800500 # number of overall miss cycles 2684system.l2c.overall_miss_latency::cpu0.data 55702167000 # number of overall miss cycles 2685system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 19492330795 # number of overall miss cycles 2686system.l2c.overall_miss_latency::cpu1.dtb.walker 71359500 # number of overall miss cycles 2687system.l2c.overall_miss_latency::cpu1.itb.walker 66724500 # number of overall miss cycles 2688system.l2c.overall_miss_latency::cpu1.inst 3695471500 # number of overall miss cycles 2689system.l2c.overall_miss_latency::cpu1.data 16498371000 # number of overall miss cycles 2690system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 13803765015 # number of overall miss cycles 2691system.l2c.overall_miss_latency::total 114880060810 # number of overall miss cycles 2692system.l2c.Writeback_accesses::writebacks 2183647 # number of Writeback accesses(hits+misses) 2693system.l2c.Writeback_accesses::total 2183647 # number of Writeback accesses(hits+misses) 2694system.l2c.UpgradeReq_accesses::cpu0.data 73427 # number of UpgradeReq accesses(hits+misses) 2695system.l2c.UpgradeReq_accesses::cpu1.data 70220 # number of UpgradeReq accesses(hits+misses) 2696system.l2c.UpgradeReq_accesses::total 143647 # number of UpgradeReq accesses(hits+misses) 2697system.l2c.SCUpgradeReq_accesses::cpu0.data 15002 # number of SCUpgradeReq accesses(hits+misses) 2698system.l2c.SCUpgradeReq_accesses::cpu1.data 13620 # number of SCUpgradeReq accesses(hits+misses) 2699system.l2c.SCUpgradeReq_accesses::total 28622 # number of SCUpgradeReq accesses(hits+misses) 2700system.l2c.ReadExReq_accesses::cpu0.data 658810 # number of ReadExReq accesses(hits+misses) 2701system.l2c.ReadExReq_accesses::cpu1.data 275925 # number of ReadExReq accesses(hits+misses) 2702system.l2c.ReadExReq_accesses::total 934735 # number of ReadExReq accesses(hits+misses) 2703system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 7796 # number of ReadSharedReq accesses(hits+misses) 2704system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6106 # number of ReadSharedReq accesses(hits+misses) 2705system.l2c.ReadSharedReq_accesses::cpu0.inst 753415 # number of ReadSharedReq accesses(hits+misses) 2706system.l2c.ReadSharedReq_accesses::cpu0.data 672020 # number of ReadSharedReq accesses(hits+misses) 2707system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 485522 # number of ReadSharedReq accesses(hits+misses) 2708system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 6431 # number of ReadSharedReq accesses(hits+misses) 2709system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 4392 # number of ReadSharedReq accesses(hits+misses) 2710system.l2c.ReadSharedReq_accesses::cpu1.inst 734786 # number of ReadSharedReq accesses(hits+misses) 2711system.l2c.ReadSharedReq_accesses::cpu1.data 592028 # number of ReadSharedReq accesses(hits+misses) 2712system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 423045 # number of ReadSharedReq accesses(hits+misses) 2713system.l2c.ReadSharedReq_accesses::total 3685541 # number of ReadSharedReq accesses(hits+misses) 2714system.l2c.demand_accesses::cpu0.dtb.walker 7796 # number of demand (read+write) accesses 2715system.l2c.demand_accesses::cpu0.itb.walker 6106 # number of demand (read+write) accesses 2716system.l2c.demand_accesses::cpu0.inst 753415 # number of demand (read+write) accesses 2717system.l2c.demand_accesses::cpu0.data 1330830 # number of demand (read+write) accesses 2718system.l2c.demand_accesses::cpu0.l2cache.prefetcher 485522 # number of demand (read+write) accesses 2719system.l2c.demand_accesses::cpu1.dtb.walker 6431 # number of demand (read+write) accesses 2720system.l2c.demand_accesses::cpu1.itb.walker 4392 # number of demand (read+write) accesses 2721system.l2c.demand_accesses::cpu1.inst 734786 # number of demand (read+write) accesses 2722system.l2c.demand_accesses::cpu1.data 867953 # number of demand (read+write) accesses 2723system.l2c.demand_accesses::cpu1.l2cache.prefetcher 423045 # number of demand (read+write) accesses 2724system.l2c.demand_accesses::total 4620276 # number of demand (read+write) accesses 2725system.l2c.overall_accesses::cpu0.dtb.walker 7796 # number of overall (read+write) accesses 2726system.l2c.overall_accesses::cpu0.itb.walker 6106 # number of overall (read+write) accesses 2727system.l2c.overall_accesses::cpu0.inst 753415 # number of overall (read+write) accesses 2728system.l2c.overall_accesses::cpu0.data 1330830 # number of overall (read+write) accesses 2729system.l2c.overall_accesses::cpu0.l2cache.prefetcher 485522 # number of overall (read+write) accesses 2730system.l2c.overall_accesses::cpu1.dtb.walker 6431 # number of overall (read+write) accesses 2731system.l2c.overall_accesses::cpu1.itb.walker 4392 # number of overall (read+write) accesses 2732system.l2c.overall_accesses::cpu1.inst 734786 # number of overall (read+write) accesses 2733system.l2c.overall_accesses::cpu1.data 867953 # number of overall (read+write) accesses 2734system.l2c.overall_accesses::cpu1.l2cache.prefetcher 423045 # number of overall (read+write) accesses 2735system.l2c.overall_accesses::total 4620276 # number of overall (read+write) accesses 2736system.l2c.UpgradeReq_miss_rate::cpu0.data 0.575728 # miss rate for UpgradeReq accesses 2737system.l2c.UpgradeReq_miss_rate::cpu1.data 0.635360 # miss rate for UpgradeReq accesses 2738system.l2c.UpgradeReq_miss_rate::total 0.604879 # miss rate for UpgradeReq accesses 2739system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.579523 # miss rate for SCUpgradeReq accesses 2740system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.606461 # miss rate for SCUpgradeReq accesses 2741system.l2c.SCUpgradeReq_miss_rate::total 0.592342 # miss rate for SCUpgradeReq accesses 2742system.l2c.ReadExReq_miss_rate::cpu0.data 0.726876 # miss rate for ReadExReq accesses 2743system.l2c.ReadExReq_miss_rate::cpu1.data 0.427986 # miss rate for ReadExReq accesses 2744system.l2c.ReadExReq_miss_rate::total 0.638646 # miss rate for ReadExReq accesses 2745system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.150975 # miss rate for ReadSharedReq accesses 2746system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.182116 # miss rate for ReadSharedReq accesses 2747system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.086290 # miss rate for ReadSharedReq accesses 2748system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.180227 # miss rate for ReadSharedReq accesses 2749system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.345377 # miss rate for ReadSharedReq accesses 2750system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.124553 # miss rate for ReadSharedReq accesses 2751system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.170082 # miss rate for ReadSharedReq accesses 2752system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.061308 # miss rate for ReadSharedReq accesses 2753system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.127638 # miss rate for ReadSharedReq accesses 2754system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.286558 # miss rate for ReadSharedReq accesses 2755system.l2c.ReadSharedReq_miss_rate::total 0.162661 # miss rate for ReadSharedReq accesses 2756system.l2c.demand_miss_rate::cpu0.dtb.walker 0.150975 # miss rate for demand accesses 2757system.l2c.demand_miss_rate::cpu0.itb.walker 0.182116 # miss rate for demand accesses 2758system.l2c.demand_miss_rate::cpu0.inst 0.086290 # miss rate for demand accesses 2759system.l2c.demand_miss_rate::cpu0.data 0.450838 # miss rate for demand accesses 2760system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.345377 # miss rate for demand accesses 2761system.l2c.demand_miss_rate::cpu1.dtb.walker 0.124553 # miss rate for demand accesses 2762system.l2c.demand_miss_rate::cpu1.itb.walker 0.170082 # miss rate for demand accesses 2763system.l2c.demand_miss_rate::cpu1.inst 0.061308 # miss rate for demand accesses 2764system.l2c.demand_miss_rate::cpu1.data 0.223119 # miss rate for demand accesses 2765system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.286558 # miss rate for demand accesses 2766system.l2c.demand_miss_rate::total 0.258958 # miss rate for demand accesses 2767system.l2c.overall_miss_rate::cpu0.dtb.walker 0.150975 # miss rate for overall accesses 2768system.l2c.overall_miss_rate::cpu0.itb.walker 0.182116 # miss rate for overall accesses 2769system.l2c.overall_miss_rate::cpu0.inst 0.086290 # miss rate for overall accesses 2770system.l2c.overall_miss_rate::cpu0.data 0.450838 # miss rate for overall accesses 2771system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.345377 # miss rate for overall accesses 2772system.l2c.overall_miss_rate::cpu1.dtb.walker 0.124553 # miss rate for overall accesses 2773system.l2c.overall_miss_rate::cpu1.itb.walker 0.170082 # miss rate for overall accesses 2774system.l2c.overall_miss_rate::cpu1.inst 0.061308 # miss rate for overall accesses 2775system.l2c.overall_miss_rate::cpu1.data 0.223119 # miss rate for overall accesses 2776system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.286558 # miss rate for overall accesses 2777system.l2c.overall_miss_rate::total 0.258958 # miss rate for overall accesses 2778system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6752.649383 # average UpgradeReq miss latency 2779system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5774.582540 # average UpgradeReq miss latency 2780system.l2c.UpgradeReq_avg_miss_latency::total 6250.440217 # average UpgradeReq miss latency 2781system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5833.275822 # average SCUpgradeReq miss latency 2782system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5924.757869 # average SCUpgradeReq miss latency 2783system.l2c.SCUpgradeReq_avg_miss_latency::total 5877.845936 # average SCUpgradeReq miss latency 2784system.l2c.ReadExReq_avg_miss_latency::cpu0.data 93943.195795 # average ReadExReq miss latency 2785system.l2c.ReadExReq_avg_miss_latency::cpu1.data 84223.474071 # average ReadExReq miss latency 2786system.l2c.ReadExReq_avg_miss_latency::total 92020.434196 # average ReadExReq miss latency 2787system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 87347.918437 # average ReadSharedReq miss latency 2788system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 88365.557554 # average ReadSharedReq miss latency 2789system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 82274.049406 # average ReadSharedReq miss latency 2790system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88471.440602 # average ReadSharedReq miss latency 2791system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 116241.655903 # average ReadSharedReq miss latency 2792system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 89088.014981 # average ReadSharedReq miss latency 2793system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 89323.293173 # average ReadSharedReq miss latency 2794system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82034.085864 # average ReadSharedReq miss latency 2795system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 86710.150202 # average ReadSharedReq miss latency 2796system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 113867.084189 # average ReadSharedReq miss latency 2797system.l2c.ReadSharedReq_avg_miss_latency::total 99996.300724 # average ReadSharedReq miss latency 2798system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 87347.918437 # average overall miss latency 2799system.l2c.demand_avg_miss_latency::cpu0.itb.walker 88365.557554 # average overall miss latency 2800system.l2c.demand_avg_miss_latency::cpu0.inst 82274.049406 # average overall miss latency 2801system.l2c.demand_avg_miss_latency::cpu0.data 92838.647042 # average overall miss latency 2802system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 116241.655903 # average overall miss latency 2803system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89088.014981 # average overall miss latency 2804system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89323.293173 # average overall miss latency 2805system.l2c.demand_avg_miss_latency::cpu1.inst 82034.085864 # average overall miss latency 2806system.l2c.demand_avg_miss_latency::cpu1.data 85193.775593 # average overall miss latency 2807system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 113867.084189 # average overall miss latency 2808system.l2c.demand_avg_miss_latency::total 96016.793577 # average overall miss latency 2809system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 87347.918437 # average overall miss latency 2810system.l2c.overall_avg_miss_latency::cpu0.itb.walker 88365.557554 # average overall miss latency 2811system.l2c.overall_avg_miss_latency::cpu0.inst 82274.049406 # average overall miss latency 2812system.l2c.overall_avg_miss_latency::cpu0.data 92838.647042 # average overall miss latency 2813system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 116241.655903 # average overall miss latency 2814system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89088.014981 # average overall miss latency 2815system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89323.293173 # average overall miss latency 2816system.l2c.overall_avg_miss_latency::cpu1.inst 82034.085864 # average overall miss latency 2817system.l2c.overall_avg_miss_latency::cpu1.data 85193.775593 # average overall miss latency 2818system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 113867.084189 # average overall miss latency 2819system.l2c.overall_avg_miss_latency::total 96016.793577 # average overall miss latency 2820system.l2c.blocked_cycles::no_mshrs 272 # number of cycles access was blocked 2821system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2822system.l2c.blocked::no_mshrs 3 # number of cycles access was blocked 2823system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2824system.l2c.avg_blocked_cycles::no_mshrs 90.666667 # average number of cycles each access was blocked 2825system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2826system.l2c.fast_writes 0 # number of fast writes performed 2827system.l2c.cache_copies 0 # number of cache copies performed 2828system.l2c.writebacks::writebacks 874415 # number of writebacks 2829system.l2c.writebacks::total 874415 # number of writebacks 2830system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 124 # number of ReadSharedReq MSHR hits 2831system.l2c.ReadSharedReq_mshr_hits::cpu0.data 6 # number of ReadSharedReq MSHR hits 2832system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 136 # number of ReadSharedReq MSHR hits 2833system.l2c.ReadSharedReq_mshr_hits::cpu1.data 15 # number of ReadSharedReq MSHR hits 2834system.l2c.ReadSharedReq_mshr_hits::total 281 # number of ReadSharedReq MSHR hits 2835system.l2c.demand_mshr_hits::cpu0.inst 124 # number of demand (read+write) MSHR hits 2836system.l2c.demand_mshr_hits::cpu0.data 6 # number of demand (read+write) MSHR hits 2837system.l2c.demand_mshr_hits::cpu1.inst 136 # number of demand (read+write) MSHR hits 2838system.l2c.demand_mshr_hits::cpu1.data 15 # number of demand (read+write) MSHR hits 2839system.l2c.demand_mshr_hits::total 281 # number of demand (read+write) MSHR hits 2840system.l2c.overall_mshr_hits::cpu0.inst 124 # number of overall MSHR hits 2841system.l2c.overall_mshr_hits::cpu0.data 6 # number of overall MSHR hits 2842system.l2c.overall_mshr_hits::cpu1.inst 136 # number of overall MSHR hits 2843system.l2c.overall_mshr_hits::cpu1.data 15 # number of overall MSHR hits 2844system.l2c.overall_mshr_hits::total 281 # number of overall MSHR hits 2845system.l2c.CleanEvict_mshr_misses::writebacks 39767 # number of CleanEvict MSHR misses 2846system.l2c.CleanEvict_mshr_misses::total 39767 # number of CleanEvict MSHR misses 2847system.l2c.UpgradeReq_mshr_misses::cpu0.data 42274 # number of UpgradeReq MSHR misses 2848system.l2c.UpgradeReq_mshr_misses::cpu1.data 44615 # number of UpgradeReq MSHR misses 2849system.l2c.UpgradeReq_mshr_misses::total 86889 # number of UpgradeReq MSHR misses 2850system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 8694 # number of SCUpgradeReq MSHR misses 2851system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 8260 # number of SCUpgradeReq MSHR misses 2852system.l2c.SCUpgradeReq_mshr_misses::total 16954 # number of SCUpgradeReq MSHR misses 2853system.l2c.ReadExReq_mshr_misses::cpu0.data 478873 # number of ReadExReq MSHR misses 2854system.l2c.ReadExReq_mshr_misses::cpu1.data 118092 # number of ReadExReq MSHR misses 2855system.l2c.ReadExReq_mshr_misses::total 596965 # number of ReadExReq MSHR misses 2856system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1177 # number of ReadSharedReq MSHR misses 2857system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1112 # number of ReadSharedReq MSHR misses 2858system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 64888 # number of ReadSharedReq MSHR misses 2859system.l2c.ReadSharedReq_mshr_misses::cpu0.data 121110 # number of ReadSharedReq MSHR misses 2860system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 167688 # number of ReadSharedReq MSHR misses 2861system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 801 # number of ReadSharedReq MSHR misses 2862system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 747 # number of ReadSharedReq MSHR misses 2863system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 44912 # number of ReadSharedReq MSHR misses 2864system.l2c.ReadSharedReq_mshr_misses::cpu1.data 75550 # number of ReadSharedReq MSHR misses 2865system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 121227 # number of ReadSharedReq MSHR misses 2866system.l2c.ReadSharedReq_mshr_misses::total 599212 # number of ReadSharedReq MSHR misses 2867system.l2c.demand_mshr_misses::cpu0.dtb.walker 1177 # number of demand (read+write) MSHR misses 2868system.l2c.demand_mshr_misses::cpu0.itb.walker 1112 # number of demand (read+write) MSHR misses 2869system.l2c.demand_mshr_misses::cpu0.inst 64888 # number of demand (read+write) MSHR misses 2870system.l2c.demand_mshr_misses::cpu0.data 599983 # number of demand (read+write) MSHR misses 2871system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 167688 # number of demand (read+write) MSHR misses 2872system.l2c.demand_mshr_misses::cpu1.dtb.walker 801 # number of demand (read+write) MSHR misses 2873system.l2c.demand_mshr_misses::cpu1.itb.walker 747 # number of demand (read+write) MSHR misses 2874system.l2c.demand_mshr_misses::cpu1.inst 44912 # number of demand (read+write) MSHR misses 2875system.l2c.demand_mshr_misses::cpu1.data 193642 # number of demand (read+write) MSHR misses 2876system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 121227 # number of demand (read+write) MSHR misses 2877system.l2c.demand_mshr_misses::total 1196177 # number of demand (read+write) MSHR misses 2878system.l2c.overall_mshr_misses::cpu0.dtb.walker 1177 # number of overall MSHR misses 2879system.l2c.overall_mshr_misses::cpu0.itb.walker 1112 # number of overall MSHR misses 2880system.l2c.overall_mshr_misses::cpu0.inst 64888 # number of overall MSHR misses 2881system.l2c.overall_mshr_misses::cpu0.data 599983 # number of overall MSHR misses 2882system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 167688 # number of overall MSHR misses 2883system.l2c.overall_mshr_misses::cpu1.dtb.walker 801 # number of overall MSHR misses 2884system.l2c.overall_mshr_misses::cpu1.itb.walker 747 # number of overall MSHR misses 2885system.l2c.overall_mshr_misses::cpu1.inst 44912 # number of overall MSHR misses 2886system.l2c.overall_mshr_misses::cpu1.data 193642 # number of overall MSHR misses 2887system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 121227 # number of overall MSHR misses 2888system.l2c.overall_mshr_misses::total 1196177 # number of overall MSHR misses 2889system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 52292 # number of ReadReq MSHR uncacheable 2890system.l2c.ReadReq_mshr_uncacheable::cpu0.data 30167 # number of ReadReq MSHR uncacheable 2891system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable 2892system.l2c.ReadReq_mshr_uncacheable::cpu1.data 8247 # number of ReadReq MSHR uncacheable 2893system.l2c.ReadReq_mshr_uncacheable::total 90799 # number of ReadReq MSHR uncacheable 2894system.l2c.WriteReq_mshr_uncacheable::cpu0.data 29885 # number of WriteReq MSHR uncacheable 2895system.l2c.WriteReq_mshr_uncacheable::cpu1.data 8420 # number of WriteReq MSHR uncacheable 2896system.l2c.WriteReq_mshr_uncacheable::total 38305 # number of WriteReq MSHR uncacheable 2897system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 52292 # number of overall MSHR uncacheable misses 2898system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60052 # number of overall MSHR uncacheable misses 2899system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses 2900system.l2c.overall_mshr_uncacheable_misses::cpu1.data 16667 # number of overall MSHR uncacheable misses 2901system.l2c.overall_mshr_uncacheable_misses::total 129104 # number of overall MSHR uncacheable misses 2902system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 877451504 # number of UpgradeReq MSHR miss cycles 2903system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 925962001 # number of UpgradeReq MSHR miss cycles 2904system.l2c.UpgradeReq_mshr_miss_latency::total 1803413505 # number of UpgradeReq MSHR miss cycles 2905system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 180795000 # number of SCUpgradeReq MSHR miss cycles 2906system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 171889500 # number of SCUpgradeReq MSHR miss cycles 2907system.l2c.SCUpgradeReq_mshr_miss_latency::total 352684500 # number of SCUpgradeReq MSHR miss cycles 2908system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 40198130000 # number of ReadExReq MSHR miss cycles 2909system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 8765198500 # number of ReadExReq MSHR miss cycles 2910system.l2c.ReadExReq_mshr_miss_latency::total 48963328500 # number of ReadExReq MSHR miss cycles 2911system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 91038500 # number of ReadSharedReq MSHR miss cycles 2912system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 87142500 # number of ReadSharedReq MSHR miss cycles 2913system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 4691111500 # number of ReadSharedReq MSHR miss cycles 2914system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 9503861000 # number of ReadSharedReq MSHR miss cycles 2915system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 17815450795 # number of ReadSharedReq MSHR miss cycles 2916system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 63349500 # number of ReadSharedReq MSHR miss cycles 2917system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 59254500 # number of ReadSharedReq MSHR miss cycles 2918system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 3237260500 # number of ReadSharedReq MSHR miss cycles 2919system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 5795509500 # number of ReadSharedReq MSHR miss cycles 2920system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 12591495015 # number of ReadSharedReq MSHR miss cycles 2921system.l2c.ReadSharedReq_mshr_miss_latency::total 53935473310 # number of ReadSharedReq MSHR miss cycles 2922system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 91038500 # number of demand (read+write) MSHR miss cycles 2923system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 87142500 # number of demand (read+write) MSHR miss cycles 2924system.l2c.demand_mshr_miss_latency::cpu0.inst 4691111500 # number of demand (read+write) MSHR miss cycles 2925system.l2c.demand_mshr_miss_latency::cpu0.data 49701991000 # number of demand (read+write) MSHR miss cycles 2926system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 17815450795 # number of demand (read+write) MSHR miss cycles 2927system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 63349500 # number of demand (read+write) MSHR miss cycles 2928system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 59254500 # number of demand (read+write) MSHR miss cycles 2929system.l2c.demand_mshr_miss_latency::cpu1.inst 3237260500 # number of demand (read+write) MSHR miss cycles 2930system.l2c.demand_mshr_miss_latency::cpu1.data 14560708000 # number of demand (read+write) MSHR miss cycles 2931system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 12591495015 # number of demand (read+write) MSHR miss cycles 2932system.l2c.demand_mshr_miss_latency::total 102898801810 # number of demand (read+write) MSHR miss cycles 2933system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 91038500 # number of overall MSHR miss cycles 2934system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 87142500 # number of overall MSHR miss cycles 2935system.l2c.overall_mshr_miss_latency::cpu0.inst 4691111500 # number of overall MSHR miss cycles 2936system.l2c.overall_mshr_miss_latency::cpu0.data 49701991000 # number of overall MSHR miss cycles 2937system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 17815450795 # number of overall MSHR miss cycles 2938system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 63349500 # number of overall MSHR miss cycles 2939system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 59254500 # number of overall MSHR miss cycles 2940system.l2c.overall_mshr_miss_latency::cpu1.inst 3237260500 # number of overall MSHR miss cycles 2941system.l2c.overall_mshr_miss_latency::cpu1.data 14560708000 # number of overall MSHR miss cycles 2942system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 12591495015 # number of overall MSHR miss cycles 2943system.l2c.overall_mshr_miss_latency::total 102898801810 # number of overall MSHR miss cycles 2944system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3261312500 # number of ReadReq MSHR uncacheable cycles 2945system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4641716000 # number of ReadReq MSHR uncacheable cycles 2946system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6042500 # number of ReadReq MSHR uncacheable cycles 2947system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 881581500 # number of ReadReq MSHR uncacheable cycles 2948system.l2c.ReadReq_mshr_uncacheable_latency::total 8790652500 # number of ReadReq MSHR uncacheable cycles 2949system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4402307500 # number of WriteReq MSHR uncacheable cycles 2950system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1020289500 # number of WriteReq MSHR uncacheable cycles 2951system.l2c.WriteReq_mshr_uncacheable_latency::total 5422597000 # number of WriteReq MSHR uncacheable cycles 2952system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3261312500 # number of overall MSHR uncacheable cycles 2953system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9044023500 # number of overall MSHR uncacheable cycles 2954system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6042500 # number of overall MSHR uncacheable cycles 2955system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1901871000 # number of overall MSHR uncacheable cycles 2956system.l2c.overall_mshr_uncacheable_latency::total 14213249500 # number of overall MSHR uncacheable cycles 2957system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2958system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2959system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.575728 # mshr miss rate for UpgradeReq accesses 2960system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.635360 # mshr miss rate for UpgradeReq accesses 2961system.l2c.UpgradeReq_mshr_miss_rate::total 0.604879 # mshr miss rate for UpgradeReq accesses 2962system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.579523 # mshr miss rate for SCUpgradeReq accesses 2963system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.606461 # mshr miss rate for SCUpgradeReq accesses 2964system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.592342 # mshr miss rate for SCUpgradeReq accesses 2965system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.726876 # mshr miss rate for ReadExReq accesses 2966system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.427986 # mshr miss rate for ReadExReq accesses 2967system.l2c.ReadExReq_mshr_miss_rate::total 0.638646 # mshr miss rate for ReadExReq accesses 2968system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.150975 # mshr miss rate for ReadSharedReq accesses 2969system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.182116 # mshr miss rate for ReadSharedReq accesses 2970system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.086125 # mshr miss rate for ReadSharedReq accesses 2971system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.180218 # mshr miss rate for ReadSharedReq accesses 2972system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.345377 # mshr miss rate for ReadSharedReq accesses 2973system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.124553 # mshr miss rate for ReadSharedReq accesses 2974system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.170082 # mshr miss rate for ReadSharedReq accesses 2975system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.061123 # mshr miss rate for ReadSharedReq accesses 2976system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.127612 # mshr miss rate for ReadSharedReq accesses 2977system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.286558 # mshr miss rate for ReadSharedReq accesses 2978system.l2c.ReadSharedReq_mshr_miss_rate::total 0.162585 # mshr miss rate for ReadSharedReq accesses 2979system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.150975 # mshr miss rate for demand accesses 2980system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.182116 # mshr miss rate for demand accesses 2981system.l2c.demand_mshr_miss_rate::cpu0.inst 0.086125 # mshr miss rate for demand accesses 2982system.l2c.demand_mshr_miss_rate::cpu0.data 0.450834 # mshr miss rate for demand accesses 2983system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.345377 # mshr miss rate for demand accesses 2984system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.124553 # mshr miss rate for demand accesses 2985system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.170082 # mshr miss rate for demand accesses 2986system.l2c.demand_mshr_miss_rate::cpu1.inst 0.061123 # mshr miss rate for demand accesses 2987system.l2c.demand_mshr_miss_rate::cpu1.data 0.223102 # mshr miss rate for demand accesses 2988system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.286558 # mshr miss rate for demand accesses 2989system.l2c.demand_mshr_miss_rate::total 0.258897 # mshr miss rate for demand accesses 2990system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.150975 # mshr miss rate for overall accesses 2991system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.182116 # mshr miss rate for overall accesses 2992system.l2c.overall_mshr_miss_rate::cpu0.inst 0.086125 # mshr miss rate for overall accesses 2993system.l2c.overall_mshr_miss_rate::cpu0.data 0.450834 # mshr miss rate for overall accesses 2994system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.345377 # mshr miss rate for overall accesses 2995system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.124553 # mshr miss rate for overall accesses 2996system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.170082 # mshr miss rate for overall accesses 2997system.l2c.overall_mshr_miss_rate::cpu1.inst 0.061123 # mshr miss rate for overall accesses 2998system.l2c.overall_mshr_miss_rate::cpu1.data 0.223102 # mshr miss rate for overall accesses 2999system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.286558 # mshr miss rate for overall accesses 3000system.l2c.overall_mshr_miss_rate::total 0.258897 # mshr miss rate for overall accesses 3001system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20756.292378 # average UpgradeReq mshr miss latency 3002system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20754.499630 # average UpgradeReq mshr miss latency 3003system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20755.371854 # average UpgradeReq mshr miss latency 3004system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20795.376121 # average SCUpgradeReq mshr miss latency 3005system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20809.866828 # average SCUpgradeReq mshr miss latency 3006system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20802.436003 # average SCUpgradeReq mshr miss latency 3007system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 83943.195795 # average ReadExReq mshr miss latency 3008system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74223.474071 # average ReadExReq mshr miss latency 3009system.l2c.ReadExReq_avg_mshr_miss_latency::total 82020.434196 # average ReadExReq mshr miss latency 3010system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 77347.918437 # average ReadSharedReq mshr miss latency 3011system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 78365.557554 # average ReadSharedReq mshr miss latency 3012system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 72295.516891 # average ReadSharedReq mshr miss latency 3013system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78472.966724 # average ReadSharedReq mshr miss latency 3014system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106241.655903 # average ReadSharedReq mshr miss latency 3015system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79088.014981 # average ReadSharedReq mshr miss latency 3016system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 79323.293173 # average ReadSharedReq mshr miss latency 3017system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72080.078821 # average ReadSharedReq mshr miss latency 3018system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 76710.913302 # average ReadSharedReq mshr miss latency 3019system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103867.084189 # average ReadSharedReq mshr miss latency 3020system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 90010.669529 # average ReadSharedReq mshr miss latency 3021system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77347.918437 # average overall mshr miss latency 3022system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78365.557554 # average overall mshr miss latency 3023system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72295.516891 # average overall mshr miss latency 3024system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82838.998772 # average overall mshr miss latency 3025system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106241.655903 # average overall mshr miss latency 3026system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79088.014981 # average overall mshr miss latency 3027system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79323.293173 # average overall mshr miss latency 3028system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72080.078821 # average overall mshr miss latency 3029system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75193.955857 # average overall mshr miss latency 3030system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103867.084189 # average overall mshr miss latency 3031system.l2c.demand_avg_mshr_miss_latency::total 86023.056630 # average overall mshr miss latency 3032system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77347.918437 # average overall mshr miss latency 3033system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78365.557554 # average overall mshr miss latency 3034system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72295.516891 # average overall mshr miss latency 3035system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82838.998772 # average overall mshr miss latency 3036system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106241.655903 # average overall mshr miss latency 3037system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79088.014981 # average overall mshr miss latency 3038system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79323.293173 # average overall mshr miss latency 3039system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72080.078821 # average overall mshr miss latency 3040system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75193.955857 # average overall mshr miss latency 3041system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103867.084189 # average overall mshr miss latency 3042system.l2c.overall_avg_mshr_miss_latency::total 86023.056630 # average overall mshr miss latency 3043system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62367.331523 # average ReadReq mshr uncacheable latency 3044system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 153867.338482 # average ReadReq mshr uncacheable latency 3045system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64973.118280 # average ReadReq mshr uncacheable latency 3046system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 106897.235358 # average ReadReq mshr uncacheable latency 3047system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 96814.419762 # average ReadReq mshr uncacheable latency 3048system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147308.265016 # average WriteReq mshr uncacheable latency 3049system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 121174.524941 # average WriteReq mshr uncacheable latency 3050system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141563.686203 # average WriteReq mshr uncacheable latency 3051system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62367.331523 # average overall mshr uncacheable latency 3052system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 150603.202225 # average overall mshr uncacheable latency 3053system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64973.118280 # average overall mshr uncacheable latency 3054system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 114109.977800 # average overall mshr uncacheable latency 3055system.l2c.overall_avg_mshr_uncacheable_latency::total 110091.472766 # average overall mshr uncacheable latency 3056system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 3057system.membus.trans_dist::ReadReq 90799 # Transaction distribution 3058system.membus.trans_dist::ReadResp 698902 # Transaction distribution 3059system.membus.trans_dist::WriteReq 38305 # Transaction distribution 3060system.membus.trans_dist::WriteResp 38305 # Transaction distribution 3061system.membus.trans_dist::Writeback 981364 # Transaction distribution 3062system.membus.trans_dist::CleanEvict 209019 # Transaction distribution 3063system.membus.trans_dist::UpgradeReq 434160 # Transaction distribution 3064system.membus.trans_dist::SCUpgradeReq 274076 # Transaction distribution 3065system.membus.trans_dist::UpgradeResp 111283 # Transaction distribution 3066system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution 3067system.membus.trans_dist::ReadExReq 609626 # Transaction distribution 3068system.membus.trans_dist::ReadExResp 589528 # Transaction distribution 3069system.membus.trans_dist::ReadSharedReq 608103 # Transaction distribution 3070system.membus.trans_dist::InvalidateReq 106984 # Transaction distribution 3071system.membus.trans_dist::InvalidateResp 106984 # Transaction distribution 3072system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122944 # Packet count per connected master and slave (bytes) 3073system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) 3074system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25274 # Packet count per connected master and slave (bytes) 3075system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4403229 # Packet count per connected master and slave (bytes) 3076system.membus.pkt_count_system.l2c.mem_side::total 4551499 # Packet count per connected master and slave (bytes) 3077system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 343039 # Packet count per connected master and slave (bytes) 3078system.membus.pkt_count_system.iocache.mem_side::total 343039 # Packet count per connected master and slave (bytes) 3079system.membus.pkt_count::total 4894538 # Packet count per connected master and slave (bytes) 3080system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155959 # Cumulative packet size per connected master and slave (bytes) 3081system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) 3082system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50548 # Cumulative packet size per connected master and slave (bytes) 3083system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 135367808 # Cumulative packet size per connected master and slave (bytes) 3084system.membus.pkt_size_system.l2c.mem_side::total 135575639 # Cumulative packet size per connected master and slave (bytes) 3085system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7275904 # Cumulative packet size per connected master and slave (bytes) 3086system.membus.pkt_size_system.iocache.mem_side::total 7275904 # Cumulative packet size per connected master and slave (bytes) 3087system.membus.pkt_size::total 142851543 # Cumulative packet size per connected master and slave (bytes) 3088system.membus.snoops 619953 # Total snoops (count) 3089system.membus.snoop_fanout::samples 3354848 # Request fanout histogram 3090system.membus.snoop_fanout::mean 1 # Request fanout histogram 3091system.membus.snoop_fanout::stdev 0 # Request fanout histogram 3092system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3093system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3094system.membus.snoop_fanout::1 3354848 100.00% 100.00% # Request fanout histogram 3095system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3096system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3097system.membus.snoop_fanout::min_value 1 # Request fanout histogram 3098system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3099system.membus.snoop_fanout::total 3354848 # Request fanout histogram 3100system.membus.reqLayer0.occupancy 109588500 # Layer occupancy (ticks) 3101system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3102system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks) 3103system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3104system.membus.reqLayer2.occupancy 21072500 # Layer occupancy (ticks) 3105system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3106system.membus.reqLayer5.occupancy 6982752656 # Layer occupancy (ticks) 3107system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3108system.membus.respLayer2.occupancy 6858580357 # Layer occupancy (ticks) 3109system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3110system.membus.respLayer3.occupancy 229669194 # Layer occupancy (ticks) 3111system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3112system.realview.ethernet.txBytes 966 # Bytes Transmitted 3113system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3114system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3115system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3116system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3117system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3118system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3119system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3120system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3121system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 3122system.realview.ethernet.totPackets 3 # Total Packets 3123system.realview.ethernet.totBytes 966 # Total Bytes 3124system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 3125system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 3126system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 3127system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3128system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 3129system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3130system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3131system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 3132system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3133system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3134system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 3135system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3136system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3137system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 3138system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3139system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3140system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 3141system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3142system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3143system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 3144system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3145system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3146system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3147system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3148system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3149system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3150system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3151system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3152system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3153system.realview.ethernet.droppedPackets 0 # number of packets dropped 3154system.toL2Bus.trans_dist::ReadReq 90801 # Transaction distribution 3155system.toL2Bus.trans_dist::ReadResp 4609563 # Transaction distribution 3156system.toL2Bus.trans_dist::WriteReq 38305 # Transaction distribution 3157system.toL2Bus.trans_dist::WriteResp 38305 # Transaction distribution 3158system.toL2Bus.trans_dist::Writeback 3165042 # Transaction distribution 3159system.toL2Bus.trans_dist::CleanEvict 1502795 # Transaction distribution 3160system.toL2Bus.trans_dist::UpgradeReq 483481 # Transaction distribution 3161system.toL2Bus.trans_dist::SCUpgradeReq 285744 # Transaction distribution 3162system.toL2Bus.trans_dist::UpgradeResp 769225 # Transaction distribution 3163system.toL2Bus.trans_dist::SCUpgradeFailReq 105 # Transaction distribution 3164system.toL2Bus.trans_dist::UpgradeFailResp 105 # Transaction distribution 3165system.toL2Bus.trans_dist::ReadExReq 1092976 # Transaction distribution 3166system.toL2Bus.trans_dist::ReadExResp 1092976 # Transaction distribution 3167system.toL2Bus.trans_dist::ReadSharedReq 4526002 # Transaction distribution 3168system.toL2Bus.trans_dist::InvalidateReq 106984 # Transaction distribution 3169system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8264892 # Packet count per connected master and slave (bytes) 3170system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6572319 # Packet count per connected master and slave (bytes) 3171system.toL2Bus.pkt_count::total 14837211 # Packet count per connected master and slave (bytes) 3172system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 254099969 # Cumulative packet size per connected master and slave (bytes) 3173system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 185036822 # Cumulative packet size per connected master and slave (bytes) 3174system.toL2Bus.pkt_size::total 439136791 # Cumulative packet size per connected master and slave (bytes) 3175system.toL2Bus.snoops 2966852 # Total snoops (count) 3176system.toL2Bus.snoop_fanout::samples 12598332 # Request fanout histogram 3177system.toL2Bus.snoop_fanout::mean 1.109406 # Request fanout histogram 3178system.toL2Bus.snoop_fanout::stdev 0.312147 # Request fanout histogram 3179system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3180system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3181system.toL2Bus.snoop_fanout::1 11220005 89.06% 89.06% # Request fanout histogram 3182system.toL2Bus.snoop_fanout::2 1378327 10.94% 100.00% # Request fanout histogram 3183system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3184system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 3185system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3186system.toL2Bus.snoop_fanout::total 12598332 # Request fanout histogram 3187system.toL2Bus.reqLayer0.occupancy 8167142441 # Layer occupancy (ticks) 3188system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3189system.toL2Bus.snoopLayer0.occupancy 2478499 # Layer occupancy (ticks) 3190system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3191system.toL2Bus.respLayer0.occupancy 4888169243 # Layer occupancy (ticks) 3192system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3193system.toL2Bus.respLayer1.occupancy 4052371405 # Layer occupancy (ticks) 3194system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3195 3196---------- End Simulation Statistics ---------- 3197