stats.txt revision 10827
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.365947 # Number of seconds simulated 4sim_ticks 47365946685500 # Number of ticks simulated 5final_tick 47365946685500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 174192 # Simulator instruction rate (inst/s) 8host_op_rate 204861 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9672451523 # Simulator tick rate (ticks/s) 10host_mem_usage 763596 # Number of bytes of host memory used 11host_seconds 4897.00 # Real time elapsed on the host 12sim_insts 853019792 # Number of instructions simulated 13sim_ops 1003201701 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 65472 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 64384 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 7833792 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 12003144 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 10766848 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 71104 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 69248 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 2839488 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 7678416 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 7994432 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 439552 # Number of bytes read from this memory 27system.physmem.bytes_read::total 49825880 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 7833792 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 2839488 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 10673280 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 62800512 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 34system.physmem.bytes_written::total 62821096 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 1023 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 1006 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 122403 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 187562 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 168232 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 1111 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 1082 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 44367 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 119988 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 124913 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 6868 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 778555 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 981258 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 50system.physmem.num_writes::total 983832 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 1382 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 1359 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 165389 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 253413 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 227312 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 1501 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 1462 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 59948 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 162108 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 168780 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 9280 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 1051935 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 165389 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 59948 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 225337 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 1325858 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::total 1326292 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 1325858 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 1382 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 1359 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 165389 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 253847 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 227312 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 1501 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 1462 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 59948 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 162108 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 168780 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 9280 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 2378227 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 778555 # Number of read requests accepted 84system.physmem.writeReqs 1622091 # Number of write requests accepted 85system.physmem.readBursts 778555 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 1622091 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 49803520 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 24000 # Total number of bytes read from write queue 89system.physmem.bytesWritten 100652928 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 49825880 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 103669672 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 375 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 49366 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 111816 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 42060 # Per bank write bursts 96system.physmem.perBankRdBursts::1 53156 # Per bank write bursts 97system.physmem.perBankRdBursts::2 42442 # Per bank write bursts 98system.physmem.perBankRdBursts::3 47567 # Per bank write bursts 99system.physmem.perBankRdBursts::4 45723 # Per bank write bursts 100system.physmem.perBankRdBursts::5 54413 # Per bank write bursts 101system.physmem.perBankRdBursts::6 50594 # Per bank write bursts 102system.physmem.perBankRdBursts::7 44772 # Per bank write bursts 103system.physmem.perBankRdBursts::8 41306 # Per bank write bursts 104system.physmem.perBankRdBursts::9 93457 # Per bank write bursts 105system.physmem.perBankRdBursts::10 34541 # Per bank write bursts 106system.physmem.perBankRdBursts::11 47870 # Per bank write bursts 107system.physmem.perBankRdBursts::12 47765 # Per bank write bursts 108system.physmem.perBankRdBursts::13 46143 # Per bank write bursts 109system.physmem.perBankRdBursts::14 39677 # Per bank write bursts 110system.physmem.perBankRdBursts::15 46694 # Per bank write bursts 111system.physmem.perBankWrBursts::0 94318 # Per bank write bursts 112system.physmem.perBankWrBursts::1 104450 # Per bank write bursts 113system.physmem.perBankWrBursts::2 99318 # Per bank write bursts 114system.physmem.perBankWrBursts::3 101345 # Per bank write bursts 115system.physmem.perBankWrBursts::4 99792 # Per bank write bursts 116system.physmem.perBankWrBursts::5 104837 # Per bank write bursts 117system.physmem.perBankWrBursts::6 100210 # Per bank write bursts 118system.physmem.perBankWrBursts::7 98464 # Per bank write bursts 119system.physmem.perBankWrBursts::8 93421 # Per bank write bursts 120system.physmem.perBankWrBursts::9 95649 # Per bank write bursts 121system.physmem.perBankWrBursts::10 88541 # Per bank write bursts 122system.physmem.perBankWrBursts::11 99820 # Per bank write bursts 123system.physmem.perBankWrBursts::12 96824 # Per bank write bursts 124system.physmem.perBankWrBursts::13 96750 # Per bank write bursts 125system.physmem.perBankWrBursts::14 94484 # Per bank write bursts 126system.physmem.perBankWrBursts::15 104479 # Per bank write bursts 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 128system.physmem.numWrRetry 276 # Number of times write queue was full causing retry 129system.physmem.totGap 47365944763000 # Total gap between requests 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 0 # Read request sizes (log2) 133system.physmem.readPktSize::3 25 # Read request sizes (log2) 134system.physmem.readPktSize::4 5 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) 136system.physmem.readPktSize::6 778525 # Read request sizes (log2) 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 2 # Write request sizes (log2) 140system.physmem.writePktSize::3 2572 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) 143system.physmem.writePktSize::6 1619517 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 550292 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 82276 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 30517 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 23784 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 20492 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 18686 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 17057 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 15108 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 12648 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 3935 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 960 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 693 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 556 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 402 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 182 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 158 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 141 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 135 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 86 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 64 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 176system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::15 40446 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 59954 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 84735 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 94224 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 98939 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 95817 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 91113 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 85467 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 82456 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 78613 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 78193 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 94725 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 83224 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 77979 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 91163 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 80486 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 75147 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 72304 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 7065 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 6188 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 6251 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 7364 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 8039 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 6897 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 6691 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 7373 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 5850 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 5415 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 5159 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 5392 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 4452 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 3922 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 3792 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 3304 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 2703 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 1783 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 1523 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 1082 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 1091 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 770 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 913 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 777 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 665 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 582 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 501 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 501 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 424 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 383 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 873 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 836953 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 179.765373 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 108.063876 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 253.948875 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 534704 63.89% 63.89% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 162086 19.37% 83.25% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 38261 4.57% 87.82% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 18116 2.16% 89.99% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 12763 1.52% 91.51% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 8799 1.05% 92.57% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 6603 0.79% 93.35% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 6067 0.72% 94.08% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 49554 5.92% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 836953 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 65558 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 11.869901 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 153.975731 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-1023 65556 100.00% 100.00% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::total 65558 # Reads before turning the bus around for writes 261system.physmem.wrPerTurnAround::samples 65558 # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::mean 23.989475 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::gmean 20.876910 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::stdev 23.036255 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::16-31 57911 88.34% 88.34% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::32-47 3625 5.53% 93.86% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::48-63 1537 2.34% 96.21% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::64-79 756 1.15% 97.36% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::80-95 457 0.70% 98.06% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::96-111 339 0.52% 98.58% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::112-127 446 0.68% 99.26% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::128-143 180 0.27% 99.53% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::144-159 59 0.09% 99.62% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::160-175 25 0.04% 99.66% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::176-191 57 0.09% 99.75% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::192-207 41 0.06% 99.81% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::208-223 16 0.02% 99.83% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::224-239 6 0.01% 99.84% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::240-255 2 0.00% 99.85% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::256-271 7 0.01% 99.86% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::272-287 6 0.01% 99.87% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::288-303 4 0.01% 99.87% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::304-319 12 0.02% 99.89% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::320-335 9 0.01% 99.90% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::336-351 13 0.02% 99.92% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::352-367 20 0.03% 99.95% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::368-383 3 0.00% 99.96% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::384-399 1 0.00% 99.96% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::400-415 2 0.00% 99.96% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::416-431 1 0.00% 99.96% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::432-447 2 0.00% 99.97% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::448-463 1 0.00% 99.97% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::480-495 4 0.01% 99.98% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::496-511 4 0.01% 99.98% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::512-527 4 0.01% 99.99% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::528-543 2 0.00% 99.99% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::544-559 2 0.00% 99.99% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::576-591 1 0.00% 100.00% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::672-687 1 0.00% 100.00% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::688-703 1 0.00% 100.00% # Writes before turning the bus around for reads 301system.physmem.wrPerTurnAround::848-863 1 0.00% 100.00% # Writes before turning the bus around for reads 302system.physmem.wrPerTurnAround::total 65558 # Writes before turning the bus around for reads 303system.physmem.totQLat 24526926504 # Total ticks spent queuing 304system.physmem.totMemAccLat 39117801504 # Total ticks spent from burst creation until serviced by the DRAM 305system.physmem.totBusLat 3890900000 # Total ticks spent in databus transfers 306system.physmem.avgQLat 31518.32 # Average queueing delay per DRAM burst 307system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 308system.physmem.avgMemAccLat 50268.32 # Average memory access latency per DRAM burst 309system.physmem.avgRdBW 1.05 # Average DRAM read bandwidth in MiByte/s 310system.physmem.avgWrBW 2.13 # Average achieved write bandwidth in MiByte/s 311system.physmem.avgRdBWSys 1.05 # Average system read bandwidth in MiByte/s 312system.physmem.avgWrBWSys 2.19 # Average system write bandwidth in MiByte/s 313system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 314system.physmem.busUtil 0.02 # Data bus utilization in percentage 315system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 316system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 317system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing 318system.physmem.avgWrQLen 26.72 # Average write queue length when enqueuing 319system.physmem.readRowHits 582169 # Number of row buffer hits during reads 320system.physmem.writeRowHits 931750 # Number of row buffer hits during writes 321system.physmem.readRowHitRate 74.81 # Row buffer hit rate for reads 322system.physmem.writeRowHitRate 59.24 # Row buffer hit rate for writes 323system.physmem.avgGap 19730499.53 # Average gap between requests 324system.physmem.pageHitRate 64.40 # Row buffer hit rate, read and write combined 325system.physmem_0.actEnergy 3287730600 # Energy for activate commands per rank (pJ) 326system.physmem_0.preEnergy 1793900625 # Energy for precharge commands per rank (pJ) 327system.physmem_0.readEnergy 2969101200 # Energy for read commands per rank (pJ) 328system.physmem_0.writeEnergy 5201632080 # Energy for write commands per rank (pJ) 329system.physmem_0.refreshEnergy 3093712876800 # Energy for refresh commands per rank (pJ) 330system.physmem_0.actBackEnergy 1175633111385 # Energy for active background per rank (pJ) 331system.physmem_0.preBackEnergy 27388306372500 # Energy for precharge background per rank (pJ) 332system.physmem_0.totalEnergy 31670904725190 # Total energy per rank (pJ) 333system.physmem_0.averagePower 668.643023 # Core power per rank (mW) 334system.physmem_0.memoryStateTime::IDLE 45562569995604 # Time in different power states 335system.physmem_0.memoryStateTime::REF 1581652800000 # Time in different power states 336system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 337system.physmem_0.memoryStateTime::ACT 221716854896 # Time in different power states 338system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 339system.physmem_1.actEnergy 3039558480 # Energy for activate commands per rank (pJ) 340system.physmem_1.preEnergy 1658489250 # Energy for precharge commands per rank (pJ) 341system.physmem_1.readEnergy 3100125600 # Energy for read commands per rank (pJ) 342system.physmem_1.writeEnergy 4989373200 # Energy for write commands per rank (pJ) 343system.physmem_1.refreshEnergy 3093712876800 # Energy for refresh commands per rank (pJ) 344system.physmem_1.actBackEnergy 1167524389710 # Energy for active background per rank (pJ) 345system.physmem_1.preBackEnergy 27395419294500 # Energy for precharge background per rank (pJ) 346system.physmem_1.totalEnergy 31669444107540 # Total energy per rank (pJ) 347system.physmem_1.averagePower 668.612186 # Core power per rank (mW) 348system.physmem_1.memoryStateTime::IDLE 45574402608448 # Time in different power states 349system.physmem_1.memoryStateTime::REF 1581652800000 # Time in different power states 350system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 351system.physmem_1.memoryStateTime::ACT 209885438552 # Time in different power states 352system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 353system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory 354system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 355system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory 356system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 357system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory 358system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory 359system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory 360system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory 361system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory 362system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 363system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory 364system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 365system.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory 366system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) 367system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 368system.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s) 369system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 370system.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s) 371system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) 372system.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s) 373system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) 374system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) 375system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 376system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s) 377system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 378system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) 379system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 380system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 381system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 382system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. 383system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. 384system.cf0.dma_write_txs 1674 # Number of DMA write transactions. 385system.cpu0.branchPred.lookups 133649210 # Number of BP lookups 386system.cpu0.branchPred.condPredicted 93568356 # Number of conditional branches predicted 387system.cpu0.branchPred.condIncorrect 6412350 # Number of conditional branches incorrect 388system.cpu0.branchPred.BTBLookups 100434532 # Number of BTB lookups 389system.cpu0.branchPred.BTBHits 71867706 # Number of BTB hits 390system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 391system.cpu0.branchPred.BTBHitPct 71.556769 # BTB Hit Percentage 392system.cpu0.branchPred.usedRAS 16148203 # Number of times the RAS was used to get a target. 393system.cpu0.branchPred.RASInCorrect 1115497 # Number of incorrect RAS predictions. 394system.cpu_clk_domain.clock 500 # Clock period in ticks 395system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 396system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 397system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 398system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 399system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 400system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 401system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 402system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 403system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 404system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 405system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 406system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 407system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 408system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 409system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 410system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 411system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 412system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 413system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 414system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 415system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 416system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 417system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 418system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 419system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 420system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 421system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 422system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 423system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 424system.cpu0.dtb.walker.walks 281840 # Table walker walks requested 425system.cpu0.dtb.walker.walksLong 281840 # Table walker walks initiated with long descriptors 426system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8577 # Level at which table walker walks with long descriptors terminate 427system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76588 # Level at which table walker walks with long descriptors terminate 428system.cpu0.dtb.walker.walkWaitTime::samples 281840 # Table walker wait (enqueue to first request) latency 429system.cpu0.dtb.walker.walkWaitTime::0 281840 100.00% 100.00% # Table walker wait (enqueue to first request) latency 430system.cpu0.dtb.walker.walkWaitTime::total 281840 # Table walker wait (enqueue to first request) latency 431system.cpu0.dtb.walker.walkCompletionTime::samples 85165 # Table walker service (enqueue to completion) latency 432system.cpu0.dtb.walker.walkCompletionTime::mean 18850.134868 # Table walker service (enqueue to completion) latency 433system.cpu0.dtb.walker.walkCompletionTime::gmean 17191.967454 # Table walker service (enqueue to completion) latency 434system.cpu0.dtb.walker.walkCompletionTime::stdev 12262.040349 # Table walker service (enqueue to completion) latency 435system.cpu0.dtb.walker.walkCompletionTime::0-32767 80924 95.02% 95.02% # Table walker service (enqueue to completion) latency 436system.cpu0.dtb.walker.walkCompletionTime::32768-65535 3552 4.17% 99.19% # Table walker service (enqueue to completion) latency 437system.cpu0.dtb.walker.walkCompletionTime::65536-98303 385 0.45% 99.64% # Table walker service (enqueue to completion) latency 438system.cpu0.dtb.walker.walkCompletionTime::98304-131071 201 0.24% 99.88% # Table walker service (enqueue to completion) latency 439system.cpu0.dtb.walker.walkCompletionTime::131072-163839 20 0.02% 99.90% # Table walker service (enqueue to completion) latency 440system.cpu0.dtb.walker.walkCompletionTime::163840-196607 10 0.01% 99.91% # Table walker service (enqueue to completion) latency 441system.cpu0.dtb.walker.walkCompletionTime::196608-229375 25 0.03% 99.94% # Table walker service (enqueue to completion) latency 442system.cpu0.dtb.walker.walkCompletionTime::229376-262143 15 0.02% 99.96% # Table walker service (enqueue to completion) latency 443system.cpu0.dtb.walker.walkCompletionTime::262144-294911 9 0.01% 99.97% # Table walker service (enqueue to completion) latency 444system.cpu0.dtb.walker.walkCompletionTime::294912-327679 16 0.02% 99.99% # Table walker service (enqueue to completion) latency 445system.cpu0.dtb.walker.walkCompletionTime::327680-360447 2 0.00% 99.99% # Table walker service (enqueue to completion) latency 446system.cpu0.dtb.walker.walkCompletionTime::360448-393215 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 447system.cpu0.dtb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 448system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 449system.cpu0.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 450system.cpu0.dtb.walker.walkCompletionTime::total 85165 # Table walker service (enqueue to completion) latency 451system.cpu0.dtb.walker.walksPending::samples 788586204 # Table walker pending requests distribution 452system.cpu0.dtb.walker.walksPending::0 788586204 100.00% 100.00% # Table walker pending requests distribution 453system.cpu0.dtb.walker.walksPending::total 788586204 # Table walker pending requests distribution 454system.cpu0.dtb.walker.walkPageSizes::4K 76588 89.93% 89.93% # Table walker page sizes translated 455system.cpu0.dtb.walker.walkPageSizes::2M 8577 10.07% 100.00% # Table walker page sizes translated 456system.cpu0.dtb.walker.walkPageSizes::total 85165 # Table walker page sizes translated 457system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 281840 # Table walker requests started/completed, data/inst 458system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 459system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 281840 # Table walker requests started/completed, data/inst 460system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85165 # Table walker requests started/completed, data/inst 461system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 462system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85165 # Table walker requests started/completed, data/inst 463system.cpu0.dtb.walker.walkRequestOrigin::total 367005 # Table walker requests started/completed, data/inst 464system.cpu0.dtb.inst_hits 0 # ITB inst hits 465system.cpu0.dtb.inst_misses 0 # ITB inst misses 466system.cpu0.dtb.read_hits 86621651 # DTB read hits 467system.cpu0.dtb.read_misses 235326 # DTB read misses 468system.cpu0.dtb.write_hits 77269391 # DTB write hits 469system.cpu0.dtb.write_misses 46514 # DTB write misses 470system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 471system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 472system.cpu0.dtb.flush_tlb_mva_asid 38373 # Number of times TLB was flushed by MVA & ASID 473system.cpu0.dtb.flush_tlb_asid 1014 # Number of times TLB was flushed by ASID 474system.cpu0.dtb.flush_entries 36825 # Number of entries that have been flushed from TLB 475system.cpu0.dtb.align_faults 2231 # Number of TLB faults due to alignment restrictions 476system.cpu0.dtb.prefetch_faults 9213 # Number of TLB faults due to prefetch 477system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 478system.cpu0.dtb.perms_faults 11443 # Number of TLB faults due to permissions restrictions 479system.cpu0.dtb.read_accesses 86856977 # DTB read accesses 480system.cpu0.dtb.write_accesses 77315905 # DTB write accesses 481system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 482system.cpu0.dtb.hits 163891042 # DTB hits 483system.cpu0.dtb.misses 281840 # DTB misses 484system.cpu0.dtb.accesses 164172882 # DTB accesses 485system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 486system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 487system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 488system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 489system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 490system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 491system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 492system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 493system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 494system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 495system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 496system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 497system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 498system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 499system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 500system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 501system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 502system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 503system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 504system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 505system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 506system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 507system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 508system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 509system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 510system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 511system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 512system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 513system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 514system.cpu0.itb.walker.walks 66347 # Table walker walks requested 515system.cpu0.itb.walker.walksLong 66347 # Table walker walks initiated with long descriptors 516system.cpu0.itb.walker.walksLongTerminationLevel::Level2 679 # Level at which table walker walks with long descriptors terminate 517system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58898 # Level at which table walker walks with long descriptors terminate 518system.cpu0.itb.walker.walkWaitTime::samples 66347 # Table walker wait (enqueue to first request) latency 519system.cpu0.itb.walker.walkWaitTime::0 66347 100.00% 100.00% # Table walker wait (enqueue to first request) latency 520system.cpu0.itb.walker.walkWaitTime::total 66347 # Table walker wait (enqueue to first request) latency 521system.cpu0.itb.walker.walkCompletionTime::samples 59577 # Table walker service (enqueue to completion) latency 522system.cpu0.itb.walker.walkCompletionTime::mean 21233.631049 # Table walker service (enqueue to completion) latency 523system.cpu0.itb.walker.walkCompletionTime::gmean 19420.255520 # Table walker service (enqueue to completion) latency 524system.cpu0.itb.walker.walkCompletionTime::stdev 13392.583355 # Table walker service (enqueue to completion) latency 525system.cpu0.itb.walker.walkCompletionTime::0-32767 54894 92.14% 92.14% # Table walker service (enqueue to completion) latency 526system.cpu0.itb.walker.walkCompletionTime::32768-65535 3878 6.51% 98.65% # Table walker service (enqueue to completion) latency 527system.cpu0.itb.walker.walkCompletionTime::65536-98303 278 0.47% 99.12% # Table walker service (enqueue to completion) latency 528system.cpu0.itb.walker.walkCompletionTime::98304-131071 464 0.78% 99.89% # Table walker service (enqueue to completion) latency 529system.cpu0.itb.walker.walkCompletionTime::131072-163839 13 0.02% 99.92% # Table walker service (enqueue to completion) latency 530system.cpu0.itb.walker.walkCompletionTime::163840-196607 10 0.02% 99.93% # Table walker service (enqueue to completion) latency 531system.cpu0.itb.walker.walkCompletionTime::196608-229375 21 0.04% 99.97% # Table walker service (enqueue to completion) latency 532system.cpu0.itb.walker.walkCompletionTime::229376-262143 10 0.02% 99.98% # Table walker service (enqueue to completion) latency 533system.cpu0.itb.walker.walkCompletionTime::262144-294911 3 0.01% 99.99% # Table walker service (enqueue to completion) latency 534system.cpu0.itb.walker.walkCompletionTime::294912-327679 1 0.00% 99.99% # Table walker service (enqueue to completion) latency 535system.cpu0.itb.walker.walkCompletionTime::327680-360447 3 0.01% 100.00% # Table walker service (enqueue to completion) latency 536system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 537system.cpu0.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 538system.cpu0.itb.walker.walkCompletionTime::total 59577 # Table walker service (enqueue to completion) latency 539system.cpu0.itb.walker.walksPending::samples 787865704 # Table walker pending requests distribution 540system.cpu0.itb.walker.walksPending::0 787865704 100.00% 100.00% # Table walker pending requests distribution 541system.cpu0.itb.walker.walksPending::total 787865704 # Table walker pending requests distribution 542system.cpu0.itb.walker.walkPageSizes::4K 58898 98.86% 98.86% # Table walker page sizes translated 543system.cpu0.itb.walker.walkPageSizes::2M 679 1.14% 100.00% # Table walker page sizes translated 544system.cpu0.itb.walker.walkPageSizes::total 59577 # Table walker page sizes translated 545system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 546system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 66347 # Table walker requests started/completed, data/inst 547system.cpu0.itb.walker.walkRequestOrigin_Requested::total 66347 # Table walker requests started/completed, data/inst 548system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 549system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 59577 # Table walker requests started/completed, data/inst 550system.cpu0.itb.walker.walkRequestOrigin_Completed::total 59577 # Table walker requests started/completed, data/inst 551system.cpu0.itb.walker.walkRequestOrigin::total 125924 # Table walker requests started/completed, data/inst 552system.cpu0.itb.inst_hits 239632917 # ITB inst hits 553system.cpu0.itb.inst_misses 66347 # ITB inst misses 554system.cpu0.itb.read_hits 0 # DTB read hits 555system.cpu0.itb.read_misses 0 # DTB read misses 556system.cpu0.itb.write_hits 0 # DTB write hits 557system.cpu0.itb.write_misses 0 # DTB write misses 558system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 559system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 560system.cpu0.itb.flush_tlb_mva_asid 38373 # Number of times TLB was flushed by MVA & ASID 561system.cpu0.itb.flush_tlb_asid 1014 # Number of times TLB was flushed by ASID 562system.cpu0.itb.flush_entries 26379 # Number of entries that have been flushed from TLB 563system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 564system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 565system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 566system.cpu0.itb.perms_faults 196328 # Number of TLB faults due to permissions restrictions 567system.cpu0.itb.read_accesses 0 # DTB read accesses 568system.cpu0.itb.write_accesses 0 # DTB write accesses 569system.cpu0.itb.inst_accesses 239699264 # ITB inst accesses 570system.cpu0.itb.hits 239632917 # DTB hits 571system.cpu0.itb.misses 66347 # DTB misses 572system.cpu0.itb.accesses 239699264 # DTB accesses 573system.cpu0.numCycles 955623985 # number of cpu cycles simulated 574system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 575system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 576system.cpu0.committedInsts 445844997 # Number of instructions committed 577system.cpu0.committedOps 524389125 # Number of ops (including micro ops) committed 578system.cpu0.discardedOps 43457031 # Number of ops (including micro ops) which were discarded before commit 579system.cpu0.numFetchSuspends 4220 # Number of times Execute suspended instruction fetching 580system.cpu0.quiesceCycles 93776986984 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 581system.cpu0.cpi 2.143400 # CPI: cycles per instruction 582system.cpu0.ipc 0.466549 # IPC: instructions per cycle 583system.cpu0.kern.inst.arm 0 # number of arm instructions executed 584system.cpu0.kern.inst.quiesce 13187 # number of quiesce instructions executed 585system.cpu0.tickCycles 717454138 # Number of cycles that the object actually ticked 586system.cpu0.idleCycles 238169847 # Total number of cycles that the object has spent stopped 587system.cpu0.dcache.tags.replacements 5506052 # number of replacements 588system.cpu0.dcache.tags.tagsinuse 502.001203 # Cycle average of tags in use 589system.cpu0.dcache.tags.total_refs 155497940 # Total number of references to valid blocks. 590system.cpu0.dcache.tags.sampled_refs 5506563 # Sample count of references to valid blocks. 591system.cpu0.dcache.tags.avg_refs 28.238656 # Average number of references to valid blocks. 592system.cpu0.dcache.tags.warmup_cycle 5093256500 # Cycle when the warmup percentage was hit. 593system.cpu0.dcache.tags.occ_blocks::cpu0.data 502.001203 # Average occupied blocks per requestor 594system.cpu0.dcache.tags.occ_percent::cpu0.data 0.980471 # Average percentage of cache occupancy 595system.cpu0.dcache.tags.occ_percent::total 0.980471 # Average percentage of cache occupancy 596system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 597system.cpu0.dcache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id 598system.cpu0.dcache.tags.age_task_id_blocks_1024::1 331 # Occupied blocks per task id 599system.cpu0.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id 600system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 601system.cpu0.dcache.tags.tag_accesses 330491760 # Number of tag accesses 602system.cpu0.dcache.tags.data_accesses 330491760 # Number of data accesses 603system.cpu0.dcache.ReadReq_hits::cpu0.data 79543100 # number of ReadReq hits 604system.cpu0.dcache.ReadReq_hits::total 79543100 # number of ReadReq hits 605system.cpu0.dcache.WriteReq_hits::cpu0.data 71719508 # number of WriteReq hits 606system.cpu0.dcache.WriteReq_hits::total 71719508 # number of WriteReq hits 607system.cpu0.dcache.SoftPFReq_hits::cpu0.data 278613 # number of SoftPFReq hits 608system.cpu0.dcache.SoftPFReq_hits::total 278613 # number of SoftPFReq hits 609system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 256505 # number of WriteInvalidateReq hits 610system.cpu0.dcache.WriteInvalidateReq_hits::total 256505 # number of WriteInvalidateReq hits 611system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1617523 # number of LoadLockedReq hits 612system.cpu0.dcache.LoadLockedReq_hits::total 1617523 # number of LoadLockedReq hits 613system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1589938 # number of StoreCondReq hits 614system.cpu0.dcache.StoreCondReq_hits::total 1589938 # number of StoreCondReq hits 615system.cpu0.dcache.demand_hits::cpu0.data 151262608 # number of demand (read+write) hits 616system.cpu0.dcache.demand_hits::total 151262608 # number of demand (read+write) hits 617system.cpu0.dcache.overall_hits::cpu0.data 151541221 # number of overall hits 618system.cpu0.dcache.overall_hits::total 151541221 # number of overall hits 619system.cpu0.dcache.ReadReq_misses::cpu0.data 3339841 # number of ReadReq misses 620system.cpu0.dcache.ReadReq_misses::total 3339841 # number of ReadReq misses 621system.cpu0.dcache.WriteReq_misses::cpu0.data 2311852 # number of WriteReq misses 622system.cpu0.dcache.WriteReq_misses::total 2311852 # number of WriteReq misses 623system.cpu0.dcache.SoftPFReq_misses::cpu0.data 620748 # number of SoftPFReq misses 624system.cpu0.dcache.SoftPFReq_misses::total 620748 # number of SoftPFReq misses 625system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 822680 # number of WriteInvalidateReq misses 626system.cpu0.dcache.WriteInvalidateReq_misses::total 822680 # number of WriteInvalidateReq misses 627system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 157499 # number of LoadLockedReq misses 628system.cpu0.dcache.LoadLockedReq_misses::total 157499 # number of LoadLockedReq misses 629system.cpu0.dcache.StoreCondReq_misses::cpu0.data 183638 # number of StoreCondReq misses 630system.cpu0.dcache.StoreCondReq_misses::total 183638 # number of StoreCondReq misses 631system.cpu0.dcache.demand_misses::cpu0.data 5651693 # number of demand (read+write) misses 632system.cpu0.dcache.demand_misses::total 5651693 # number of demand (read+write) misses 633system.cpu0.dcache.overall_misses::cpu0.data 6272441 # number of overall misses 634system.cpu0.dcache.overall_misses::total 6272441 # number of overall misses 635system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 49670372012 # number of ReadReq miss cycles 636system.cpu0.dcache.ReadReq_miss_latency::total 49670372012 # number of ReadReq miss cycles 637system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 43497452544 # number of WriteReq miss cycles 638system.cpu0.dcache.WriteReq_miss_latency::total 43497452544 # number of WriteReq miss cycles 639system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 32835554230 # number of WriteInvalidateReq miss cycles 640system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 32835554230 # number of WriteInvalidateReq miss cycles 641system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2312206455 # number of LoadLockedReq miss cycles 642system.cpu0.dcache.LoadLockedReq_miss_latency::total 2312206455 # number of LoadLockedReq miss cycles 643system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3898320876 # number of StoreCondReq miss cycles 644system.cpu0.dcache.StoreCondReq_miss_latency::total 3898320876 # number of StoreCondReq miss cycles 645system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3663000 # number of StoreCondFailReq miss cycles 646system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3663000 # number of StoreCondFailReq miss cycles 647system.cpu0.dcache.demand_miss_latency::cpu0.data 93167824556 # number of demand (read+write) miss cycles 648system.cpu0.dcache.demand_miss_latency::total 93167824556 # number of demand (read+write) miss cycles 649system.cpu0.dcache.overall_miss_latency::cpu0.data 93167824556 # number of overall miss cycles 650system.cpu0.dcache.overall_miss_latency::total 93167824556 # number of overall miss cycles 651system.cpu0.dcache.ReadReq_accesses::cpu0.data 82882941 # number of ReadReq accesses(hits+misses) 652system.cpu0.dcache.ReadReq_accesses::total 82882941 # number of ReadReq accesses(hits+misses) 653system.cpu0.dcache.WriteReq_accesses::cpu0.data 74031360 # number of WriteReq accesses(hits+misses) 654system.cpu0.dcache.WriteReq_accesses::total 74031360 # number of WriteReq accesses(hits+misses) 655system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 899361 # number of SoftPFReq accesses(hits+misses) 656system.cpu0.dcache.SoftPFReq_accesses::total 899361 # number of SoftPFReq accesses(hits+misses) 657system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1079185 # number of WriteInvalidateReq accesses(hits+misses) 658system.cpu0.dcache.WriteInvalidateReq_accesses::total 1079185 # number of WriteInvalidateReq accesses(hits+misses) 659system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1775022 # number of LoadLockedReq accesses(hits+misses) 660system.cpu0.dcache.LoadLockedReq_accesses::total 1775022 # number of LoadLockedReq accesses(hits+misses) 661system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1773576 # number of StoreCondReq accesses(hits+misses) 662system.cpu0.dcache.StoreCondReq_accesses::total 1773576 # number of StoreCondReq accesses(hits+misses) 663system.cpu0.dcache.demand_accesses::cpu0.data 156914301 # number of demand (read+write) accesses 664system.cpu0.dcache.demand_accesses::total 156914301 # number of demand (read+write) accesses 665system.cpu0.dcache.overall_accesses::cpu0.data 157813662 # number of overall (read+write) accesses 666system.cpu0.dcache.overall_accesses::total 157813662 # number of overall (read+write) accesses 667system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040296 # miss rate for ReadReq accesses 668system.cpu0.dcache.ReadReq_miss_rate::total 0.040296 # miss rate for ReadReq accesses 669system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031228 # miss rate for WriteReq accesses 670system.cpu0.dcache.WriteReq_miss_rate::total 0.031228 # miss rate for WriteReq accesses 671system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.690210 # miss rate for SoftPFReq accesses 672system.cpu0.dcache.SoftPFReq_miss_rate::total 0.690210 # miss rate for SoftPFReq accesses 673system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.762316 # miss rate for WriteInvalidateReq accesses 674system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.762316 # miss rate for WriteInvalidateReq accesses 675system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088731 # miss rate for LoadLockedReq accesses 676system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088731 # miss rate for LoadLockedReq accesses 677system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.103541 # miss rate for StoreCondReq accesses 678system.cpu0.dcache.StoreCondReq_miss_rate::total 0.103541 # miss rate for StoreCondReq accesses 679system.cpu0.dcache.demand_miss_rate::cpu0.data 0.036018 # miss rate for demand accesses 680system.cpu0.dcache.demand_miss_rate::total 0.036018 # miss rate for demand accesses 681system.cpu0.dcache.overall_miss_rate::cpu0.data 0.039746 # miss rate for overall accesses 682system.cpu0.dcache.overall_miss_rate::total 0.039746 # miss rate for overall accesses 683system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14872.076848 # average ReadReq miss latency 684system.cpu0.dcache.ReadReq_avg_miss_latency::total 14872.076848 # average ReadReq miss latency 685system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18814.981471 # average WriteReq miss latency 686system.cpu0.dcache.WriteReq_avg_miss_latency::total 18814.981471 # average WriteReq miss latency 687system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 39912.911740 # average WriteInvalidateReq miss latency 688system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 39912.911740 # average WriteInvalidateReq miss latency 689system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14680.769116 # average LoadLockedReq miss latency 690system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14680.769116 # average LoadLockedReq miss latency 691system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21228.290855 # average StoreCondReq miss latency 692system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21228.290855 # average StoreCondReq miss latency 693system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 694system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 695system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16484.940806 # average overall miss latency 696system.cpu0.dcache.demand_avg_miss_latency::total 16484.940806 # average overall miss latency 697system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14853.519476 # average overall miss latency 698system.cpu0.dcache.overall_avg_miss_latency::total 14853.519476 # average overall miss latency 699system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 700system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 701system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 702system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 703system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 704system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 705system.cpu0.dcache.fast_writes 0 # number of fast writes performed 706system.cpu0.dcache.cache_copies 0 # number of cache copies performed 707system.cpu0.dcache.writebacks::writebacks 3760610 # number of writebacks 708system.cpu0.dcache.writebacks::total 3760610 # number of writebacks 709system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 413115 # number of ReadReq MSHR hits 710system.cpu0.dcache.ReadReq_mshr_hits::total 413115 # number of ReadReq MSHR hits 711system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 966709 # number of WriteReq MSHR hits 712system.cpu0.dcache.WriteReq_mshr_hits::total 966709 # number of WriteReq MSHR hits 713system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 96 # number of WriteInvalidateReq MSHR hits 714system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 96 # number of WriteInvalidateReq MSHR hits 715system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 42490 # number of LoadLockedReq MSHR hits 716system.cpu0.dcache.LoadLockedReq_mshr_hits::total 42490 # number of LoadLockedReq MSHR hits 717system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 52 # number of StoreCondReq MSHR hits 718system.cpu0.dcache.StoreCondReq_mshr_hits::total 52 # number of StoreCondReq MSHR hits 719system.cpu0.dcache.demand_mshr_hits::cpu0.data 1379824 # number of demand (read+write) MSHR hits 720system.cpu0.dcache.demand_mshr_hits::total 1379824 # number of demand (read+write) MSHR hits 721system.cpu0.dcache.overall_mshr_hits::cpu0.data 1379824 # number of overall MSHR hits 722system.cpu0.dcache.overall_mshr_hits::total 1379824 # number of overall MSHR hits 723system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2926726 # number of ReadReq MSHR misses 724system.cpu0.dcache.ReadReq_mshr_misses::total 2926726 # number of ReadReq MSHR misses 725system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1345143 # number of WriteReq MSHR misses 726system.cpu0.dcache.WriteReq_mshr_misses::total 1345143 # number of WriteReq MSHR misses 727system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 614981 # number of SoftPFReq MSHR misses 728system.cpu0.dcache.SoftPFReq_mshr_misses::total 614981 # number of SoftPFReq MSHR misses 729system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 822584 # number of WriteInvalidateReq MSHR misses 730system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 822584 # number of WriteInvalidateReq MSHR misses 731system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 115009 # number of LoadLockedReq MSHR misses 732system.cpu0.dcache.LoadLockedReq_mshr_misses::total 115009 # number of LoadLockedReq MSHR misses 733system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 183586 # number of StoreCondReq MSHR misses 734system.cpu0.dcache.StoreCondReq_mshr_misses::total 183586 # number of StoreCondReq MSHR misses 735system.cpu0.dcache.demand_mshr_misses::cpu0.data 4271869 # number of demand (read+write) MSHR misses 736system.cpu0.dcache.demand_mshr_misses::total 4271869 # number of demand (read+write) MSHR misses 737system.cpu0.dcache.overall_mshr_misses::cpu0.data 4886850 # number of overall MSHR misses 738system.cpu0.dcache.overall_mshr_misses::total 4886850 # number of overall MSHR misses 739system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 33259 # number of ReadReq MSHR uncacheable 740system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33259 # number of ReadReq MSHR uncacheable 741system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 33163 # number of WriteReq MSHR uncacheable 742system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33163 # number of WriteReq MSHR uncacheable 743system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 66422 # number of overall MSHR uncacheable misses 744system.cpu0.dcache.overall_mshr_uncacheable_misses::total 66422 # number of overall MSHR uncacheable misses 745system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 37662767131 # number of ReadReq MSHR miss cycles 746system.cpu0.dcache.ReadReq_mshr_miss_latency::total 37662767131 # number of ReadReq MSHR miss cycles 747system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 23537156289 # number of WriteReq MSHR miss cycles 748system.cpu0.dcache.WriteReq_mshr_miss_latency::total 23537156289 # number of WriteReq MSHR miss cycles 749system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13208319439 # number of SoftPFReq MSHR miss cycles 750system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13208319439 # number of SoftPFReq MSHR miss cycles 751system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 31592370271 # number of WriteInvalidateReq MSHR miss cycles 752system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 31592370271 # number of WriteInvalidateReq MSHR miss cycles 753system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1454810141 # number of LoadLockedReq MSHR miss cycles 754system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1454810141 # number of LoadLockedReq MSHR miss cycles 755system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3611856094 # number of StoreCondReq MSHR miss cycles 756system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3611856094 # number of StoreCondReq MSHR miss cycles 757system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3160000 # number of StoreCondFailReq MSHR miss cycles 758system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3160000 # number of StoreCondFailReq MSHR miss cycles 759system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61199923420 # number of demand (read+write) MSHR miss cycles 760system.cpu0.dcache.demand_mshr_miss_latency::total 61199923420 # number of demand (read+write) MSHR miss cycles 761system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 74408242859 # number of overall MSHR miss cycles 762system.cpu0.dcache.overall_mshr_miss_latency::total 74408242859 # number of overall MSHR miss cycles 763system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5916157251 # number of ReadReq MSHR uncacheable cycles 764system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5916157251 # number of ReadReq MSHR uncacheable cycles 765system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5692664250 # number of WriteReq MSHR uncacheable cycles 766system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5692664250 # number of WriteReq MSHR uncacheable cycles 767system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11608821501 # number of overall MSHR uncacheable cycles 768system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11608821501 # number of overall MSHR uncacheable cycles 769system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035312 # mshr miss rate for ReadReq accesses 770system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035312 # mshr miss rate for ReadReq accesses 771system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018170 # mshr miss rate for WriteReq accesses 772system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018170 # mshr miss rate for WriteReq accesses 773system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.683798 # mshr miss rate for SoftPFReq accesses 774system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.683798 # mshr miss rate for SoftPFReq accesses 775system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.762227 # mshr miss rate for WriteInvalidateReq accesses 776system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.762227 # mshr miss rate for WriteInvalidateReq accesses 777system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064793 # mshr miss rate for LoadLockedReq accesses 778system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064793 # mshr miss rate for LoadLockedReq accesses 779system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.103512 # mshr miss rate for StoreCondReq accesses 780system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.103512 # mshr miss rate for StoreCondReq accesses 781system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027224 # mshr miss rate for demand accesses 782system.cpu0.dcache.demand_mshr_miss_rate::total 0.027224 # mshr miss rate for demand accesses 783system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030966 # mshr miss rate for overall accesses 784system.cpu0.dcache.overall_mshr_miss_rate::total 0.030966 # mshr miss rate for overall accesses 785system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12868.566149 # average ReadReq mshr miss latency 786system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12868.566149 # average ReadReq mshr miss latency 787system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17497.884083 # average WriteReq mshr miss latency 788system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17497.884083 # average WriteReq mshr miss latency 789system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21477.605713 # average SoftPFReq mshr miss latency 790system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21477.605713 # average SoftPFReq mshr miss latency 791system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 38406.254280 # average WriteInvalidateReq mshr miss latency 792system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 38406.254280 # average WriteInvalidateReq mshr miss latency 793system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12649.533002 # average LoadLockedReq mshr miss latency 794system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12649.533002 # average LoadLockedReq mshr miss latency 795system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19673.919003 # average StoreCondReq mshr miss latency 796system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19673.919003 # average StoreCondReq mshr miss latency 797system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 798system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 799system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14326.264083 # average overall mshr miss latency 800system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14326.264083 # average overall mshr miss latency 801system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15226.217882 # average overall mshr miss latency 802system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15226.217882 # average overall mshr miss latency 803system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177881.393036 # average ReadReq mshr uncacheable latency 804system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 177881.393036 # average ReadReq mshr uncacheable latency 805system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171657.095257 # average WriteReq mshr uncacheable latency 806system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171657.095257 # average WriteReq mshr uncacheable latency 807system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 174773.742149 # average overall mshr uncacheable latency 808system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 174773.742149 # average overall mshr uncacheable latency 809system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 810system.cpu0.icache.tags.replacements 9994306 # number of replacements 811system.cpu0.icache.tags.tagsinuse 511.930109 # Cycle average of tags in use 812system.cpu0.icache.tags.total_refs 229434949 # Total number of references to valid blocks. 813system.cpu0.icache.tags.sampled_refs 9994818 # Sample count of references to valid blocks. 814system.cpu0.icache.tags.avg_refs 22.955390 # Average number of references to valid blocks. 815system.cpu0.icache.tags.warmup_cycle 24035147250 # Cycle when the warmup percentage was hit. 816system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.930109 # Average occupied blocks per requestor 817system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999863 # Average percentage of cache occupancy 818system.cpu0.icache.tags.occ_percent::total 0.999863 # Average percentage of cache occupancy 819system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 820system.cpu0.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id 821system.cpu0.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id 822system.cpu0.icache.tags.age_task_id_blocks_1024::2 254 # Occupied blocks per task id 823system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 824system.cpu0.icache.tags.tag_accesses 488854379 # Number of tag accesses 825system.cpu0.icache.tags.data_accesses 488854379 # Number of data accesses 826system.cpu0.icache.ReadReq_hits::cpu0.inst 229434949 # number of ReadReq hits 827system.cpu0.icache.ReadReq_hits::total 229434949 # number of ReadReq hits 828system.cpu0.icache.demand_hits::cpu0.inst 229434949 # number of demand (read+write) hits 829system.cpu0.icache.demand_hits::total 229434949 # number of demand (read+write) hits 830system.cpu0.icache.overall_hits::cpu0.inst 229434949 # number of overall hits 831system.cpu0.icache.overall_hits::total 229434949 # number of overall hits 832system.cpu0.icache.ReadReq_misses::cpu0.inst 9994827 # number of ReadReq misses 833system.cpu0.icache.ReadReq_misses::total 9994827 # number of ReadReq misses 834system.cpu0.icache.demand_misses::cpu0.inst 9994827 # number of demand (read+write) misses 835system.cpu0.icache.demand_misses::total 9994827 # number of demand (read+write) misses 836system.cpu0.icache.overall_misses::cpu0.inst 9994827 # number of overall misses 837system.cpu0.icache.overall_misses::total 9994827 # number of overall misses 838system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 98560798487 # number of ReadReq miss cycles 839system.cpu0.icache.ReadReq_miss_latency::total 98560798487 # number of ReadReq miss cycles 840system.cpu0.icache.demand_miss_latency::cpu0.inst 98560798487 # number of demand (read+write) miss cycles 841system.cpu0.icache.demand_miss_latency::total 98560798487 # number of demand (read+write) miss cycles 842system.cpu0.icache.overall_miss_latency::cpu0.inst 98560798487 # number of overall miss cycles 843system.cpu0.icache.overall_miss_latency::total 98560798487 # number of overall miss cycles 844system.cpu0.icache.ReadReq_accesses::cpu0.inst 239429776 # number of ReadReq accesses(hits+misses) 845system.cpu0.icache.ReadReq_accesses::total 239429776 # number of ReadReq accesses(hits+misses) 846system.cpu0.icache.demand_accesses::cpu0.inst 239429776 # number of demand (read+write) accesses 847system.cpu0.icache.demand_accesses::total 239429776 # number of demand (read+write) accesses 848system.cpu0.icache.overall_accesses::cpu0.inst 239429776 # number of overall (read+write) accesses 849system.cpu0.icache.overall_accesses::total 239429776 # number of overall (read+write) accesses 850system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.041744 # miss rate for ReadReq accesses 851system.cpu0.icache.ReadReq_miss_rate::total 0.041744 # miss rate for ReadReq accesses 852system.cpu0.icache.demand_miss_rate::cpu0.inst 0.041744 # miss rate for demand accesses 853system.cpu0.icache.demand_miss_rate::total 0.041744 # miss rate for demand accesses 854system.cpu0.icache.overall_miss_rate::cpu0.inst 0.041744 # miss rate for overall accesses 855system.cpu0.icache.overall_miss_rate::total 0.041744 # miss rate for overall accesses 856system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9861.181038 # average ReadReq miss latency 857system.cpu0.icache.ReadReq_avg_miss_latency::total 9861.181038 # average ReadReq miss latency 858system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9861.181038 # average overall miss latency 859system.cpu0.icache.demand_avg_miss_latency::total 9861.181038 # average overall miss latency 860system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9861.181038 # average overall miss latency 861system.cpu0.icache.overall_avg_miss_latency::total 9861.181038 # average overall miss latency 862system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 863system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 864system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 865system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 866system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 867system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 868system.cpu0.icache.fast_writes 0 # number of fast writes performed 869system.cpu0.icache.cache_copies 0 # number of cache copies performed 870system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9994827 # number of ReadReq MSHR misses 871system.cpu0.icache.ReadReq_mshr_misses::total 9994827 # number of ReadReq MSHR misses 872system.cpu0.icache.demand_mshr_misses::cpu0.inst 9994827 # number of demand (read+write) MSHR misses 873system.cpu0.icache.demand_mshr_misses::total 9994827 # number of demand (read+write) MSHR misses 874system.cpu0.icache.overall_mshr_misses::cpu0.inst 9994827 # number of overall MSHR misses 875system.cpu0.icache.overall_mshr_misses::total 9994827 # number of overall MSHR misses 876system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52307 # number of ReadReq MSHR uncacheable 877system.cpu0.icache.ReadReq_mshr_uncacheable::total 52307 # number of ReadReq MSHR uncacheable 878system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52307 # number of overall MSHR uncacheable misses 879system.cpu0.icache.overall_mshr_uncacheable_misses::total 52307 # number of overall MSHR uncacheable misses 880system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 88537189453 # number of ReadReq MSHR miss cycles 881system.cpu0.icache.ReadReq_mshr_miss_latency::total 88537189453 # number of ReadReq MSHR miss cycles 882system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 88537189453 # number of demand (read+write) MSHR miss cycles 883system.cpu0.icache.demand_mshr_miss_latency::total 88537189453 # number of demand (read+write) MSHR miss cycles 884system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 88537189453 # number of overall MSHR miss cycles 885system.cpu0.icache.overall_mshr_miss_latency::total 88537189453 # number of overall MSHR miss cycles 886system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4833897250 # number of ReadReq MSHR uncacheable cycles 887system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4833897250 # number of ReadReq MSHR uncacheable cycles 888system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4833897250 # number of overall MSHR uncacheable cycles 889system.cpu0.icache.overall_mshr_uncacheable_latency::total 4833897250 # number of overall MSHR uncacheable cycles 890system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.041744 # mshr miss rate for ReadReq accesses 891system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.041744 # mshr miss rate for ReadReq accesses 892system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.041744 # mshr miss rate for demand accesses 893system.cpu0.icache.demand_mshr_miss_rate::total 0.041744 # mshr miss rate for demand accesses 894system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.041744 # mshr miss rate for overall accesses 895system.cpu0.icache.overall_mshr_miss_rate::total 0.041744 # mshr miss rate for overall accesses 896system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8858.301345 # average ReadReq mshr miss latency 897system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8858.301345 # average ReadReq mshr miss latency 898system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8858.301345 # average overall mshr miss latency 899system.cpu0.icache.demand_avg_mshr_miss_latency::total 8858.301345 # average overall mshr miss latency 900system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8858.301345 # average overall mshr miss latency 901system.cpu0.icache.overall_avg_mshr_miss_latency::total 8858.301345 # average overall mshr miss latency 902system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92413.964670 # average ReadReq mshr uncacheable latency 903system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92413.964670 # average ReadReq mshr uncacheable latency 904system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92413.964670 # average overall mshr uncacheable latency 905system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92413.964670 # average overall mshr uncacheable latency 906system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 907system.cpu0.l2cache.prefetcher.num_hwpf_issued 7230073 # number of hwpf issued 908system.cpu0.l2cache.prefetcher.pfIdentified 7233896 # number of prefetch candidates identified 909system.cpu0.l2cache.prefetcher.pfBufferHit 3309 # number of redundant prefetches already in prefetch queue 910system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 911system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 912system.cpu0.l2cache.prefetcher.pfSpanPage 950560 # number of prefetches not generated due to page crossing 913system.cpu0.l2cache.tags.replacements 2661651 # number of replacements 914system.cpu0.l2cache.tags.tagsinuse 16101.576152 # Cycle average of tags in use 915system.cpu0.l2cache.tags.total_refs 15630806 # Total number of references to valid blocks. 916system.cpu0.l2cache.tags.sampled_refs 2677359 # Sample count of references to valid blocks. 917system.cpu0.l2cache.tags.avg_refs 5.838143 # Average number of references to valid blocks. 918system.cpu0.l2cache.tags.warmup_cycle 5822133500 # Cycle when the warmup percentage was hit. 919system.cpu0.l2cache.tags.occ_blocks::writebacks 5793.980406 # Average occupied blocks per requestor 920system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 73.792044 # Average occupied blocks per requestor 921system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 73.619480 # Average occupied blocks per requestor 922system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5777.684117 # Average occupied blocks per requestor 923system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3504.905506 # Average occupied blocks per requestor 924system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 877.594600 # Average occupied blocks per requestor 925system.cpu0.l2cache.tags.occ_percent::writebacks 0.353636 # Average percentage of cache occupancy 926system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004504 # Average percentage of cache occupancy 927system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004493 # Average percentage of cache occupancy 928system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.352642 # Average percentage of cache occupancy 929system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.213922 # Average percentage of cache occupancy 930system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.053564 # Average percentage of cache occupancy 931system.cpu0.l2cache.tags.occ_percent::total 0.982762 # Average percentage of cache occupancy 932system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1351 # Occupied blocks per task id 933system.cpu0.l2cache.tags.occ_task_id_blocks::1023 92 # Occupied blocks per task id 934system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14265 # Occupied blocks per task id 935system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 52 # Occupied blocks per task id 936system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 263 # Occupied blocks per task id 937system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 985 # Occupied blocks per task id 938system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 51 # Occupied blocks per task id 939system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id 940system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 56 # Occupied blocks per task id 941system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 31 # Occupied blocks per task id 942system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id 943system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id 944system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 705 # Occupied blocks per task id 945system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5210 # Occupied blocks per task id 946system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7781 # Occupied blocks per task id 947system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 446 # Occupied blocks per task id 948system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.082458 # Percentage of cache occupancy per task id 949system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005615 # Percentage of cache occupancy per task id 950system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.870667 # Percentage of cache occupancy per task id 951system.cpu0.l2cache.tags.tag_accesses 331999507 # Number of tag accesses 952system.cpu0.l2cache.tags.data_accesses 331999507 # Number of data accesses 953system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 494334 # number of ReadReq hits 954system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 160804 # number of ReadReq hits 955system.cpu0.l2cache.ReadReq_hits::cpu0.inst 9208783 # number of ReadReq hits 956system.cpu0.l2cache.ReadReq_hits::cpu0.data 2710357 # number of ReadReq hits 957system.cpu0.l2cache.ReadReq_hits::total 12574278 # number of ReadReq hits 958system.cpu0.l2cache.Writeback_hits::writebacks 3760607 # number of Writeback hits 959system.cpu0.l2cache.Writeback_hits::total 3760607 # number of Writeback hits 960system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 232072 # number of WriteInvalidateReq hits 961system.cpu0.l2cache.WriteInvalidateReq_hits::total 232072 # number of WriteInvalidateReq hits 962system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 101378 # number of UpgradeReq hits 963system.cpu0.l2cache.UpgradeReq_hits::total 101378 # number of UpgradeReq hits 964system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 33994 # number of SCUpgradeReq hits 965system.cpu0.l2cache.SCUpgradeReq_hits::total 33994 # number of SCUpgradeReq hits 966system.cpu0.l2cache.ReadExReq_hits::cpu0.data 863447 # number of ReadExReq hits 967system.cpu0.l2cache.ReadExReq_hits::total 863447 # number of ReadExReq hits 968system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 494334 # number of demand (read+write) hits 969system.cpu0.l2cache.demand_hits::cpu0.itb.walker 160804 # number of demand (read+write) hits 970system.cpu0.l2cache.demand_hits::cpu0.inst 9208783 # number of demand (read+write) hits 971system.cpu0.l2cache.demand_hits::cpu0.data 3573804 # number of demand (read+write) hits 972system.cpu0.l2cache.demand_hits::total 13437725 # number of demand (read+write) hits 973system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 494334 # number of overall hits 974system.cpu0.l2cache.overall_hits::cpu0.itb.walker 160804 # number of overall hits 975system.cpu0.l2cache.overall_hits::cpu0.inst 9208783 # number of overall hits 976system.cpu0.l2cache.overall_hits::cpu0.data 3573804 # number of overall hits 977system.cpu0.l2cache.overall_hits::total 13437725 # number of overall hits 978system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10659 # number of ReadReq misses 979system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7834 # number of ReadReq misses 980system.cpu0.l2cache.ReadReq_misses::cpu0.inst 786043 # number of ReadReq misses 981system.cpu0.l2cache.ReadReq_misses::cpu0.data 946030 # number of ReadReq misses 982system.cpu0.l2cache.ReadReq_misses::total 1750566 # number of ReadReq misses 983system.cpu0.l2cache.Writeback_misses::writebacks 2 # number of Writeback misses 984system.cpu0.l2cache.Writeback_misses::total 2 # number of Writeback misses 985system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 588987 # number of WriteInvalidateReq misses 986system.cpu0.l2cache.WriteInvalidateReq_misses::total 588987 # number of WriteInvalidateReq misses 987system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 124560 # number of UpgradeReq misses 988system.cpu0.l2cache.UpgradeReq_misses::total 124560 # number of UpgradeReq misses 989system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 149586 # number of SCUpgradeReq misses 990system.cpu0.l2cache.SCUpgradeReq_misses::total 149586 # number of SCUpgradeReq misses 991system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 6 # number of SCUpgradeFailReq misses 992system.cpu0.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses 993system.cpu0.l2cache.ReadExReq_misses::cpu0.data 267892 # number of ReadExReq misses 994system.cpu0.l2cache.ReadExReq_misses::total 267892 # number of ReadExReq misses 995system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10659 # number of demand (read+write) misses 996system.cpu0.l2cache.demand_misses::cpu0.itb.walker 7834 # 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number of SCUpgradeFailReq miss cycles 1018system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 12386704821 # number of ReadExReq miss cycles 1019system.cpu0.l2cache.ReadExReq_miss_latency::total 12386704821 # number of ReadExReq miss cycles 1020system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 318928487 # number of demand (read+write) miss cycles 1021system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 253391761 # number of demand (read+write) miss cycles 1022system.cpu0.l2cache.demand_miss_latency::cpu0.inst 23635812248 # number of demand (read+write) miss cycles 1023system.cpu0.l2cache.demand_miss_latency::cpu0.data 43306876902 # number of demand (read+write) miss cycles 1024system.cpu0.l2cache.demand_miss_latency::total 67515009398 # number of demand (read+write) miss cycles 1025system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 318928487 # number of overall miss cycles 1026system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 253391761 # number of overall miss cycles 1027system.cpu0.l2cache.overall_miss_latency::cpu0.inst 23635812248 # number of overall miss cycles 1028system.cpu0.l2cache.overall_miss_latency::cpu0.data 43306876902 # number of overall miss cycles 1029system.cpu0.l2cache.overall_miss_latency::total 67515009398 # number of overall miss cycles 1030system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 504993 # number of ReadReq accesses(hits+misses) 1031system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 168638 # number of ReadReq accesses(hits+misses) 1032system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 9994826 # number of ReadReq accesses(hits+misses) 1033system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3656387 # number of ReadReq accesses(hits+misses) 1034system.cpu0.l2cache.ReadReq_accesses::total 14324844 # number of ReadReq accesses(hits+misses) 1035system.cpu0.l2cache.Writeback_accesses::writebacks 3760609 # number of Writeback accesses(hits+misses) 1036system.cpu0.l2cache.Writeback_accesses::total 3760609 # number of Writeback accesses(hits+misses) 1037system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 821059 # 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number of demand (read+write) accesses 1048system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 168638 # number of demand (read+write) accesses 1049system.cpu0.l2cache.demand_accesses::cpu0.inst 9994826 # number of demand (read+write) accesses 1050system.cpu0.l2cache.demand_accesses::cpu0.data 4787726 # number of demand (read+write) accesses 1051system.cpu0.l2cache.demand_accesses::total 15456183 # number of demand (read+write) accesses 1052system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 504993 # number of overall (read+write) accesses 1053system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 168638 # number of overall (read+write) accesses 1054system.cpu0.l2cache.overall_accesses::cpu0.inst 9994826 # number of overall (read+write) accesses 1055system.cpu0.l2cache.overall_accesses::cpu0.data 4787726 # number of overall (read+write) accesses 1056system.cpu0.l2cache.overall_accesses::total 15456183 # number of overall (read+write) accesses 1057system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.021107 # miss rate for ReadReq accesses 1058system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.046455 # miss rate for ReadReq accesses 1059system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.078645 # miss rate for ReadReq accesses 1060system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.258734 # miss rate for ReadReq accesses 1061system.cpu0.l2cache.ReadReq_miss_rate::total 0.122205 # miss rate for ReadReq accesses 1062system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000001 # miss rate for Writeback accesses 1063system.cpu0.l2cache.Writeback_miss_rate::total 0.000001 # miss rate for Writeback accesses 1064system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.717350 # miss rate for WriteInvalidateReq accesses 1065system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.717350 # miss rate for WriteInvalidateReq accesses 1066system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.551302 # miss rate for UpgradeReq accesses 1067system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.551302 # miss rate for UpgradeReq accesses 1068system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.814827 # miss rate for SCUpgradeReq accesses 1069system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.814827 # miss rate for SCUpgradeReq accesses 1070system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1071system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1072system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.236792 # miss rate for ReadExReq accesses 1073system.cpu0.l2cache.ReadExReq_miss_rate::total 0.236792 # miss rate for ReadExReq accesses 1074system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.021107 # miss rate for demand accesses 1075system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.046455 # miss rate for demand accesses 1076system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.078645 # miss rate for demand accesses 1077system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.253549 # miss rate for demand accesses 1078system.cpu0.l2cache.demand_miss_rate::total 0.130592 # miss rate for demand accesses 1079system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.021107 # miss rate for overall accesses 1080system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.046455 # miss rate for overall accesses 1081system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.078645 # miss rate for overall accesses 1082system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.253549 # miss rate for overall accesses 1083system.cpu0.l2cache.overall_miss_rate::total 0.130592 # miss rate for overall accesses 1084system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 29921.051412 # average ReadReq miss latency 1085system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 32345.131606 # average ReadReq miss latency 1086system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30069.362933 # average ReadReq miss latency 1087system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 32684.134838 # average ReadReq miss latency 1088system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31491.703013 # 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number of UpgradeReq MSHR miss cycles 1181system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2234342769 # number of SCUpgradeReq MSHR miss cycles 1182system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2234342769 # number of SCUpgradeReq MSHR miss cycles 1183system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2647998 # number of SCUpgradeFailReq MSHR miss cycles 1184system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2647998 # number of SCUpgradeFailReq MSHR miss cycles 1185system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 9878225571 # number of ReadExReq MSHR miss cycles 1186system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 9878225571 # number of ReadExReq MSHR miss cycles 1187system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 249336497 # number of demand (read+write) MSHR miss cycles 1188system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 202183759 # number of demand (read+write) MSHR miss cycles 1189system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 18500486252 # number of demand (read+write) MSHR miss cycles 1190system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 34515967726 # number of demand (read+write) MSHR miss cycles 1191system.cpu0.l2cache.demand_mshr_miss_latency::total 53467974234 # number of demand (read+write) MSHR miss cycles 1192system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 249336497 # number of overall MSHR miss cycles 1193system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 202183759 # number of overall MSHR miss cycles 1194system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 18500486252 # number of overall MSHR miss cycles 1195system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 34515967726 # number of overall MSHR miss cycles 1196system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 26923200622 # number of overall MSHR miss cycles 1197system.cpu0.l2cache.overall_mshr_miss_latency::total 80391174856 # number of overall MSHR miss cycles 1198system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4391070750 # number of ReadReq MSHR uncacheable cycles 1199system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5650020250 # number of ReadReq MSHR uncacheable cycles 1200system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10041091000 # number of ReadReq MSHR uncacheable cycles 1201system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5443925500 # number of WriteReq MSHR uncacheable cycles 1202system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5443925500 # number of WriteReq MSHR uncacheable cycles 1203system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4391070750 # number of overall MSHR uncacheable cycles 1204system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11093945750 # number of overall MSHR uncacheable cycles 1205system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15485016500 # number of overall MSHR uncacheable cycles 1206system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021107 # mshr miss rate for ReadReq accesses 1207system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.046455 # mshr miss rate for ReadReq accesses 1208system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.078644 # mshr miss rate for ReadReq accesses 1209system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.258465 # mshr miss rate for ReadReq accesses 1210system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.122136 # mshr miss rate for ReadReq accesses 1211system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for Writeback accesses 1212system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000001 # mshr miss rate for Writeback accesses 1213system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1214system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1215system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.717313 # mshr miss rate for WriteInvalidateReq accesses 1216system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.717313 # mshr miss rate for WriteInvalidateReq accesses 1217system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.551302 # mshr miss rate for UpgradeReq accesses 1218system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.551302 # mshr miss rate for UpgradeReq accesses 1219system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.814827 # mshr miss rate for SCUpgradeReq accesses 1220system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.814827 # mshr miss rate for SCUpgradeReq accesses 1221system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1222system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1223system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.231279 # mshr miss rate for ReadExReq accesses 1224system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.231279 # mshr miss rate for ReadExReq accesses 1225system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021107 # mshr miss rate for demand accesses 1226system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.046455 # mshr miss rate for demand accesses 1227system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.078644 # mshr miss rate for demand accesses 1228system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.252041 # mshr miss rate for demand accesses 1229system.cpu0.l2cache.demand_mshr_miss_rate::total 0.130125 # mshr miss rate for demand accesses 1230system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021107 # mshr miss rate for overall accesses 1231system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.046455 # mshr miss rate for overall accesses 1232system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.078644 # mshr miss rate for overall accesses 1233system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.252041 # mshr miss rate for overall accesses 1234system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1235system.cpu0.l2cache.overall_mshr_miss_rate::total 0.174466 # mshr miss rate for overall accesses 1236system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 23392.109673 # average ReadReq mshr miss latency 1237system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 25808.496171 # average ReadReq mshr miss latency 1238system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23536.406368 # average ReadReq mshr miss latency 1239system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 26070.333025 # average ReadReq mshr miss latency 1240system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24914.421505 # average ReadReq mshr miss latency 1241system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 39284.329024 # average HardPFReq mshr miss latency 1242system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 39284.329024 # average HardPFReq mshr miss latency 1243system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 42944.709754 # average WriteInvalidateReq mshr miss latency 1244system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 42944.709754 # average WriteInvalidateReq mshr miss latency 1245system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20269.613166 # average UpgradeReq mshr miss latency 1246system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20269.613166 # average UpgradeReq mshr miss latency 1247system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14936.844150 # average SCUpgradeReq mshr miss latency 1248system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14936.844150 # average SCUpgradeReq mshr miss latency 1249system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 441333 # average SCUpgradeFailReq mshr miss latency 1250system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 441333 # average SCUpgradeFailReq mshr miss latency 1251system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 37752.863775 # average ReadExReq mshr miss latency 1252system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 37752.863775 # average ReadExReq mshr miss latency 1253system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 23392.109673 # average overall mshr miss latency 1254system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 25808.496171 # average overall mshr miss latency 1255system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23536.406368 # average overall mshr miss latency 1256system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28603.508173 # average overall mshr miss latency 1257system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26584.661076 # average overall mshr miss latency 1258system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 23392.109673 # average overall mshr miss latency 1259system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 25808.496171 # average overall mshr miss latency 1260system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23536.406368 # average overall mshr miss latency 1261system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28603.508173 # average overall mshr miss latency 1262system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 39284.329024 # average overall mshr miss latency 1263system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 29812.315639 # average overall mshr miss latency 1264system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83948.051886 # average ReadReq mshr uncacheable latency 1265system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 169879.438648 # average ReadReq mshr uncacheable latency 1266system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117349.075567 # average ReadReq mshr uncacheable latency 1267system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164156.605253 # average WriteReq mshr uncacheable latency 1268system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164156.605253 # average WriteReq mshr uncacheable latency 1269system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83948.051886 # average overall mshr uncacheable latency 1270system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 167022.157568 # average overall mshr uncacheable latency 1271system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 130423.203261 # average overall mshr uncacheable latency 1272system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1273system.cpu0.toL2Bus.trans_dist::ReadReq 16764997 # Transaction distribution 1274system.cpu0.toL2Bus.trans_dist::ReadResp 14635279 # Transaction distribution 1275system.cpu0.toL2Bus.trans_dist::WriteReq 38250 # Transaction distribution 1276system.cpu0.toL2Bus.trans_dist::WriteResp 33163 # Transaction distribution 1277system.cpu0.toL2Bus.trans_dist::Writeback 3760609 # Transaction distribution 1278system.cpu0.toL2Bus.trans_dist::HardPFReq 997781 # Transaction distribution 1279system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1159753 # Transaction distribution 1280system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 821059 # Transaction distribution 1281system.cpu0.toL2Bus.trans_dist::UpgradeReq 475624 # Transaction distribution 1282system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 336764 # Transaction distribution 1283system.cpu0.toL2Bus.trans_dist::UpgradeResp 482191 # Transaction distribution 1284system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution 1285system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution 1286system.cpu0.toL2Bus.trans_dist::ReadExReq 1257493 # Transaction distribution 1287system.cpu0.toL2Bus.trans_dist::ReadExResp 1141567 # Transaction distribution 1288system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20094267 # Packet count per connected master and slave (bytes) 1289system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16118866 # Packet count per connected master and slave (bytes) 1290system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 366766 # Packet count per connected master and slave (bytes) 1291system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1099589 # Packet count per connected master and slave (bytes) 1292system.cpu0.toL2Bus.pkt_count::total 37679488 # Packet count per connected master and slave (bytes) 1293system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 643016512 # Cumulative packet size per connected master and slave (bytes) 1294system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 607271415 # Cumulative packet size per connected master and slave (bytes) 1295system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1349104 # Cumulative packet size per connected master and slave (bytes) 1296system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4039944 # Cumulative packet size per connected master and slave (bytes) 1297system.cpu0.toL2Bus.pkt_size::total 1255676975 # Cumulative packet size per connected master and slave (bytes) 1298system.cpu0.toL2Bus.snoops 4414025 # Total snoops (count) 1299system.cpu0.toL2Bus.snoop_fanout::samples 24791334 # Request fanout histogram 1300system.cpu0.toL2Bus.snoop_fanout::mean 1.197604 # Request fanout histogram 1301system.cpu0.toL2Bus.snoop_fanout::stdev 0.398192 # Request fanout histogram 1302system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1303system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1304system.cpu0.toL2Bus.snoop_fanout::1 19892474 80.24% 80.24% # Request fanout histogram 1305system.cpu0.toL2Bus.snoop_fanout::2 4898860 19.76% 100.00% # Request fanout histogram 1306system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1307system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1308system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1309system.cpu0.toL2Bus.snoop_fanout::total 24791334 # Request fanout histogram 1310system.cpu0.toL2Bus.reqLayer0.occupancy 14940946397 # Layer occupancy (ticks) 1311system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 1312system.cpu0.toL2Bus.snoopLayer0.occupancy 210442490 # Layer occupancy (ticks) 1313system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1314system.cpu0.toL2Bus.respLayer0.occupancy 15097277267 # Layer occupancy (ticks) 1315system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1316system.cpu0.toL2Bus.respLayer1.occupancy 7911607131 # Layer occupancy (ticks) 1317system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1318system.cpu0.toL2Bus.respLayer2.occupancy 198319454 # Layer occupancy (ticks) 1319system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1320system.cpu0.toL2Bus.respLayer3.occupancy 594828175 # Layer occupancy (ticks) 1321system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1322system.cpu1.branchPred.lookups 123549187 # Number of BP lookups 1323system.cpu1.branchPred.condPredicted 87841692 # Number of conditional branches predicted 1324system.cpu1.branchPred.condIncorrect 5708078 # Number of conditional branches incorrect 1325system.cpu1.branchPred.BTBLookups 93157119 # Number of BTB lookups 1326system.cpu1.branchPred.BTBHits 67436708 # Number of BTB hits 1327system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1328system.cpu1.branchPred.BTBHitPct 72.390289 # BTB Hit Percentage 1329system.cpu1.branchPred.usedRAS 14460012 # Number of times the RAS was used to get a target. 1330system.cpu1.branchPred.RASInCorrect 934859 # Number of incorrect RAS predictions. 1331system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1332system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1333system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1334system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1335system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1336system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1337system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1338system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1339system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1340system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1341system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1342system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1343system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1344system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1345system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1346system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1347system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1348system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1349system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1350system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1351system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1352system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1353system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1354system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1355system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1356system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1357system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1358system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1359system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1360system.cpu1.dtb.walker.walks 259362 # Table walker walks requested 1361system.cpu1.dtb.walker.walksLong 259362 # Table walker walks initiated with long descriptors 1362system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8416 # Level at which table walker walks with long descriptors terminate 1363system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 76621 # Level at which table walker walks with long descriptors terminate 1364system.cpu1.dtb.walker.walkWaitTime::samples 259362 # Table walker wait (enqueue to first request) latency 1365system.cpu1.dtb.walker.walkWaitTime::0 259362 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1366system.cpu1.dtb.walker.walkWaitTime::total 259362 # Table walker wait (enqueue to first request) latency 1367system.cpu1.dtb.walker.walkCompletionTime::samples 85037 # Table walker service (enqueue to completion) latency 1368system.cpu1.dtb.walker.walkCompletionTime::mean 18225.042946 # Table walker service (enqueue to completion) latency 1369system.cpu1.dtb.walker.walkCompletionTime::gmean 16628.571422 # Table walker service (enqueue to completion) latency 1370system.cpu1.dtb.walker.walkCompletionTime::stdev 11774.469557 # Table walker service (enqueue to completion) latency 1371system.cpu1.dtb.walker.walkCompletionTime::0-32767 81545 95.89% 95.89% # Table walker service (enqueue to completion) latency 1372system.cpu1.dtb.walker.walkCompletionTime::32768-65535 2790 3.28% 99.17% # Table walker service (enqueue to completion) latency 1373system.cpu1.dtb.walker.walkCompletionTime::65536-98303 403 0.47% 99.65% # Table walker service (enqueue to completion) latency 1374system.cpu1.dtb.walker.walkCompletionTime::98304-131071 201 0.24% 99.88% # Table walker service (enqueue to completion) latency 1375system.cpu1.dtb.walker.walkCompletionTime::131072-163839 25 0.03% 99.91% # Table walker service (enqueue to completion) latency 1376system.cpu1.dtb.walker.walkCompletionTime::163840-196607 11 0.01% 99.93% # Table walker service (enqueue to completion) latency 1377system.cpu1.dtb.walker.walkCompletionTime::196608-229375 23 0.03% 99.95% # Table walker service (enqueue to completion) latency 1378system.cpu1.dtb.walker.walkCompletionTime::229376-262143 9 0.01% 99.96% # Table walker service (enqueue to completion) latency 1379system.cpu1.dtb.walker.walkCompletionTime::262144-294911 14 0.02% 99.98% # Table walker service (enqueue to completion) latency 1380system.cpu1.dtb.walker.walkCompletionTime::294912-327679 11 0.01% 99.99% # Table walker service (enqueue to completion) latency 1381system.cpu1.dtb.walker.walkCompletionTime::327680-360447 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1382system.cpu1.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1383system.cpu1.dtb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1384system.cpu1.dtb.walker.walkCompletionTime::total 85037 # Table walker service (enqueue to completion) latency 1385system.cpu1.dtb.walker.walksPending::samples 1261494444 # Table walker pending requests distribution 1386system.cpu1.dtb.walker.walksPending::0 1261494444 100.00% 100.00% # Table walker pending requests distribution 1387system.cpu1.dtb.walker.walksPending::total 1261494444 # Table walker pending requests distribution 1388system.cpu1.dtb.walker.walkPageSizes::4K 76621 90.10% 90.10% # Table walker page sizes translated 1389system.cpu1.dtb.walker.walkPageSizes::2M 8416 9.90% 100.00% # Table walker page sizes translated 1390system.cpu1.dtb.walker.walkPageSizes::total 85037 # Table walker page sizes translated 1391system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 259362 # Table walker requests started/completed, data/inst 1392system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1393system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 259362 # Table walker requests started/completed, data/inst 1394system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 85037 # Table walker requests started/completed, data/inst 1395system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1396system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 85037 # Table walker requests started/completed, data/inst 1397system.cpu1.dtb.walker.walkRequestOrigin::total 344399 # Table walker requests started/completed, data/inst 1398system.cpu1.dtb.inst_hits 0 # ITB inst hits 1399system.cpu1.dtb.inst_misses 0 # ITB inst misses 1400system.cpu1.dtb.read_hits 80542266 # DTB read hits 1401system.cpu1.dtb.read_misses 214982 # DTB read misses 1402system.cpu1.dtb.write_hits 69249357 # DTB write hits 1403system.cpu1.dtb.write_misses 44380 # DTB write misses 1404system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1405system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1406system.cpu1.dtb.flush_tlb_mva_asid 38373 # Number of times TLB was flushed by MVA & ASID 1407system.cpu1.dtb.flush_tlb_asid 1014 # Number of times TLB was flushed by ASID 1408system.cpu1.dtb.flush_entries 35601 # Number of entries that have been flushed from TLB 1409system.cpu1.dtb.align_faults 736 # Number of TLB faults due to alignment restrictions 1410system.cpu1.dtb.prefetch_faults 6438 # Number of TLB faults due to prefetch 1411system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1412system.cpu1.dtb.perms_faults 9960 # Number of TLB faults due to permissions restrictions 1413system.cpu1.dtb.read_accesses 80757248 # DTB read accesses 1414system.cpu1.dtb.write_accesses 69293737 # DTB write accesses 1415system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1416system.cpu1.dtb.hits 149791623 # DTB hits 1417system.cpu1.dtb.misses 259362 # DTB misses 1418system.cpu1.dtb.accesses 150050985 # DTB accesses 1419system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1420system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1421system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1422system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1423system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1424system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1425system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1426system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1427system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1428system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1429system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1430system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1431system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1432system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1433system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1434system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1435system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1436system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1437system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1438system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1439system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1440system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1441system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1442system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1443system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1444system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1445system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1446system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1447system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1448system.cpu1.itb.walker.walks 60478 # Table walker walks requested 1449system.cpu1.itb.walker.walksLong 60478 # Table walker walks initiated with long descriptors 1450system.cpu1.itb.walker.walksLongTerminationLevel::Level2 478 # Level at which table walker walks with long descriptors terminate 1451system.cpu1.itb.walker.walksLongTerminationLevel::Level3 50972 # Level at which table walker walks with long descriptors terminate 1452system.cpu1.itb.walker.walkWaitTime::samples 60478 # Table walker wait (enqueue to first request) latency 1453system.cpu1.itb.walker.walkWaitTime::0 60478 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1454system.cpu1.itb.walker.walkWaitTime::total 60478 # Table walker wait (enqueue to first request) latency 1455system.cpu1.itb.walker.walkCompletionTime::samples 51450 # Table walker service (enqueue to completion) latency 1456system.cpu1.itb.walker.walkCompletionTime::mean 20568.513975 # Table walker service (enqueue to completion) latency 1457system.cpu1.itb.walker.walkCompletionTime::gmean 18499.951285 # Table walker service (enqueue to completion) latency 1458system.cpu1.itb.walker.walkCompletionTime::stdev 14805.800668 # Table walker service (enqueue to completion) latency 1459system.cpu1.itb.walker.walkCompletionTime::0-32767 47723 92.76% 92.76% # Table walker service (enqueue to completion) latency 1460system.cpu1.itb.walker.walkCompletionTime::32768-65535 2940 5.71% 98.47% # Table walker service (enqueue to completion) latency 1461system.cpu1.itb.walker.walkCompletionTime::65536-98303 278 0.54% 99.01% # Table walker service (enqueue to completion) latency 1462system.cpu1.itb.walker.walkCompletionTime::98304-131071 425 0.83% 99.84% # Table walker service (enqueue to completion) latency 1463system.cpu1.itb.walker.walkCompletionTime::131072-163839 16 0.03% 99.87% # Table walker service (enqueue to completion) latency 1464system.cpu1.itb.walker.walkCompletionTime::163840-196607 10 0.02% 99.89% # Table walker service (enqueue to completion) latency 1465system.cpu1.itb.walker.walkCompletionTime::196608-229375 27 0.05% 99.94% # Table walker service (enqueue to completion) latency 1466system.cpu1.itb.walker.walkCompletionTime::229376-262143 13 0.03% 99.97% # Table walker service (enqueue to completion) latency 1467system.cpu1.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.98% # Table walker service (enqueue to completion) latency 1468system.cpu1.itb.walker.walkCompletionTime::294912-327679 5 0.01% 99.99% # Table walker service (enqueue to completion) latency 1469system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency 1470system.cpu1.itb.walker.walkCompletionTime::360448-393215 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1471system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1472system.cpu1.itb.walker.walkCompletionTime::total 51450 # Table walker service (enqueue to completion) latency 1473system.cpu1.itb.walker.walksPending::samples 1260837944 # Table walker pending requests distribution 1474system.cpu1.itb.walker.walksPending::0 1260837944 100.00% 100.00% # Table walker pending requests distribution 1475system.cpu1.itb.walker.walksPending::total 1260837944 # Table walker pending requests distribution 1476system.cpu1.itb.walker.walkPageSizes::4K 50972 99.07% 99.07% # Table walker page sizes translated 1477system.cpu1.itb.walker.walkPageSizes::2M 478 0.93% 100.00% # Table walker page sizes translated 1478system.cpu1.itb.walker.walkPageSizes::total 51450 # Table walker page sizes translated 1479system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1480system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60478 # Table walker requests started/completed, data/inst 1481system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60478 # Table walker requests started/completed, data/inst 1482system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1483system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 51450 # Table walker requests started/completed, data/inst 1484system.cpu1.itb.walker.walkRequestOrigin_Completed::total 51450 # Table walker requests started/completed, data/inst 1485system.cpu1.itb.walker.walkRequestOrigin::total 111928 # Table walker requests started/completed, data/inst 1486system.cpu1.itb.inst_hits 220701471 # ITB inst hits 1487system.cpu1.itb.inst_misses 60478 # ITB inst misses 1488system.cpu1.itb.read_hits 0 # DTB read hits 1489system.cpu1.itb.read_misses 0 # DTB read misses 1490system.cpu1.itb.write_hits 0 # DTB write hits 1491system.cpu1.itb.write_misses 0 # DTB write misses 1492system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1493system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1494system.cpu1.itb.flush_tlb_mva_asid 38373 # Number of times TLB was flushed by MVA & ASID 1495system.cpu1.itb.flush_tlb_asid 1014 # Number of times TLB was flushed by ASID 1496system.cpu1.itb.flush_entries 25765 # Number of entries that have been flushed from TLB 1497system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1498system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1499system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1500system.cpu1.itb.perms_faults 203408 # Number of TLB faults due to permissions restrictions 1501system.cpu1.itb.read_accesses 0 # DTB read accesses 1502system.cpu1.itb.write_accesses 0 # DTB write accesses 1503system.cpu1.itb.inst_accesses 220761949 # ITB inst accesses 1504system.cpu1.itb.hits 220701471 # DTB hits 1505system.cpu1.itb.misses 60478 # DTB misses 1506system.cpu1.itb.accesses 220761949 # DTB accesses 1507system.cpu1.numCycles 819495419 # number of cpu cycles simulated 1508system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1509system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1510system.cpu1.committedInsts 407174795 # Number of instructions committed 1511system.cpu1.committedOps 478812576 # Number of ops (including micro ops) committed 1512system.cpu1.discardedOps 42038613 # Number of ops (including micro ops) which were discarded before commit 1513system.cpu1.numFetchSuspends 5231 # Number of times Execute suspended instruction fetching 1514system.cpu1.quiesceCycles 93913157476 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1515system.cpu1.cpi 2.012638 # CPI: cycles per instruction 1516system.cpu1.ipc 0.496860 # IPC: instructions per cycle 1517system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1518system.cpu1.kern.inst.quiesce 5271 # number of quiesce instructions executed 1519system.cpu1.tickCycles 656184177 # Number of cycles that the object actually ticked 1520system.cpu1.idleCycles 163311242 # Total number of cycles that the object has spent stopped 1521system.cpu1.dcache.tags.replacements 4776829 # number of replacements 1522system.cpu1.dcache.tags.tagsinuse 427.655512 # Cycle average of tags in use 1523system.cpu1.dcache.tags.total_refs 142582647 # Total number of references to valid blocks. 1524system.cpu1.dcache.tags.sampled_refs 4777341 # Sample count of references to valid blocks. 1525system.cpu1.dcache.tags.avg_refs 29.845608 # Average number of references to valid blocks. 1526system.cpu1.dcache.tags.warmup_cycle 8380053198500 # Cycle when the warmup percentage was hit. 1527system.cpu1.dcache.tags.occ_blocks::cpu1.data 427.655512 # Average occupied blocks per requestor 1528system.cpu1.dcache.tags.occ_percent::cpu1.data 0.835265 # Average percentage of cache occupancy 1529system.cpu1.dcache.tags.occ_percent::total 0.835265 # Average percentage of cache occupancy 1530system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1531system.cpu1.dcache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id 1532system.cpu1.dcache.tags.age_task_id_blocks_1024::1 405 # Occupied blocks per task id 1533system.cpu1.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id 1534system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1535system.cpu1.dcache.tags.tag_accesses 302037341 # Number of tag accesses 1536system.cpu1.dcache.tags.data_accesses 302037341 # Number of data accesses 1537system.cpu1.dcache.ReadReq_hits::cpu1.data 73896099 # number of ReadReq hits 1538system.cpu1.dcache.ReadReq_hits::total 73896099 # number of ReadReq hits 1539system.cpu1.dcache.WriteReq_hits::cpu1.data 64629380 # number of WriteReq hits 1540system.cpu1.dcache.WriteReq_hits::total 64629380 # number of WriteReq hits 1541system.cpu1.dcache.SoftPFReq_hits::cpu1.data 204586 # number of SoftPFReq hits 1542system.cpu1.dcache.SoftPFReq_hits::total 204586 # number of SoftPFReq hits 1543system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 67650 # number of WriteInvalidateReq hits 1544system.cpu1.dcache.WriteInvalidateReq_hits::total 67650 # number of WriteInvalidateReq hits 1545system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1684264 # number of LoadLockedReq hits 1546system.cpu1.dcache.LoadLockedReq_hits::total 1684264 # number of LoadLockedReq hits 1547system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1653940 # number of StoreCondReq hits 1548system.cpu1.dcache.StoreCondReq_hits::total 1653940 # number of StoreCondReq hits 1549system.cpu1.dcache.demand_hits::cpu1.data 138525479 # number of demand (read+write) hits 1550system.cpu1.dcache.demand_hits::total 138525479 # number of demand (read+write) hits 1551system.cpu1.dcache.overall_hits::cpu1.data 138730065 # number of overall hits 1552system.cpu1.dcache.overall_hits::total 138730065 # number of overall hits 1553system.cpu1.dcache.ReadReq_misses::cpu1.data 3123049 # number of ReadReq misses 1554system.cpu1.dcache.ReadReq_misses::total 3123049 # number of ReadReq misses 1555system.cpu1.dcache.WriteReq_misses::cpu1.data 2001792 # number of WriteReq misses 1556system.cpu1.dcache.WriteReq_misses::total 2001792 # number of WriteReq misses 1557system.cpu1.dcache.SoftPFReq_misses::cpu1.data 560125 # number of SoftPFReq misses 1558system.cpu1.dcache.SoftPFReq_misses::total 560125 # number of SoftPFReq misses 1559system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 418714 # number of WriteInvalidateReq misses 1560system.cpu1.dcache.WriteInvalidateReq_misses::total 418714 # number of WriteInvalidateReq misses 1561system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 158898 # number of LoadLockedReq misses 1562system.cpu1.dcache.LoadLockedReq_misses::total 158898 # number of LoadLockedReq misses 1563system.cpu1.dcache.StoreCondReq_misses::cpu1.data 187849 # number of StoreCondReq misses 1564system.cpu1.dcache.StoreCondReq_misses::total 187849 # number of StoreCondReq misses 1565system.cpu1.dcache.demand_misses::cpu1.data 5124841 # number of demand (read+write) misses 1566system.cpu1.dcache.demand_misses::total 5124841 # number of demand (read+write) misses 1567system.cpu1.dcache.overall_misses::cpu1.data 5684966 # number of overall misses 1568system.cpu1.dcache.overall_misses::total 5684966 # number of overall misses 1569system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 43997999443 # number of ReadReq miss cycles 1570system.cpu1.dcache.ReadReq_miss_latency::total 43997999443 # number of ReadReq miss cycles 1571system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 34323796172 # number of WriteReq miss cycles 1572system.cpu1.dcache.WriteReq_miss_latency::total 34323796172 # number of WriteReq miss cycles 1573system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 11321642584 # number of WriteInvalidateReq miss cycles 1574system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 11321642584 # number of WriteInvalidateReq miss cycles 1575system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2327905715 # number of LoadLockedReq miss cycles 1576system.cpu1.dcache.LoadLockedReq_miss_latency::total 2327905715 # number of LoadLockedReq miss cycles 1577system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3931505754 # number of StoreCondReq miss cycles 1578system.cpu1.dcache.StoreCondReq_miss_latency::total 3931505754 # number of StoreCondReq miss cycles 1579system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3098000 # number of StoreCondFailReq miss cycles 1580system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3098000 # number of StoreCondFailReq miss cycles 1581system.cpu1.dcache.demand_miss_latency::cpu1.data 78321795615 # number of demand (read+write) miss cycles 1582system.cpu1.dcache.demand_miss_latency::total 78321795615 # number of demand (read+write) miss cycles 1583system.cpu1.dcache.overall_miss_latency::cpu1.data 78321795615 # number of overall miss cycles 1584system.cpu1.dcache.overall_miss_latency::total 78321795615 # number of overall miss cycles 1585system.cpu1.dcache.ReadReq_accesses::cpu1.data 77019148 # number of ReadReq accesses(hits+misses) 1586system.cpu1.dcache.ReadReq_accesses::total 77019148 # number of ReadReq accesses(hits+misses) 1587system.cpu1.dcache.WriteReq_accesses::cpu1.data 66631172 # number of WriteReq accesses(hits+misses) 1588system.cpu1.dcache.WriteReq_accesses::total 66631172 # number of WriteReq accesses(hits+misses) 1589system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 764711 # number of SoftPFReq accesses(hits+misses) 1590system.cpu1.dcache.SoftPFReq_accesses::total 764711 # number of SoftPFReq accesses(hits+misses) 1591system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 486364 # number of WriteInvalidateReq accesses(hits+misses) 1592system.cpu1.dcache.WriteInvalidateReq_accesses::total 486364 # number of WriteInvalidateReq accesses(hits+misses) 1593system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1843162 # number of LoadLockedReq accesses(hits+misses) 1594system.cpu1.dcache.LoadLockedReq_accesses::total 1843162 # number of LoadLockedReq accesses(hits+misses) 1595system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1841789 # number of StoreCondReq accesses(hits+misses) 1596system.cpu1.dcache.StoreCondReq_accesses::total 1841789 # number of StoreCondReq accesses(hits+misses) 1597system.cpu1.dcache.demand_accesses::cpu1.data 143650320 # number of demand (read+write) accesses 1598system.cpu1.dcache.demand_accesses::total 143650320 # number of demand (read+write) accesses 1599system.cpu1.dcache.overall_accesses::cpu1.data 144415031 # number of overall (read+write) accesses 1600system.cpu1.dcache.overall_accesses::total 144415031 # number of overall (read+write) accesses 1601system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.040549 # miss rate for ReadReq accesses 1602system.cpu1.dcache.ReadReq_miss_rate::total 0.040549 # miss rate for ReadReq accesses 1603system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030043 # miss rate for WriteReq accesses 1604system.cpu1.dcache.WriteReq_miss_rate::total 0.030043 # miss rate for WriteReq accesses 1605system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.732466 # miss rate for SoftPFReq accesses 1606system.cpu1.dcache.SoftPFReq_miss_rate::total 0.732466 # miss rate for SoftPFReq accesses 1607system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.860907 # miss rate for WriteInvalidateReq accesses 1608system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.860907 # miss rate for WriteInvalidateReq accesses 1609system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086209 # miss rate for LoadLockedReq accesses 1610system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086209 # miss rate for LoadLockedReq accesses 1611system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.101993 # miss rate for StoreCondReq accesses 1612system.cpu1.dcache.StoreCondReq_miss_rate::total 0.101993 # miss rate for StoreCondReq accesses 1613system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035676 # miss rate for demand accesses 1614system.cpu1.dcache.demand_miss_rate::total 0.035676 # miss rate for demand accesses 1615system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039365 # miss rate for overall accesses 1616system.cpu1.dcache.overall_miss_rate::total 0.039365 # miss rate for overall accesses 1617system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14088.155339 # average ReadReq miss latency 1618system.cpu1.dcache.ReadReq_avg_miss_latency::total 14088.155339 # average ReadReq miss latency 1619system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17146.534791 # average WriteReq miss latency 1620system.cpu1.dcache.WriteReq_avg_miss_latency::total 17146.534791 # average WriteReq miss latency 1621system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 27039.082964 # average WriteInvalidateReq miss latency 1622system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 27039.082964 # average WriteInvalidateReq miss latency 1623system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14650.314762 # average LoadLockedReq miss latency 1624system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14650.314762 # average LoadLockedReq miss latency 1625system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20929.074704 # average StoreCondReq miss latency 1626system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20929.074704 # average StoreCondReq miss latency 1627system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1628system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1629system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15282.775722 # average overall miss latency 1630system.cpu1.dcache.demand_avg_miss_latency::total 15282.775722 # average overall miss latency 1631system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13777.003348 # average overall miss latency 1632system.cpu1.dcache.overall_avg_miss_latency::total 13777.003348 # average overall miss latency 1633system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1634system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1635system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1636system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1637system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1638system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1639system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1640system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1641system.cpu1.dcache.writebacks::writebacks 3038485 # number of writebacks 1642system.cpu1.dcache.writebacks::total 3038485 # number of writebacks 1643system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 341138 # number of ReadReq MSHR hits 1644system.cpu1.dcache.ReadReq_mshr_hits::total 341138 # number of ReadReq MSHR hits 1645system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 817934 # number of WriteReq MSHR hits 1646system.cpu1.dcache.WriteReq_mshr_hits::total 817934 # number of WriteReq MSHR hits 1647system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 47 # number of WriteInvalidateReq MSHR hits 1648system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 47 # number of WriteInvalidateReq MSHR hits 1649system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 39869 # number of LoadLockedReq MSHR hits 1650system.cpu1.dcache.LoadLockedReq_mshr_hits::total 39869 # number of LoadLockedReq MSHR hits 1651system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 63 # number of StoreCondReq MSHR hits 1652system.cpu1.dcache.StoreCondReq_mshr_hits::total 63 # number of StoreCondReq MSHR hits 1653system.cpu1.dcache.demand_mshr_hits::cpu1.data 1159072 # number of demand (read+write) MSHR hits 1654system.cpu1.dcache.demand_mshr_hits::total 1159072 # number of demand (read+write) MSHR hits 1655system.cpu1.dcache.overall_mshr_hits::cpu1.data 1159072 # number of overall MSHR hits 1656system.cpu1.dcache.overall_mshr_hits::total 1159072 # number of overall MSHR hits 1657system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2781911 # number of ReadReq MSHR misses 1658system.cpu1.dcache.ReadReq_mshr_misses::total 2781911 # number of ReadReq MSHR misses 1659system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1183858 # number of WriteReq MSHR misses 1660system.cpu1.dcache.WriteReq_mshr_misses::total 1183858 # number of WriteReq MSHR misses 1661system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 559909 # number of SoftPFReq MSHR misses 1662system.cpu1.dcache.SoftPFReq_mshr_misses::total 559909 # number of SoftPFReq MSHR misses 1663system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 418667 # number of WriteInvalidateReq MSHR misses 1664system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 418667 # number of WriteInvalidateReq MSHR misses 1665system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 119029 # number of LoadLockedReq MSHR misses 1666system.cpu1.dcache.LoadLockedReq_mshr_misses::total 119029 # number of LoadLockedReq MSHR misses 1667system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 187786 # number of StoreCondReq MSHR misses 1668system.cpu1.dcache.StoreCondReq_mshr_misses::total 187786 # number of StoreCondReq MSHR misses 1669system.cpu1.dcache.demand_mshr_misses::cpu1.data 3965769 # number of demand (read+write) MSHR misses 1670system.cpu1.dcache.demand_mshr_misses::total 3965769 # number of demand (read+write) MSHR misses 1671system.cpu1.dcache.overall_mshr_misses::cpu1.data 4525678 # number of overall MSHR misses 1672system.cpu1.dcache.overall_mshr_misses::total 4525678 # number of overall MSHR misses 1673system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5083 # number of ReadReq MSHR uncacheable 1674system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5083 # number of ReadReq MSHR uncacheable 1675system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5087 # number of WriteReq MSHR uncacheable 1676system.cpu1.dcache.WriteReq_mshr_uncacheable::total 5087 # number of WriteReq MSHR uncacheable 1677system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10170 # number of overall MSHR uncacheable misses 1678system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10170 # number of overall MSHR uncacheable misses 1679system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 34163110205 # number of ReadReq MSHR miss cycles 1680system.cpu1.dcache.ReadReq_mshr_miss_latency::total 34163110205 # number of ReadReq MSHR miss cycles 1681system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 18897365962 # number of WriteReq MSHR miss cycles 1682system.cpu1.dcache.WriteReq_mshr_miss_latency::total 18897365962 # number of WriteReq MSHR miss cycles 1683system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 10922522145 # number of SoftPFReq MSHR miss cycles 1684system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 10922522145 # number of SoftPFReq MSHR miss cycles 1685system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 10687856416 # number of WriteInvalidateReq MSHR miss cycles 1686system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 10687856416 # number of WriteInvalidateReq MSHR miss cycles 1687system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1507570159 # number of LoadLockedReq MSHR miss cycles 1688system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1507570159 # number of LoadLockedReq MSHR miss cycles 1689system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3640144702 # number of StoreCondReq MSHR miss cycles 1690system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3640144702 # number of StoreCondReq MSHR miss cycles 1691system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2571500 # number of StoreCondFailReq MSHR miss cycles 1692system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2571500 # number of StoreCondFailReq MSHR miss cycles 1693system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 53060476167 # number of demand (read+write) MSHR miss cycles 1694system.cpu1.dcache.demand_mshr_miss_latency::total 53060476167 # number of demand (read+write) MSHR miss cycles 1695system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 63982998312 # number of overall MSHR miss cycles 1696system.cpu1.dcache.overall_mshr_miss_latency::total 63982998312 # number of overall MSHR miss cycles 1697system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 518115500 # number of ReadReq MSHR uncacheable cycles 1698system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 518115500 # number of ReadReq MSHR uncacheable cycles 1699system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 583373999 # number of WriteReq MSHR uncacheable cycles 1700system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 583373999 # number of WriteReq MSHR uncacheable cycles 1701system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1101489499 # number of overall MSHR uncacheable cycles 1702system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1101489499 # number of overall MSHR uncacheable cycles 1703system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036120 # mshr miss rate for ReadReq accesses 1704system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036120 # mshr miss rate for ReadReq accesses 1705system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017767 # mshr miss rate for WriteReq accesses 1706system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017767 # mshr miss rate for WriteReq accesses 1707system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.732184 # mshr miss rate for SoftPFReq accesses 1708system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.732184 # mshr miss rate for SoftPFReq accesses 1709system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.860810 # mshr miss rate for WriteInvalidateReq accesses 1710system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.860810 # mshr miss rate for WriteInvalidateReq accesses 1711system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064579 # mshr miss rate for LoadLockedReq accesses 1712system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064579 # mshr miss rate for LoadLockedReq accesses 1713system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101958 # mshr miss rate for StoreCondReq accesses 1714system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101958 # mshr miss rate for StoreCondReq accesses 1715system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027607 # mshr miss rate for demand accesses 1716system.cpu1.dcache.demand_mshr_miss_rate::total 0.027607 # mshr miss rate for demand accesses 1717system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031338 # mshr miss rate for overall accesses 1718system.cpu1.dcache.overall_mshr_miss_rate::total 0.031338 # mshr miss rate for overall accesses 1719system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12280.446860 # average ReadReq mshr miss latency 1720system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12280.446860 # average ReadReq mshr miss latency 1721system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15962.527568 # average WriteReq mshr miss latency 1722system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15962.527568 # average WriteReq mshr miss latency 1723system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19507.673827 # average SoftPFReq mshr miss latency 1724system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19507.673827 # average SoftPFReq mshr miss latency 1725system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 25528.299140 # average WriteInvalidateReq mshr miss latency 1726system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25528.299140 # average WriteInvalidateReq mshr miss latency 1727system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12665.570231 # average LoadLockedReq mshr miss latency 1728system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12665.570231 # average LoadLockedReq mshr miss latency 1729system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19384.537197 # average StoreCondReq mshr miss latency 1730system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19384.537197 # average StoreCondReq mshr miss latency 1731system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1732system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1733system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13379.618472 # average overall mshr miss latency 1734system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13379.618472 # average overall mshr miss latency 1735system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14137.770807 # average overall mshr miss latency 1736system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14137.770807 # average overall mshr miss latency 1737system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 101931.044659 # average ReadReq mshr uncacheable latency 1738system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 101931.044659 # average ReadReq mshr uncacheable latency 1739system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 114679.378612 # average WriteReq mshr uncacheable latency 1740system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 114679.378612 # average WriteReq mshr uncacheable latency 1741system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 108307.718682 # average overall mshr uncacheable latency 1742system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 108307.718682 # average overall mshr uncacheable latency 1743system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1744system.cpu1.icache.tags.replacements 8549825 # number of replacements 1745system.cpu1.icache.tags.tagsinuse 507.203595 # Cycle average of tags in use 1746system.cpu1.icache.tags.total_refs 211942190 # Total number of references to valid blocks. 1747system.cpu1.icache.tags.sampled_refs 8550337 # Sample count of references to valid blocks. 1748system.cpu1.icache.tags.avg_refs 24.787583 # Average number of references to valid blocks. 1749system.cpu1.icache.tags.warmup_cycle 8370006207500 # Cycle when the warmup percentage was hit. 1750system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.203595 # Average occupied blocks per requestor 1751system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990632 # Average percentage of cache occupancy 1752system.cpu1.icache.tags.occ_percent::total 0.990632 # Average percentage of cache occupancy 1753system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1754system.cpu1.icache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id 1755system.cpu1.icache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id 1756system.cpu1.icache.tags.age_task_id_blocks_1024::2 76 # Occupied blocks per task id 1757system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1758system.cpu1.icache.tags.tag_accesses 449535393 # Number of tag accesses 1759system.cpu1.icache.tags.data_accesses 449535393 # Number of data accesses 1760system.cpu1.icache.ReadReq_hits::cpu1.inst 211942190 # number of ReadReq hits 1761system.cpu1.icache.ReadReq_hits::total 211942190 # number of ReadReq hits 1762system.cpu1.icache.demand_hits::cpu1.inst 211942190 # number of demand (read+write) hits 1763system.cpu1.icache.demand_hits::total 211942190 # number of demand (read+write) hits 1764system.cpu1.icache.overall_hits::cpu1.inst 211942190 # number of overall hits 1765system.cpu1.icache.overall_hits::total 211942190 # number of overall hits 1766system.cpu1.icache.ReadReq_misses::cpu1.inst 8550338 # number of ReadReq misses 1767system.cpu1.icache.ReadReq_misses::total 8550338 # number of ReadReq misses 1768system.cpu1.icache.demand_misses::cpu1.inst 8550338 # number of demand (read+write) misses 1769system.cpu1.icache.demand_misses::total 8550338 # number of demand (read+write) misses 1770system.cpu1.icache.overall_misses::cpu1.inst 8550338 # number of overall misses 1771system.cpu1.icache.overall_misses::total 8550338 # number of overall misses 1772system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 84064963562 # number of ReadReq miss cycles 1773system.cpu1.icache.ReadReq_miss_latency::total 84064963562 # number of ReadReq miss cycles 1774system.cpu1.icache.demand_miss_latency::cpu1.inst 84064963562 # number of demand (read+write) miss cycles 1775system.cpu1.icache.demand_miss_latency::total 84064963562 # number of demand (read+write) miss cycles 1776system.cpu1.icache.overall_miss_latency::cpu1.inst 84064963562 # number of overall miss cycles 1777system.cpu1.icache.overall_miss_latency::total 84064963562 # number of overall miss cycles 1778system.cpu1.icache.ReadReq_accesses::cpu1.inst 220492528 # number of ReadReq accesses(hits+misses) 1779system.cpu1.icache.ReadReq_accesses::total 220492528 # number of ReadReq accesses(hits+misses) 1780system.cpu1.icache.demand_accesses::cpu1.inst 220492528 # number of demand (read+write) accesses 1781system.cpu1.icache.demand_accesses::total 220492528 # number of demand (read+write) accesses 1782system.cpu1.icache.overall_accesses::cpu1.inst 220492528 # number of overall (read+write) accesses 1783system.cpu1.icache.overall_accesses::total 220492528 # number of overall (read+write) accesses 1784system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.038778 # miss rate for ReadReq accesses 1785system.cpu1.icache.ReadReq_miss_rate::total 0.038778 # miss rate for ReadReq accesses 1786system.cpu1.icache.demand_miss_rate::cpu1.inst 0.038778 # miss rate for demand accesses 1787system.cpu1.icache.demand_miss_rate::total 0.038778 # miss rate for demand accesses 1788system.cpu1.icache.overall_miss_rate::cpu1.inst 0.038778 # miss rate for overall accesses 1789system.cpu1.icache.overall_miss_rate::total 0.038778 # miss rate for overall accesses 1790system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9831.770810 # average ReadReq miss latency 1791system.cpu1.icache.ReadReq_avg_miss_latency::total 9831.770810 # average ReadReq miss latency 1792system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9831.770810 # average overall miss latency 1793system.cpu1.icache.demand_avg_miss_latency::total 9831.770810 # average overall miss latency 1794system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9831.770810 # average overall miss latency 1795system.cpu1.icache.overall_avg_miss_latency::total 9831.770810 # average overall miss latency 1796system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1797system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1798system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1799system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1800system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1801system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1802system.cpu1.icache.fast_writes 0 # number of fast writes performed 1803system.cpu1.icache.cache_copies 0 # number of cache copies performed 1804system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8550338 # number of ReadReq MSHR misses 1805system.cpu1.icache.ReadReq_mshr_misses::total 8550338 # number of ReadReq MSHR misses 1806system.cpu1.icache.demand_mshr_misses::cpu1.inst 8550338 # number of demand (read+write) MSHR misses 1807system.cpu1.icache.demand_mshr_misses::total 8550338 # number of demand (read+write) MSHR misses 1808system.cpu1.icache.overall_mshr_misses::cpu1.inst 8550338 # number of overall MSHR misses 1809system.cpu1.icache.overall_mshr_misses::total 8550338 # number of overall MSHR misses 1810system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 90 # number of ReadReq MSHR uncacheable 1811system.cpu1.icache.ReadReq_mshr_uncacheable::total 90 # number of ReadReq MSHR uncacheable 1812system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 90 # number of overall MSHR uncacheable misses 1813system.cpu1.icache.overall_mshr_uncacheable_misses::total 90 # number of overall MSHR uncacheable misses 1814system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 75495426368 # number of ReadReq MSHR miss cycles 1815system.cpu1.icache.ReadReq_mshr_miss_latency::total 75495426368 # number of ReadReq MSHR miss cycles 1816system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 75495426368 # number of demand (read+write) MSHR miss cycles 1817system.cpu1.icache.demand_mshr_miss_latency::total 75495426368 # number of demand (read+write) MSHR miss cycles 1818system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 75495426368 # number of overall MSHR miss cycles 1819system.cpu1.icache.overall_mshr_miss_latency::total 75495426368 # number of overall MSHR miss cycles 1820system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8549000 # number of ReadReq MSHR uncacheable cycles 1821system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8549000 # number of ReadReq MSHR uncacheable cycles 1822system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8549000 # number of overall MSHR uncacheable cycles 1823system.cpu1.icache.overall_mshr_uncacheable_latency::total 8549000 # number of overall MSHR uncacheable cycles 1824system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.038778 # mshr miss rate for ReadReq accesses 1825system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.038778 # mshr miss rate for ReadReq accesses 1826system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.038778 # mshr miss rate for demand accesses 1827system.cpu1.icache.demand_mshr_miss_rate::total 0.038778 # mshr miss rate for demand accesses 1828system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.038778 # mshr miss rate for overall accesses 1829system.cpu1.icache.overall_mshr_miss_rate::total 0.038778 # mshr miss rate for overall accesses 1830system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8829.525379 # average ReadReq mshr miss latency 1831system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8829.525379 # average ReadReq mshr miss latency 1832system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8829.525379 # average overall mshr miss latency 1833system.cpu1.icache.demand_avg_mshr_miss_latency::total 8829.525379 # average overall mshr miss latency 1834system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8829.525379 # average overall mshr miss latency 1835system.cpu1.icache.overall_avg_mshr_miss_latency::total 8829.525379 # average overall mshr miss latency 1836system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 94988.888889 # average ReadReq mshr uncacheable latency 1837system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 94988.888889 # average ReadReq mshr uncacheable latency 1838system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 94988.888889 # average overall mshr uncacheable latency 1839system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 94988.888889 # average overall mshr uncacheable latency 1840system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1841system.cpu1.l2cache.prefetcher.num_hwpf_issued 6602862 # number of hwpf issued 1842system.cpu1.l2cache.prefetcher.pfIdentified 6604361 # number of prefetch candidates identified 1843system.cpu1.l2cache.prefetcher.pfBufferHit 1239 # number of redundant prefetches already in prefetch queue 1844system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1845system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1846system.cpu1.l2cache.prefetcher.pfSpanPage 840391 # number of prefetches not generated due to page crossing 1847system.cpu1.l2cache.tags.replacements 2149670 # number of replacements 1848system.cpu1.l2cache.tags.tagsinuse 13538.161783 # Cycle average of tags in use 1849system.cpu1.l2cache.tags.total_refs 13667574 # Total number of references to valid blocks. 1850system.cpu1.l2cache.tags.sampled_refs 2165890 # Sample count of references to valid blocks. 1851system.cpu1.l2cache.tags.avg_refs 6.310373 # Average number of references to valid blocks. 1852system.cpu1.l2cache.tags.warmup_cycle 9806309103500 # Cycle when the warmup percentage was hit. 1853system.cpu1.l2cache.tags.occ_blocks::writebacks 5443.099185 # Average occupied blocks per requestor 1854system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 82.941597 # Average occupied blocks per requestor 1855system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 88.885416 # Average occupied blocks per requestor 1856system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3832.023077 # Average occupied blocks per requestor 1857system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3147.321084 # Average occupied blocks per requestor 1858system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 943.891423 # Average occupied blocks per requestor 1859system.cpu1.l2cache.tags.occ_percent::writebacks 0.332220 # Average percentage of cache occupancy 1860system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.005062 # Average percentage of cache occupancy 1861system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005425 # Average percentage of cache occupancy 1862system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.233888 # Average percentage of cache occupancy 1863system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.192097 # Average percentage of cache occupancy 1864system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.057611 # Average percentage of cache occupancy 1865system.cpu1.l2cache.tags.occ_percent::total 0.826304 # Average percentage of cache occupancy 1866system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1444 # Occupied blocks per task id 1867system.cpu1.l2cache.tags.occ_task_id_blocks::1023 51 # Occupied blocks per task id 1868system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14725 # Occupied blocks per task id 1869system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 21 # Occupied blocks per task id 1870system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 436 # Occupied blocks per task id 1871system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 846 # Occupied blocks per task id 1872system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 141 # Occupied blocks per task id 1873system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id 1874system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 24 # Occupied blocks per task id 1875system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 24 # Occupied blocks per task id 1876system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id 1877system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id 1878system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1094 # Occupied blocks per task id 1879system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5482 # Occupied blocks per task id 1880system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7066 # Occupied blocks per task id 1881system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 978 # Occupied blocks per task id 1882system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.088135 # Percentage of cache occupancy per task id 1883system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003113 # Percentage of cache occupancy per task id 1884system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.898743 # Percentage of cache occupancy per task id 1885system.cpu1.l2cache.tags.tag_accesses 283341479 # Number of tag accesses 1886system.cpu1.l2cache.tags.data_accesses 283341479 # Number of data accesses 1887system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 455761 # number of ReadReq hits 1888system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 138301 # number of ReadReq hits 1889system.cpu1.l2cache.ReadReq_hits::cpu1.inst 7823529 # number of ReadReq hits 1890system.cpu1.l2cache.ReadReq_hits::cpu1.data 2545685 # number of ReadReq hits 1891system.cpu1.l2cache.ReadReq_hits::total 10963276 # number of ReadReq hits 1892system.cpu1.l2cache.Writeback_hits::writebacks 3038484 # number of Writeback hits 1893system.cpu1.l2cache.Writeback_hits::total 3038484 # number of Writeback hits 1894system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 176317 # number of WriteInvalidateReq hits 1895system.cpu1.l2cache.WriteInvalidateReq_hits::total 176317 # number of WriteInvalidateReq hits 1896system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 59890 # number of UpgradeReq hits 1897system.cpu1.l2cache.UpgradeReq_hits::total 59890 # number of UpgradeReq hits 1898system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 34545 # number of SCUpgradeReq hits 1899system.cpu1.l2cache.SCUpgradeReq_hits::total 34545 # number of SCUpgradeReq hits 1900system.cpu1.l2cache.ReadExReq_hits::cpu1.data 755491 # number of ReadExReq hits 1901system.cpu1.l2cache.ReadExReq_hits::total 755491 # number of ReadExReq hits 1902system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 455761 # number of demand (read+write) hits 1903system.cpu1.l2cache.demand_hits::cpu1.itb.walker 138301 # number of demand (read+write) hits 1904system.cpu1.l2cache.demand_hits::cpu1.inst 7823529 # number of demand (read+write) hits 1905system.cpu1.l2cache.demand_hits::cpu1.data 3301176 # number of demand (read+write) hits 1906system.cpu1.l2cache.demand_hits::total 11718767 # number of demand (read+write) hits 1907system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 455761 # number of overall hits 1908system.cpu1.l2cache.overall_hits::cpu1.itb.walker 138301 # number of overall hits 1909system.cpu1.l2cache.overall_hits::cpu1.inst 7823529 # number of overall hits 1910system.cpu1.l2cache.overall_hits::cpu1.data 3301176 # number of overall hits 1911system.cpu1.l2cache.overall_hits::total 11718767 # number of overall hits 1912system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11008 # number of ReadReq misses 1913system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7757 # number of ReadReq misses 1914system.cpu1.l2cache.ReadReq_misses::cpu1.inst 726809 # number of ReadReq misses 1915system.cpu1.l2cache.ReadReq_misses::cpu1.data 914890 # number of ReadReq misses 1916system.cpu1.l2cache.ReadReq_misses::total 1660464 # number of ReadReq misses 1917system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 241215 # number of WriteInvalidateReq misses 1918system.cpu1.l2cache.WriteInvalidateReq_misses::total 241215 # number of WriteInvalidateReq misses 1919system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 139061 # number of UpgradeReq misses 1920system.cpu1.l2cache.UpgradeReq_misses::total 139061 # number of UpgradeReq misses 1921system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 153238 # number of SCUpgradeReq misses 1922system.cpu1.l2cache.SCUpgradeReq_misses::total 153238 # number of SCUpgradeReq misses 1923system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses 1924system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses 1925system.cpu1.l2cache.ReadExReq_misses::cpu1.data 230973 # number of ReadExReq misses 1926system.cpu1.l2cache.ReadExReq_misses::total 230973 # number of ReadExReq misses 1927system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11008 # number of demand (read+write) misses 1928system.cpu1.l2cache.demand_misses::cpu1.itb.walker 7757 # number of demand (read+write) misses 1929system.cpu1.l2cache.demand_misses::cpu1.inst 726809 # number of demand (read+write) misses 1930system.cpu1.l2cache.demand_misses::cpu1.data 1145863 # number of demand (read+write) misses 1931system.cpu1.l2cache.demand_misses::total 1891437 # number of demand (read+write) misses 1932system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11008 # number of overall misses 1933system.cpu1.l2cache.overall_misses::cpu1.itb.walker 7757 # number of overall misses 1934system.cpu1.l2cache.overall_misses::cpu1.inst 726809 # number of overall misses 1935system.cpu1.l2cache.overall_misses::cpu1.data 1145863 # number of overall misses 1936system.cpu1.l2cache.overall_misses::total 1891437 # number of overall misses 1937system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 327528752 # number of ReadReq miss cycles 1938system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 257164513 # number of ReadReq miss cycles 1939system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 20327901458 # number of ReadReq miss cycles 1940system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 26467087148 # number of ReadReq miss cycles 1941system.cpu1.l2cache.ReadReq_miss_latency::total 47379681871 # number of ReadReq miss cycles 1942system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 239660388 # number of WriteInvalidateReq miss cycles 1943system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 239660388 # number of WriteInvalidateReq miss cycles 1944system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3007716761 # number of UpgradeReq miss cycles 1945system.cpu1.l2cache.UpgradeReq_miss_latency::total 3007716761 # number of UpgradeReq miss cycles 1946system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3151750139 # number of SCUpgradeReq miss cycles 1947system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3151750139 # number of SCUpgradeReq miss cycles 1948system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2513499 # number of SCUpgradeFailReq miss cycles 1949system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2513499 # number of SCUpgradeFailReq miss cycles 1950system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 8819162910 # number of ReadExReq miss cycles 1951system.cpu1.l2cache.ReadExReq_miss_latency::total 8819162910 # number of ReadExReq miss cycles 1952system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 327528752 # number of demand (read+write) miss cycles 1953system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 257164513 # number of demand (read+write) miss cycles 1954system.cpu1.l2cache.demand_miss_latency::cpu1.inst 20327901458 # number of demand (read+write) miss cycles 1955system.cpu1.l2cache.demand_miss_latency::cpu1.data 35286250058 # number of demand (read+write) miss cycles 1956system.cpu1.l2cache.demand_miss_latency::total 56198844781 # number of demand (read+write) miss cycles 1957system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 327528752 # number of overall miss cycles 1958system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 257164513 # number of overall miss cycles 1959system.cpu1.l2cache.overall_miss_latency::cpu1.inst 20327901458 # number of overall miss cycles 1960system.cpu1.l2cache.overall_miss_latency::cpu1.data 35286250058 # number of overall miss cycles 1961system.cpu1.l2cache.overall_miss_latency::total 56198844781 # number of overall miss cycles 1962system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 466769 # number of ReadReq accesses(hits+misses) 1963system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 146058 # number of ReadReq accesses(hits+misses) 1964system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 8550338 # number of ReadReq accesses(hits+misses) 1965system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3460575 # number of ReadReq accesses(hits+misses) 1966system.cpu1.l2cache.ReadReq_accesses::total 12623740 # number of ReadReq accesses(hits+misses) 1967system.cpu1.l2cache.Writeback_accesses::writebacks 3038484 # number of Writeback accesses(hits+misses) 1968system.cpu1.l2cache.Writeback_accesses::total 3038484 # number of Writeback accesses(hits+misses) 1969system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 417532 # number of WriteInvalidateReq accesses(hits+misses) 1970system.cpu1.l2cache.WriteInvalidateReq_accesses::total 417532 # number of WriteInvalidateReq accesses(hits+misses) 1971system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 198951 # number of UpgradeReq accesses(hits+misses) 1972system.cpu1.l2cache.UpgradeReq_accesses::total 198951 # number of UpgradeReq accesses(hits+misses) 1973system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 187783 # number of SCUpgradeReq accesses(hits+misses) 1974system.cpu1.l2cache.SCUpgradeReq_accesses::total 187783 # number of SCUpgradeReq accesses(hits+misses) 1975system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses) 1976system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) 1977system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 986464 # number of ReadExReq accesses(hits+misses) 1978system.cpu1.l2cache.ReadExReq_accesses::total 986464 # number of ReadExReq accesses(hits+misses) 1979system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 466769 # number of demand (read+write) accesses 1980system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 146058 # number of demand (read+write) accesses 1981system.cpu1.l2cache.demand_accesses::cpu1.inst 8550338 # number of demand (read+write) accesses 1982system.cpu1.l2cache.demand_accesses::cpu1.data 4447039 # number of demand (read+write) accesses 1983system.cpu1.l2cache.demand_accesses::total 13610204 # number of demand (read+write) accesses 1984system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 466769 # number of overall (read+write) accesses 1985system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 146058 # number of overall (read+write) accesses 1986system.cpu1.l2cache.overall_accesses::cpu1.inst 8550338 # number of overall (read+write) accesses 1987system.cpu1.l2cache.overall_accesses::cpu1.data 4447039 # number of overall (read+write) accesses 1988system.cpu1.l2cache.overall_accesses::total 13610204 # number of overall (read+write) accesses 1989system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.023583 # miss rate for ReadReq accesses 1990system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.053109 # miss rate for ReadReq accesses 1991system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.085004 # miss rate for ReadReq accesses 1992system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.264375 # miss rate for ReadReq accesses 1993system.cpu1.l2cache.ReadReq_miss_rate::total 0.131535 # miss rate for ReadReq accesses 1994system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.577716 # miss rate for WriteInvalidateReq accesses 1995system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.577716 # miss rate for WriteInvalidateReq accesses 1996system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.698971 # miss rate for UpgradeReq accesses 1997system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.698971 # miss rate for UpgradeReq accesses 1998system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.816038 # miss rate for SCUpgradeReq accesses 1999system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.816038 # miss rate for SCUpgradeReq accesses 2000system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2001system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2002system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.234142 # miss rate for ReadExReq accesses 2003system.cpu1.l2cache.ReadExReq_miss_rate::total 0.234142 # miss rate for ReadExReq accesses 2004system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.023583 # miss rate for demand accesses 2005system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.053109 # miss rate for demand accesses 2006system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.085004 # miss rate for demand accesses 2007system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.257669 # miss rate for demand accesses 2008system.cpu1.l2cache.demand_miss_rate::total 0.138972 # miss rate for demand accesses 2009system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.023583 # miss rate for overall accesses 2010system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.053109 # miss rate for overall accesses 2011system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.085004 # miss rate for overall accesses 2012system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.257669 # miss rate for overall accesses 2013system.cpu1.l2cache.overall_miss_rate::total 0.138972 # miss rate for overall accesses 2014system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 29753.702035 # average ReadReq miss latency 2015system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 33152.573546 # average ReadReq miss latency 2016system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 27968.698046 # average ReadReq miss latency 2017system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 28929.256138 # average ReadReq miss latency 2018system.cpu1.l2cache.ReadReq_avg_miss_latency::total 28534.001262 # average ReadReq miss latency 2019system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 993.555077 # average WriteInvalidateReq miss latency 2020system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 993.555077 # average WriteInvalidateReq miss latency 2021system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21628.758322 # average UpgradeReq miss latency 2022system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21628.758322 # average UpgradeReq miss latency 2023system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20567.679942 # average SCUpgradeReq miss latency 2024system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20567.679942 # average SCUpgradeReq miss latency 2025system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 837833 # average SCUpgradeFailReq miss latency 2026system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 837833 # average SCUpgradeFailReq miss latency 2027system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38182.657324 # average ReadExReq miss latency 2028system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38182.657324 # average ReadExReq miss latency 2029system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 29753.702035 # average overall miss latency 2030system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 33152.573546 # average overall miss latency 2031system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 27968.698046 # average overall miss latency 2032system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 30794.475481 # average overall miss latency 2033system.cpu1.l2cache.demand_avg_miss_latency::total 29712.247768 # average overall miss latency 2034system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 29753.702035 # average overall miss latency 2035system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 33152.573546 # average overall miss latency 2036system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 27968.698046 # average overall miss latency 2037system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 30794.475481 # average overall miss latency 2038system.cpu1.l2cache.overall_avg_miss_latency::total 29712.247768 # average overall miss latency 2039system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2040system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2041system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2042system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2043system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2044system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2045system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2046system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 2047system.cpu1.l2cache.writebacks::writebacks 875308 # number of writebacks 2048system.cpu1.l2cache.writebacks::total 875308 # number of writebacks 2049system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 1 # number of ReadReq MSHR hits 2050system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 3 # number of ReadReq MSHR hits 2051system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 523 # number of ReadReq MSHR hits 2052system.cpu1.l2cache.ReadReq_mshr_hits::total 527 # number of ReadReq MSHR hits 2053system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data 9 # number of WriteInvalidateReq MSHR hits 2054system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total 9 # number of WriteInvalidateReq MSHR hits 2055system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 3864 # number of ReadExReq MSHR hits 2056system.cpu1.l2cache.ReadExReq_mshr_hits::total 3864 # number of ReadExReq MSHR hits 2057system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 1 # number of demand (read+write) MSHR hits 2058system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits 2059system.cpu1.l2cache.demand_mshr_hits::cpu1.data 4387 # number of demand (read+write) MSHR hits 2060system.cpu1.l2cache.demand_mshr_hits::total 4391 # number of demand (read+write) MSHR hits 2061system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 1 # number of overall MSHR hits 2062system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits 2063system.cpu1.l2cache.overall_mshr_hits::cpu1.data 4387 # number of overall MSHR hits 2064system.cpu1.l2cache.overall_mshr_hits::total 4391 # number of overall MSHR hits 2065system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 11008 # number of ReadReq MSHR misses 2066system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 7756 # number of ReadReq MSHR misses 2067system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 726806 # number of ReadReq MSHR misses 2068system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 914367 # number of ReadReq MSHR misses 2069system.cpu1.l2cache.ReadReq_mshr_misses::total 1659937 # number of ReadReq MSHR misses 2070system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 617005 # number of HardPFReq MSHR misses 2071system.cpu1.l2cache.HardPFReq_mshr_misses::total 617005 # number of HardPFReq MSHR misses 2072system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 241206 # number of WriteInvalidateReq MSHR misses 2073system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 241206 # number of WriteInvalidateReq MSHR misses 2074system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 139061 # number of UpgradeReq MSHR misses 2075system.cpu1.l2cache.UpgradeReq_mshr_misses::total 139061 # number of UpgradeReq MSHR misses 2076system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 153238 # number of SCUpgradeReq MSHR misses 2077system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 153238 # number of SCUpgradeReq MSHR misses 2078system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses 2079system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses 2080system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 227109 # number of ReadExReq MSHR misses 2081system.cpu1.l2cache.ReadExReq_mshr_misses::total 227109 # number of ReadExReq MSHR misses 2082system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 11008 # number of demand (read+write) MSHR misses 2083system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 7756 # number of demand (read+write) MSHR misses 2084system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 726806 # number of demand (read+write) MSHR misses 2085system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1141476 # number of demand (read+write) MSHR misses 2086system.cpu1.l2cache.demand_mshr_misses::total 1887046 # number of demand (read+write) MSHR misses 2087system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 11008 # number of overall MSHR misses 2088system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 7756 # number of overall MSHR misses 2089system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 726806 # number of overall MSHR misses 2090system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1141476 # number of overall MSHR misses 2091system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 617005 # number of overall MSHR misses 2092system.cpu1.l2cache.overall_mshr_misses::total 2504051 # number of overall MSHR misses 2093system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 90 # number of ReadReq MSHR uncacheable 2094system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 5083 # number of ReadReq MSHR uncacheable 2095system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 5173 # number of ReadReq MSHR uncacheable 2096system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 5087 # number of WriteReq MSHR uncacheable 2097system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 5087 # number of WriteReq MSHR uncacheable 2098system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 90 # number of overall MSHR uncacheable misses 2099system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10170 # number of overall MSHR uncacheable misses 2100system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10260 # number of overall MSHR uncacheable misses 2101system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 255658756 # number of ReadReq MSHR miss cycles 2102system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 206438003 # number of ReadReq MSHR miss cycles 2103system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 15587531792 # number of ReadReq MSHR miss cycles 2104system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 20464504451 # number of ReadReq MSHR miss cycles 2105system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 36514133002 # number of ReadReq MSHR miss cycles 2106system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 19899573281 # number of HardPFReq MSHR miss cycles 2107system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 19899573281 # number of HardPFReq MSHR miss cycles 2108system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 7445733077 # number of WriteInvalidateReq MSHR miss cycles 2109system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 7445733077 # number of WriteInvalidateReq MSHR miss cycles 2110system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2687293206 # number of UpgradeReq MSHR miss cycles 2111system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2687293206 # number of UpgradeReq MSHR miss cycles 2112system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2230899638 # number of SCUpgradeReq MSHR miss cycles 2113system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2230899638 # number of SCUpgradeReq MSHR miss cycles 2114system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2142999 # number of SCUpgradeFailReq MSHR miss cycles 2115system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2142999 # number of SCUpgradeFailReq MSHR miss cycles 2116system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 6831385140 # number of ReadExReq MSHR miss cycles 2117system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 6831385140 # number of ReadExReq MSHR miss cycles 2118system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 255658756 # number of demand (read+write) MSHR miss cycles 2119system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 206438003 # number of demand (read+write) MSHR miss cycles 2120system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 15587531792 # number of demand (read+write) MSHR miss cycles 2121system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 27295889591 # number of demand (read+write) MSHR miss cycles 2122system.cpu1.l2cache.demand_mshr_miss_latency::total 43345518142 # number of demand (read+write) MSHR miss cycles 2123system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 255658756 # number of overall MSHR miss cycles 2124system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 206438003 # number of overall MSHR miss cycles 2125system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 15587531792 # number of overall MSHR miss cycles 2126system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 27295889591 # number of overall MSHR miss cycles 2127system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 19899573281 # number of overall MSHR miss cycles 2128system.cpu1.l2cache.overall_mshr_miss_latency::total 63245091423 # number of overall MSHR miss cycles 2129system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7792000 # number of ReadReq MSHR uncacheable cycles 2130system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 477441500 # number of ReadReq MSHR uncacheable cycles 2131system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 485233500 # number of ReadReq MSHR uncacheable cycles 2132system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 545217001 # number of WriteReq MSHR uncacheable cycles 2133system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 545217001 # number of WriteReq MSHR uncacheable cycles 2134system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7792000 # number of overall MSHR uncacheable cycles 2135system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1022658501 # number of overall MSHR uncacheable cycles 2136system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1030450501 # number of overall MSHR uncacheable cycles 2137system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023583 # mshr miss rate for ReadReq accesses 2138system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.053102 # mshr miss rate for ReadReq accesses 2139system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.085003 # mshr miss rate for ReadReq accesses 2140system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.264224 # mshr miss rate for ReadReq accesses 2141system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.131493 # mshr miss rate for ReadReq accesses 2142system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2143system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2144system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.577695 # mshr miss rate for WriteInvalidateReq accesses 2145system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.577695 # mshr miss rate for WriteInvalidateReq accesses 2146system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.698971 # mshr miss rate for UpgradeReq accesses 2147system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.698971 # mshr miss rate for UpgradeReq accesses 2148system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.816038 # mshr miss rate for SCUpgradeReq accesses 2149system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.816038 # mshr miss rate for SCUpgradeReq accesses 2150system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2151system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2152system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.230225 # mshr miss rate for ReadExReq accesses 2153system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.230225 # mshr miss rate for ReadExReq accesses 2154system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023583 # mshr miss rate for demand accesses 2155system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.053102 # mshr miss rate for demand accesses 2156system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.085003 # mshr miss rate for demand accesses 2157system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.256682 # mshr miss rate for demand accesses 2158system.cpu1.l2cache.demand_mshr_miss_rate::total 0.138649 # mshr miss rate for demand accesses 2159system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023583 # mshr miss rate for overall accesses 2160system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.053102 # mshr miss rate for overall accesses 2161system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.085003 # mshr miss rate for overall accesses 2162system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.256682 # mshr miss rate for overall accesses 2163system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2164system.cpu1.l2cache.overall_mshr_miss_rate::total 0.183983 # mshr miss rate for overall accesses 2165system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 23224.814317 # average ReadReq mshr miss latency 2166system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 26616.555312 # average ReadReq mshr miss latency 2167system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21446.619582 # average ReadReq mshr miss latency 2168system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 22381.061927 # average ReadReq mshr miss latency 2169system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 21997.300501 # average ReadReq mshr miss latency 2170system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 32251.883341 # average HardPFReq mshr miss latency 2171system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 32251.883341 # average HardPFReq mshr miss latency 2172system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 30868.772240 # average WriteInvalidateReq mshr miss latency 2173system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 30868.772240 # average WriteInvalidateReq mshr miss latency 2174system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19324.564083 # average UpgradeReq mshr miss latency 2175system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19324.564083 # average UpgradeReq mshr miss latency 2176system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14558.396990 # average SCUpgradeReq mshr miss latency 2177system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14558.396990 # average SCUpgradeReq mshr miss latency 2178system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 714333 # average SCUpgradeFailReq mshr miss latency 2179system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 714333 # average SCUpgradeFailReq mshr miss latency 2180system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30079.764078 # average ReadExReq mshr miss latency 2181system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30079.764078 # average ReadExReq mshr miss latency 2182system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 23224.814317 # average overall mshr miss latency 2183system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 26616.555312 # average overall mshr miss latency 2184system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21446.619582 # average overall mshr miss latency 2185system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23912.802013 # average overall mshr miss latency 2186system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22970.037902 # average overall mshr miss latency 2187system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 23224.814317 # average overall mshr miss latency 2188system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 26616.555312 # average overall mshr miss latency 2189system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21446.619582 # average overall mshr miss latency 2190system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23912.802013 # average overall mshr miss latency 2191system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 32251.883341 # average overall mshr miss latency 2192system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25257.109948 # average overall mshr miss latency 2193system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86577.777778 # average ReadReq mshr uncacheable latency 2194system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 93929.077317 # average ReadReq mshr uncacheable latency 2195system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 93801.179200 # average ReadReq mshr uncacheable latency 2196system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 107178.494397 # average WriteReq mshr uncacheable latency 2197system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 107178.494397 # average WriteReq mshr uncacheable latency 2198system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86577.777778 # average overall mshr uncacheable latency 2199system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 100556.391445 # average overall mshr uncacheable latency 2200system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 100433.772027 # average overall mshr uncacheable latency 2201system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2202system.cpu1.toL2Bus.trans_dist::ReadReq 15242466 # Transaction distribution 2203system.cpu1.toL2Bus.trans_dist::ReadResp 12851003 # Transaction distribution 2204system.cpu1.toL2Bus.trans_dist::WriteReq 38250 # Transaction distribution 2205system.cpu1.toL2Bus.trans_dist::WriteResp 5087 # Transaction distribution 2206system.cpu1.toL2Bus.trans_dist::Writeback 3038484 # Transaction distribution 2207system.cpu1.toL2Bus.trans_dist::HardPFReq 900400 # Transaction distribution 2208system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1105427 # Transaction distribution 2209system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 417532 # Transaction distribution 2210system.cpu1.toL2Bus.trans_dist::UpgradeReq 439071 # Transaction distribution 2211system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 337307 # Transaction distribution 2212system.cpu1.toL2Bus.trans_dist::UpgradeResp 446846 # Transaction distribution 2213system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 71 # Transaction distribution 2214system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution 2215system.cpu1.toL2Bus.trans_dist::ReadExReq 1140783 # Transaction distribution 2216system.cpu1.toL2Bus.trans_dist::ReadExResp 991898 # Transaction distribution 2217system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17100855 # Packet count per connected master and slave (bytes) 2218system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 13710565 # Packet count per connected master and slave (bytes) 2219system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 326713 # Packet count per connected master and slave (bytes) 2220system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1037575 # Packet count per connected master and slave (bytes) 2221system.cpu1.toL2Bus.pkt_count::total 32175708 # Packet count per connected master and slave (bytes) 2222system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 547227328 # Cumulative packet size per connected master and slave (bytes) 2223system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 511521449 # Cumulative packet size per connected master and slave (bytes) 2224system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1168464 # Cumulative packet size per connected master and slave (bytes) 2225system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3734152 # Cumulative packet size per connected master and slave (bytes) 2226system.cpu1.toL2Bus.pkt_size::total 1063651393 # Cumulative packet size per connected master and slave (bytes) 2227system.cpu1.toL2Bus.snoops 4928167 # Total snoops (count) 2228system.cpu1.toL2Bus.snoop_fanout::samples 22242259 # Request fanout histogram 2229system.cpu1.toL2Bus.snoop_fanout::mean 1.242416 # Request fanout histogram 2230system.cpu1.toL2Bus.snoop_fanout::stdev 0.428544 # Request fanout histogram 2231system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2232system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2233system.cpu1.toL2Bus.snoop_fanout::1 16850390 75.76% 75.76% # Request fanout histogram 2234system.cpu1.toL2Bus.snoop_fanout::2 5391869 24.24% 100.00% # Request fanout histogram 2235system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2236system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 2237system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2238system.cpu1.toL2Bus.snoop_fanout::total 22242259 # Request fanout histogram 2239system.cpu1.toL2Bus.reqLayer0.occupancy 12259577677 # Layer occupancy (ticks) 2240system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2241system.cpu1.toL2Bus.snoopLayer0.occupancy 163507981 # Layer occupancy (ticks) 2242system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2243system.cpu1.toL2Bus.respLayer0.occupancy 12835259097 # Layer occupancy (ticks) 2244system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2245system.cpu1.toL2Bus.respLayer1.occupancy 7129308669 # Layer occupancy (ticks) 2246system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2247system.cpu1.toL2Bus.respLayer2.occupancy 180853196 # Layer occupancy (ticks) 2248system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2249system.cpu1.toL2Bus.respLayer3.occupancy 571040175 # Layer occupancy (ticks) 2250system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2251system.iobus.trans_dist::ReadReq 40383 # Transaction distribution 2252system.iobus.trans_dist::ReadResp 40383 # Transaction distribution 2253system.iobus.trans_dist::WriteReq 136956 # Transaction distribution 2254system.iobus.trans_dist::WriteResp 29972 # Transaction distribution 2255system.iobus.trans_dist::WriteInvalidateResp 106984 # Transaction distribution 2256system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47768 # Packet count per connected master and slave (bytes) 2257system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2258system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2259system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2260system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2261system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2262system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2263system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2264system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2265system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2266system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29756 # Packet count per connected master and slave (bytes) 2267system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2268system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 2269system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2270system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 2271system.iobus.pkt_count_system.bridge.master::total 122858 # Packet count per connected master and slave (bytes) 2272system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231740 # Packet count per connected master and slave (bytes) 2273system.iobus.pkt_count_system.realview.ide.dma::total 231740 # Packet count per connected master and slave (bytes) 2274system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2275system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 2276system.iobus.pkt_count::total 354678 # Packet count per connected master and slave (bytes) 2277system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47788 # Cumulative packet size per connected master and slave (bytes) 2278system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2279system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2280system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2281system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2282system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2283system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2284system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2285system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2286system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2287system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17674 # Cumulative packet size per connected master and slave (bytes) 2288system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 2289system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 2290system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 2291system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 2292system.iobus.pkt_size_system.bridge.master::total 155896 # Cumulative packet size per connected master and slave (bytes) 2293system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355312 # Cumulative packet size per connected master and slave (bytes) 2294system.iobus.pkt_size_system.realview.ide.dma::total 7355312 # Cumulative packet size per connected master and slave (bytes) 2295system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2296system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 2297system.iobus.pkt_size::total 7513294 # Cumulative packet size per connected master and slave (bytes) 2298system.iobus.reqLayer0.occupancy 36287000 # Layer occupancy (ticks) 2299system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2300system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 2301system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2302system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 2303system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2304system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 2305system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2306system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 2307system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2308system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 2309system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2310system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 2311system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2312system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 2313system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2314system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 2315system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2316system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 2317system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2318system.iobus.reqLayer23.occupancy 22103000 # Layer occupancy (ticks) 2319system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2320system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 2321system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2322system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 2323system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2324system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 2325system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 2326system.iobus.reqLayer27.occupancy 608916622 # Layer occupancy (ticks) 2327system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2328system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2329system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 2330system.iobus.respLayer0.occupancy 92889000 # Layer occupancy (ticks) 2331system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2332system.iobus.respLayer3.occupancy 148804483 # Layer occupancy (ticks) 2333system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2334system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks) 2335system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 2336system.iocache.tags.replacements 115850 # number of replacements 2337system.iocache.tags.tagsinuse 11.297267 # Cycle average of tags in use 2338system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 2339system.iocache.tags.sampled_refs 115866 # Sample count of references to valid blocks. 2340system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 2341system.iocache.tags.warmup_cycle 9129662020000 # Cycle when the warmup percentage was hit. 2342system.iocache.tags.occ_blocks::realview.ethernet 3.840346 # Average occupied blocks per requestor 2343system.iocache.tags.occ_blocks::realview.ide 7.456922 # Average occupied blocks per requestor 2344system.iocache.tags.occ_percent::realview.ethernet 0.240022 # Average percentage of cache occupancy 2345system.iocache.tags.occ_percent::realview.ide 0.466058 # Average percentage of cache occupancy 2346system.iocache.tags.occ_percent::total 0.706079 # Average percentage of cache occupancy 2347system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2348system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2349system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2350system.iocache.tags.tag_accesses 1043187 # Number of tag accesses 2351system.iocache.tags.data_accesses 1043187 # Number of data accesses 2352system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2353system.iocache.ReadReq_misses::realview.ide 8886 # number of ReadReq misses 2354system.iocache.ReadReq_misses::total 8923 # number of ReadReq misses 2355system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2356system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2357system.iocache.WriteInvalidateReq_misses::realview.ide 106984 # number of WriteInvalidateReq misses 2358system.iocache.WriteInvalidateReq_misses::total 106984 # number of WriteInvalidateReq misses 2359system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 2360system.iocache.demand_misses::realview.ide 8886 # number of demand (read+write) misses 2361system.iocache.demand_misses::total 8926 # number of demand (read+write) misses 2362system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 2363system.iocache.overall_misses::realview.ide 8886 # number of overall misses 2364system.iocache.overall_misses::total 8926 # number of overall misses 2365system.iocache.ReadReq_miss_latency::realview.ethernet 5219500 # number of ReadReq miss cycles 2366system.iocache.ReadReq_miss_latency::realview.ide 1645546182 # number of ReadReq miss cycles 2367system.iocache.ReadReq_miss_latency::total 1650765682 # number of ReadReq miss cycles 2368system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 2369system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 2370system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19952013957 # number of WriteInvalidateReq miss cycles 2371system.iocache.WriteInvalidateReq_miss_latency::total 19952013957 # number of WriteInvalidateReq miss cycles 2372system.iocache.demand_miss_latency::realview.ethernet 5588500 # number of demand (read+write) miss cycles 2373system.iocache.demand_miss_latency::realview.ide 1645546182 # number of demand (read+write) miss cycles 2374system.iocache.demand_miss_latency::total 1651134682 # number of demand (read+write) miss cycles 2375system.iocache.overall_miss_latency::realview.ethernet 5588500 # number of overall miss cycles 2376system.iocache.overall_miss_latency::realview.ide 1645546182 # number of overall miss cycles 2377system.iocache.overall_miss_latency::total 1651134682 # number of overall miss cycles 2378system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 2379system.iocache.ReadReq_accesses::realview.ide 8886 # number of ReadReq accesses(hits+misses) 2380system.iocache.ReadReq_accesses::total 8923 # number of ReadReq accesses(hits+misses) 2381system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2382system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2383system.iocache.WriteInvalidateReq_accesses::realview.ide 106984 # number of WriteInvalidateReq accesses(hits+misses) 2384system.iocache.WriteInvalidateReq_accesses::total 106984 # number of WriteInvalidateReq accesses(hits+misses) 2385system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 2386system.iocache.demand_accesses::realview.ide 8886 # number of demand (read+write) accesses 2387system.iocache.demand_accesses::total 8926 # number of demand (read+write) accesses 2388system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 2389system.iocache.overall_accesses::realview.ide 8886 # number of overall (read+write) accesses 2390system.iocache.overall_accesses::total 8926 # number of overall (read+write) accesses 2391system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2392system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2393system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2394system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2395system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2396system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 2397system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 2398system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2399system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2400system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2401system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2402system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2403system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2404system.iocache.ReadReq_avg_miss_latency::realview.ethernet 141067.567568 # average ReadReq miss latency 2405system.iocache.ReadReq_avg_miss_latency::realview.ide 185184.130317 # average ReadReq miss latency 2406system.iocache.ReadReq_avg_miss_latency::total 185001.197131 # average ReadReq miss latency 2407system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 2408system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 2409system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186495.307308 # average WriteInvalidateReq miss latency 2410system.iocache.WriteInvalidateReq_avg_miss_latency::total 186495.307308 # average WriteInvalidateReq miss latency 2411system.iocache.demand_avg_miss_latency::realview.ethernet 139712.500000 # average overall miss latency 2412system.iocache.demand_avg_miss_latency::realview.ide 185184.130317 # average overall miss latency 2413system.iocache.demand_avg_miss_latency::total 184980.358727 # average overall miss latency 2414system.iocache.overall_avg_miss_latency::realview.ethernet 139712.500000 # average overall miss latency 2415system.iocache.overall_avg_miss_latency::realview.ide 185184.130317 # average overall miss latency 2416system.iocache.overall_avg_miss_latency::total 184980.358727 # average overall miss latency 2417system.iocache.blocked_cycles::no_mshrs 111929 # number of cycles access was blocked 2418system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2419system.iocache.blocked::no_mshrs 16372 # number of cycles access was blocked 2420system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2421system.iocache.avg_blocked_cycles::no_mshrs 6.836611 # average number of cycles each access was blocked 2422system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2423system.iocache.fast_writes 0 # number of fast writes performed 2424system.iocache.cache_copies 0 # number of cache copies performed 2425system.iocache.writebacks::writebacks 106949 # number of writebacks 2426system.iocache.writebacks::total 106949 # number of writebacks 2427system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 2428system.iocache.ReadReq_mshr_misses::realview.ide 8886 # number of ReadReq MSHR misses 2429system.iocache.ReadReq_mshr_misses::total 8923 # number of ReadReq MSHR misses 2430system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2431system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2432system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106984 # number of WriteInvalidateReq MSHR misses 2433system.iocache.WriteInvalidateReq_mshr_misses::total 106984 # number of WriteInvalidateReq MSHR misses 2434system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 2435system.iocache.demand_mshr_misses::realview.ide 8886 # number of demand (read+write) MSHR misses 2436system.iocache.demand_mshr_misses::total 8926 # number of demand (read+write) MSHR misses 2437system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 2438system.iocache.overall_mshr_misses::realview.ide 8886 # number of overall MSHR misses 2439system.iocache.overall_mshr_misses::total 8926 # number of overall MSHR misses 2440system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3294500 # number of ReadReq MSHR miss cycles 2441system.iocache.ReadReq_mshr_miss_latency::realview.ide 1182279102 # number of ReadReq MSHR miss cycles 2442system.iocache.ReadReq_mshr_miss_latency::total 1185573602 # number of ReadReq MSHR miss cycles 2443system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 213000 # number of WriteReq MSHR miss cycles 2444system.iocache.WriteReq_mshr_miss_latency::total 213000 # number of WriteReq MSHR miss cycles 2445system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14388800003 # number of WriteInvalidateReq MSHR miss cycles 2446system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14388800003 # number of WriteInvalidateReq MSHR miss cycles 2447system.iocache.demand_mshr_miss_latency::realview.ethernet 3507500 # number of demand (read+write) MSHR miss cycles 2448system.iocache.demand_mshr_miss_latency::realview.ide 1182279102 # number of demand (read+write) MSHR miss cycles 2449system.iocache.demand_mshr_miss_latency::total 1185786602 # number of demand (read+write) MSHR miss cycles 2450system.iocache.overall_mshr_miss_latency::realview.ethernet 3507500 # number of overall MSHR miss cycles 2451system.iocache.overall_mshr_miss_latency::realview.ide 1182279102 # number of overall MSHR miss cycles 2452system.iocache.overall_mshr_miss_latency::total 1185786602 # number of overall MSHR miss cycles 2453system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2454system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2455system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2456system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2457system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2458system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 2459system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 2460system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 2461system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2462system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2463system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 2464system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2465system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2466system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 89040.540541 # average ReadReq mshr miss latency 2467system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133049.640108 # average ReadReq mshr miss latency 2468system.iocache.ReadReq_avg_mshr_miss_latency::total 132867.152527 # average ReadReq mshr miss latency 2469system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 71000 # average WriteReq mshr miss latency 2470system.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency 2471system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134494.877767 # average WriteInvalidateReq mshr miss latency 2472system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134494.877767 # average WriteInvalidateReq mshr miss latency 2473system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87687.500000 # average overall mshr miss latency 2474system.iocache.demand_avg_mshr_miss_latency::realview.ide 133049.640108 # average overall mshr miss latency 2475system.iocache.demand_avg_mshr_miss_latency::total 132846.359175 # average overall mshr miss latency 2476system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87687.500000 # average overall mshr miss latency 2477system.iocache.overall_avg_mshr_miss_latency::realview.ide 133049.640108 # average overall mshr miss latency 2478system.iocache.overall_avg_mshr_miss_latency::total 132846.359175 # average overall mshr miss latency 2479system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2480system.l2c.tags.replacements 1147719 # number of replacements 2481system.l2c.tags.tagsinuse 64326.028489 # Cycle average of tags in use 2482system.l2c.tags.total_refs 4694874 # Total number of references to valid blocks. 2483system.l2c.tags.sampled_refs 1208975 # Sample count of references to valid blocks. 2484system.l2c.tags.avg_refs 3.883351 # Average number of references to valid blocks. 2485system.l2c.tags.warmup_cycle 8775850000 # Cycle when the warmup percentage was hit. 2486system.l2c.tags.occ_blocks::writebacks 21201.345204 # Average occupied blocks per requestor 2487system.l2c.tags.occ_blocks::cpu0.dtb.walker 99.174306 # Average occupied blocks per requestor 2488system.l2c.tags.occ_blocks::cpu0.itb.walker 102.969089 # Average occupied blocks per requestor 2489system.l2c.tags.occ_blocks::cpu0.inst 6287.304380 # Average occupied blocks per requestor 2490system.l2c.tags.occ_blocks::cpu0.data 9789.287555 # Average occupied blocks per requestor 2491system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 7119.681672 # Average occupied blocks per requestor 2492system.l2c.tags.occ_blocks::cpu1.dtb.walker 173.781032 # Average occupied blocks per requestor 2493system.l2c.tags.occ_blocks::cpu1.itb.walker 211.002205 # Average occupied blocks per requestor 2494system.l2c.tags.occ_blocks::cpu1.inst 4753.478760 # Average occupied blocks per requestor 2495system.l2c.tags.occ_blocks::cpu1.data 6062.523137 # Average occupied blocks per requestor 2496system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8525.481150 # Average occupied blocks per requestor 2497system.l2c.tags.occ_percent::writebacks 0.323507 # Average percentage of cache occupancy 2498system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001513 # Average percentage of cache occupancy 2499system.l2c.tags.occ_percent::cpu0.itb.walker 0.001571 # Average percentage of cache occupancy 2500system.l2c.tags.occ_percent::cpu0.inst 0.095937 # Average percentage of cache occupancy 2501system.l2c.tags.occ_percent::cpu0.data 0.149373 # Average percentage of cache occupancy 2502system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.108638 # Average percentage of cache occupancy 2503system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002652 # Average percentage of cache occupancy 2504system.l2c.tags.occ_percent::cpu1.itb.walker 0.003220 # Average percentage of cache occupancy 2505system.l2c.tags.occ_percent::cpu1.inst 0.072532 # Average percentage of cache occupancy 2506system.l2c.tags.occ_percent::cpu1.data 0.092507 # Average percentage of cache occupancy 2507system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.130089 # Average percentage of cache occupancy 2508system.l2c.tags.occ_percent::total 0.981537 # Average percentage of cache occupancy 2509system.l2c.tags.occ_task_id_blocks::1022 9955 # Occupied blocks per task id 2510system.l2c.tags.occ_task_id_blocks::1023 220 # Occupied blocks per task id 2511system.l2c.tags.occ_task_id_blocks::1024 51081 # Occupied blocks per task id 2512system.l2c.tags.age_task_id_blocks_1022::0 63 # Occupied blocks per task id 2513system.l2c.tags.age_task_id_blocks_1022::1 299 # Occupied blocks per task id 2514system.l2c.tags.age_task_id_blocks_1022::2 192 # Occupied blocks per task id 2515system.l2c.tags.age_task_id_blocks_1022::3 1433 # Occupied blocks per task id 2516system.l2c.tags.age_task_id_blocks_1022::4 7968 # Occupied blocks per task id 2517system.l2c.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id 2518system.l2c.tags.age_task_id_blocks_1023::4 215 # Occupied blocks per task id 2519system.l2c.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 2520system.l2c.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id 2521system.l2c.tags.age_task_id_blocks_1024::2 2117 # Occupied blocks per task id 2522system.l2c.tags.age_task_id_blocks_1024::3 11769 # Occupied blocks per task id 2523system.l2c.tags.age_task_id_blocks_1024::4 36932 # Occupied blocks per task id 2524system.l2c.tags.occ_task_id_percent::1022 0.151901 # Percentage of cache occupancy per task id 2525system.l2c.tags.occ_task_id_percent::1023 0.003357 # Percentage of cache occupancy per task id 2526system.l2c.tags.occ_task_id_percent::1024 0.779434 # Percentage of cache occupancy per task id 2527system.l2c.tags.tag_accesses 59123537 # Number of tag accesses 2528system.l2c.tags.data_accesses 59123537 # Number of data accesses 2529system.l2c.ReadReq_hits::cpu0.dtb.walker 6743 # number of ReadReq hits 2530system.l2c.ReadReq_hits::cpu0.itb.walker 4986 # number of ReadReq hits 2531system.l2c.ReadReq_hits::cpu0.inst 715760 # number of ReadReq hits 2532system.l2c.ReadReq_hits::cpu0.data 559628 # number of ReadReq hits 2533system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 328609 # number of ReadReq hits 2534system.l2c.ReadReq_hits::cpu1.dtb.walker 6048 # number of ReadReq hits 2535system.l2c.ReadReq_hits::cpu1.itb.walker 4129 # number of ReadReq hits 2536system.l2c.ReadReq_hits::cpu1.inst 682361 # number of ReadReq hits 2537system.l2c.ReadReq_hits::cpu1.data 522413 # number of ReadReq hits 2538system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 303271 # number of ReadReq hits 2539system.l2c.ReadReq_hits::total 3133948 # number of ReadReq hits 2540system.l2c.Writeback_hits::writebacks 2214381 # number of Writeback hits 2541system.l2c.Writeback_hits::total 2214381 # number of Writeback hits 2542system.l2c.WriteInvalidateReq_hits::cpu0.data 145887 # number of WriteInvalidateReq hits 2543system.l2c.WriteInvalidateReq_hits::cpu1.data 132101 # number of WriteInvalidateReq hits 2544system.l2c.WriteInvalidateReq_hits::total 277988 # number of WriteInvalidateReq hits 2545system.l2c.UpgradeReq_hits::cpu0.data 29325 # number of UpgradeReq hits 2546system.l2c.UpgradeReq_hits::cpu1.data 26221 # number of UpgradeReq hits 2547system.l2c.UpgradeReq_hits::total 55546 # number of UpgradeReq hits 2548system.l2c.SCUpgradeReq_hits::cpu0.data 6410 # number of SCUpgradeReq hits 2549system.l2c.SCUpgradeReq_hits::cpu1.data 5303 # number of SCUpgradeReq hits 2550system.l2c.SCUpgradeReq_hits::total 11713 # number of SCUpgradeReq hits 2551system.l2c.ReadExReq_hits::cpu0.data 57124 # number of ReadExReq hits 2552system.l2c.ReadExReq_hits::cpu1.data 48409 # number of ReadExReq hits 2553system.l2c.ReadExReq_hits::total 105533 # number of ReadExReq hits 2554system.l2c.demand_hits::cpu0.dtb.walker 6743 # number of demand (read+write) hits 2555system.l2c.demand_hits::cpu0.itb.walker 4986 # number of demand (read+write) hits 2556system.l2c.demand_hits::cpu0.inst 715760 # number of demand (read+write) hits 2557system.l2c.demand_hits::cpu0.data 616752 # number of demand (read+write) hits 2558system.l2c.demand_hits::cpu0.l2cache.prefetcher 328609 # number of demand (read+write) hits 2559system.l2c.demand_hits::cpu1.dtb.walker 6048 # number of demand (read+write) hits 2560system.l2c.demand_hits::cpu1.itb.walker 4129 # number of demand (read+write) hits 2561system.l2c.demand_hits::cpu1.inst 682361 # number of demand (read+write) hits 2562system.l2c.demand_hits::cpu1.data 570822 # number of demand (read+write) hits 2563system.l2c.demand_hits::cpu1.l2cache.prefetcher 303271 # number of demand (read+write) hits 2564system.l2c.demand_hits::total 3239481 # number of demand (read+write) hits 2565system.l2c.overall_hits::cpu0.dtb.walker 6743 # number of overall hits 2566system.l2c.overall_hits::cpu0.itb.walker 4986 # number of overall hits 2567system.l2c.overall_hits::cpu0.inst 715760 # number of overall hits 2568system.l2c.overall_hits::cpu0.data 616752 # number of overall hits 2569system.l2c.overall_hits::cpu0.l2cache.prefetcher 328609 # number of overall hits 2570system.l2c.overall_hits::cpu1.dtb.walker 6048 # number of overall hits 2571system.l2c.overall_hits::cpu1.itb.walker 4129 # number of overall hits 2572system.l2c.overall_hits::cpu1.inst 682361 # number of overall hits 2573system.l2c.overall_hits::cpu1.data 570822 # number of overall hits 2574system.l2c.overall_hits::cpu1.l2cache.prefetcher 303271 # number of overall hits 2575system.l2c.overall_hits::total 3239481 # number of overall hits 2576system.l2c.ReadReq_misses::cpu0.dtb.walker 1023 # number of ReadReq misses 2577system.l2c.ReadReq_misses::cpu0.itb.walker 1006 # number of ReadReq misses 2578system.l2c.ReadReq_misses::cpu0.inst 70277 # number of ReadReq misses 2579system.l2c.ReadReq_misses::cpu0.data 119509 # number of ReadReq misses 2580system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 168399 # number of ReadReq misses 2581system.l2c.ReadReq_misses::cpu1.dtb.walker 1111 # number of ReadReq misses 2582system.l2c.ReadReq_misses::cpu1.itb.walker 1082 # number of ReadReq misses 2583system.l2c.ReadReq_misses::cpu1.inst 44445 # number of ReadReq misses 2584system.l2c.ReadReq_misses::cpu1.data 78155 # number of ReadReq misses 2585system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 124967 # number of ReadReq misses 2586system.l2c.ReadReq_misses::total 609974 # number of ReadReq misses 2587system.l2c.WriteInvalidateReq_misses::cpu0.data 434854 # number of WriteInvalidateReq misses 2588system.l2c.WriteInvalidateReq_misses::cpu1.data 99438 # number of WriteInvalidateReq misses 2589system.l2c.WriteInvalidateReq_misses::total 534292 # number of WriteInvalidateReq misses 2590system.l2c.UpgradeReq_misses::cpu0.data 45074 # number of UpgradeReq misses 2591system.l2c.UpgradeReq_misses::cpu1.data 42732 # number of UpgradeReq misses 2592system.l2c.UpgradeReq_misses::total 87806 # number of UpgradeReq misses 2593system.l2c.SCUpgradeReq_misses::cpu0.data 9265 # number of SCUpgradeReq misses 2594system.l2c.SCUpgradeReq_misses::cpu1.data 7405 # number of SCUpgradeReq misses 2595system.l2c.SCUpgradeReq_misses::total 16670 # number of SCUpgradeReq misses 2596system.l2c.ReadExReq_misses::cpu0.data 70615 # number of ReadExReq misses 2597system.l2c.ReadExReq_misses::cpu1.data 44107 # number of ReadExReq misses 2598system.l2c.ReadExReq_misses::total 114722 # number of ReadExReq misses 2599system.l2c.demand_misses::cpu0.dtb.walker 1023 # number of demand (read+write) misses 2600system.l2c.demand_misses::cpu0.itb.walker 1006 # number of demand (read+write) misses 2601system.l2c.demand_misses::cpu0.inst 70277 # number of demand (read+write) misses 2602system.l2c.demand_misses::cpu0.data 190124 # number of demand (read+write) misses 2603system.l2c.demand_misses::cpu0.l2cache.prefetcher 168399 # number of demand (read+write) misses 2604system.l2c.demand_misses::cpu1.dtb.walker 1111 # number of demand (read+write) misses 2605system.l2c.demand_misses::cpu1.itb.walker 1082 # number of demand (read+write) misses 2606system.l2c.demand_misses::cpu1.inst 44445 # number of demand (read+write) misses 2607system.l2c.demand_misses::cpu1.data 122262 # number of demand (read+write) misses 2608system.l2c.demand_misses::cpu1.l2cache.prefetcher 124967 # number of demand (read+write) misses 2609system.l2c.demand_misses::total 724696 # number of demand (read+write) misses 2610system.l2c.overall_misses::cpu0.dtb.walker 1023 # number of overall misses 2611system.l2c.overall_misses::cpu0.itb.walker 1006 # number of overall misses 2612system.l2c.overall_misses::cpu0.inst 70277 # number of overall misses 2613system.l2c.overall_misses::cpu0.data 190124 # number of overall misses 2614system.l2c.overall_misses::cpu0.l2cache.prefetcher 168399 # number of overall misses 2615system.l2c.overall_misses::cpu1.dtb.walker 1111 # number of overall misses 2616system.l2c.overall_misses::cpu1.itb.walker 1082 # number of overall misses 2617system.l2c.overall_misses::cpu1.inst 44445 # number of overall misses 2618system.l2c.overall_misses::cpu1.data 122262 # number of overall misses 2619system.l2c.overall_misses::cpu1.l2cache.prefetcher 124967 # number of overall misses 2620system.l2c.overall_misses::total 724696 # number of overall misses 2621system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 90170503 # number of ReadReq miss cycles 2622system.l2c.ReadReq_miss_latency::cpu0.itb.walker 86831257 # number of ReadReq miss cycles 2623system.l2c.ReadReq_miss_latency::cpu0.inst 5869737346 # number of ReadReq miss cycles 2624system.l2c.ReadReq_miss_latency::cpu0.data 10761538889 # number of ReadReq miss cycles 2625system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 21763176095 # number of ReadReq miss cycles 2626system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 95166250 # number of ReadReq miss cycles 2627system.l2c.ReadReq_miss_latency::cpu1.itb.walker 96017000 # number of ReadReq miss cycles 2628system.l2c.ReadReq_miss_latency::cpu1.inst 3692339104 # number of ReadReq miss cycles 2629system.l2c.ReadReq_miss_latency::cpu1.data 6847833445 # number of ReadReq miss cycles 2630system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 15053704575 # number of ReadReq miss cycles 2631system.l2c.ReadReq_miss_latency::total 64356514464 # number of ReadReq miss cycles 2632system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 50866916 # number of WriteInvalidateReq miss cycles 2633system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 43440127 # number of WriteInvalidateReq miss cycles 2634system.l2c.WriteInvalidateReq_miss_latency::total 94307043 # number of WriteInvalidateReq miss cycles 2635system.l2c.UpgradeReq_miss_latency::cpu0.data 280117177 # number of UpgradeReq miss cycles 2636system.l2c.UpgradeReq_miss_latency::cpu1.data 285028454 # number of UpgradeReq miss cycles 2637system.l2c.UpgradeReq_miss_latency::total 565145631 # number of UpgradeReq miss cycles 2638system.l2c.SCUpgradeReq_miss_latency::cpu0.data 53423811 # number of SCUpgradeReq miss cycles 2639system.l2c.SCUpgradeReq_miss_latency::cpu1.data 47784487 # number of SCUpgradeReq miss cycles 2640system.l2c.SCUpgradeReq_miss_latency::total 101208298 # number of SCUpgradeReq miss cycles 2641system.l2c.ReadExReq_miss_latency::cpu0.data 6307677426 # number of ReadExReq miss cycles 2642system.l2c.ReadExReq_miss_latency::cpu1.data 3604652546 # number of ReadExReq miss cycles 2643system.l2c.ReadExReq_miss_latency::total 9912329972 # number of ReadExReq miss cycles 2644system.l2c.demand_miss_latency::cpu0.dtb.walker 90170503 # number of demand (read+write) miss cycles 2645system.l2c.demand_miss_latency::cpu0.itb.walker 86831257 # number of demand (read+write) miss cycles 2646system.l2c.demand_miss_latency::cpu0.inst 5869737346 # number of demand (read+write) miss cycles 2647system.l2c.demand_miss_latency::cpu0.data 17069216315 # number of demand (read+write) miss cycles 2648system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 21763176095 # number of demand (read+write) miss cycles 2649system.l2c.demand_miss_latency::cpu1.dtb.walker 95166250 # number of demand (read+write) miss cycles 2650system.l2c.demand_miss_latency::cpu1.itb.walker 96017000 # number of demand (read+write) miss cycles 2651system.l2c.demand_miss_latency::cpu1.inst 3692339104 # number of demand (read+write) miss cycles 2652system.l2c.demand_miss_latency::cpu1.data 10452485991 # number of demand (read+write) miss cycles 2653system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 15053704575 # number of demand (read+write) miss cycles 2654system.l2c.demand_miss_latency::total 74268844436 # number of demand (read+write) miss cycles 2655system.l2c.overall_miss_latency::cpu0.dtb.walker 90170503 # number of overall miss cycles 2656system.l2c.overall_miss_latency::cpu0.itb.walker 86831257 # number of overall miss cycles 2657system.l2c.overall_miss_latency::cpu0.inst 5869737346 # number of overall miss cycles 2658system.l2c.overall_miss_latency::cpu0.data 17069216315 # number of overall miss cycles 2659system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 21763176095 # number of overall miss cycles 2660system.l2c.overall_miss_latency::cpu1.dtb.walker 95166250 # number of overall miss cycles 2661system.l2c.overall_miss_latency::cpu1.itb.walker 96017000 # number of overall miss cycles 2662system.l2c.overall_miss_latency::cpu1.inst 3692339104 # number of overall miss cycles 2663system.l2c.overall_miss_latency::cpu1.data 10452485991 # number of overall miss cycles 2664system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 15053704575 # number of overall miss cycles 2665system.l2c.overall_miss_latency::total 74268844436 # number of overall miss cycles 2666system.l2c.ReadReq_accesses::cpu0.dtb.walker 7766 # number of ReadReq accesses(hits+misses) 2667system.l2c.ReadReq_accesses::cpu0.itb.walker 5992 # number of ReadReq accesses(hits+misses) 2668system.l2c.ReadReq_accesses::cpu0.inst 786037 # number of ReadReq accesses(hits+misses) 2669system.l2c.ReadReq_accesses::cpu0.data 679137 # number of ReadReq accesses(hits+misses) 2670system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 497008 # number of ReadReq accesses(hits+misses) 2671system.l2c.ReadReq_accesses::cpu1.dtb.walker 7159 # number of ReadReq accesses(hits+misses) 2672system.l2c.ReadReq_accesses::cpu1.itb.walker 5211 # number of ReadReq accesses(hits+misses) 2673system.l2c.ReadReq_accesses::cpu1.inst 726806 # number of ReadReq accesses(hits+misses) 2674system.l2c.ReadReq_accesses::cpu1.data 600568 # number of ReadReq accesses(hits+misses) 2675system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 428238 # number of ReadReq accesses(hits+misses) 2676system.l2c.ReadReq_accesses::total 3743922 # number of ReadReq accesses(hits+misses) 2677system.l2c.Writeback_accesses::writebacks 2214381 # number of Writeback accesses(hits+misses) 2678system.l2c.Writeback_accesses::total 2214381 # number of Writeback accesses(hits+misses) 2679system.l2c.WriteInvalidateReq_accesses::cpu0.data 580741 # number of WriteInvalidateReq accesses(hits+misses) 2680system.l2c.WriteInvalidateReq_accesses::cpu1.data 231539 # number of WriteInvalidateReq accesses(hits+misses) 2681system.l2c.WriteInvalidateReq_accesses::total 812280 # number of WriteInvalidateReq accesses(hits+misses) 2682system.l2c.UpgradeReq_accesses::cpu0.data 74399 # number of UpgradeReq accesses(hits+misses) 2683system.l2c.UpgradeReq_accesses::cpu1.data 68953 # number of UpgradeReq accesses(hits+misses) 2684system.l2c.UpgradeReq_accesses::total 143352 # number of UpgradeReq accesses(hits+misses) 2685system.l2c.SCUpgradeReq_accesses::cpu0.data 15675 # number of SCUpgradeReq accesses(hits+misses) 2686system.l2c.SCUpgradeReq_accesses::cpu1.data 12708 # number of SCUpgradeReq accesses(hits+misses) 2687system.l2c.SCUpgradeReq_accesses::total 28383 # number of SCUpgradeReq accesses(hits+misses) 2688system.l2c.ReadExReq_accesses::cpu0.data 127739 # number of ReadExReq accesses(hits+misses) 2689system.l2c.ReadExReq_accesses::cpu1.data 92516 # number of ReadExReq accesses(hits+misses) 2690system.l2c.ReadExReq_accesses::total 220255 # number of ReadExReq accesses(hits+misses) 2691system.l2c.demand_accesses::cpu0.dtb.walker 7766 # number of demand (read+write) accesses 2692system.l2c.demand_accesses::cpu0.itb.walker 5992 # number of demand (read+write) accesses 2693system.l2c.demand_accesses::cpu0.inst 786037 # number of demand (read+write) accesses 2694system.l2c.demand_accesses::cpu0.data 806876 # number of demand (read+write) accesses 2695system.l2c.demand_accesses::cpu0.l2cache.prefetcher 497008 # number of demand (read+write) accesses 2696system.l2c.demand_accesses::cpu1.dtb.walker 7159 # number of demand (read+write) accesses 2697system.l2c.demand_accesses::cpu1.itb.walker 5211 # number of demand (read+write) accesses 2698system.l2c.demand_accesses::cpu1.inst 726806 # number of demand (read+write) accesses 2699system.l2c.demand_accesses::cpu1.data 693084 # number of demand (read+write) accesses 2700system.l2c.demand_accesses::cpu1.l2cache.prefetcher 428238 # number of demand (read+write) accesses 2701system.l2c.demand_accesses::total 3964177 # number of demand (read+write) accesses 2702system.l2c.overall_accesses::cpu0.dtb.walker 7766 # number of overall (read+write) accesses 2703system.l2c.overall_accesses::cpu0.itb.walker 5992 # number of overall (read+write) accesses 2704system.l2c.overall_accesses::cpu0.inst 786037 # number of overall (read+write) accesses 2705system.l2c.overall_accesses::cpu0.data 806876 # number of overall (read+write) accesses 2706system.l2c.overall_accesses::cpu0.l2cache.prefetcher 497008 # number of overall (read+write) accesses 2707system.l2c.overall_accesses::cpu1.dtb.walker 7159 # number of overall (read+write) accesses 2708system.l2c.overall_accesses::cpu1.itb.walker 5211 # number of overall (read+write) accesses 2709system.l2c.overall_accesses::cpu1.inst 726806 # number of overall (read+write) accesses 2710system.l2c.overall_accesses::cpu1.data 693084 # number of overall (read+write) accesses 2711system.l2c.overall_accesses::cpu1.l2cache.prefetcher 428238 # number of overall (read+write) accesses 2712system.l2c.overall_accesses::total 3964177 # number of overall (read+write) accesses 2713system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.131728 # miss rate for ReadReq accesses 2714system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.167891 # miss rate for ReadReq accesses 2715system.l2c.ReadReq_miss_rate::cpu0.inst 0.089407 # miss rate for ReadReq accesses 2716system.l2c.ReadReq_miss_rate::cpu0.data 0.175972 # miss rate for ReadReq accesses 2717system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.338826 # miss rate for ReadReq accesses 2718system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.155189 # miss rate for ReadReq accesses 2719system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.207638 # miss rate for ReadReq accesses 2720system.l2c.ReadReq_miss_rate::cpu1.inst 0.061151 # miss rate for ReadReq accesses 2721system.l2c.ReadReq_miss_rate::cpu1.data 0.130135 # miss rate for ReadReq accesses 2722system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.291817 # miss rate for ReadReq accesses 2723system.l2c.ReadReq_miss_rate::total 0.162924 # miss rate for ReadReq accesses 2724system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.748792 # miss rate for WriteInvalidateReq accesses 2725system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.429465 # miss rate for WriteInvalidateReq accesses 2726system.l2c.WriteInvalidateReq_miss_rate::total 0.657768 # miss rate for WriteInvalidateReq accesses 2727system.l2c.UpgradeReq_miss_rate::cpu0.data 0.605841 # miss rate for UpgradeReq accesses 2728system.l2c.UpgradeReq_miss_rate::cpu1.data 0.619726 # miss rate for UpgradeReq accesses 2729system.l2c.UpgradeReq_miss_rate::total 0.612520 # miss rate for UpgradeReq accesses 2730system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.591069 # miss rate for SCUpgradeReq accesses 2731system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.582704 # miss rate for SCUpgradeReq accesses 2732system.l2c.SCUpgradeReq_miss_rate::total 0.587323 # miss rate for SCUpgradeReq accesses 2733system.l2c.ReadExReq_miss_rate::cpu0.data 0.552807 # miss rate for ReadExReq accesses 2734system.l2c.ReadExReq_miss_rate::cpu1.data 0.476750 # miss rate for ReadExReq accesses 2735system.l2c.ReadExReq_miss_rate::total 0.520860 # miss rate for ReadExReq accesses 2736system.l2c.demand_miss_rate::cpu0.dtb.walker 0.131728 # miss rate for demand accesses 2737system.l2c.demand_miss_rate::cpu0.itb.walker 0.167891 # miss rate for demand accesses 2738system.l2c.demand_miss_rate::cpu0.inst 0.089407 # miss rate for demand accesses 2739system.l2c.demand_miss_rate::cpu0.data 0.235630 # miss rate for demand accesses 2740system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.338826 # miss rate for demand accesses 2741system.l2c.demand_miss_rate::cpu1.dtb.walker 0.155189 # miss rate for demand accesses 2742system.l2c.demand_miss_rate::cpu1.itb.walker 0.207638 # miss rate for demand accesses 2743system.l2c.demand_miss_rate::cpu1.inst 0.061151 # miss rate for demand accesses 2744system.l2c.demand_miss_rate::cpu1.data 0.176403 # miss rate for demand accesses 2745system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.291817 # miss rate for demand accesses 2746system.l2c.demand_miss_rate::total 0.182811 # miss rate for demand accesses 2747system.l2c.overall_miss_rate::cpu0.dtb.walker 0.131728 # miss rate for overall accesses 2748system.l2c.overall_miss_rate::cpu0.itb.walker 0.167891 # miss rate for overall accesses 2749system.l2c.overall_miss_rate::cpu0.inst 0.089407 # miss rate for overall accesses 2750system.l2c.overall_miss_rate::cpu0.data 0.235630 # miss rate for overall accesses 2751system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.338826 # miss rate for overall accesses 2752system.l2c.overall_miss_rate::cpu1.dtb.walker 0.155189 # miss rate for overall accesses 2753system.l2c.overall_miss_rate::cpu1.itb.walker 0.207638 # miss rate for overall accesses 2754system.l2c.overall_miss_rate::cpu1.inst 0.061151 # miss rate for overall accesses 2755system.l2c.overall_miss_rate::cpu1.data 0.176403 # miss rate for overall accesses 2756system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.291817 # miss rate for overall accesses 2757system.l2c.overall_miss_rate::total 0.182811 # miss rate for overall accesses 2758system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 88143.209189 # average ReadReq miss latency 2759system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 86313.376740 # average ReadReq miss latency 2760system.l2c.ReadReq_avg_miss_latency::cpu0.inst 83522.878694 # average ReadReq miss latency 2761system.l2c.ReadReq_avg_miss_latency::cpu0.data 90047.936883 # average ReadReq miss latency 2762system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 129235.779874 # average ReadReq miss latency 2763system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 85658.190819 # average ReadReq miss latency 2764system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 88740.295749 # average ReadReq miss latency 2765system.l2c.ReadReq_avg_miss_latency::cpu1.inst 83076.591383 # average ReadReq miss latency 2766system.l2c.ReadReq_avg_miss_latency::cpu1.data 87618.622545 # average ReadReq miss latency 2767system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 120461.438420 # average ReadReq miss latency 2768system.l2c.ReadReq_avg_miss_latency::total 105506.979747 # average ReadReq miss latency 2769system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 116.974700 # average WriteInvalidateReq miss latency 2770system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 436.856403 # average WriteInvalidateReq miss latency 2771system.l2c.WriteInvalidateReq_avg_miss_latency::total 176.508432 # average WriteInvalidateReq miss latency 2772system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6214.606580 # average UpgradeReq miss latency 2773system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6670.140738 # average UpgradeReq miss latency 2774system.l2c.UpgradeReq_avg_miss_latency::total 6436.298556 # average UpgradeReq miss latency 2775system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5766.196546 # average SCUpgradeReq miss latency 2776system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6453.002971 # average SCUpgradeReq miss latency 2777system.l2c.SCUpgradeReq_avg_miss_latency::total 6071.283623 # average SCUpgradeReq miss latency 2778system.l2c.ReadExReq_avg_miss_latency::cpu0.data 89324.894512 # average ReadExReq miss latency 2779system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81725.180720 # average ReadExReq miss latency 2780system.l2c.ReadExReq_avg_miss_latency::total 86403.043636 # average ReadExReq miss latency 2781system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 88143.209189 # average overall miss latency 2782system.l2c.demand_avg_miss_latency::cpu0.itb.walker 86313.376740 # average overall miss latency 2783system.l2c.demand_avg_miss_latency::cpu0.inst 83522.878694 # average overall miss latency 2784system.l2c.demand_avg_miss_latency::cpu0.data 89779.387742 # average overall miss latency 2785system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 129235.779874 # average overall miss latency 2786system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 85658.190819 # average overall miss latency 2787system.l2c.demand_avg_miss_latency::cpu1.itb.walker 88740.295749 # average overall miss latency 2788system.l2c.demand_avg_miss_latency::cpu1.inst 83076.591383 # average overall miss latency 2789system.l2c.demand_avg_miss_latency::cpu1.data 85492.515998 # average overall miss latency 2790system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 120461.438420 # average overall miss latency 2791system.l2c.demand_avg_miss_latency::total 102482.757509 # average overall miss latency 2792system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 88143.209189 # average overall miss latency 2793system.l2c.overall_avg_miss_latency::cpu0.itb.walker 86313.376740 # average overall miss latency 2794system.l2c.overall_avg_miss_latency::cpu0.inst 83522.878694 # average overall miss latency 2795system.l2c.overall_avg_miss_latency::cpu0.data 89779.387742 # average overall miss latency 2796system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 129235.779874 # average overall miss latency 2797system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 85658.190819 # average overall miss latency 2798system.l2c.overall_avg_miss_latency::cpu1.itb.walker 88740.295749 # average overall miss latency 2799system.l2c.overall_avg_miss_latency::cpu1.inst 83076.591383 # average overall miss latency 2800system.l2c.overall_avg_miss_latency::cpu1.data 85492.515998 # average overall miss latency 2801system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 120461.438420 # average overall miss latency 2802system.l2c.overall_avg_miss_latency::total 102482.757509 # average overall miss latency 2803system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2804system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2805system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2806system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2807system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2808system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2809system.l2c.fast_writes 0 # number of fast writes performed 2810system.l2c.cache_copies 0 # number of cache copies performed 2811system.l2c.writebacks::writebacks 874309 # number of writebacks 2812system.l2c.writebacks::total 874309 # number of writebacks 2813system.l2c.ReadReq_mshr_hits::cpu0.inst 170 # number of ReadReq MSHR hits 2814system.l2c.ReadReq_mshr_hits::cpu0.data 24 # number of ReadReq MSHR hits 2815system.l2c.ReadReq_mshr_hits::cpu1.inst 144 # number of ReadReq MSHR hits 2816system.l2c.ReadReq_mshr_hits::cpu1.data 21 # number of ReadReq MSHR hits 2817system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 1 # number of ReadReq MSHR hits 2818system.l2c.ReadReq_mshr_hits::total 360 # number of ReadReq MSHR hits 2819system.l2c.demand_mshr_hits::cpu0.inst 170 # number of demand (read+write) MSHR hits 2820system.l2c.demand_mshr_hits::cpu0.data 24 # number of demand (read+write) MSHR hits 2821system.l2c.demand_mshr_hits::cpu1.inst 144 # number of demand (read+write) MSHR hits 2822system.l2c.demand_mshr_hits::cpu1.data 21 # number of demand (read+write) MSHR hits 2823system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits 2824system.l2c.demand_mshr_hits::total 360 # number of demand (read+write) MSHR hits 2825system.l2c.overall_mshr_hits::cpu0.inst 170 # number of overall MSHR hits 2826system.l2c.overall_mshr_hits::cpu0.data 24 # number of overall MSHR hits 2827system.l2c.overall_mshr_hits::cpu1.inst 144 # number of overall MSHR hits 2828system.l2c.overall_mshr_hits::cpu1.data 21 # number of overall MSHR hits 2829system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 1 # number of overall MSHR hits 2830system.l2c.overall_mshr_hits::total 360 # number of overall MSHR hits 2831system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1023 # number of ReadReq MSHR misses 2832system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1006 # number of ReadReq MSHR misses 2833system.l2c.ReadReq_mshr_misses::cpu0.inst 70107 # number of ReadReq MSHR misses 2834system.l2c.ReadReq_mshr_misses::cpu0.data 119485 # number of ReadReq MSHR misses 2835system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 168399 # number of ReadReq MSHR misses 2836system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1111 # number of ReadReq MSHR misses 2837system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1082 # number of ReadReq MSHR misses 2838system.l2c.ReadReq_mshr_misses::cpu1.inst 44301 # number of ReadReq MSHR misses 2839system.l2c.ReadReq_mshr_misses::cpu1.data 78134 # number of ReadReq MSHR misses 2840system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 124966 # number of ReadReq MSHR misses 2841system.l2c.ReadReq_mshr_misses::total 609614 # number of ReadReq MSHR misses 2842system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 434854 # number of WriteInvalidateReq MSHR misses 2843system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 99438 # number of WriteInvalidateReq MSHR misses 2844system.l2c.WriteInvalidateReq_mshr_misses::total 534292 # number of WriteInvalidateReq MSHR misses 2845system.l2c.UpgradeReq_mshr_misses::cpu0.data 45074 # number of UpgradeReq MSHR misses 2846system.l2c.UpgradeReq_mshr_misses::cpu1.data 42732 # number of UpgradeReq MSHR misses 2847system.l2c.UpgradeReq_mshr_misses::total 87806 # number of UpgradeReq MSHR misses 2848system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 9265 # number of SCUpgradeReq MSHR misses 2849system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 7405 # number of SCUpgradeReq MSHR misses 2850system.l2c.SCUpgradeReq_mshr_misses::total 16670 # number of SCUpgradeReq MSHR misses 2851system.l2c.ReadExReq_mshr_misses::cpu0.data 70615 # number of ReadExReq MSHR misses 2852system.l2c.ReadExReq_mshr_misses::cpu1.data 44107 # number of ReadExReq MSHR misses 2853system.l2c.ReadExReq_mshr_misses::total 114722 # number of ReadExReq MSHR misses 2854system.l2c.demand_mshr_misses::cpu0.dtb.walker 1023 # number of demand (read+write) MSHR misses 2855system.l2c.demand_mshr_misses::cpu0.itb.walker 1006 # number of demand (read+write) MSHR misses 2856system.l2c.demand_mshr_misses::cpu0.inst 70107 # number of demand (read+write) MSHR misses 2857system.l2c.demand_mshr_misses::cpu0.data 190100 # number of demand (read+write) MSHR misses 2858system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 168399 # number of demand (read+write) MSHR misses 2859system.l2c.demand_mshr_misses::cpu1.dtb.walker 1111 # number of demand (read+write) MSHR misses 2860system.l2c.demand_mshr_misses::cpu1.itb.walker 1082 # number of demand (read+write) MSHR misses 2861system.l2c.demand_mshr_misses::cpu1.inst 44301 # number of demand (read+write) MSHR misses 2862system.l2c.demand_mshr_misses::cpu1.data 122241 # number of demand (read+write) MSHR misses 2863system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 124966 # number of demand (read+write) MSHR misses 2864system.l2c.demand_mshr_misses::total 724336 # number of demand (read+write) MSHR misses 2865system.l2c.overall_mshr_misses::cpu0.dtb.walker 1023 # number of overall MSHR misses 2866system.l2c.overall_mshr_misses::cpu0.itb.walker 1006 # number of overall MSHR misses 2867system.l2c.overall_mshr_misses::cpu0.inst 70107 # number of overall MSHR misses 2868system.l2c.overall_mshr_misses::cpu0.data 190100 # number of overall MSHR misses 2869system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 168399 # number of overall MSHR misses 2870system.l2c.overall_mshr_misses::cpu1.dtb.walker 1111 # number of overall MSHR misses 2871system.l2c.overall_mshr_misses::cpu1.itb.walker 1082 # number of overall MSHR misses 2872system.l2c.overall_mshr_misses::cpu1.inst 44301 # number of overall MSHR misses 2873system.l2c.overall_mshr_misses::cpu1.data 122241 # number of overall MSHR misses 2874system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 124966 # number of overall MSHR misses 2875system.l2c.overall_mshr_misses::total 724336 # number of overall MSHR misses 2876system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 52307 # number of ReadReq MSHR uncacheable 2877system.l2c.ReadReq_mshr_uncacheable::cpu0.data 33259 # number of ReadReq MSHR uncacheable 2878system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 90 # number of ReadReq MSHR uncacheable 2879system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5081 # number of ReadReq MSHR uncacheable 2880system.l2c.ReadReq_mshr_uncacheable::total 90737 # number of ReadReq MSHR uncacheable 2881system.l2c.WriteReq_mshr_uncacheable::cpu0.data 33163 # number of WriteReq MSHR uncacheable 2882system.l2c.WriteReq_mshr_uncacheable::cpu1.data 5087 # number of WriteReq MSHR uncacheable 2883system.l2c.WriteReq_mshr_uncacheable::total 38250 # number of WriteReq MSHR uncacheable 2884system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 52307 # number of overall MSHR uncacheable misses 2885system.l2c.overall_mshr_uncacheable_misses::cpu0.data 66422 # number of overall MSHR uncacheable misses 2886system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 90 # number of overall MSHR uncacheable misses 2887system.l2c.overall_mshr_uncacheable_misses::cpu1.data 10168 # number of overall MSHR uncacheable misses 2888system.l2c.overall_mshr_uncacheable_misses::total 128987 # number of overall MSHR uncacheable misses 2889system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 77296003 # number of ReadReq MSHR miss cycles 2890system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 74149743 # number of ReadReq MSHR miss cycles 2891system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 4978677404 # number of ReadReq MSHR miss cycles 2892system.l2c.ReadReq_mshr_miss_latency::cpu0.data 9263784361 # number of ReadReq MSHR miss cycles 2893system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 19697035299 # number of ReadReq MSHR miss cycles 2894system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 81192250 # number of ReadReq MSHR miss cycles 2895system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 82396000 # number of ReadReq MSHR miss cycles 2896system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3126135146 # number of ReadReq MSHR miss cycles 2897system.l2c.ReadReq_mshr_miss_latency::cpu1.data 5867580805 # number of ReadReq MSHR miss cycles 2898system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 13516096621 # number of ReadReq MSHR miss cycles 2899system.l2c.ReadReq_mshr_miss_latency::total 56764343632 # number of ReadReq MSHR miss cycles 2900system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 14608180584 # number of WriteInvalidateReq MSHR miss cycles 2901system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 3180916875 # number of WriteInvalidateReq MSHR miss cycles 2902system.l2c.WriteInvalidateReq_mshr_miss_latency::total 17789097459 # number of WriteInvalidateReq MSHR miss cycles 2903system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 802841847 # number of UpgradeReq MSHR miss cycles 2904system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 760303552 # number of UpgradeReq MSHR miss cycles 2905system.l2c.UpgradeReq_mshr_miss_latency::total 1563145399 # number of UpgradeReq MSHR miss cycles 2906system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 165105237 # number of SCUpgradeReq MSHR miss cycles 2907system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 131856877 # number of SCUpgradeReq MSHR miss cycles 2908system.l2c.SCUpgradeReq_mshr_miss_latency::total 296962114 # number of SCUpgradeReq MSHR miss cycles 2909system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5424714574 # number of ReadExReq MSHR miss cycles 2910system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3052436454 # number of ReadExReq MSHR miss cycles 2911system.l2c.ReadExReq_mshr_miss_latency::total 8477151028 # number of ReadExReq MSHR miss cycles 2912system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 77296003 # number of demand (read+write) MSHR miss cycles 2913system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 74149743 # number of demand (read+write) MSHR miss cycles 2914system.l2c.demand_mshr_miss_latency::cpu0.inst 4978677404 # number of demand (read+write) MSHR miss cycles 2915system.l2c.demand_mshr_miss_latency::cpu0.data 14688498935 # number of demand (read+write) MSHR miss cycles 2916system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 19697035299 # number of demand (read+write) MSHR miss cycles 2917system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 81192250 # number of demand (read+write) MSHR miss cycles 2918system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 82396000 # number of demand (read+write) MSHR miss cycles 2919system.l2c.demand_mshr_miss_latency::cpu1.inst 3126135146 # number of demand (read+write) MSHR miss cycles 2920system.l2c.demand_mshr_miss_latency::cpu1.data 8920017259 # number of demand (read+write) MSHR miss cycles 2921system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 13516096621 # number of demand (read+write) MSHR miss cycles 2922system.l2c.demand_mshr_miss_latency::total 65241494660 # number of demand (read+write) MSHR miss cycles 2923system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 77296003 # number of overall MSHR miss cycles 2924system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 74149743 # number of overall MSHR miss cycles 2925system.l2c.overall_mshr_miss_latency::cpu0.inst 4978677404 # number of overall MSHR miss cycles 2926system.l2c.overall_mshr_miss_latency::cpu0.data 14688498935 # number of overall MSHR miss cycles 2927system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 19697035299 # number of overall MSHR miss cycles 2928system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 81192250 # number of overall MSHR miss cycles 2929system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 82396000 # number of overall MSHR miss cycles 2930system.l2c.overall_mshr_miss_latency::cpu1.inst 3126135146 # number of overall MSHR miss cycles 2931system.l2c.overall_mshr_miss_latency::cpu1.data 8920017259 # number of overall MSHR miss cycles 2932system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 13516096621 # number of overall MSHR miss cycles 2933system.l2c.overall_mshr_miss_latency::total 65241494660 # number of overall MSHR miss cycles 2934system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3188012750 # number of ReadReq MSHR uncacheable cycles 2935system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5000535750 # number of ReadReq MSHR uncacheable cycles 2936system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5725000 # number of ReadReq MSHR uncacheable cycles 2937system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 377455500 # number of ReadReq MSHR uncacheable cycles 2938system.l2c.ReadReq_mshr_uncacheable_latency::total 8571729000 # number of ReadReq MSHR uncacheable cycles 2939system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4829727000 # number of WriteReq MSHR uncacheable cycles 2940system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 450782500 # number of WriteReq MSHR uncacheable cycles 2941system.l2c.WriteReq_mshr_uncacheable_latency::total 5280509500 # number of WriteReq MSHR uncacheable cycles 2942system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3188012750 # number of overall MSHR uncacheable cycles 2943system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9830262750 # number of overall MSHR uncacheable cycles 2944system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5725000 # number of overall MSHR uncacheable cycles 2945system.l2c.overall_mshr_uncacheable_latency::cpu1.data 828238000 # number of overall MSHR uncacheable cycles 2946system.l2c.overall_mshr_uncacheable_latency::total 13852238500 # number of overall MSHR uncacheable cycles 2947system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.131728 # mshr miss rate for ReadReq accesses 2948system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.167891 # mshr miss rate for ReadReq accesses 2949system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.089190 # mshr miss rate for ReadReq accesses 2950system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.175937 # mshr miss rate for ReadReq accesses 2951system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.338826 # mshr miss rate for ReadReq accesses 2952system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.155189 # mshr miss rate for ReadReq accesses 2953system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.207638 # mshr miss rate for ReadReq accesses 2954system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.060953 # mshr miss rate for ReadReq accesses 2955system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.130100 # mshr miss rate for ReadReq accesses 2956system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.291814 # mshr miss rate for ReadReq accesses 2957system.l2c.ReadReq_mshr_miss_rate::total 0.162828 # mshr miss rate for ReadReq accesses 2958system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.748792 # mshr miss rate for WriteInvalidateReq accesses 2959system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.429465 # mshr miss rate for WriteInvalidateReq accesses 2960system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.657768 # mshr miss rate for WriteInvalidateReq accesses 2961system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.605841 # mshr miss rate for UpgradeReq accesses 2962system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.619726 # mshr miss rate for UpgradeReq accesses 2963system.l2c.UpgradeReq_mshr_miss_rate::total 0.612520 # mshr miss rate for UpgradeReq accesses 2964system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.591069 # mshr miss rate for SCUpgradeReq accesses 2965system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.582704 # mshr miss rate for SCUpgradeReq accesses 2966system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.587323 # mshr miss rate for SCUpgradeReq accesses 2967system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.552807 # mshr miss rate for ReadExReq accesses 2968system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.476750 # mshr miss rate for ReadExReq accesses 2969system.l2c.ReadExReq_mshr_miss_rate::total 0.520860 # mshr miss rate for ReadExReq accesses 2970system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.131728 # mshr miss rate for demand accesses 2971system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.167891 # mshr miss rate for demand accesses 2972system.l2c.demand_mshr_miss_rate::cpu0.inst 0.089190 # mshr miss rate for demand accesses 2973system.l2c.demand_mshr_miss_rate::cpu0.data 0.235600 # mshr miss rate for demand accesses 2974system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.338826 # mshr miss rate for demand accesses 2975system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.155189 # mshr miss rate for demand accesses 2976system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.207638 # mshr miss rate for demand accesses 2977system.l2c.demand_mshr_miss_rate::cpu1.inst 0.060953 # mshr miss rate for demand accesses 2978system.l2c.demand_mshr_miss_rate::cpu1.data 0.176373 # mshr miss rate for demand accesses 2979system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.291814 # mshr miss rate for demand accesses 2980system.l2c.demand_mshr_miss_rate::total 0.182720 # mshr miss rate for demand accesses 2981system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.131728 # mshr miss rate for overall accesses 2982system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.167891 # mshr miss rate for overall accesses 2983system.l2c.overall_mshr_miss_rate::cpu0.inst 0.089190 # mshr miss rate for overall accesses 2984system.l2c.overall_mshr_miss_rate::cpu0.data 0.235600 # mshr miss rate for overall accesses 2985system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.338826 # mshr miss rate for overall accesses 2986system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.155189 # mshr miss rate for overall accesses 2987system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.207638 # mshr miss rate for overall accesses 2988system.l2c.overall_mshr_miss_rate::cpu1.inst 0.060953 # mshr miss rate for overall accesses 2989system.l2c.overall_mshr_miss_rate::cpu1.data 0.176373 # mshr miss rate for overall accesses 2990system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.291814 # mshr miss rate for overall accesses 2991system.l2c.overall_mshr_miss_rate::total 0.182720 # mshr miss rate for overall accesses 2992system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 75558.165200 # average ReadReq mshr miss latency 2993system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 73707.498012 # average ReadReq mshr miss latency 2994system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 71015.410786 # average ReadReq mshr miss latency 2995system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 77530.939959 # average ReadReq mshr miss latency 2996system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116966.462384 # average ReadReq mshr miss latency 2997system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 73080.333033 # average ReadReq mshr miss latency 2998system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76151.571165 # average ReadReq mshr miss latency 2999system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70565.791878 # average ReadReq mshr miss latency 3000system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75096.383201 # average ReadReq mshr miss latency 3001system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108158.191996 # average ReadReq mshr miss latency 3002system.l2c.ReadReq_avg_mshr_miss_latency::total 93115.223128 # average ReadReq mshr miss latency 3003system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33593.299323 # average WriteInvalidateReq mshr miss latency 3004system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31988.946630 # average WriteInvalidateReq mshr miss latency 3005system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 33294.710494 # average WriteInvalidateReq mshr miss latency 3006system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17811.639681 # average UpgradeReq mshr miss latency 3007system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17792.369934 # average UpgradeReq mshr miss latency 3008system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17802.261793 # average UpgradeReq mshr miss latency 3009system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17820.316999 # average SCUpgradeReq mshr miss latency 3010system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17806.465496 # average SCUpgradeReq mshr miss latency 3011system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17814.164007 # average SCUpgradeReq mshr miss latency 3012system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 76820.995171 # average ReadExReq mshr miss latency 3013system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69205.261160 # average ReadExReq mshr miss latency 3014system.l2c.ReadExReq_avg_mshr_miss_latency::total 73892.985025 # average ReadExReq mshr miss latency 3015system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 75558.165200 # average overall mshr miss latency 3016system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 73707.498012 # average overall mshr miss latency 3017system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71015.410786 # average overall mshr miss latency 3018system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77267.222173 # average overall mshr miss latency 3019system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116966.462384 # average overall mshr miss latency 3020system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 73080.333033 # average overall mshr miss latency 3021system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76151.571165 # average overall mshr miss latency 3022system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70565.791878 # average overall mshr miss latency 3023system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72970.748431 # average overall mshr miss latency 3024system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108158.191996 # average overall mshr miss latency 3025system.l2c.demand_avg_mshr_miss_latency::total 90070.760890 # average overall mshr miss latency 3026system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 75558.165200 # average overall mshr miss latency 3027system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73707.498012 # average overall mshr miss latency 3028system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71015.410786 # average overall mshr miss latency 3029system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77267.222173 # average overall mshr miss latency 3030system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116966.462384 # average overall mshr miss latency 3031system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 73080.333033 # average overall mshr miss latency 3032system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76151.571165 # average overall mshr miss latency 3033system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70565.791878 # average overall mshr miss latency 3034system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72970.748431 # average overall mshr miss latency 3035system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108158.191996 # average overall mshr miss latency 3036system.l2c.overall_avg_mshr_miss_latency::total 90070.760890 # average overall mshr miss latency 3037system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60948.109240 # average ReadReq mshr uncacheable latency 3038system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 150351.356024 # average ReadReq mshr uncacheable latency 3039system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63611.111111 # average ReadReq mshr uncacheable latency 3040system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 74287.640228 # average ReadReq mshr uncacheable latency 3041system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 94467.846634 # average ReadReq mshr uncacheable latency 3042system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 145636.010011 # average WriteReq mshr uncacheable latency 3043system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 88614.605858 # average WriteReq mshr uncacheable latency 3044system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 138052.535948 # average WriteReq mshr uncacheable latency 3045system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60948.109240 # average overall mshr uncacheable latency 3046system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 147997.090572 # average overall mshr uncacheable latency 3047system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63611.111111 # average overall mshr uncacheable latency 3048system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81455.350118 # average overall mshr uncacheable latency 3049system.l2c.overall_avg_mshr_uncacheable_latency::total 107392.516300 # average overall mshr uncacheable latency 3050system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 3051system.membus.trans_dist::ReadReq 709274 # Transaction distribution 3052system.membus.trans_dist::ReadResp 709274 # Transaction distribution 3053system.membus.trans_dist::WriteReq 38250 # Transaction distribution 3054system.membus.trans_dist::WriteResp 38250 # Transaction distribution 3055system.membus.trans_dist::Writeback 981258 # Transaction distribution 3056system.membus.trans_dist::WriteInvalidateReq 638260 # Transaction distribution 3057system.membus.trans_dist::WriteInvalidateResp 638259 # Transaction distribution 3058system.membus.trans_dist::UpgradeReq 441618 # Transaction distribution 3059system.membus.trans_dist::SCUpgradeReq 290995 # Transaction distribution 3060system.membus.trans_dist::UpgradeResp 111840 # Transaction distribution 3061system.membus.trans_dist::SCUpgradeFailReq 38 # Transaction distribution 3062system.membus.trans_dist::ReadExReq 127489 # Transaction distribution 3063system.membus.trans_dist::ReadExResp 110378 # Transaction distribution 3064system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122858 # Packet count per connected master and slave (bytes) 3065system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) 3066system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25102 # Packet count per connected master and slave (bytes) 3067system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4347669 # Packet count per connected master and slave (bytes) 3068system.membus.pkt_count_system.l2c.mem_side::total 4495681 # Packet count per connected master and slave (bytes) 3069system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336711 # Packet count per connected master and slave (bytes) 3070system.membus.pkt_count_system.iocache.mem_side::total 336711 # Packet count per connected master and slave (bytes) 3071system.membus.pkt_count::total 4832392 # Packet count per connected master and slave (bytes) 3072system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155896 # Cumulative packet size per connected master and slave (bytes) 3073system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) 3074system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50204 # Cumulative packet size per connected master and slave (bytes) 3075system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 139364352 # Cumulative packet size per connected master and slave (bytes) 3076system.membus.pkt_size_system.l2c.mem_side::total 139571776 # Cumulative packet size per connected master and slave (bytes) 3077system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14131264 # Cumulative packet size per connected master and slave (bytes) 3078system.membus.pkt_size_system.iocache.mem_side::total 14131264 # Cumulative packet size per connected master and slave (bytes) 3079system.membus.pkt_size::total 153703040 # Cumulative packet size per connected master and slave (bytes) 3080system.membus.snoops 640714 # Total snoops (count) 3081system.membus.snoop_fanout::samples 3227461 # Request fanout histogram 3082system.membus.snoop_fanout::mean 1 # Request fanout histogram 3083system.membus.snoop_fanout::stdev 0 # Request fanout histogram 3084system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3085system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3086system.membus.snoop_fanout::1 3227461 100.00% 100.00% # Request fanout histogram 3087system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3088system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3089system.membus.snoop_fanout::min_value 1 # Request fanout histogram 3090system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3091system.membus.snoop_fanout::total 3227461 # Request fanout histogram 3092system.membus.reqLayer0.occupancy 110051499 # Layer occupancy (ticks) 3093system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3094system.membus.reqLayer1.occupancy 33484 # Layer occupancy (ticks) 3095system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3096system.membus.reqLayer2.occupancy 20984500 # Layer occupancy (ticks) 3097system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3098system.membus.reqLayer5.occupancy 9462597488 # Layer occupancy (ticks) 3099system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3100system.membus.respLayer2.occupancy 4943193797 # Layer occupancy (ticks) 3101system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3102system.membus.respLayer3.occupancy 152223017 # Layer occupancy (ticks) 3103system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3104system.realview.ethernet.txBytes 966 # Bytes Transmitted 3105system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3106system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3107system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3108system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3109system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3110system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3111system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3112system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3113system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 3114system.realview.ethernet.totPackets 3 # Total Packets 3115system.realview.ethernet.totBytes 966 # Total Bytes 3116system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 3117system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 3118system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 3119system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3120system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 3121system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3122system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3123system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 3124system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3125system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3126system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 3127system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3128system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3129system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 3130system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3131system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3132system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 3133system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3134system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3135system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 3136system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3137system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3138system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3139system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3140system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3141system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3142system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3143system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3144system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3145system.realview.ethernet.droppedPackets 0 # number of packets dropped 3146system.toL2Bus.trans_dist::ReadReq 4701983 # Transaction distribution 3147system.toL2Bus.trans_dist::ReadResp 4694752 # Transaction distribution 3148system.toL2Bus.trans_dist::WriteReq 38250 # Transaction distribution 3149system.toL2Bus.trans_dist::WriteResp 38250 # Transaction distribution 3150system.toL2Bus.trans_dist::Writeback 2214381 # Transaction distribution 3151system.toL2Bus.trans_dist::WriteInvalidateReq 919435 # Transaction distribution 3152system.toL2Bus.trans_dist::WriteInvalidateResp 812281 # Transaction distribution 3153system.toL2Bus.trans_dist::UpgradeReq 489803 # Transaction distribution 3154system.toL2Bus.trans_dist::SCUpgradeReq 302708 # Transaction distribution 3155system.toL2Bus.trans_dist::UpgradeResp 792511 # Transaction distribution 3156system.toL2Bus.trans_dist::SCUpgradeFailReq 125 # Transaction distribution 3157system.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution 3158system.toL2Bus.trans_dist::ReadExReq 280473 # Transaction distribution 3159system.toL2Bus.trans_dist::ReadExResp 280473 # Transaction distribution 3160system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7857713 # Packet count per connected master and slave (bytes) 3161system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6052239 # Packet count per connected master and slave (bytes) 3162system.toL2Bus.pkt_count::total 13909952 # Packet count per connected master and slave (bytes) 3163system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 261128039 # Cumulative packet size per connected master and slave (bytes) 3164system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 189974361 # Cumulative packet size per connected master and slave (bytes) 3165system.toL2Bus.pkt_size::total 451102400 # Cumulative packet size per connected master and slave (bytes) 3166system.toL2Bus.snoops 1657293 # Total snoops (count) 3167system.toL2Bus.snoop_fanout::samples 8947338 # Request fanout histogram 3168system.toL2Bus.snoop_fanout::mean 1.012974 # Request fanout histogram 3169system.toL2Bus.snoop_fanout::stdev 0.113161 # Request fanout histogram 3170system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3171system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3172system.toL2Bus.snoop_fanout::1 8831258 98.70% 98.70% # Request fanout histogram 3173system.toL2Bus.snoop_fanout::2 116080 1.30% 100.00% # Request fanout histogram 3174system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3175system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 3176system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3177system.toL2Bus.snoop_fanout::total 8947338 # Request fanout histogram 3178system.toL2Bus.reqLayer0.occupancy 7728831785 # Layer occupancy (ticks) 3179system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3180system.toL2Bus.snoopLayer0.occupancy 2539500 # Layer occupancy (ticks) 3181system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3182system.toL2Bus.respLayer0.occupancy 4493592227 # Layer occupancy (ticks) 3183system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3184system.toL2Bus.respLayer1.occupancy 3891101888 # Layer occupancy (ticks) 3185system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3186 3187---------- End Simulation Statistics ---------- 3188