stats.txt revision 11680
110515SAli.Saidi@ARM.com 210515SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 311680SCurtis.Dunham@arm.comsim_seconds 47.554910 # Number of seconds simulated 411680SCurtis.Dunham@arm.comsim_ticks 47554910274000 # Number of ticks simulated 511680SCurtis.Dunham@arm.comfinal_tick 47554910274000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 711680SCurtis.Dunham@arm.comhost_inst_rate 172972 # Simulator instruction rate (inst/s) 811680SCurtis.Dunham@arm.comhost_op_rate 203472 # Simulator op (including micro ops) rate (op/s) 911680SCurtis.Dunham@arm.comhost_tick_rate 9377554592 # Simulator tick rate (ticks/s) 1011680SCurtis.Dunham@arm.comhost_mem_usage 769556 # Number of bytes of host memory used 1111680SCurtis.Dunham@arm.comhost_seconds 5071.14 # Real time elapsed on the host 1211680SCurtis.Dunham@arm.comsim_insts 877166784 # Number of instructions simulated 1311680SCurtis.Dunham@arm.comsim_ops 1031833041 # Number of ops (including micro ops) simulated 1410515SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611680SCurtis.Dunham@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 1711680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 127616 # Number of bytes read from this memory 1811680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 113728 # Number of bytes read from this memory 1911680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.inst 7300032 # Number of bytes read from this memory 2011680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.data 13854920 # Number of bytes read from this memory 2111680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.l2cache.prefetcher 13786176 # Number of bytes read from this memory 2211680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 105536 # Number of bytes read from this memory 2311680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.itb.walker 93440 # Number of bytes read from this memory 2411680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.inst 3887680 # Number of bytes read from this memory 2511680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.data 9545552 # Number of bytes read from this memory 2611680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.l2cache.prefetcher 11958848 # Number of bytes read from this memory 2711680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::realview.ide 442112 # Number of bytes read from this memory 2811680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 61215640 # Number of bytes read from this memory 2911680SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 7300032 # Number of instructions bytes read from this memory 3011680SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 3887680 # Number of instructions bytes read from this memory 3111680SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 11187712 # Number of instructions bytes read from this memory 3211680SCurtis.Dunham@arm.comsystem.physmem.bytes_written::writebacks 74339904 # Number of bytes written to this memory 3310827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 3410636Snilay@cs.wisc.edusystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3511680SCurtis.Dunham@arm.comsystem.physmem.bytes_written::total 74360488 # Number of bytes written to this memory 3611680SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 1994 # Number of read requests responded to by this memory 3711680SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.itb.walker 1777 # Number of read requests responded to by this memory 3811680SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.inst 114063 # Number of read requests responded to by this memory 3911680SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.data 216496 # Number of read requests responded to by this memory 4011680SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.l2cache.prefetcher 215409 # Number of read requests responded to by this memory 4111680SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 1649 # Number of read requests responded to by this memory 4211680SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.itb.walker 1460 # Number of read requests responded to by this memory 4311680SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.inst 60745 # Number of read requests responded to by this memory 4411680SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.data 149162 # Number of read requests responded to by this memory 4511680SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.l2cache.prefetcher 186857 # Number of read requests responded to by this memory 4611680SCurtis.Dunham@arm.comsystem.physmem.num_reads::realview.ide 6908 # Number of read requests responded to by this memory 4711680SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 956520 # Number of read requests responded to by this memory 4811680SCurtis.Dunham@arm.comsystem.physmem.num_writes::writebacks 1161561 # Number of write requests responded to by this memory 4910827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 5010636Snilay@cs.wisc.edusystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 5111680SCurtis.Dunham@arm.comsystem.physmem.num_writes::total 1164135 # Number of write requests responded to by this memory 5211680SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 2684 # Total read bandwidth from this memory (bytes/s) 5311680SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.itb.walker 2392 # Total read bandwidth from this memory (bytes/s) 5411680SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.inst 153507 # Total read bandwidth from this memory (bytes/s) 5511680SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.data 291346 # Total read bandwidth from this memory (bytes/s) 5611680SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.l2cache.prefetcher 289900 # Total read bandwidth from this memory (bytes/s) 5711680SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 2219 # Total read bandwidth from this memory (bytes/s) 5811680SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.itb.walker 1965 # Total read bandwidth from this memory (bytes/s) 5911680SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.inst 81751 # Total read bandwidth from this memory (bytes/s) 6011680SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.data 200727 # Total read bandwidth from this memory (bytes/s) 6111680SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.l2cache.prefetcher 251475 # Total read bandwidth from this memory (bytes/s) 6211680SCurtis.Dunham@arm.comsystem.physmem.bw_read::realview.ide 9297 # Total read bandwidth from this memory (bytes/s) 6311680SCurtis.Dunham@arm.comsystem.physmem.bw_read::total 1287262 # Total read bandwidth from this memory (bytes/s) 6411680SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu0.inst 153507 # Instruction read bandwidth from this memory (bytes/s) 6511680SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu1.inst 81751 # Instruction read bandwidth from this memory (bytes/s) 6611680SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::total 235259 # Instruction read bandwidth from this memory (bytes/s) 6711680SCurtis.Dunham@arm.comsystem.physmem.bw_write::writebacks 1563243 # Write bandwidth from this memory (bytes/s) 6811680SCurtis.Dunham@arm.comsystem.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) 6910636Snilay@cs.wisc.edusystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 7011680SCurtis.Dunham@arm.comsystem.physmem.bw_write::total 1563676 # Write bandwidth from this memory (bytes/s) 7111680SCurtis.Dunham@arm.comsystem.physmem.bw_total::writebacks 1563243 # Total bandwidth to/from this memory (bytes/s) 7211680SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 2684 # Total bandwidth to/from this memory (bytes/s) 7311680SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.itb.walker 2392 # Total bandwidth to/from this memory (bytes/s) 7411680SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.inst 153507 # Total bandwidth to/from this memory (bytes/s) 7511680SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.data 291778 # Total bandwidth to/from this memory (bytes/s) 7611680SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.l2cache.prefetcher 289900 # Total bandwidth to/from this memory (bytes/s) 7711680SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 2219 # Total bandwidth to/from this memory (bytes/s) 7811680SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.itb.walker 1965 # Total bandwidth to/from this memory (bytes/s) 7911680SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.inst 81751 # Total bandwidth to/from this memory (bytes/s) 8011680SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.data 200727 # Total bandwidth to/from this memory (bytes/s) 8111680SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.l2cache.prefetcher 251475 # Total bandwidth to/from this memory (bytes/s) 8211680SCurtis.Dunham@arm.comsystem.physmem.bw_total::realview.ide 9297 # Total bandwidth to/from this memory (bytes/s) 8311680SCurtis.Dunham@arm.comsystem.physmem.bw_total::total 2850939 # Total bandwidth to/from this memory (bytes/s) 8411680SCurtis.Dunham@arm.comsystem.physmem.readReqs 956520 # Number of read requests accepted 8511680SCurtis.Dunham@arm.comsystem.physmem.writeReqs 1164135 # Number of write requests accepted 8611680SCurtis.Dunham@arm.comsystem.physmem.readBursts 956520 # Number of DRAM read bursts, including those serviced by the write queue 8711680SCurtis.Dunham@arm.comsystem.physmem.writeBursts 1164135 # Number of DRAM write bursts, including those merged in the write queue 8811680SCurtis.Dunham@arm.comsystem.physmem.bytesReadDRAM 61192448 # Total number of bytes read from DRAM 8911680SCurtis.Dunham@arm.comsystem.physmem.bytesReadWrQ 24832 # Total number of bytes read from write queue 9011680SCurtis.Dunham@arm.comsystem.physmem.bytesWritten 74357824 # Total number of bytes written to DRAM 9111680SCurtis.Dunham@arm.comsystem.physmem.bytesReadSys 61215640 # Total read bytes from the system interface side 9211680SCurtis.Dunham@arm.comsystem.physmem.bytesWrittenSys 74360488 # Total written bytes from the system interface side 9311680SCurtis.Dunham@arm.comsystem.physmem.servicedByWrQ 388 # Number of DRAM read bursts serviced by the write queue 9411680SCurtis.Dunham@arm.comsystem.physmem.mergedWrBursts 2263 # Number of DRAM write bursts merged with an existing one 9511336Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 9611680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::0 50657 # Per bank write bursts 9711680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::1 60930 # Per bank write bursts 9811680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::2 49716 # Per bank write bursts 9911680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::3 55090 # Per bank write bursts 10011680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::4 56536 # Per bank write bursts 10111680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::5 68947 # Per bank write bursts 10211680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::6 58003 # Per bank write bursts 10311680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::7 60908 # Per bank write bursts 10411680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::8 53263 # Per bank write bursts 10511680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::9 106420 # Per bank write bursts 10611680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::10 50504 # Per bank write bursts 10711680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::11 59458 # Per bank write bursts 10811680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::12 56712 # Per bank write bursts 10911680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::13 60494 # Per bank write bursts 11011680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::14 55357 # Per bank write bursts 11111680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::15 53137 # Per bank write bursts 11211680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::0 68064 # Per bank write bursts 11311680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::1 74120 # Per bank write bursts 11411680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::2 68663 # Per bank write bursts 11511680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::3 72095 # Per bank write bursts 11611680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::4 73476 # Per bank write bursts 11711680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::5 80505 # Per bank write bursts 11811680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::6 71958 # Per bank write bursts 11911680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::7 74882 # Per bank write bursts 12011680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::8 69253 # Per bank write bursts 12111680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::9 72875 # Per bank write bursts 12211680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::10 68876 # Per bank write bursts 12311680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::11 75926 # Per bank write bursts 12411680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::12 72095 # Per bank write bursts 12511680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::13 75544 # Per bank write bursts 12611680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::14 71950 # Per bank write bursts 12711680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::15 71559 # Per bank write bursts 12810515SAli.Saidi@ARM.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 12911680SCurtis.Dunham@arm.comsystem.physmem.numWrRetry 408 # Number of times write queue was full causing retry 13011680SCurtis.Dunham@arm.comsystem.physmem.totGap 47554908178500 # Total gap between requests 13110515SAli.Saidi@ARM.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 13210515SAli.Saidi@ARM.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 13310515SAli.Saidi@ARM.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 13410827Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 25 # Read request sizes (log2) 13510515SAli.Saidi@ARM.comsystem.physmem.readPktSize::4 5 # Read request sizes (log2) 13610515SAli.Saidi@ARM.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 13711680SCurtis.Dunham@arm.comsystem.physmem.readPktSize::6 956490 # Read request sizes (log2) 13810515SAli.Saidi@ARM.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 13910515SAli.Saidi@ARM.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 14010515SAli.Saidi@ARM.comsystem.physmem.writePktSize::2 2 # Write request sizes (log2) 14110827Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 14210515SAli.Saidi@ARM.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 14310515SAli.Saidi@ARM.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 14411680SCurtis.Dunham@arm.comsystem.physmem.writePktSize::6 1161561 # Write request sizes (log2) 14511680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::0 589555 # What read queue length does an incoming req see 14611680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::1 157739 # What read queue length does an incoming req see 14711680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::2 46445 # What read queue length does an incoming req see 14811680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::3 36293 # What read queue length does an incoming req see 14911680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::4 27945 # What read queue length does an incoming req see 15011680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::5 25583 # What read queue length does an incoming req see 15111680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::6 23391 # What read queue length does an incoming req see 15211680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::7 20914 # What read queue length does an incoming req see 15311680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::8 18402 # What read queue length does an incoming req see 15411680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::9 4361 # What read queue length does an incoming req see 15511680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::10 1587 # What read queue length does an incoming req see 15611680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::11 1163 # What read queue length does an incoming req see 15711680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::12 874 # What read queue length does an incoming req see 15811680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::13 609 # What read queue length does an incoming req see 15911680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::14 336 # What read queue length does an incoming req see 16011680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::15 287 # What read queue length does an incoming req see 16111680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::16 249 # What read queue length does an incoming req see 16211680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::17 205 # What read queue length does an incoming req see 16311680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::18 102 # What read queue length does an incoming req see 16411680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::19 84 # What read queue length does an incoming req see 16511680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see 16611680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 16711680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 16811353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 16911353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 17010515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 17110515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 17210515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 17310515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 17410515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 17510515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 17610515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 17710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 17810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 17910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 18010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 18110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 18210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 18310515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 18410515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 18510515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 18610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 18710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 18810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 18910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 19010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 19110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 19211680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::15 24143 # What write queue length does an incoming req see 19311680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::16 31849 # What write queue length does an incoming req see 19411680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::17 48338 # What write queue length does an incoming req see 19511680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::18 55864 # What write queue length does an incoming req see 19611680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::19 61058 # What write queue length does an incoming req see 19711680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::20 64206 # What write queue length does an incoming req see 19811680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::21 66032 # What write queue length does an incoming req see 19911680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::22 67782 # What write queue length does an incoming req see 20011680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::23 70569 # What write queue length does an incoming req see 20111680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::24 70728 # What write queue length does an incoming req see 20211680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::25 73352 # What write queue length does an incoming req see 20311680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::26 74938 # What write queue length does an incoming req see 20411680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::27 72063 # What write queue length does an incoming req see 20511680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::28 70410 # What write queue length does an incoming req see 20611680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::29 71450 # What write queue length does an incoming req see 20711680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::30 74135 # What write queue length does an incoming req see 20811680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::31 66609 # What write queue length does an incoming req see 20911680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::32 62837 # What write queue length does an incoming req see 21011680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::33 4834 # What write queue length does an incoming req see 21111680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::34 2922 # What write queue length does an incoming req see 21211680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::35 2290 # What write queue length does an incoming req see 21311680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::36 1924 # What write queue length does an incoming req see 21411680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::37 1530 # What write queue length does an incoming req see 21511680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::38 1398 # What write queue length does an incoming req see 21611680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::39 1235 # What write queue length does an incoming req see 21711680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::40 995 # What write queue length does an incoming req see 21811680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::41 863 # What write queue length does an incoming req see 21911680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::42 908 # What write queue length does an incoming req see 22011680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::43 855 # What write queue length does an incoming req see 22111680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::44 856 # What write queue length does an incoming req see 22211680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::45 772 # What write queue length does an incoming req see 22311680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::46 896 # What write queue length does an incoming req see 22411680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::47 762 # What write queue length does an incoming req see 22511680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::48 737 # What write queue length does an incoming req see 22611680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::49 763 # What write queue length does an incoming req see 22711680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::50 757 # What write queue length does an incoming req see 22811680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::51 750 # What write queue length does an incoming req see 22911680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::52 714 # What write queue length does an incoming req see 23011680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::53 706 # What write queue length does an incoming req see 23111680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::54 687 # What write queue length does an incoming req see 23211680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::55 740 # What write queue length does an incoming req see 23311680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::56 794 # What write queue length does an incoming req see 23411680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::57 717 # What write queue length does an incoming req see 23511680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::58 562 # What write queue length does an incoming req see 23611680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::59 748 # What write queue length does an incoming req see 23711680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::60 1309 # What write queue length does an incoming req see 23811680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::61 1089 # What write queue length does an incoming req see 23911680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::62 448 # What write queue length does an incoming req see 24011680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::63 933 # What write queue length does an incoming req see 24111680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::samples 917155 # Bytes accessed per row activation 24211680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::mean 147.793592 # Bytes accessed per row activation 24311680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::gmean 99.753334 # Bytes accessed per row activation 24411680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::stdev 195.501852 # Bytes accessed per row activation 24511680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::0-127 602356 65.68% 65.68% # Bytes accessed per row activation 24611680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::128-255 188931 20.60% 86.28% # Bytes accessed per row activation 24711680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::256-383 45653 4.98% 91.25% # Bytes accessed per row activation 24811680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::384-511 20839 2.27% 93.53% # Bytes accessed per row activation 24911680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::512-639 15350 1.67% 95.20% # Bytes accessed per row activation 25011680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::640-767 9574 1.04% 96.24% # Bytes accessed per row activation 25111680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::768-895 6849 0.75% 96.99% # Bytes accessed per row activation 25211680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::896-1023 5486 0.60% 97.59% # Bytes accessed per row activation 25311680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::1024-1151 22117 2.41% 100.00% # Bytes accessed per row activation 25411680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::total 917155 # Bytes accessed per row activation 25511680SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::samples 56545 # Reads before turning the bus around for writes 25611680SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::mean 16.908586 # Reads before turning the bus around for writes 25711680SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::stdev 165.794592 # Reads before turning the bus around for writes 25811680SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::0-1023 56543 100.00% 100.00% # Reads before turning the bus around for writes 25911353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 26011353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes 26111680SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::total 56545 # Reads before turning the bus around for writes 26211680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::samples 56545 # Writes before turning the bus around for reads 26311680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::mean 20.547193 # Writes before turning the bus around for reads 26411680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::gmean 18.712168 # Writes before turning the bus around for reads 26511680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::stdev 14.106429 # Writes before turning the bus around for reads 26611680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::16-19 48673 86.08% 86.08% # Writes before turning the bus around for reads 26711680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::20-23 2227 3.94% 90.02% # Writes before turning the bus around for reads 26811680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::24-27 713 1.26% 91.28% # Writes before turning the bus around for reads 26911680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::28-31 569 1.01% 92.28% # Writes before turning the bus around for reads 27011680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::32-35 930 1.64% 93.93% # Writes before turning the bus around for reads 27111680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::36-39 406 0.72% 94.65% # Writes before turning the bus around for reads 27211680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::40-43 286 0.51% 95.15% # Writes before turning the bus around for reads 27311680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::44-47 280 0.50% 95.65% # Writes before turning the bus around for reads 27411680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::48-51 183 0.32% 95.97% # Writes before turning the bus around for reads 27511680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::52-55 127 0.22% 96.20% # Writes before turning the bus around for reads 27611680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::56-59 115 0.20% 96.40% # Writes before turning the bus around for reads 27711680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::60-63 143 0.25% 96.65% # Writes before turning the bus around for reads 27811680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::64-67 579 1.02% 97.68% # Writes before turning the bus around for reads 27911680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::68-71 140 0.25% 97.92% # Writes before turning the bus around for reads 28011680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::72-75 130 0.23% 98.15% # Writes before turning the bus around for reads 28111680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::76-79 128 0.23% 98.38% # Writes before turning the bus around for reads 28211680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::80-83 106 0.19% 98.57% # Writes before turning the bus around for reads 28311680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::84-87 75 0.13% 98.70% # Writes before turning the bus around for reads 28411680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::88-91 85 0.15% 98.85% # Writes before turning the bus around for reads 28511680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::92-95 94 0.17% 99.02% # Writes before turning the bus around for reads 28611680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::96-99 75 0.13% 99.15% # Writes before turning the bus around for reads 28711680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::100-103 62 0.11% 99.26% # Writes before turning the bus around for reads 28811680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::104-107 61 0.11% 99.37% # Writes before turning the bus around for reads 28911680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::108-111 71 0.13% 99.49% # Writes before turning the bus around for reads 29011680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::112-115 39 0.07% 99.56% # Writes before turning the bus around for reads 29111680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::116-119 37 0.07% 99.63% # Writes before turning the bus around for reads 29211680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::120-123 45 0.08% 99.71% # Writes before turning the bus around for reads 29311680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::124-127 34 0.06% 99.77% # Writes before turning the bus around for reads 29411680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::128-131 51 0.09% 99.86% # Writes before turning the bus around for reads 29511680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::132-135 18 0.03% 99.89% # Writes before turning the bus around for reads 29611680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::136-139 12 0.02% 99.91% # Writes before turning the bus around for reads 29711680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::140-143 17 0.03% 99.94% # Writes before turning the bus around for reads 29811680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::144-147 4 0.01% 99.95% # Writes before turning the bus around for reads 29911680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::148-151 3 0.01% 99.95% # Writes before turning the bus around for reads 30011680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::152-155 2 0.00% 99.96% # Writes before turning the bus around for reads 30111680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::156-159 3 0.01% 99.96% # Writes before turning the bus around for reads 30211680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::160-163 3 0.01% 99.97% # Writes before turning the bus around for reads 30311680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::164-167 2 0.00% 99.97% # Writes before turning the bus around for reads 30411680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::172-175 3 0.01% 99.98% # Writes before turning the bus around for reads 30511680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::176-179 3 0.01% 99.98% # Writes before turning the bus around for reads 30611680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::188-191 2 0.00% 99.98% # Writes before turning the bus around for reads 30711680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::192-195 5 0.01% 99.99% # Writes before turning the bus around for reads 30811680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::196-199 1 0.00% 99.99% # Writes before turning the bus around for reads 30911680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads 31011680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::204-207 1 0.00% 100.00% # Writes before turning the bus around for reads 31111680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::228-231 1 0.00% 100.00% # Writes before turning the bus around for reads 31211680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::total 56545 # Writes before turning the bus around for reads 31311680SCurtis.Dunham@arm.comsystem.physmem.totQLat 49127716705 # Total ticks spent queuing 31411680SCurtis.Dunham@arm.comsystem.physmem.totMemAccLat 67055191705 # Total ticks spent from burst creation until serviced by the DRAM 31511680SCurtis.Dunham@arm.comsystem.physmem.totBusLat 4780660000 # Total ticks spent in databus transfers 31611680SCurtis.Dunham@arm.comsystem.physmem.avgQLat 51381.73 # Average queueing delay per DRAM burst 31710515SAli.Saidi@ARM.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 31811680SCurtis.Dunham@arm.comsystem.physmem.avgMemAccLat 70131.73 # Average memory access latency per DRAM burst 31911680SCurtis.Dunham@arm.comsystem.physmem.avgRdBW 1.29 # Average DRAM read bandwidth in MiByte/s 32011680SCurtis.Dunham@arm.comsystem.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MiByte/s 32111680SCurtis.Dunham@arm.comsystem.physmem.avgRdBWSys 1.29 # Average system read bandwidth in MiByte/s 32211680SCurtis.Dunham@arm.comsystem.physmem.avgWrBWSys 1.56 # Average system write bandwidth in MiByte/s 32310515SAli.Saidi@ARM.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 32411680SCurtis.Dunham@arm.comsystem.physmem.busUtil 0.02 # Data bus utilization in percentage 32511353Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 32611441Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 32711680SCurtis.Dunham@arm.comsystem.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing 32811680SCurtis.Dunham@arm.comsystem.physmem.avgWrQLen 22.69 # Average write queue length when enqueuing 32911680SCurtis.Dunham@arm.comsystem.physmem.readRowHits 713884 # Number of row buffer hits during reads 33011680SCurtis.Dunham@arm.comsystem.physmem.writeRowHits 486930 # Number of row buffer hits during writes 33111680SCurtis.Dunham@arm.comsystem.physmem.readRowHitRate 74.66 # Row buffer hit rate for reads 33211680SCurtis.Dunham@arm.comsystem.physmem.writeRowHitRate 41.91 # Row buffer hit rate for writes 33311680SCurtis.Dunham@arm.comsystem.physmem.avgGap 22424632.10 # Average gap between requests 33411680SCurtis.Dunham@arm.comsystem.physmem.pageHitRate 56.70 # Row buffer hit rate, read and write combined 33511680SCurtis.Dunham@arm.comsystem.physmem_0.actEnergy 3312517320 # Energy for activate commands per rank (pJ) 33611680SCurtis.Dunham@arm.comsystem.physmem_0.preEnergy 1760633325 # Energy for precharge commands per rank (pJ) 33711680SCurtis.Dunham@arm.comsystem.physmem_0.readEnergy 3290019180 # Energy for read commands per rank (pJ) 33811680SCurtis.Dunham@arm.comsystem.physmem_0.writeEnergy 3047242860 # Energy for write commands per rank (pJ) 33911680SCurtis.Dunham@arm.comsystem.physmem_0.refreshEnergy 39654114240.000008 # Energy for refresh commands per rank (pJ) 34011680SCurtis.Dunham@arm.comsystem.physmem_0.actBackEnergy 43514746200 # Energy for active background per rank (pJ) 34111680SCurtis.Dunham@arm.comsystem.physmem_0.preBackEnergy 2086179840 # Energy for precharge background per rank (pJ) 34211680SCurtis.Dunham@arm.comsystem.physmem_0.actPowerDownEnergy 77547983010 # Energy for active power-down per rank (pJ) 34311680SCurtis.Dunham@arm.comsystem.physmem_0.prePowerDownEnergy 55697482080 # Energy for precharge power-down per rank (pJ) 34411680SCurtis.Dunham@arm.comsystem.physmem_0.selfRefreshEnergy 11319929946090 # Energy for self refresh per rank (pJ) 34511680SCurtis.Dunham@arm.comsystem.physmem_0.totalEnergy 11549857795695 # Total energy per rank (pJ) 34611680SCurtis.Dunham@arm.comsystem.physmem_0.averagePower 242.874137 # Core power per rank (mW) 34711680SCurtis.Dunham@arm.comsystem.physmem_0.totalIdleTime 47454012976233 # Total Idle time Per DRAM Rank 34811680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::IDLE 3696049077 # Time in different power states 34911680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::REF 16847240000 # Time in different power states 35011680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::SREF 47138905885000 # Time in different power states 35111680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 145045339612 # Time in different power states 35211680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT 80353958440 # Time in different power states 35311680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 170061801871 # Time in different power states 35411680SCurtis.Dunham@arm.comsystem.physmem_1.actEnergy 3235997940 # Energy for activate commands per rank (pJ) 35511680SCurtis.Dunham@arm.comsystem.physmem_1.preEnergy 1719969900 # Energy for precharge commands per rank (pJ) 35611680SCurtis.Dunham@arm.comsystem.physmem_1.readEnergy 3536763300 # Energy for read commands per rank (pJ) 35711680SCurtis.Dunham@arm.comsystem.physmem_1.writeEnergy 3017567160 # Energy for write commands per rank (pJ) 35811680SCurtis.Dunham@arm.comsystem.physmem_1.refreshEnergy 38496747120.000008 # Energy for refresh commands per rank (pJ) 35911680SCurtis.Dunham@arm.comsystem.physmem_1.actBackEnergy 44079949650 # Energy for active background per rank (pJ) 36011680SCurtis.Dunham@arm.comsystem.physmem_1.preBackEnergy 2012350560 # Energy for precharge background per rank (pJ) 36111680SCurtis.Dunham@arm.comsystem.physmem_1.actPowerDownEnergy 72751641060 # Energy for active power-down per rank (pJ) 36211680SCurtis.Dunham@arm.comsystem.physmem_1.prePowerDownEnergy 54144086400 # Energy for precharge power-down per rank (pJ) 36311680SCurtis.Dunham@arm.comsystem.physmem_1.selfRefreshEnergy 11323086477345 # Energy for self refresh per rank (pJ) 36411680SCurtis.Dunham@arm.comsystem.physmem_1.totalEnergy 11546099446905 # Total energy per rank (pJ) 36511680SCurtis.Dunham@arm.comsystem.physmem_1.averagePower 242.795105 # Core power per rank (mW) 36611680SCurtis.Dunham@arm.comsystem.physmem_1.totalIdleTime 47452962329328 # Total Idle time Per DRAM Rank 36711680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::IDLE 3512995347 # Time in different power states 36811680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::REF 16356664000 # Time in different power states 36911680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::SREF 47152420144750 # Time in different power states 37011680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 141000345458 # Time in different power states 37111680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT 82076677575 # Time in different power states 37211680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 159543446870 # Time in different power states 37311680SCurtis.Dunham@arm.comsystem.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 37410636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory 37510636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 37611570SCurtis.Dunham@arm.comsystem.realview.nvmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory 37710636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 37811570SCurtis.Dunham@arm.comsystem.realview.nvmem.bytes_read::total 1388 # Number of bytes read from this memory 37910515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory 38011570SCurtis.Dunham@arm.comsystem.realview.nvmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory 38111570SCurtis.Dunham@arm.comsystem.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory 38210636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory 38310636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 38411570SCurtis.Dunham@arm.comsystem.realview.nvmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory 38510636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 38611570SCurtis.Dunham@arm.comsystem.realview.nvmem.num_reads::total 27 # Number of read requests responded to by this memory 38710636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) 38810636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 38911680SCurtis.Dunham@arm.comsystem.realview.nvmem.bw_read::cpu1.inst 13 # Total read bandwidth from this memory (bytes/s) 39010636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 39111570SCurtis.Dunham@arm.comsystem.realview.nvmem.bw_read::total 29 # Total read bandwidth from this memory (bytes/s) 39210515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) 39311680SCurtis.Dunham@arm.comsystem.realview.nvmem.bw_inst_read::cpu1.inst 13 # Instruction read bandwidth from this memory (bytes/s) 39411570SCurtis.Dunham@arm.comsystem.realview.nvmem.bw_inst_read::total 28 # Instruction read bandwidth from this memory (bytes/s) 39510636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) 39610636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 39711680SCurtis.Dunham@arm.comsystem.realview.nvmem.bw_total::cpu1.inst 13 # Total bandwidth to/from this memory (bytes/s) 39810636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 39911570SCurtis.Dunham@arm.comsystem.realview.nvmem.bw_total::total 29 # Total bandwidth to/from this memory (bytes/s) 40011680SCurtis.Dunham@arm.comsystem.realview.vram.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 40111680SCurtis.Dunham@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 40211680SCurtis.Dunham@arm.comsystem.bridge.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 40310585Sandreas.hansson@arm.comsystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 40410585Sandreas.hansson@arm.comsystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 40510585Sandreas.hansson@arm.comsystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 40611606Sandreas.sandberg@arm.comsystem.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 40711606Sandreas.sandberg@arm.comsystem.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 40811606Sandreas.sandberg@arm.comsystem.cf0.dma_write_txs 1670 # Number of DMA write transactions. 40911680SCurtis.Dunham@arm.comsystem.cpu0.branchPred.lookups 137627857 # Number of BP lookups 41011680SCurtis.Dunham@arm.comsystem.cpu0.branchPred.condPredicted 96352530 # Number of conditional branches predicted 41111680SCurtis.Dunham@arm.comsystem.cpu0.branchPred.condIncorrect 6353129 # Number of conditional branches incorrect 41211680SCurtis.Dunham@arm.comsystem.cpu0.branchPred.BTBLookups 102612546 # Number of BTB lookups 41311680SCurtis.Dunham@arm.comsystem.cpu0.branchPred.BTBHits 71378761 # Number of BTB hits 41410585Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 41511680SCurtis.Dunham@arm.comsystem.cpu0.branchPred.BTBHitPct 69.561436 # BTB Hit Percentage 41611680SCurtis.Dunham@arm.comsystem.cpu0.branchPred.usedRAS 16463463 # Number of times the RAS was used to get a target. 41711680SCurtis.Dunham@arm.comsystem.cpu0.branchPred.RASInCorrect 1088270 # Number of incorrect RAS predictions. 41811680SCurtis.Dunham@arm.comsystem.cpu0.branchPred.indirectLookups 3669510 # Number of indirect predictor lookups. 41911680SCurtis.Dunham@arm.comsystem.cpu0.branchPred.indirectHits 2436336 # Number of indirect target hits. 42011680SCurtis.Dunham@arm.comsystem.cpu0.branchPred.indirectMisses 1233174 # Number of indirect misses. 42111680SCurtis.Dunham@arm.comsystem.cpu0.branchPredindirectMispredicted 447439 # Number of mispredicted indirect branches. 42210515SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 42311680SCurtis.Dunham@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 42410628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 42510628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 42610628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 42710628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 42810628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 42910628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 43010628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 43110628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 43210585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 43310585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 43410585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 43510585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 43610585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 43710585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 43810585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 43910585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 44010585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 44110585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 44210585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 44310585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 44410585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 44510585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 44610585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 44710585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 44810585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 44910585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 45010585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 45110585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 45210585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 45311680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 45411680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walks 282889 # Table walker walks requested 45511680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksLong 282889 # Table walker walks initiated with long descriptors 45611680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9418 # Level at which table walker walks with long descriptors terminate 45711680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level3 82700 # Level at which table walker walks with long descriptors terminate 45811680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 282889 # Table walker wait (enqueue to first request) latency 45911680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0 282889 100.00% 100.00% # Table walker wait (enqueue to first request) latency 46011680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 282889 # Table walker wait (enqueue to first request) latency 46111680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::samples 92118 # Table walker service (enqueue to completion) latency 46211680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::mean 24516.006644 # Table walker service (enqueue to completion) latency 46311680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::gmean 22528.646157 # Table walker service (enqueue to completion) latency 46411680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::stdev 18042.498572 # Table walker service (enqueue to completion) latency 46511680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::0-65535 90947 98.73% 98.73% # Table walker service (enqueue to completion) latency 46611680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::65536-131071 867 0.94% 99.67% # Table walker service (enqueue to completion) latency 46711680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::131072-196607 159 0.17% 99.84% # Table walker service (enqueue to completion) latency 46811680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::196608-262143 56 0.06% 99.90% # Table walker service (enqueue to completion) latency 46911680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::262144-327679 44 0.05% 99.95% # Table walker service (enqueue to completion) latency 47011680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::327680-393215 20 0.02% 99.97% # Table walker service (enqueue to completion) latency 47111680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 99.98% # Table walker service (enqueue to completion) latency 47211680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.98% # Table walker service (enqueue to completion) latency 47311680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.98% # Table walker service (enqueue to completion) latency 47411680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::589824-655359 17 0.02% 100.00% # Table walker service (enqueue to completion) latency 47511680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 47611680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 47711680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::total 92118 # Table walker service (enqueue to completion) latency 47811680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksPending::samples 1049600704 # Table walker pending requests distribution 47911680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksPending::0 1049600704 100.00% 100.00% # Table walker pending requests distribution 48011680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksPending::total 1049600704 # Table walker pending requests distribution 48111680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 82700 89.78% 89.78% # Table walker page sizes translated 48211680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkPageSizes::2M 9418 10.22% 100.00% # Table walker page sizes translated 48311680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 92118 # Table walker page sizes translated 48411680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 282889 # Table walker requests started/completed, data/inst 48510628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 48611680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 282889 # Table walker requests started/completed, data/inst 48711680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 92118 # Table walker requests started/completed, data/inst 48810628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 48911680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 92118 # Table walker requests started/completed, data/inst 49011680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 375007 # Table walker requests started/completed, data/inst 49110585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_hits 0 # ITB inst hits 49210585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_misses 0 # ITB inst misses 49311680SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_hits 87675894 # DTB read hits 49411680SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_misses 234519 # DTB read misses 49511680SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_hits 78239753 # DTB write hits 49611680SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_misses 48370 # DTB write misses 49711441Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 49810585Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 49911680SCurtis.Dunham@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 40666 # Number of times TLB was flushed by MVA & ASID 50011680SCurtis.Dunham@arm.comsystem.cpu0.dtb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID 50111680SCurtis.Dunham@arm.comsystem.cpu0.dtb.flush_entries 38151 # Number of entries that have been flushed from TLB 50211680SCurtis.Dunham@arm.comsystem.cpu0.dtb.align_faults 2038 # Number of TLB faults due to alignment restrictions 50311680SCurtis.Dunham@arm.comsystem.cpu0.dtb.prefetch_faults 9397 # Number of TLB faults due to prefetch 50410585Sandreas.hansson@arm.comsystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 50511680SCurtis.Dunham@arm.comsystem.cpu0.dtb.perms_faults 11689 # Number of TLB faults due to permissions restrictions 50611680SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_accesses 87910413 # DTB read accesses 50711680SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_accesses 78288123 # DTB write accesses 50810585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 50911680SCurtis.Dunham@arm.comsystem.cpu0.dtb.hits 165915647 # DTB hits 51011680SCurtis.Dunham@arm.comsystem.cpu0.dtb.misses 282889 # DTB misses 51111680SCurtis.Dunham@arm.comsystem.cpu0.dtb.accesses 166198536 # DTB accesses 51211680SCurtis.Dunham@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 51310628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 51410628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 51510628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 51610628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 51710628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 51810628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 51910628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 52010628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 52110585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 52210585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 52310585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 52410585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 52510585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 52610585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 52710585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 52810585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 52910585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 53010585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 53110585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 53210585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 53310585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 53410585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 53510585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 53610585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 53710585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 53810585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 53910585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 54010585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 54110585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 54211680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 54311680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walks 69273 # Table walker walks requested 54411680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksLong 69273 # Table walker walks initiated with long descriptors 54511680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level2 583 # Level at which table walker walks with long descriptors terminate 54611680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level3 61330 # Level at which table walker walks with long descriptors terminate 54711680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 69273 # Table walker wait (enqueue to first request) latency 54811680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkWaitTime::0 69273 100.00% 100.00% # Table walker wait (enqueue to first request) latency 54911680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 69273 # Table walker wait (enqueue to first request) latency 55011680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::samples 61913 # Table walker service (enqueue to completion) latency 55111680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::mean 26255.972090 # Table walker service (enqueue to completion) latency 55211680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::gmean 24021.087370 # Table walker service (enqueue to completion) latency 55311680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::stdev 22669.077424 # Table walker service (enqueue to completion) latency 55411680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::0-65535 60695 98.03% 98.03% # Table walker service (enqueue to completion) latency 55511680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::65536-131071 852 1.38% 99.41% # Table walker service (enqueue to completion) latency 55611680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::131072-196607 248 0.40% 99.81% # Table walker service (enqueue to completion) latency 55711680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::196608-262143 49 0.08% 99.89% # Table walker service (enqueue to completion) latency 55811680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::262144-327679 14 0.02% 99.91% # Table walker service (enqueue to completion) latency 55911680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::327680-393215 11 0.02% 99.93% # Table walker service (enqueue to completion) latency 56011680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.94% # Table walker service (enqueue to completion) latency 56111680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.94% # Table walker service (enqueue to completion) latency 56211680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::589824-655359 39 0.06% 100.00% # Table walker service (enqueue to completion) latency 56311680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::total 61913 # Table walker service (enqueue to completion) latency 56411680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksPending::samples 1048830204 # Table walker pending requests distribution 56511680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksPending::0 1048830204 100.00% 100.00% # Table walker pending requests distribution 56611680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksPending::total 1048830204 # Table walker pending requests distribution 56711680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 61330 99.06% 99.06% # Table walker page sizes translated 56811680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkPageSizes::2M 583 0.94% 100.00% # Table walker page sizes translated 56911680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 61913 # Table walker page sizes translated 57010628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 57111680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 69273 # Table walker requests started/completed, data/inst 57211680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 69273 # Table walker requests started/completed, data/inst 57310628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 57411680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 61913 # Table walker requests started/completed, data/inst 57511680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 61913 # Table walker requests started/completed, data/inst 57611680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 131186 # Table walker requests started/completed, data/inst 57711680SCurtis.Dunham@arm.comsystem.cpu0.itb.inst_hits 244690597 # ITB inst hits 57811680SCurtis.Dunham@arm.comsystem.cpu0.itb.inst_misses 69273 # ITB inst misses 57910585Sandreas.hansson@arm.comsystem.cpu0.itb.read_hits 0 # DTB read hits 58010585Sandreas.hansson@arm.comsystem.cpu0.itb.read_misses 0 # DTB read misses 58110585Sandreas.hansson@arm.comsystem.cpu0.itb.write_hits 0 # DTB write hits 58210585Sandreas.hansson@arm.comsystem.cpu0.itb.write_misses 0 # DTB write misses 58311441Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 58410585Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 58511680SCurtis.Dunham@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 40666 # Number of times TLB was flushed by MVA & ASID 58611680SCurtis.Dunham@arm.comsystem.cpu0.itb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID 58711680SCurtis.Dunham@arm.comsystem.cpu0.itb.flush_entries 27059 # Number of entries that have been flushed from TLB 58810585Sandreas.hansson@arm.comsystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 58910585Sandreas.hansson@arm.comsystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 59010585Sandreas.hansson@arm.comsystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 59111680SCurtis.Dunham@arm.comsystem.cpu0.itb.perms_faults 167788 # Number of TLB faults due to permissions restrictions 59210585Sandreas.hansson@arm.comsystem.cpu0.itb.read_accesses 0 # DTB read accesses 59310585Sandreas.hansson@arm.comsystem.cpu0.itb.write_accesses 0 # DTB write accesses 59411680SCurtis.Dunham@arm.comsystem.cpu0.itb.inst_accesses 244759870 # ITB inst accesses 59511680SCurtis.Dunham@arm.comsystem.cpu0.itb.hits 244690597 # DTB hits 59611680SCurtis.Dunham@arm.comsystem.cpu0.itb.misses 69273 # DTB misses 59711680SCurtis.Dunham@arm.comsystem.cpu0.itb.accesses 244759870 # DTB accesses 59811680SCurtis.Dunham@arm.comsystem.cpu0.numPwrStateTransitions 27904 # Number of power state transitions 59911680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::samples 13952 # Distribution of time spent in the clock gated state 60011680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::mean 3372797482.084218 # Distribution of time spent in the clock gated state 60111680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::stdev 110921496988.059006 # Distribution of time spent in the clock gated state 60211680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::underflows 3863 27.69% 27.69% # Distribution of time spent in the clock gated state 60311680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::1000-5e+10 10067 72.15% 99.84% # Distribution of time spent in the clock gated state 60411680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::5e+10-1e+11 11 0.08% 99.92% # Distribution of time spent in the clock gated state 60511680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.93% # Distribution of time spent in the clock gated state 60611680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.94% # Distribution of time spent in the clock gated state 60711680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.94% # Distribution of time spent in the clock gated state 60811680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::overflows 8 0.06% 100.00% # Distribution of time spent in the clock gated state 60911570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 61011680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::max_value 7351146409252 # Distribution of time spent in the clock gated state 61111680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::total 13952 # Distribution of time spent in the clock gated state 61211680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateResidencyTicks::ON 497639803961 # Cumulative time (in ticks) in various power states 61311680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateResidencyTicks::CLK_GATED 47057270470039 # Cumulative time (in ticks) in various power states 61411680SCurtis.Dunham@arm.comsystem.cpu0.numCycles 995321471 # number of cpu cycles simulated 61510585Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 61610585Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 61711680SCurtis.Dunham@arm.comsystem.cpu0.committedInsts 452001209 # Number of instructions committed 61811680SCurtis.Dunham@arm.comsystem.cpu0.committedOps 531851100 # Number of ops (including micro ops) committed 61911680SCurtis.Dunham@arm.comsystem.cpu0.discardedOps 46239027 # Number of ops (including micro ops) which were discarded before commit 62011680SCurtis.Dunham@arm.comsystem.cpu0.numFetchSuspends 5092 # Number of times Execute suspended instruction fetching 62111680SCurtis.Dunham@arm.comsystem.cpu0.quiesceCycles 94115325169 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 62211680SCurtis.Dunham@arm.comsystem.cpu0.cpi 2.202033 # CPI: cycles per instruction 62311680SCurtis.Dunham@arm.comsystem.cpu0.ipc 0.454126 # IPC: instructions per cycle 62411606Sandreas.sandberg@arm.comsystem.cpu0.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction 62511680SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::IntAlu 368287155 69.25% 69.25% # Class of committed instruction 62611680SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::IntMult 1118982 0.21% 69.46% # Class of committed instruction 62711680SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::IntDiv 57276 0.01% 69.47% # Class of committed instruction 62811680SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::FloatAdd 0 0.00% 69.47% # Class of committed instruction 62911680SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::FloatCmp 0 0.00% 69.47% # Class of committed instruction 63011680SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::FloatCvt 0 0.00% 69.47% # Class of committed instruction 63111680SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::FloatMult 0 0.00% 69.47% # Class of committed instruction 63211680SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::FloatDiv 0 0.00% 69.47% # Class of committed instruction 63311680SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::FloatSqrt 0 0.00% 69.47% # Class of committed instruction 63411680SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdAdd 0 0.00% 69.47% # Class of committed instruction 63511680SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.47% # Class of committed instruction 63611680SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdAlu 0 0.00% 69.47% # Class of committed instruction 63711680SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdCmp 0 0.00% 69.47% # Class of committed instruction 63811680SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdCvt 0 0.00% 69.47% # Class of committed instruction 63911680SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdMisc 0 0.00% 69.47% # Class of committed instruction 64011680SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdMult 0 0.00% 69.47% # Class of committed instruction 64111680SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.47% # Class of committed instruction 64211680SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdShift 0 0.00% 69.47% # Class of committed instruction 64311680SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.47% # Class of committed instruction 64411680SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdSqrt 0 0.00% 69.47% # Class of committed instruction 64511680SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdFloatAdd 8 0.00% 69.47% # Class of committed instruction 64611680SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.47% # Class of committed instruction 64711680SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdFloatCmp 13 0.00% 69.47% # Class of committed instruction 64811680SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdFloatCvt 21 0.00% 69.47% # Class of committed instruction 64911680SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.47% # Class of committed instruction 65011680SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdFloatMisc 85306 0.02% 69.48% # Class of committed instruction 65111680SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.48% # Class of committed instruction 65211680SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.48% # Class of committed instruction 65311680SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.48% # Class of committed instruction 65411680SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::MemRead 84402084 15.87% 85.35% # Class of committed instruction 65511680SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::MemWrite 77900254 14.65% 100.00% # Class of committed instruction 65611441Sandreas.hansson@arm.comsystem.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 65711441Sandreas.hansson@arm.comsystem.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 65811680SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::total 531851100 # Class of committed instruction 65910585Sandreas.hansson@arm.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 66011680SCurtis.Dunham@arm.comsystem.cpu0.kern.inst.quiesce 13952 # number of quiesce instructions executed 66111680SCurtis.Dunham@arm.comsystem.cpu0.tickCycles 729574114 # Number of cycles that the object actually ticked 66211680SCurtis.Dunham@arm.comsystem.cpu0.idleCycles 265747357 # Total number of cycles that the object has spent stopped 66311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 66411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.replacements 5787900 # number of replacements 66511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.tagsinuse 490.209920 # Cycle average of tags in use 66611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.total_refs 157471988 # Total number of references to valid blocks. 66711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.sampled_refs 5788412 # Sample count of references to valid blocks. 66811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.avg_refs 27.204696 # Average number of references to valid blocks. 66911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.warmup_cycle 5354308000 # Cycle when the warmup percentage was hit. 67011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 490.209920 # Average occupied blocks per requestor 67111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.957441 # Average percentage of cache occupancy 67211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.957441 # Average percentage of cache occupancy 67311336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 67411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id 67511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 397 # Occupied blocks per task id 67611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id 67711336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 67811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.tag_accesses 334937152 # Number of tag accesses 67911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.data_accesses 334937152 # Number of data accesses 68011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 68111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 80549957 # number of ReadReq hits 68211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_hits::total 80549957 # number of ReadReq hits 68311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 72496805 # number of WriteReq hits 68411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_hits::total 72496805 # number of WriteReq hits 68511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 269794 # number of SoftPFReq hits 68611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 269794 # number of SoftPFReq hits 68711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_hits::cpu0.data 177007 # number of WriteLineReq hits 68811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_hits::total 177007 # number of WriteLineReq hits 68911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1734640 # number of LoadLockedReq hits 69011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 1734640 # number of LoadLockedReq hits 69111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 1715473 # number of StoreCondReq hits 69211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 1715473 # number of StoreCondReq hits 69311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 153223769 # number of demand (read+write) hits 69411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_hits::total 153223769 # number of demand (read+write) hits 69511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 153493563 # number of overall hits 69611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_hits::total 153493563 # number of overall hits 69711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 3263198 # number of ReadReq misses 69811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_misses::total 3263198 # number of ReadReq misses 69911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 2445366 # number of WriteReq misses 70011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_misses::total 2445366 # number of WriteReq misses 70111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 673099 # number of SoftPFReq misses 70211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 673099 # number of SoftPFReq misses 70311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_misses::cpu0.data 844507 # number of WriteLineReq misses 70411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_misses::total 844507 # number of WriteLineReq misses 70511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 169054 # number of LoadLockedReq misses 70611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 169054 # number of LoadLockedReq misses 70711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 187078 # number of StoreCondReq misses 70811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 187078 # number of StoreCondReq misses 70911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 6553071 # number of demand (read+write) misses 71011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_misses::total 6553071 # number of demand (read+write) misses 71111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 7226170 # number of overall misses 71211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_misses::total 7226170 # number of overall misses 71311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 52395902500 # number of ReadReq miss cycles 71411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 52395902500 # number of ReadReq miss cycles 71511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 52490790500 # number of WriteReq miss cycles 71611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 52490790500 # number of WriteReq miss cycles 71711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 27335813500 # number of WriteLineReq miss cycles 71811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::total 27335813500 # number of WriteLineReq miss cycles 71911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2555333500 # number of LoadLockedReq miss cycles 72011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 2555333500 # number of LoadLockedReq miss cycles 72111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4463485500 # number of StoreCondReq miss cycles 72211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 4463485500 # number of StoreCondReq miss cycles 72311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2023000 # number of StoreCondFailReq miss cycles 72411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::total 2023000 # number of StoreCondFailReq miss cycles 72511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_latency::cpu0.data 132222506500 # number of demand (read+write) miss cycles 72611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_latency::total 132222506500 # number of demand (read+write) miss cycles 72711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_latency::cpu0.data 132222506500 # number of overall miss cycles 72811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_latency::total 132222506500 # number of overall miss cycles 72911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 83813155 # number of ReadReq accesses(hits+misses) 73011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 83813155 # number of ReadReq accesses(hits+misses) 73111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 74942171 # number of WriteReq accesses(hits+misses) 73211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 74942171 # number of WriteReq accesses(hits+misses) 73311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 942893 # number of SoftPFReq accesses(hits+misses) 73411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 942893 # number of SoftPFReq accesses(hits+misses) 73511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1021514 # number of WriteLineReq accesses(hits+misses) 73611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::total 1021514 # number of WriteLineReq accesses(hits+misses) 73711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1903694 # number of LoadLockedReq accesses(hits+misses) 73811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 1903694 # number of LoadLockedReq accesses(hits+misses) 73911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1902551 # number of StoreCondReq accesses(hits+misses) 74011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 1902551 # number of StoreCondReq accesses(hits+misses) 74111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 159776840 # number of demand (read+write) accesses 74211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_accesses::total 159776840 # number of demand (read+write) accesses 74311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 160719733 # number of overall (read+write) accesses 74411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_accesses::total 160719733 # number of overall (read+write) accesses 74511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.038934 # miss rate for ReadReq accesses 74611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.038934 # miss rate for ReadReq accesses 74711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032630 # miss rate for WriteReq accesses 74811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.032630 # miss rate for WriteReq accesses 74911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.713866 # miss rate for SoftPFReq accesses 75011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.713866 # miss rate for SoftPFReq accesses 75111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.826721 # miss rate for WriteLineReq accesses 75211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::total 0.826721 # miss rate for WriteLineReq accesses 75311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088803 # miss rate for LoadLockedReq accesses 75411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088803 # miss rate for LoadLockedReq accesses 75511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.098330 # miss rate for StoreCondReq accesses 75611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.098330 # miss rate for StoreCondReq accesses 75711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.041014 # miss rate for demand accesses 75811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.041014 # miss rate for demand accesses 75911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.044961 # miss rate for overall accesses 76011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.044961 # miss rate for overall accesses 76111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16056.611490 # average ReadReq miss latency 76211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 16056.611490 # average ReadReq miss latency 76311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21465.412744 # average WriteReq miss latency 76411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 21465.412744 # average WriteReq miss latency 76511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32368.960234 # average WriteLineReq miss latency 76611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32368.960234 # average WriteLineReq miss latency 76711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15115.486768 # average LoadLockedReq miss latency 76811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15115.486768 # average LoadLockedReq miss latency 76911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23858.954554 # average StoreCondReq miss latency 77011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23858.954554 # average StoreCondReq miss latency 77110636Snilay@cs.wisc.edusystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 77210585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 77311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20177.182042 # average overall miss latency 77411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 20177.182042 # average overall miss latency 77511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18297.729849 # average overall miss latency 77611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 18297.729849 # average overall miss latency 77710585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 77810585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 77910585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 78010585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 78110585Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 78210585Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 78311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.writebacks::writebacks 5787917 # number of writebacks 78411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.writebacks::total 5787917 # number of writebacks 78511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 205447 # number of ReadReq MSHR hits 78611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 205447 # number of ReadReq MSHR hits 78711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1015907 # number of WriteReq MSHR hits 78811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 1015907 # number of WriteReq MSHR hits 78911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 99 # number of WriteLineReq MSHR hits 79011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_hits::total 99 # number of WriteLineReq MSHR hits 79111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 45884 # number of LoadLockedReq MSHR hits 79211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 45884 # number of LoadLockedReq MSHR hits 79311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 37 # number of StoreCondReq MSHR hits 79411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_hits::total 37 # number of StoreCondReq MSHR hits 79511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_hits::cpu0.data 1221453 # number of demand (read+write) MSHR hits 79611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_hits::total 1221453 # number of demand (read+write) MSHR hits 79711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_hits::cpu0.data 1221453 # number of overall MSHR hits 79811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_hits::total 1221453 # number of overall MSHR hits 79911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3057751 # number of ReadReq MSHR misses 80011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 3057751 # number of ReadReq MSHR misses 80111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1429459 # number of WriteReq MSHR misses 80211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 1429459 # number of WriteReq MSHR misses 80311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 670780 # number of SoftPFReq MSHR misses 80411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::total 670780 # number of SoftPFReq MSHR misses 80511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 844408 # number of WriteLineReq MSHR misses 80611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::total 844408 # number of WriteLineReq MSHR misses 80711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 123170 # number of LoadLockedReq MSHR misses 80811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 123170 # number of LoadLockedReq MSHR misses 80911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 187041 # number of StoreCondReq MSHR misses 81011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 187041 # number of StoreCondReq MSHR misses 81111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.data 5331618 # number of demand (read+write) MSHR misses 81211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 5331618 # number of demand (read+write) MSHR misses 81311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.data 6002398 # number of overall MSHR misses 81411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 6002398 # number of overall MSHR misses 81511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31212 # number of ReadReq MSHR uncacheable 81611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::total 31212 # number of ReadReq MSHR uncacheable 81711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 30755 # number of WriteReq MSHR uncacheable 81811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::total 30755 # number of WriteReq MSHR uncacheable 81911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 61967 # number of overall MSHR uncacheable misses 82011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::total 61967 # number of overall MSHR uncacheable misses 82111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 44254087500 # number of ReadReq MSHR miss cycles 82211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 44254087500 # number of ReadReq MSHR miss cycles 82311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 29600010500 # number of WriteReq MSHR miss cycles 82411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 29600010500 # number of WriteReq MSHR miss cycles 82511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 15858321000 # number of SoftPFReq MSHR miss cycles 82611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 15858321000 # number of SoftPFReq MSHR miss cycles 82711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 26484603000 # number of WriteLineReq MSHR miss cycles 82811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 26484603000 # number of WriteLineReq MSHR miss cycles 82911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1676878500 # number of LoadLockedReq MSHR miss cycles 83011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1676878500 # number of LoadLockedReq MSHR miss cycles 83111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4275603000 # number of StoreCondReq MSHR miss cycles 83211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4275603000 # number of StoreCondReq MSHR miss cycles 83311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1773000 # number of StoreCondFailReq MSHR miss cycles 83411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1773000 # number of StoreCondFailReq MSHR miss cycles 83511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 100338701000 # number of demand (read+write) MSHR miss cycles 83611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 100338701000 # number of demand (read+write) MSHR miss cycles 83711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 116197022000 # number of overall MSHR miss cycles 83811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 116197022000 # number of overall MSHR miss cycles 83911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6038825000 # number of ReadReq MSHR uncacheable cycles 84011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6038825000 # number of ReadReq MSHR uncacheable cycles 84111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6038825000 # number of overall MSHR uncacheable cycles 84211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 6038825000 # number of overall MSHR uncacheable cycles 84311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036483 # mshr miss rate for ReadReq accesses 84411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036483 # mshr miss rate for ReadReq accesses 84511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019074 # mshr miss rate for WriteReq accesses 84611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019074 # mshr miss rate for WriteReq accesses 84711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.711406 # mshr miss rate for SoftPFReq accesses 84811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.711406 # mshr miss rate for SoftPFReq accesses 84911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.826624 # mshr miss rate for WriteLineReq accesses 85011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.826624 # mshr miss rate for WriteLineReq accesses 85111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064701 # mshr miss rate for LoadLockedReq accesses 85211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064701 # mshr miss rate for LoadLockedReq accesses 85311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.098311 # mshr miss rate for StoreCondReq accesses 85411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.098311 # mshr miss rate for StoreCondReq accesses 85511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.033369 # mshr miss rate for demand accesses 85611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.033369 # mshr miss rate for demand accesses 85711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.037347 # mshr miss rate for overall accesses 85811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.037347 # mshr miss rate for overall accesses 85911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14472.757102 # average ReadReq mshr miss latency 86011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14472.757102 # average ReadReq mshr miss latency 86111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20707.142003 # average WriteReq mshr miss latency 86211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20707.142003 # average WriteReq mshr miss latency 86311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23641.612749 # average SoftPFReq mshr miss latency 86411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23641.612749 # average SoftPFReq mshr miss latency 86511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31364.699292 # average WriteLineReq mshr miss latency 86611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31364.699292 # average WriteLineReq mshr miss latency 86711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13614.341966 # average LoadLockedReq mshr miss latency 86811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13614.341966 # average LoadLockedReq mshr miss latency 86911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22859.175261 # average StoreCondReq mshr miss latency 87011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22859.175261 # average StoreCondReq mshr miss latency 87110636Snilay@cs.wisc.edusystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 87210585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 87311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18819.559278 # average overall mshr miss latency 87411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 18819.559278 # average overall mshr miss latency 87511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19358.433413 # average overall mshr miss latency 87611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 19358.433413 # average overall mshr miss latency 87711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193477.668845 # average ReadReq mshr uncacheable latency 87811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193477.668845 # average ReadReq mshr uncacheable latency 87911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97452.272984 # average overall mshr uncacheable latency 88011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 97452.272984 # average overall mshr uncacheable latency 88111680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 88211680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.replacements 9773833 # number of replacements 88311680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.tagsinuse 511.928996 # Cycle average of tags in use 88411680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.total_refs 234741496 # Total number of references to valid blocks. 88511680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.sampled_refs 9774345 # Sample count of references to valid blocks. 88611680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.avg_refs 24.016085 # Average number of references to valid blocks. 88711680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.warmup_cycle 22886662000 # Cycle when the warmup percentage was hit. 88811680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.928996 # Average occupied blocks per requestor 88911680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999861 # Average percentage of cache occupancy 89011680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999861 # Average percentage of cache occupancy 89110585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 89211680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id 89311680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id 89411680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 45 # Occupied blocks per task id 89510585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 89611680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.tag_accesses 498806059 # Number of tag accesses 89711680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.data_accesses 498806059 # Number of data accesses 89811680SCurtis.Dunham@arm.comsystem.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 89911680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 234741496 # number of ReadReq hits 90011680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_hits::total 234741496 # number of ReadReq hits 90111680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 234741496 # number of demand (read+write) hits 90211680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_hits::total 234741496 # number of demand (read+write) hits 90311680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 234741496 # number of overall hits 90411680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_hits::total 234741496 # number of overall hits 90511680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 9774356 # number of ReadReq misses 90611680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_misses::total 9774356 # number of ReadReq misses 90711680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 9774356 # number of demand (read+write) misses 90811680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_misses::total 9774356 # number of demand (read+write) misses 90911680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 9774356 # number of overall misses 91011680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_misses::total 9774356 # number of overall misses 91111680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 99441985000 # number of ReadReq miss cycles 91211680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 99441985000 # number of ReadReq miss cycles 91311680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 99441985000 # number of demand (read+write) miss cycles 91411680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_latency::total 99441985000 # number of demand (read+write) miss cycles 91511680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 99441985000 # number of overall miss cycles 91611680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_latency::total 99441985000 # number of overall miss cycles 91711680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 244515852 # number of ReadReq accesses(hits+misses) 91811680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_accesses::total 244515852 # number of ReadReq accesses(hits+misses) 91911680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 244515852 # number of demand (read+write) accesses 92011680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_accesses::total 244515852 # number of demand (read+write) accesses 92111680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 244515852 # number of overall (read+write) accesses 92211680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_accesses::total 244515852 # number of overall (read+write) accesses 92311680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039974 # miss rate for ReadReq accesses 92411680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.039974 # miss rate for ReadReq accesses 92511680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.039974 # miss rate for demand accesses 92611680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.039974 # miss rate for demand accesses 92711680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.039974 # miss rate for overall accesses 92811680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.039974 # miss rate for overall accesses 92911680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10173.763366 # average ReadReq miss latency 93011680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 10173.763366 # average ReadReq miss latency 93111680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10173.763366 # average overall miss latency 93211680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 10173.763366 # average overall miss latency 93311680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10173.763366 # average overall miss latency 93411680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 10173.763366 # average overall miss latency 93510585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 93610585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 93710585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 93810585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 93910585Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 94010585Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 94111680SCurtis.Dunham@arm.comsystem.cpu0.icache.writebacks::writebacks 9773833 # number of writebacks 94211680SCurtis.Dunham@arm.comsystem.cpu0.icache.writebacks::total 9773833 # number of writebacks 94311680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9774356 # number of ReadReq MSHR misses 94411680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 9774356 # number of ReadReq MSHR misses 94511680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 9774356 # number of demand (read+write) MSHR misses 94611680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_misses::total 9774356 # number of demand (read+write) MSHR misses 94711680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 9774356 # number of overall MSHR misses 94811680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_misses::total 9774356 # number of overall MSHR misses 94911680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52284 # number of ReadReq MSHR uncacheable 95011680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::total 52284 # number of ReadReq MSHR uncacheable 95111680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52284 # number of overall MSHR uncacheable misses 95211680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::total 52284 # number of overall MSHR uncacheable misses 95311680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 94554807500 # number of ReadReq MSHR miss cycles 95411680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 94554807500 # number of ReadReq MSHR miss cycles 95511680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 94554807500 # number of demand (read+write) MSHR miss cycles 95611680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 94554807500 # number of demand (read+write) MSHR miss cycles 95711680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 94554807500 # number of overall MSHR miss cycles 95811680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 94554807500 # number of overall MSHR miss cycles 95911680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5161606000 # number of ReadReq MSHR uncacheable cycles 96011680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 5161606000 # number of ReadReq MSHR uncacheable cycles 96111680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 5161606000 # number of overall MSHR uncacheable cycles 96211680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::total 5161606000 # number of overall MSHR uncacheable cycles 96311680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039974 # mshr miss rate for ReadReq accesses 96411680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039974 # mshr miss rate for ReadReq accesses 96511680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039974 # mshr miss rate for demand accesses 96611680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.039974 # mshr miss rate for demand accesses 96711680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039974 # mshr miss rate for overall accesses 96811680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.039974 # mshr miss rate for overall accesses 96911680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9673.763417 # average ReadReq mshr miss latency 97011680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9673.763417 # average ReadReq mshr miss latency 97111680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9673.763417 # average overall mshr miss latency 97211680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 9673.763417 # average overall mshr miss latency 97311680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9673.763417 # average overall mshr miss latency 97411680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 9673.763417 # average overall mshr miss latency 97511680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 98722.477240 # average ReadReq mshr uncacheable latency 97611680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 98722.477240 # average ReadReq mshr uncacheable latency 97711680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 98722.477240 # average overall mshr uncacheable latency 97811680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 98722.477240 # average overall mshr uncacheable latency 97911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 98011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.prefetcher.num_hwpf_issued 7608993 # number of hwpf issued 98111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.prefetcher.pfIdentified 7610336 # number of prefetch candidates identified 98211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.prefetcher.pfBufferHit 1188 # number of redundant prefetches already in prefetch queue 98310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 98410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 98511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.prefetcher.pfSpanPage 1005416 # number of prefetches not generated due to page crossing 98611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 98711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.replacements 2646552 # number of replacements 98811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.tagsinuse 15691.473570 # Cycle average of tags in use 98911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.total_refs 14028250 # Total number of references to valid blocks. 99011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.sampled_refs 2662377 # Sample count of references to valid blocks. 99111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.avg_refs 5.269070 # Average number of references to valid blocks. 99211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 5985886000 # Cycle when the warmup percentage was hit. 99311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 15348.189818 # Average occupied blocks per requestor 99411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 32.039011 # Average occupied blocks per requestor 99511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 8.868609 # Average occupied blocks per requestor 99611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 302.376132 # Average occupied blocks per requestor 99711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.936779 # Average percentage of cache occupancy 99811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001956 # Average percentage of cache occupancy 99911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000541 # Average percentage of cache occupancy 100011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.018456 # Average percentage of cache occupancy 100111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.957732 # Average percentage of cache occupancy 100211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1022 352 # Occupied blocks per task id 100311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 63 # Occupied blocks per task id 100411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 15410 # Occupied blocks per task id 100511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::1 7 # Occupied blocks per task id 100611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::2 163 # Occupied blocks per task id 100711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::3 65 # Occupied blocks per task id 100811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::4 117 # Occupied blocks per task id 100911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 37 # Occupied blocks per task id 101011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 101111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 24 # Occupied blocks per task id 101211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id 101311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1727 # Occupied blocks per task id 101411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6563 # Occupied blocks per task id 101511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4041 # Occupied blocks per task id 101611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2911 # Occupied blocks per task id 101711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1022 0.021484 # Percentage of cache occupancy per task id 101811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003845 # Percentage of cache occupancy per task id 101911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.940552 # Percentage of cache occupancy per task id 102011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.tag_accesses 534452534 # Number of tag accesses 102111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.data_accesses 534452534 # Number of data accesses 102211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 102311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 527649 # number of ReadReq hits 102411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 180298 # number of ReadReq hits 102511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 707947 # number of ReadReq hits 102611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::writebacks 3832122 # number of WritebackDirty hits 102711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::total 3832122 # number of WritebackDirty hits 102811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_hits::writebacks 11726658 # number of WritebackClean hits 102911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_hits::total 11726658 # number of WritebackClean hits 103011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::cpu0.data 1 # number of UpgradeReq hits 103111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits 103211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 904488 # number of ReadExReq hits 103311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 904488 # number of ReadExReq hits 103411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 9076171 # number of ReadCleanReq hits 103511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 9076171 # number of ReadCleanReq hits 103611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2875219 # number of ReadSharedReq hits 103711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 2875219 # number of ReadSharedReq hits 103811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::cpu0.data 241369 # number of InvalidateReq hits 103911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::total 241369 # number of InvalidateReq hits 104011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 527649 # number of demand (read+write) hits 104111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 180298 # number of demand (read+write) hits 104211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 9076171 # number of demand (read+write) hits 104311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 3779707 # number of demand (read+write) hits 104411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::total 13563825 # number of demand (read+write) hits 104511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 527649 # number of overall hits 104611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 180298 # number of overall hits 104711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 9076171 # number of overall hits 104811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 3779707 # number of overall hits 104911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::total 13563825 # number of overall hits 105011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 21665 # number of ReadReq misses 105111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10120 # number of ReadReq misses 105211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 31785 # number of ReadReq misses 105311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 246294 # number of UpgradeReq misses 105411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 246294 # number of UpgradeReq misses 105511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 187036 # number of SCUpgradeReq misses 105611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 187036 # number of SCUpgradeReq misses 105711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses 105811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses 105911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 286789 # number of ReadExReq misses 106011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 286789 # number of ReadExReq misses 106111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 698184 # number of ReadCleanReq misses 106211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 698184 # number of ReadCleanReq misses 106311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 976175 # number of ReadSharedReq misses 106411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 976175 # number of ReadSharedReq misses 106511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::cpu0.data 601118 # number of InvalidateReq misses 106611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::total 601118 # number of InvalidateReq misses 106711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 21665 # number of demand (read+write) misses 106811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 10120 # number of demand (read+write) misses 106911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 698184 # number of demand (read+write) misses 107011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 1262964 # number of demand (read+write) misses 107111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::total 1992933 # number of demand (read+write) misses 107211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 21665 # number of overall misses 107311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 10120 # number of overall misses 107411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 698184 # number of overall misses 107511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 1262964 # number of overall misses 107611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::total 1992933 # number of overall misses 107711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 696360500 # number of ReadReq miss cycles 107811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 404225000 # number of ReadReq miss cycles 107911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::total 1100585500 # number of ReadReq miss cycles 108011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 910928500 # number of UpgradeReq miss cycles 108111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::total 910928500 # number of UpgradeReq miss cycles 108211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 289294500 # number of SCUpgradeReq miss cycles 108311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::total 289294500 # number of SCUpgradeReq miss cycles 108411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1705497 # number of SCUpgradeFailReq miss cycles 108511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1705497 # number of SCUpgradeFailReq miss cycles 108611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 15428607998 # number of ReadExReq miss cycles 108711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::total 15428607998 # number of ReadExReq miss cycles 108811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 25059292500 # number of ReadCleanReq miss cycles 108911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::total 25059292500 # number of ReadCleanReq miss cycles 109011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 37051733995 # number of ReadSharedReq miss cycles 109111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::total 37051733995 # number of ReadSharedReq miss cycles 109211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 336301500 # number of InvalidateReq miss cycles 109311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::total 336301500 # number of InvalidateReq miss cycles 109411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 696360500 # number of demand (read+write) miss cycles 109511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 404225000 # number of demand (read+write) miss cycles 109611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.inst 25059292500 # number of demand (read+write) miss cycles 109711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.data 52480341993 # number of demand (read+write) miss cycles 109811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_latency::total 78640219993 # number of demand (read+write) miss cycles 109911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 696360500 # number of overall miss cycles 110011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 404225000 # number of overall miss cycles 110111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.inst 25059292500 # number of overall miss cycles 110211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.data 52480341993 # number of overall miss cycles 110311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_latency::total 78640219993 # number of overall miss cycles 110411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 549314 # number of ReadReq accesses(hits+misses) 110511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 190418 # number of ReadReq accesses(hits+misses) 110611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 739732 # number of ReadReq accesses(hits+misses) 110711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::writebacks 3832122 # number of WritebackDirty accesses(hits+misses) 110811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::total 3832122 # number of WritebackDirty accesses(hits+misses) 110911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::writebacks 11726658 # number of WritebackClean accesses(hits+misses) 111011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::total 11726658 # number of WritebackClean accesses(hits+misses) 111111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 246295 # number of UpgradeReq accesses(hits+misses) 111211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 246295 # number of UpgradeReq accesses(hits+misses) 111311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 187036 # number of SCUpgradeReq accesses(hits+misses) 111411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 187036 # number of SCUpgradeReq accesses(hits+misses) 111511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses) 111611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) 111711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1191277 # number of ReadExReq accesses(hits+misses) 111811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1191277 # number of ReadExReq accesses(hits+misses) 111911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9774355 # number of ReadCleanReq accesses(hits+misses) 112011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 9774355 # number of ReadCleanReq accesses(hits+misses) 112111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3851394 # number of ReadSharedReq accesses(hits+misses) 112211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 3851394 # number of ReadSharedReq accesses(hits+misses) 112311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 842487 # number of InvalidateReq accesses(hits+misses) 112411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::total 842487 # number of InvalidateReq accesses(hits+misses) 112511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 549314 # number of demand (read+write) accesses 112611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 190418 # number of demand (read+write) accesses 112711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 9774355 # number of demand (read+write) accesses 112811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 5042671 # number of demand (read+write) accesses 112911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::total 15556758 # number of demand (read+write) accesses 113011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 549314 # number of overall (read+write) accesses 113111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 190418 # number of overall (read+write) accesses 113211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 9774355 # number of overall (read+write) accesses 113311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 5042671 # number of overall (read+write) accesses 113411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::total 15556758 # number of overall (read+write) accesses 113511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.039440 # miss rate for ReadReq accesses 113611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.053146 # miss rate for ReadReq accesses 113711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.042968 # miss rate for ReadReq accesses 113811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999996 # miss rate for UpgradeReq accesses 113911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999996 # miss rate for UpgradeReq accesses 114011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 114111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 114210636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 114310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 114411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.240741 # miss rate for ReadExReq accesses 114511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.240741 # miss rate for ReadExReq accesses 114611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.071430 # miss rate for ReadCleanReq accesses 114711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.071430 # miss rate for ReadCleanReq accesses 114811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.253460 # miss rate for ReadSharedReq accesses 114911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.253460 # miss rate for ReadSharedReq accesses 115011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.713504 # miss rate for InvalidateReq accesses 115111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::total 0.713504 # miss rate for InvalidateReq accesses 115211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.039440 # miss rate for demand accesses 115311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.053146 # miss rate for demand accesses 115411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.071430 # miss rate for demand accesses 115511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.250455 # miss rate for demand accesses 115611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.128107 # miss rate for demand accesses 115711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.039440 # miss rate for overall accesses 115811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.053146 # miss rate for overall accesses 115911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.071430 # miss rate for overall accesses 116011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.250455 # miss rate for overall accesses 116111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.128107 # miss rate for overall accesses 116211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32142.187861 # average ReadReq miss latency 116311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 39943.181818 # average ReadReq miss latency 116411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::total 34625.939909 # average ReadReq miss latency 116511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3698.541174 # average UpgradeReq miss latency 116611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3698.541174 # average UpgradeReq miss latency 116711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1546.731645 # average SCUpgradeReq miss latency 116811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1546.731645 # average SCUpgradeReq miss latency 116911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 341099.400000 # average SCUpgradeFailReq miss latency 117011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 341099.400000 # average SCUpgradeFailReq miss latency 117111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 53797.767690 # average ReadExReq miss latency 117211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::total 53797.767690 # average ReadExReq miss latency 117311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 35892.103657 # average ReadCleanReq miss latency 117411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 35892.103657 # average ReadCleanReq miss latency 117511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 37956.036566 # average ReadSharedReq miss latency 117611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 37956.036566 # average ReadSharedReq miss latency 117711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 559.460039 # average InvalidateReq miss latency 117811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 559.460039 # average InvalidateReq miss latency 117911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32142.187861 # average overall miss latency 118011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 39943.181818 # average overall miss latency 118111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 35892.103657 # average overall miss latency 118211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 41553.315845 # average overall miss latency 118311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::total 39459.540282 # average overall miss latency 118411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32142.187861 # average overall miss latency 118511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 39943.181818 # average overall miss latency 118611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 35892.103657 # average overall miss latency 118711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 41553.315845 # average overall miss latency 118811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::total 39459.540282 # average overall miss latency 118911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 119010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 119111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 119210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 119311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 119410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 119511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.unused_prefetches 45829 # number of HardPF blocks evicted w/o reference 119611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.writebacks::writebacks 1629804 # number of writebacks 119711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.writebacks::total 1629804 # number of writebacks 119811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 24 # number of ReadReq MSHR hits 119911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 98 # number of ReadReq MSHR hits 120011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::total 122 # number of ReadReq MSHR hits 120111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 8277 # number of ReadExReq MSHR hits 120211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::total 8277 # number of ReadExReq MSHR hits 120311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 12 # number of ReadCleanReq MSHR hits 120411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_hits::total 12 # number of ReadCleanReq MSHR hits 120511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 866 # number of ReadSharedReq MSHR hits 120611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::total 866 # number of ReadSharedReq MSHR hits 120711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 3 # number of InvalidateReq MSHR hits 120811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits 120911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 24 # number of demand (read+write) MSHR hits 121011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 98 # number of demand (read+write) MSHR hits 121111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.inst 12 # number of demand (read+write) MSHR hits 121211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.data 9143 # number of demand (read+write) MSHR hits 121311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_hits::total 9277 # number of demand (read+write) MSHR hits 121411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 24 # number of overall MSHR hits 121511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 98 # number of overall MSHR hits 121611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.inst 12 # number of overall MSHR hits 121711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.data 9143 # number of overall MSHR hits 121811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_hits::total 9277 # number of overall MSHR hits 121911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 21641 # number of ReadReq MSHR misses 122011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 10022 # number of ReadReq MSHR misses 122111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::total 31663 # number of ReadReq MSHR misses 122211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 782860 # number of HardPFReq MSHR misses 122311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::total 782860 # number of HardPFReq MSHR misses 122411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 246294 # number of UpgradeReq MSHR misses 122511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::total 246294 # number of UpgradeReq MSHR misses 122611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 187036 # number of SCUpgradeReq MSHR misses 122711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 187036 # number of SCUpgradeReq MSHR misses 122811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses 122911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses 123011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 278512 # number of ReadExReq MSHR misses 123111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::total 278512 # number of ReadExReq MSHR misses 123211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 698172 # number of ReadCleanReq MSHR misses 123311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::total 698172 # number of ReadCleanReq MSHR misses 123411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 975309 # number of ReadSharedReq MSHR misses 123511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::total 975309 # number of ReadSharedReq MSHR misses 123611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 601115 # number of InvalidateReq MSHR misses 123711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::total 601115 # number of InvalidateReq MSHR misses 123811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 21641 # number of demand (read+write) MSHR misses 123911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 10022 # number of demand (read+write) MSHR misses 124011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.inst 698172 # number of demand (read+write) MSHR misses 124111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.data 1253821 # number of demand (read+write) MSHR misses 124211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_misses::total 1983656 # number of demand (read+write) MSHR misses 124311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 21641 # number of overall MSHR misses 124411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 10022 # number of overall MSHR misses 124511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.inst 698172 # number of overall MSHR misses 124611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.data 1253821 # number of overall MSHR misses 124711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 782860 # number of overall MSHR misses 124811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_misses::total 2766516 # number of overall MSHR misses 124911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52284 # number of ReadReq MSHR uncacheable 125011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31212 # number of ReadReq MSHR uncacheable 125111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::total 83496 # number of ReadReq MSHR uncacheable 125211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 30755 # number of WriteReq MSHR uncacheable 125311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::total 30755 # number of WriteReq MSHR uncacheable 125411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52284 # number of overall MSHR uncacheable misses 125511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 61967 # number of overall MSHR uncacheable misses 125611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::total 114251 # number of overall MSHR uncacheable misses 125711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 565944000 # number of ReadReq MSHR miss cycles 125811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 342540500 # number of ReadReq MSHR miss cycles 125911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::total 908484500 # number of ReadReq MSHR miss cycles 126011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 36299233693 # number of HardPFReq MSHR miss cycles 126111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 36299233693 # number of HardPFReq MSHR miss cycles 126211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4539562995 # number of UpgradeReq MSHR miss cycles 126311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4539562995 # number of UpgradeReq MSHR miss cycles 126411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2868254998 # number of SCUpgradeReq MSHR miss cycles 126511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2868254998 # number of SCUpgradeReq MSHR miss cycles 126611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1441497 # number of SCUpgradeFailReq MSHR miss cycles 126711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1441497 # number of SCUpgradeFailReq MSHR miss cycles 126811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 12630779498 # number of ReadExReq MSHR miss cycles 126911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 12630779498 # number of ReadExReq MSHR miss cycles 127011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 20869901000 # number of ReadCleanReq MSHR miss cycles 127111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 20869901000 # number of ReadCleanReq MSHR miss cycles 127211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 31074032995 # number of ReadSharedReq MSHR miss cycles 127311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 31074032995 # number of ReadSharedReq MSHR miss cycles 127411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 19885865000 # number of InvalidateReq MSHR miss cycles 127511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 19885865000 # number of InvalidateReq MSHR miss cycles 127611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 565944000 # number of demand (read+write) MSHR miss cycles 127711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 342540500 # number of demand (read+write) MSHR miss cycles 127811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 20869901000 # number of demand (read+write) MSHR miss cycles 127911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 43704812493 # number of demand (read+write) MSHR miss cycles 128011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::total 65483197993 # number of demand (read+write) MSHR miss cycles 128111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 565944000 # number of overall MSHR miss cycles 128211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 342540500 # number of overall MSHR miss cycles 128311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 20869901000 # number of overall MSHR miss cycles 128411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 43704812493 # number of overall MSHR miss cycles 128511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 36299233693 # number of overall MSHR miss cycles 128611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::total 101782431686 # number of overall MSHR miss cycles 128711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4743334000 # number of ReadReq MSHR uncacheable cycles 128811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5788958500 # number of ReadReq MSHR uncacheable cycles 128911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10532292500 # number of ReadReq MSHR uncacheable cycles 129011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4743334000 # number of overall MSHR uncacheable cycles 129111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5788958500 # number of overall MSHR uncacheable cycles 129211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10532292500 # number of overall MSHR uncacheable cycles 129311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.039396 # mshr miss rate for ReadReq accesses 129411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052632 # mshr miss rate for ReadReq accesses 129511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.042803 # mshr miss rate for ReadReq accesses 129610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 129710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 129811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999996 # mshr miss rate for UpgradeReq accesses 129911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999996 # mshr miss rate for UpgradeReq accesses 130011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 130111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 130210636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 130310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 130411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.233793 # mshr miss rate for ReadExReq accesses 130511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.233793 # mshr miss rate for ReadExReq accesses 130611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.071429 # mshr miss rate for ReadCleanReq accesses 130711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.071429 # mshr miss rate for ReadCleanReq accesses 130811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.253235 # mshr miss rate for ReadSharedReq accesses 130911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.253235 # mshr miss rate for ReadSharedReq accesses 131011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.713501 # mshr miss rate for InvalidateReq accesses 131111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.713501 # mshr miss rate for InvalidateReq accesses 131211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.039396 # mshr miss rate for demand accesses 131311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052632 # mshr miss rate for demand accesses 131411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.071429 # mshr miss rate for demand accesses 131511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.248642 # mshr miss rate for demand accesses 131611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::total 0.127511 # mshr miss rate for demand accesses 131711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.039396 # mshr miss rate for overall accesses 131811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052632 # mshr miss rate for overall accesses 131911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.071429 # mshr miss rate for overall accesses 132011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.248642 # mshr miss rate for overall accesses 132110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 132211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::total 0.177834 # mshr miss rate for overall accesses 132311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26151.471743 # average ReadReq mshr miss latency 132411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34178.856516 # average ReadReq mshr miss latency 132511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28692.306478 # average ReadReq mshr miss latency 132611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46367.465055 # average HardPFReq mshr miss latency 132711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46367.465055 # average HardPFReq mshr miss latency 132811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18431.480243 # average UpgradeReq mshr miss latency 132911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18431.480243 # average UpgradeReq mshr miss latency 133011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15335.309769 # average SCUpgradeReq mshr miss latency 133111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15335.309769 # average SCUpgradeReq mshr miss latency 133211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 288299.400000 # average SCUpgradeFailReq mshr miss latency 133311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 288299.400000 # average SCUpgradeFailReq mshr miss latency 133411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 45350.934602 # average ReadExReq mshr miss latency 133511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 45350.934602 # average ReadExReq mshr miss latency 133611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 29892.205646 # average ReadCleanReq mshr miss latency 133711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29892.205646 # average ReadCleanReq mshr miss latency 133811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31860.705679 # average ReadSharedReq mshr miss latency 133911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31860.705679 # average ReadSharedReq mshr miss latency 134011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 33081.631635 # average InvalidateReq mshr miss latency 134111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 33081.631635 # average InvalidateReq mshr miss latency 134211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26151.471743 # average overall mshr miss latency 134311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34178.856516 # average overall mshr miss latency 134411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 29892.205646 # average overall mshr miss latency 134511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34857.298205 # average overall mshr miss latency 134611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33011.367895 # average overall mshr miss latency 134711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26151.471743 # average overall mshr miss latency 134811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34178.856516 # average overall mshr miss latency 134911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 29892.205646 # average overall mshr miss latency 135011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34857.298205 # average overall mshr miss latency 135111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46367.465055 # average overall mshr miss latency 135211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36790.834279 # average overall mshr miss latency 135311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 90722.477240 # average ReadReq mshr uncacheable latency 135411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185472.206203 # average ReadReq mshr uncacheable latency 135511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 126141.282217 # average ReadReq mshr uncacheable latency 135611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 90722.477240 # average overall mshr uncacheable latency 135711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 93420.021947 # average overall mshr uncacheable latency 135811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 92185.560739 # average overall mshr uncacheable latency 135911680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_requests 31945858 # Total number of requests made to the snoop filter. 136011680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_requests 16286466 # Number of requests hitting in the snoop filter with a single holder of the requested data. 136111680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2971 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 136211680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_snoops 662323 # Total number of snoops made to the snoop filter. 136311680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_snoops 662303 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 136411680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 20 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 136511680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 136611680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 897088 # Transaction distribution 136711680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 14618500 # Transaction distribution 136811680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 30756 # Transaction distribution 136911680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 30755 # Transaction distribution 137011680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackDirty 5466694 # Transaction distribution 137111680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackClean 11729628 # Transaction distribution 137211680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::CleanEvict 1381452 # Transaction distribution 137311680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::HardPFReq 1000780 # Transaction distribution 137411680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 137511680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 445154 # Transaction distribution 137611680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 338634 # Transaction distribution 137711680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 499902 # Transaction distribution 137811680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution 137911680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeFailResp 83 # Transaction distribution 138011680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1222912 # Transaction distribution 138111680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1199223 # Transaction distribution 138211680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 9774356 # Transaction distribution 138311680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 4899750 # Transaction distribution 138411680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateReq 895142 # Transaction distribution 138511680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateResp 842487 # Transaction distribution 138611680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 29427111 # Packet count per connected master and slave (bytes) 138711680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18719100 # Packet count per connected master and slave (bytes) 138811680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 397503 # Packet count per connected master and slave (bytes) 138911680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1155819 # Packet count per connected master and slave (bytes) 139011680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count::total 49699533 # Packet count per connected master and slave (bytes) 139111680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1254430144 # Cumulative packet size per connected master and slave (bytes) 139211680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 699985190 # Cumulative packet size per connected master and slave (bytes) 139311680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1523344 # Cumulative packet size per connected master and slave (bytes) 139411680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4394512 # Cumulative packet size per connected master and slave (bytes) 139511680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size::total 1960333190 # Cumulative packet size per connected master and slave (bytes) 139611680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoops 5744069 # Total snoops (count) 139711680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoopTraffic 111836388 # Total snoop traffic (bytes) 139811680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 22520641 # Request fanout histogram 139911680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 0.042476 # Request fanout histogram 140011680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.201677 # Request fanout histogram 140110585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 140211680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 21564077 95.75% 95.75% # Request fanout histogram 140311680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 956544 4.25% 100.00% # Request fanout histogram 140411680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 20 0.00% 100.00% # Request fanout histogram 140510585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 140611138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 140710827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 140811680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 22520641 # Request fanout histogram 140911680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.reqLayer0.occupancy 31868357980 # Layer occupancy (ticks) 141011201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 141111680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoopLayer0.occupancy 188944290 # Layer occupancy (ticks) 141210585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 141311680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.respLayer0.occupancy 14742648604 # Layer occupancy (ticks) 141410585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 141511680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.respLayer1.occupancy 8252120363 # Layer occupancy (ticks) 141610585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 141711680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.respLayer2.occupancy 207185798 # Layer occupancy (ticks) 141810585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 141911680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.respLayer3.occupancy 606624760 # Layer occupancy (ticks) 142010585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 142111680SCurtis.Dunham@arm.comsystem.cpu1.branchPred.lookups 130393488 # Number of BP lookups 142211680SCurtis.Dunham@arm.comsystem.cpu1.branchPred.condPredicted 92735412 # Number of conditional branches predicted 142311680SCurtis.Dunham@arm.comsystem.cpu1.branchPred.condIncorrect 5902942 # Number of conditional branches incorrect 142411680SCurtis.Dunham@arm.comsystem.cpu1.branchPred.BTBLookups 97710710 # Number of BTB lookups 142511680SCurtis.Dunham@arm.comsystem.cpu1.branchPred.BTBHits 68499677 # Number of BTB hits 142610585Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 142711680SCurtis.Dunham@arm.comsystem.cpu1.branchPred.BTBHitPct 70.104574 # BTB Hit Percentage 142811680SCurtis.Dunham@arm.comsystem.cpu1.branchPred.usedRAS 15029088 # Number of times the RAS was used to get a target. 142911680SCurtis.Dunham@arm.comsystem.cpu1.branchPred.RASInCorrect 982146 # Number of incorrect RAS predictions. 143011680SCurtis.Dunham@arm.comsystem.cpu1.branchPred.indirectLookups 3431599 # Number of indirect predictor lookups. 143111680SCurtis.Dunham@arm.comsystem.cpu1.branchPred.indirectHits 2322480 # Number of indirect target hits. 143211680SCurtis.Dunham@arm.comsystem.cpu1.branchPred.indirectMisses 1109119 # Number of indirect misses. 143311680SCurtis.Dunham@arm.comsystem.cpu1.branchPredindirectMispredicted 398100 # Number of mispredicted indirect branches. 143411680SCurtis.Dunham@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 143510628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 143610628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 143710628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 143810628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 143910628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 144010628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 144110628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 144210628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 144310585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 144410585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 144510585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 144610585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 144710585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 144810585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 144910585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 145010585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 145110585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 145210585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 145310585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 145410585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 145510585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 145610585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 145710585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 145810585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 145910585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 146010585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 146110585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 146210585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 146310585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 146411680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 146511680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walks 266586 # Table walker walks requested 146611680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksLong 266586 # Table walker walks initiated with long descriptors 146711680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9178 # Level at which table walker walks with long descriptors terminate 146811680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level3 75276 # Level at which table walker walks with long descriptors terminate 146911680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 266586 # Table walker wait (enqueue to first request) latency 147011680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0 266586 100.00% 100.00% # Table walker wait (enqueue to first request) latency 147111680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 266586 # Table walker wait (enqueue to first request) latency 147211680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::samples 84454 # Table walker service (enqueue to completion) latency 147311680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::mean 23652.319606 # Table walker service (enqueue to completion) latency 147411680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::gmean 21901.867132 # Table walker service (enqueue to completion) latency 147511680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::stdev 15135.594089 # Table walker service (enqueue to completion) latency 147611680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::0-65535 83574 98.96% 98.96% # Table walker service (enqueue to completion) latency 147711680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::65536-131071 653 0.77% 99.73% # Table walker service (enqueue to completion) latency 147811680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::131072-196607 133 0.16% 99.89% # Table walker service (enqueue to completion) latency 147911680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::196608-262143 39 0.05% 99.93% # Table walker service (enqueue to completion) latency 148011680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::262144-327679 30 0.04% 99.97% # Table walker service (enqueue to completion) latency 148111680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::327680-393215 15 0.02% 99.99% # Table walker service (enqueue to completion) latency 148211680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 99.99% # Table walker service (enqueue to completion) latency 148311680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 99.99% # Table walker service (enqueue to completion) latency 148411680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::589824-655359 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 148511680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 148611680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::total 84454 # Table walker service (enqueue to completion) latency 148711680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksPending::samples 112342944 # Table walker pending requests distribution 148811680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksPending::0 112342944 100.00% 100.00% # Table walker pending requests distribution 148911680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksPending::total 112342944 # Table walker pending requests distribution 149011680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 75276 89.13% 89.13% # Table walker page sizes translated 149111680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkPageSizes::2M 9178 10.87% 100.00% # Table walker page sizes translated 149211680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 84454 # Table walker page sizes translated 149311680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 266586 # Table walker requests started/completed, data/inst 149410628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 149511680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 266586 # Table walker requests started/completed, data/inst 149611680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 84454 # Table walker requests started/completed, data/inst 149710628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 149811680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 84454 # Table walker requests started/completed, data/inst 149911680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 351040 # Table walker requests started/completed, data/inst 150010585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_hits 0 # ITB inst hits 150110585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_misses 0 # ITB inst misses 150211680SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_hits 83602508 # DTB read hits 150311680SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_misses 221634 # DTB read misses 150411680SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_hits 72407946 # DTB write hits 150511680SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_misses 44952 # DTB write misses 150611441Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 150710585Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 150811680SCurtis.Dunham@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 40666 # Number of times TLB was flushed by MVA & ASID 150911680SCurtis.Dunham@arm.comsystem.cpu1.dtb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID 151011680SCurtis.Dunham@arm.comsystem.cpu1.dtb.flush_entries 35586 # Number of entries that have been flushed from TLB 151111680SCurtis.Dunham@arm.comsystem.cpu1.dtb.align_faults 1113 # Number of TLB faults due to alignment restrictions 151211680SCurtis.Dunham@arm.comsystem.cpu1.dtb.prefetch_faults 7045 # Number of TLB faults due to prefetch 151310585Sandreas.hansson@arm.comsystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 151411680SCurtis.Dunham@arm.comsystem.cpu1.dtb.perms_faults 10293 # Number of TLB faults due to permissions restrictions 151511680SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_accesses 83824142 # DTB read accesses 151611680SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_accesses 72452898 # DTB write accesses 151710585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 151811680SCurtis.Dunham@arm.comsystem.cpu1.dtb.hits 156010454 # DTB hits 151911680SCurtis.Dunham@arm.comsystem.cpu1.dtb.misses 266586 # DTB misses 152011680SCurtis.Dunham@arm.comsystem.cpu1.dtb.accesses 156277040 # DTB accesses 152111680SCurtis.Dunham@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 152210628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 152310628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 152410628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 152510628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 152610628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 152710628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 152810628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 152910628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 153010585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 153110585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 153210585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 153310585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 153410585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 153510585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 153610585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 153710585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 153810585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 153910585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 154010585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 154110585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 154210585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 154310585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 154410585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 154510585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 154610585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 154710585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 154810585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 154910585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 155010585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 155111680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 155211680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walks 60007 # Table walker walks requested 155311680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksLong 60007 # Table walker walks initiated with long descriptors 155411680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level2 568 # Level at which table walker walks with long descriptors terminate 155511680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level3 49765 # Level at which table walker walks with long descriptors terminate 155611680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 60007 # Table walker wait (enqueue to first request) latency 155711680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkWaitTime::0 60007 100.00% 100.00% # Table walker wait (enqueue to first request) latency 155811680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 60007 # Table walker wait (enqueue to first request) latency 155911680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::samples 50333 # Table walker service (enqueue to completion) latency 156011680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::mean 25530.089603 # Table walker service (enqueue to completion) latency 156111680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::gmean 23478.456634 # Table walker service (enqueue to completion) latency 156211680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::stdev 19036.287161 # Table walker service (enqueue to completion) latency 156311680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::0-65535 49435 98.22% 98.22% # Table walker service (enqueue to completion) latency 156411680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::65536-131071 638 1.27% 99.48% # Table walker service (enqueue to completion) latency 156511680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::131072-196607 189 0.38% 99.86% # Table walker service (enqueue to completion) latency 156611680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::196608-262143 38 0.08% 99.93% # Table walker service (enqueue to completion) latency 156711680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::262144-327679 10 0.02% 99.95% # Table walker service (enqueue to completion) latency 156811680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::327680-393215 6 0.01% 99.97% # Table walker service (enqueue to completion) latency 156911680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.01% 99.97% # Table walker service (enqueue to completion) latency 157011680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::589824-655359 14 0.03% 100.00% # Table walker service (enqueue to completion) latency 157111680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::total 50333 # Table walker service (enqueue to completion) latency 157211680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksPending::samples 111619444 # Table walker pending requests distribution 157311680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksPending::0 111619444 100.00% 100.00% # Table walker pending requests distribution 157411680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksPending::total 111619444 # Table walker pending requests distribution 157511680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 49765 98.87% 98.87% # Table walker page sizes translated 157611680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkPageSizes::2M 568 1.13% 100.00% # Table walker page sizes translated 157711680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 50333 # Table walker page sizes translated 157810628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 157911680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60007 # Table walker requests started/completed, data/inst 158011680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 60007 # Table walker requests started/completed, data/inst 158110628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 158211680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 50333 # Table walker requests started/completed, data/inst 158311680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 50333 # Table walker requests started/completed, data/inst 158411680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 110340 # Table walker requests started/completed, data/inst 158511680SCurtis.Dunham@arm.comsystem.cpu1.itb.inst_hits 231314016 # ITB inst hits 158611680SCurtis.Dunham@arm.comsystem.cpu1.itb.inst_misses 60007 # ITB inst misses 158710585Sandreas.hansson@arm.comsystem.cpu1.itb.read_hits 0 # DTB read hits 158810585Sandreas.hansson@arm.comsystem.cpu1.itb.read_misses 0 # DTB read misses 158910585Sandreas.hansson@arm.comsystem.cpu1.itb.write_hits 0 # DTB write hits 159010585Sandreas.hansson@arm.comsystem.cpu1.itb.write_misses 0 # DTB write misses 159111441Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 159210585Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 159311680SCurtis.Dunham@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 40666 # Number of times TLB was flushed by MVA & ASID 159411680SCurtis.Dunham@arm.comsystem.cpu1.itb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID 159511680SCurtis.Dunham@arm.comsystem.cpu1.itb.flush_entries 25531 # Number of entries that have been flushed from TLB 159610585Sandreas.hansson@arm.comsystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 159710585Sandreas.hansson@arm.comsystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 159810585Sandreas.hansson@arm.comsystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 159911680SCurtis.Dunham@arm.comsystem.cpu1.itb.perms_faults 167507 # Number of TLB faults due to permissions restrictions 160010585Sandreas.hansson@arm.comsystem.cpu1.itb.read_accesses 0 # DTB read accesses 160110585Sandreas.hansson@arm.comsystem.cpu1.itb.write_accesses 0 # DTB write accesses 160211680SCurtis.Dunham@arm.comsystem.cpu1.itb.inst_accesses 231374023 # ITB inst accesses 160311680SCurtis.Dunham@arm.comsystem.cpu1.itb.hits 231314016 # DTB hits 160411680SCurtis.Dunham@arm.comsystem.cpu1.itb.misses 60007 # DTB misses 160511680SCurtis.Dunham@arm.comsystem.cpu1.itb.accesses 231374023 # DTB accesses 160611680SCurtis.Dunham@arm.comsystem.cpu1.numPwrStateTransitions 9626 # Number of power state transitions 160711680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::samples 4813 # Distribution of time spent in the clock gated state 160811680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::mean 9788374174.243299 # Distribution of time spent in the clock gated state 160911680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::stdev 115006828751.685410 # Distribution of time spent in the clock gated state 161011680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::underflows 3303 68.63% 68.63% # Distribution of time spent in the clock gated state 161111680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::1000-5e+10 1483 30.81% 99.44% # Distribution of time spent in the clock gated state 161211680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.02% 99.46% # Distribution of time spent in the clock gated state 161311680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.48% # Distribution of time spent in the clock gated state 161411680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 4 0.08% 99.56% # Distribution of time spent in the clock gated state 161511680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::2.5e+11-3e+11 1 0.02% 99.58% # Distribution of time spent in the clock gated state 161611680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.61% # Distribution of time spent in the clock gated state 161711680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.02% 99.63% # Distribution of time spent in the clock gated state 161811680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::overflows 18 0.37% 100.00% # Distribution of time spent in the clock gated state 161911570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 162011680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::max_value 1988779353616 # Distribution of time spent in the clock gated state 162111680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::total 4813 # Distribution of time spent in the clock gated state 162211680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateResidencyTicks::ON 443465373367 # Cumulative time (in ticks) in various power states 162311680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateResidencyTicks::CLK_GATED 47111444900633 # Cumulative time (in ticks) in various power states 162411680SCurtis.Dunham@arm.comsystem.cpu1.numCycles 886937326 # number of cpu cycles simulated 162510585Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 162610585Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 162711680SCurtis.Dunham@arm.comsystem.cpu1.committedInsts 425165575 # Number of instructions committed 162811680SCurtis.Dunham@arm.comsystem.cpu1.committedOps 499981941 # Number of ops (including micro ops) committed 162911680SCurtis.Dunham@arm.comsystem.cpu1.discardedOps 45360018 # Number of ops (including micro ops) which were discarded before commit 163011680SCurtis.Dunham@arm.comsystem.cpu1.numFetchSuspends 4813 # Number of times Execute suspended instruction fetching 163111680SCurtis.Dunham@arm.comsystem.cpu1.quiesceCycles 94223530921 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 163211680SCurtis.Dunham@arm.comsystem.cpu1.cpi 2.086099 # CPI: cycles per instruction 163311680SCurtis.Dunham@arm.comsystem.cpu1.ipc 0.479364 # IPC: instructions per cycle 163411606Sandreas.sandberg@arm.comsystem.cpu1.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 163511680SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::IntAlu 346104827 69.22% 69.22% # Class of committed instruction 163611680SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::IntMult 1095440 0.22% 69.44% # Class of committed instruction 163711680SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::IntDiv 59698 0.01% 69.45% # Class of committed instruction 163811680SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction 163911680SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction 164011680SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction 164111680SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::FloatMult 0 0.00% 69.45% # Class of committed instruction 164211680SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::FloatDiv 0 0.00% 69.45% # Class of committed instruction 164311680SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::FloatSqrt 0 0.00% 69.45% # Class of committed instruction 164411680SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdAdd 0 0.00% 69.45% # Class of committed instruction 164511680SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.45% # Class of committed instruction 164611680SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdAlu 0 0.00% 69.45% # Class of committed instruction 164711680SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdCmp 0 0.00% 69.45% # Class of committed instruction 164811680SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdCvt 0 0.00% 69.45% # Class of committed instruction 164911680SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdMisc 0 0.00% 69.45% # Class of committed instruction 165011680SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdMult 0 0.00% 69.45% # Class of committed instruction 165111680SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.45% # Class of committed instruction 165211680SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdShift 0 0.00% 69.45% # Class of committed instruction 165311680SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.45% # Class of committed instruction 165411680SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdSqrt 0 0.00% 69.45% # Class of committed instruction 165511680SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdFloatAdd 0 0.00% 69.45% # Class of committed instruction 165611680SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.45% # Class of committed instruction 165711680SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdFloatCmp 0 0.00% 69.45% # Class of committed instruction 165811680SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdFloatCvt 0 0.00% 69.45% # Class of committed instruction 165911680SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.45% # Class of committed instruction 166011680SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdFloatMisc 26657 0.01% 69.46% # Class of committed instruction 166111680SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction 166211680SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction 166311680SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction 166411680SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::MemRead 80579122 16.12% 85.58% # Class of committed instruction 166511680SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::MemWrite 72116197 14.42% 100.00% # Class of committed instruction 166611441Sandreas.hansson@arm.comsystem.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 166711441Sandreas.hansson@arm.comsystem.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 166811680SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::total 499981941 # Class of committed instruction 166910585Sandreas.hansson@arm.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 167011680SCurtis.Dunham@arm.comsystem.cpu1.kern.inst.quiesce 4813 # number of quiesce instructions executed 167111680SCurtis.Dunham@arm.comsystem.cpu1.tickCycles 688160387 # Number of cycles that the object actually ticked 167211680SCurtis.Dunham@arm.comsystem.cpu1.idleCycles 198776939 # Total number of cycles that the object has spent stopped 167311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 167411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.replacements 4915770 # number of replacements 167511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.tagsinuse 461.565771 # Cycle average of tags in use 167611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.total_refs 148821179 # Total number of references to valid blocks. 167711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.sampled_refs 4916282 # Sample count of references to valid blocks. 167811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.avg_refs 30.271083 # Average number of references to valid blocks. 167911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.warmup_cycle 8378532705500 # Cycle when the warmup percentage was hit. 168011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 461.565771 # Average occupied blocks per requestor 168111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.901496 # Average percentage of cache occupancy 168211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.901496 # Average percentage of cache occupancy 168311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 168411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id 168511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 154 # Occupied blocks per task id 168611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 267 # Occupied blocks per task id 168711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 168811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.tag_accesses 314637839 # Number of tag accesses 168911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.data_accesses 314637839 # Number of data accesses 169011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 169111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 76998524 # number of ReadReq hits 169211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_hits::total 76998524 # number of ReadReq hits 169311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 67544283 # number of WriteReq hits 169411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_hits::total 67544283 # number of WriteReq hits 169511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 228025 # number of SoftPFReq hits 169611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 228025 # number of SoftPFReq hits 169711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_hits::cpu1.data 143759 # number of WriteLineReq hits 169811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_hits::total 143759 # number of WriteLineReq hits 169911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1733263 # number of LoadLockedReq hits 170011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 1733263 # number of LoadLockedReq hits 170111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 1698082 # number of StoreCondReq hits 170211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 1698082 # number of StoreCondReq hits 170311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 144686566 # number of demand (read+write) hits 170411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_hits::total 144686566 # number of demand (read+write) hits 170511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 144914591 # number of overall hits 170611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_hits::total 144914591 # number of overall hits 170711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 2997503 # number of ReadReq misses 170811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_misses::total 2997503 # number of ReadReq misses 170911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 2132920 # number of WriteReq misses 171011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_misses::total 2132920 # number of WriteReq misses 171111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 598160 # number of SoftPFReq misses 171211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 598160 # number of SoftPFReq misses 171311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_misses::cpu1.data 396373 # number of WriteLineReq misses 171411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_misses::total 396373 # number of WriteLineReq misses 171511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 156072 # number of LoadLockedReq misses 171611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 156072 # number of LoadLockedReq misses 171711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 190006 # number of StoreCondReq misses 171811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 190006 # number of StoreCondReq misses 171911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 5526796 # number of demand (read+write) misses 172011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_misses::total 5526796 # number of demand (read+write) misses 172111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 6124956 # number of overall misses 172211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_misses::total 6124956 # number of overall misses 172311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 46710580500 # number of ReadReq miss cycles 172411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 46710580500 # number of ReadReq miss cycles 172511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 40169374000 # number of WriteReq miss cycles 172611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 40169374000 # number of WriteReq miss cycles 172711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10226397500 # number of WriteLineReq miss cycles 172811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::total 10226397500 # number of WriteLineReq miss cycles 172911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2373794500 # number of LoadLockedReq miss cycles 173011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 2373794500 # number of LoadLockedReq miss cycles 173111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4526922000 # number of StoreCondReq miss cycles 173211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 4526922000 # number of StoreCondReq miss cycles 173311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1761500 # number of StoreCondFailReq miss cycles 173411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::total 1761500 # number of StoreCondFailReq miss cycles 173511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_latency::cpu1.data 97106352000 # number of demand (read+write) miss cycles 173611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_latency::total 97106352000 # number of demand (read+write) miss cycles 173711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_latency::cpu1.data 97106352000 # number of overall miss cycles 173811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_latency::total 97106352000 # number of overall miss cycles 173911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 79996027 # number of ReadReq accesses(hits+misses) 174011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 79996027 # number of ReadReq accesses(hits+misses) 174111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 69677203 # number of WriteReq accesses(hits+misses) 174211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 69677203 # number of WriteReq accesses(hits+misses) 174311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 826185 # number of SoftPFReq accesses(hits+misses) 174411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 826185 # number of SoftPFReq accesses(hits+misses) 174511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::cpu1.data 540132 # number of WriteLineReq accesses(hits+misses) 174611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::total 540132 # number of WriteLineReq accesses(hits+misses) 174711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1889335 # number of LoadLockedReq accesses(hits+misses) 174811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 1889335 # number of LoadLockedReq accesses(hits+misses) 174911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1888088 # number of StoreCondReq accesses(hits+misses) 175011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 1888088 # number of StoreCondReq accesses(hits+misses) 175111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 150213362 # number of demand (read+write) accesses 175211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_accesses::total 150213362 # number of demand (read+write) accesses 175311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 151039547 # number of overall (read+write) accesses 175411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_accesses::total 151039547 # number of overall (read+write) accesses 175511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037471 # miss rate for ReadReq accesses 175611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.037471 # miss rate for ReadReq accesses 175711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030611 # miss rate for WriteReq accesses 175811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.030611 # miss rate for WriteReq accesses 175911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.724002 # miss rate for SoftPFReq accesses 176011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.724002 # miss rate for SoftPFReq accesses 176111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.733845 # miss rate for WriteLineReq accesses 176211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::total 0.733845 # miss rate for WriteLineReq accesses 176311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.082607 # miss rate for LoadLockedReq accesses 176411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.082607 # miss rate for LoadLockedReq accesses 176511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100634 # miss rate for StoreCondReq accesses 176611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.100634 # miss rate for StoreCondReq accesses 176711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.036793 # miss rate for demand accesses 176811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.036793 # miss rate for demand accesses 176911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.040552 # miss rate for overall accesses 177011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.040552 # miss rate for overall accesses 177111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15583.163887 # average ReadReq miss latency 177211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 15583.163887 # average ReadReq miss latency 177311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18833.042965 # average WriteReq miss latency 177411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 18833.042965 # average WriteReq miss latency 177511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 25799.934658 # average WriteLineReq miss latency 177611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::total 25799.934658 # average WriteLineReq miss latency 177711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15209.611590 # average LoadLockedReq miss latency 177811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15209.611590 # average LoadLockedReq miss latency 177911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23825.152890 # average StoreCondReq miss latency 178011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23825.152890 # average StoreCondReq miss latency 178110636Snilay@cs.wisc.edusystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 178210585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 178311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17570.098842 # average overall miss latency 178411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 17570.098842 # average overall miss latency 178511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15854.212177 # average overall miss latency 178611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 15854.212177 # average overall miss latency 178710585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 178810585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 178910585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 179010585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 179110585Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 179210585Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 179311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.writebacks::writebacks 4915771 # number of writebacks 179411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.writebacks::total 4915771 # number of writebacks 179511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 147995 # number of ReadReq MSHR hits 179611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 147995 # number of ReadReq MSHR hits 179711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 874601 # number of WriteReq MSHR hits 179811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 874601 # number of WriteReq MSHR hits 179911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 58 # number of WriteLineReq MSHR hits 180011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_hits::total 58 # number of WriteLineReq MSHR hits 180111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 38344 # number of LoadLockedReq MSHR hits 180211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 38344 # number of LoadLockedReq MSHR hits 180311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 50 # number of StoreCondReq MSHR hits 180411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_hits::total 50 # number of StoreCondReq MSHR hits 180511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_hits::cpu1.data 1022654 # number of demand (read+write) MSHR hits 180611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_hits::total 1022654 # number of demand (read+write) MSHR hits 180711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_hits::cpu1.data 1022654 # number of overall MSHR hits 180811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_hits::total 1022654 # number of overall MSHR hits 180911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2849508 # number of ReadReq MSHR misses 181011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 2849508 # number of ReadReq MSHR misses 181111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1258319 # number of WriteReq MSHR misses 181211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 1258319 # number of WriteReq MSHR misses 181311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 597912 # number of SoftPFReq MSHR misses 181411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::total 597912 # number of SoftPFReq MSHR misses 181511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 396315 # number of WriteLineReq MSHR misses 181611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::total 396315 # number of WriteLineReq MSHR misses 181711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 117728 # number of LoadLockedReq MSHR misses 181811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 117728 # number of LoadLockedReq MSHR misses 181911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 189956 # number of StoreCondReq MSHR misses 182011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 189956 # number of StoreCondReq MSHR misses 182111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.data 4504142 # number of demand (read+write) MSHR misses 182211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 4504142 # number of demand (read+write) MSHR misses 182311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.data 5102054 # number of overall MSHR misses 182411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 5102054 # number of overall MSHR misses 182511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 7183 # number of ReadReq MSHR uncacheable 182611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::total 7183 # number of ReadReq MSHR uncacheable 182711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7509 # number of WriteReq MSHR uncacheable 182811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::total 7509 # number of WriteReq MSHR uncacheable 182911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14692 # number of overall MSHR uncacheable misses 183011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::total 14692 # number of overall MSHR uncacheable misses 183111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 40476665500 # number of ReadReq MSHR miss cycles 183211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 40476665500 # number of ReadReq MSHR miss cycles 183311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23125073000 # number of WriteReq MSHR miss cycles 183411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 23125073000 # number of WriteReq MSHR miss cycles 183511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13939684500 # number of SoftPFReq MSHR miss cycles 183611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13939684500 # number of SoftPFReq MSHR miss cycles 183711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9826633500 # number of WriteLineReq MSHR miss cycles 183811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9826633500 # number of WriteLineReq MSHR miss cycles 183911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1586206000 # number of LoadLockedReq MSHR miss cycles 184011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1586206000 # number of LoadLockedReq MSHR miss cycles 184111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4335749000 # number of StoreCondReq MSHR miss cycles 184211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4335749000 # number of StoreCondReq MSHR miss cycles 184311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1584500 # number of StoreCondFailReq MSHR miss cycles 184411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1584500 # number of StoreCondFailReq MSHR miss cycles 184511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 73428372000 # number of demand (read+write) MSHR miss cycles 184611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 73428372000 # number of demand (read+write) MSHR miss cycles 184711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 87368056500 # number of overall MSHR miss cycles 184811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 87368056500 # number of overall MSHR miss cycles 184911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 918087500 # number of ReadReq MSHR uncacheable cycles 185011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 918087500 # number of ReadReq MSHR uncacheable cycles 185111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 918087500 # number of overall MSHR uncacheable cycles 185211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 918087500 # number of overall MSHR uncacheable cycles 185311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035621 # mshr miss rate for ReadReq accesses 185411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035621 # mshr miss rate for ReadReq accesses 185511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018059 # mshr miss rate for WriteReq accesses 185611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018059 # mshr miss rate for WriteReq accesses 185711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.723702 # mshr miss rate for SoftPFReq accesses 185811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.723702 # mshr miss rate for SoftPFReq accesses 185911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.733737 # mshr miss rate for WriteLineReq accesses 186011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.733737 # mshr miss rate for WriteLineReq accesses 186111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.062312 # mshr miss rate for LoadLockedReq accesses 186211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.062312 # mshr miss rate for LoadLockedReq accesses 186311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100608 # mshr miss rate for StoreCondReq accesses 186411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100608 # mshr miss rate for StoreCondReq accesses 186511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029985 # mshr miss rate for demand accesses 186611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.029985 # mshr miss rate for demand accesses 186711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033780 # mshr miss rate for overall accesses 186811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.033780 # mshr miss rate for overall accesses 186911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14204.790967 # average ReadReq mshr miss latency 187011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14204.790967 # average ReadReq mshr miss latency 187111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18377.750793 # average WriteReq mshr miss latency 187211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18377.750793 # average WriteReq mshr miss latency 187311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23313.940011 # average SoftPFReq mshr miss latency 187411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23313.940011 # average SoftPFReq mshr miss latency 187511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 24795.007759 # average WriteLineReq mshr miss latency 187611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 24795.007759 # average WriteLineReq mshr miss latency 187711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13473.481245 # average LoadLockedReq mshr miss latency 187811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13473.481245 # average LoadLockedReq mshr miss latency 187911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22825.017372 # average StoreCondReq mshr miss latency 188011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22825.017372 # average StoreCondReq mshr miss latency 188110636Snilay@cs.wisc.edusystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 188210585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 188311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16302.410537 # average overall mshr miss latency 188411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 16302.410537 # average overall mshr miss latency 188511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17124.094825 # average overall mshr miss latency 188611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 17124.094825 # average overall mshr miss latency 188711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 127813.935681 # average ReadReq mshr uncacheable latency 188811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 127813.935681 # average ReadReq mshr uncacheable latency 188911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 62488.939559 # average overall mshr uncacheable latency 189011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 62488.939559 # average overall mshr uncacheable latency 189111680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 189211680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.replacements 8832346 # number of replacements 189311680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.tagsinuse 507.234959 # Cycle average of tags in use 189411680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.total_refs 222308626 # Total number of references to valid blocks. 189511680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.sampled_refs 8832858 # Sample count of references to valid blocks. 189611680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.avg_refs 25.168369 # Average number of references to valid blocks. 189711680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.warmup_cycle 8368864848000 # Cycle when the warmup percentage was hit. 189811680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 507.234959 # Average occupied blocks per requestor 189911680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.990693 # Average percentage of cache occupancy 190011680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.990693 # Average percentage of cache occupancy 190110585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 190211680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id 190311680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id 190411680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id 190510585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 190611680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.tag_accesses 471115826 # Number of tag accesses 190711680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.data_accesses 471115826 # Number of data accesses 190811680SCurtis.Dunham@arm.comsystem.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 190911680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 222308626 # number of ReadReq hits 191011680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_hits::total 222308626 # number of ReadReq hits 191111680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 222308626 # number of demand (read+write) hits 191211680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_hits::total 222308626 # number of demand (read+write) hits 191311680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 222308626 # number of overall hits 191411680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_hits::total 222308626 # number of overall hits 191511680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 8832858 # number of ReadReq misses 191611680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_misses::total 8832858 # number of ReadReq misses 191711680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 8832858 # number of demand (read+write) misses 191811680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_misses::total 8832858 # number of demand (read+write) misses 191911680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 8832858 # number of overall misses 192011680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_misses::total 8832858 # number of overall misses 192111680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 91672034000 # number of ReadReq miss cycles 192211680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 91672034000 # number of ReadReq miss cycles 192311680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 91672034000 # number of demand (read+write) miss cycles 192411680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_latency::total 91672034000 # number of demand (read+write) miss cycles 192511680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 91672034000 # number of overall miss cycles 192611680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_latency::total 91672034000 # number of overall miss cycles 192711680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 231141484 # number of ReadReq accesses(hits+misses) 192811680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_accesses::total 231141484 # number of ReadReq accesses(hits+misses) 192911680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 231141484 # number of demand (read+write) accesses 193011680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_accesses::total 231141484 # number of demand (read+write) accesses 193111680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 231141484 # number of overall (read+write) accesses 193211680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_accesses::total 231141484 # number of overall (read+write) accesses 193311680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.038214 # miss rate for ReadReq accesses 193411680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.038214 # miss rate for ReadReq accesses 193511680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.038214 # miss rate for demand accesses 193611680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.038214 # miss rate for demand accesses 193711680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.038214 # miss rate for overall accesses 193811680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.038214 # miss rate for overall accesses 193911680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10378.524595 # average ReadReq miss latency 194011680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 10378.524595 # average ReadReq miss latency 194111680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10378.524595 # average overall miss latency 194211680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 10378.524595 # average overall miss latency 194311680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10378.524595 # average overall miss latency 194411680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 10378.524595 # average overall miss latency 194510585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 194610585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 194710585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 194810585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 194910585Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 195010585Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 195111680SCurtis.Dunham@arm.comsystem.cpu1.icache.writebacks::writebacks 8832346 # number of writebacks 195211680SCurtis.Dunham@arm.comsystem.cpu1.icache.writebacks::total 8832346 # number of writebacks 195311680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8832858 # number of ReadReq MSHR misses 195411680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 8832858 # number of ReadReq MSHR misses 195511680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 8832858 # number of demand (read+write) MSHR misses 195611680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_misses::total 8832858 # number of demand (read+write) MSHR misses 195711680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 8832858 # number of overall MSHR misses 195811680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_misses::total 8832858 # number of overall MSHR misses 195911570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable 196011570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::total 95 # number of ReadReq MSHR uncacheable 196111570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses 196211570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::total 95 # number of overall MSHR uncacheable misses 196311680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 87255605000 # number of ReadReq MSHR miss cycles 196411680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 87255605000 # number of ReadReq MSHR miss cycles 196511680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 87255605000 # number of demand (read+write) MSHR miss cycles 196611680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 87255605000 # number of demand (read+write) MSHR miss cycles 196711680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 87255605000 # number of overall MSHR miss cycles 196811680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 87255605000 # number of overall MSHR miss cycles 196911680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9824500 # number of ReadReq MSHR uncacheable cycles 197011680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9824500 # number of ReadReq MSHR uncacheable cycles 197111680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9824500 # number of overall MSHR uncacheable cycles 197211680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::total 9824500 # number of overall MSHR uncacheable cycles 197311680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.038214 # mshr miss rate for ReadReq accesses 197411680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.038214 # mshr miss rate for ReadReq accesses 197511680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.038214 # mshr miss rate for demand accesses 197611680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.038214 # mshr miss rate for demand accesses 197711680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.038214 # mshr miss rate for overall accesses 197811680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.038214 # mshr miss rate for overall accesses 197911680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9878.524595 # average ReadReq mshr miss latency 198011680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9878.524595 # average ReadReq mshr miss latency 198111680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9878.524595 # average overall mshr miss latency 198211680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 9878.524595 # average overall mshr miss latency 198311680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9878.524595 # average overall mshr miss latency 198411680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 9878.524595 # average overall mshr miss latency 198511680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 103415.789474 # average ReadReq mshr uncacheable latency 198611680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 103415.789474 # average ReadReq mshr uncacheable latency 198711680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 103415.789474 # average overall mshr uncacheable latency 198811680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 103415.789474 # average overall mshr uncacheable latency 198911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 199011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.prefetcher.num_hwpf_issued 6928823 # number of hwpf issued 199111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.prefetcher.pfIdentified 6928917 # number of prefetch candidates identified 199211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.prefetcher.pfBufferHit 84 # number of redundant prefetches already in prefetch queue 199310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 199410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 199511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.prefetcher.pfSpanPage 861587 # number of prefetches not generated due to page crossing 199611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 199711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.replacements 2157597 # number of replacements 199811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.tagsinuse 13047.513497 # Cycle average of tags in use 199911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.total_refs 12560684 # Total number of references to valid blocks. 200011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.sampled_refs 2173028 # Sample count of references to valid blocks. 200111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.avg_refs 5.780268 # Average number of references to valid blocks. 200211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 200311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 12721.719403 # Average occupied blocks per requestor 200411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 48.343114 # Average occupied blocks per requestor 200511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 32.192156 # Average occupied blocks per requestor 200611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 245.258823 # Average occupied blocks per requestor 200711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.776472 # Average percentage of cache occupancy 200811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002951 # Average percentage of cache occupancy 200911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001965 # Average percentage of cache occupancy 201011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.014969 # Average percentage of cache occupancy 201111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.796357 # Average percentage of cache occupancy 201211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1022 270 # Occupied blocks per task id 201311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 73 # Occupied blocks per task id 201411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 15088 # Occupied blocks per task id 201511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::2 102 # Occupied blocks per task id 201611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::3 107 # Occupied blocks per task id 201711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::4 61 # Occupied blocks per task id 201811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 201911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 202011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 42 # Occupied blocks per task id 202111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id 202211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 273 # Occupied blocks per task id 202311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 832 # Occupied blocks per task id 202411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6150 # Occupied blocks per task id 202511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6722 # Occupied blocks per task id 202611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1111 # Occupied blocks per task id 202711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1022 0.016479 # Percentage of cache occupancy per task id 202811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004456 # Percentage of cache occupancy per task id 202911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.920898 # Percentage of cache occupancy per task id 203011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.tag_accesses 472979438 # Number of tag accesses 203111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.data_accesses 472979438 # Number of data accesses 203211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 203311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 496781 # number of ReadReq hits 203411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 150336 # number of ReadReq hits 203511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 647117 # number of ReadReq hits 203611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::writebacks 3051311 # number of WritebackDirty hits 203711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::total 3051311 # number of WritebackDirty hits 203811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_hits::writebacks 10695223 # number of WritebackClean hits 203911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_hits::total 10695223 # number of WritebackClean hits 204011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2 # number of UpgradeReq hits 204111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::total 2 # number of UpgradeReq hits 204211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 813214 # number of ReadExReq hits 204311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 813214 # number of ReadExReq hits 204411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8132856 # number of ReadCleanReq hits 204511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 8132856 # number of ReadCleanReq hits 204611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2632220 # number of ReadSharedReq hits 204711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 2632220 # number of ReadSharedReq hits 204811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::cpu1.data 143613 # number of InvalidateReq hits 204911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::total 143613 # number of InvalidateReq hits 205011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 496781 # number of demand (read+write) hits 205111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 150336 # number of demand (read+write) hits 205211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 8132856 # number of demand (read+write) hits 205311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 3445434 # number of demand (read+write) hits 205411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::total 12225407 # number of demand (read+write) hits 205511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 496781 # number of overall hits 205611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 150336 # number of overall hits 205711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 8132856 # number of overall hits 205811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 3445434 # number of overall hits 205911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::total 12225407 # number of overall hits 206011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 19778 # number of ReadReq misses 206111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9507 # number of ReadReq misses 206211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 29285 # number of ReadReq misses 206311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 216104 # number of UpgradeReq misses 206411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 216104 # number of UpgradeReq misses 206511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 189953 # number of SCUpgradeReq misses 206611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 189953 # number of SCUpgradeReq misses 206711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses 206811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses 206911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 231177 # number of ReadExReq misses 207011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 231177 # number of ReadExReq misses 207111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 700002 # number of ReadCleanReq misses 207211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 700002 # number of ReadCleanReq misses 207311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 932644 # number of ReadSharedReq misses 207411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 932644 # number of ReadSharedReq misses 207511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::cpu1.data 250983 # number of InvalidateReq misses 207611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::total 250983 # number of InvalidateReq misses 207711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 19778 # number of demand (read+write) misses 207811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 9507 # number of demand (read+write) misses 207911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 700002 # number of demand (read+write) misses 208011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 1163821 # number of demand (read+write) misses 208111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::total 1893108 # number of demand (read+write) misses 208211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 19778 # number of overall misses 208311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 9507 # number of overall misses 208411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 700002 # number of overall misses 208511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 1163821 # number of overall misses 208611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::total 1893108 # number of overall misses 208711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 605384500 # number of ReadReq miss cycles 208811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 346513000 # number of ReadReq miss cycles 208911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::total 951897500 # number of ReadReq miss cycles 209011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 912243000 # number of UpgradeReq miss cycles 209111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::total 912243000 # number of UpgradeReq miss cycles 209211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 268121000 # number of SCUpgradeReq miss cycles 209311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::total 268121000 # number of SCUpgradeReq miss cycles 209411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1526000 # number of SCUpgradeFailReq miss cycles 209511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1526000 # number of SCUpgradeFailReq miss cycles 209611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10578569498 # number of ReadExReq miss cycles 209711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::total 10578569498 # number of ReadExReq miss cycles 209811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 24914386500 # number of ReadCleanReq miss cycles 209911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::total 24914386500 # number of ReadCleanReq miss cycles 210011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 33296141988 # number of ReadSharedReq miss cycles 210111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::total 33296141988 # number of ReadSharedReq miss cycles 210211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 300579500 # number of InvalidateReq miss cycles 210311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::total 300579500 # number of InvalidateReq miss cycles 210411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 605384500 # number of demand (read+write) miss cycles 210511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 346513000 # number of demand (read+write) miss cycles 210611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.inst 24914386500 # number of demand (read+write) miss cycles 210711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.data 43874711486 # number of demand (read+write) miss cycles 210811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_latency::total 69740995486 # number of demand (read+write) miss cycles 210911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 605384500 # number of overall miss cycles 211011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 346513000 # number of overall miss cycles 211111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.inst 24914386500 # number of overall miss cycles 211211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.data 43874711486 # number of overall miss cycles 211311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_latency::total 69740995486 # number of overall miss cycles 211411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 516559 # number of ReadReq accesses(hits+misses) 211511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 159843 # number of ReadReq accesses(hits+misses) 211611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 676402 # number of ReadReq accesses(hits+misses) 211711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::writebacks 3051311 # number of WritebackDirty accesses(hits+misses) 211811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::total 3051311 # number of WritebackDirty accesses(hits+misses) 211911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::writebacks 10695223 # number of WritebackClean accesses(hits+misses) 212011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::total 10695223 # number of WritebackClean accesses(hits+misses) 212111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 216106 # number of UpgradeReq accesses(hits+misses) 212211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 216106 # number of UpgradeReq accesses(hits+misses) 212311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 189953 # number of SCUpgradeReq accesses(hits+misses) 212411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 189953 # number of SCUpgradeReq accesses(hits+misses) 212511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses) 212611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) 212711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1044391 # number of ReadExReq accesses(hits+misses) 212811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 1044391 # number of ReadExReq accesses(hits+misses) 212911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 8832858 # number of ReadCleanReq accesses(hits+misses) 213011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 8832858 # number of ReadCleanReq accesses(hits+misses) 213111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3564864 # number of ReadSharedReq accesses(hits+misses) 213211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 3564864 # number of ReadSharedReq accesses(hits+misses) 213311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 394596 # number of InvalidateReq accesses(hits+misses) 213411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::total 394596 # number of InvalidateReq accesses(hits+misses) 213511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 516559 # number of demand (read+write) accesses 213611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 159843 # number of demand (read+write) accesses 213711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 8832858 # number of demand (read+write) accesses 213811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 4609255 # number of demand (read+write) accesses 213911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::total 14118515 # number of demand (read+write) accesses 214011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 516559 # number of overall (read+write) accesses 214111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 159843 # number of overall (read+write) accesses 214211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 8832858 # number of overall (read+write) accesses 214311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 4609255 # number of overall (read+write) accesses 214411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::total 14118515 # number of overall (read+write) accesses 214511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.038288 # miss rate for ReadReq accesses 214611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.059477 # miss rate for ReadReq accesses 214711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.043295 # miss rate for ReadReq accesses 214811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999991 # miss rate for UpgradeReq accesses 214911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999991 # miss rate for UpgradeReq accesses 215011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 215111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 215210636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 215310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 215411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.221351 # miss rate for ReadExReq accesses 215511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.221351 # miss rate for ReadExReq accesses 215611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.079250 # miss rate for ReadCleanReq accesses 215711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.079250 # miss rate for ReadCleanReq accesses 215811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.261621 # miss rate for ReadSharedReq accesses 215911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.261621 # miss rate for ReadSharedReq accesses 216011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.636051 # miss rate for InvalidateReq accesses 216111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::total 0.636051 # miss rate for InvalidateReq accesses 216211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.038288 # miss rate for demand accesses 216311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.059477 # miss rate for demand accesses 216411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.079250 # miss rate for demand accesses 216511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.252497 # miss rate for demand accesses 216611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.134087 # miss rate for demand accesses 216711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.038288 # miss rate for overall accesses 216811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.059477 # miss rate for overall accesses 216911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.079250 # miss rate for overall accesses 217011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.252497 # miss rate for overall accesses 217111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.134087 # miss rate for overall accesses 217211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 30608.984731 # average ReadReq miss latency 217311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 36448.196066 # average ReadReq miss latency 217411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::total 32504.609869 # average ReadReq miss latency 217511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4221.314737 # average UpgradeReq miss latency 217611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4221.314737 # average UpgradeReq miss latency 217711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1411.512321 # average SCUpgradeReq miss latency 217811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1411.512321 # average SCUpgradeReq miss latency 217911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 508666.666667 # average SCUpgradeFailReq miss latency 218011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 508666.666667 # average SCUpgradeFailReq miss latency 218111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 45759.610593 # average ReadExReq miss latency 218211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::total 45759.610593 # average ReadExReq miss latency 218311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35591.879023 # average ReadCleanReq miss latency 218411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35591.879023 # average ReadCleanReq miss latency 218511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 35700.805439 # average ReadSharedReq miss latency 218611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 35700.805439 # average ReadSharedReq miss latency 218711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1197.609001 # average InvalidateReq miss latency 218811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1197.609001 # average InvalidateReq miss latency 218911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 30608.984731 # average overall miss latency 219011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 36448.196066 # average overall miss latency 219111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35591.879023 # average overall miss latency 219211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 37698.848436 # average overall miss latency 219311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::total 36839.417237 # average overall miss latency 219411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 30608.984731 # average overall miss latency 219511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 36448.196066 # average overall miss latency 219611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35591.879023 # average overall miss latency 219711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 37698.848436 # average overall miss latency 219811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::total 36839.417237 # average overall miss latency 219911441Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 220010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 220111441Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 220210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 220311441Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 220410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 220511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.unused_prefetches 43184 # number of HardPF blocks evicted w/o reference 220611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.writebacks::writebacks 1062517 # number of writebacks 220711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.writebacks::total 1062517 # number of writebacks 220811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 15 # number of ReadReq MSHR hits 220911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 83 # number of ReadReq MSHR hits 221011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::total 98 # number of ReadReq MSHR hits 221111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 6377 # number of ReadExReq MSHR hits 221211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::total 6377 # number of ReadExReq MSHR hits 221311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 2 # number of ReadCleanReq MSHR hits 221411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits 221511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 790 # number of ReadSharedReq MSHR hits 221611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::total 790 # number of ReadSharedReq MSHR hits 221711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 1 # number of InvalidateReq MSHR hits 221811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_hits::total 1 # number of InvalidateReq MSHR hits 221911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 15 # number of demand (read+write) MSHR hits 222011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 83 # number of demand (read+write) MSHR hits 222111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits 222211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.data 7167 # number of demand (read+write) MSHR hits 222311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_hits::total 7267 # number of demand (read+write) MSHR hits 222411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 15 # number of overall MSHR hits 222511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 83 # number of overall MSHR hits 222611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits 222711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.data 7167 # number of overall MSHR hits 222811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_hits::total 7267 # number of overall MSHR hits 222911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 19763 # number of ReadReq MSHR misses 223011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9424 # number of ReadReq MSHR misses 223111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::total 29187 # number of ReadReq MSHR misses 223211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 714287 # number of HardPFReq MSHR misses 223311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::total 714287 # number of HardPFReq MSHR misses 223411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 216104 # number of UpgradeReq MSHR misses 223511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::total 216104 # number of UpgradeReq MSHR misses 223611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 189953 # number of SCUpgradeReq MSHR misses 223711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 189953 # number of SCUpgradeReq MSHR misses 223811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses 223911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses 224011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 224800 # number of ReadExReq MSHR misses 224111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::total 224800 # number of ReadExReq MSHR misses 224211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 700000 # number of ReadCleanReq MSHR misses 224311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::total 700000 # number of ReadCleanReq MSHR misses 224411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 931854 # number of ReadSharedReq MSHR misses 224511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::total 931854 # number of ReadSharedReq MSHR misses 224611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 250982 # number of InvalidateReq MSHR misses 224711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::total 250982 # number of InvalidateReq MSHR misses 224811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 19763 # number of demand (read+write) MSHR misses 224911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9424 # number of demand (read+write) MSHR misses 225011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.inst 700000 # number of demand (read+write) MSHR misses 225111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.data 1156654 # number of demand (read+write) MSHR misses 225211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_misses::total 1885841 # number of demand (read+write) MSHR misses 225311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 19763 # number of overall MSHR misses 225411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9424 # number of overall MSHR misses 225511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.inst 700000 # number of overall MSHR misses 225611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.data 1156654 # number of overall MSHR misses 225711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 714287 # number of overall MSHR misses 225811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_misses::total 2600128 # number of overall MSHR misses 225911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable 226011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 7183 # number of ReadReq MSHR uncacheable 226111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::total 7278 # number of ReadReq MSHR uncacheable 226211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 7509 # number of WriteReq MSHR uncacheable 226311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::total 7509 # number of WriteReq MSHR uncacheable 226411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses 226511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 14692 # number of overall MSHR uncacheable misses 226611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::total 14787 # number of overall MSHR uncacheable misses 226711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 486444500 # number of ReadReq MSHR miss cycles 226811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 288576500 # number of ReadReq MSHR miss cycles 226911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::total 775021000 # number of ReadReq MSHR miss cycles 227011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 30894742332 # number of HardPFReq MSHR miss cycles 227111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 30894742332 # number of HardPFReq MSHR miss cycles 227211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4083186496 # number of UpgradeReq MSHR miss cycles 227311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4083186496 # number of UpgradeReq MSHR miss cycles 227411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2906568497 # number of SCUpgradeReq MSHR miss cycles 227511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2906568497 # number of SCUpgradeReq MSHR miss cycles 227611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1292000 # number of SCUpgradeFailReq MSHR miss cycles 227711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1292000 # number of SCUpgradeFailReq MSHR miss cycles 227811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8335690998 # number of ReadExReq MSHR miss cycles 227911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8335690998 # number of ReadExReq MSHR miss cycles 228011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 20714350500 # number of ReadCleanReq MSHR miss cycles 228111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 20714350500 # number of ReadCleanReq MSHR miss cycles 228211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 27592853988 # number of ReadSharedReq MSHR miss cycles 228311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 27592853988 # number of ReadSharedReq MSHR miss cycles 228411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6684154500 # number of InvalidateReq MSHR miss cycles 228511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6684154500 # number of InvalidateReq MSHR miss cycles 228611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 486444500 # number of demand (read+write) MSHR miss cycles 228711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 288576500 # number of demand (read+write) MSHR miss cycles 228811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 20714350500 # number of demand (read+write) MSHR miss cycles 228911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 35928544986 # number of demand (read+write) MSHR miss cycles 229011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::total 57417916486 # number of demand (read+write) MSHR miss cycles 229111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 486444500 # number of overall MSHR miss cycles 229211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 288576500 # number of overall MSHR miss cycles 229311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 20714350500 # number of overall MSHR miss cycles 229411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 35928544986 # number of overall MSHR miss cycles 229511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 30894742332 # number of overall MSHR miss cycles 229611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::total 88312658818 # number of overall MSHR miss cycles 229711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9064500 # number of ReadReq MSHR uncacheable cycles 229811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 860524000 # number of ReadReq MSHR uncacheable cycles 229911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 869588500 # number of ReadReq MSHR uncacheable cycles 230011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9064500 # number of overall MSHR uncacheable cycles 230111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 860524000 # number of overall MSHR uncacheable cycles 230211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::total 869588500 # number of overall MSHR uncacheable cycles 230311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.038259 # mshr miss rate for ReadReq accesses 230411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.058958 # mshr miss rate for ReadReq accesses 230511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.043150 # mshr miss rate for ReadReq accesses 230610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 230710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 230811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.999991 # mshr miss rate for UpgradeReq accesses 230911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.999991 # mshr miss rate for UpgradeReq accesses 231011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 231111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 231210636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 231310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 231411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.215245 # mshr miss rate for ReadExReq accesses 231511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.215245 # mshr miss rate for ReadExReq accesses 231611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.079250 # mshr miss rate for ReadCleanReq accesses 231711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.079250 # mshr miss rate for ReadCleanReq accesses 231811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.261400 # mshr miss rate for ReadSharedReq accesses 231911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.261400 # mshr miss rate for ReadSharedReq accesses 232011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.636048 # mshr miss rate for InvalidateReq accesses 232111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.636048 # mshr miss rate for InvalidateReq accesses 232211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.038259 # mshr miss rate for demand accesses 232311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.058958 # mshr miss rate for demand accesses 232411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.079250 # mshr miss rate for demand accesses 232511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.250942 # mshr miss rate for demand accesses 232611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::total 0.133572 # mshr miss rate for demand accesses 232711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.038259 # mshr miss rate for overall accesses 232811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.058958 # mshr miss rate for overall accesses 232911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.079250 # mshr miss rate for overall accesses 233011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.250942 # mshr miss rate for overall accesses 233110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 233211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::total 0.184164 # mshr miss rate for overall accesses 233311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24613.899712 # average ReadReq mshr miss latency 233411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 30621.445246 # average ReadReq mshr miss latency 233511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 26553.636893 # average ReadReq mshr miss latency 233611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43252.561410 # average HardPFReq mshr miss latency 233711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43252.561410 # average HardPFReq mshr miss latency 233811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18894.543812 # average UpgradeReq mshr miss latency 233911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18894.543812 # average UpgradeReq mshr miss latency 234011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15301.514043 # average SCUpgradeReq mshr miss latency 234111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15301.514043 # average SCUpgradeReq mshr miss latency 234211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 430666.666667 # average SCUpgradeFailReq mshr miss latency 234311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 430666.666667 # average SCUpgradeFailReq mshr miss latency 234411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37080.475970 # average ReadExReq mshr miss latency 234511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37080.475970 # average ReadExReq mshr miss latency 234611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29591.929286 # average ReadCleanReq mshr miss latency 234711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29591.929286 # average ReadCleanReq mshr miss latency 234811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 29610.705098 # average ReadSharedReq mshr miss latency 234911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29610.705098 # average ReadSharedReq mshr miss latency 235011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26632.007475 # average InvalidateReq mshr miss latency 235111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26632.007475 # average InvalidateReq mshr miss latency 235211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24613.899712 # average overall mshr miss latency 235311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 30621.445246 # average overall mshr miss latency 235411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29591.929286 # average overall mshr miss latency 235511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31062.482805 # average overall mshr miss latency 235611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::total 30446.849170 # average overall mshr miss latency 235711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24613.899712 # average overall mshr miss latency 235811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 30621.445246 # average overall mshr miss latency 235911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29591.929286 # average overall mshr miss latency 236011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31062.482805 # average overall mshr miss latency 236111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43252.561410 # average overall mshr miss latency 236211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33964.735128 # average overall mshr miss latency 236311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95415.789474 # average ReadReq mshr uncacheable latency 236411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 119800.083531 # average ReadReq mshr uncacheable latency 236511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 119481.794449 # average ReadReq mshr uncacheable latency 236611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95415.789474 # average overall mshr uncacheable latency 236711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 58570.922951 # average overall mshr uncacheable latency 236811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 58807.635085 # average overall mshr uncacheable latency 236911680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_requests 28307892 # Total number of requests made to the snoop filter. 237011680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_requests 14471357 # Number of requests hitting in the snoop filter with a single holder of the requested data. 237111680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1579 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 237211680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_snoops 577788 # Total number of snoops made to the snoop filter. 237311680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_snoops 577774 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 237411680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 14 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 237511680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 237611680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 765944 # Transaction distribution 237711680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 13251577 # Transaction distribution 237811680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution 237911680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 7509 # Transaction distribution 238011680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 7509 # Transaction distribution 238111680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackDirty 4119049 # Transaction distribution 238211680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackClean 10696803 # Transaction distribution 238311680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::CleanEvict 1405207 # Transaction distribution 238411680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFReq 907922 # Transaction distribution 238511680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution 238611680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 426575 # Transaction distribution 238711680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 338167 # Transaction distribution 238811680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 466317 # Transaction distribution 238911680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 47 # Transaction distribution 239011680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeFailResp 83 # Transaction distribution 239111680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 1072889 # Transaction distribution 239211680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 1050772 # Transaction distribution 239311680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 8832858 # Transaction distribution 239411680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 4591457 # Transaction distribution 239511680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateReq 449471 # Transaction distribution 239611680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateResp 394596 # Transaction distribution 239711680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 26498252 # Packet count per connected master and slave (bytes) 239811680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15919614 # Packet count per connected master and slave (bytes) 239911680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 339109 # Packet count per connected master and slave (bytes) 240011680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1095958 # Packet count per connected master and slave (bytes) 240111680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count::total 43852933 # Packet count per connected master and slave (bytes) 240211680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1130579136 # Cumulative packet size per connected master and slave (bytes) 240311680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 615678398 # Cumulative packet size per connected master and slave (bytes) 240411680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1278736 # Cumulative packet size per connected master and slave (bytes) 240511680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4132472 # Cumulative packet size per connected master and slave (bytes) 240611680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size::total 1751668742 # Cumulative packet size per connected master and slave (bytes) 240711680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoops 5086460 # Total snoops (count) 240811680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoopTraffic 75030592 # Total snoop traffic (bytes) 240911680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 19865784 # Request fanout histogram 241011680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 0.045122 # Request fanout histogram 241111680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.207576 # Request fanout histogram 241210585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 241311680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 18969410 95.49% 95.49% # Request fanout histogram 241411680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 896360 4.51% 100.00% # Request fanout histogram 241511680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 14 0.00% 100.00% # Request fanout histogram 241610585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 241711138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 241810827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 241911680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 19865784 # Request fanout histogram 242011680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.reqLayer0.occupancy 28134048478 # Layer occupancy (ticks) 242111201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 242211680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoopLayer0.occupancy 171886209 # Layer occupancy (ticks) 242310585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 242411680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.respLayer0.occupancy 13252138560 # Layer occupancy (ticks) 242510585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 242611680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.respLayer1.occupancy 7328947477 # Layer occupancy (ticks) 242710585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 242811680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.respLayer2.occupancy 179350830 # Layer occupancy (ticks) 242910585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 243011680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.respLayer3.occupancy 579510776 # Layer occupancy (ticks) 243110585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 243211680SCurtis.Dunham@arm.comsystem.iobus.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 243311680SCurtis.Dunham@arm.comsystem.iobus.trans_dist::ReadReq 40272 # Transaction distribution 243411680SCurtis.Dunham@arm.comsystem.iobus.trans_dist::ReadResp 40272 # Transaction distribution 243511680SCurtis.Dunham@arm.comsystem.iobus.trans_dist::WriteReq 136595 # Transaction distribution 243611680SCurtis.Dunham@arm.comsystem.iobus.trans_dist::WriteResp 136595 # Transaction distribution 243711680SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47628 # Packet count per connected master and slave (bytes) 243810585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 243911245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 244010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 244110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 244210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 244310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 244410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 244510585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 244610585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 244710585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 244811680SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 244910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 245011680SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122510 # Packet count per connected master and slave (bytes) 245111680SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231144 # Packet count per connected master and slave (bytes) 245211680SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231144 # Packet count per connected master and slave (bytes) 245310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 245410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 245511680SCurtis.Dunham@arm.comsystem.iobus.pkt_count::total 353734 # Packet count per connected master and slave (bytes) 245611680SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47648 # Cumulative packet size per connected master and slave (bytes) 245710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 245811245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 245910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 246010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 246110585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 246210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 246310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 246410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 246510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 246610585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 246711680SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 246810585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 246911680SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::total 155640 # Cumulative packet size per connected master and slave (bytes) 247011680SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338592 # Cumulative packet size per connected master and slave (bytes) 247111680SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7338592 # Cumulative packet size per connected master and slave (bytes) 247210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 247310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 247411680SCurtis.Dunham@arm.comsystem.iobus.pkt_size::total 7496318 # Cumulative packet size per connected master and slave (bytes) 247511680SCurtis.Dunham@arm.comsystem.iobus.reqLayer0.occupancy 42593000 # Layer occupancy (ticks) 247610585Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 247711680SCurtis.Dunham@arm.comsystem.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) 247810585Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 247911680SCurtis.Dunham@arm.comsystem.iobus.reqLayer2.occupancy 316000 # Layer occupancy (ticks) 248010585Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 248111680SCurtis.Dunham@arm.comsystem.iobus.reqLayer3.occupancy 10500 # Layer occupancy (ticks) 248210585Sandreas.hansson@arm.comsystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 248311680SCurtis.Dunham@arm.comsystem.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) 248411245Sandreas.sandberg@arm.comsystem.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 248511680SCurtis.Dunham@arm.comsystem.iobus.reqLayer10.occupancy 10500 # Layer occupancy (ticks) 248610585Sandreas.hansson@arm.comsystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 248711606Sandreas.sandberg@arm.comsystem.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) 248810585Sandreas.hansson@arm.comsystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 248911680SCurtis.Dunham@arm.comsystem.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) 249010585Sandreas.hansson@arm.comsystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 249111570SCurtis.Dunham@arm.comsystem.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) 249210585Sandreas.hansson@arm.comsystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 249311680SCurtis.Dunham@arm.comsystem.iobus.reqLayer16.occupancy 16000 # Layer occupancy (ticks) 249410585Sandreas.hansson@arm.comsystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 249511680SCurtis.Dunham@arm.comsystem.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) 249610585Sandreas.hansson@arm.comsystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 249711680SCurtis.Dunham@arm.comsystem.iobus.reqLayer23.occupancy 25879501 # Layer occupancy (ticks) 249810585Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 249911680SCurtis.Dunham@arm.comsystem.iobus.reqLayer24.occupancy 34434000 # Layer occupancy (ticks) 250010585Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 250111680SCurtis.Dunham@arm.comsystem.iobus.reqLayer25.occupancy 569469195 # Layer occupancy (ticks) 250210585Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 250311680SCurtis.Dunham@arm.comsystem.iobus.respLayer0.occupancy 92646000 # Layer occupancy (ticks) 250410585Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 250511680SCurtis.Dunham@arm.comsystem.iobus.respLayer3.occupancy 147840000 # Layer occupancy (ticks) 250610585Sandreas.hansson@arm.comsystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 250710892Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 250810585Sandreas.hansson@arm.comsystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 250911680SCurtis.Dunham@arm.comsystem.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 251011680SCurtis.Dunham@arm.comsystem.iocache.tags.replacements 115567 # number of replacements 251111680SCurtis.Dunham@arm.comsystem.iocache.tags.tagsinuse 11.304352 # Cycle average of tags in use 251211336Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 251311680SCurtis.Dunham@arm.comsystem.iocache.tags.sampled_refs 115583 # Sample count of references to valid blocks. 251411336Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 251511680SCurtis.Dunham@arm.comsystem.iocache.tags.warmup_cycle 9167343261000 # Cycle when the warmup percentage was hit. 251611680SCurtis.Dunham@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 7.387949 # Average occupied blocks per requestor 251711680SCurtis.Dunham@arm.comsystem.iocache.tags.occ_blocks::realview.ide 3.916404 # Average occupied blocks per requestor 251811680SCurtis.Dunham@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.461747 # Average percentage of cache occupancy 251911680SCurtis.Dunham@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.244775 # Average percentage of cache occupancy 252011680SCurtis.Dunham@arm.comsystem.iocache.tags.occ_percent::total 0.706522 # Average percentage of cache occupancy 252110585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 252210827Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 252310585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 252411680SCurtis.Dunham@arm.comsystem.iocache.tags.tag_accesses 1040505 # Number of tag accesses 252511680SCurtis.Dunham@arm.comsystem.iocache.tags.data_accesses 1040505 # Number of data accesses 252611680SCurtis.Dunham@arm.comsystem.iocache.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 252710585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 252811680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_misses::realview.ide 8844 # number of ReadReq misses 252911680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_misses::total 8881 # number of ReadReq misses 253010585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 253110585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 253211606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 253311606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 253410585Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 253511680SCurtis.Dunham@arm.comsystem.iocache.demand_misses::realview.ide 115572 # number of demand (read+write) misses 253611680SCurtis.Dunham@arm.comsystem.iocache.demand_misses::total 115612 # number of demand (read+write) misses 253710585Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 253811680SCurtis.Dunham@arm.comsystem.iocache.overall_misses::realview.ide 115572 # number of overall misses 253911680SCurtis.Dunham@arm.comsystem.iocache.overall_misses::total 115612 # number of overall misses 254011680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5196500 # number of ReadReq miss cycles 254111680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_miss_latency::realview.ide 1979797452 # number of ReadReq miss cycles 254211680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_miss_latency::total 1984993952 # number of ReadReq miss cycles 254310726Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 254410726Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 254511680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_miss_latency::realview.ide 13211000243 # number of WriteLineReq miss cycles 254611680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_miss_latency::total 13211000243 # number of WriteLineReq miss cycles 254711680SCurtis.Dunham@arm.comsystem.iocache.demand_miss_latency::realview.ethernet 5565500 # number of demand (read+write) miss cycles 254811680SCurtis.Dunham@arm.comsystem.iocache.demand_miss_latency::realview.ide 15190797695 # number of demand (read+write) miss cycles 254911680SCurtis.Dunham@arm.comsystem.iocache.demand_miss_latency::total 15196363195 # number of demand (read+write) miss cycles 255011680SCurtis.Dunham@arm.comsystem.iocache.overall_miss_latency::realview.ethernet 5565500 # number of overall miss cycles 255111680SCurtis.Dunham@arm.comsystem.iocache.overall_miss_latency::realview.ide 15190797695 # number of overall miss cycles 255211680SCurtis.Dunham@arm.comsystem.iocache.overall_miss_latency::total 15196363195 # number of overall miss cycles 255310585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 255411680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8844 # number of ReadReq accesses(hits+misses) 255511680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_accesses::total 8881 # number of ReadReq accesses(hits+misses) 255610585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 255710585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 255811606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 255911606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 256010585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 256111680SCurtis.Dunham@arm.comsystem.iocache.demand_accesses::realview.ide 115572 # number of demand (read+write) accesses 256211680SCurtis.Dunham@arm.comsystem.iocache.demand_accesses::total 115612 # number of demand (read+write) accesses 256310585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 256411680SCurtis.Dunham@arm.comsystem.iocache.overall_accesses::realview.ide 115572 # number of overall (read+write) accesses 256511680SCurtis.Dunham@arm.comsystem.iocache.overall_accesses::total 115612 # number of overall (read+write) accesses 256610585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 256710585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 256810585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 256910585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 257010585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 257111336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 257211336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 257310585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 257410585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 257510585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 257610585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 257710585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 257810585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 257911680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 140445.945946 # average ReadReq miss latency 258011680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 223857.694708 # average ReadReq miss latency 258111680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 223510.184889 # average ReadReq miss latency 258210726Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 258310726Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 258411680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::realview.ide 123781.952655 # average WriteLineReq miss latency 258511680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 123781.952655 # average WriteLineReq miss latency 258611680SCurtis.Dunham@arm.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 139137.500000 # average overall miss latency 258711680SCurtis.Dunham@arm.comsystem.iocache.demand_avg_miss_latency::realview.ide 131440.121266 # average overall miss latency 258811680SCurtis.Dunham@arm.comsystem.iocache.demand_avg_miss_latency::total 131442.784443 # average overall miss latency 258911680SCurtis.Dunham@arm.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 139137.500000 # average overall miss latency 259011680SCurtis.Dunham@arm.comsystem.iocache.overall_avg_miss_latency::realview.ide 131440.121266 # average overall miss latency 259111680SCurtis.Dunham@arm.comsystem.iocache.overall_avg_miss_latency::total 131442.784443 # average overall miss latency 259211680SCurtis.Dunham@arm.comsystem.iocache.blocked_cycles::no_mshrs 49739 # number of cycles access was blocked 259310585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 259411680SCurtis.Dunham@arm.comsystem.iocache.blocked::no_mshrs 3574 # number of cycles access was blocked 259510585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 259611680SCurtis.Dunham@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 13.916900 # average number of cycles each access was blocked 259710585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 259811680SCurtis.Dunham@arm.comsystem.iocache.writebacks::writebacks 106693 # number of writebacks 259911680SCurtis.Dunham@arm.comsystem.iocache.writebacks::total 106693 # number of writebacks 260010585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 260111680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8844 # number of ReadReq MSHR misses 260211680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_misses::total 8881 # number of ReadReq MSHR misses 260310585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 260410585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 260511606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 260611606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 260710585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 260811680SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_misses::realview.ide 115572 # number of demand (read+write) MSHR misses 260911680SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_misses::total 115612 # number of demand (read+write) MSHR misses 261010585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 261111680SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_misses::realview.ide 115572 # number of overall MSHR misses 261211680SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_misses::total 115612 # number of overall MSHR misses 261311680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3346500 # number of ReadReq MSHR miss cycles 261411680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1537597452 # number of ReadReq MSHR miss cycles 261511680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 1540943952 # number of ReadReq MSHR miss cycles 261610892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 261710892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 261811680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7865666947 # number of WriteLineReq MSHR miss cycles 261911680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 7865666947 # number of WriteLineReq MSHR miss cycles 262011680SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3565500 # number of demand (read+write) MSHR miss cycles 262111680SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ide 9403264399 # number of demand (read+write) MSHR miss cycles 262211680SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_miss_latency::total 9406829899 # number of demand (read+write) MSHR miss cycles 262311680SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3565500 # number of overall MSHR miss cycles 262411680SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ide 9403264399 # number of overall MSHR miss cycles 262511680SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_miss_latency::total 9406829899 # number of overall MSHR miss cycles 262610585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 262710585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 262810585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 262910585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 263010585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 263111336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 263211336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 263310585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 263410585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 263510585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 263610585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 263710585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 263810585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 263911680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90445.945946 # average ReadReq mshr miss latency 264011680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 173857.694708 # average ReadReq mshr miss latency 264111680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 173510.184889 # average ReadReq mshr miss latency 264210892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 264310892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 264411680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 73698.251134 # average WriteLineReq mshr miss latency 264511680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 73698.251134 # average WriteLineReq mshr miss latency 264611680SCurtis.Dunham@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89137.500000 # average overall mshr miss latency 264711680SCurtis.Dunham@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 81362.824897 # average overall mshr miss latency 264811680SCurtis.Dunham@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 81365.514817 # average overall mshr miss latency 264911680SCurtis.Dunham@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89137.500000 # average overall mshr miss latency 265011680SCurtis.Dunham@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 81362.824897 # average overall mshr miss latency 265111680SCurtis.Dunham@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 81365.514817 # average overall mshr miss latency 265211680SCurtis.Dunham@arm.comsystem.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 265311680SCurtis.Dunham@arm.comsystem.l2c.tags.replacements 1396284 # number of replacements 265411680SCurtis.Dunham@arm.comsystem.l2c.tags.tagsinuse 65138.751942 # Cycle average of tags in use 265511680SCurtis.Dunham@arm.comsystem.l2c.tags.total_refs 7016729 # Total number of references to valid blocks. 265611680SCurtis.Dunham@arm.comsystem.l2c.tags.sampled_refs 1457215 # Sample count of references to valid blocks. 265711680SCurtis.Dunham@arm.comsystem.l2c.tags.avg_refs 4.815164 # Average number of references to valid blocks. 265811680SCurtis.Dunham@arm.comsystem.l2c.tags.warmup_cycle 8133240500 # Cycle when the warmup percentage was hit. 265911680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::writebacks 10857.852094 # Average occupied blocks per requestor 266011680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 193.720367 # Average occupied blocks per requestor 266111680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 194.423316 # Average occupied blocks per requestor 266211680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 4494.530949 # Average occupied blocks per requestor 266311680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 16342.707209 # Average occupied blocks per requestor 266411680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9582.831884 # Average occupied blocks per requestor 266511680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 263.988799 # Average occupied blocks per requestor 266611680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 269.731759 # Average occupied blocks per requestor 266711680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 4576.542600 # Average occupied blocks per requestor 266811680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 8162.860696 # Average occupied blocks per requestor 266911680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 10199.562268 # Average occupied blocks per requestor 267011680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::writebacks 0.165678 # Average percentage of cache occupancy 267111680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.002956 # Average percentage of cache occupancy 267211680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.002967 # Average percentage of cache occupancy 267311680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.068581 # Average percentage of cache occupancy 267411680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.249370 # Average percentage of cache occupancy 267511680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.146222 # Average percentage of cache occupancy 267611680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.004028 # Average percentage of cache occupancy 267711680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.004116 # Average percentage of cache occupancy 267811680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.069832 # Average percentage of cache occupancy 267911680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.124555 # Average percentage of cache occupancy 268011680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.155633 # Average percentage of cache occupancy 268111680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::total 0.993938 # Average percentage of cache occupancy 268211680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_blocks::1022 9763 # Occupied blocks per task id 268311680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 241 # Occupied blocks per task id 268411680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 50927 # Occupied blocks per task id 268511680SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1022::2 80 # Occupied blocks per task id 268611680SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1022::3 414 # Occupied blocks per task id 268711680SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1022::4 9269 # Occupied blocks per task id 268811680SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 241 # Occupied blocks per task id 268911680SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id 269011680SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id 269111680SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 1371 # Occupied blocks per task id 269211680SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 4645 # Occupied blocks per task id 269311680SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 44789 # Occupied blocks per task id 269411680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_percent::1022 0.148972 # Percentage of cache occupancy per task id 269511680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.003677 # Percentage of cache occupancy per task id 269611680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.777084 # Percentage of cache occupancy per task id 269711680SCurtis.Dunham@arm.comsystem.l2c.tags.tag_accesses 77350226 # Number of tag accesses 269811680SCurtis.Dunham@arm.comsystem.l2c.tags.data_accesses 77350226 # Number of data accesses 269911680SCurtis.Dunham@arm.comsystem.l2c.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 270011680SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_hits::writebacks 2692321 # number of WritebackDirty hits 270111680SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_hits::total 2692321 # number of WritebackDirty hits 270211680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 204225 # number of UpgradeReq hits 270311680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 155483 # number of UpgradeReq hits 270411680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::total 359708 # number of UpgradeReq hits 270511680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 52320 # number of SCUpgradeReq hits 270611680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 51074 # number of SCUpgradeReq hits 270711680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_hits::total 103394 # number of SCUpgradeReq hits 270811680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 55531 # number of ReadExReq hits 270911680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 51791 # number of ReadExReq hits 271011680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_hits::total 107322 # number of ReadExReq hits 271111680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 13410 # number of ReadSharedReq hits 271211680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 5332 # number of ReadSharedReq hits 271311680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 636242 # number of ReadSharedReq hits 271411680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 595342 # number of ReadSharedReq hits 271511680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 315678 # number of ReadSharedReq hits 271611680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 10946 # number of ReadSharedReq hits 271711680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 4404 # number of ReadSharedReq hits 271811680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 639193 # number of ReadSharedReq hits 271911680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 560416 # number of ReadSharedReq hits 272011680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 301207 # number of ReadSharedReq hits 272111680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::total 3082170 # number of ReadSharedReq hits 272211680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_hits::cpu0.data 138800 # number of InvalidateReq hits 272311680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_hits::cpu1.data 132737 # number of InvalidateReq hits 272411680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_hits::total 271537 # number of InvalidateReq hits 272511680SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 13410 # number of demand (read+write) hits 272611680SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 5332 # number of demand (read+write) hits 272711680SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.inst 636242 # number of demand (read+write) hits 272811680SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.data 650873 # number of demand (read+write) hits 272911680SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.l2cache.prefetcher 315678 # number of demand (read+write) hits 273011680SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 10946 # number of demand (read+write) hits 273111680SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 4404 # number of demand (read+write) hits 273211680SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.inst 639193 # number of demand (read+write) hits 273311680SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.data 612207 # number of demand (read+write) hits 273411680SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.l2cache.prefetcher 301207 # number of demand (read+write) hits 273511680SCurtis.Dunham@arm.comsystem.l2c.demand_hits::total 3189492 # number of demand (read+write) hits 273611680SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 13410 # number of overall hits 273711680SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 5332 # number of overall hits 273811680SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.inst 636242 # number of overall hits 273911680SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.data 650873 # number of overall hits 274011680SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.l2cache.prefetcher 315678 # number of overall hits 274111680SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 10946 # number of overall hits 274211680SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 4404 # number of overall hits 274311680SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.inst 639193 # number of overall hits 274411680SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.data 612207 # number of overall hits 274511680SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.l2cache.prefetcher 301207 # number of overall hits 274611680SCurtis.Dunham@arm.comsystem.l2c.overall_hits::total 3189492 # number of overall hits 274711680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 22618 # number of UpgradeReq misses 274811680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 28127 # number of UpgradeReq misses 274911680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::total 50745 # number of UpgradeReq misses 275011680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 499 # number of SCUpgradeReq misses 275111680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 689 # number of SCUpgradeReq misses 275211680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_misses::total 1188 # number of SCUpgradeReq misses 275311680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 80171 # number of ReadExReq misses 275411680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 45173 # number of ReadExReq misses 275511680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::total 125344 # number of ReadExReq misses 275611680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1994 # number of ReadSharedReq misses 275711680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 1777 # number of ReadSharedReq misses 275811680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 61929 # number of ReadSharedReq misses 275911680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 136966 # number of ReadSharedReq misses 276011680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 215441 # number of ReadSharedReq misses 276111680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1649 # number of ReadSharedReq misses 276211680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.itb.walker 1460 # number of ReadSharedReq misses 276311680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 60807 # number of ReadSharedReq misses 276411680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 104797 # number of ReadSharedReq misses 276511680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 187062 # number of ReadSharedReq misses 276611680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::total 773882 # number of ReadSharedReq misses 276711680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_misses::cpu0.data 449504 # number of InvalidateReq misses 276811680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_misses::cpu1.data 106576 # number of InvalidateReq misses 276911680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_misses::total 556080 # number of InvalidateReq misses 277011680SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 1994 # number of demand (read+write) misses 277111680SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 1777 # number of demand (read+write) misses 277211680SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.inst 61929 # number of demand (read+write) misses 277311680SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.data 217137 # number of demand (read+write) misses 277411680SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.l2cache.prefetcher 215441 # number of demand (read+write) misses 277511680SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 1649 # number of demand (read+write) misses 277611680SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.itb.walker 1460 # number of demand (read+write) misses 277711680SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.inst 60807 # number of demand (read+write) misses 277811680SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.data 149970 # number of demand (read+write) misses 277911680SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.l2cache.prefetcher 187062 # number of demand (read+write) misses 278011680SCurtis.Dunham@arm.comsystem.l2c.demand_misses::total 899226 # number of demand (read+write) misses 278111680SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 1994 # number of overall misses 278211680SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 1777 # number of overall misses 278311680SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.inst 61929 # number of overall misses 278411680SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.data 217137 # number of overall misses 278511680SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.l2cache.prefetcher 215441 # number of overall misses 278611680SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 1649 # number of overall misses 278711680SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.itb.walker 1460 # number of overall misses 278811680SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.inst 60807 # number of overall misses 278911680SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.data 149970 # number of overall misses 279011680SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.l2cache.prefetcher 187062 # number of overall misses 279111680SCurtis.Dunham@arm.comsystem.l2c.overall_misses::total 899226 # number of overall misses 279211680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu0.data 166509500 # number of UpgradeReq miss cycles 279311680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu1.data 180855500 # number of UpgradeReq miss cycles 279411680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_latency::total 347365000 # number of UpgradeReq miss cycles 279511680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu0.data 6105500 # number of SCUpgradeReq miss cycles 279611680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu1.data 8200500 # number of SCUpgradeReq miss cycles 279711680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_latency::total 14306000 # number of SCUpgradeReq miss cycles 279811680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_latency::cpu0.data 8647457500 # number of ReadExReq miss cycles 279911680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_latency::cpu1.data 4904092500 # number of ReadExReq miss cycles 280011680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_latency::total 13551550000 # number of ReadExReq miss cycles 280111680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 211493000 # number of ReadSharedReq miss cycles 280211680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 194819500 # number of ReadSharedReq miss cycles 280311680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.inst 6896332000 # number of ReadSharedReq miss cycles 280411680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.data 15165548000 # number of ReadSharedReq miss cycles 280511680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 30671403248 # number of ReadSharedReq miss cycles 280611680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 166890000 # number of ReadSharedReq miss cycles 280711680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 150626500 # number of ReadSharedReq miss cycles 280811680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.inst 6689940000 # number of ReadSharedReq miss cycles 280911680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.data 12141260000 # number of ReadSharedReq miss cycles 281011680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 25575724378 # number of ReadSharedReq miss cycles 281111680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::total 97864036626 # number of ReadSharedReq miss cycles 281211680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_latency::cpu0.data 46615500 # number of InvalidateReq miss cycles 281311680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_latency::cpu1.data 36764000 # number of InvalidateReq miss cycles 281411680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_latency::total 83379500 # number of InvalidateReq miss cycles 281511680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu0.dtb.walker 211493000 # number of demand (read+write) miss cycles 281611680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu0.itb.walker 194819500 # number of demand (read+write) miss cycles 281711680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu0.inst 6896332000 # number of demand (read+write) miss cycles 281811680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu0.data 23813005500 # number of demand (read+write) miss cycles 281911680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 30671403248 # number of demand (read+write) miss cycles 282011680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu1.dtb.walker 166890000 # number of demand (read+write) miss cycles 282111680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu1.itb.walker 150626500 # number of demand (read+write) miss cycles 282211680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu1.inst 6689940000 # number of demand (read+write) miss cycles 282311680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu1.data 17045352500 # number of demand (read+write) miss cycles 282411680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 25575724378 # number of demand (read+write) miss cycles 282511680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::total 111415586626 # number of demand (read+write) miss cycles 282611680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu0.dtb.walker 211493000 # number of overall miss cycles 282711680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu0.itb.walker 194819500 # number of overall miss cycles 282811680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu0.inst 6896332000 # number of overall miss cycles 282911680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu0.data 23813005500 # number of overall miss cycles 283011680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 30671403248 # number of overall miss cycles 283111680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu1.dtb.walker 166890000 # number of overall miss cycles 283211680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu1.itb.walker 150626500 # number of overall miss cycles 283311680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu1.inst 6689940000 # number of overall miss cycles 283411680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu1.data 17045352500 # number of overall miss cycles 283511680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 25575724378 # number of overall miss cycles 283611680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::total 111415586626 # number of overall miss cycles 283711680SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 2692321 # number of WritebackDirty accesses(hits+misses) 283811680SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_accesses::total 2692321 # number of WritebackDirty accesses(hits+misses) 283911680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 226843 # number of UpgradeReq accesses(hits+misses) 284011680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 183610 # number of UpgradeReq accesses(hits+misses) 284111680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::total 410453 # number of UpgradeReq accesses(hits+misses) 284211680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 52819 # number of SCUpgradeReq accesses(hits+misses) 284311680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 51763 # number of SCUpgradeReq accesses(hits+misses) 284411680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_accesses::total 104582 # number of SCUpgradeReq accesses(hits+misses) 284511680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 135702 # number of ReadExReq accesses(hits+misses) 284611680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 96964 # number of ReadExReq accesses(hits+misses) 284711680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::total 232666 # number of ReadExReq accesses(hits+misses) 284811680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 15404 # number of ReadSharedReq accesses(hits+misses) 284911680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7109 # number of ReadSharedReq accesses(hits+misses) 285011680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 698171 # number of ReadSharedReq accesses(hits+misses) 285111680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 732308 # number of ReadSharedReq accesses(hits+misses) 285211680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 531119 # number of ReadSharedReq accesses(hits+misses) 285311680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 12595 # number of ReadSharedReq accesses(hits+misses) 285411680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 5864 # number of ReadSharedReq accesses(hits+misses) 285511680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 700000 # number of ReadSharedReq accesses(hits+misses) 285611680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 665213 # number of ReadSharedReq accesses(hits+misses) 285711680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 488269 # number of ReadSharedReq accesses(hits+misses) 285811680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::total 3856052 # number of ReadSharedReq accesses(hits+misses) 285911680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_accesses::cpu0.data 588304 # number of InvalidateReq accesses(hits+misses) 286011680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_accesses::cpu1.data 239313 # number of InvalidateReq accesses(hits+misses) 286111680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_accesses::total 827617 # number of InvalidateReq accesses(hits+misses) 286211680SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 15404 # number of demand (read+write) accesses 286311680SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 7109 # number of demand (read+write) accesses 286411680SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.inst 698171 # number of demand (read+write) accesses 286511680SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.data 868010 # number of demand (read+write) accesses 286611680SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.l2cache.prefetcher 531119 # number of demand (read+write) accesses 286711680SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 12595 # number of demand (read+write) accesses 286811680SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 5864 # number of demand (read+write) accesses 286911680SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.inst 700000 # number of demand (read+write) accesses 287011680SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.data 762177 # number of demand (read+write) accesses 287111680SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.l2cache.prefetcher 488269 # number of demand (read+write) accesses 287211680SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::total 4088718 # number of demand (read+write) accesses 287311680SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 15404 # number of overall (read+write) accesses 287411680SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 7109 # number of overall (read+write) accesses 287511680SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.inst 698171 # number of overall (read+write) accesses 287611680SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.data 868010 # number of overall (read+write) accesses 287711680SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.l2cache.prefetcher 531119 # number of overall (read+write) accesses 287811680SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 12595 # number of overall (read+write) accesses 287911680SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 5864 # number of overall (read+write) accesses 288011680SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.inst 700000 # number of overall (read+write) accesses 288111680SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.data 762177 # number of overall (read+write) accesses 288211680SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.l2cache.prefetcher 488269 # number of overall (read+write) accesses 288311680SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::total 4088718 # number of overall (read+write) accesses 288411680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.099708 # miss rate for UpgradeReq accesses 288511680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.153189 # miss rate for UpgradeReq accesses 288611680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.123632 # miss rate for UpgradeReq accesses 288711680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.009447 # miss rate for SCUpgradeReq accesses 288811680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.013311 # miss rate for SCUpgradeReq accesses 288911680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.011360 # miss rate for SCUpgradeReq accesses 289011680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.590787 # miss rate for ReadExReq accesses 289111680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.465874 # miss rate for ReadExReq accesses 289211680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.538729 # miss rate for ReadExReq accesses 289311680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.129447 # miss rate for ReadSharedReq accesses 289411680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.249965 # miss rate for ReadSharedReq accesses 289511680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.088702 # miss rate for ReadSharedReq accesses 289611680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.187033 # miss rate for ReadSharedReq accesses 289711680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.405636 # miss rate for ReadSharedReq accesses 289811680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.130925 # miss rate for ReadSharedReq accesses 289911680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.248977 # miss rate for ReadSharedReq accesses 290011680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.086867 # miss rate for ReadSharedReq accesses 290111680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.157539 # miss rate for ReadSharedReq accesses 290211680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.383113 # miss rate for ReadSharedReq accesses 290311680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.200693 # miss rate for ReadSharedReq accesses 290411680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu0.data 0.764068 # miss rate for InvalidateReq accesses 290511680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu1.data 0.445341 # miss rate for InvalidateReq accesses 290611680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_rate::total 0.671905 # miss rate for InvalidateReq accesses 290711680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.129447 # miss rate for demand accesses 290811680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.249965 # miss rate for demand accesses 290911680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.088702 # miss rate for demand accesses 291011680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.250155 # miss rate for demand accesses 291111680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.405636 # miss rate for demand accesses 291211680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.130925 # miss rate for demand accesses 291311680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.248977 # miss rate for demand accesses 291411680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.086867 # miss rate for demand accesses 291511680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.196765 # miss rate for demand accesses 291611680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.383113 # miss rate for demand accesses 291711680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::total 0.219929 # miss rate for demand accesses 291811680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.129447 # miss rate for overall accesses 291911680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.249965 # miss rate for overall accesses 292011680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.088702 # miss rate for overall accesses 292111680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.250155 # miss rate for overall accesses 292211680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.405636 # miss rate for overall accesses 292311680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.130925 # miss rate for overall accesses 292411680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.248977 # miss rate for overall accesses 292511680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.086867 # miss rate for overall accesses 292611680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.196765 # miss rate for overall accesses 292711680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.383113 # miss rate for overall accesses 292811680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::total 0.219929 # miss rate for overall accesses 292911680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu0.data 7361.813600 # average UpgradeReq miss latency 293011680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6429.960536 # average UpgradeReq miss latency 293111680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::total 6845.304956 # average UpgradeReq miss latency 293211680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 12235.470942 # average SCUpgradeReq miss latency 293311680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 11902.031930 # average SCUpgradeReq miss latency 293411680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::total 12042.087542 # average SCUpgradeReq miss latency 293511680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu0.data 107862.662309 # average ReadExReq miss latency 293611680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu1.data 108562.470945 # average ReadExReq miss latency 293711680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_miss_latency::total 108114.867884 # average ReadExReq miss latency 293811680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 106064.694082 # average ReadSharedReq miss latency 293911680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 109633.933596 # average ReadSharedReq miss latency 294011680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 111358.684946 # average ReadSharedReq miss latency 294111680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 110724.909832 # average ReadSharedReq miss latency 294211680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 142365.674352 # average ReadSharedReq miss latency 294311680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 101206.791995 # average ReadSharedReq miss latency 294411680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 103168.835616 # average ReadSharedReq miss latency 294511680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 110019.241206 # average ReadSharedReq miss latency 294611680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 115855.034018 # average ReadSharedReq miss latency 294711680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 136723.248859 # average ReadSharedReq miss latency 294811680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::total 126458.603025 # average ReadSharedReq miss latency 294911680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_avg_miss_latency::cpu0.data 103.704305 # average InvalidateReq miss latency 295011680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_avg_miss_latency::cpu1.data 344.955712 # average InvalidateReq miss latency 295111680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_avg_miss_latency::total 149.941555 # average InvalidateReq miss latency 295211680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.dtb.walker 106064.694082 # average overall miss latency 295311680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.itb.walker 109633.933596 # average overall miss latency 295411680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.inst 111358.684946 # average overall miss latency 295511680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.data 109668.115061 # average overall miss latency 295611680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 142365.674352 # average overall miss latency 295711680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.dtb.walker 101206.791995 # average overall miss latency 295811680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.itb.walker 103168.835616 # average overall miss latency 295911680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.inst 110019.241206 # average overall miss latency 296011680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.data 113658.415016 # average overall miss latency 296111680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 136723.248859 # average overall miss latency 296211680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::total 123901.651672 # average overall miss latency 296311680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.dtb.walker 106064.694082 # average overall miss latency 296411680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.itb.walker 109633.933596 # average overall miss latency 296511680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.inst 111358.684946 # average overall miss latency 296611680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.data 109668.115061 # average overall miss latency 296711680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 142365.674352 # average overall miss latency 296811680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.dtb.walker 101206.791995 # average overall miss latency 296911680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.itb.walker 103168.835616 # average overall miss latency 297011680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.inst 110019.241206 # average overall miss latency 297111680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.data 113658.415016 # average overall miss latency 297211680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 136723.248859 # average overall miss latency 297311680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::total 123901.651672 # average overall miss latency 297411680SCurtis.Dunham@arm.comsystem.l2c.blocked_cycles::no_mshrs 622 # number of cycles access was blocked 297510515SAli.Saidi@ARM.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 297611680SCurtis.Dunham@arm.comsystem.l2c.blocked::no_mshrs 12 # number of cycles access was blocked 297710515SAli.Saidi@ARM.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 297811680SCurtis.Dunham@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs 51.833333 # average number of cycles each access was blocked 297910515SAli.Saidi@ARM.comsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 298011680SCurtis.Dunham@arm.comsystem.l2c.writebacks::writebacks 1054868 # number of writebacks 298111680SCurtis.Dunham@arm.comsystem.l2c.writebacks::total 1054868 # number of writebacks 298211680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.inst 139 # number of ReadSharedReq MSHR hits 298311680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.data 25 # number of ReadSharedReq MSHR hits 298411680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.l2cache.prefetcher 1 # number of ReadSharedReq MSHR hits 298511680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.inst 132 # number of ReadSharedReq MSHR hits 298611680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.data 14 # number of ReadSharedReq MSHR hits 298711680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_hits::total 311 # number of ReadSharedReq MSHR hits 298811680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::cpu0.inst 139 # number of demand (read+write) MSHR hits 298911680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::cpu0.data 25 # number of demand (read+write) MSHR hits 299011680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits 299111680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::cpu1.inst 132 # number of demand (read+write) MSHR hits 299211680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::cpu1.data 14 # number of demand (read+write) MSHR hits 299311680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::total 311 # number of demand (read+write) MSHR hits 299411680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::cpu0.inst 139 # number of overall MSHR hits 299511680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::cpu0.data 25 # number of overall MSHR hits 299611680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 1 # number of overall MSHR hits 299711680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::cpu1.inst 132 # number of overall MSHR hits 299811680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::cpu1.data 14 # number of overall MSHR hits 299911680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::total 311 # number of overall MSHR hits 300011680SCurtis.Dunham@arm.comsystem.l2c.CleanEvict_mshr_misses::writebacks 56418 # number of CleanEvict MSHR misses 300111680SCurtis.Dunham@arm.comsystem.l2c.CleanEvict_mshr_misses::total 56418 # number of CleanEvict MSHR misses 300211680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu0.data 22618 # number of UpgradeReq MSHR misses 300311680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu1.data 28127 # number of UpgradeReq MSHR misses 300411680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_misses::total 50745 # number of UpgradeReq MSHR misses 300511680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu0.data 499 # number of SCUpgradeReq MSHR misses 300611680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu1.data 689 # number of SCUpgradeReq MSHR misses 300711680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::total 1188 # number of SCUpgradeReq MSHR misses 300811680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu0.data 80171 # number of ReadExReq MSHR misses 300911680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu1.data 45173 # number of ReadExReq MSHR misses 301011680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_misses::total 125344 # number of ReadExReq MSHR misses 301111680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1994 # number of ReadSharedReq MSHR misses 301211680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1777 # number of ReadSharedReq MSHR misses 301311680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.inst 61790 # number of ReadSharedReq MSHR misses 301411680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.data 136941 # number of ReadSharedReq MSHR misses 301511680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 215440 # number of ReadSharedReq MSHR misses 301611680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1649 # number of ReadSharedReq MSHR misses 301711680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1460 # number of ReadSharedReq MSHR misses 301811680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.inst 60675 # number of ReadSharedReq MSHR misses 301911680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.data 104783 # number of ReadSharedReq MSHR misses 302011680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 187062 # number of ReadSharedReq MSHR misses 302111680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::total 773571 # number of ReadSharedReq MSHR misses 302211680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_misses::cpu0.data 449504 # number of InvalidateReq MSHR misses 302311680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_misses::cpu1.data 106576 # number of InvalidateReq MSHR misses 302411680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_misses::total 556080 # number of InvalidateReq MSHR misses 302511680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu0.dtb.walker 1994 # number of demand (read+write) MSHR misses 302611680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu0.itb.walker 1777 # number of demand (read+write) MSHR misses 302711680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu0.inst 61790 # number of demand (read+write) MSHR misses 302811680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu0.data 217112 # number of demand (read+write) MSHR misses 302911680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 215440 # number of demand (read+write) MSHR misses 303011680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu1.dtb.walker 1649 # number of demand (read+write) MSHR misses 303111680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu1.itb.walker 1460 # number of demand (read+write) MSHR misses 303211680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu1.inst 60675 # number of demand (read+write) MSHR misses 303311680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu1.data 149956 # number of demand (read+write) MSHR misses 303411680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 187062 # number of demand (read+write) MSHR misses 303511680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::total 898915 # number of demand (read+write) MSHR misses 303611680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu0.dtb.walker 1994 # number of overall MSHR misses 303711680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu0.itb.walker 1777 # number of overall MSHR misses 303811680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu0.inst 61790 # number of overall MSHR misses 303911680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu0.data 217112 # number of overall MSHR misses 304011680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 215440 # number of overall MSHR misses 304111680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu1.dtb.walker 1649 # number of overall MSHR misses 304211680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu1.itb.walker 1460 # number of overall MSHR misses 304311680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu1.inst 60675 # number of overall MSHR misses 304411680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu1.data 149956 # number of overall MSHR misses 304511680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 187062 # number of overall MSHR misses 304611680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::total 898915 # number of overall MSHR misses 304711680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu0.inst 52284 # number of ReadReq MSHR uncacheable 304811680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu0.data 31212 # number of ReadReq MSHR uncacheable 304911570SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable 305011680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu1.data 7181 # number of ReadReq MSHR uncacheable 305111680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable::total 90772 # number of ReadReq MSHR uncacheable 305211680SCurtis.Dunham@arm.comsystem.l2c.WriteReq_mshr_uncacheable::cpu0.data 30755 # number of WriteReq MSHR uncacheable 305311680SCurtis.Dunham@arm.comsystem.l2c.WriteReq_mshr_uncacheable::cpu1.data 7509 # number of WriteReq MSHR uncacheable 305411680SCurtis.Dunham@arm.comsystem.l2c.WriteReq_mshr_uncacheable::total 38264 # number of WriteReq MSHR uncacheable 305511680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu0.inst 52284 # number of overall MSHR uncacheable misses 305611680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu0.data 61967 # number of overall MSHR uncacheable misses 305711570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses 305811680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu1.data 14690 # number of overall MSHR uncacheable misses 305911680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_misses::total 129036 # number of overall MSHR uncacheable misses 306011680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 461841000 # number of UpgradeReq MSHR miss cycles 306111680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 578903500 # number of UpgradeReq MSHR miss cycles 306211680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::total 1040744500 # number of UpgradeReq MSHR miss cycles 306311680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 11863000 # number of SCUpgradeReq MSHR miss cycles 306411680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 16565000 # number of SCUpgradeReq MSHR miss cycles 306511680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::total 28428000 # number of SCUpgradeReq MSHR miss cycles 306611680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7845723550 # number of ReadExReq MSHR miss cycles 306711680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4452337552 # number of ReadExReq MSHR miss cycles 306811680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::total 12298061102 # number of ReadExReq MSHR miss cycles 306911680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 191553000 # number of ReadSharedReq MSHR miss cycles 307011680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 177048502 # number of ReadSharedReq MSHR miss cycles 307111680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 6267361033 # number of ReadSharedReq MSHR miss cycles 307211680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 13793559696 # number of ReadSharedReq MSHR miss cycles 307311680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 28516814074 # number of ReadSharedReq MSHR miss cycles 307411680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 150400000 # number of ReadSharedReq MSHR miss cycles 307511680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 136026500 # number of ReadSharedReq MSHR miss cycles 307611680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 6069566554 # number of ReadSharedReq MSHR miss cycles 307711680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 11092033207 # number of ReadSharedReq MSHR miss cycles 307811680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 23704989123 # number of ReadSharedReq MSHR miss cycles 307911680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::total 90099351689 # number of ReadSharedReq MSHR miss cycles 308011680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 9394175000 # number of InvalidateReq MSHR miss cycles 308111680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 2170818500 # number of InvalidateReq MSHR miss cycles 308211680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_miss_latency::total 11564993500 # number of InvalidateReq MSHR miss cycles 308311680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 191553000 # number of demand (read+write) MSHR miss cycles 308411680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.itb.walker 177048502 # number of demand (read+write) MSHR miss cycles 308511680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.inst 6267361033 # number of demand (read+write) MSHR miss cycles 308611680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.data 21639283246 # number of demand (read+write) MSHR miss cycles 308711680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 28516814074 # number of demand (read+write) MSHR miss cycles 308811680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 150400000 # number of demand (read+write) MSHR miss cycles 308911680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.itb.walker 136026500 # number of demand (read+write) MSHR miss cycles 309011680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.inst 6069566554 # number of demand (read+write) MSHR miss cycles 309111680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.data 15544370759 # number of demand (read+write) MSHR miss cycles 309211680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 23704989123 # number of demand (read+write) MSHR miss cycles 309311680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::total 102397412791 # number of demand (read+write) MSHR miss cycles 309411680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 191553000 # number of overall MSHR miss cycles 309511680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.itb.walker 177048502 # number of overall MSHR miss cycles 309611680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.inst 6267361033 # number of overall MSHR miss cycles 309711680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.data 21639283246 # number of overall MSHR miss cycles 309811680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 28516814074 # number of overall MSHR miss cycles 309911680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 150400000 # number of overall MSHR miss cycles 310011680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.itb.walker 136026500 # number of overall MSHR miss cycles 310111680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.inst 6069566554 # number of overall MSHR miss cycles 310211680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.data 15544370759 # number of overall MSHR miss cycles 310311680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 23704989123 # number of overall MSHR miss cycles 310411680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::total 102397412791 # number of overall MSHR miss cycles 310511680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3645369500 # number of ReadReq MSHR uncacheable cycles 310611680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5226952503 # number of ReadReq MSHR uncacheable cycles 310711680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7066500 # number of ReadReq MSHR uncacheable cycles 310811680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 731143001 # number of ReadReq MSHR uncacheable cycles 310911680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::total 9610531504 # number of ReadReq MSHR uncacheable cycles 311011680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3645369500 # number of overall MSHR uncacheable cycles 311111680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.data 5226952503 # number of overall MSHR uncacheable cycles 311211680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7066500 # number of overall MSHR uncacheable cycles 311311680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.data 731143001 # number of overall MSHR uncacheable cycles 311411680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_latency::total 9610531504 # number of overall MSHR uncacheable cycles 311510892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 311610892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 311711680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.099708 # mshr miss rate for UpgradeReq accesses 311811680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.153189 # mshr miss rate for UpgradeReq accesses 311911680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::total 0.123632 # mshr miss rate for UpgradeReq accesses 312011680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.009447 # mshr miss rate for SCUpgradeReq accesses 312111680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.013311 # mshr miss rate for SCUpgradeReq accesses 312211680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::total 0.011360 # mshr miss rate for SCUpgradeReq accesses 312311680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.590787 # mshr miss rate for ReadExReq accesses 312411680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.465874 # mshr miss rate for ReadExReq accesses 312511680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::total 0.538729 # mshr miss rate for ReadExReq accesses 312611680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.129447 # mshr miss rate for ReadSharedReq accesses 312711680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.249965 # mshr miss rate for ReadSharedReq accesses 312811680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.088503 # mshr miss rate for ReadSharedReq accesses 312911680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.186999 # mshr miss rate for ReadSharedReq accesses 313011680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.405634 # mshr miss rate for ReadSharedReq accesses 313111680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.130925 # mshr miss rate for ReadSharedReq accesses 313211680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.248977 # mshr miss rate for ReadSharedReq accesses 313311680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.086679 # mshr miss rate for ReadSharedReq accesses 313411680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.157518 # mshr miss rate for ReadSharedReq accesses 313511680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383113 # mshr miss rate for ReadSharedReq accesses 313611680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::total 0.200612 # mshr miss rate for ReadSharedReq accesses 313711680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.764068 # mshr miss rate for InvalidateReq accesses 313811680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.445341 # mshr miss rate for InvalidateReq accesses 313911680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::total 0.671905 # mshr miss rate for InvalidateReq accesses 314011680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.129447 # mshr miss rate for demand accesses 314111680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.249965 # mshr miss rate for demand accesses 314211680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.088503 # mshr miss rate for demand accesses 314311680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.data 0.250126 # mshr miss rate for demand accesses 314411680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.405634 # mshr miss rate for demand accesses 314511680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.130925 # mshr miss rate for demand accesses 314611680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.248977 # mshr miss rate for demand accesses 314711680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.086679 # mshr miss rate for demand accesses 314811680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.data 0.196747 # mshr miss rate for demand accesses 314911680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383113 # mshr miss rate for demand accesses 315011680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::total 0.219853 # mshr miss rate for demand accesses 315111680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.129447 # mshr miss rate for overall accesses 315211680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.249965 # mshr miss rate for overall accesses 315311680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.088503 # mshr miss rate for overall accesses 315411680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.data 0.250126 # mshr miss rate for overall accesses 315511680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.405634 # mshr miss rate for overall accesses 315611680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.130925 # mshr miss rate for overall accesses 315711680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.248977 # mshr miss rate for overall accesses 315811680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.086679 # mshr miss rate for overall accesses 315911680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.data 0.196747 # mshr miss rate for overall accesses 316011680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383113 # mshr miss rate for overall accesses 316111680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::total 0.219853 # mshr miss rate for overall accesses 316211680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20419.179415 # average UpgradeReq mshr miss latency 316311680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20581.771963 # average UpgradeReq mshr miss latency 316411680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 20509.301409 # average UpgradeReq mshr miss latency 316511680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 23773.547094 # average SCUpgradeReq mshr miss latency 316611680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24042.089985 # average SCUpgradeReq mshr miss latency 316711680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 23929.292929 # average SCUpgradeReq mshr miss latency 316811680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 97862.363573 # average ReadExReq mshr miss latency 316911680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 98561.918668 # average ReadExReq mshr miss latency 317011680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 98114.477773 # average ReadExReq mshr miss latency 317111680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 96064.694082 # average ReadSharedReq mshr miss latency 317211680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 99633.371975 # average ReadSharedReq mshr miss latency 317311680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 101430.021573 # average ReadSharedReq mshr miss latency 317411680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 100726.295967 # average ReadSharedReq mshr miss latency 317511680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 132365.457083 # average ReadSharedReq mshr miss latency 317611680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 91206.791995 # average ReadSharedReq mshr miss latency 317711680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 93168.835616 # average ReadSharedReq mshr miss latency 317811680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 100034.059398 # average ReadSharedReq mshr miss latency 317911680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 105857.183007 # average ReadSharedReq mshr miss latency 318011680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126722.632726 # average ReadSharedReq mshr miss latency 318111680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::total 116471.987302 # average ReadSharedReq mshr miss latency 318211680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20898.979764 # average InvalidateReq mshr miss latency 318311680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20368.736864 # average InvalidateReq mshr miss latency 318411680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::total 20797.355596 # average InvalidateReq mshr miss latency 318511680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 96064.694082 # average overall mshr miss latency 318611680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 99633.371975 # average overall mshr miss latency 318711680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 101430.021573 # average overall mshr miss latency 318811680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 99668.757351 # average overall mshr miss latency 318911680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 132365.457083 # average overall mshr miss latency 319011680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 91206.791995 # average overall mshr miss latency 319111680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 93168.835616 # average overall mshr miss latency 319211680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 100034.059398 # average overall mshr miss latency 319311680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 103659.545193 # average overall mshr miss latency 319411680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126722.632726 # average overall mshr miss latency 319511680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 113912.230624 # average overall mshr miss latency 319611680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 96064.694082 # average overall mshr miss latency 319711680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 99633.371975 # average overall mshr miss latency 319811680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 101430.021573 # average overall mshr miss latency 319911680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 99668.757351 # average overall mshr miss latency 320011680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 132365.457083 # average overall mshr miss latency 320111680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 91206.791995 # average overall mshr miss latency 320211680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 93168.835616 # average overall mshr miss latency 320311680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 100034.059398 # average overall mshr miss latency 320411680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 103659.545193 # average overall mshr miss latency 320511680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126722.632726 # average overall mshr miss latency 320611680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 113912.230624 # average overall mshr miss latency 320711680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69722.467677 # average ReadReq mshr uncacheable latency 320811680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167466.118897 # average ReadReq mshr uncacheable latency 320911680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 74384.210526 # average ReadReq mshr uncacheable latency 321011680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 101816.320986 # average ReadReq mshr uncacheable latency 321111680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total 105875.506808 # average ReadReq mshr uncacheable latency 321211680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69722.467677 # average overall mshr uncacheable latency 321311680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 84350.581810 # average overall mshr uncacheable latency 321411680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 74384.210526 # average overall mshr uncacheable latency 321511680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 49771.477263 # average overall mshr uncacheable latency 321611680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::total 74479.459252 # average overall mshr uncacheable latency 321711680SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_requests 3616665 # Total number of requests made to the snoop filter. 321811680SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_requests 2148581 # Number of requests hitting in the snoop filter with a single holder of the requested data. 321911680SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_requests 2925 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 322011502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 322111502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 322211502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 322311680SCurtis.Dunham@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 322411680SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadReq 90772 # Transaction distribution 322511680SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 873224 # Transaction distribution 322611680SCurtis.Dunham@arm.comsystem.membus.trans_dist::WriteReq 38264 # Transaction distribution 322711680SCurtis.Dunham@arm.comsystem.membus.trans_dist::WriteResp 38264 # Transaction distribution 322811680SCurtis.Dunham@arm.comsystem.membus.trans_dist::WritebackDirty 1161561 # Transaction distribution 322911680SCurtis.Dunham@arm.comsystem.membus.trans_dist::CleanEvict 250705 # Transaction distribution 323011680SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeReq 347946 # Transaction distribution 323111680SCurtis.Dunham@arm.comsystem.membus.trans_dist::SCUpgradeReq 273520 # Transaction distribution 323211680SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeResp 24 # Transaction distribution 323311606Sandreas.sandberg@arm.comsystem.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution 323411680SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExReq 139972 # Transaction distribution 323511680SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExResp 124377 # Transaction distribution 323611680SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 782452 # Transaction distribution 323711680SCurtis.Dunham@arm.comsystem.membus.trans_dist::InvalidateReq 660097 # Transaction distribution 323811680SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122510 # Packet count per connected master and slave (bytes) 323911570SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 54 # Packet count per connected master and slave (bytes) 324011680SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25584 # Packet count per connected master and slave (bytes) 324111680SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4392225 # Packet count per connected master and slave (bytes) 324211680SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 4540373 # Packet count per connected master and slave (bytes) 324311680SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238087 # Packet count per connected master and slave (bytes) 324411680SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 238087 # Packet count per connected master and slave (bytes) 324511680SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 4778460 # Packet count per connected master and slave (bytes) 324611680SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155640 # Cumulative packet size per connected master and slave (bytes) 324711570SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1388 # Cumulative packet size per connected master and slave (bytes) 324811680SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51168 # Cumulative packet size per connected master and slave (bytes) 324911680SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 128305664 # Cumulative packet size per connected master and slave (bytes) 325011680SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 128513860 # Cumulative packet size per connected master and slave (bytes) 325111680SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7270464 # Cumulative packet size per connected master and slave (bytes) 325211680SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7270464 # Cumulative packet size per connected master and slave (bytes) 325311680SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 135784324 # Cumulative packet size per connected master and slave (bytes) 325411680SCurtis.Dunham@arm.comsystem.membus.snoops 584171 # Total snoops (count) 325511680SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 172608 # Total snoop traffic (bytes) 325611680SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 2333030 # Request fanout histogram 325711680SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0.013166 # Request fanout histogram 325811680SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0.113984 # Request fanout histogram 325910585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 326011680SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 2302314 98.68% 98.68% # Request fanout histogram 326111680SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 30716 1.32% 100.00% # Request fanout histogram 326210585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 326310585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 326411502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 326510585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 326611680SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 2333030 # Request fanout histogram 326711680SCurtis.Dunham@arm.comsystem.membus.reqLayer0.occupancy 103320999 # Layer occupancy (ticks) 326810585Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 326911570SCurtis.Dunham@arm.comsystem.membus.reqLayer1.occupancy 34812 # Layer occupancy (ticks) 327010585Sandreas.hansson@arm.comsystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 327111680SCurtis.Dunham@arm.comsystem.membus.reqLayer2.occupancy 21353996 # Layer occupancy (ticks) 327210585Sandreas.hansson@arm.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 327311680SCurtis.Dunham@arm.comsystem.membus.reqLayer5.occupancy 8035790677 # Layer occupancy (ticks) 327410585Sandreas.hansson@arm.comsystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 327511680SCurtis.Dunham@arm.comsystem.membus.respLayer2.occupancy 5121349382 # Layer occupancy (ticks) 327610585Sandreas.hansson@arm.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 327711680SCurtis.Dunham@arm.comsystem.membus.respLayer3.occupancy 45284261 # Layer occupancy (ticks) 327810585Sandreas.hansson@arm.comsystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 327911680SCurtis.Dunham@arm.comsystem.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 328011680SCurtis.Dunham@arm.comsystem.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 328111680SCurtis.Dunham@arm.comsystem.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 328211680SCurtis.Dunham@arm.comsystem.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 328311680SCurtis.Dunham@arm.comsystem.realview.gic.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 328411680SCurtis.Dunham@arm.comsystem.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 328511680SCurtis.Dunham@arm.comsystem.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 328611239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 328711239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 328811239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 328911239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 329011239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 329111239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 329211680SCurtis.Dunham@arm.comsystem.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 329311680SCurtis.Dunham@arm.comsystem.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 329410515SAli.Saidi@ARM.comsystem.realview.ethernet.txBytes 966 # Bytes Transmitted 329510515SAli.Saidi@ARM.comsystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 329610515SAli.Saidi@ARM.comsystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 329710515SAli.Saidi@ARM.comsystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 329810515SAli.Saidi@ARM.comsystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 329910515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 330010515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 330110515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 330210515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 330311201Sandreas.hansson@arm.comsystem.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 330410515SAli.Saidi@ARM.comsystem.realview.ethernet.totPackets 3 # Total Packets 330510515SAli.Saidi@ARM.comsystem.realview.ethernet.totBytes 966 # Total Bytes 330610515SAli.Saidi@ARM.comsystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 330711201Sandreas.hansson@arm.comsystem.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 330810515SAli.Saidi@ARM.comsystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 330910515SAli.Saidi@ARM.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 331010515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 331110515SAli.Saidi@ARM.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 331210515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 331310515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 331410515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 331510515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 331610515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 331710515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 331810515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 331910515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 332010515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 332110515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 332210515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 332310515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 332410515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 332510515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 332610515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 332710515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 332810515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 332910515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 333010515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 333110515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 333210515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 333310515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 333410515SAli.Saidi@ARM.comsystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 333510515SAli.Saidi@ARM.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 333611680SCurtis.Dunham@arm.comsystem.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 333711680SCurtis.Dunham@arm.comsystem.realview.ide.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 333811680SCurtis.Dunham@arm.comsystem.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 333911680SCurtis.Dunham@arm.comsystem.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 334011680SCurtis.Dunham@arm.comsystem.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 334111680SCurtis.Dunham@arm.comsystem.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 334211680SCurtis.Dunham@arm.comsystem.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 334311239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 334411239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 334511239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 334611239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 334711680SCurtis.Dunham@arm.comsystem.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 334811680SCurtis.Dunham@arm.comsystem.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 334911680SCurtis.Dunham@arm.comsystem.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 335011680SCurtis.Dunham@arm.comsystem.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 335111680SCurtis.Dunham@arm.comsystem.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 335211680SCurtis.Dunham@arm.comsystem.realview.uart.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 335311680SCurtis.Dunham@arm.comsystem.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 335411680SCurtis.Dunham@arm.comsystem.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 335511680SCurtis.Dunham@arm.comsystem.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 335611680SCurtis.Dunham@arm.comsystem.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 335711680SCurtis.Dunham@arm.comsystem.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 335811680SCurtis.Dunham@arm.comsystem.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 335911680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.tot_requests 12127091 # Total number of requests made to the snoop filter. 336011680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 6563266 # Number of requests hitting in the snoop filter with a single holder of the requested data. 336111680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 2068389 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 336211680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 180040 # Total number of snoops made to the snoop filter. 336311680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 163507 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 336411680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 16533 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 336511680SCurtis.Dunham@arm.comsystem.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states 336611680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadReq 90774 # Transaction distribution 336711680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadResp 4717359 # Transaction distribution 336811680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WriteReq 38264 # Transaction distribution 336911680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WriteResp 38264 # Transaction distribution 337011680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 3747189 # Transaction distribution 337111680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::CleanEvict 2956256 # Transaction distribution 337211680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 703976 # Transaction distribution 337311680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 376914 # Transaction distribution 337411680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 1080890 # Transaction distribution 337511680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::SCUpgradeFailReq 83 # Transaction distribution 337611680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::UpgradeFailResp 83 # Transaction distribution 337711680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadExReq 286236 # Transaction distribution 337811680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadExResp 286236 # Transaction distribution 337911680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 4627139 # Transaction distribution 338011680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::InvalidateReq 855379 # Transaction distribution 338111680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::InvalidateResp 827617 # Transaction distribution 338211680SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9817286 # Packet count per connected master and slave (bytes) 338311680SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8000729 # Packet count per connected master and slave (bytes) 338411680SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count::total 17818015 # Packet count per connected master and slave (bytes) 338511680SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 243574806 # Cumulative packet size per connected master and slave (bytes) 338611680SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 194096942 # Cumulative packet size per connected master and slave (bytes) 338711680SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size::total 437671748 # Cumulative packet size per connected master and slave (bytes) 338811680SCurtis.Dunham@arm.comsystem.toL2Bus.snoops 2816292 # Total snoops (count) 338911680SCurtis.Dunham@arm.comsystem.toL2Bus.snoopTraffic 120259472 # Total snoop traffic (bytes) 339011680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::samples 8375094 # Request fanout histogram 339111680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::mean 0.374182 # Request fanout histogram 339211680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.487973 # Request fanout histogram 339310515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 339411680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::0 5257818 62.78% 62.78% # Request fanout histogram 339511680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::1 3100743 37.02% 99.80% # Request fanout histogram 339611680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::2 16533 0.20% 100.00% # Request fanout histogram 339710515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 339811138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 339910515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 340011680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::total 8375094 # Request fanout histogram 340111680SCurtis.Dunham@arm.comsystem.toL2Bus.reqLayer0.occupancy 9230074402 # Layer occupancy (ticks) 340210515SAli.Saidi@ARM.comsystem.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 340311680SCurtis.Dunham@arm.comsystem.toL2Bus.snoopLayer0.occupancy 2547405 # Layer occupancy (ticks) 340410515SAli.Saidi@ARM.comsystem.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 340511680SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer0.occupancy 4495965489 # Layer occupancy (ticks) 340610515SAli.Saidi@ARM.comsystem.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 340711680SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer1.occupancy 3978820805 # Layer occupancy (ticks) 340810515SAli.Saidi@ARM.comsystem.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 340910515SAli.Saidi@ARM.com 341010515SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 3411