stats.txt revision 11502
110515SAli.Saidi@ARM.com 210515SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 311502SCurtis.Dunham@arm.comsim_seconds 47.355903 # Number of seconds simulated 411502SCurtis.Dunham@arm.comsim_ticks 47355903328000 # Number of ticks simulated 511502SCurtis.Dunham@arm.comfinal_tick 47355903328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 711502SCurtis.Dunham@arm.comhost_inst_rate 234942 # Simulator instruction rate (inst/s) 811502SCurtis.Dunham@arm.comhost_op_rate 276333 # Simulator op (including micro ops) rate (op/s) 911502SCurtis.Dunham@arm.comhost_tick_rate 12593783431 # Simulator tick rate (ticks/s) 1011502SCurtis.Dunham@arm.comhost_mem_usage 765460 # Number of bytes of host memory used 1111502SCurtis.Dunham@arm.comhost_seconds 3760.26 # Real time elapsed on the host 1211502SCurtis.Dunham@arm.comsim_insts 883443630 # Number of instructions simulated 1311502SCurtis.Dunham@arm.comsim_ops 1039082168 # Number of ops (including micro ops) simulated 1410515SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 131584 # Number of bytes read from this memory 1711502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 123776 # Number of bytes read from this memory 1811502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.inst 7567040 # Number of bytes read from this memory 1911502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.data 14160840 # Number of bytes read from this memory 2011502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.l2cache.prefetcher 16409728 # Number of bytes read from this memory 2111502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 122112 # Number of bytes read from this memory 2211502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.itb.walker 100992 # Number of bytes read from this memory 2311502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.inst 3330560 # Number of bytes read from this memory 2411502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.data 9705936 # Number of bytes read from this memory 2511502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.l2cache.prefetcher 10452736 # Number of bytes read from this memory 2611502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::realview.ide 444224 # Number of bytes read from this memory 2711502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 62549528 # Number of bytes read from this memory 2811502SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 7567040 # Number of instructions bytes read from this memory 2911502SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 3330560 # Number of instructions bytes read from this memory 3011502SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 10897600 # Number of instructions bytes read from this memory 3111502SCurtis.Dunham@arm.comsystem.physmem.bytes_written::writebacks 75633728 # Number of bytes written to this memory 3210827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 3310636Snilay@cs.wisc.edusystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3411502SCurtis.Dunham@arm.comsystem.physmem.bytes_written::total 75654312 # Number of bytes written to this memory 3511502SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 2056 # Number of read requests responded to by this memory 3611502SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.itb.walker 1934 # Number of read requests responded to by this memory 3711502SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.inst 118235 # Number of read requests responded to by this memory 3811502SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.data 221276 # Number of read requests responded to by this memory 3911502SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.l2cache.prefetcher 256402 # Number of read requests responded to by this memory 4011502SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 1908 # Number of read requests responded to by this memory 4111502SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.itb.walker 1578 # Number of read requests responded to by this memory 4211502SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.inst 52040 # Number of read requests responded to by this memory 4311502SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.data 151668 # Number of read requests responded to by this memory 4411502SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.l2cache.prefetcher 163324 # Number of read requests responded to by this memory 4511502SCurtis.Dunham@arm.comsystem.physmem.num_reads::realview.ide 6941 # Number of read requests responded to by this memory 4611502SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 977362 # Number of read requests responded to by this memory 4711502SCurtis.Dunham@arm.comsystem.physmem.num_writes::writebacks 1181777 # Number of write requests responded to by this memory 4810827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 4910636Snilay@cs.wisc.edusystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 5011502SCurtis.Dunham@arm.comsystem.physmem.num_writes::total 1184351 # Number of write requests responded to by this memory 5111502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 2779 # Total read bandwidth from this memory (bytes/s) 5211502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.itb.walker 2614 # Total read bandwidth from this memory (bytes/s) 5311502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.inst 159791 # Total read bandwidth from this memory (bytes/s) 5411502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.data 299030 # Total read bandwidth from this memory (bytes/s) 5511502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.l2cache.prefetcher 346519 # Total read bandwidth from this memory (bytes/s) 5611502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 2579 # Total read bandwidth from this memory (bytes/s) 5711502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.itb.walker 2133 # Total read bandwidth from this memory (bytes/s) 5811502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.inst 70330 # Total read bandwidth from this memory (bytes/s) 5911502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.data 204957 # Total read bandwidth from this memory (bytes/s) 6011502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.l2cache.prefetcher 220727 # Total read bandwidth from this memory (bytes/s) 6111502SCurtis.Dunham@arm.comsystem.physmem.bw_read::realview.ide 9381 # Total read bandwidth from this memory (bytes/s) 6211502SCurtis.Dunham@arm.comsystem.physmem.bw_read::total 1320839 # Total read bandwidth from this memory (bytes/s) 6311502SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu0.inst 159791 # Instruction read bandwidth from this memory (bytes/s) 6411502SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu1.inst 70330 # Instruction read bandwidth from this memory (bytes/s) 6511502SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::total 230121 # Instruction read bandwidth from this memory (bytes/s) 6611502SCurtis.Dunham@arm.comsystem.physmem.bw_write::writebacks 1597134 # Write bandwidth from this memory (bytes/s) 6711502SCurtis.Dunham@arm.comsystem.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) 6810636Snilay@cs.wisc.edusystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 6911502SCurtis.Dunham@arm.comsystem.physmem.bw_write::total 1597569 # Write bandwidth from this memory (bytes/s) 7011502SCurtis.Dunham@arm.comsystem.physmem.bw_total::writebacks 1597134 # Total bandwidth to/from this memory (bytes/s) 7111502SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 2779 # Total bandwidth to/from this memory (bytes/s) 7211502SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.itb.walker 2614 # Total bandwidth to/from this memory (bytes/s) 7311502SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.inst 159791 # Total bandwidth to/from this memory (bytes/s) 7411502SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.data 299465 # Total bandwidth to/from this memory (bytes/s) 7511502SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.l2cache.prefetcher 346519 # Total bandwidth to/from this memory (bytes/s) 7611502SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 2579 # Total bandwidth to/from this memory (bytes/s) 7711502SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.itb.walker 2133 # Total bandwidth to/from this memory (bytes/s) 7811502SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.inst 70330 # Total bandwidth to/from this memory (bytes/s) 7911502SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.data 204957 # Total bandwidth to/from this memory (bytes/s) 8011502SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.l2cache.prefetcher 220727 # Total bandwidth to/from this memory (bytes/s) 8111502SCurtis.Dunham@arm.comsystem.physmem.bw_total::realview.ide 9381 # Total bandwidth to/from this memory (bytes/s) 8211502SCurtis.Dunham@arm.comsystem.physmem.bw_total::total 2918408 # Total bandwidth to/from this memory (bytes/s) 8311502SCurtis.Dunham@arm.comsystem.physmem.readReqs 977362 # Number of read requests accepted 8411502SCurtis.Dunham@arm.comsystem.physmem.writeReqs 1184351 # Number of write requests accepted 8511502SCurtis.Dunham@arm.comsystem.physmem.readBursts 977362 # Number of DRAM read bursts, including those serviced by the write queue 8611502SCurtis.Dunham@arm.comsystem.physmem.writeBursts 1184351 # Number of DRAM write bursts, including those merged in the write queue 8711502SCurtis.Dunham@arm.comsystem.physmem.bytesReadDRAM 62527296 # Total number of bytes read from DRAM 8811502SCurtis.Dunham@arm.comsystem.physmem.bytesReadWrQ 23872 # Total number of bytes read from write queue 8911502SCurtis.Dunham@arm.comsystem.physmem.bytesWritten 75653504 # Total number of bytes written to DRAM 9011502SCurtis.Dunham@arm.comsystem.physmem.bytesReadSys 62549528 # Total read bytes from the system interface side 9111502SCurtis.Dunham@arm.comsystem.physmem.bytesWrittenSys 75654312 # Total written bytes from the system interface side 9211502SCurtis.Dunham@arm.comsystem.physmem.servicedByWrQ 373 # Number of DRAM read bursts serviced by the write queue 9311502SCurtis.Dunham@arm.comsystem.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one 9411336Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 9511502SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::0 54912 # Per bank write bursts 9611502SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::1 56908 # Per bank write bursts 9711502SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::2 51582 # Per bank write bursts 9811502SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::3 63469 # Per bank write bursts 9911502SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::4 61411 # Per bank write bursts 10011502SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::5 61841 # Per bank write bursts 10111502SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::6 57272 # Per bank write bursts 10211502SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::7 62841 # Per bank write bursts 10311502SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::8 51834 # Per bank write bursts 10411502SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::9 112088 # Per bank write bursts 10511502SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::10 55237 # Per bank write bursts 10611502SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::11 58857 # Per bank write bursts 10711502SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::12 56745 # Per bank write bursts 10811502SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::13 58205 # Per bank write bursts 10911502SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::14 53859 # Per bank write bursts 11011502SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::15 59928 # Per bank write bursts 11111502SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::0 69820 # Per bank write bursts 11211502SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::1 73385 # Per bank write bursts 11311502SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::2 70846 # Per bank write bursts 11411502SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::3 76844 # Per bank write bursts 11511502SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::4 76655 # Per bank write bursts 11611502SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::5 78828 # Per bank write bursts 11711502SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::6 72793 # Per bank write bursts 11811502SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::7 76848 # Per bank write bursts 11911502SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::8 69899 # Per bank write bursts 12011502SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::9 74878 # Per bank write bursts 12111502SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::10 69893 # Per bank write bursts 12211502SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::11 73658 # Per bank write bursts 12311502SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::12 73258 # Per bank write bursts 12411502SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::13 76164 # Per bank write bursts 12511502SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::14 72361 # Per bank write bursts 12611502SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::15 75956 # Per bank write bursts 12710515SAli.Saidi@ARM.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 12811502SCurtis.Dunham@arm.comsystem.physmem.numWrRetry 28 # Number of times write queue was full causing retry 12911502SCurtis.Dunham@arm.comsystem.physmem.totGap 47355901307500 # Total gap between requests 13010515SAli.Saidi@ARM.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 13110515SAli.Saidi@ARM.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 13210515SAli.Saidi@ARM.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 13310827Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 25 # Read request sizes (log2) 13410515SAli.Saidi@ARM.comsystem.physmem.readPktSize::4 5 # Read request sizes (log2) 13510515SAli.Saidi@ARM.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 13611502SCurtis.Dunham@arm.comsystem.physmem.readPktSize::6 977332 # Read request sizes (log2) 13710515SAli.Saidi@ARM.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 13810515SAli.Saidi@ARM.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 13910515SAli.Saidi@ARM.comsystem.physmem.writePktSize::2 2 # Write request sizes (log2) 14010827Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 14110515SAli.Saidi@ARM.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 14210515SAli.Saidi@ARM.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 14311502SCurtis.Dunham@arm.comsystem.physmem.writePktSize::6 1181777 # Write request sizes (log2) 14411502SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::0 653624 # What read queue length does an incoming req see 14511502SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::1 118392 # What read queue length does an incoming req see 14611502SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::2 43298 # What read queue length does an incoming req see 14711502SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::3 33441 # What read queue length does an incoming req see 14811502SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::4 28719 # What read queue length does an incoming req see 14911502SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::5 26608 # What read queue length does an incoming req see 15011502SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::6 24389 # What read queue length does an incoming req see 15111502SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::7 21172 # What read queue length does an incoming req see 15211502SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::8 19081 # What read queue length does an incoming req see 15311502SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::9 3369 # What read queue length does an incoming req see 15411502SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::10 1474 # What read queue length does an incoming req see 15511502SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::11 993 # What read queue length does an incoming req see 15611502SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::12 791 # What read queue length does an incoming req see 15711502SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::13 539 # What read queue length does an incoming req see 15811502SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::14 292 # What read queue length does an incoming req see 15911502SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::15 238 # What read queue length does an incoming req see 16011502SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::16 217 # What read queue length does an incoming req see 16111502SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::17 181 # What read queue length does an incoming req see 16211502SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::18 95 # What read queue length does an incoming req see 16311502SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::19 68 # What read queue length does an incoming req see 16411502SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see 16511502SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see 16611353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 16711353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 16811353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 16910515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 17010515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 17110515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 17210515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 17310515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 17410515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 17510515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 17610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 17710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 17810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 17910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 18010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 18110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 18210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 18310515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 18410515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 18510515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 18610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 18710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 18810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 18910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 19010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 19111502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::15 26534 # What write queue length does an incoming req see 19211502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::16 34947 # What write queue length does an incoming req see 19311502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::17 50320 # What write queue length does an incoming req see 19411502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::18 57992 # What write queue length does an incoming req see 19511502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::19 63163 # What write queue length does an incoming req see 19611502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::20 65860 # What write queue length does an incoming req see 19711502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::21 68534 # What write queue length does an incoming req see 19811502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::22 70437 # What write queue length does an incoming req see 19911502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::23 72935 # What write queue length does an incoming req see 20011502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::24 73131 # What write queue length does an incoming req see 20111502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::25 75636 # What write queue length does an incoming req see 20211502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::26 78760 # What write queue length does an incoming req see 20311502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::27 75174 # What write queue length does an incoming req see 20411502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::28 74381 # What write queue length does an incoming req see 20511502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::29 78953 # What write queue length does an incoming req see 20611502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::30 69890 # What write queue length does an incoming req see 20711502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::31 64098 # What write queue length does an incoming req see 20811502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::32 61316 # What write queue length does an incoming req see 20911502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::33 3117 # What write queue length does an incoming req see 21011502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::34 2352 # What write queue length does an incoming req see 21111502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::35 1927 # What write queue length does an incoming req see 21211502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::36 1425 # What write queue length does an incoming req see 21311502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::37 1156 # What write queue length does an incoming req see 21411502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::38 977 # What write queue length does an incoming req see 21511502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::39 837 # What write queue length does an incoming req see 21611502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::40 699 # What write queue length does an incoming req see 21711502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::41 531 # What write queue length does an incoming req see 21811502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::42 599 # What write queue length does an incoming req see 21911502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::43 547 # What write queue length does an incoming req see 22011502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::44 500 # What write queue length does an incoming req see 22111502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::45 401 # What write queue length does an incoming req see 22211502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::46 502 # What write queue length does an incoming req see 22311502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::47 396 # What write queue length does an incoming req see 22411502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::48 357 # What write queue length does an incoming req see 22511502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::49 372 # What write queue length does an incoming req see 22611502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::50 385 # What write queue length does an incoming req see 22711502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::51 328 # What write queue length does an incoming req see 22811502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::52 331 # What write queue length does an incoming req see 22911502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::53 310 # What write queue length does an incoming req see 23011502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::54 300 # What write queue length does an incoming req see 23111502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::55 259 # What write queue length does an incoming req see 23211502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::56 273 # What write queue length does an incoming req see 23311502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::57 241 # What write queue length does an incoming req see 23411502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::58 225 # What write queue length does an incoming req see 23511502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::59 168 # What write queue length does an incoming req see 23611502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::60 172 # What write queue length does an incoming req see 23711502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::61 147 # What write queue length does an incoming req see 23811441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 94 # What write queue length does an incoming req see 23911502SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::63 102 # What write queue length does an incoming req see 24011502SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::samples 973522 # Bytes accessed per row activation 24111502SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::mean 141.938602 # Bytes accessed per row activation 24211502SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::gmean 96.538228 # Bytes accessed per row activation 24311502SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::stdev 191.263762 # Bytes accessed per row activation 24411502SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::0-127 662821 68.08% 68.08% # Bytes accessed per row activation 24511502SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::128-255 188353 19.35% 87.43% # Bytes accessed per row activation 24611502SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::256-383 43865 4.51% 91.94% # Bytes accessed per row activation 24711502SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::384-511 19742 2.03% 93.97% # Bytes accessed per row activation 24811502SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::512-639 14303 1.47% 95.44% # Bytes accessed per row activation 24911502SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::640-767 9443 0.97% 96.41% # Bytes accessed per row activation 25011502SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::768-895 6391 0.66% 97.06% # Bytes accessed per row activation 25111502SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::896-1023 5216 0.54% 97.60% # Bytes accessed per row activation 25211502SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::1024-1151 23388 2.40% 100.00% # Bytes accessed per row activation 25311502SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::total 973522 # Bytes accessed per row activation 25411502SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::samples 57494 # Reads before turning the bus around for writes 25511502SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::mean 16.992747 # Reads before turning the bus around for writes 25611502SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::stdev 164.605284 # Reads before turning the bus around for writes 25711502SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::0-1023 57491 99.99% 99.99% # Reads before turning the bus around for writes 25811502SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes 25911353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 26011353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes 26111502SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::total 57494 # Reads before turning the bus around for writes 26211502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::samples 57494 # Writes before turning the bus around for reads 26311502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::mean 20.560163 # Writes before turning the bus around for reads 26411502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::gmean 18.793170 # Writes before turning the bus around for reads 26511502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::stdev 13.728131 # Writes before turning the bus around for reads 26611502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::16-19 49230 85.63% 85.63% # Writes before turning the bus around for reads 26711502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::20-23 2347 4.08% 89.71% # Writes before turning the bus around for reads 26811502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::24-27 805 1.40% 91.11% # Writes before turning the bus around for reads 26911502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::28-31 601 1.05% 92.15% # Writes before turning the bus around for reads 27011502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::32-35 998 1.74% 93.89% # Writes before turning the bus around for reads 27111502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::36-39 486 0.85% 94.74% # Writes before turning the bus around for reads 27211502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::40-43 329 0.57% 95.31% # Writes before turning the bus around for reads 27311502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::44-47 263 0.46% 95.76% # Writes before turning the bus around for reads 27411502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::48-51 216 0.38% 96.14% # Writes before turning the bus around for reads 27511502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::52-55 180 0.31% 96.45% # Writes before turning the bus around for reads 27611502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::56-59 129 0.22% 96.68% # Writes before turning the bus around for reads 27711502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::60-63 154 0.27% 96.95% # Writes before turning the bus around for reads 27811502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::64-67 478 0.83% 97.78% # Writes before turning the bus around for reads 27911502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::68-71 131 0.23% 98.01% # Writes before turning the bus around for reads 28011502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::72-75 143 0.25% 98.25% # Writes before turning the bus around for reads 28111502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::76-79 111 0.19% 98.45% # Writes before turning the bus around for reads 28211502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::80-83 107 0.19% 98.63% # Writes before turning the bus around for reads 28311502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::84-87 71 0.12% 98.76% # Writes before turning the bus around for reads 28411502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::88-91 85 0.15% 98.90% # Writes before turning the bus around for reads 28511502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::92-95 71 0.12% 99.03% # Writes before turning the bus around for reads 28611502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::96-99 101 0.18% 99.20% # Writes before turning the bus around for reads 28711502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::100-103 73 0.13% 99.33% # Writes before turning the bus around for reads 28811502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::104-107 62 0.11% 99.44% # Writes before turning the bus around for reads 28911502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::108-111 52 0.09% 99.53% # Writes before turning the bus around for reads 29011502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::112-115 38 0.07% 99.59% # Writes before turning the bus around for reads 29111502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::116-119 47 0.08% 99.68% # Writes before turning the bus around for reads 29211502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::120-123 26 0.05% 99.72% # Writes before turning the bus around for reads 29311502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::124-127 37 0.06% 99.79% # Writes before turning the bus around for reads 29411502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::128-131 49 0.09% 99.87% # Writes before turning the bus around for reads 29511502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::132-135 22 0.04% 99.91% # Writes before turning the bus around for reads 29611502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::136-139 8 0.01% 99.92% # Writes before turning the bus around for reads 29711502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::140-143 12 0.02% 99.94% # Writes before turning the bus around for reads 29811502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::144-147 6 0.01% 99.95% # Writes before turning the bus around for reads 29911502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::148-151 5 0.01% 99.96% # Writes before turning the bus around for reads 30011502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::152-155 2 0.00% 99.97% # Writes before turning the bus around for reads 30111441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::160-163 6 0.01% 99.98% # Writes before turning the bus around for reads 30211502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::172-175 4 0.01% 99.98% # Writes before turning the bus around for reads 30311502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::176-179 1 0.00% 99.99% # Writes before turning the bus around for reads 30411502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::184-187 1 0.00% 99.99% # Writes before turning the bus around for reads 30511502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::188-191 2 0.00% 99.99% # Writes before turning the bus around for reads 30611502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::192-195 3 0.01% 100.00% # Writes before turning the bus around for reads 30711502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::220-223 1 0.00% 100.00% # Writes before turning the bus around for reads 30811502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::236-239 1 0.00% 100.00% # Writes before turning the bus around for reads 30911502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::total 57494 # Writes before turning the bus around for reads 31011502SCurtis.Dunham@arm.comsystem.physmem.totQLat 32578317305 # Total ticks spent queuing 31111502SCurtis.Dunham@arm.comsystem.physmem.totMemAccLat 50896861055 # Total ticks spent from burst creation until serviced by the DRAM 31211502SCurtis.Dunham@arm.comsystem.physmem.totBusLat 4884945000 # Total ticks spent in databus transfers 31311502SCurtis.Dunham@arm.comsystem.physmem.avgQLat 33345.63 # Average queueing delay per DRAM burst 31410515SAli.Saidi@ARM.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 31511502SCurtis.Dunham@arm.comsystem.physmem.avgMemAccLat 52095.63 # Average memory access latency per DRAM burst 31611502SCurtis.Dunham@arm.comsystem.physmem.avgRdBW 1.32 # Average DRAM read bandwidth in MiByte/s 31711502SCurtis.Dunham@arm.comsystem.physmem.avgWrBW 1.60 # Average achieved write bandwidth in MiByte/s 31811502SCurtis.Dunham@arm.comsystem.physmem.avgRdBWSys 1.32 # Average system read bandwidth in MiByte/s 31911502SCurtis.Dunham@arm.comsystem.physmem.avgWrBWSys 1.60 # Average system write bandwidth in MiByte/s 32010515SAli.Saidi@ARM.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 32111441Sandreas.hansson@arm.comsystem.physmem.busUtil 0.02 # Data bus utilization in percentage 32211353Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 32311441Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 32411502SCurtis.Dunham@arm.comsystem.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing 32511502SCurtis.Dunham@arm.comsystem.physmem.avgWrQLen 22.69 # Average write queue length when enqueuing 32611502SCurtis.Dunham@arm.comsystem.physmem.readRowHits 734277 # Number of row buffer hits during reads 32711502SCurtis.Dunham@arm.comsystem.physmem.writeRowHits 451275 # Number of row buffer hits during writes 32811502SCurtis.Dunham@arm.comsystem.physmem.readRowHitRate 75.16 # Row buffer hit rate for reads 32911502SCurtis.Dunham@arm.comsystem.physmem.writeRowHitRate 38.18 # Row buffer hit rate for writes 33011502SCurtis.Dunham@arm.comsystem.physmem.avgGap 21906655.19 # Average gap between requests 33111502SCurtis.Dunham@arm.comsystem.physmem.pageHitRate 54.91 # Row buffer hit rate, read and write combined 33211502SCurtis.Dunham@arm.comsystem.physmem_0.actEnergy 3752269920 # Energy for activate commands per rank (pJ) 33311502SCurtis.Dunham@arm.comsystem.physmem_0.preEnergy 2047369500 # Energy for precharge commands per rank (pJ) 33411502SCurtis.Dunham@arm.comsystem.physmem_0.readEnergy 3667786200 # Energy for read commands per rank (pJ) 33511502SCurtis.Dunham@arm.comsystem.physmem_0.writeEnergy 3862203120 # Energy for write commands per rank (pJ) 33611502SCurtis.Dunham@arm.comsystem.physmem_0.refreshEnergy 3093057342960 # Energy for refresh commands per rank (pJ) 33711502SCurtis.Dunham@arm.comsystem.physmem_0.actBackEnergy 1180767055500 # Energy for active background per rank (pJ) 33811502SCurtis.Dunham@arm.comsystem.physmem_0.preBackEnergy 27377781027000 # Energy for precharge background per rank (pJ) 33911502SCurtis.Dunham@arm.comsystem.physmem_0.totalEnergy 31664935054200 # Total energy per rank (pJ) 34011502SCurtis.Dunham@arm.comsystem.physmem_0.averagePower 668.658673 # Core power per rank (mW) 34111502SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::IDLE 45545161867023 # Time in different power states 34211502SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::REF 1581317660000 # Time in different power states 34310628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 34411502SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT 229423166977 # Time in different power states 34510628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 34611502SCurtis.Dunham@arm.comsystem.physmem_1.actEnergy 3607556400 # Energy for activate commands per rank (pJ) 34711502SCurtis.Dunham@arm.comsystem.physmem_1.preEnergy 1968408750 # Energy for precharge commands per rank (pJ) 34811502SCurtis.Dunham@arm.comsystem.physmem_1.readEnergy 3952673400 # Energy for read commands per rank (pJ) 34911502SCurtis.Dunham@arm.comsystem.physmem_1.writeEnergy 3797714160 # Energy for write commands per rank (pJ) 35011502SCurtis.Dunham@arm.comsystem.physmem_1.refreshEnergy 3093057342960 # Energy for refresh commands per rank (pJ) 35111502SCurtis.Dunham@arm.comsystem.physmem_1.actBackEnergy 1177905490200 # Energy for active background per rank (pJ) 35211502SCurtis.Dunham@arm.comsystem.physmem_1.preBackEnergy 27380291180250 # Energy for precharge background per rank (pJ) 35311502SCurtis.Dunham@arm.comsystem.physmem_1.totalEnergy 31664580366120 # Total energy per rank (pJ) 35411502SCurtis.Dunham@arm.comsystem.physmem_1.averagePower 668.651183 # Core power per rank (mW) 35511502SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::IDLE 45549316476567 # Time in different power states 35611502SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::REF 1581317660000 # Time in different power states 35710628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 35811502SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT 225268560933 # Time in different power states 35910628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 36010636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory 36110636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 36210636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory 36310636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 36410515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory 36510515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory 36610515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory 36710515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory 36810636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory 36910636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 37010636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory 37110636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 37210515SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory 37310636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) 37410636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 37510515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s) 37610636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 37710515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s) 37810515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) 37910515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s) 38010515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) 38110636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) 38210636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 38310515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s) 38410636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 38510515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) 38610585Sandreas.hansson@arm.comsystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 38710585Sandreas.hansson@arm.comsystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 38810585Sandreas.hansson@arm.comsystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 38911502SCurtis.Dunham@arm.comsystem.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 39011502SCurtis.Dunham@arm.comsystem.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 39111502SCurtis.Dunham@arm.comsystem.cf0.dma_write_txs 1670 # Number of DMA write transactions. 39211502SCurtis.Dunham@arm.comsystem.cpu0.branchPred.lookups 145452632 # Number of BP lookups 39311502SCurtis.Dunham@arm.comsystem.cpu0.branchPred.condPredicted 102233764 # Number of conditional branches predicted 39411502SCurtis.Dunham@arm.comsystem.cpu0.branchPred.condIncorrect 6537956 # Number of conditional branches incorrect 39511502SCurtis.Dunham@arm.comsystem.cpu0.branchPred.BTBLookups 107843095 # Number of BTB lookups 39611502SCurtis.Dunham@arm.comsystem.cpu0.branchPred.BTBHits 75495824 # Number of BTB hits 39710585Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 39811502SCurtis.Dunham@arm.comsystem.cpu0.branchPred.BTBHitPct 70.005246 # BTB Hit Percentage 39911502SCurtis.Dunham@arm.comsystem.cpu0.branchPred.usedRAS 17327542 # Number of times the RAS was used to get a target. 40011502SCurtis.Dunham@arm.comsystem.cpu0.branchPred.RASInCorrect 1162135 # Number of incorrect RAS predictions. 40111502SCurtis.Dunham@arm.comsystem.cpu0.branchPred.indirectLookups 3835403 # Number of indirect predictor lookups. 40211502SCurtis.Dunham@arm.comsystem.cpu0.branchPred.indirectHits 2658726 # Number of indirect target hits. 40311502SCurtis.Dunham@arm.comsystem.cpu0.branchPred.indirectMisses 1176677 # Number of indirect misses. 40411502SCurtis.Dunham@arm.comsystem.cpu0.branchPredindirectMispredicted 420775 # Number of mispredicted indirect branches. 40510515SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 40610628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 40710628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 40810628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 40910628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 41010628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 41110628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 41210628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 41310628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 41410585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 41510585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 41610585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 41710585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 41810585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 41910585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 42010585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 42110585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 42210585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 42310585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 42410585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 42510585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 42610585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 42710585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 42810585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 42910585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 43010585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 43110585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 43210585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 43310585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 43410585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 43511502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walks 298304 # Table walker walks requested 43611502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksLong 298304 # Table walker walks initiated with long descriptors 43711502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10716 # Level at which table walker walks with long descriptors terminate 43811502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level3 85635 # Level at which table walker walks with long descriptors terminate 43911502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 298304 # Table walker wait (enqueue to first request) latency 44011502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0 298304 100.00% 100.00% # Table walker wait (enqueue to first request) latency 44111502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 298304 # Table walker wait (enqueue to first request) latency 44211502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::samples 96351 # Table walker service (enqueue to completion) latency 44311502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::mean 22754.257870 # Table walker service (enqueue to completion) latency 44411502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::gmean 21300.315388 # Table walker service (enqueue to completion) latency 44511502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::stdev 14215.969550 # Table walker service (enqueue to completion) latency 44611502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::0-65535 95122 98.72% 98.72% # Table walker service (enqueue to completion) latency 44711502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::65536-131071 1073 1.11% 99.84% # Table walker service (enqueue to completion) latency 44811502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::131072-196607 26 0.03% 99.87% # Table walker service (enqueue to completion) latency 44911502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::196608-262143 56 0.06% 99.92% # Table walker service (enqueue to completion) latency 45011502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::262144-327679 56 0.06% 99.98% # Table walker service (enqueue to completion) latency 45111502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::327680-393215 10 0.01% 99.99% # Table walker service (enqueue to completion) latency 45211502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::393216-458751 6 0.01% 100.00% # Table walker service (enqueue to completion) latency 45311502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 45411502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 45511502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::total 96351 # Table walker service (enqueue to completion) latency 45611502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksPending::samples 734209704 # Table walker pending requests distribution 45711502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksPending::0 734209704 100.00% 100.00% # Table walker pending requests distribution 45811502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksPending::total 734209704 # Table walker pending requests distribution 45911502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 85635 88.88% 88.88% # Table walker page sizes translated 46011502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkPageSizes::2M 10716 11.12% 100.00% # Table walker page sizes translated 46111502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 96351 # Table walker page sizes translated 46211502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 298304 # Table walker requests started/completed, data/inst 46310628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 46411502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 298304 # Table walker requests started/completed, data/inst 46511502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 96351 # Table walker requests started/completed, data/inst 46610628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 46711502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 96351 # Table walker requests started/completed, data/inst 46811502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 394655 # Table walker requests started/completed, data/inst 46910585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_hits 0 # ITB inst hits 47010585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_misses 0 # ITB inst misses 47111502SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_hits 93899745 # DTB read hits 47211502SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_misses 250404 # DTB read misses 47311502SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_hits 82108561 # DTB write hits 47411502SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_misses 47900 # DTB write misses 47511441Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 47610585Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 47711502SCurtis.Dunham@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID 47811502SCurtis.Dunham@arm.comsystem.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 47911502SCurtis.Dunham@arm.comsystem.cpu0.dtb.flush_entries 39156 # Number of entries that have been flushed from TLB 48011502SCurtis.Dunham@arm.comsystem.cpu0.dtb.align_faults 2185 # Number of TLB faults due to alignment restrictions 48111502SCurtis.Dunham@arm.comsystem.cpu0.dtb.prefetch_faults 10307 # Number of TLB faults due to prefetch 48210585Sandreas.hansson@arm.comsystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 48311502SCurtis.Dunham@arm.comsystem.cpu0.dtb.perms_faults 10956 # Number of TLB faults due to permissions restrictions 48411502SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_accesses 94150149 # DTB read accesses 48511502SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_accesses 82156461 # DTB write accesses 48610585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 48711502SCurtis.Dunham@arm.comsystem.cpu0.dtb.hits 176008306 # DTB hits 48811502SCurtis.Dunham@arm.comsystem.cpu0.dtb.misses 298304 # DTB misses 48911502SCurtis.Dunham@arm.comsystem.cpu0.dtb.accesses 176306610 # DTB accesses 49010628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 49110628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 49210628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 49310628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 49410628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 49510628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 49610628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 49710628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 49810585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 49910585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 50010585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 50110585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 50210585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 50310585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 50410585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 50510585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 50610585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 50710585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 50810585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 50910585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 51010585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 51110585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 51210585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 51310585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 51410585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 51510585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 51610585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 51710585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 51810585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 51911502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walks 65048 # Table walker walks requested 52011502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksLong 65048 # Table walker walks initiated with long descriptors 52111502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level2 515 # Level at which table walker walks with long descriptors terminate 52211502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level3 52970 # Level at which table walker walks with long descriptors terminate 52311502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 65048 # Table walker wait (enqueue to first request) latency 52411502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkWaitTime::0 65048 100.00% 100.00% # Table walker wait (enqueue to first request) latency 52511502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 65048 # Table walker wait (enqueue to first request) latency 52611502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::samples 53485 # Table walker service (enqueue to completion) latency 52711502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::mean 25497.494625 # Table walker service (enqueue to completion) latency 52811502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::gmean 23453.450778 # Table walker service (enqueue to completion) latency 52911502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::stdev 17328.133028 # Table walker service (enqueue to completion) latency 53011502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::0-32767 49469 92.49% 92.49% # Table walker service (enqueue to completion) latency 53111502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::32768-65535 2789 5.21% 97.71% # Table walker service (enqueue to completion) latency 53211502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::65536-98303 9 0.02% 97.72% # Table walker service (enqueue to completion) latency 53311502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::98304-131071 1088 2.03% 99.76% # Table walker service (enqueue to completion) latency 53411502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::131072-163839 21 0.04% 99.80% # Table walker service (enqueue to completion) latency 53511502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::163840-196607 14 0.03% 99.82% # Table walker service (enqueue to completion) latency 53611502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::196608-229375 47 0.09% 99.91% # Table walker service (enqueue to completion) latency 53711502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::229376-262143 18 0.03% 99.94% # Table walker service (enqueue to completion) latency 53811502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.96% # Table walker service (enqueue to completion) latency 53911502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::294912-327679 8 0.01% 99.97% # Table walker service (enqueue to completion) latency 54011502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.98% # Table walker service (enqueue to completion) latency 54111502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::360448-393215 8 0.01% 99.99% # Table walker service (enqueue to completion) latency 54211502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 54311502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 54411502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::total 53485 # Table walker service (enqueue to completion) latency 54511502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksPending::samples 733487204 # Table walker pending requests distribution 54611502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksPending::0 733487204 100.00% 100.00% # Table walker pending requests distribution 54711502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksPending::total 733487204 # Table walker pending requests distribution 54811502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 52970 99.04% 99.04% # Table walker page sizes translated 54911502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkPageSizes::2M 515 0.96% 100.00% # Table walker page sizes translated 55011502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 53485 # Table walker page sizes translated 55110628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 55211502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 65048 # Table walker requests started/completed, data/inst 55311502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 65048 # Table walker requests started/completed, data/inst 55410628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 55511502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 53485 # Table walker requests started/completed, data/inst 55611502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 53485 # Table walker requests started/completed, data/inst 55711502SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 118533 # Table walker requests started/completed, data/inst 55811502SCurtis.Dunham@arm.comsystem.cpu0.itb.inst_hits 259203584 # ITB inst hits 55911502SCurtis.Dunham@arm.comsystem.cpu0.itb.inst_misses 65048 # ITB inst misses 56010585Sandreas.hansson@arm.comsystem.cpu0.itb.read_hits 0 # DTB read hits 56110585Sandreas.hansson@arm.comsystem.cpu0.itb.read_misses 0 # DTB read misses 56210585Sandreas.hansson@arm.comsystem.cpu0.itb.write_hits 0 # DTB write hits 56310585Sandreas.hansson@arm.comsystem.cpu0.itb.write_misses 0 # DTB write misses 56411441Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 56510585Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 56611502SCurtis.Dunham@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID 56711502SCurtis.Dunham@arm.comsystem.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 56811502SCurtis.Dunham@arm.comsystem.cpu0.itb.flush_entries 28333 # Number of entries that have been flushed from TLB 56910585Sandreas.hansson@arm.comsystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 57010585Sandreas.hansson@arm.comsystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 57110585Sandreas.hansson@arm.comsystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 57211502SCurtis.Dunham@arm.comsystem.cpu0.itb.perms_faults 171713 # Number of TLB faults due to permissions restrictions 57310585Sandreas.hansson@arm.comsystem.cpu0.itb.read_accesses 0 # DTB read accesses 57410585Sandreas.hansson@arm.comsystem.cpu0.itb.write_accesses 0 # DTB write accesses 57511502SCurtis.Dunham@arm.comsystem.cpu0.itb.inst_accesses 259268632 # ITB inst accesses 57611502SCurtis.Dunham@arm.comsystem.cpu0.itb.hits 259203584 # DTB hits 57711502SCurtis.Dunham@arm.comsystem.cpu0.itb.misses 65048 # DTB misses 57811502SCurtis.Dunham@arm.comsystem.cpu0.itb.accesses 259268632 # DTB accesses 57911502SCurtis.Dunham@arm.comsystem.cpu0.numCycles 1023758481 # number of cpu cycles simulated 58010585Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 58110585Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 58211502SCurtis.Dunham@arm.comsystem.cpu0.committedInsts 483101155 # Number of instructions committed 58311502SCurtis.Dunham@arm.comsystem.cpu0.committedOps 567019823 # Number of ops (including micro ops) committed 58411502SCurtis.Dunham@arm.comsystem.cpu0.discardedOps 47457065 # Number of ops (including micro ops) which were discarded before commit 58511502SCurtis.Dunham@arm.comsystem.cpu0.numFetchSuspends 4178 # Number of times Execute suspended instruction fetching 58611502SCurtis.Dunham@arm.comsystem.cpu0.quiesceCycles 93688785177 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 58711502SCurtis.Dunham@arm.comsystem.cpu0.cpi 2.119139 # CPI: cycles per instruction 58811502SCurtis.Dunham@arm.comsystem.cpu0.ipc 0.471890 # IPC: instructions per cycle 58911441Sandreas.hansson@arm.comsystem.cpu0.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction 59011502SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::IntAlu 393333975 69.37% 69.37% # Class of committed instruction 59111502SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::IntMult 1298911 0.23% 69.60% # Class of committed instruction 59211502SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::IntDiv 62117 0.01% 69.61% # Class of committed instruction 59311502SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::FloatAdd 0 0.00% 69.61% # Class of committed instruction 59411502SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::FloatCmp 0 0.00% 69.61% # Class of committed instruction 59511502SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::FloatCvt 0 0.00% 69.61% # Class of committed instruction 59611502SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::FloatMult 0 0.00% 69.61% # Class of committed instruction 59711502SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::FloatDiv 0 0.00% 69.61% # Class of committed instruction 59811502SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::FloatSqrt 0 0.00% 69.61% # Class of committed instruction 59911502SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdAdd 0 0.00% 69.61% # Class of committed instruction 60011502SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.61% # Class of committed instruction 60111502SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdAlu 0 0.00% 69.61% # Class of committed instruction 60211502SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdCmp 0 0.00% 69.61% # Class of committed instruction 60311502SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdCvt 0 0.00% 69.61% # Class of committed instruction 60411502SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdMisc 0 0.00% 69.61% # Class of committed instruction 60511502SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdMult 0 0.00% 69.61% # Class of committed instruction 60611502SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.61% # Class of committed instruction 60711502SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdShift 0 0.00% 69.61% # Class of committed instruction 60811502SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.61% # Class of committed instruction 60911502SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdSqrt 0 0.00% 69.61% # Class of committed instruction 61011502SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdFloatAdd 0 0.00% 69.61% # Class of committed instruction 61111502SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.61% # Class of committed instruction 61211502SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdFloatCmp 0 0.00% 69.61% # Class of committed instruction 61311502SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdFloatCvt 0 0.00% 69.61% # Class of committed instruction 61411502SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.61% # Class of committed instruction 61511502SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdFloatMisc 39633 0.01% 69.62% # Class of committed instruction 61611502SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.62% # Class of committed instruction 61711502SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.62% # Class of committed instruction 61811502SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.62% # Class of committed instruction 61911502SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::MemRead 90520623 15.96% 85.58% # Class of committed instruction 62011502SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::MemWrite 81764563 14.42% 100.00% # Class of committed instruction 62111441Sandreas.hansson@arm.comsystem.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 62211441Sandreas.hansson@arm.comsystem.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 62311502SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::total 567019823 # Class of committed instruction 62410585Sandreas.hansson@arm.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 62511502SCurtis.Dunham@arm.comsystem.cpu0.kern.inst.quiesce 13020 # number of quiesce instructions executed 62611502SCurtis.Dunham@arm.comsystem.cpu0.tickCycles 768761843 # Number of cycles that the object actually ticked 62711502SCurtis.Dunham@arm.comsystem.cpu0.idleCycles 254996638 # Total number of cycles that the object has spent stopped 62811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.replacements 6026209 # number of replacements 62911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.tagsinuse 478.505782 # Cycle average of tags in use 63011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.total_refs 166971566 # Total number of references to valid blocks. 63111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.sampled_refs 6026721 # Sample count of references to valid blocks. 63211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.avg_refs 27.705209 # Average number of references to valid blocks. 63311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.warmup_cycle 5039130000 # Cycle when the warmup percentage was hit. 63411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 478.505782 # Average occupied blocks per requestor 63511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.934582 # Average percentage of cache occupancy 63611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.934582 # Average percentage of cache occupancy 63711336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 63811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id 63911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id 64011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id 64111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 64211336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 64311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.tag_accesses 355154483 # Number of tag accesses 64411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.data_accesses 355154483 # Number of data accesses 64511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 85976696 # number of ReadReq hits 64611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_hits::total 85976696 # number of ReadReq hits 64711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 76051356 # number of WriteReq hits 64811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_hits::total 76051356 # number of WriteReq hits 64911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 300861 # number of SoftPFReq hits 65011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 300861 # number of SoftPFReq hits 65111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_hits::cpu0.data 281214 # number of WriteLineReq hits 65211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_hits::total 281214 # number of WriteLineReq hits 65311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1915398 # number of LoadLockedReq hits 65411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 1915398 # number of LoadLockedReq hits 65511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 1894723 # number of StoreCondReq hits 65611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 1894723 # number of StoreCondReq hits 65711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 162309266 # number of demand (read+write) hits 65811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_hits::total 162309266 # number of demand (read+write) hits 65911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 162610127 # number of overall hits 66011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_hits::total 162610127 # number of overall hits 66111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 3729679 # number of ReadReq misses 66211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_misses::total 3729679 # number of ReadReq misses 66311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 2481919 # number of WriteReq misses 66411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_misses::total 2481919 # number of WriteReq misses 66511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 681303 # number of SoftPFReq misses 66611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 681303 # number of SoftPFReq misses 66711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_misses::cpu0.data 827220 # number of WriteLineReq misses 66811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_misses::total 827220 # number of WriteLineReq misses 66911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 176003 # number of LoadLockedReq misses 67011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 176003 # number of LoadLockedReq misses 67111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 195484 # number of StoreCondReq misses 67211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 195484 # number of StoreCondReq misses 67311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 7038818 # number of demand (read+write) misses 67411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_misses::total 7038818 # number of demand (read+write) misses 67511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 7720121 # number of overall misses 67611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_misses::total 7720121 # number of overall misses 67711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 57503024000 # number of ReadReq miss cycles 67811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 57503024000 # number of ReadReq miss cycles 67911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 50806938500 # number of WriteReq miss cycles 68011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 50806938500 # number of WriteReq miss cycles 68111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 27591387500 # number of WriteLineReq miss cycles 68211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::total 27591387500 # number of WriteLineReq miss cycles 68311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2577956500 # number of LoadLockedReq miss cycles 68411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 2577956500 # number of LoadLockedReq miss cycles 68511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4885048500 # number of StoreCondReq miss cycles 68611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 4885048500 # number of StoreCondReq miss cycles 68711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3405000 # number of StoreCondFailReq miss cycles 68811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::total 3405000 # number of StoreCondFailReq miss cycles 68911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_latency::cpu0.data 135901350000 # number of demand (read+write) miss cycles 69011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_latency::total 135901350000 # number of demand (read+write) miss cycles 69111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_latency::cpu0.data 135901350000 # number of overall miss cycles 69211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_latency::total 135901350000 # number of overall miss cycles 69311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 89706375 # number of ReadReq accesses(hits+misses) 69411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 89706375 # number of ReadReq accesses(hits+misses) 69511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 78533275 # number of WriteReq accesses(hits+misses) 69611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 78533275 # number of WriteReq accesses(hits+misses) 69711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 982164 # number of SoftPFReq accesses(hits+misses) 69811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 982164 # number of SoftPFReq accesses(hits+misses) 69911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1108434 # number of WriteLineReq accesses(hits+misses) 70011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::total 1108434 # number of WriteLineReq accesses(hits+misses) 70111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2091401 # number of LoadLockedReq accesses(hits+misses) 70211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 2091401 # number of LoadLockedReq accesses(hits+misses) 70311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2090207 # number of StoreCondReq accesses(hits+misses) 70411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 2090207 # number of StoreCondReq accesses(hits+misses) 70511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 169348084 # number of demand (read+write) accesses 70611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_accesses::total 169348084 # number of demand (read+write) accesses 70711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 170330248 # number of overall (read+write) accesses 70811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_accesses::total 170330248 # number of overall (read+write) accesses 70911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041577 # miss rate for ReadReq accesses 71011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.041577 # miss rate for ReadReq accesses 71111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031603 # miss rate for WriteReq accesses 71211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.031603 # miss rate for WriteReq accesses 71311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.693675 # miss rate for SoftPFReq accesses 71411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.693675 # miss rate for SoftPFReq accesses 71511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.746296 # miss rate for WriteLineReq accesses 71611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::total 0.746296 # miss rate for WriteLineReq accesses 71711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.084156 # miss rate for LoadLockedReq accesses 71811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.084156 # miss rate for LoadLockedReq accesses 71911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.093524 # miss rate for StoreCondReq accesses 72011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.093524 # miss rate for StoreCondReq accesses 72111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.041564 # miss rate for demand accesses 72211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.041564 # miss rate for demand accesses 72311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.045324 # miss rate for overall accesses 72411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.045324 # miss rate for overall accesses 72511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15417.687152 # average ReadReq miss latency 72611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 15417.687152 # average ReadReq miss latency 72711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20470.828621 # average WriteReq miss latency 72811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 20470.828621 # average WriteReq miss latency 72911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 33354.352530 # average WriteLineReq miss latency 73011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::total 33354.352530 # average WriteLineReq miss latency 73111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14647.230445 # average LoadLockedReq miss latency 73211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14647.230445 # average LoadLockedReq miss latency 73311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24989.505535 # average StoreCondReq miss latency 73411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24989.505535 # average StoreCondReq miss latency 73510636Snilay@cs.wisc.edusystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 73610585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 73711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19307.410704 # average overall miss latency 73811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 19307.410704 # average overall miss latency 73911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17603.525903 # average overall miss latency 74011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 17603.525903 # average overall miss latency 74110585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 74210585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 74310585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 74410585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 74510585Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 74610585Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 74711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.writebacks::writebacks 6026220 # number of writebacks 74811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.writebacks::total 6026220 # number of writebacks 74911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 447326 # number of ReadReq MSHR hits 75011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 447326 # number of ReadReq MSHR hits 75111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1020420 # number of WriteReq MSHR hits 75211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 1020420 # number of WriteReq MSHR hits 75311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 73 # number of WriteLineReq MSHR hits 75411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_hits::total 73 # number of WriteLineReq MSHR hits 75511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44988 # number of LoadLockedReq MSHR hits 75611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 44988 # number of LoadLockedReq MSHR hits 75711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 67 # number of StoreCondReq MSHR hits 75811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_hits::total 67 # number of StoreCondReq MSHR hits 75911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_hits::cpu0.data 1467819 # number of demand (read+write) MSHR hits 76011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_hits::total 1467819 # number of demand (read+write) MSHR hits 76111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_hits::cpu0.data 1467819 # number of overall MSHR hits 76211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_hits::total 1467819 # number of overall MSHR hits 76311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3282353 # number of ReadReq MSHR misses 76411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 3282353 # number of ReadReq MSHR misses 76511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1461499 # number of WriteReq MSHR misses 76611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 1461499 # number of WriteReq MSHR misses 76711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 679841 # number of SoftPFReq MSHR misses 76811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::total 679841 # number of SoftPFReq MSHR misses 76911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 827147 # number of WriteLineReq MSHR misses 77011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::total 827147 # number of WriteLineReq MSHR misses 77111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 131015 # number of LoadLockedReq MSHR misses 77211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 131015 # number of LoadLockedReq MSHR misses 77311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 195417 # number of StoreCondReq MSHR misses 77411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 195417 # number of StoreCondReq MSHR misses 77511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.data 5570999 # number of demand (read+write) MSHR misses 77611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 5570999 # number of demand (read+write) MSHR misses 77711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.data 6250840 # number of overall MSHR misses 77811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 6250840 # number of overall MSHR misses 77911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31702 # number of ReadReq MSHR uncacheable 78011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::total 31702 # number of ReadReq MSHR uncacheable 78111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31225 # number of WriteReq MSHR uncacheable 78211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::total 31225 # number of WriteReq MSHR uncacheable 78311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 62927 # number of overall MSHR uncacheable misses 78411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::total 62927 # number of overall MSHR uncacheable misses 78511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 45702695000 # number of ReadReq MSHR miss cycles 78611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 45702695000 # number of ReadReq MSHR miss cycles 78711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 29281044500 # number of WriteReq MSHR miss cycles 78811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 29281044500 # number of WriteReq MSHR miss cycles 78911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14665959000 # number of SoftPFReq MSHR miss cycles 79011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14665959000 # number of SoftPFReq MSHR miss cycles 79111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 26759895500 # number of WriteLineReq MSHR miss cycles 79211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 26759895500 # number of WriteLineReq MSHR miss cycles 79311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1703041500 # number of LoadLockedReq MSHR miss cycles 79411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1703041500 # number of LoadLockedReq MSHR miss cycles 79511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4687173500 # number of StoreCondReq MSHR miss cycles 79611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4687173500 # number of StoreCondReq MSHR miss cycles 79711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3267500 # number of StoreCondFailReq MSHR miss cycles 79811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3267500 # number of StoreCondFailReq MSHR miss cycles 79911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 101743635000 # number of demand (read+write) MSHR miss cycles 80011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 101743635000 # number of demand (read+write) MSHR miss cycles 80111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 116409594000 # number of overall MSHR miss cycles 80211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 116409594000 # number of overall MSHR miss cycles 80311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6136923000 # number of ReadReq MSHR uncacheable cycles 80411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6136923000 # number of ReadReq MSHR uncacheable cycles 80511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6136923000 # number of overall MSHR uncacheable cycles 80611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 6136923000 # number of overall MSHR uncacheable cycles 80711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036590 # mshr miss rate for ReadReq accesses 80811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036590 # mshr miss rate for ReadReq accesses 80911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018610 # mshr miss rate for WriteReq accesses 81011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018610 # mshr miss rate for WriteReq accesses 81111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.692187 # mshr miss rate for SoftPFReq accesses 81211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.692187 # mshr miss rate for SoftPFReq accesses 81311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.746230 # mshr miss rate for WriteLineReq accesses 81411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.746230 # mshr miss rate for WriteLineReq accesses 81511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062645 # mshr miss rate for LoadLockedReq accesses 81611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062645 # mshr miss rate for LoadLockedReq accesses 81711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.093492 # mshr miss rate for StoreCondReq accesses 81811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.093492 # mshr miss rate for StoreCondReq accesses 81911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032897 # mshr miss rate for demand accesses 82011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.032897 # mshr miss rate for demand accesses 82111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036698 # mshr miss rate for overall accesses 82211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.036698 # mshr miss rate for overall accesses 82311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13923.759876 # average ReadReq mshr miss latency 82411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13923.759876 # average ReadReq mshr miss latency 82511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20034.939812 # average WriteReq mshr miss latency 82611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20034.939812 # average WriteReq mshr miss latency 82711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21572.630953 # average SoftPFReq mshr miss latency 82811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21572.630953 # average SoftPFReq mshr miss latency 82911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 32352.043228 # average WriteLineReq mshr miss latency 83011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 32352.043228 # average WriteLineReq mshr miss latency 83111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12998.828378 # average LoadLockedReq mshr miss latency 83211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12998.828378 # average LoadLockedReq mshr miss latency 83311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23985.495121 # average StoreCondReq mshr miss latency 83411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23985.495121 # average StoreCondReq mshr miss latency 83510636Snilay@cs.wisc.edusystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 83610585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 83711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18263.086208 # average overall mshr miss latency 83811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 18263.086208 # average overall mshr miss latency 83911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18623.032104 # average overall mshr miss latency 84011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 18623.032104 # average overall mshr miss latency 84111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193581.572141 # average ReadReq mshr uncacheable latency 84211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193581.572141 # average ReadReq mshr uncacheable latency 84311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97524.480748 # average overall mshr uncacheable latency 84411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 97524.480748 # average overall mshr uncacheable latency 84511502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.replacements 9817579 # number of replacements 84611502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.tagsinuse 511.932451 # Cycle average of tags in use 84711502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.total_refs 249208397 # Total number of references to valid blocks. 84811502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.sampled_refs 9818091 # Sample count of references to valid blocks. 84911502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.avg_refs 25.382572 # Average number of references to valid blocks. 85011502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.warmup_cycle 22021065000 # Cycle when the warmup percentage was hit. 85111502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.932451 # Average occupied blocks per requestor 85211502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999868 # Average percentage of cache occupancy 85311502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999868 # Average percentage of cache occupancy 85410585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 85511502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id 85611502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id 85711502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id 85810585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 85911502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.tag_accesses 527871096 # Number of tag accesses 86011502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.data_accesses 527871096 # Number of data accesses 86111502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 249208397 # number of ReadReq hits 86211502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_hits::total 249208397 # number of ReadReq hits 86311502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 249208397 # number of demand (read+write) hits 86411502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_hits::total 249208397 # number of demand (read+write) hits 86511502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 249208397 # number of overall hits 86611502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_hits::total 249208397 # number of overall hits 86711502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 9818101 # number of ReadReq misses 86811502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_misses::total 9818101 # number of ReadReq misses 86911502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 9818101 # number of demand (read+write) misses 87011502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_misses::total 9818101 # number of demand (read+write) misses 87111502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 9818101 # number of overall misses 87211502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_misses::total 9818101 # number of overall misses 87311502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 99002118000 # number of ReadReq miss cycles 87411502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 99002118000 # number of ReadReq miss cycles 87511502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 99002118000 # number of demand (read+write) miss cycles 87611502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_latency::total 99002118000 # number of demand (read+write) miss cycles 87711502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 99002118000 # number of overall miss cycles 87811502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_latency::total 99002118000 # number of overall miss cycles 87911502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 259026498 # number of ReadReq accesses(hits+misses) 88011502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_accesses::total 259026498 # number of ReadReq accesses(hits+misses) 88111502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 259026498 # number of demand (read+write) accesses 88211502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_accesses::total 259026498 # number of demand (read+write) accesses 88311502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 259026498 # number of overall (read+write) accesses 88411502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_accesses::total 259026498 # number of overall (read+write) accesses 88511502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.037904 # miss rate for ReadReq accesses 88611502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.037904 # miss rate for ReadReq accesses 88711502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.037904 # miss rate for demand accesses 88811502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.037904 # miss rate for demand accesses 88911502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.037904 # miss rate for overall accesses 89011502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.037904 # miss rate for overall accesses 89111502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10083.632059 # average ReadReq miss latency 89211502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 10083.632059 # average ReadReq miss latency 89311502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10083.632059 # average overall miss latency 89411502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 10083.632059 # average overall miss latency 89511502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10083.632059 # average overall miss latency 89611502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 10083.632059 # average overall miss latency 89710585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 89810585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 89910585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 90010585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 90110585Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 90210585Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 90311502SCurtis.Dunham@arm.comsystem.cpu0.icache.writebacks::writebacks 9817579 # number of writebacks 90411502SCurtis.Dunham@arm.comsystem.cpu0.icache.writebacks::total 9817579 # number of writebacks 90511502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9818101 # number of ReadReq MSHR misses 90611502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 9818101 # number of ReadReq MSHR misses 90711502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 9818101 # number of demand (read+write) MSHR misses 90811502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_misses::total 9818101 # number of demand (read+write) MSHR misses 90911502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 9818101 # number of overall MSHR misses 91011502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_misses::total 9818101 # number of overall MSHR misses 91111502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52299 # number of ReadReq MSHR uncacheable 91211502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::total 52299 # number of ReadReq MSHR uncacheable 91311502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52299 # number of overall MSHR uncacheable misses 91411502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::total 52299 # number of overall MSHR uncacheable misses 91511502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 94093068000 # number of ReadReq MSHR miss cycles 91611502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 94093068000 # number of ReadReq MSHR miss cycles 91711502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 94093068000 # number of demand (read+write) MSHR miss cycles 91811502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 94093068000 # number of demand (read+write) MSHR miss cycles 91911502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 94093068000 # number of overall MSHR miss cycles 92011502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 94093068000 # number of overall MSHR miss cycles 92111502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4837195500 # number of ReadReq MSHR uncacheable cycles 92211502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4837195500 # number of ReadReq MSHR uncacheable cycles 92311502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4837195500 # number of overall MSHR uncacheable cycles 92411502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::total 4837195500 # number of overall MSHR uncacheable cycles 92511502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.037904 # mshr miss rate for ReadReq accesses 92611502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.037904 # mshr miss rate for ReadReq accesses 92711502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.037904 # mshr miss rate for demand accesses 92811502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.037904 # mshr miss rate for demand accesses 92911502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.037904 # mshr miss rate for overall accesses 93011502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.037904 # mshr miss rate for overall accesses 93111502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9583.632110 # average ReadReq mshr miss latency 93211502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9583.632110 # average ReadReq mshr miss latency 93311502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9583.632110 # average overall mshr miss latency 93411502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 9583.632110 # average overall mshr miss latency 93511502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9583.632110 # average overall mshr miss latency 93611502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 9583.632110 # average overall mshr miss latency 93711502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92491.166179 # average ReadReq mshr uncacheable latency 93811502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92491.166179 # average ReadReq mshr uncacheable latency 93911502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92491.166179 # average overall mshr uncacheable latency 94011502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92491.166179 # average overall mshr uncacheable latency 94111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.prefetcher.num_hwpf_issued 8242304 # number of hwpf issued 94211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.prefetcher.pfIdentified 8243665 # number of prefetch candidates identified 94311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.prefetcher.pfBufferHit 1198 # number of redundant prefetches already in prefetch queue 94410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 94510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 94611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.prefetcher.pfSpanPage 1073071 # number of prefetches not generated due to page crossing 94711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.replacements 2829183 # number of replacements 94811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.tagsinuse 16163.343057 # Cycle average of tags in use 94911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.total_refs 24764914 # Total number of references to valid blocks. 95011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.sampled_refs 2845343 # Sample count of references to valid blocks. 95111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.avg_refs 8.703666 # Average number of references to valid blocks. 95211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 5659477500 # Cycle when the warmup percentage was hit. 95311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 15257.249232 # Average occupied blocks per requestor 95411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 57.561913 # Average occupied blocks per requestor 95511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 60.708141 # Average occupied blocks per requestor 95611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 787.823770 # Average occupied blocks per requestor 95711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.931229 # Average percentage of cache occupancy 95811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003513 # Average percentage of cache occupancy 95911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003705 # Average percentage of cache occupancy 96011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.048085 # Average percentage of cache occupancy 96111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.986532 # Average percentage of cache occupancy 96211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1022 1356 # Occupied blocks per task id 96311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 56 # Occupied blocks per task id 96411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 14748 # Occupied blocks per task id 96511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::1 16 # Occupied blocks per task id 96611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::2 123 # Occupied blocks per task id 96711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::3 574 # Occupied blocks per task id 96811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::4 643 # Occupied blocks per task id 96911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 23 # Occupied blocks per task id 97011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 22 # Occupied blocks per task id 97111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id 97211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id 97311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1176 # Occupied blocks per task id 97411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2616 # Occupied blocks per task id 97511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5298 # Occupied blocks per task id 97611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 5548 # Occupied blocks per task id 97711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1022 0.082764 # Percentage of cache occupancy per task id 97811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003418 # Percentage of cache occupancy per task id 97911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.900146 # Percentage of cache occupancy per task id 98011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.tag_accesses 533961635 # Number of tag accesses 98111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.data_accesses 533961635 # Number of data accesses 98211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 561309 # number of ReadReq hits 98311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 167224 # number of ReadReq hits 98411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 728533 # number of ReadReq hits 98511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::writebacks 3942058 # number of WritebackDirty hits 98611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::total 3942058 # number of WritebackDirty hits 98711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_hits::writebacks 11898812 # number of WritebackClean hits 98811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_hits::total 11898812 # number of WritebackClean hits 98911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::cpu0.data 611 # number of UpgradeReq hits 99011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::total 611 # number of UpgradeReq hits 99111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 933174 # number of ReadExReq hits 99211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 933174 # number of ReadExReq hits 99311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 9093916 # number of ReadCleanReq hits 99411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 9093916 # number of ReadCleanReq hits 99511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3073539 # number of ReadSharedReq hits 99611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 3073539 # number of ReadSharedReq hits 99711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::cpu0.data 216814 # number of InvalidateReq hits 99811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::total 216814 # number of InvalidateReq hits 99911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 561309 # number of demand (read+write) hits 100011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 167224 # number of demand (read+write) hits 100111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 9093916 # number of demand (read+write) hits 100211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 4006713 # number of demand (read+write) hits 100311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::total 13829162 # number of demand (read+write) hits 100411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 561309 # number of overall hits 100511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 167224 # number of overall hits 100611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 9093916 # number of overall hits 100711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 4006713 # number of overall hits 100811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::total 13829162 # number of overall hits 100911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12299 # number of ReadReq misses 101011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8468 # number of ReadReq misses 101111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 20767 # number of ReadReq misses 101211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 256901 # number of UpgradeReq misses 101311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 256901 # number of UpgradeReq misses 101411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 195411 # number of SCUpgradeReq misses 101511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 195411 # number of SCUpgradeReq misses 101611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 6 # number of SCUpgradeFailReq misses 101711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses 101811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 279617 # number of ReadExReq misses 101911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 279617 # number of ReadExReq misses 102011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 724184 # number of ReadCleanReq misses 102111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 724184 # number of ReadCleanReq misses 102211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1019232 # number of ReadSharedReq misses 102311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 1019232 # number of ReadSharedReq misses 102411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::cpu0.data 608335 # number of InvalidateReq misses 102511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::total 608335 # number of InvalidateReq misses 102611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12299 # number of demand (read+write) misses 102711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 8468 # number of demand (read+write) misses 102811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 724184 # number of demand (read+write) misses 102911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 1298849 # number of demand (read+write) misses 103011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::total 2043800 # number of demand (read+write) misses 103111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12299 # number of overall misses 103211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 8468 # number of overall misses 103311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 724184 # number of overall misses 103411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 1298849 # number of overall misses 103511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::total 2043800 # number of overall misses 103611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 444586500 # number of ReadReq miss cycles 103711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 341709500 # number of ReadReq miss cycles 103811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::total 786296000 # number of ReadReq miss cycles 103911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2032659000 # number of UpgradeReq miss cycles 104011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::total 2032659000 # number of UpgradeReq miss cycles 104111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1558169000 # number of SCUpgradeReq miss cycles 104211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1558169000 # number of SCUpgradeReq miss cycles 104311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 3166000 # number of SCUpgradeFailReq miss cycles 104411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 3166000 # number of SCUpgradeFailReq miss cycles 104511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 14018472997 # number of ReadExReq miss cycles 104611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::total 14018472997 # number of ReadExReq miss cycles 104711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 24426242000 # number of ReadCleanReq miss cycles 104811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::total 24426242000 # number of ReadCleanReq miss cycles 104911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 35646536993 # number of ReadSharedReq miss cycles 105011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::total 35646536993 # number of ReadSharedReq miss cycles 105111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 333062000 # number of InvalidateReq miss cycles 105211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::total 333062000 # number of InvalidateReq miss cycles 105311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 444586500 # number of demand (read+write) miss cycles 105411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 341709500 # number of demand (read+write) miss cycles 105511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.inst 24426242000 # number of demand (read+write) miss cycles 105611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.data 49665009990 # number of demand (read+write) miss cycles 105711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_latency::total 74877547990 # number of demand (read+write) miss cycles 105811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 444586500 # number of overall miss cycles 105911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 341709500 # number of overall miss cycles 106011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.inst 24426242000 # number of overall miss cycles 106111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.data 49665009990 # number of overall miss cycles 106211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_latency::total 74877547990 # number of overall miss cycles 106311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 573608 # number of ReadReq accesses(hits+misses) 106411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 175692 # number of ReadReq accesses(hits+misses) 106511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 749300 # number of ReadReq accesses(hits+misses) 106611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::writebacks 3942058 # number of WritebackDirty accesses(hits+misses) 106711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::total 3942058 # number of WritebackDirty accesses(hits+misses) 106811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::writebacks 11898812 # number of WritebackClean accesses(hits+misses) 106911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::total 11898812 # number of WritebackClean accesses(hits+misses) 107011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 257512 # number of UpgradeReq accesses(hits+misses) 107111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 257512 # number of UpgradeReq accesses(hits+misses) 107211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 195411 # number of SCUpgradeReq accesses(hits+misses) 107311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 195411 # number of SCUpgradeReq accesses(hits+misses) 107411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 6 # number of SCUpgradeFailReq accesses(hits+misses) 107511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) 107611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1212791 # number of ReadExReq accesses(hits+misses) 107711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1212791 # number of ReadExReq accesses(hits+misses) 107811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9818100 # number of ReadCleanReq accesses(hits+misses) 107911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 9818100 # number of ReadCleanReq accesses(hits+misses) 108011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4092771 # number of ReadSharedReq accesses(hits+misses) 108111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 4092771 # number of ReadSharedReq accesses(hits+misses) 108211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 825149 # number of InvalidateReq accesses(hits+misses) 108311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::total 825149 # number of InvalidateReq accesses(hits+misses) 108411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 573608 # number of demand (read+write) accesses 108511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 175692 # number of demand (read+write) accesses 108611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 9818100 # number of demand (read+write) accesses 108711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 5305562 # number of demand (read+write) accesses 108811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::total 15872962 # number of demand (read+write) accesses 108911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 573608 # number of overall (read+write) accesses 109011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 175692 # number of overall (read+write) accesses 109111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 9818100 # number of overall (read+write) accesses 109211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 5305562 # number of overall (read+write) accesses 109311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::total 15872962 # number of overall (read+write) accesses 109411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.021441 # miss rate for ReadReq accesses 109511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.048198 # miss rate for ReadReq accesses 109611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.027715 # miss rate for ReadReq accesses 109711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.997627 # miss rate for UpgradeReq accesses 109811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 0.997627 # miss rate for UpgradeReq accesses 109911441Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 110011441Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 110110636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 110210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 110311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.230557 # miss rate for ReadExReq accesses 110411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.230557 # miss rate for ReadExReq accesses 110511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.073760 # miss rate for ReadCleanReq accesses 110611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.073760 # miss rate for ReadCleanReq accesses 110711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.249032 # miss rate for ReadSharedReq accesses 110811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.249032 # miss rate for ReadSharedReq accesses 110911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.737243 # miss rate for InvalidateReq accesses 111011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::total 0.737243 # miss rate for InvalidateReq accesses 111111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.021441 # miss rate for demand accesses 111211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.048198 # miss rate for demand accesses 111311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.073760 # miss rate for demand accesses 111411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.244809 # miss rate for demand accesses 111511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.128760 # miss rate for demand accesses 111611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.021441 # miss rate for overall accesses 111711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.048198 # miss rate for overall accesses 111811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.073760 # miss rate for overall accesses 111911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.244809 # miss rate for overall accesses 112011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.128760 # miss rate for overall accesses 112111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 36148.182779 # average ReadReq miss latency 112211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 40353.034955 # average ReadReq miss latency 112311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::total 37862.763038 # average ReadReq miss latency 112411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 7912.226889 # average UpgradeReq miss latency 112511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 7912.226889 # average UpgradeReq miss latency 112611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 7973.803931 # average SCUpgradeReq miss latency 112711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 7973.803931 # average SCUpgradeReq miss latency 112811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 527666.666667 # average SCUpgradeFailReq miss latency 112911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 527666.666667 # average SCUpgradeFailReq miss latency 113011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50134.551894 # average ReadExReq miss latency 113111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50134.551894 # average ReadExReq miss latency 113211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 33729.331220 # average ReadCleanReq miss latency 113311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 33729.331220 # average ReadCleanReq miss latency 113411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34973.918591 # average ReadSharedReq miss latency 113511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34973.918591 # average ReadSharedReq miss latency 113611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 547.497678 # average InvalidateReq miss latency 113711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 547.497678 # average InvalidateReq miss latency 113811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 36148.182779 # average overall miss latency 113911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 40353.034955 # average overall miss latency 114011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 33729.331220 # average overall miss latency 114111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38237.708918 # average overall miss latency 114211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::total 36636.436046 # average overall miss latency 114311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 36148.182779 # average overall miss latency 114411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 40353.034955 # average overall miss latency 114511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 33729.331220 # average overall miss latency 114611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38237.708918 # average overall miss latency 114711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::total 36636.436046 # average overall miss latency 114811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.blocked_cycles::no_mshrs 90 # number of cycles access was blocked 114910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 115011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked 115110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 115211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs 90 # average number of cycles each access was blocked 115310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 115411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.unused_prefetches 48128 # number of HardPF blocks evicted w/o reference 115511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.writebacks::writebacks 1646117 # number of writebacks 115611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.writebacks::total 1646117 # number of writebacks 115711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 3 # number of ReadReq MSHR hits 115811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits 115911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 9808 # number of ReadExReq MSHR hits 116011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::total 9808 # number of ReadExReq MSHR hits 116111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 9 # number of ReadCleanReq MSHR hits 116211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits 116311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 898 # number of ReadSharedReq MSHR hits 116411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::total 898 # number of ReadSharedReq MSHR hits 116511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 3 # number of InvalidateReq MSHR hits 116611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits 116711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 3 # number of demand (read+write) MSHR hits 116811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.inst 9 # number of demand (read+write) MSHR hits 116911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.data 10706 # number of demand (read+write) MSHR hits 117011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_hits::total 10718 # number of demand (read+write) MSHR hits 117111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 3 # number of overall MSHR hits 117211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.inst 9 # number of overall MSHR hits 117311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.data 10706 # number of overall MSHR hits 117411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_hits::total 10718 # number of overall MSHR hits 117511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 12299 # number of ReadReq MSHR misses 117611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8465 # number of ReadReq MSHR misses 117711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::total 20764 # number of ReadReq MSHR misses 117811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 828377 # number of HardPFReq MSHR misses 117911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::total 828377 # number of HardPFReq MSHR misses 118011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 256901 # number of UpgradeReq MSHR misses 118111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::total 256901 # number of UpgradeReq MSHR misses 118211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 195411 # number of SCUpgradeReq MSHR misses 118311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 195411 # number of SCUpgradeReq MSHR misses 118411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 6 # number of SCUpgradeFailReq MSHR misses 118511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses 118611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 269809 # number of ReadExReq MSHR misses 118711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::total 269809 # number of ReadExReq MSHR misses 118811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 724175 # number of ReadCleanReq MSHR misses 118911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::total 724175 # number of ReadCleanReq MSHR misses 119011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1018334 # number of ReadSharedReq MSHR misses 119111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1018334 # number of ReadSharedReq MSHR misses 119211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 608332 # number of InvalidateReq MSHR misses 119311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::total 608332 # number of InvalidateReq MSHR misses 119411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 12299 # number of demand (read+write) MSHR misses 119511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8465 # number of demand (read+write) MSHR misses 119611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.inst 724175 # number of demand (read+write) MSHR misses 119711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.data 1288143 # number of demand (read+write) MSHR misses 119811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_misses::total 2033082 # number of demand (read+write) MSHR misses 119911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 12299 # number of overall MSHR misses 120011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8465 # number of overall MSHR misses 120111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.inst 724175 # number of overall MSHR misses 120211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.data 1288143 # number of overall MSHR misses 120311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 828377 # number of overall MSHR misses 120411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_misses::total 2861459 # number of overall MSHR misses 120511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52299 # number of ReadReq MSHR uncacheable 120611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31702 # number of ReadReq MSHR uncacheable 120711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::total 84001 # number of ReadReq MSHR uncacheable 120811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 31225 # number of WriteReq MSHR uncacheable 120911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::total 31225 # number of WriteReq MSHR uncacheable 121011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52299 # number of overall MSHR uncacheable misses 121111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 62927 # number of overall MSHR uncacheable misses 121211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::total 115226 # number of overall MSHR uncacheable misses 121311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 370792500 # number of ReadReq MSHR miss cycles 121411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 290829500 # number of ReadReq MSHR miss cycles 121511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::total 661622000 # number of ReadReq MSHR miss cycles 121611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 38426708957 # number of HardPFReq MSHR miss cycles 121711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 38426708957 # number of HardPFReq MSHR miss cycles 121811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 5314605493 # number of UpgradeReq MSHR miss cycles 121911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 5314605493 # number of UpgradeReq MSHR miss cycles 122011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3216326998 # number of SCUpgradeReq MSHR miss cycles 122111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3216326998 # number of SCUpgradeReq MSHR miss cycles 122211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2770000 # number of SCUpgradeFailReq MSHR miss cycles 122311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2770000 # number of SCUpgradeFailReq MSHR miss cycles 122411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11196985497 # number of ReadExReq MSHR miss cycles 122511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11196985497 # number of ReadExReq MSHR miss cycles 122611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 20080949000 # number of ReadCleanReq MSHR miss cycles 122711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 20080949000 # number of ReadCleanReq MSHR miss cycles 122811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 29451947493 # number of ReadSharedReq MSHR miss cycles 122911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 29451947493 # number of ReadSharedReq MSHR miss cycles 123011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 20309675000 # number of InvalidateReq MSHR miss cycles 123111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 20309675000 # number of InvalidateReq MSHR miss cycles 123211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 370792500 # number of demand (read+write) MSHR miss cycles 123311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 290829500 # number of demand (read+write) MSHR miss cycles 123411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 20080949000 # number of demand (read+write) MSHR miss cycles 123511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 40648932990 # number of demand (read+write) MSHR miss cycles 123611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::total 61391503990 # number of demand (read+write) MSHR miss cycles 123711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 370792500 # number of overall MSHR miss cycles 123811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 290829500 # number of overall MSHR miss cycles 123911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 20080949000 # number of overall MSHR miss cycles 124011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 40648932990 # number of overall MSHR miss cycles 124111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 38426708957 # number of overall MSHR miss cycles 124211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::total 99818212947 # number of overall MSHR miss cycles 124311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4418803500 # number of ReadReq MSHR uncacheable cycles 124411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5883144500 # number of ReadReq MSHR uncacheable cycles 124511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10301948000 # number of ReadReq MSHR uncacheable cycles 124611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4418803500 # number of overall MSHR uncacheable cycles 124711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5883144500 # number of overall MSHR uncacheable cycles 124811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10301948000 # number of overall MSHR uncacheable cycles 124911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021441 # mshr miss rate for ReadReq accesses 125011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.048181 # mshr miss rate for ReadReq accesses 125111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.027711 # mshr miss rate for ReadReq accesses 125210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 125310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 125411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.997627 # mshr miss rate for UpgradeReq accesses 125511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.997627 # mshr miss rate for UpgradeReq accesses 125611441Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 125711441Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 125810636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 125910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 126011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.222469 # mshr miss rate for ReadExReq accesses 126111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.222469 # mshr miss rate for ReadExReq accesses 126211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.073759 # mshr miss rate for ReadCleanReq accesses 126311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.073759 # mshr miss rate for ReadCleanReq accesses 126411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.248813 # mshr miss rate for ReadSharedReq accesses 126511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248813 # mshr miss rate for ReadSharedReq accesses 126611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.737239 # mshr miss rate for InvalidateReq accesses 126711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.737239 # mshr miss rate for InvalidateReq accesses 126811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021441 # mshr miss rate for demand accesses 126911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.048181 # mshr miss rate for demand accesses 127011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.073759 # mshr miss rate for demand accesses 127111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.242791 # mshr miss rate for demand accesses 127211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::total 0.128085 # mshr miss rate for demand accesses 127311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021441 # mshr miss rate for overall accesses 127411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.048181 # mshr miss rate for overall accesses 127511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.073759 # mshr miss rate for overall accesses 127611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.242791 # mshr miss rate for overall accesses 127710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 127811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::total 0.180273 # mshr miss rate for overall accesses 127911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30148.182779 # average ReadReq mshr miss latency 128011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34356.704076 # average ReadReq mshr miss latency 128111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 31863.899056 # average ReadReq mshr miss latency 128211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46387.947706 # average HardPFReq mshr miss latency 128311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46387.947706 # average HardPFReq mshr miss latency 128411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20687.367869 # average UpgradeReq mshr miss latency 128511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20687.367869 # average UpgradeReq mshr miss latency 128611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16459.293479 # average SCUpgradeReq mshr miss latency 128711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16459.293479 # average SCUpgradeReq mshr miss latency 128811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 461666.666667 # average SCUpgradeFailReq mshr miss latency 128911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 461666.666667 # average SCUpgradeFailReq mshr miss latency 129011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41499.673832 # average ReadExReq mshr miss latency 129111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41499.673832 # average ReadExReq mshr miss latency 129211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 27729.414851 # average ReadCleanReq mshr miss latency 129311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27729.414851 # average ReadCleanReq mshr miss latency 129411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28921.697098 # average ReadSharedReq mshr miss latency 129511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28921.697098 # average ReadSharedReq mshr miss latency 129611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 33385.840298 # average InvalidateReq mshr miss latency 129711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 33385.840298 # average InvalidateReq mshr miss latency 129811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30148.182779 # average overall mshr miss latency 129911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34356.704076 # average overall mshr miss latency 130011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 27729.414851 # average overall mshr miss latency 130111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31556.227057 # average overall mshr miss latency 130211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30196.275404 # average overall mshr miss latency 130311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30148.182779 # average overall mshr miss latency 130411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34356.704076 # average overall mshr miss latency 130511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 27729.414851 # average overall mshr miss latency 130611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31556.227057 # average overall mshr miss latency 130711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46387.947706 # average overall mshr miss latency 130811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34883.677504 # average overall mshr miss latency 130911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84491.166179 # average ReadReq mshr uncacheable latency 131011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185576.446281 # average ReadReq mshr uncacheable latency 131111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 122640.778086 # average ReadReq mshr uncacheable latency 131211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84491.166179 # average overall mshr uncacheable latency 131311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 93491.577542 # average overall mshr uncacheable latency 131411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 89406.453405 # average overall mshr uncacheable latency 131511502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_requests 32574371 # Total number of requests made to the snoop filter. 131611502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_requests 16625689 # Number of requests hitting in the snoop filter with a single holder of the requested data. 131711502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2928 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 131811502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_snoops 2229520 # Total number of snoops made to the snoop filter. 131911502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2229086 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 132011502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 434 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 132111502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 913111 # Transaction distribution 132211502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 14927613 # Transaction distribution 132311502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution 132411502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 31225 # Transaction distribution 132511502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 31225 # Transaction distribution 132611502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackDirty 5591471 # Transaction distribution 132711502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackClean 11901739 # Transaction distribution 132811502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::CleanEvict 2979875 # Transaction distribution 132911502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::HardPFReq 1058098 # Transaction distribution 133011502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution 133111502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 473129 # Transaction distribution 133211502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 352230 # Transaction distribution 133311502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 525861 # Transaction distribution 133411502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 51 # Transaction distribution 133511502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution 133611502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1247048 # Transaction distribution 133711502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1223348 # Transaction distribution 133811502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 9818101 # Transaction distribution 133911502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 5127973 # Transaction distribution 134011502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateReq 875849 # Transaction distribution 134111502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateResp 825149 # Transaction distribution 134211502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 29558377 # Packet count per connected master and slave (bytes) 134311502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19506589 # Packet count per connected master and slave (bytes) 134411502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 370132 # Packet count per connected master and slave (bytes) 134511502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1208276 # Packet count per connected master and slave (bytes) 134611502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count::total 50643374 # Packet count per connected master and slave (bytes) 134711502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1260030528 # Cumulative packet size per connected master and slave (bytes) 134811502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 732739948 # Cumulative packet size per connected master and slave (bytes) 134911502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1405536 # Cumulative packet size per connected master and slave (bytes) 135011502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4588864 # Cumulative packet size per connected master and slave (bytes) 135111502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size::total 1998764876 # Cumulative packet size per connected master and slave (bytes) 135211502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoops 7447074 # Total snoops (count) 135311502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 24526103 # Request fanout histogram 135411502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 0.104449 # Request fanout histogram 135511502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.305900 # Request fanout histogram 135610585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 135711502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 21964812 89.56% 89.56% # Request fanout histogram 135811502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 2560857 10.44% 100.00% # Request fanout histogram 135911502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 434 0.00% 100.00% # Request fanout histogram 136010585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 136111138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 136210827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 136311502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 24526103 # Request fanout histogram 136411502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.reqLayer0.occupancy 32454354981 # Layer occupancy (ticks) 136511201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 136611502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoopLayer0.occupancy 208052919 # Layer occupancy (ticks) 136710585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 136811502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.respLayer0.occupancy 14809077024 # Layer occupancy (ticks) 136910585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 137011502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.respLayer1.occupancy 8648892723 # Layer occupancy (ticks) 137110585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 137211502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.respLayer2.occupancy 194486906 # Layer occupancy (ticks) 137310585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 137411502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.respLayer3.occupancy 634782270 # Layer occupancy (ticks) 137510585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 137611502SCurtis.Dunham@arm.comsystem.cpu1.branchPred.lookups 123875539 # Number of BP lookups 137711502SCurtis.Dunham@arm.comsystem.cpu1.branchPred.condPredicted 88073767 # Number of conditional branches predicted 137811502SCurtis.Dunham@arm.comsystem.cpu1.branchPred.condIncorrect 5721607 # Number of conditional branches incorrect 137911502SCurtis.Dunham@arm.comsystem.cpu1.branchPred.BTBLookups 93465185 # Number of BTB lookups 138011502SCurtis.Dunham@arm.comsystem.cpu1.branchPred.BTBHits 65276742 # Number of BTB hits 138110585Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 138211502SCurtis.Dunham@arm.comsystem.cpu1.branchPred.BTBHitPct 69.840703 # BTB Hit Percentage 138311502SCurtis.Dunham@arm.comsystem.cpu1.branchPred.usedRAS 14217829 # Number of times the RAS was used to get a target. 138411502SCurtis.Dunham@arm.comsystem.cpu1.branchPred.RASInCorrect 926540 # Number of incorrect RAS predictions. 138511502SCurtis.Dunham@arm.comsystem.cpu1.branchPred.indirectLookups 3290763 # Number of indirect predictor lookups. 138611502SCurtis.Dunham@arm.comsystem.cpu1.branchPred.indirectHits 2135700 # Number of indirect target hits. 138711502SCurtis.Dunham@arm.comsystem.cpu1.branchPred.indirectMisses 1155063 # Number of indirect misses. 138811502SCurtis.Dunham@arm.comsystem.cpu1.branchPredindirectMispredicted 419705 # Number of mispredicted indirect branches. 138910628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 139010628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 139110628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 139210628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 139310628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 139410628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 139510628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 139610628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 139710585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 139810585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 139910585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 140010585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 140110585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 140210585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 140310585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 140410585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 140510585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 140610585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 140710585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 140810585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 140910585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 141010585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 141110585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 141210585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 141310585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 141410585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 141510585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 141610585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 141710585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 141811502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walks 255224 # Table walker walks requested 141911502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksLong 255224 # Table walker walks initiated with long descriptors 142011502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8861 # Level at which table walker walks with long descriptors terminate 142111502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level3 76574 # Level at which table walker walks with long descriptors terminate 142211502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 255224 # Table walker wait (enqueue to first request) latency 142311502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0 255224 100.00% 100.00% # Table walker wait (enqueue to first request) latency 142411502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 255224 # Table walker wait (enqueue to first request) latency 142511502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::samples 85435 # Table walker service (enqueue to completion) latency 142611502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::mean 22815.538128 # Table walker service (enqueue to completion) latency 142711502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::gmean 21300.261475 # Table walker service (enqueue to completion) latency 142811502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::stdev 14551.493747 # Table walker service (enqueue to completion) latency 142911502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::0-65535 84387 98.77% 98.77% # Table walker service (enqueue to completion) latency 143011502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::65536-131071 897 1.05% 99.82% # Table walker service (enqueue to completion) latency 143111502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::131072-196607 42 0.05% 99.87% # Table walker service (enqueue to completion) latency 143211502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::196608-262143 51 0.06% 99.93% # Table walker service (enqueue to completion) latency 143311502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::262144-327679 31 0.04% 99.97% # Table walker service (enqueue to completion) latency 143411502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::327680-393215 13 0.02% 99.98% # Table walker service (enqueue to completion) latency 143511502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::393216-458751 7 0.01% 99.99% # Table walker service (enqueue to completion) latency 143611502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 143711502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 143811502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::total 85435 # Table walker service (enqueue to completion) latency 143911502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksPending::samples -788977056 # Table walker pending requests distribution 144011502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksPending::0 -788977056 100.00% 100.00% # Table walker pending requests distribution 144111502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksPending::total -788977056 # Table walker pending requests distribution 144211502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 76574 89.63% 89.63% # Table walker page sizes translated 144311502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkPageSizes::2M 8861 10.37% 100.00% # Table walker page sizes translated 144411502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 85435 # Table walker page sizes translated 144511502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 255224 # Table walker requests started/completed, data/inst 144610628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 144711502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 255224 # Table walker requests started/completed, data/inst 144811502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 85435 # Table walker requests started/completed, data/inst 144910628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 145011502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 85435 # Table walker requests started/completed, data/inst 145111502SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 340659 # Table walker requests started/completed, data/inst 145210585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_hits 0 # ITB inst hits 145310585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_misses 0 # ITB inst misses 145411502SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_hits 78594683 # DTB read hits 145511502SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_misses 208094 # DTB read misses 145611502SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_hits 69544419 # DTB write hits 145711502SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_misses 47130 # DTB write misses 145811441Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 145910585Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 146011502SCurtis.Dunham@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID 146111502SCurtis.Dunham@arm.comsystem.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 146211502SCurtis.Dunham@arm.comsystem.cpu1.dtb.flush_entries 35846 # Number of entries that have been flushed from TLB 146311502SCurtis.Dunham@arm.comsystem.cpu1.dtb.align_faults 839 # Number of TLB faults due to alignment restrictions 146411502SCurtis.Dunham@arm.comsystem.cpu1.dtb.prefetch_faults 6709 # Number of TLB faults due to prefetch 146510585Sandreas.hansson@arm.comsystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 146611502SCurtis.Dunham@arm.comsystem.cpu1.dtb.perms_faults 11450 # Number of TLB faults due to permissions restrictions 146711502SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_accesses 78802777 # DTB read accesses 146811502SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_accesses 69591549 # DTB write accesses 146910585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 147011502SCurtis.Dunham@arm.comsystem.cpu1.dtb.hits 148139102 # DTB hits 147111502SCurtis.Dunham@arm.comsystem.cpu1.dtb.misses 255224 # DTB misses 147211502SCurtis.Dunham@arm.comsystem.cpu1.dtb.accesses 148394326 # DTB accesses 147310628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 147410628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 147510628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 147610628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 147710628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 147810628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 147910628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 148010628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 148110585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 148210585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 148310585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 148410585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 148510585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 148610585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 148710585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 148810585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 148910585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 149010585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 149110585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 149210585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 149310585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 149410585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 149510585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 149610585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 149710585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 149810585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 149910585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 150010585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 150110585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 150211502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walks 62177 # Table walker walks requested 150311502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksLong 62177 # Table walker walks initiated with long descriptors 150411502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level2 630 # Level at which table walker walks with long descriptors terminate 150511502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level3 54596 # Level at which table walker walks with long descriptors terminate 150611502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 62177 # Table walker wait (enqueue to first request) latency 150711502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkWaitTime::0 62177 100.00% 100.00% # Table walker wait (enqueue to first request) latency 150811502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 62177 # Table walker wait (enqueue to first request) latency 150911502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::samples 55226 # Table walker service (enqueue to completion) latency 151011502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::mean 25650.988665 # Table walker service (enqueue to completion) latency 151111502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::gmean 23787.605646 # Table walker service (enqueue to completion) latency 151211502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::stdev 16059.408850 # Table walker service (enqueue to completion) latency 151311502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::0-32767 49961 90.47% 90.47% # Table walker service (enqueue to completion) latency 151411502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::32768-65535 4236 7.67% 98.14% # Table walker service (enqueue to completion) latency 151511502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::65536-98303 9 0.02% 98.15% # Table walker service (enqueue to completion) latency 151611502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::98304-131071 906 1.64% 99.79% # Table walker service (enqueue to completion) latency 151711502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::131072-163839 24 0.04% 99.84% # Table walker service (enqueue to completion) latency 151811502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::163840-196607 14 0.03% 99.86% # Table walker service (enqueue to completion) latency 151911502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::196608-229375 28 0.05% 99.91% # Table walker service (enqueue to completion) latency 152011502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::229376-262143 21 0.04% 99.95% # Table walker service (enqueue to completion) latency 152111502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::262144-294911 9 0.02% 99.97% # Table walker service (enqueue to completion) latency 152211502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::294912-327679 5 0.01% 99.98% # Table walker service (enqueue to completion) latency 152311502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::327680-360447 3 0.01% 99.98% # Table walker service (enqueue to completion) latency 152411502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::360448-393215 7 0.01% 99.99% # Table walker service (enqueue to completion) latency 152511502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 152611502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 152711502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::total 55226 # Table walker service (enqueue to completion) latency 152811502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksPending::samples -789630556 # Table walker pending requests distribution 152911502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksPending::0 -789630556 100.00% 100.00% # Table walker pending requests distribution 153011502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksPending::total -789630556 # Table walker pending requests distribution 153111502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 54596 98.86% 98.86% # Table walker page sizes translated 153211502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkPageSizes::2M 630 1.14% 100.00% # Table walker page sizes translated 153311502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 55226 # Table walker page sizes translated 153410628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 153511502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 62177 # Table walker requests started/completed, data/inst 153611502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 62177 # Table walker requests started/completed, data/inst 153710628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 153811502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55226 # Table walker requests started/completed, data/inst 153911502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 55226 # Table walker requests started/completed, data/inst 154011502SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 117403 # Table walker requests started/completed, data/inst 154111502SCurtis.Dunham@arm.comsystem.cpu1.itb.inst_hits 219337574 # ITB inst hits 154211502SCurtis.Dunham@arm.comsystem.cpu1.itb.inst_misses 62177 # ITB inst misses 154310585Sandreas.hansson@arm.comsystem.cpu1.itb.read_hits 0 # DTB read hits 154410585Sandreas.hansson@arm.comsystem.cpu1.itb.read_misses 0 # DTB read misses 154510585Sandreas.hansson@arm.comsystem.cpu1.itb.write_hits 0 # DTB write hits 154610585Sandreas.hansson@arm.comsystem.cpu1.itb.write_misses 0 # DTB write misses 154711441Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 154810585Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 154911502SCurtis.Dunham@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID 155011502SCurtis.Dunham@arm.comsystem.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 155111502SCurtis.Dunham@arm.comsystem.cpu1.itb.flush_entries 25383 # Number of entries that have been flushed from TLB 155210585Sandreas.hansson@arm.comsystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 155310585Sandreas.hansson@arm.comsystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 155410585Sandreas.hansson@arm.comsystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 155511502SCurtis.Dunham@arm.comsystem.cpu1.itb.perms_faults 167002 # Number of TLB faults due to permissions restrictions 155610585Sandreas.hansson@arm.comsystem.cpu1.itb.read_accesses 0 # DTB read accesses 155710585Sandreas.hansson@arm.comsystem.cpu1.itb.write_accesses 0 # DTB write accesses 155811502SCurtis.Dunham@arm.comsystem.cpu1.itb.inst_accesses 219399751 # ITB inst accesses 155911502SCurtis.Dunham@arm.comsystem.cpu1.itb.hits 219337574 # DTB hits 156011502SCurtis.Dunham@arm.comsystem.cpu1.itb.misses 62177 # DTB misses 156111502SCurtis.Dunham@arm.comsystem.cpu1.itb.accesses 219399751 # DTB accesses 156211502SCurtis.Dunham@arm.comsystem.cpu1.numCycles 838096745 # number of cpu cycles simulated 156310585Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 156410585Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 156511502SCurtis.Dunham@arm.comsystem.cpu1.committedInsts 400342475 # Number of instructions committed 156611502SCurtis.Dunham@arm.comsystem.cpu1.committedOps 472062345 # Number of ops (including micro ops) committed 156711502SCurtis.Dunham@arm.comsystem.cpu1.discardedOps 44700411 # Number of ops (including micro ops) which were discarded before commit 156811502SCurtis.Dunham@arm.comsystem.cpu1.numFetchSuspends 5381 # Number of times Execute suspended instruction fetching 156911502SCurtis.Dunham@arm.comsystem.cpu1.quiesceCycles 93874475142 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 157011502SCurtis.Dunham@arm.comsystem.cpu1.cpi 2.093449 # CPI: cycles per instruction 157111502SCurtis.Dunham@arm.comsystem.cpu1.ipc 0.477681 # IPC: instructions per cycle 157211441Sandreas.hansson@arm.comsystem.cpu1.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 157311502SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::IntAlu 326101667 69.08% 69.08% # Class of committed instruction 157411502SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::IntMult 925373 0.20% 69.28% # Class of committed instruction 157511502SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::IntDiv 54057 0.01% 69.29% # Class of committed instruction 157611502SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::FloatAdd 0 0.00% 69.29% # Class of committed instruction 157711502SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::FloatCmp 0 0.00% 69.29% # Class of committed instruction 157811502SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::FloatCvt 0 0.00% 69.29% # Class of committed instruction 157911502SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::FloatMult 0 0.00% 69.29% # Class of committed instruction 158011502SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::FloatDiv 0 0.00% 69.29% # Class of committed instruction 158111502SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::FloatSqrt 0 0.00% 69.29% # Class of committed instruction 158211502SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdAdd 0 0.00% 69.29% # Class of committed instruction 158311502SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.29% # Class of committed instruction 158411502SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdAlu 0 0.00% 69.29% # Class of committed instruction 158511502SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdCmp 0 0.00% 69.29% # Class of committed instruction 158611502SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdCvt 0 0.00% 69.29% # Class of committed instruction 158711502SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdMisc 0 0.00% 69.29% # Class of committed instruction 158811502SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdMult 0 0.00% 69.29% # Class of committed instruction 158911502SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.29% # Class of committed instruction 159011502SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdShift 0 0.00% 69.29% # Class of committed instruction 159111502SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.29% # Class of committed instruction 159211502SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdSqrt 0 0.00% 69.29% # Class of committed instruction 159311502SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdFloatAdd 8 0.00% 69.29% # Class of committed instruction 159411502SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.29% # Class of committed instruction 159511502SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdFloatCmp 13 0.00% 69.29% # Class of committed instruction 159611502SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdFloatCvt 21 0.00% 69.29% # Class of committed instruction 159711502SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.29% # Class of committed instruction 159811502SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdFloatMisc 72329 0.02% 69.30% # Class of committed instruction 159911502SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.30% # Class of committed instruction 160011502SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.30% # Class of committed instruction 160111502SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.30% # Class of committed instruction 160211502SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::MemRead 75664367 16.03% 85.33% # Class of committed instruction 160311502SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::MemWrite 69244510 14.67% 100.00% # Class of committed instruction 160411441Sandreas.hansson@arm.comsystem.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 160511441Sandreas.hansson@arm.comsystem.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 160611502SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::total 472062345 # Class of committed instruction 160710585Sandreas.hansson@arm.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 160811502SCurtis.Dunham@arm.comsystem.cpu1.kern.inst.quiesce 5498 # number of quiesce instructions executed 160911502SCurtis.Dunham@arm.comsystem.cpu1.tickCycles 657140254 # Number of cycles that the object actually ticked 161011502SCurtis.Dunham@arm.comsystem.cpu1.idleCycles 180956491 # Total number of cycles that the object has spent stopped 161111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.replacements 4810857 # number of replacements 161211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.tagsinuse 458.623346 # Cycle average of tags in use 161311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.total_refs 140763490 # Total number of references to valid blocks. 161411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.sampled_refs 4811366 # Sample count of references to valid blocks. 161511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.avg_refs 29.256450 # Average number of references to valid blocks. 161611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.warmup_cycle 8377530544000 # Cycle when the warmup percentage was hit. 161711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 458.623346 # Average occupied blocks per requestor 161811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.895749 # Average percentage of cache occupancy 161911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.895749 # Average percentage of cache occupancy 162011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id 162111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 162211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id 162311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id 162411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id 162511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.tag_accesses 298669128 # Number of tag accesses 162611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.data_accesses 298669128 # Number of data accesses 162711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 72030058 # number of ReadReq hits 162811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_hits::total 72030058 # number of ReadReq hits 162911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 64877267 # number of WriteReq hits 163011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_hits::total 64877267 # number of WriteReq hits 163111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 197389 # number of SoftPFReq hits 163211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 197389 # number of SoftPFReq hits 163311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_hits::cpu1.data 40268 # number of WriteLineReq hits 163411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_hits::total 40268 # number of WriteLineReq hits 163511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1587155 # number of LoadLockedReq hits 163611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 1587155 # number of LoadLockedReq hits 163711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 1543611 # number of StoreCondReq hits 163811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 1543611 # number of StoreCondReq hits 163911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 136947593 # number of demand (read+write) hits 164011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_hits::total 136947593 # number of demand (read+write) hits 164111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 137144982 # number of overall hits 164211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_hits::total 137144982 # number of overall hits 164311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 3077185 # number of ReadReq misses 164411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_misses::total 3077185 # number of ReadReq misses 164511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 2162319 # number of WriteReq misses 164611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_misses::total 2162319 # number of WriteReq misses 164711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 609138 # number of SoftPFReq misses 164811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 609138 # number of SoftPFReq misses 164911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_misses::cpu1.data 415243 # number of WriteLineReq misses 165011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_misses::total 415243 # number of WriteLineReq misses 165111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 150447 # number of LoadLockedReq misses 165211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 150447 # number of LoadLockedReq misses 165311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 192941 # number of StoreCondReq misses 165411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 192941 # number of StoreCondReq misses 165511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 5654747 # number of demand (read+write) misses 165611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_misses::total 5654747 # number of demand (read+write) misses 165711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 6263885 # number of overall misses 165811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_misses::total 6263885 # number of overall misses 165911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 46366444000 # number of ReadReq miss cycles 166011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 46366444000 # number of ReadReq miss cycles 166111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 40662976500 # number of WriteReq miss cycles 166211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 40662976500 # number of WriteReq miss cycles 166311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10070349000 # number of WriteLineReq miss cycles 166411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::total 10070349000 # number of WriteLineReq miss cycles 166511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2311960000 # number of LoadLockedReq miss cycles 166611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 2311960000 # number of LoadLockedReq miss cycles 166711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4775235000 # number of StoreCondReq miss cycles 166811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 4775235000 # number of StoreCondReq miss cycles 166911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2623000 # number of StoreCondFailReq miss cycles 167011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::total 2623000 # number of StoreCondFailReq miss cycles 167111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_latency::cpu1.data 97099769500 # number of demand (read+write) miss cycles 167211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_latency::total 97099769500 # number of demand (read+write) miss cycles 167311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_latency::cpu1.data 97099769500 # number of overall miss cycles 167411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_latency::total 97099769500 # number of overall miss cycles 167511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 75107243 # number of ReadReq accesses(hits+misses) 167611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 75107243 # number of ReadReq accesses(hits+misses) 167711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 67039586 # number of WriteReq accesses(hits+misses) 167811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 67039586 # number of WriteReq accesses(hits+misses) 167911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 806527 # number of SoftPFReq accesses(hits+misses) 168011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 806527 # number of SoftPFReq accesses(hits+misses) 168111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::cpu1.data 455511 # number of WriteLineReq accesses(hits+misses) 168211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::total 455511 # number of WriteLineReq accesses(hits+misses) 168311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1737602 # number of LoadLockedReq accesses(hits+misses) 168411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 1737602 # number of LoadLockedReq accesses(hits+misses) 168511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1736552 # number of StoreCondReq accesses(hits+misses) 168611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 1736552 # number of StoreCondReq accesses(hits+misses) 168711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 142602340 # number of demand (read+write) accesses 168811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_accesses::total 142602340 # number of demand (read+write) accesses 168911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 143408867 # number of overall (read+write) accesses 169011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_accesses::total 143408867 # number of overall (read+write) accesses 169111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.040971 # miss rate for ReadReq accesses 169211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.040971 # miss rate for ReadReq accesses 169311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032254 # miss rate for WriteReq accesses 169411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.032254 # miss rate for WriteReq accesses 169511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.755261 # miss rate for SoftPFReq accesses 169611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.755261 # miss rate for SoftPFReq accesses 169711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.911598 # miss rate for WriteLineReq accesses 169811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::total 0.911598 # miss rate for WriteLineReq accesses 169911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086583 # miss rate for LoadLockedReq accesses 170011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086583 # miss rate for LoadLockedReq accesses 170111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.111106 # miss rate for StoreCondReq accesses 170211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.111106 # miss rate for StoreCondReq accesses 170311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.039654 # miss rate for demand accesses 170411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.039654 # miss rate for demand accesses 170511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.043679 # miss rate for overall accesses 170611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.043679 # miss rate for overall accesses 170711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15067.811653 # average ReadReq miss latency 170811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 15067.811653 # average ReadReq miss latency 170911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18805.262545 # average WriteReq miss latency 171011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 18805.262545 # average WriteReq miss latency 171111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24251.700811 # average WriteLineReq miss latency 171211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24251.700811 # average WriteLineReq miss latency 171311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15367.272196 # average LoadLockedReq miss latency 171411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15367.272196 # average LoadLockedReq miss latency 171511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24749.716234 # average StoreCondReq miss latency 171611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24749.716234 # average StoreCondReq miss latency 171710636Snilay@cs.wisc.edusystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 171810585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 171911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17171.372919 # average overall miss latency 172011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 17171.372919 # average overall miss latency 172111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15501.524932 # average overall miss latency 172211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 15501.524932 # average overall miss latency 172310585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 172410585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 172510585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 172610585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 172710585Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 172810585Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 172911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.writebacks::writebacks 4810864 # number of writebacks 173011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.writebacks::total 4810864 # number of writebacks 173111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 357052 # number of ReadReq MSHR hits 173211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 357052 # number of ReadReq MSHR hits 173311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 892415 # number of WriteReq MSHR hits 173411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 892415 # number of WriteReq MSHR hits 173511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 74 # number of WriteLineReq MSHR hits 173611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_hits::total 74 # number of WriteLineReq MSHR hits 173711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 40665 # number of LoadLockedReq MSHR hits 173811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 40665 # number of LoadLockedReq MSHR hits 173911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 58 # number of StoreCondReq MSHR hits 174011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_hits::total 58 # number of StoreCondReq MSHR hits 174111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_hits::cpu1.data 1249541 # number of demand (read+write) MSHR hits 174211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_hits::total 1249541 # number of demand (read+write) MSHR hits 174311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_hits::cpu1.data 1249541 # number of overall MSHR hits 174411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_hits::total 1249541 # number of overall MSHR hits 174511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2720133 # number of ReadReq MSHR misses 174611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 2720133 # number of ReadReq MSHR misses 174711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1269904 # number of WriteReq MSHR misses 174811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 1269904 # number of WriteReq MSHR misses 174911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 608760 # number of SoftPFReq MSHR misses 175011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::total 608760 # number of SoftPFReq MSHR misses 175111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 415169 # number of WriteLineReq MSHR misses 175211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::total 415169 # number of WriteLineReq MSHR misses 175311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 109782 # number of LoadLockedReq MSHR misses 175411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 109782 # number of LoadLockedReq MSHR misses 175511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 192883 # number of StoreCondReq MSHR misses 175611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 192883 # number of StoreCondReq MSHR misses 175711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.data 4405206 # number of demand (read+write) MSHR misses 175811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 4405206 # number of demand (read+write) MSHR misses 175911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.data 5013966 # number of overall MSHR misses 176011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 5013966 # number of overall MSHR misses 176111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6941 # number of ReadReq MSHR uncacheable 176211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::total 6941 # number of ReadReq MSHR uncacheable 176311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7280 # number of WriteReq MSHR uncacheable 176411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::total 7280 # number of WriteReq MSHR uncacheable 176511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14221 # number of overall MSHR uncacheable misses 176611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::total 14221 # number of overall MSHR uncacheable misses 176711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 36972803500 # number of ReadReq MSHR miss cycles 176811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 36972803500 # number of ReadReq MSHR miss cycles 176911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23335803000 # number of WriteReq MSHR miss cycles 177011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 23335803000 # number of WriteReq MSHR miss cycles 177111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13834846000 # number of SoftPFReq MSHR miss cycles 177211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13834846000 # number of SoftPFReq MSHR miss cycles 177311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9650155000 # number of WriteLineReq MSHR miss cycles 177411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9650155000 # number of WriteLineReq MSHR miss cycles 177511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1512082000 # number of LoadLockedReq MSHR miss cycles 177611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1512082000 # number of LoadLockedReq MSHR miss cycles 177711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4580259000 # number of StoreCondReq MSHR miss cycles 177811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4580259000 # number of StoreCondReq MSHR miss cycles 177911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2341500 # number of StoreCondFailReq MSHR miss cycles 178011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2341500 # number of StoreCondFailReq MSHR miss cycles 178111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 69958761500 # number of demand (read+write) MSHR miss cycles 178211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 69958761500 # number of demand (read+write) MSHR miss cycles 178311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 83793607500 # number of overall MSHR miss cycles 178411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 83793607500 # number of overall MSHR miss cycles 178511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 837242500 # number of ReadReq MSHR uncacheable cycles 178611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 837242500 # number of ReadReq MSHR uncacheable cycles 178711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 837242500 # number of overall MSHR uncacheable cycles 178811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 837242500 # number of overall MSHR uncacheable cycles 178911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036217 # mshr miss rate for ReadReq accesses 179011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036217 # mshr miss rate for ReadReq accesses 179111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018943 # mshr miss rate for WriteReq accesses 179211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018943 # mshr miss rate for WriteReq accesses 179311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.754792 # mshr miss rate for SoftPFReq accesses 179411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.754792 # mshr miss rate for SoftPFReq accesses 179511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.911436 # mshr miss rate for WriteLineReq accesses 179611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.911436 # mshr miss rate for WriteLineReq accesses 179711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063180 # mshr miss rate for LoadLockedReq accesses 179811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063180 # mshr miss rate for LoadLockedReq accesses 179911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.111072 # mshr miss rate for StoreCondReq accesses 180011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.111072 # mshr miss rate for StoreCondReq accesses 180111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030892 # mshr miss rate for demand accesses 180211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.030892 # mshr miss rate for demand accesses 180311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034963 # mshr miss rate for overall accesses 180411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.034963 # mshr miss rate for overall accesses 180511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13592.277841 # average ReadReq mshr miss latency 180611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13592.277841 # average ReadReq mshr miss latency 180711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18376.037086 # average WriteReq mshr miss latency 180811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18376.037086 # average WriteReq mshr miss latency 180911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22726.273080 # average SoftPFReq mshr miss latency 181011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22726.273080 # average SoftPFReq mshr miss latency 181111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23243.919946 # average WriteLineReq mshr miss latency 181211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23243.919946 # average WriteLineReq mshr miss latency 181311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13773.496566 # average LoadLockedReq mshr miss latency 181411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13773.496566 # average LoadLockedReq mshr miss latency 181511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23746.307347 # average StoreCondReq mshr miss latency 181611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23746.307347 # average StoreCondReq mshr miss latency 181710636Snilay@cs.wisc.edusystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 181810585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 181911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15880.928497 # average overall mshr miss latency 182011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 15880.928497 # average overall mshr miss latency 182111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16712.041426 # average overall mshr miss latency 182211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 16712.041426 # average overall mshr miss latency 182311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 120622.748883 # average ReadReq mshr uncacheable latency 182411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 120622.748883 # average ReadReq mshr uncacheable latency 182511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 58873.672738 # average overall mshr uncacheable latency 182611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 58873.672738 # average overall mshr uncacheable latency 182711502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.replacements 8744967 # number of replacements 182811502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.tagsinuse 507.224680 # Cycle average of tags in use 182911502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.total_refs 210419103 # Total number of references to valid blocks. 183011502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.sampled_refs 8745479 # Sample count of references to valid blocks. 183111502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.avg_refs 24.060329 # Average number of references to valid blocks. 183211502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.warmup_cycle 8367967785000 # Cycle when the warmup percentage was hit. 183311502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 507.224680 # Average occupied blocks per requestor 183411502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.990673 # Average percentage of cache occupancy 183511502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.990673 # Average percentage of cache occupancy 183610585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 183711502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 183811502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 304 # Occupied blocks per task id 183911502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 162 # Occupied blocks per task id 184010585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 184111502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.tag_accesses 447074643 # Number of tag accesses 184211502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.data_accesses 447074643 # Number of data accesses 184311502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 210419103 # number of ReadReq hits 184411502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_hits::total 210419103 # number of ReadReq hits 184511502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 210419103 # number of demand (read+write) hits 184611502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_hits::total 210419103 # number of demand (read+write) hits 184711502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 210419103 # number of overall hits 184811502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_hits::total 210419103 # number of overall hits 184911502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 8745479 # number of ReadReq misses 185011502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_misses::total 8745479 # number of ReadReq misses 185111502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 8745479 # number of demand (read+write) misses 185211502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_misses::total 8745479 # number of demand (read+write) misses 185311502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 8745479 # number of overall misses 185411502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_misses::total 8745479 # number of overall misses 185511502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 88268174500 # number of ReadReq miss cycles 185611502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 88268174500 # number of ReadReq miss cycles 185711502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 88268174500 # number of demand (read+write) miss cycles 185811502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_latency::total 88268174500 # number of demand (read+write) miss cycles 185911502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 88268174500 # number of overall miss cycles 186011502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_latency::total 88268174500 # number of overall miss cycles 186111502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 219164582 # number of ReadReq accesses(hits+misses) 186211502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_accesses::total 219164582 # number of ReadReq accesses(hits+misses) 186311502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 219164582 # number of demand (read+write) accesses 186411502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_accesses::total 219164582 # number of demand (read+write) accesses 186511502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 219164582 # number of overall (read+write) accesses 186611502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_accesses::total 219164582 # number of overall (read+write) accesses 186711502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.039904 # miss rate for ReadReq accesses 186811502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.039904 # miss rate for ReadReq accesses 186911502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.039904 # miss rate for demand accesses 187011502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.039904 # miss rate for demand accesses 187111502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.039904 # miss rate for overall accesses 187211502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.039904 # miss rate for overall accesses 187311502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10093.006284 # average ReadReq miss latency 187411502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 10093.006284 # average ReadReq miss latency 187511502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10093.006284 # average overall miss latency 187611502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 10093.006284 # average overall miss latency 187711502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10093.006284 # average overall miss latency 187811502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 10093.006284 # average overall miss latency 187910585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 188010585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 188110585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 188210585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 188310585Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 188410585Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 188511502SCurtis.Dunham@arm.comsystem.cpu1.icache.writebacks::writebacks 8744967 # number of writebacks 188611502SCurtis.Dunham@arm.comsystem.cpu1.icache.writebacks::total 8744967 # number of writebacks 188711502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8745479 # number of ReadReq MSHR misses 188811502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 8745479 # number of ReadReq MSHR misses 188911502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 8745479 # number of demand (read+write) MSHR misses 189011502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_misses::total 8745479 # number of demand (read+write) MSHR misses 189111502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 8745479 # number of overall MSHR misses 189211502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_misses::total 8745479 # number of overall MSHR misses 189311353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable 189411353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::total 93 # number of ReadReq MSHR uncacheable 189511353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses 189611353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::total 93 # number of overall MSHR uncacheable misses 189711502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 83895435000 # number of ReadReq MSHR miss cycles 189811502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 83895435000 # number of ReadReq MSHR miss cycles 189911502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 83895435000 # number of demand (read+write) MSHR miss cycles 190011502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 83895435000 # number of demand (read+write) MSHR miss cycles 190111502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 83895435000 # number of overall MSHR miss cycles 190211502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 83895435000 # number of overall MSHR miss cycles 190311502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8450000 # number of ReadReq MSHR uncacheable cycles 190411502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8450000 # number of ReadReq MSHR uncacheable cycles 190511502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8450000 # number of overall MSHR uncacheable cycles 190611502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::total 8450000 # number of overall MSHR uncacheable cycles 190711502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.039904 # mshr miss rate for ReadReq accesses 190811502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.039904 # mshr miss rate for ReadReq accesses 190911502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.039904 # mshr miss rate for demand accesses 191011502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.039904 # mshr miss rate for demand accesses 191111502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.039904 # mshr miss rate for overall accesses 191211502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.039904 # mshr miss rate for overall accesses 191311502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9593.006284 # average ReadReq mshr miss latency 191411502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9593.006284 # average ReadReq mshr miss latency 191511502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9593.006284 # average overall mshr miss latency 191611502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 9593.006284 # average overall mshr miss latency 191711502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9593.006284 # average overall mshr miss latency 191811502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 9593.006284 # average overall mshr miss latency 191911502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90860.215054 # average ReadReq mshr uncacheable latency 192011502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90860.215054 # average ReadReq mshr uncacheable latency 192111502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90860.215054 # average overall mshr uncacheable latency 192211502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90860.215054 # average overall mshr uncacheable latency 192311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.prefetcher.num_hwpf_issued 6641051 # number of hwpf issued 192411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.prefetcher.pfIdentified 6641093 # number of prefetch candidates identified 192511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.prefetcher.pfBufferHit 36 # number of redundant prefetches already in prefetch queue 192610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 192710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 192811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.prefetcher.pfSpanPage 796339 # number of prefetches not generated due to page crossing 192911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.replacements 2218428 # number of replacements 193011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.tagsinuse 13419.558556 # Cycle average of tags in use 193111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.total_refs 21617433 # Total number of references to valid blocks. 193211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.sampled_refs 2233865 # Sample count of references to valid blocks. 193311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.avg_refs 9.677144 # Average number of references to valid blocks. 193411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 10005238958500 # Cycle when the warmup percentage was hit. 193511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 12516.094704 # Average occupied blocks per requestor 193611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 63.377354 # Average occupied blocks per requestor 193711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 44.102544 # Average occupied blocks per requestor 193811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 795.983954 # Average occupied blocks per requestor 193911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.763922 # Average percentage of cache occupancy 194011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003868 # Average percentage of cache occupancy 194111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.002692 # Average percentage of cache occupancy 194211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.048583 # Average percentage of cache occupancy 194311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.819065 # Average percentage of cache occupancy 194411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1022 1192 # Occupied blocks per task id 194511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 81 # Occupied blocks per task id 194611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 14164 # Occupied blocks per task id 194711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::2 158 # Occupied blocks per task id 194811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::3 771 # Occupied blocks per task id 194911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::4 263 # Occupied blocks per task id 195011441Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id 195111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 54 # Occupied blocks per task id 195211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 195311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id 195411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id 195511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id 195611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4872 # Occupied blocks per task id 195711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6319 # Occupied blocks per task id 195811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2682 # Occupied blocks per task id 195911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1022 0.072754 # Percentage of cache occupancy per task id 196011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004944 # Percentage of cache occupancy per task id 196111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.864502 # Percentage of cache occupancy per task id 196211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.tag_accesses 457671450 # Number of tag accesses 196311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.data_accesses 457671450 # Number of data accesses 196411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 494400 # number of ReadReq hits 196511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 160613 # number of ReadReq hits 196611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 655013 # number of ReadReq hits 196711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::writebacks 3026488 # number of WritebackDirty hits 196811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::total 3026488 # number of WritebackDirty hits 196911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_hits::writebacks 10527430 # number of WritebackClean hits 197011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_hits::total 10527430 # number of WritebackClean hits 197111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::cpu1.data 434 # number of UpgradeReq hits 197211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::total 434 # number of UpgradeReq hits 197311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 789107 # number of ReadExReq hits 197411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 789107 # number of ReadExReq hits 197511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8072877 # number of ReadCleanReq hits 197611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 8072877 # number of ReadCleanReq hits 197711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2507088 # number of ReadSharedReq hits 197811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 2507088 # number of ReadSharedReq hits 197911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::cpu1.data 171056 # number of InvalidateReq hits 198011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::total 171056 # number of InvalidateReq hits 198111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 494400 # number of demand (read+write) hits 198211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 160613 # number of demand (read+write) hits 198311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 8072877 # number of demand (read+write) hits 198411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 3296195 # number of demand (read+write) hits 198511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::total 12024085 # number of demand (read+write) hits 198611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 494400 # number of overall hits 198711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 160613 # number of overall hits 198811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 8072877 # number of overall hits 198911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 3296195 # number of overall hits 199011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::total 12024085 # number of overall hits 199111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11721 # number of ReadReq misses 199211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8689 # number of ReadReq misses 199311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 20410 # number of ReadReq misses 199411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses 199511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses 199611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses 199711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses 199811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 220631 # number of UpgradeReq misses 199911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 220631 # number of UpgradeReq misses 200011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 192879 # number of SCUpgradeReq misses 200111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 192879 # number of SCUpgradeReq misses 200211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 4 # number of SCUpgradeFailReq misses 200311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses 200411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 261966 # number of ReadExReq misses 200511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 261966 # number of ReadExReq misses 200611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 672602 # number of ReadCleanReq misses 200711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 672602 # number of ReadCleanReq misses 200811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 931427 # number of ReadSharedReq misses 200911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 931427 # number of ReadSharedReq misses 201011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::cpu1.data 242391 # number of InvalidateReq misses 201111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::total 242391 # number of InvalidateReq misses 201211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11721 # number of demand (read+write) misses 201311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 8689 # number of demand (read+write) misses 201411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 672602 # number of demand (read+write) misses 201511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 1193393 # number of demand (read+write) misses 201611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::total 1886405 # number of demand (read+write) misses 201711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11721 # number of overall misses 201811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 8689 # number of overall misses 201911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 672602 # number of overall misses 202011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 1193393 # number of overall misses 202111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::total 1886405 # number of overall misses 202211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 429270500 # number of ReadReq miss cycles 202311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 326619000 # number of ReadReq miss cycles 202411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::total 755889500 # number of ReadReq miss cycles 202511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 1918862500 # number of UpgradeReq miss cycles 202611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::total 1918862500 # number of UpgradeReq miss cycles 202711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1442678000 # number of SCUpgradeReq miss cycles 202811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1442678000 # number of SCUpgradeReq miss cycles 202911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2273499 # number of SCUpgradeFailReq miss cycles 203011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2273499 # number of SCUpgradeFailReq miss cycles 203111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10385042497 # number of ReadExReq miss cycles 203211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::total 10385042497 # number of ReadExReq miss cycles 203311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 22017991000 # number of ReadCleanReq miss cycles 203411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::total 22017991000 # number of ReadCleanReq miss cycles 203511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 30592821494 # number of ReadSharedReq miss cycles 203611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::total 30592821494 # number of ReadSharedReq miss cycles 203711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 352126000 # number of InvalidateReq miss cycles 203811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::total 352126000 # number of InvalidateReq miss cycles 203911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 429270500 # number of demand (read+write) miss cycles 204011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 326619000 # number of demand (read+write) miss cycles 204111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.inst 22017991000 # number of demand (read+write) miss cycles 204211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.data 40977863991 # number of demand (read+write) miss cycles 204311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_latency::total 63751744491 # number of demand (read+write) miss cycles 204411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 429270500 # number of overall miss cycles 204511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 326619000 # number of overall miss cycles 204611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.inst 22017991000 # number of overall miss cycles 204711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.data 40977863991 # number of overall miss cycles 204811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_latency::total 63751744491 # number of overall miss cycles 204911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 506121 # number of ReadReq accesses(hits+misses) 205011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 169302 # number of ReadReq accesses(hits+misses) 205111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 675423 # number of ReadReq accesses(hits+misses) 205211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::writebacks 3026489 # number of WritebackDirty accesses(hits+misses) 205311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::total 3026489 # number of WritebackDirty accesses(hits+misses) 205411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::writebacks 10527431 # number of WritebackClean accesses(hits+misses) 205511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::total 10527431 # number of WritebackClean accesses(hits+misses) 205611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 221065 # number of UpgradeReq accesses(hits+misses) 205711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 221065 # number of UpgradeReq accesses(hits+misses) 205811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 192879 # number of SCUpgradeReq accesses(hits+misses) 205911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 192879 # number of SCUpgradeReq accesses(hits+misses) 206011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 4 # number of SCUpgradeFailReq accesses(hits+misses) 206111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) 206211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1051073 # number of ReadExReq accesses(hits+misses) 206311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 1051073 # number of ReadExReq accesses(hits+misses) 206411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 8745479 # number of ReadCleanReq accesses(hits+misses) 206511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 8745479 # number of ReadCleanReq accesses(hits+misses) 206611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3438515 # number of ReadSharedReq accesses(hits+misses) 206711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 3438515 # number of ReadSharedReq accesses(hits+misses) 206811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 413447 # number of InvalidateReq accesses(hits+misses) 206911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::total 413447 # number of InvalidateReq accesses(hits+misses) 207011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 506121 # number of demand (read+write) accesses 207111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 169302 # number of demand (read+write) accesses 207211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 8745479 # number of demand (read+write) accesses 207311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 4489588 # number of demand (read+write) accesses 207411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::total 13910490 # number of demand (read+write) accesses 207511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 506121 # number of overall (read+write) accesses 207611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 169302 # number of overall (read+write) accesses 207711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 8745479 # number of overall (read+write) accesses 207811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 4489588 # number of overall (read+write) accesses 207911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::total 13910490 # number of overall (read+write) accesses 208011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.023158 # miss rate for ReadReq accesses 208111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.051322 # miss rate for ReadReq accesses 208211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.030218 # miss rate for ReadReq accesses 208311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000000 # miss rate for WritebackDirty accesses 208411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000000 # miss rate for WritebackDirty accesses 208511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses 208611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses 208711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.998037 # miss rate for UpgradeReq accesses 208811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 0.998037 # miss rate for UpgradeReq accesses 208911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 209011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 209110636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 209210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 209311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.249237 # miss rate for ReadExReq accesses 209411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.249237 # miss rate for ReadExReq accesses 209511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.076909 # miss rate for ReadCleanReq accesses 209611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.076909 # miss rate for ReadCleanReq accesses 209711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.270881 # miss rate for ReadSharedReq accesses 209811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.270881 # miss rate for ReadSharedReq accesses 209911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.586269 # miss rate for InvalidateReq accesses 210011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::total 0.586269 # miss rate for InvalidateReq accesses 210111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.023158 # miss rate for demand accesses 210211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.051322 # miss rate for demand accesses 210311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.076909 # miss rate for demand accesses 210411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.265813 # miss rate for demand accesses 210511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.135610 # miss rate for demand accesses 210611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.023158 # miss rate for overall accesses 210711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.051322 # miss rate for overall accesses 210811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.076909 # miss rate for overall accesses 210911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.265813 # miss rate for overall accesses 211011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.135610 # miss rate for overall accesses 211111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 36624.050849 # average ReadReq miss latency 211211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 37589.941305 # average ReadReq miss latency 211311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::total 37035.252327 # average ReadReq miss latency 211411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 8697.157244 # average UpgradeReq miss latency 211511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 8697.157244 # average UpgradeReq miss latency 211611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 7479.704893 # average SCUpgradeReq miss latency 211711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 7479.704893 # average SCUpgradeReq miss latency 211811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 568374.750000 # average SCUpgradeFailReq miss latency 211911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 568374.750000 # average SCUpgradeFailReq miss latency 212011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39642.711256 # average ReadExReq miss latency 212111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39642.711256 # average ReadExReq miss latency 212211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 32735.541970 # average ReadCleanReq miss latency 212311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 32735.541970 # average ReadCleanReq miss latency 212411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 32845.109165 # average ReadSharedReq miss latency 212511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 32845.109165 # average ReadSharedReq miss latency 212611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1452.718954 # average InvalidateReq miss latency 212711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1452.718954 # average InvalidateReq miss latency 212811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 36624.050849 # average overall miss latency 212911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 37589.941305 # average overall miss latency 213011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 32735.541970 # average overall miss latency 213111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34337.275307 # average overall miss latency 213211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::total 33795.364458 # average overall miss latency 213311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 36624.050849 # average overall miss latency 213411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 37589.941305 # average overall miss latency 213511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 32735.541970 # average overall miss latency 213611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34337.275307 # average overall miss latency 213711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::total 33795.364458 # average overall miss latency 213811441Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 213910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 214011441Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 214110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 214211441Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 214310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 214411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.unused_prefetches 43661 # number of HardPF blocks evicted w/o reference 214511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.writebacks::writebacks 1101410 # number of writebacks 214611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.writebacks::total 1101410 # number of writebacks 214711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits 214811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 2 # number of ReadReq MSHR hits 214911441Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits 215011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 4694 # number of ReadExReq MSHR hits 215111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::total 4694 # number of ReadExReq MSHR hits 215211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 3 # number of ReadCleanReq MSHR hits 215311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits 215411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 558 # number of ReadSharedReq MSHR hits 215511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::total 558 # number of ReadSharedReq MSHR hits 215611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits 215711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 2 # number of demand (read+write) MSHR hits 215811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits 215911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.data 5252 # number of demand (read+write) MSHR hits 216011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_hits::total 5258 # number of demand (read+write) MSHR hits 216111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits 216211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 2 # number of overall MSHR hits 216311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits 216411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.data 5252 # number of overall MSHR hits 216511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_hits::total 5258 # number of overall MSHR hits 216611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 11720 # number of ReadReq MSHR misses 216711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8687 # number of ReadReq MSHR misses 216811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::total 20407 # number of ReadReq MSHR misses 216911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 1 # number of WritebackDirty MSHR misses 217011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_mshr_misses::total 1 # number of WritebackDirty MSHR misses 217111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses 217211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses 217311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 709103 # number of HardPFReq MSHR misses 217411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::total 709103 # number of HardPFReq MSHR misses 217511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 220631 # number of UpgradeReq MSHR misses 217611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::total 220631 # number of UpgradeReq MSHR misses 217711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 192879 # number of SCUpgradeReq MSHR misses 217811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 192879 # number of SCUpgradeReq MSHR misses 217911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 4 # number of SCUpgradeFailReq MSHR misses 218011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses 218111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 257272 # number of ReadExReq MSHR misses 218211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::total 257272 # number of ReadExReq MSHR misses 218311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 672599 # number of ReadCleanReq MSHR misses 218411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::total 672599 # number of ReadCleanReq MSHR misses 218511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 930869 # number of ReadSharedReq MSHR misses 218611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::total 930869 # number of ReadSharedReq MSHR misses 218711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 242391 # number of InvalidateReq MSHR misses 218811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::total 242391 # number of InvalidateReq MSHR misses 218911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 11720 # number of demand (read+write) MSHR misses 219011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8687 # number of demand (read+write) MSHR misses 219111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.inst 672599 # number of demand (read+write) MSHR misses 219211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.data 1188141 # number of demand (read+write) MSHR misses 219311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_misses::total 1881147 # number of demand (read+write) MSHR misses 219411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 11720 # number of overall MSHR misses 219511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8687 # number of overall MSHR misses 219611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.inst 672599 # number of overall MSHR misses 219711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.data 1188141 # number of overall MSHR misses 219811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 709103 # number of overall MSHR misses 219911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_misses::total 2590250 # number of overall MSHR misses 220011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable 220111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 6941 # number of ReadReq MSHR uncacheable 220211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::total 7034 # number of ReadReq MSHR uncacheable 220311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 7280 # number of WriteReq MSHR uncacheable 220411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::total 7280 # number of WriteReq MSHR uncacheable 220511353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses 220611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 14221 # number of overall MSHR uncacheable misses 220711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::total 14314 # number of overall MSHR uncacheable misses 220811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 358927500 # number of ReadReq MSHR miss cycles 220911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 274457000 # number of ReadReq MSHR miss cycles 221011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::total 633384500 # number of ReadReq MSHR miss cycles 221111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 25470013765 # number of HardPFReq MSHR miss cycles 221211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 25470013765 # number of HardPFReq MSHR miss cycles 221311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4591069994 # number of UpgradeReq MSHR miss cycles 221411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4591069994 # number of UpgradeReq MSHR miss cycles 221511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3129353001 # number of SCUpgradeReq MSHR miss cycles 221611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3129353001 # number of SCUpgradeReq MSHR miss cycles 221711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2003499 # number of SCUpgradeFailReq MSHR miss cycles 221811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2003499 # number of SCUpgradeFailReq MSHR miss cycles 221911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8263742497 # number of ReadExReq MSHR miss cycles 222011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8263742497 # number of ReadExReq MSHR miss cycles 222111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 17982320500 # number of ReadCleanReq MSHR miss cycles 222211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 17982320500 # number of ReadCleanReq MSHR miss cycles 222311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 24961268994 # number of ReadSharedReq MSHR miss cycles 222411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 24961268994 # number of ReadSharedReq MSHR miss cycles 222511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6347282500 # number of InvalidateReq MSHR miss cycles 222611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6347282500 # number of InvalidateReq MSHR miss cycles 222711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 358927500 # number of demand (read+write) MSHR miss cycles 222811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 274457000 # number of demand (read+write) MSHR miss cycles 222911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 17982320500 # number of demand (read+write) MSHR miss cycles 223011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 33225011491 # number of demand (read+write) MSHR miss cycles 223111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::total 51840716491 # number of demand (read+write) MSHR miss cycles 223211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 358927500 # number of overall MSHR miss cycles 223311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 274457000 # number of overall MSHR miss cycles 223411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 17982320500 # number of overall MSHR miss cycles 223511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 33225011491 # number of overall MSHR miss cycles 223611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 25470013765 # number of overall MSHR miss cycles 223711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::total 77310730256 # number of overall MSHR miss cycles 223811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7706000 # number of ReadReq MSHR uncacheable cycles 223911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 781601000 # number of ReadReq MSHR uncacheable cycles 224011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 789307000 # number of ReadReq MSHR uncacheable cycles 224111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7706000 # number of overall MSHR uncacheable cycles 224211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 781601000 # number of overall MSHR uncacheable cycles 224311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::total 789307000 # number of overall MSHR uncacheable cycles 224411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023157 # mshr miss rate for ReadReq accesses 224511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.051311 # mshr miss rate for ReadReq accesses 224611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.030214 # mshr miss rate for ReadReq accesses 224711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackDirty accesses 224811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackDirty accesses 224911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses 225011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses 225110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 225210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 225311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.998037 # mshr miss rate for UpgradeReq accesses 225411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.998037 # mshr miss rate for UpgradeReq accesses 225511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 225611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 225710636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 225810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 225911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.244771 # mshr miss rate for ReadExReq accesses 226011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.244771 # mshr miss rate for ReadExReq accesses 226111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.076908 # mshr miss rate for ReadCleanReq accesses 226211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.076908 # mshr miss rate for ReadCleanReq accesses 226311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.270718 # mshr miss rate for ReadSharedReq accesses 226411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.270718 # mshr miss rate for ReadSharedReq accesses 226511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.586269 # mshr miss rate for InvalidateReq accesses 226611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.586269 # mshr miss rate for InvalidateReq accesses 226711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023157 # mshr miss rate for demand accesses 226811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.051311 # mshr miss rate for demand accesses 226911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.076908 # mshr miss rate for demand accesses 227011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.264644 # mshr miss rate for demand accesses 227111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::total 0.135232 # mshr miss rate for demand accesses 227211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023157 # mshr miss rate for overall accesses 227311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.051311 # mshr miss rate for overall accesses 227411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.076908 # mshr miss rate for overall accesses 227511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.264644 # mshr miss rate for overall accesses 227610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 227711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::total 0.186208 # mshr miss rate for overall accesses 227811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 30625.213311 # average ReadReq mshr miss latency 227911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31593.991021 # average ReadReq mshr miss latency 228011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 31037.609644 # average ReadReq mshr miss latency 228111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35918.637723 # average HardPFReq mshr miss latency 228211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35918.637723 # average HardPFReq mshr miss latency 228311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20808.816504 # average UpgradeReq mshr miss latency 228411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20808.816504 # average UpgradeReq mshr miss latency 228511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16224.436051 # average SCUpgradeReq mshr miss latency 228611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16224.436051 # average SCUpgradeReq mshr miss latency 228711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 500874.750000 # average SCUpgradeFailReq mshr miss latency 228811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 500874.750000 # average SCUpgradeFailReq mshr miss latency 228911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32120.644676 # average ReadExReq mshr miss latency 229011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32120.644676 # average ReadExReq mshr miss latency 229111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 26735.574243 # average ReadCleanReq mshr miss latency 229211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 26735.574243 # average ReadCleanReq mshr miss latency 229311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 26815.018004 # average ReadSharedReq mshr miss latency 229411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26815.018004 # average ReadSharedReq mshr miss latency 229511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26186.131086 # average InvalidateReq mshr miss latency 229611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26186.131086 # average InvalidateReq mshr miss latency 229711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 30625.213311 # average overall mshr miss latency 229811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31593.991021 # average overall mshr miss latency 229911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26735.574243 # average overall mshr miss latency 230011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27963.862446 # average overall mshr miss latency 230111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27558.035864 # average overall mshr miss latency 230211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 30625.213311 # average overall mshr miss latency 230311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31593.991021 # average overall mshr miss latency 230411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26735.574243 # average overall mshr miss latency 230511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27963.862446 # average overall mshr miss latency 230611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35918.637723 # average overall mshr miss latency 230711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29846.821834 # average overall mshr miss latency 230811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 82860.215054 # average ReadReq mshr uncacheable latency 230911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 112606.396773 # average ReadReq mshr uncacheable latency 231011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 112213.107762 # average ReadReq mshr uncacheable latency 231111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 82860.215054 # average overall mshr uncacheable latency 231211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 54961.043527 # average overall mshr uncacheable latency 231311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 55142.308230 # average overall mshr uncacheable latency 231411502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_requests 27911552 # Total number of requests made to the snoop filter. 231511502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_requests 14263179 # Number of requests hitting in the snoop filter with a single holder of the requested data. 231611502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1909 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 231711502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_snoops 2035614 # Total number of snoops made to the snoop filter. 231811502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2035313 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 231911502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 301 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 232011502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 755700 # Transaction distribution 232111502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 13030335 # Transaction distribution 232211502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 7280 # Transaction distribution 232311502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 7280 # Transaction distribution 232411502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackDirty 4134671 # Transaction distribution 232511502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackClean 10529340 # Transaction distribution 232611502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::CleanEvict 2783515 # Transaction distribution 232711502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFReq 903944 # Transaction distribution 232811502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 232911502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 426493 # Transaction distribution 233011502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 348519 # Transaction distribution 233111502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 477830 # Transaction distribution 233211502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 70 # Transaction distribution 233311502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution 233411502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 1080105 # Transaction distribution 233511502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 1057121 # Transaction distribution 233611502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 8745479 # Transaction distribution 233711502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 4495606 # Transaction distribution 233811502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateReq 466229 # Transaction distribution 233911502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateResp 413447 # Transaction distribution 234011502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 26236111 # Packet count per connected master and slave (bytes) 234111502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15633953 # Packet count per connected master and slave (bytes) 234211502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 355051 # Packet count per connected master and slave (bytes) 234311502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1069038 # Packet count per connected master and slave (bytes) 234411502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count::total 43294153 # Packet count per connected master and slave (bytes) 234511502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1119394496 # Cumulative packet size per connected master and slave (bytes) 234611502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 601463021 # Cumulative packet size per connected master and slave (bytes) 234711502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1354416 # Cumulative packet size per connected master and slave (bytes) 234811502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4048968 # Cumulative packet size per connected master and slave (bytes) 234911502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size::total 1726260901 # Cumulative packet size per connected master and slave (bytes) 235011502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoops 6529606 # Total snoops (count) 235111502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 21121122 # Request fanout histogram 235211502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 0.110367 # Request fanout histogram 235311502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.313393 # Request fanout histogram 235410585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 235511502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 18790338 88.96% 88.96% # Request fanout histogram 235611502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 2330483 11.03% 100.00% # Request fanout histogram 235711502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 301 0.00% 100.00% # Request fanout histogram 235810585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 235911138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 236010827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 236111502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 21121122 # Request fanout histogram 236211502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.reqLayer0.occupancy 27750114484 # Layer occupancy (ticks) 236311201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 236411502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoopLayer0.occupancy 177306545 # Layer occupancy (ticks) 236510585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 236611502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.respLayer0.occupancy 13121677843 # Layer occupancy (ticks) 236710585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 236811502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.respLayer1.occupancy 7163335235 # Layer occupancy (ticks) 236910585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 237011502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.respLayer2.occupancy 185802393 # Layer occupancy (ticks) 237110585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 237211502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.respLayer3.occupancy 563017795 # Layer occupancy (ticks) 237310585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 237411502SCurtis.Dunham@arm.comsystem.iobus.trans_dist::ReadReq 40337 # Transaction distribution 237511502SCurtis.Dunham@arm.comsystem.iobus.trans_dist::ReadResp 40337 # Transaction distribution 237611502SCurtis.Dunham@arm.comsystem.iobus.trans_dist::WriteReq 136616 # Transaction distribution 237711502SCurtis.Dunham@arm.comsystem.iobus.trans_dist::WriteResp 136616 # Transaction distribution 237811502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47664 # Packet count per connected master and slave (bytes) 237910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 238011245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 238110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 238210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 238310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 238410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 238510585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 238610585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 238710585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 238810585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 238911502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 239010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 239111502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122598 # Packet count per connected master and slave (bytes) 239211502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231228 # Packet count per connected master and slave (bytes) 239311502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231228 # Packet count per connected master and slave (bytes) 239410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 239510585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 239611502SCurtis.Dunham@arm.comsystem.iobus.pkt_count::total 353906 # Packet count per connected master and slave (bytes) 239711502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47684 # Cumulative packet size per connected master and slave (bytes) 239810585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 239911245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 240010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 240110585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 240210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 240310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 240410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 240510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 240610585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 240710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 240811502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 240910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 241011502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::total 155705 # Cumulative packet size per connected master and slave (bytes) 241111502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338928 # Cumulative packet size per connected master and slave (bytes) 241211502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7338928 # Cumulative packet size per connected master and slave (bytes) 241310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 241410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 241511502SCurtis.Dunham@arm.comsystem.iobus.pkt_size::total 7496719 # Cumulative packet size per connected master and slave (bytes) 241611502SCurtis.Dunham@arm.comsystem.iobus.reqLayer0.occupancy 43180502 # Layer occupancy (ticks) 241710585Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 241811353Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) 241910585Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 242011502SCurtis.Dunham@arm.comsystem.iobus.reqLayer2.occupancy 324000 # Layer occupancy (ticks) 242110585Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 242211502SCurtis.Dunham@arm.comsystem.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 242310585Sandreas.hansson@arm.comsystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 242411502SCurtis.Dunham@arm.comsystem.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks) 242511245Sandreas.sandberg@arm.comsystem.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 242611502SCurtis.Dunham@arm.comsystem.iobus.reqLayer10.occupancy 9000 # Layer occupancy (ticks) 242710585Sandreas.hansson@arm.comsystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 242811502SCurtis.Dunham@arm.comsystem.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) 242910585Sandreas.hansson@arm.comsystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 243011502SCurtis.Dunham@arm.comsystem.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 243110585Sandreas.hansson@arm.comsystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 243211502SCurtis.Dunham@arm.comsystem.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) 243310585Sandreas.hansson@arm.comsystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 243411502SCurtis.Dunham@arm.comsystem.iobus.reqLayer16.occupancy 15500 # Layer occupancy (ticks) 243510585Sandreas.hansson@arm.comsystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 243611502SCurtis.Dunham@arm.comsystem.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 243710585Sandreas.hansson@arm.comsystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 243811502SCurtis.Dunham@arm.comsystem.iobus.reqLayer23.occupancy 25595502 # Layer occupancy (ticks) 243910585Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 244011502SCurtis.Dunham@arm.comsystem.iobus.reqLayer24.occupancy 36402501 # Layer occupancy (ticks) 244110585Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 244211502SCurtis.Dunham@arm.comsystem.iobus.reqLayer25.occupancy 569469754 # Layer occupancy (ticks) 244310585Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 244411502SCurtis.Dunham@arm.comsystem.iobus.respLayer0.occupancy 92713000 # Layer occupancy (ticks) 244510585Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 244611502SCurtis.Dunham@arm.comsystem.iobus.respLayer3.occupancy 147924000 # Layer occupancy (ticks) 244710585Sandreas.hansson@arm.comsystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 244810892Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 244910585Sandreas.hansson@arm.comsystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 245011502SCurtis.Dunham@arm.comsystem.iocache.tags.replacements 115611 # number of replacements 245111502SCurtis.Dunham@arm.comsystem.iocache.tags.tagsinuse 11.284790 # Cycle average of tags in use 245211336Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 245311502SCurtis.Dunham@arm.comsystem.iocache.tags.sampled_refs 115627 # Sample count of references to valid blocks. 245411336Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 245511502SCurtis.Dunham@arm.comsystem.iocache.tags.warmup_cycle 9167417766000 # Cycle when the warmup percentage was hit. 245611502SCurtis.Dunham@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 7.418888 # Average occupied blocks per requestor 245711502SCurtis.Dunham@arm.comsystem.iocache.tags.occ_blocks::realview.ide 3.865902 # Average occupied blocks per requestor 245811502SCurtis.Dunham@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.463681 # Average percentage of cache occupancy 245911502SCurtis.Dunham@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.241619 # Average percentage of cache occupancy 246011502SCurtis.Dunham@arm.comsystem.iocache.tags.occ_percent::total 0.705299 # Average percentage of cache occupancy 246110585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 246210827Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 246310585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 246411502SCurtis.Dunham@arm.comsystem.iocache.tags.tag_accesses 1040883 # Number of tag accesses 246511502SCurtis.Dunham@arm.comsystem.iocache.tags.data_accesses 1040883 # Number of data accesses 246610585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 246711502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_misses::realview.ide 8886 # number of ReadReq misses 246811502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_misses::total 8923 # number of ReadReq misses 246910585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 247010585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 247111502SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 247211502SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 247310585Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 247411502SCurtis.Dunham@arm.comsystem.iocache.demand_misses::realview.ide 115614 # number of demand (read+write) misses 247511502SCurtis.Dunham@arm.comsystem.iocache.demand_misses::total 115654 # number of demand (read+write) misses 247610585Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 247711502SCurtis.Dunham@arm.comsystem.iocache.overall_misses::realview.ide 115614 # number of overall misses 247811502SCurtis.Dunham@arm.comsystem.iocache.overall_misses::total 115654 # number of overall misses 247911502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles 248011502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_miss_latency::realview.ide 1668794518 # number of ReadReq miss cycles 248111502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_miss_latency::total 1673992518 # number of ReadReq miss cycles 248210726Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 248310726Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 248411502SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_miss_latency::realview.ide 12857701236 # number of WriteLineReq miss cycles 248511502SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_miss_latency::total 12857701236 # number of WriteLineReq miss cycles 248611502SCurtis.Dunham@arm.comsystem.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles 248711502SCurtis.Dunham@arm.comsystem.iocache.demand_miss_latency::realview.ide 14526495754 # number of demand (read+write) miss cycles 248811502SCurtis.Dunham@arm.comsystem.iocache.demand_miss_latency::total 14532062754 # number of demand (read+write) miss cycles 248911502SCurtis.Dunham@arm.comsystem.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles 249011502SCurtis.Dunham@arm.comsystem.iocache.overall_miss_latency::realview.ide 14526495754 # number of overall miss cycles 249111502SCurtis.Dunham@arm.comsystem.iocache.overall_miss_latency::total 14532062754 # number of overall miss cycles 249210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 249311502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8886 # number of ReadReq accesses(hits+misses) 249411502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_accesses::total 8923 # number of ReadReq accesses(hits+misses) 249510585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 249610585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 249711502SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 249811502SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 249910585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 250011502SCurtis.Dunham@arm.comsystem.iocache.demand_accesses::realview.ide 115614 # number of demand (read+write) accesses 250111502SCurtis.Dunham@arm.comsystem.iocache.demand_accesses::total 115654 # number of demand (read+write) accesses 250210585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 250311502SCurtis.Dunham@arm.comsystem.iocache.overall_accesses::realview.ide 115614 # number of overall (read+write) accesses 250411502SCurtis.Dunham@arm.comsystem.iocache.overall_accesses::total 115654 # number of overall (read+write) accesses 250510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 250610585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 250710585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 250810585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 250910585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 251011336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 251111336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 251210585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 251310585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 251410585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 251510585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 251610585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 251710585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 251811502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency 251911502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 187800.418411 # average ReadReq miss latency 252011502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 187604.227054 # average ReadReq miss latency 252110726Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 252210726Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 252311502SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::realview.ide 120471.677873 # average WriteLineReq miss latency 252411502SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 120471.677873 # average WriteLineReq miss latency 252511502SCurtis.Dunham@arm.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency 252611502SCurtis.Dunham@arm.comsystem.iocache.demand_avg_miss_latency::realview.ide 125646.511270 # average overall miss latency 252711502SCurtis.Dunham@arm.comsystem.iocache.demand_avg_miss_latency::total 125651.190223 # average overall miss latency 252811502SCurtis.Dunham@arm.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency 252911502SCurtis.Dunham@arm.comsystem.iocache.overall_avg_miss_latency::realview.ide 125646.511270 # average overall miss latency 253011502SCurtis.Dunham@arm.comsystem.iocache.overall_avg_miss_latency::total 125651.190223 # average overall miss latency 253111502SCurtis.Dunham@arm.comsystem.iocache.blocked_cycles::no_mshrs 33480 # number of cycles access was blocked 253210585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 253311502SCurtis.Dunham@arm.comsystem.iocache.blocked::no_mshrs 3531 # number of cycles access was blocked 253410585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 253511502SCurtis.Dunham@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 9.481733 # average number of cycles each access was blocked 253610585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 253711502SCurtis.Dunham@arm.comsystem.iocache.writebacks::writebacks 106695 # number of writebacks 253811502SCurtis.Dunham@arm.comsystem.iocache.writebacks::total 106695 # number of writebacks 253910585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 254011502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8886 # number of ReadReq MSHR misses 254111502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_misses::total 8923 # number of ReadReq MSHR misses 254210585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 254310585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 254411502SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 254511502SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 254610585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 254711502SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_misses::realview.ide 115614 # number of demand (read+write) MSHR misses 254811502SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_misses::total 115654 # number of demand (read+write) MSHR misses 254910585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 255011502SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_misses::realview.ide 115614 # number of overall MSHR misses 255111502SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_misses::total 115654 # number of overall MSHR misses 255211502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles 255311502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1224494518 # number of ReadReq MSHR miss cycles 255411502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 1227842518 # number of ReadReq MSHR miss cycles 255510892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 255610892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 255711502SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7512769435 # number of WriteLineReq MSHR miss cycles 255811502SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 7512769435 # number of WriteLineReq MSHR miss cycles 255911502SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles 256011502SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ide 8737263953 # number of demand (read+write) MSHR miss cycles 256111502SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_miss_latency::total 8740830953 # number of demand (read+write) MSHR miss cycles 256211502SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles 256311502SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ide 8737263953 # number of overall MSHR miss cycles 256411502SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_miss_latency::total 8740830953 # number of overall MSHR miss cycles 256510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 256610585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 256710585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 256810585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 256910585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 257011336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 257111336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 257210585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 257310585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 257410585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 257510585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 257610585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 257710585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 257811502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency 257911502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137800.418411 # average ReadReq mshr miss latency 258011502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 137604.227054 # average ReadReq mshr miss latency 258110892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 258210892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 258311502SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70391.738204 # average WriteLineReq mshr miss latency 258411502SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 70391.738204 # average WriteLineReq mshr miss latency 258511502SCurtis.Dunham@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency 258611502SCurtis.Dunham@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 75572.715701 # average overall mshr miss latency 258711502SCurtis.Dunham@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 75577.420176 # average overall mshr miss latency 258811502SCurtis.Dunham@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency 258911502SCurtis.Dunham@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 75572.715701 # average overall mshr miss latency 259011502SCurtis.Dunham@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 75577.420176 # average overall mshr miss latency 259111502SCurtis.Dunham@arm.comsystem.l2c.tags.replacements 1371243 # number of replacements 259211502SCurtis.Dunham@arm.comsystem.l2c.tags.tagsinuse 63411.869664 # Cycle average of tags in use 259311502SCurtis.Dunham@arm.comsystem.l2c.tags.total_refs 6460055 # Total number of references to valid blocks. 259411502SCurtis.Dunham@arm.comsystem.l2c.tags.sampled_refs 1430877 # Sample count of references to valid blocks. 259511502SCurtis.Dunham@arm.comsystem.l2c.tags.avg_refs 4.514752 # Average number of references to valid blocks. 259611502SCurtis.Dunham@arm.comsystem.l2c.tags.warmup_cycle 7876910500 # Cycle when the warmup percentage was hit. 259711502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::writebacks 21329.379338 # Average occupied blocks per requestor 259811502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 243.549056 # Average occupied blocks per requestor 259911502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 346.213430 # Average occupied blocks per requestor 260011502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 5332.164924 # Average occupied blocks per requestor 260111502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 9972.711960 # Average occupied blocks per requestor 260211502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14780.287325 # Average occupied blocks per requestor 260311502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 85.709675 # Average occupied blocks per requestor 260411502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 92.474711 # Average occupied blocks per requestor 260511502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 3611.694384 # Average occupied blocks per requestor 260611502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 3808.494767 # Average occupied blocks per requestor 260711502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3809.190093 # Average occupied blocks per requestor 260811502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::writebacks 0.325461 # Average percentage of cache occupancy 260911502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.003716 # Average percentage of cache occupancy 261011502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.005283 # Average percentage of cache occupancy 261111502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.081362 # Average percentage of cache occupancy 261211502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.152172 # Average percentage of cache occupancy 261311502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.225529 # Average percentage of cache occupancy 261411502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.001308 # Average percentage of cache occupancy 261511502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.001411 # Average percentage of cache occupancy 261611502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.055110 # Average percentage of cache occupancy 261711502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.058113 # Average percentage of cache occupancy 261811502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.058124 # Average percentage of cache occupancy 261911502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::total 0.967588 # Average percentage of cache occupancy 262011502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_blocks::1022 9222 # Occupied blocks per task id 262111502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 255 # Occupied blocks per task id 262211502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 50157 # Occupied blocks per task id 262311502SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id 262411502SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1022::2 98 # Occupied blocks per task id 262511502SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1022::3 408 # Occupied blocks per task id 262611502SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1022::4 8708 # Occupied blocks per task id 262711502SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 262811502SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 254 # Occupied blocks per task id 262911502SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id 263011502SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id 263111502SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 1961 # Occupied blocks per task id 263211502SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 5894 # Occupied blocks per task id 263311502SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 42105 # Occupied blocks per task id 263411502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_percent::1022 0.140717 # Percentage of cache occupancy per task id 263511502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.003891 # Percentage of cache occupancy per task id 263611502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.765335 # Percentage of cache occupancy per task id 263711502SCurtis.Dunham@arm.comsystem.l2c.tags.tag_accesses 79235647 # Number of tag accesses 263811502SCurtis.Dunham@arm.comsystem.l2c.tags.data_accesses 79235647 # Number of data accesses 263911502SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_hits::writebacks 2747527 # number of WritebackDirty hits 264011502SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_hits::total 2747527 # number of WritebackDirty hits 264111502SCurtis.Dunham@arm.comsystem.l2c.WritebackClean_hits::writebacks 1 # number of WritebackClean hits 264211502SCurtis.Dunham@arm.comsystem.l2c.WritebackClean_hits::total 1 # number of WritebackClean hits 264311502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 170119 # number of UpgradeReq hits 264411502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 132427 # number of UpgradeReq hits 264511502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::total 302546 # number of UpgradeReq hits 264611502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 41747 # number of SCUpgradeReq hits 264711502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 38038 # number of SCUpgradeReq hits 264811502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_hits::total 79785 # number of SCUpgradeReq hits 264911502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 52086 # number of ReadExReq hits 265011502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 59057 # number of ReadExReq hits 265111502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_hits::total 111143 # number of ReadExReq hits 265211502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6348 # number of ReadSharedReq hits 265311502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 3788 # number of ReadSharedReq hits 265411502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 658119 # number of ReadSharedReq hits 265511502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 620329 # number of ReadSharedReq hits 265611502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 316694 # number of ReadSharedReq hits 265711502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6918 # number of ReadSharedReq hits 265811502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 5196 # number of ReadSharedReq hits 265911502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 620556 # number of ReadSharedReq hits 266011502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 563518 # number of ReadSharedReq hits 266111502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 312616 # number of ReadSharedReq hits 266211502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::total 3114082 # number of ReadSharedReq hits 266311502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_hits::cpu0.data 130339 # number of InvalidateReq hits 266411502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_hits::cpu1.data 134354 # number of InvalidateReq hits 266511502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_hits::total 264693 # number of InvalidateReq hits 266611502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 6348 # number of demand (read+write) hits 266711502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 3788 # number of demand (read+write) hits 266811502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.inst 658119 # number of demand (read+write) hits 266911502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.data 672415 # number of demand (read+write) hits 267011502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.l2cache.prefetcher 316694 # number of demand (read+write) hits 267111502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 6918 # number of demand (read+write) hits 267211502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 5196 # number of demand (read+write) hits 267311502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.inst 620556 # number of demand (read+write) hits 267411502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.data 622575 # number of demand (read+write) hits 267511502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.l2cache.prefetcher 312616 # number of demand (read+write) hits 267611502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::total 3225225 # number of demand (read+write) hits 267711502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 6348 # number of overall hits 267811502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 3788 # number of overall hits 267911502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.inst 658119 # number of overall hits 268011502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.data 672415 # number of overall hits 268111502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.l2cache.prefetcher 316694 # number of overall hits 268211502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 6918 # number of overall hits 268311502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 5196 # number of overall hits 268411502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.inst 620556 # number of overall hits 268511502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.data 622575 # number of overall hits 268611502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.l2cache.prefetcher 312616 # number of overall hits 268711502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::total 3225225 # number of overall hits 268811502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 63896 # number of UpgradeReq misses 268911502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 60301 # number of UpgradeReq misses 269011502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::total 124197 # number of UpgradeReq misses 269111502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 12467 # number of SCUpgradeReq misses 269211502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 11210 # number of SCUpgradeReq misses 269311502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_misses::total 23677 # number of SCUpgradeReq misses 269411502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 80795 # number of ReadExReq misses 269511502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 51109 # number of ReadExReq misses 269611502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::total 131904 # number of ReadExReq misses 269711502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2056 # number of ReadSharedReq misses 269811502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 1934 # number of ReadSharedReq misses 269911502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 66055 # number of ReadSharedReq misses 270011502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 143274 # number of ReadSharedReq misses 270111502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 256484 # number of ReadSharedReq misses 270211502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1908 # number of ReadSharedReq misses 270311502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.itb.walker 1578 # number of ReadSharedReq misses 270411502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 52043 # number of ReadSharedReq misses 270511502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 103878 # number of ReadSharedReq misses 270611502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 163476 # number of ReadSharedReq misses 270711502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::total 792686 # number of ReadSharedReq misses 270811502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_misses::cpu0.data 465421 # number of InvalidateReq misses 270911502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_misses::cpu1.data 95414 # number of InvalidateReq misses 271011502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_misses::total 560835 # number of InvalidateReq misses 271111502SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 2056 # number of demand (read+write) misses 271211502SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 1934 # number of demand (read+write) misses 271311502SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.inst 66055 # number of demand (read+write) misses 271411502SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.data 224069 # number of demand (read+write) misses 271511502SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.l2cache.prefetcher 256484 # number of demand (read+write) misses 271611502SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 1908 # number of demand (read+write) misses 271711502SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.itb.walker 1578 # number of demand (read+write) misses 271811502SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.inst 52043 # number of demand (read+write) misses 271911502SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.data 154987 # number of demand (read+write) misses 272011502SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.l2cache.prefetcher 163476 # number of demand (read+write) misses 272111502SCurtis.Dunham@arm.comsystem.l2c.demand_misses::total 924590 # number of demand (read+write) misses 272211502SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 2056 # number of overall misses 272311502SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 1934 # number of overall misses 272411502SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.inst 66055 # number of overall misses 272511502SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.data 224069 # number of overall misses 272611502SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.l2cache.prefetcher 256484 # number of overall misses 272711502SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 1908 # number of overall misses 272811502SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.itb.walker 1578 # number of overall misses 272911502SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.inst 52043 # number of overall misses 273011502SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.data 154987 # number of overall misses 273111502SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.l2cache.prefetcher 163476 # number of overall misses 273211502SCurtis.Dunham@arm.comsystem.l2c.overall_misses::total 924590 # number of overall misses 273311502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu0.data 446027000 # number of UpgradeReq miss cycles 273411502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu1.data 423537000 # number of UpgradeReq miss cycles 273511502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_latency::total 869564000 # number of UpgradeReq miss cycles 273611502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu0.data 79642000 # number of SCUpgradeReq miss cycles 273711502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu1.data 73423000 # number of SCUpgradeReq miss cycles 273811502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_latency::total 153065000 # number of SCUpgradeReq miss cycles 273911502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_latency::cpu0.data 7209880999 # number of ReadExReq miss cycles 274011502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_latency::cpu1.data 4224259500 # number of ReadExReq miss cycles 274111502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_latency::total 11434140499 # number of ReadExReq miss cycles 274211502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 181168500 # number of ReadSharedReq miss cycles 274311502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 173308500 # number of ReadSharedReq miss cycles 274411502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.inst 5614644500 # number of ReadSharedReq miss cycles 274511502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.data 12851594000 # number of ReadSharedReq miss cycles 274611502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 32734884574 # number of ReadSharedReq miss cycles 274711502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 174846500 # number of ReadSharedReq miss cycles 274811502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 145724500 # number of ReadSharedReq miss cycles 274911502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.inst 4416688500 # number of ReadSharedReq miss cycles 275011502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.data 9519600500 # number of ReadSharedReq miss cycles 275111502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 19884865739 # number of ReadSharedReq miss cycles 275211502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::total 85697325813 # number of ReadSharedReq miss cycles 275311502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_latency::cpu0.data 65788000 # number of InvalidateReq miss cycles 275411502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_latency::cpu1.data 54373000 # number of InvalidateReq miss cycles 275511502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_latency::total 120161000 # number of InvalidateReq miss cycles 275611502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu0.dtb.walker 181168500 # number of demand (read+write) miss cycles 275711502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu0.itb.walker 173308500 # number of demand (read+write) miss cycles 275811502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu0.inst 5614644500 # number of demand (read+write) miss cycles 275911502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu0.data 20061474999 # number of demand (read+write) miss cycles 276011502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 32734884574 # number of demand (read+write) miss cycles 276111502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu1.dtb.walker 174846500 # number of demand (read+write) miss cycles 276211502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu1.itb.walker 145724500 # number of demand (read+write) miss cycles 276311502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu1.inst 4416688500 # number of demand (read+write) miss cycles 276411502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu1.data 13743860000 # number of demand (read+write) miss cycles 276511502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 19884865739 # number of demand (read+write) miss cycles 276611502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::total 97131466312 # number of demand (read+write) miss cycles 276711502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu0.dtb.walker 181168500 # number of overall miss cycles 276811502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu0.itb.walker 173308500 # number of overall miss cycles 276911502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu0.inst 5614644500 # number of overall miss cycles 277011502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu0.data 20061474999 # number of overall miss cycles 277111502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 32734884574 # number of overall miss cycles 277211502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu1.dtb.walker 174846500 # number of overall miss cycles 277311502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu1.itb.walker 145724500 # number of overall miss cycles 277411502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu1.inst 4416688500 # number of overall miss cycles 277511502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu1.data 13743860000 # number of overall miss cycles 277611502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 19884865739 # number of overall miss cycles 277711502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::total 97131466312 # number of overall miss cycles 277811502SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 2747527 # number of WritebackDirty accesses(hits+misses) 277911502SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_accesses::total 2747527 # number of WritebackDirty accesses(hits+misses) 278011502SCurtis.Dunham@arm.comsystem.l2c.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) 278111502SCurtis.Dunham@arm.comsystem.l2c.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) 278211502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 234015 # number of UpgradeReq accesses(hits+misses) 278311502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 192728 # number of UpgradeReq accesses(hits+misses) 278411502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::total 426743 # number of UpgradeReq accesses(hits+misses) 278511502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 54214 # number of SCUpgradeReq accesses(hits+misses) 278611502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 49248 # number of SCUpgradeReq accesses(hits+misses) 278711502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_accesses::total 103462 # number of SCUpgradeReq accesses(hits+misses) 278811502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 132881 # number of ReadExReq accesses(hits+misses) 278911502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 110166 # number of ReadExReq accesses(hits+misses) 279011502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::total 243047 # number of ReadExReq accesses(hits+misses) 279111502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8404 # number of ReadSharedReq accesses(hits+misses) 279211502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5722 # number of ReadSharedReq accesses(hits+misses) 279311502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 724174 # number of ReadSharedReq accesses(hits+misses) 279411502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 763603 # number of ReadSharedReq accesses(hits+misses) 279511502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 573178 # number of ReadSharedReq accesses(hits+misses) 279611502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8826 # number of ReadSharedReq accesses(hits+misses) 279711502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6774 # number of ReadSharedReq accesses(hits+misses) 279811502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 672599 # number of ReadSharedReq accesses(hits+misses) 279911502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 667396 # number of ReadSharedReq accesses(hits+misses) 280011502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 476092 # number of ReadSharedReq accesses(hits+misses) 280111502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::total 3906768 # number of ReadSharedReq accesses(hits+misses) 280211502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_accesses::cpu0.data 595760 # number of InvalidateReq accesses(hits+misses) 280311502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_accesses::cpu1.data 229768 # number of InvalidateReq accesses(hits+misses) 280411502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_accesses::total 825528 # number of InvalidateReq accesses(hits+misses) 280511502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 8404 # number of demand (read+write) accesses 280611502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 5722 # number of demand (read+write) accesses 280711502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.inst 724174 # number of demand (read+write) accesses 280811502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.data 896484 # number of demand (read+write) accesses 280911502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.l2cache.prefetcher 573178 # number of demand (read+write) accesses 281011502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 8826 # number of demand (read+write) accesses 281111502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 6774 # number of demand (read+write) accesses 281211502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.inst 672599 # number of demand (read+write) accesses 281311502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.data 777562 # number of demand (read+write) accesses 281411502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.l2cache.prefetcher 476092 # number of demand (read+write) accesses 281511502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::total 4149815 # number of demand (read+write) accesses 281611502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 8404 # number of overall (read+write) accesses 281711502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 5722 # number of overall (read+write) accesses 281811502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.inst 724174 # number of overall (read+write) accesses 281911502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.data 896484 # number of overall (read+write) accesses 282011502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.l2cache.prefetcher 573178 # number of overall (read+write) accesses 282111502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 8826 # number of overall (read+write) accesses 282211502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 6774 # number of overall (read+write) accesses 282311502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.inst 672599 # number of overall (read+write) accesses 282411502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.data 777562 # number of overall (read+write) accesses 282511502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.l2cache.prefetcher 476092 # number of overall (read+write) accesses 282611502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::total 4149815 # number of overall (read+write) accesses 282711502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.273042 # miss rate for UpgradeReq accesses 282811502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.312881 # miss rate for UpgradeReq accesses 282911502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.291035 # miss rate for UpgradeReq accesses 283011502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.229959 # miss rate for SCUpgradeReq accesses 283111502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.227623 # miss rate for SCUpgradeReq accesses 283211502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.228847 # miss rate for SCUpgradeReq accesses 283311502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.608025 # miss rate for ReadExReq accesses 283411502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.463927 # miss rate for ReadExReq accesses 283511502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.542710 # miss rate for ReadExReq accesses 283611502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.244645 # miss rate for ReadSharedReq accesses 283711502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.337994 # miss rate for ReadSharedReq accesses 283811502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.091214 # miss rate for ReadSharedReq accesses 283911502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.187629 # miss rate for ReadSharedReq accesses 284011502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.447477 # miss rate for ReadSharedReq accesses 284111502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.216179 # miss rate for ReadSharedReq accesses 284211502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.232950 # miss rate for ReadSharedReq accesses 284311502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.077376 # miss rate for ReadSharedReq accesses 284411502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.155647 # miss rate for ReadSharedReq accesses 284511502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.343371 # miss rate for ReadSharedReq accesses 284611502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.202901 # miss rate for ReadSharedReq accesses 284711502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu0.data 0.781222 # miss rate for InvalidateReq accesses 284811502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu1.data 0.415262 # miss rate for InvalidateReq accesses 284911502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_rate::total 0.679365 # miss rate for InvalidateReq accesses 285011502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.244645 # miss rate for demand accesses 285111502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.337994 # miss rate for demand accesses 285211502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.091214 # miss rate for demand accesses 285311502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.249942 # miss rate for demand accesses 285411502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.447477 # miss rate for demand accesses 285511502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.216179 # miss rate for demand accesses 285611502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.232950 # miss rate for demand accesses 285711502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.077376 # miss rate for demand accesses 285811502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.199324 # miss rate for demand accesses 285911502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.343371 # miss rate for demand accesses 286011502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::total 0.222803 # miss rate for demand accesses 286111502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.244645 # miss rate for overall accesses 286211502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.337994 # miss rate for overall accesses 286311502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.091214 # miss rate for overall accesses 286411502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.249942 # miss rate for overall accesses 286511502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.447477 # miss rate for overall accesses 286611502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.216179 # miss rate for overall accesses 286711502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.232950 # miss rate for overall accesses 286811502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.077376 # miss rate for overall accesses 286911502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.199324 # miss rate for overall accesses 287011502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.343371 # miss rate for overall accesses 287111502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::total 0.222803 # miss rate for overall accesses 287211502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6980.515212 # average UpgradeReq miss latency 287311502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7023.714366 # average UpgradeReq miss latency 287411502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::total 7001.489569 # average UpgradeReq miss latency 287511502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6388.224914 # average SCUpgradeReq miss latency 287611502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6549.776985 # average SCUpgradeReq miss latency 287711502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::total 6464.712590 # average SCUpgradeReq miss latency 287811502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu0.data 89236.722557 # average ReadExReq miss latency 287911502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu1.data 82651.969320 # average ReadExReq miss latency 288011502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_miss_latency::total 86685.320377 # average ReadExReq miss latency 288111502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 88116.974708 # average ReadSharedReq miss latency 288211502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 89611.427094 # average ReadSharedReq miss latency 288311502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 84999.538264 # average ReadSharedReq miss latency 288411502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 89699.415107 # average ReadSharedReq miss latency 288511502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 127629.343639 # average ReadSharedReq miss latency 288611502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 91638.626834 # average ReadSharedReq miss latency 288711502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 92347.591888 # average ReadSharedReq miss latency 288811502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 84866.139538 # average ReadSharedReq miss latency 288911502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 91642.123453 # average ReadSharedReq miss latency 289011502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 121637.829033 # average ReadSharedReq miss latency 289111502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::total 108110.053430 # average ReadSharedReq miss latency 289211502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_avg_miss_latency::cpu0.data 141.351594 # average InvalidateReq miss latency 289311502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_avg_miss_latency::cpu1.data 569.863961 # average InvalidateReq miss latency 289411502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_avg_miss_latency::total 214.253747 # average InvalidateReq miss latency 289511502SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.dtb.walker 88116.974708 # average overall miss latency 289611502SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.itb.walker 89611.427094 # average overall miss latency 289711502SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.inst 84999.538264 # average overall miss latency 289811502SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.data 89532.577014 # average overall miss latency 289911502SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 127629.343639 # average overall miss latency 290011502SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.dtb.walker 91638.626834 # average overall miss latency 290111502SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.itb.walker 92347.591888 # average overall miss latency 290211502SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.inst 84866.139538 # average overall miss latency 290311502SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.data 88677.501984 # average overall miss latency 290411502SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 121637.829033 # average overall miss latency 290511502SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::total 105053.554886 # average overall miss latency 290611502SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.dtb.walker 88116.974708 # average overall miss latency 290711502SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.itb.walker 89611.427094 # average overall miss latency 290811502SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.inst 84999.538264 # average overall miss latency 290911502SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.data 89532.577014 # average overall miss latency 291011502SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 127629.343639 # average overall miss latency 291111502SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.dtb.walker 91638.626834 # average overall miss latency 291211502SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.itb.walker 92347.591888 # average overall miss latency 291311502SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.inst 84866.139538 # average overall miss latency 291411502SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.data 88677.501984 # average overall miss latency 291511502SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 121637.829033 # average overall miss latency 291611502SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::total 105053.554886 # average overall miss latency 291711502SCurtis.Dunham@arm.comsystem.l2c.blocked_cycles::no_mshrs 547 # number of cycles access was blocked 291810515SAli.Saidi@ARM.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 291911502SCurtis.Dunham@arm.comsystem.l2c.blocked::no_mshrs 8 # number of cycles access was blocked 292010515SAli.Saidi@ARM.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 292111502SCurtis.Dunham@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs 68.375000 # average number of cycles each access was blocked 292210515SAli.Saidi@ARM.comsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 292311502SCurtis.Dunham@arm.comsystem.l2c.writebacks::writebacks 1075082 # number of writebacks 292411502SCurtis.Dunham@arm.comsystem.l2c.writebacks::total 1075082 # number of writebacks 292511502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.inst 93 # number of ReadSharedReq MSHR hits 292611502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.data 13 # number of ReadSharedReq MSHR hits 292711502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.inst 87 # number of ReadSharedReq MSHR hits 292811502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.data 17 # number of ReadSharedReq MSHR hits 292911502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_hits::total 210 # number of ReadSharedReq MSHR hits 293011502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::cpu0.inst 93 # number of demand (read+write) MSHR hits 293111502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::cpu0.data 13 # number of demand (read+write) MSHR hits 293211502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::cpu1.inst 87 # number of demand (read+write) MSHR hits 293311502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::cpu1.data 17 # number of demand (read+write) MSHR hits 293411502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::total 210 # number of demand (read+write) MSHR hits 293511502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::cpu0.inst 93 # number of overall MSHR hits 293611502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::cpu0.data 13 # number of overall MSHR hits 293711502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::cpu1.inst 87 # number of overall MSHR hits 293811502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::cpu1.data 17 # number of overall MSHR hits 293911502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::total 210 # number of overall MSHR hits 294011502SCurtis.Dunham@arm.comsystem.l2c.CleanEvict_mshr_misses::writebacks 54168 # number of CleanEvict MSHR misses 294111502SCurtis.Dunham@arm.comsystem.l2c.CleanEvict_mshr_misses::total 54168 # number of CleanEvict MSHR misses 294211502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu0.data 63896 # number of UpgradeReq MSHR misses 294311502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu1.data 60301 # number of UpgradeReq MSHR misses 294411502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_misses::total 124197 # number of UpgradeReq MSHR misses 294511502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu0.data 12467 # number of SCUpgradeReq MSHR misses 294611502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11210 # number of SCUpgradeReq MSHR misses 294711502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::total 23677 # number of SCUpgradeReq MSHR misses 294811502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu0.data 80795 # number of ReadExReq MSHR misses 294911502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu1.data 51109 # number of ReadExReq MSHR misses 295011502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_misses::total 131904 # number of ReadExReq MSHR misses 295111502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 2056 # number of ReadSharedReq MSHR misses 295211502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1934 # number of ReadSharedReq MSHR misses 295311502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.inst 65962 # number of ReadSharedReq MSHR misses 295411502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.data 143261 # number of ReadSharedReq MSHR misses 295511502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 256484 # number of ReadSharedReq MSHR misses 295611502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1908 # number of ReadSharedReq MSHR misses 295711502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1578 # number of ReadSharedReq MSHR misses 295811502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.inst 51956 # number of ReadSharedReq MSHR misses 295911502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.data 103861 # number of ReadSharedReq MSHR misses 296011502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 163476 # number of ReadSharedReq MSHR misses 296111502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::total 792476 # number of ReadSharedReq MSHR misses 296211502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_misses::cpu0.data 465421 # number of InvalidateReq MSHR misses 296311502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_misses::cpu1.data 95414 # number of InvalidateReq MSHR misses 296411502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_misses::total 560835 # number of InvalidateReq MSHR misses 296511502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu0.dtb.walker 2056 # number of demand (read+write) MSHR misses 296611502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu0.itb.walker 1934 # number of demand (read+write) MSHR misses 296711502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu0.inst 65962 # number of demand (read+write) MSHR misses 296811502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu0.data 224056 # number of demand (read+write) MSHR misses 296911502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 256484 # number of demand (read+write) MSHR misses 297011502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu1.dtb.walker 1908 # number of demand (read+write) MSHR misses 297111502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu1.itb.walker 1578 # number of demand (read+write) MSHR misses 297211502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu1.inst 51956 # number of demand (read+write) MSHR misses 297311502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu1.data 154970 # number of demand (read+write) MSHR misses 297411502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 163476 # number of demand (read+write) MSHR misses 297511502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::total 924380 # number of demand (read+write) MSHR misses 297611502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu0.dtb.walker 2056 # number of overall MSHR misses 297711502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu0.itb.walker 1934 # number of overall MSHR misses 297811502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu0.inst 65962 # number of overall MSHR misses 297911502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu0.data 224056 # number of overall MSHR misses 298011502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 256484 # number of overall MSHR misses 298111502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu1.dtb.walker 1908 # number of overall MSHR misses 298211502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu1.itb.walker 1578 # number of overall MSHR misses 298311502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu1.inst 51956 # number of overall MSHR misses 298411502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu1.data 154970 # number of overall MSHR misses 298511502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 163476 # number of overall MSHR misses 298611502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::total 924380 # number of overall MSHR misses 298711502SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu0.inst 52299 # number of ReadReq MSHR uncacheable 298811502SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu0.data 31702 # number of ReadReq MSHR uncacheable 298911353Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable 299011502SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu1.data 6939 # number of ReadReq MSHR uncacheable 299111502SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable::total 91033 # number of ReadReq MSHR uncacheable 299211502SCurtis.Dunham@arm.comsystem.l2c.WriteReq_mshr_uncacheable::cpu0.data 31225 # number of WriteReq MSHR uncacheable 299311502SCurtis.Dunham@arm.comsystem.l2c.WriteReq_mshr_uncacheable::cpu1.data 7280 # number of WriteReq MSHR uncacheable 299411502SCurtis.Dunham@arm.comsystem.l2c.WriteReq_mshr_uncacheable::total 38505 # number of WriteReq MSHR uncacheable 299511502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu0.inst 52299 # number of overall MSHR uncacheable misses 299611502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu0.data 62927 # number of overall MSHR uncacheable misses 299711353Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses 299811502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu1.data 14219 # number of overall MSHR uncacheable misses 299911502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_misses::total 129538 # number of overall MSHR uncacheable misses 300011502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1380806993 # number of UpgradeReq MSHR miss cycles 300111502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 1305380495 # number of UpgradeReq MSHR miss cycles 300211502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::total 2686187488 # number of UpgradeReq MSHR miss cycles 300311502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 306900998 # number of SCUpgradeReq MSHR miss cycles 300411502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 275849499 # number of SCUpgradeReq MSHR miss cycles 300511502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::total 582750497 # number of SCUpgradeReq MSHR miss cycles 300611502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6401900063 # number of ReadExReq MSHR miss cycles 300711502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3713131578 # number of ReadExReq MSHR miss cycles 300811502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::total 10115031641 # number of ReadExReq MSHR miss cycles 300911502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 160608500 # number of ReadSharedReq MSHR miss cycles 301011502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 153968500 # number of ReadSharedReq MSHR miss cycles 301111502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 4948095074 # number of ReadSharedReq MSHR miss cycles 301211502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 11417870701 # number of ReadSharedReq MSHR miss cycles 301311502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 30169861471 # number of ReadSharedReq MSHR miss cycles 301411502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 155763506 # number of ReadSharedReq MSHR miss cycles 301511502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 129943003 # number of ReadSharedReq MSHR miss cycles 301611502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 3891093570 # number of ReadSharedReq MSHR miss cycles 301711502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 8479584227 # number of ReadSharedReq MSHR miss cycles 301811502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 18249884712 # number of ReadSharedReq MSHR miss cycles 301911502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::total 77756673264 # number of ReadSharedReq MSHR miss cycles 302011502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 9735980999 # number of InvalidateReq MSHR miss cycles 302111502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1980875000 # number of InvalidateReq MSHR miss cycles 302211502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_miss_latency::total 11716855999 # number of InvalidateReq MSHR miss cycles 302311502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 160608500 # number of demand (read+write) MSHR miss cycles 302411502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.itb.walker 153968500 # number of demand (read+write) MSHR miss cycles 302511502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.inst 4948095074 # number of demand (read+write) MSHR miss cycles 302611502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.data 17819770764 # number of demand (read+write) MSHR miss cycles 302711502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 30169861471 # number of demand (read+write) MSHR miss cycles 302811502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 155763506 # number of demand (read+write) MSHR miss cycles 302911502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.itb.walker 129943003 # number of demand (read+write) MSHR miss cycles 303011502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.inst 3891093570 # number of demand (read+write) MSHR miss cycles 303111502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.data 12192715805 # number of demand (read+write) MSHR miss cycles 303211502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 18249884712 # number of demand (read+write) MSHR miss cycles 303311502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::total 87871704905 # number of demand (read+write) MSHR miss cycles 303411502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 160608500 # number of overall MSHR miss cycles 303511502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.itb.walker 153968500 # number of overall MSHR miss cycles 303611502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.inst 4948095074 # number of overall MSHR miss cycles 303711502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.data 17819770764 # number of overall MSHR miss cycles 303811502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 30169861471 # number of overall MSHR miss cycles 303911502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 155763506 # number of overall MSHR miss cycles 304011502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.itb.walker 129943003 # number of overall MSHR miss cycles 304111502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.inst 3891093570 # number of overall MSHR miss cycles 304211502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.data 12192715805 # number of overall MSHR miss cycles 304311502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 18249884712 # number of overall MSHR miss cycles 304411502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::total 87871704905 # number of overall MSHR miss cycles 304511502SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3320524500 # number of ReadReq MSHR uncacheable cycles 304611502SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5312322505 # number of ReadReq MSHR uncacheable cycles 304711502SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5752000 # number of ReadReq MSHR uncacheable cycles 304811502SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 656593502 # number of ReadReq MSHR uncacheable cycles 304911502SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::total 9295192507 # number of ReadReq MSHR uncacheable cycles 305011502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3320524500 # number of overall MSHR uncacheable cycles 305111502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.data 5312322505 # number of overall MSHR uncacheable cycles 305211502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5752000 # number of overall MSHR uncacheable cycles 305311502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.data 656593502 # number of overall MSHR uncacheable cycles 305411502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_latency::total 9295192507 # number of overall MSHR uncacheable cycles 305510892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 305610892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 305711502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.273042 # mshr miss rate for UpgradeReq accesses 305811502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.312881 # mshr miss rate for UpgradeReq accesses 305911502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::total 0.291035 # mshr miss rate for UpgradeReq accesses 306011502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.229959 # mshr miss rate for SCUpgradeReq accesses 306111502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.227623 # mshr miss rate for SCUpgradeReq accesses 306211502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::total 0.228847 # mshr miss rate for SCUpgradeReq accesses 306311502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.608025 # mshr miss rate for ReadExReq accesses 306411502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.463927 # mshr miss rate for ReadExReq accesses 306511502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::total 0.542710 # mshr miss rate for ReadExReq accesses 306611502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.244645 # mshr miss rate for ReadSharedReq accesses 306711502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.337994 # mshr miss rate for ReadSharedReq accesses 306811502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.091086 # mshr miss rate for ReadSharedReq accesses 306911502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.187612 # mshr miss rate for ReadSharedReq accesses 307011502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447477 # mshr miss rate for ReadSharedReq accesses 307111502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.216179 # mshr miss rate for ReadSharedReq accesses 307211502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.232950 # mshr miss rate for ReadSharedReq accesses 307311502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.077247 # mshr miss rate for ReadSharedReq accesses 307411502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.155621 # mshr miss rate for ReadSharedReq accesses 307511502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.343371 # mshr miss rate for ReadSharedReq accesses 307611502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::total 0.202847 # mshr miss rate for ReadSharedReq accesses 307711502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.781222 # mshr miss rate for InvalidateReq accesses 307811502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.415262 # mshr miss rate for InvalidateReq accesses 307911502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::total 0.679365 # mshr miss rate for InvalidateReq accesses 308011502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.244645 # mshr miss rate for demand accesses 308111502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.337994 # mshr miss rate for demand accesses 308211502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.091086 # mshr miss rate for demand accesses 308311502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.data 0.249927 # mshr miss rate for demand accesses 308411502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447477 # mshr miss rate for demand accesses 308511502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.216179 # mshr miss rate for demand accesses 308611502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.232950 # mshr miss rate for demand accesses 308711502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.077247 # mshr miss rate for demand accesses 308811502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.data 0.199302 # mshr miss rate for demand accesses 308911502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.343371 # mshr miss rate for demand accesses 309011502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::total 0.222752 # mshr miss rate for demand accesses 309111502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.244645 # mshr miss rate for overall accesses 309211502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.337994 # mshr miss rate for overall accesses 309311502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.091086 # mshr miss rate for overall accesses 309411502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.data 0.249927 # mshr miss rate for overall accesses 309511502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447477 # mshr miss rate for overall accesses 309611502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.216179 # mshr miss rate for overall accesses 309711502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.232950 # mshr miss rate for overall accesses 309811502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.077247 # mshr miss rate for overall accesses 309911502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.data 0.199302 # mshr miss rate for overall accesses 310011502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.343371 # mshr miss rate for overall accesses 310111502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::total 0.222752 # mshr miss rate for overall accesses 310211502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21610.225883 # average UpgradeReq mshr miss latency 310311502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21647.742077 # average UpgradeReq mshr miss latency 310411502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 21628.441009 # average UpgradeReq mshr miss latency 310511502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24617.068902 # average SCUpgradeReq mshr miss latency 310611502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24607.448617 # average SCUpgradeReq mshr miss latency 310711502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24612.514128 # average SCUpgradeReq mshr miss latency 310811502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79236.339662 # average ReadExReq mshr miss latency 310911502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72651.227338 # average ReadExReq mshr miss latency 311011502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 76684.798346 # average ReadExReq mshr miss latency 311111502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 78116.974708 # average ReadSharedReq mshr miss latency 311211502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 79611.427094 # average ReadSharedReq mshr miss latency 311311502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75014.327552 # average ReadSharedReq mshr miss latency 311411502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 79699.783619 # average ReadSharedReq mshr miss latency 311511502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117628.629743 # average ReadSharedReq mshr miss latency 311611502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 81637.057652 # average ReadSharedReq mshr miss latency 311711502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 82346.643219 # average ReadSharedReq mshr miss latency 311811502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 74892.092732 # average ReadSharedReq mshr miss latency 311911502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 81643.583511 # average ReadSharedReq mshr miss latency 312011502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111636.476987 # average ReadSharedReq mshr miss latency 312111502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::total 98118.647459 # average ReadSharedReq mshr miss latency 312211502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20918.654291 # average InvalidateReq mshr miss latency 312311502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20760.842224 # average InvalidateReq mshr miss latency 312411502SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::total 20891.805966 # average InvalidateReq mshr miss latency 312511502SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78116.974708 # average overall mshr miss latency 312611502SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79611.427094 # average overall mshr miss latency 312711502SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75014.327552 # average overall mshr miss latency 312811502SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 79532.664887 # average overall mshr miss latency 312911502SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117628.629743 # average overall mshr miss latency 313011502SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 81637.057652 # average overall mshr miss latency 313111502SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 82346.643219 # average overall mshr miss latency 313211502SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74892.092732 # average overall mshr miss latency 313311502SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 78677.910596 # average overall mshr miss latency 313411502SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111636.476987 # average overall mshr miss latency 313511502SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 95060.153730 # average overall mshr miss latency 313611502SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78116.974708 # average overall mshr miss latency 313711502SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79611.427094 # average overall mshr miss latency 313811502SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75014.327552 # average overall mshr miss latency 313911502SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 79532.664887 # average overall mshr miss latency 314011502SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117628.629743 # average overall mshr miss latency 314111502SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 81637.057652 # average overall mshr miss latency 314211502SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 82346.643219 # average overall mshr miss latency 314311502SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74892.092732 # average overall mshr miss latency 314411502SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 78677.910596 # average overall mshr miss latency 314511502SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111636.476987 # average overall mshr miss latency 314611502SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 95060.153730 # average overall mshr miss latency 314711502SCurtis.Dunham@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63491.166179 # average ReadReq mshr uncacheable latency 314811502SCurtis.Dunham@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167570.579301 # average ReadReq mshr uncacheable latency 314911502SCurtis.Dunham@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 61849.462366 # average ReadReq mshr uncacheable latency 315011502SCurtis.Dunham@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 94623.649229 # average ReadReq mshr uncacheable latency 315111502SCurtis.Dunham@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total 102107.944449 # average ReadReq mshr uncacheable latency 315211502SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63491.166179 # average overall mshr uncacheable latency 315311502SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 84420.399908 # average overall mshr uncacheable latency 315411502SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 61849.462366 # average overall mshr uncacheable latency 315511502SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 46177.192630 # average overall mshr uncacheable latency 315611502SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::total 71756.492357 # average overall mshr uncacheable latency 315711502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_requests 3789204 # Total number of requests made to the snoop filter. 315811502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_requests 2296931 # Number of requests hitting in the snoop filter with a single holder of the requested data. 315911502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_requests 2908 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 316011502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 316111502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 316211502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 316311502SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadReq 91033 # Transaction distribution 316411502SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 892432 # Transaction distribution 316511502SCurtis.Dunham@arm.comsystem.membus.trans_dist::WriteReq 38505 # Transaction distribution 316611502SCurtis.Dunham@arm.comsystem.membus.trans_dist::WriteResp 38505 # Transaction distribution 316711502SCurtis.Dunham@arm.comsystem.membus.trans_dist::WritebackDirty 1181777 # Transaction distribution 316811502SCurtis.Dunham@arm.comsystem.membus.trans_dist::CleanEvict 252869 # Transaction distribution 316911502SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeReq 437143 # Transaction distribution 317011502SCurtis.Dunham@arm.comsystem.membus.trans_dist::SCUpgradeReq 308404 # Transaction distribution 317111441Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 22 # Transaction distribution 317211441Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution 317311502SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExReq 143945 # Transaction distribution 317411502SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExResp 126263 # Transaction distribution 317511502SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 801399 # Transaction distribution 317611502SCurtis.Dunham@arm.comsystem.membus.trans_dist::InvalidateReq 663637 # Transaction distribution 317711502SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122598 # Packet count per connected master and slave (bytes) 317810585Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) 317911502SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26474 # Packet count per connected master and slave (bytes) 318011502SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4585882 # Packet count per connected master and slave (bytes) 318111502SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 4735006 # Packet count per connected master and slave (bytes) 318211502SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238206 # Packet count per connected master and slave (bytes) 318311502SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 238206 # Packet count per connected master and slave (bytes) 318411502SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 4973212 # Packet count per connected master and slave (bytes) 318511502SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155705 # Cumulative packet size per connected master and slave (bytes) 318610585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) 318711502SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52948 # Cumulative packet size per connected master and slave (bytes) 318811502SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 130931136 # Cumulative packet size per connected master and slave (bytes) 318911502SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 131141113 # Cumulative packet size per connected master and slave (bytes) 319011502SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7272704 # Cumulative packet size per connected master and slave (bytes) 319111502SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7272704 # Cumulative packet size per connected master and slave (bytes) 319211502SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 138413817 # Cumulative packet size per connected master and slave (bytes) 319311502SCurtis.Dunham@arm.comsystem.membus.snoops 608511 # Total snoops (count) 319411502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 2484071 # Request fanout histogram 319511502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0.012278 # Request fanout histogram 319611502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0.110125 # Request fanout histogram 319710585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 319811502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 2453571 98.77% 98.77% # Request fanout histogram 319911502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 30500 1.23% 100.00% # Request fanout histogram 320010585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 320110585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 320211502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 320310585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 320411502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 2484071 # Request fanout histogram 320511502SCurtis.Dunham@arm.comsystem.membus.reqLayer0.occupancy 105594995 # Layer occupancy (ticks) 320610585Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 320710892Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks) 320810585Sandreas.hansson@arm.comsystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 320911502SCurtis.Dunham@arm.comsystem.membus.reqLayer2.occupancy 22316500 # Layer occupancy (ticks) 321010585Sandreas.hansson@arm.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 321111502SCurtis.Dunham@arm.comsystem.membus.reqLayer5.occupancy 8304045809 # Layer occupancy (ticks) 321210585Sandreas.hansson@arm.comsystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 321311502SCurtis.Dunham@arm.comsystem.membus.respLayer2.occupancy 5231778477 # Layer occupancy (ticks) 321410585Sandreas.hansson@arm.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 321511502SCurtis.Dunham@arm.comsystem.membus.respLayer3.occupancy 45499333 # Layer occupancy (ticks) 321610585Sandreas.hansson@arm.comsystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 321711239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 321811239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 321911239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 322011239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 322111239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 322211239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 322310515SAli.Saidi@ARM.comsystem.realview.ethernet.txBytes 966 # Bytes Transmitted 322410515SAli.Saidi@ARM.comsystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 322510515SAli.Saidi@ARM.comsystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 322610515SAli.Saidi@ARM.comsystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 322710515SAli.Saidi@ARM.comsystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 322810515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 322910515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 323010515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 323110515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 323211201Sandreas.hansson@arm.comsystem.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 323310515SAli.Saidi@ARM.comsystem.realview.ethernet.totPackets 3 # Total Packets 323410515SAli.Saidi@ARM.comsystem.realview.ethernet.totBytes 966 # Total Bytes 323510515SAli.Saidi@ARM.comsystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 323611201Sandreas.hansson@arm.comsystem.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 323710515SAli.Saidi@ARM.comsystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 323810515SAli.Saidi@ARM.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 323910515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 324010515SAli.Saidi@ARM.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 324110515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 324210515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 324310515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 324410515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 324510515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 324610515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 324710515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 324810515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 324910515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 325010515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 325110515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 325210515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 325310515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 325410515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 325510515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 325610515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 325710515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 325810515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 325910515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 326010515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 326110515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 326210515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 326310515SAli.Saidi@ARM.comsystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 326410515SAli.Saidi@ARM.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 326511239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 326611239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 326711239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 326811239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 326911502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.tot_requests 12326432 # Total number of requests made to the snoop filter. 327011502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 6670511 # Number of requests hitting in the snoop filter with a single holder of the requested data. 327111502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 2086069 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 327211502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 130580 # Total number of snoops made to the snoop filter. 327311502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 118652 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 327411502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 11928 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 327511502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadReq 91035 # Transaction distribution 327611502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadResp 4782322 # Transaction distribution 327711502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WriteReq 38505 # Transaction distribution 327811502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WriteResp 38505 # Transaction distribution 327911502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 3822609 # Transaction distribution 328011502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution 328111502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::CleanEvict 2941580 # Transaction distribution 328211502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 730122 # Transaction distribution 328311502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 388189 # Transaction distribution 328411502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 1118311 # Transaction distribution 328511502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::SCUpgradeFailReq 111 # Transaction distribution 328611502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution 328711502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadExReq 299700 # Transaction distribution 328811502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadExResp 299700 # Transaction distribution 328911502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 4691812 # Transaction distribution 329011502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::InvalidateReq 853093 # Transaction distribution 329111502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::InvalidateResp 825528 # Transaction distribution 329211502SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10130133 # Packet count per connected master and slave (bytes) 329311502SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7962376 # Packet count per connected master and slave (bytes) 329411502SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count::total 18092509 # Packet count per connected master and slave (bytes) 329511502SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 250257116 # Cumulative packet size per connected master and slave (bytes) 329611502SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 194861853 # Cumulative packet size per connected master and slave (bytes) 329711502SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size::total 445118969 # Cumulative packet size per connected master and slave (bytes) 329811502SCurtis.Dunham@arm.comsystem.toL2Bus.snoops 2830390 # Total snoops (count) 329911502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::samples 8463866 # Request fanout histogram 330011502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::mean 0.368667 # Request fanout histogram 330111502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.485356 # Request fanout histogram 330210515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 330311502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::0 5355444 63.27% 63.27% # Request fanout histogram 330411502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::1 3096494 36.58% 99.86% # Request fanout histogram 330511502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::2 11928 0.14% 100.00% # Request fanout histogram 330610515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 330711138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 330810515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 330911502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::total 8463866 # Request fanout histogram 331011502SCurtis.Dunham@arm.comsystem.toL2Bus.reqLayer0.occupancy 9400124055 # Layer occupancy (ticks) 331110515SAli.Saidi@ARM.comsystem.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 331211502SCurtis.Dunham@arm.comsystem.toL2Bus.snoopLayer0.occupancy 2566916 # Layer occupancy (ticks) 331310515SAli.Saidi@ARM.comsystem.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 331411502SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer0.occupancy 4651836575 # Layer occupancy (ticks) 331510515SAli.Saidi@ARM.comsystem.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 331611502SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer1.occupancy 3960751843 # Layer occupancy (ticks) 331710515SAli.Saidi@ARM.comsystem.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 331810515SAli.Saidi@ARM.com 331910515SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 3320