stats.txt revision 11374
110515SAli.Saidi@ARM.com 210515SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 311374Ssteve.reinhardt@amd.comsim_seconds 47.454492 # Number of seconds simulated 411374Ssteve.reinhardt@amd.comsim_ticks 47454492026000 # Number of ticks simulated 511374Ssteve.reinhardt@amd.comfinal_tick 47454492026000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 711374Ssteve.reinhardt@amd.comhost_inst_rate 169815 # Simulator instruction rate (inst/s) 811374Ssteve.reinhardt@amd.comhost_op_rate 199687 # Simulator op (including micro ops) rate (op/s) 911374Ssteve.reinhardt@amd.comhost_tick_rate 8468561033 # Simulator tick rate (ticks/s) 1011374Ssteve.reinhardt@amd.comhost_mem_usage 764912 # Number of bytes of host memory used 1111374Ssteve.reinhardt@amd.comhost_seconds 5603.61 # Real time elapsed on the host 1211374Ssteve.reinhardt@amd.comsim_insts 951575519 # Number of instructions simulated 1311374Ssteve.reinhardt@amd.comsim_ops 1118968402 # Number of ops (including micro ops) simulated 1410515SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611374Ssteve.reinhardt@amd.comsystem.physmem.bytes_read::cpu0.dtb.walker 233088 # Number of bytes read from this memory 1711374Ssteve.reinhardt@amd.comsystem.physmem.bytes_read::cpu0.itb.walker 210624 # Number of bytes read from this memory 1811374Ssteve.reinhardt@amd.comsystem.physmem.bytes_read::cpu0.inst 7916672 # Number of bytes read from this memory 1911374Ssteve.reinhardt@amd.comsystem.physmem.bytes_read::cpu0.data 17537736 # Number of bytes read from this memory 2011374Ssteve.reinhardt@amd.comsystem.physmem.bytes_read::cpu0.l2cache.prefetcher 18153728 # Number of bytes read from this memory 2111374Ssteve.reinhardt@amd.comsystem.physmem.bytes_read::cpu1.dtb.walker 166400 # Number of bytes read from this memory 2211374Ssteve.reinhardt@amd.comsystem.physmem.bytes_read::cpu1.itb.walker 132160 # Number of bytes read from this memory 2311374Ssteve.reinhardt@amd.comsystem.physmem.bytes_read::cpu1.inst 3894272 # Number of bytes read from this memory 2411374Ssteve.reinhardt@amd.comsystem.physmem.bytes_read::cpu1.data 12497872 # Number of bytes read from this memory 2511374Ssteve.reinhardt@amd.comsystem.physmem.bytes_read::cpu1.l2cache.prefetcher 21171968 # Number of bytes read from this memory 2611374Ssteve.reinhardt@amd.comsystem.physmem.bytes_read::realview.ide 432064 # Number of bytes read from this memory 2711374Ssteve.reinhardt@amd.comsystem.physmem.bytes_read::total 82346584 # Number of bytes read from this memory 2811374Ssteve.reinhardt@amd.comsystem.physmem.bytes_inst_read::cpu0.inst 7916672 # Number of instructions bytes read from this memory 2911374Ssteve.reinhardt@amd.comsystem.physmem.bytes_inst_read::cpu1.inst 3894272 # Number of instructions bytes read from this memory 3011374Ssteve.reinhardt@amd.comsystem.physmem.bytes_inst_read::total 11810944 # Number of instructions bytes read from this memory 3111374Ssteve.reinhardt@amd.comsystem.physmem.bytes_written::writebacks 92922304 # Number of bytes written to this memory 3210827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 3310636Snilay@cs.wisc.edusystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3411374Ssteve.reinhardt@amd.comsystem.physmem.bytes_written::total 92942888 # Number of bytes written to this memory 3511374Ssteve.reinhardt@amd.comsystem.physmem.num_reads::cpu0.dtb.walker 3642 # Number of read requests responded to by this memory 3611374Ssteve.reinhardt@amd.comsystem.physmem.num_reads::cpu0.itb.walker 3291 # Number of read requests responded to by this memory 3711374Ssteve.reinhardt@amd.comsystem.physmem.num_reads::cpu0.inst 123698 # Number of read requests responded to by this memory 3811374Ssteve.reinhardt@amd.comsystem.physmem.num_reads::cpu0.data 274040 # Number of read requests responded to by this memory 3911374Ssteve.reinhardt@amd.comsystem.physmem.num_reads::cpu0.l2cache.prefetcher 283652 # Number of read requests responded to by this memory 4011374Ssteve.reinhardt@amd.comsystem.physmem.num_reads::cpu1.dtb.walker 2600 # Number of read requests responded to by this memory 4111374Ssteve.reinhardt@amd.comsystem.physmem.num_reads::cpu1.itb.walker 2065 # Number of read requests responded to by this memory 4211374Ssteve.reinhardt@amd.comsystem.physmem.num_reads::cpu1.inst 60848 # Number of read requests responded to by this memory 4311374Ssteve.reinhardt@amd.comsystem.physmem.num_reads::cpu1.data 195292 # Number of read requests responded to by this memory 4411374Ssteve.reinhardt@amd.comsystem.physmem.num_reads::cpu1.l2cache.prefetcher 330812 # Number of read requests responded to by this memory 4511374Ssteve.reinhardt@amd.comsystem.physmem.num_reads::realview.ide 6751 # Number of read requests responded to by this memory 4611374Ssteve.reinhardt@amd.comsystem.physmem.num_reads::total 1286691 # Number of read requests responded to by this memory 4711374Ssteve.reinhardt@amd.comsystem.physmem.num_writes::writebacks 1451911 # Number of write requests responded to by this memory 4810827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 4910636Snilay@cs.wisc.edusystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 5011374Ssteve.reinhardt@amd.comsystem.physmem.num_writes::total 1454485 # Number of write requests responded to by this memory 5111374Ssteve.reinhardt@amd.comsystem.physmem.bw_read::cpu0.dtb.walker 4912 # Total read bandwidth from this memory (bytes/s) 5211374Ssteve.reinhardt@amd.comsystem.physmem.bw_read::cpu0.itb.walker 4438 # Total read bandwidth from this memory (bytes/s) 5311374Ssteve.reinhardt@amd.comsystem.physmem.bw_read::cpu0.inst 166827 # Total read bandwidth from this memory (bytes/s) 5411374Ssteve.reinhardt@amd.comsystem.physmem.bw_read::cpu0.data 369570 # Total read bandwidth from this memory (bytes/s) 5511374Ssteve.reinhardt@amd.comsystem.physmem.bw_read::cpu0.l2cache.prefetcher 382550 # Total read bandwidth from this memory (bytes/s) 5611374Ssteve.reinhardt@amd.comsystem.physmem.bw_read::cpu1.dtb.walker 3507 # Total read bandwidth from this memory (bytes/s) 5711374Ssteve.reinhardt@amd.comsystem.physmem.bw_read::cpu1.itb.walker 2785 # Total read bandwidth from this memory (bytes/s) 5811374Ssteve.reinhardt@amd.comsystem.physmem.bw_read::cpu1.inst 82063 # Total read bandwidth from this memory (bytes/s) 5911374Ssteve.reinhardt@amd.comsystem.physmem.bw_read::cpu1.data 263365 # Total read bandwidth from this memory (bytes/s) 6011374Ssteve.reinhardt@amd.comsystem.physmem.bw_read::cpu1.l2cache.prefetcher 446153 # Total read bandwidth from this memory (bytes/s) 6111374Ssteve.reinhardt@amd.comsystem.physmem.bw_read::realview.ide 9105 # Total read bandwidth from this memory (bytes/s) 6211374Ssteve.reinhardt@amd.comsystem.physmem.bw_read::total 1735275 # Total read bandwidth from this memory (bytes/s) 6311374Ssteve.reinhardt@amd.comsystem.physmem.bw_inst_read::cpu0.inst 166827 # Instruction read bandwidth from this memory (bytes/s) 6411374Ssteve.reinhardt@amd.comsystem.physmem.bw_inst_read::cpu1.inst 82063 # Instruction read bandwidth from this memory (bytes/s) 6511374Ssteve.reinhardt@amd.comsystem.physmem.bw_inst_read::total 248890 # Instruction read bandwidth from this memory (bytes/s) 6611374Ssteve.reinhardt@amd.comsystem.physmem.bw_write::writebacks 1958135 # Write bandwidth from this memory (bytes/s) 6711374Ssteve.reinhardt@amd.comsystem.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) 6810636Snilay@cs.wisc.edusystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 6911374Ssteve.reinhardt@amd.comsystem.physmem.bw_write::total 1958569 # Write bandwidth from this memory (bytes/s) 7011374Ssteve.reinhardt@amd.comsystem.physmem.bw_total::writebacks 1958135 # Total bandwidth to/from this memory (bytes/s) 7111374Ssteve.reinhardt@amd.comsystem.physmem.bw_total::cpu0.dtb.walker 4912 # Total bandwidth to/from this memory (bytes/s) 7211374Ssteve.reinhardt@amd.comsystem.physmem.bw_total::cpu0.itb.walker 4438 # Total bandwidth to/from this memory (bytes/s) 7311374Ssteve.reinhardt@amd.comsystem.physmem.bw_total::cpu0.inst 166827 # Total bandwidth to/from this memory (bytes/s) 7411374Ssteve.reinhardt@amd.comsystem.physmem.bw_total::cpu0.data 370003 # Total bandwidth to/from this memory (bytes/s) 7511374Ssteve.reinhardt@amd.comsystem.physmem.bw_total::cpu0.l2cache.prefetcher 382550 # Total bandwidth to/from this memory (bytes/s) 7611374Ssteve.reinhardt@amd.comsystem.physmem.bw_total::cpu1.dtb.walker 3507 # Total bandwidth to/from this memory (bytes/s) 7711374Ssteve.reinhardt@amd.comsystem.physmem.bw_total::cpu1.itb.walker 2785 # Total bandwidth to/from this memory (bytes/s) 7811374Ssteve.reinhardt@amd.comsystem.physmem.bw_total::cpu1.inst 82063 # Total bandwidth to/from this memory (bytes/s) 7911374Ssteve.reinhardt@amd.comsystem.physmem.bw_total::cpu1.data 263365 # Total bandwidth to/from this memory (bytes/s) 8011374Ssteve.reinhardt@amd.comsystem.physmem.bw_total::cpu1.l2cache.prefetcher 446153 # Total bandwidth to/from this memory (bytes/s) 8111374Ssteve.reinhardt@amd.comsystem.physmem.bw_total::realview.ide 9105 # Total bandwidth to/from this memory (bytes/s) 8211374Ssteve.reinhardt@amd.comsystem.physmem.bw_total::total 3693844 # Total bandwidth to/from this memory (bytes/s) 8311374Ssteve.reinhardt@amd.comsystem.physmem.readReqs 1286691 # Number of read requests accepted 8411374Ssteve.reinhardt@amd.comsystem.physmem.writeReqs 1454485 # Number of write requests accepted 8511374Ssteve.reinhardt@amd.comsystem.physmem.readBursts 1286691 # Number of DRAM read bursts, including those serviced by the write queue 8611374Ssteve.reinhardt@amd.comsystem.physmem.writeBursts 1454485 # Number of DRAM write bursts, including those merged in the write queue 8711374Ssteve.reinhardt@amd.comsystem.physmem.bytesReadDRAM 82317440 # Total number of bytes read from DRAM 8811374Ssteve.reinhardt@amd.comsystem.physmem.bytesReadWrQ 30784 # Total number of bytes read from write queue 8911374Ssteve.reinhardt@amd.comsystem.physmem.bytesWritten 92941888 # Total number of bytes written to DRAM 9011374Ssteve.reinhardt@amd.comsystem.physmem.bytesReadSys 82346584 # Total read bytes from the system interface side 9111374Ssteve.reinhardt@amd.comsystem.physmem.bytesWrittenSys 92942888 # Total written bytes from the system interface side 9211374Ssteve.reinhardt@amd.comsystem.physmem.servicedByWrQ 481 # Number of DRAM read bursts serviced by the write queue 9311353Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one 9411336Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 9511374Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::0 68545 # Per bank write bursts 9611374Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::1 77862 # Per bank write bursts 9711374Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::2 76461 # Per bank write bursts 9811374Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::3 81936 # Per bank write bursts 9911374Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::4 74664 # Per bank write bursts 10011374Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::5 81822 # Per bank write bursts 10111374Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::6 81067 # Per bank write bursts 10211374Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::7 83827 # Per bank write bursts 10311374Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::8 73756 # Per bank write bursts 10411374Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::9 133954 # Per bank write bursts 10511374Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::10 75964 # Per bank write bursts 10611374Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::11 77586 # Per bank write bursts 10711374Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::12 69247 # Per bank write bursts 10811374Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::13 78127 # Per bank write bursts 10911374Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::14 73347 # Per bank write bursts 11011374Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::15 78045 # Per bank write bursts 11111374Ssteve.reinhardt@amd.comsystem.physmem.perBankWrBursts::0 83788 # Per bank write bursts 11211374Ssteve.reinhardt@amd.comsystem.physmem.perBankWrBursts::1 90226 # Per bank write bursts 11311374Ssteve.reinhardt@amd.comsystem.physmem.perBankWrBursts::2 90168 # Per bank write bursts 11411374Ssteve.reinhardt@amd.comsystem.physmem.perBankWrBursts::3 95983 # Per bank write bursts 11511374Ssteve.reinhardt@amd.comsystem.physmem.perBankWrBursts::4 89513 # Per bank write bursts 11611374Ssteve.reinhardt@amd.comsystem.physmem.perBankWrBursts::5 93413 # Per bank write bursts 11711374Ssteve.reinhardt@amd.comsystem.physmem.perBankWrBursts::6 92742 # Per bank write bursts 11811374Ssteve.reinhardt@amd.comsystem.physmem.perBankWrBursts::7 93553 # Per bank write bursts 11911374Ssteve.reinhardt@amd.comsystem.physmem.perBankWrBursts::8 87937 # Per bank write bursts 12011374Ssteve.reinhardt@amd.comsystem.physmem.perBankWrBursts::9 94416 # Per bank write bursts 12111374Ssteve.reinhardt@amd.comsystem.physmem.perBankWrBursts::10 91588 # Per bank write bursts 12211374Ssteve.reinhardt@amd.comsystem.physmem.perBankWrBursts::11 94818 # Per bank write bursts 12311374Ssteve.reinhardt@amd.comsystem.physmem.perBankWrBursts::12 85405 # Per bank write bursts 12411374Ssteve.reinhardt@amd.comsystem.physmem.perBankWrBursts::13 92349 # Per bank write bursts 12511374Ssteve.reinhardt@amd.comsystem.physmem.perBankWrBursts::14 86484 # Per bank write bursts 12611374Ssteve.reinhardt@amd.comsystem.physmem.perBankWrBursts::15 89834 # Per bank write bursts 12710515SAli.Saidi@ARM.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 12811374Ssteve.reinhardt@amd.comsystem.physmem.numWrRetry 36 # Number of times write queue was full causing retry 12911374Ssteve.reinhardt@amd.comsystem.physmem.totGap 47454489913500 # Total gap between requests 13010515SAli.Saidi@ARM.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 13110515SAli.Saidi@ARM.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 13210515SAli.Saidi@ARM.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 13310827Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 25 # Read request sizes (log2) 13410515SAli.Saidi@ARM.comsystem.physmem.readPktSize::4 5 # Read request sizes (log2) 13510515SAli.Saidi@ARM.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 13611374Ssteve.reinhardt@amd.comsystem.physmem.readPktSize::6 1286661 # Read request sizes (log2) 13710515SAli.Saidi@ARM.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 13810515SAli.Saidi@ARM.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 13910515SAli.Saidi@ARM.comsystem.physmem.writePktSize::2 2 # Write request sizes (log2) 14010827Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 14110515SAli.Saidi@ARM.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 14210515SAli.Saidi@ARM.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 14311374Ssteve.reinhardt@amd.comsystem.physmem.writePktSize::6 1451911 # Write request sizes (log2) 14411374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::0 827173 # What read queue length does an incoming req see 14511374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::1 164897 # What read queue length does an incoming req see 14611374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::2 63225 # What read queue length does an incoming req see 14711374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::3 47515 # What read queue length does an incoming req see 14811374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::4 40751 # What read queue length does an incoming req see 14911374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::5 37481 # What read queue length does an incoming req see 15011374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::6 33938 # What read queue length does an incoming req see 15111374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::7 30502 # What read queue length does an incoming req see 15211374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::8 26328 # What read queue length does an incoming req see 15311374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::9 5741 # What read queue length does an incoming req see 15411374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::10 2483 # What read queue length does an incoming req see 15511374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::11 1712 # What read queue length does an incoming req see 15611374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::12 1354 # What read queue length does an incoming req see 15711374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::13 989 # What read queue length does an incoming req see 15811374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::14 645 # What read queue length does an incoming req see 15911374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::15 527 # What read queue length does an incoming req see 16011374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::16 427 # What read queue length does an incoming req see 16111374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::17 343 # What read queue length does an incoming req see 16211374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::18 108 # What read queue length does an incoming req see 16311374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::19 65 # What read queue length does an incoming req see 16411374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see 16511374Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 16611353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 16711353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 16811353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 16910515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 17010515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 17110515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 17210515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 17310515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 17410515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 17510515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 17610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 17710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 17810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 17910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 18010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 18110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 18210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 18310515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 18410515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 18510515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 18610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 18710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 18810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 18910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 19010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 19111374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::15 34612 # What write queue length does an incoming req see 19211374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::16 41901 # What write queue length does an incoming req see 19311374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::17 58265 # What write queue length does an incoming req see 19411374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::18 63048 # What write queue length does an incoming req see 19511374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::19 69768 # What write queue length does an incoming req see 19611374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::20 73771 # What write queue length does an incoming req see 19711374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::21 78937 # What write queue length does an incoming req see 19811374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::22 85048 # What write queue length does an incoming req see 19911374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::23 89045 # What write queue length does an incoming req see 20011374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::24 90562 # What write queue length does an incoming req see 20111374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::25 92833 # What write queue length does an incoming req see 20211374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::26 96249 # What write queue length does an incoming req see 20311374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::27 94408 # What write queue length does an incoming req see 20411374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::28 95986 # What write queue length does an incoming req see 20511374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::29 105469 # What write queue length does an incoming req see 20611374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::30 93952 # What write queue length does an incoming req see 20711374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::31 86808 # What write queue length does an incoming req see 20811374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::32 83066 # What write queue length does an incoming req see 20911374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::33 4836 # What write queue length does an incoming req see 21011374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::34 2469 # What write queue length does an incoming req see 21111374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::35 1685 # What write queue length does an incoming req see 21211374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::36 1217 # What write queue length does an incoming req see 21311374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::37 978 # What write queue length does an incoming req see 21411374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::38 762 # What write queue length does an incoming req see 21511374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::39 690 # What write queue length does an incoming req see 21611374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::40 465 # What write queue length does an incoming req see 21711374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::41 413 # What write queue length does an incoming req see 21811374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::42 418 # What write queue length does an incoming req see 21911374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::43 367 # What write queue length does an incoming req see 22011374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::44 375 # What write queue length does an incoming req see 22111374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::45 388 # What write queue length does an incoming req see 22211374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::46 318 # What write queue length does an incoming req see 22311374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::47 299 # What write queue length does an incoming req see 22411374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::48 254 # What write queue length does an incoming req see 22511374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::49 267 # What write queue length does an incoming req see 22611374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::50 235 # What write queue length does an incoming req see 22711374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::51 212 # What write queue length does an incoming req see 22811374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::52 200 # What write queue length does an incoming req see 22911374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::53 208 # What write queue length does an incoming req see 23011374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::54 212 # What write queue length does an incoming req see 23111374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::55 148 # What write queue length does an incoming req see 23211374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::56 153 # What write queue length does an incoming req see 23311353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 172 # What write queue length does an incoming req see 23411374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::58 167 # What write queue length does an incoming req see 23511374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::59 125 # What write queue length does an incoming req see 23611374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::60 142 # What write queue length does an incoming req see 23711374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::61 156 # What write queue length does an incoming req see 23811374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::62 67 # What write queue length does an incoming req see 23911374Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::63 99 # What write queue length does an incoming req see 24011374Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::samples 1224605 # Bytes accessed per row activation 24111374Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::mean 143.114986 # Bytes accessed per row activation 24211374Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::gmean 97.246112 # Bytes accessed per row activation 24311374Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::stdev 190.672457 # Bytes accessed per row activation 24411374Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::0-127 830563 67.82% 67.82% # Bytes accessed per row activation 24511374Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::128-255 233051 19.03% 86.85% # Bytes accessed per row activation 24611374Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::256-383 57759 4.72% 91.57% # Bytes accessed per row activation 24711374Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::384-511 27718 2.26% 93.83% # Bytes accessed per row activation 24811374Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::512-639 20623 1.68% 95.52% # Bytes accessed per row activation 24911374Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::640-767 13112 1.07% 96.59% # Bytes accessed per row activation 25011374Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::768-895 7173 0.59% 97.17% # Bytes accessed per row activation 25111374Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::896-1023 5754 0.47% 97.64% # Bytes accessed per row activation 25211374Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::1024-1151 28852 2.36% 100.00% # Bytes accessed per row activation 25311374Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::total 1224605 # Bytes accessed per row activation 25411374Ssteve.reinhardt@amd.comsystem.physmem.rdPerTurnAround::samples 77530 # Reads before turning the bus around for writes 25511374Ssteve.reinhardt@amd.comsystem.physmem.rdPerTurnAround::mean 16.589449 # Reads before turning the bus around for writes 25611374Ssteve.reinhardt@amd.comsystem.physmem.rdPerTurnAround::stdev 141.842916 # Reads before turning the bus around for writes 25711374Ssteve.reinhardt@amd.comsystem.physmem.rdPerTurnAround::0-1023 77527 100.00% 100.00% # Reads before turning the bus around for writes 25811353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes 25911353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 26011353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes 26111374Ssteve.reinhardt@amd.comsystem.physmem.rdPerTurnAround::total 77530 # Reads before turning the bus around for writes 26211374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::samples 77530 # Writes before turning the bus around for reads 26311374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::mean 18.731033 # Writes before turning the bus around for reads 26411374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::gmean 18.088703 # Writes before turning the bus around for reads 26511374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::stdev 7.268543 # Writes before turning the bus around for reads 26611374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::16-19 64617 83.34% 83.34% # Writes before turning the bus around for reads 26711374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::20-23 6035 7.78% 91.13% # Writes before turning the bus around for reads 26811374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::24-27 3056 3.94% 95.07% # Writes before turning the bus around for reads 26911374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::28-31 1620 2.09% 97.16% # Writes before turning the bus around for reads 27011374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::32-35 474 0.61% 97.77% # Writes before turning the bus around for reads 27111374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::36-39 277 0.36% 98.13% # Writes before turning the bus around for reads 27211374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::40-43 269 0.35% 98.48% # Writes before turning the bus around for reads 27311374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::44-47 83 0.11% 98.58% # Writes before turning the bus around for reads 27411374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::48-51 290 0.37% 98.96% # Writes before turning the bus around for reads 27511374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::52-55 69 0.09% 99.05% # Writes before turning the bus around for reads 27611374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::56-59 30 0.04% 99.08% # Writes before turning the bus around for reads 27711374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::60-63 52 0.07% 99.15% # Writes before turning the bus around for reads 27811374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::64-67 249 0.32% 99.47% # Writes before turning the bus around for reads 27911374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::68-71 33 0.04% 99.52% # Writes before turning the bus around for reads 28011374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::72-75 40 0.05% 99.57% # Writes before turning the bus around for reads 28111374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::76-79 110 0.14% 99.71% # Writes before turning the bus around for reads 28211374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::80-83 167 0.22% 99.92% # Writes before turning the bus around for reads 28311374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::84-87 1 0.00% 99.93% # Writes before turning the bus around for reads 28411374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::88-91 2 0.00% 99.93% # Writes before turning the bus around for reads 28511374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::92-95 2 0.00% 99.93% # Writes before turning the bus around for reads 28611374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads 28711374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::100-103 1 0.00% 99.93% # Writes before turning the bus around for reads 28811374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::104-107 2 0.00% 99.94% # Writes before turning the bus around for reads 28911374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::108-111 1 0.00% 99.94% # Writes before turning the bus around for reads 29011374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::112-115 2 0.00% 99.94% # Writes before turning the bus around for reads 29111374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::120-123 3 0.00% 99.94% # Writes before turning the bus around for reads 29211374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::128-131 15 0.02% 99.96% # Writes before turning the bus around for reads 29311374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::132-135 1 0.00% 99.96% # Writes before turning the bus around for reads 29411374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::136-139 1 0.00% 99.97% # Writes before turning the bus around for reads 29511374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::140-143 5 0.01% 99.97% # Writes before turning the bus around for reads 29611374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::144-147 13 0.02% 99.99% # Writes before turning the bus around for reads 29711374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::156-159 3 0.00% 99.99% # Writes before turning the bus around for reads 29811374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::160-163 2 0.00% 99.99% # Writes before turning the bus around for reads 29911374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads 30011353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads 30111374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads 30211374Ssteve.reinhardt@amd.comsystem.physmem.wrPerTurnAround::total 77530 # Writes before turning the bus around for reads 30311374Ssteve.reinhardt@amd.comsystem.physmem.totQLat 47048753044 # Total ticks spent queuing 30411374Ssteve.reinhardt@amd.comsystem.physmem.totMemAccLat 71165190544 # Total ticks spent from burst creation until serviced by the DRAM 30511374Ssteve.reinhardt@amd.comsystem.physmem.totBusLat 6431050000 # Total ticks spent in databus transfers 30611374Ssteve.reinhardt@amd.comsystem.physmem.avgQLat 36579.37 # Average queueing delay per DRAM burst 30710515SAli.Saidi@ARM.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 30811374Ssteve.reinhardt@amd.comsystem.physmem.avgMemAccLat 55329.37 # Average memory access latency per DRAM burst 30911374Ssteve.reinhardt@amd.comsystem.physmem.avgRdBW 1.73 # Average DRAM read bandwidth in MiByte/s 31011374Ssteve.reinhardt@amd.comsystem.physmem.avgWrBW 1.96 # Average achieved write bandwidth in MiByte/s 31111374Ssteve.reinhardt@amd.comsystem.physmem.avgRdBWSys 1.74 # Average system read bandwidth in MiByte/s 31211374Ssteve.reinhardt@amd.comsystem.physmem.avgWrBWSys 1.96 # Average system write bandwidth in MiByte/s 31310515SAli.Saidi@ARM.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 31411374Ssteve.reinhardt@amd.comsystem.physmem.busUtil 0.03 # Data bus utilization in percentage 31511353Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 31611374Ssteve.reinhardt@amd.comsystem.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 31711374Ssteve.reinhardt@amd.comsystem.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing 31811374Ssteve.reinhardt@amd.comsystem.physmem.avgWrQLen 24.33 # Average write queue length when enqueuing 31911374Ssteve.reinhardt@amd.comsystem.physmem.readRowHits 962295 # Number of row buffer hits during reads 32011374Ssteve.reinhardt@amd.comsystem.physmem.writeRowHits 551527 # Number of row buffer hits during writes 32111374Ssteve.reinhardt@amd.comsystem.physmem.readRowHitRate 74.82 # Row buffer hit rate for reads 32211374Ssteve.reinhardt@amd.comsystem.physmem.writeRowHitRate 37.98 # Row buffer hit rate for writes 32311374Ssteve.reinhardt@amd.comsystem.physmem.avgGap 17311726.76 # Average gap between requests 32411374Ssteve.reinhardt@amd.comsystem.physmem.pageHitRate 55.28 # Row buffer hit rate, read and write combined 32511374Ssteve.reinhardt@amd.comsystem.physmem_0.actEnergy 4656869280 # Energy for activate commands per rank (pJ) 32611374Ssteve.reinhardt@amd.comsystem.physmem_0.preEnergy 2540950500 # Energy for precharge commands per rank (pJ) 32711374Ssteve.reinhardt@amd.comsystem.physmem_0.readEnergy 4884235200 # Energy for read commands per rank (pJ) 32811374Ssteve.reinhardt@amd.comsystem.physmem_0.writeEnergy 4726421280 # Energy for write commands per rank (pJ) 32911374Ssteve.reinhardt@amd.comsystem.physmem_0.refreshEnergy 3099496729680 # Energy for refresh commands per rank (pJ) 33011374Ssteve.reinhardt@amd.comsystem.physmem_0.actBackEnergy 1219171959180 # Energy for active background per rank (pJ) 33111374Ssteve.reinhardt@amd.comsystem.physmem_0.preBackEnergy 27403246221750 # Energy for precharge background per rank (pJ) 33211374Ssteve.reinhardt@amd.comsystem.physmem_0.totalEnergy 31738723386870 # Total energy per rank (pJ) 33311374Ssteve.reinhardt@amd.comsystem.physmem_0.averagePower 668.824424 # Core power per rank (mW) 33411374Ssteve.reinhardt@amd.comsystem.physmem_0.memoryStateTime::IDLE 45587152483743 # Time in different power states 33511374Ssteve.reinhardt@amd.comsystem.physmem_0.memoryStateTime::REF 1584609520000 # Time in different power states 33610628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 33711374Ssteve.reinhardt@amd.comsystem.physmem_0.memoryStateTime::ACT 282729931257 # Time in different power states 33810628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 33911374Ssteve.reinhardt@amd.comsystem.physmem_1.actEnergy 4601144520 # Energy for activate commands per rank (pJ) 34011374Ssteve.reinhardt@amd.comsystem.physmem_1.preEnergy 2510545125 # Energy for precharge commands per rank (pJ) 34111374Ssteve.reinhardt@amd.comsystem.physmem_1.readEnergy 5148202800 # Energy for read commands per rank (pJ) 34211374Ssteve.reinhardt@amd.comsystem.physmem_1.writeEnergy 4683944880 # Energy for write commands per rank (pJ) 34311374Ssteve.reinhardt@amd.comsystem.physmem_1.refreshEnergy 3099496729680 # Energy for refresh commands per rank (pJ) 34411374Ssteve.reinhardt@amd.comsystem.physmem_1.actBackEnergy 1221460881390 # Energy for active background per rank (pJ) 34511374Ssteve.reinhardt@amd.comsystem.physmem_1.preBackEnergy 27401238395250 # Energy for precharge background per rank (pJ) 34611374Ssteve.reinhardt@amd.comsystem.physmem_1.totalEnergy 31739139843645 # Total energy per rank (pJ) 34711374Ssteve.reinhardt@amd.comsystem.physmem_1.averagePower 668.833200 # Core power per rank (mW) 34811374Ssteve.reinhardt@amd.comsystem.physmem_1.memoryStateTime::IDLE 45583769039323 # Time in different power states 34911374Ssteve.reinhardt@amd.comsystem.physmem_1.memoryStateTime::REF 1584609520000 # Time in different power states 35010628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 35111374Ssteve.reinhardt@amd.comsystem.physmem_1.memoryStateTime::ACT 286113375677 # Time in different power states 35210628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 35310636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory 35410636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 35510636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory 35610636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 35710515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory 35810515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory 35910515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory 36010515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory 36110636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory 36210636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 36310636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory 36410636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 36510515SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory 36610636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) 36710636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 36810515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s) 36910636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 37010515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s) 37110515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) 37210515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s) 37310515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) 37410636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) 37510636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 37610515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s) 37710636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 37810515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) 37910585Sandreas.hansson@arm.comsystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 38010585Sandreas.hansson@arm.comsystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 38110585Sandreas.hansson@arm.comsystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 38211201Sandreas.hansson@arm.comsystem.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. 38311201Sandreas.hansson@arm.comsystem.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. 38411201Sandreas.hansson@arm.comsystem.cf0.dma_write_txs 1674 # Number of DMA write transactions. 38511374Ssteve.reinhardt@amd.comsystem.cpu0.branchPred.lookups 147959066 # Number of BP lookups 38611374Ssteve.reinhardt@amd.comsystem.cpu0.branchPred.condPredicted 105493690 # Number of conditional branches predicted 38711374Ssteve.reinhardt@amd.comsystem.cpu0.branchPred.condIncorrect 6448516 # Number of conditional branches incorrect 38811374Ssteve.reinhardt@amd.comsystem.cpu0.branchPred.BTBLookups 111296242 # Number of BTB lookups 38911374Ssteve.reinhardt@amd.comsystem.cpu0.branchPred.BTBHits 81329533 # Number of BTB hits 39010585Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 39111374Ssteve.reinhardt@amd.comsystem.cpu0.branchPred.BTBHitPct 73.074824 # BTB Hit Percentage 39211374Ssteve.reinhardt@amd.comsystem.cpu0.branchPred.usedRAS 17161750 # Number of times the RAS was used to get a target. 39311374Ssteve.reinhardt@amd.comsystem.cpu0.branchPred.RASInCorrect 1109253 # Number of incorrect RAS predictions. 39410515SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 39510628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 39610628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 39710628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 39810628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 39910628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 40010628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 40110628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 40210628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 40310585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 40410585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 40510585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 40610585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 40710585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 40810585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 40910585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 41010585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 41110585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 41210585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 41310585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 41410585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 41510585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 41610585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 41710585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 41810585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 41910585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 42010585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 42110585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 42210585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 42310585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 42411374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walks 300034 # Table walker walks requested 42511374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walksLong 300034 # Table walker walks initiated with long descriptors 42611374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level2 11904 # Level at which table walker walks with long descriptors terminate 42711374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level3 91094 # Level at which table walker walks with long descriptors terminate 42811374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkWaitTime::samples 300034 # Table walker wait (enqueue to first request) latency 42911374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkWaitTime::0 300034 100.00% 100.00% # Table walker wait (enqueue to first request) latency 43011374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkWaitTime::total 300034 # Table walker wait (enqueue to first request) latency 43111374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkCompletionTime::samples 102998 # Table walker service (enqueue to completion) latency 43211374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkCompletionTime::mean 24703.863182 # Table walker service (enqueue to completion) latency 43311374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkCompletionTime::gmean 21663.255890 # Table walker service (enqueue to completion) latency 43411374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkCompletionTime::stdev 26203.116698 # Table walker service (enqueue to completion) latency 43511374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkCompletionTime::0-65535 100872 97.94% 97.94% # Table walker service (enqueue to completion) latency 43611374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkCompletionTime::65536-131071 180 0.17% 98.11% # Table walker service (enqueue to completion) latency 43711374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkCompletionTime::131072-196607 1639 1.59% 99.70% # Table walker service (enqueue to completion) latency 43811374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkCompletionTime::196608-262143 73 0.07% 99.77% # Table walker service (enqueue to completion) latency 43911374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkCompletionTime::262144-327679 76 0.07% 99.85% # Table walker service (enqueue to completion) latency 44011374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkCompletionTime::327680-393215 46 0.04% 99.89% # Table walker service (enqueue to completion) latency 44111374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkCompletionTime::393216-458751 69 0.07% 99.96% # Table walker service (enqueue to completion) latency 44211374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkCompletionTime::458752-524287 28 0.03% 99.99% # Table walker service (enqueue to completion) latency 44311374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkCompletionTime::524288-589823 6 0.01% 99.99% # Table walker service (enqueue to completion) latency 44411374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkCompletionTime::589824-655359 7 0.01% 100.00% # Table walker service (enqueue to completion) latency 44511374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 44611374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 44711374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkCompletionTime::total 102998 # Table walker service (enqueue to completion) latency 44811201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::samples -909613592 # Table walker pending requests distribution 44911201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::0 -909613592 100.00% 100.00% # Table walker pending requests distribution 45011201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::total -909613592 # Table walker pending requests distribution 45111374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkPageSizes::4K 91094 88.44% 88.44% # Table walker page sizes translated 45211374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkPageSizes::2M 11904 11.56% 100.00% # Table walker page sizes translated 45311374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkPageSizes::total 102998 # Table walker page sizes translated 45411374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 300034 # Table walker requests started/completed, data/inst 45510628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 45611374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 300034 # Table walker requests started/completed, data/inst 45711374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 102998 # Table walker requests started/completed, data/inst 45810628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 45911374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 102998 # Table walker requests started/completed, data/inst 46011374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 403032 # Table walker requests started/completed, data/inst 46110585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_hits 0 # ITB inst hits 46210585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_misses 0 # ITB inst misses 46311374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.read_hits 94891169 # DTB read hits 46411374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.read_misses 247198 # DTB read misses 46511374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.write_hits 84318368 # DTB write hits 46611374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.write_misses 52836 # DTB write misses 46711374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed 46810585Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 46911374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.flush_tlb_mva_asid 47226 # Number of times TLB was flushed by MVA & ASID 47011374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.flush_tlb_asid 1094 # Number of times TLB was flushed by ASID 47111374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.flush_entries 40307 # Number of entries that have been flushed from TLB 47211374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.align_faults 1747 # Number of TLB faults due to alignment restrictions 47311374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.prefetch_faults 9392 # Number of TLB faults due to prefetch 47410585Sandreas.hansson@arm.comsystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 47511374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.perms_faults 12141 # Number of TLB faults due to permissions restrictions 47611374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.read_accesses 95138367 # DTB read accesses 47711374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.write_accesses 84371204 # DTB write accesses 47810585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 47911374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.hits 179209537 # DTB hits 48011374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.misses 300034 # DTB misses 48111374Ssteve.reinhardt@amd.comsystem.cpu0.dtb.accesses 179509571 # DTB accesses 48210628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 48310628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 48410628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 48510628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 48610628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 48710628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 48810628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 48910628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 49010585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 49110585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 49210585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 49310585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 49410585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 49510585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 49610585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 49710585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 49810585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 49910585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 50010585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 50110585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 50210585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 50310585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 50410585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 50510585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 50610585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 50710585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 50810585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 50910585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 51010585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 51111374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walks 71231 # Table walker walks requested 51211374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walksLong 71231 # Table walker walks initiated with long descriptors 51311374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level2 667 # Level at which table walker walks with long descriptors terminate 51411374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level3 60897 # Level at which table walker walks with long descriptors terminate 51511374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkWaitTime::samples 71231 # Table walker wait (enqueue to first request) latency 51611374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkWaitTime::0 71231 100.00% 100.00% # Table walker wait (enqueue to first request) latency 51711374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkWaitTime::total 71231 # Table walker wait (enqueue to first request) latency 51811374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkCompletionTime::samples 61564 # Table walker service (enqueue to completion) latency 51911374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkCompletionTime::mean 29116.975830 # Table walker service (enqueue to completion) latency 52011374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkCompletionTime::gmean 24576.932577 # Table walker service (enqueue to completion) latency 52111374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkCompletionTime::stdev 30900.488305 # Table walker service (enqueue to completion) latency 52211374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkCompletionTime::0-65535 59287 96.30% 96.30% # Table walker service (enqueue to completion) latency 52311374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkCompletionTime::65536-131071 14 0.02% 96.32% # Table walker service (enqueue to completion) latency 52411374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkCompletionTime::131072-196607 2011 3.27% 99.59% # Table walker service (enqueue to completion) latency 52511374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkCompletionTime::196608-262143 94 0.15% 99.74% # Table walker service (enqueue to completion) latency 52611374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkCompletionTime::262144-327679 85 0.14% 99.88% # Table walker service (enqueue to completion) latency 52711374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkCompletionTime::327680-393215 46 0.07% 99.96% # Table walker service (enqueue to completion) latency 52811374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkCompletionTime::393216-458751 21 0.03% 99.99% # Table walker service (enqueue to completion) latency 52911374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkCompletionTime::458752-524287 4 0.01% 100.00% # Table walker service (enqueue to completion) latency 53011374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 53111374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkCompletionTime::total 61564 # Table walker service (enqueue to completion) latency 53211201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::samples -910742092 # Table walker pending requests distribution 53311201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::0 -910742092 100.00% 100.00% # Table walker pending requests distribution 53411201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::total -910742092 # Table walker pending requests distribution 53511374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkPageSizes::4K 60897 98.92% 98.92% # Table walker page sizes translated 53611374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkPageSizes::2M 667 1.08% 100.00% # Table walker page sizes translated 53711374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkPageSizes::total 61564 # Table walker page sizes translated 53810628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 53911374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 71231 # Table walker requests started/completed, data/inst 54011374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 71231 # Table walker requests started/completed, data/inst 54110628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 54211374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 61564 # Table walker requests started/completed, data/inst 54311374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 61564 # Table walker requests started/completed, data/inst 54411374Ssteve.reinhardt@amd.comsystem.cpu0.itb.walker.walkRequestOrigin::total 132795 # Table walker requests started/completed, data/inst 54511374Ssteve.reinhardt@amd.comsystem.cpu0.itb.inst_hits 264582301 # ITB inst hits 54611374Ssteve.reinhardt@amd.comsystem.cpu0.itb.inst_misses 71231 # ITB inst misses 54710585Sandreas.hansson@arm.comsystem.cpu0.itb.read_hits 0 # DTB read hits 54810585Sandreas.hansson@arm.comsystem.cpu0.itb.read_misses 0 # DTB read misses 54910585Sandreas.hansson@arm.comsystem.cpu0.itb.write_hits 0 # DTB write hits 55010585Sandreas.hansson@arm.comsystem.cpu0.itb.write_misses 0 # DTB write misses 55111374Ssteve.reinhardt@amd.comsystem.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed 55210585Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 55311374Ssteve.reinhardt@amd.comsystem.cpu0.itb.flush_tlb_mva_asid 47226 # Number of times TLB was flushed by MVA & ASID 55411374Ssteve.reinhardt@amd.comsystem.cpu0.itb.flush_tlb_asid 1094 # Number of times TLB was flushed by ASID 55511374Ssteve.reinhardt@amd.comsystem.cpu0.itb.flush_entries 28772 # Number of entries that have been flushed from TLB 55610585Sandreas.hansson@arm.comsystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 55710585Sandreas.hansson@arm.comsystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 55810585Sandreas.hansson@arm.comsystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 55911374Ssteve.reinhardt@amd.comsystem.cpu0.itb.perms_faults 223649 # Number of TLB faults due to permissions restrictions 56010585Sandreas.hansson@arm.comsystem.cpu0.itb.read_accesses 0 # DTB read accesses 56110585Sandreas.hansson@arm.comsystem.cpu0.itb.write_accesses 0 # DTB write accesses 56211374Ssteve.reinhardt@amd.comsystem.cpu0.itb.inst_accesses 264653532 # ITB inst accesses 56311374Ssteve.reinhardt@amd.comsystem.cpu0.itb.hits 264582301 # DTB hits 56411374Ssteve.reinhardt@amd.comsystem.cpu0.itb.misses 71231 # DTB misses 56511374Ssteve.reinhardt@amd.comsystem.cpu0.itb.accesses 264653532 # DTB accesses 56611374Ssteve.reinhardt@amd.comsystem.cpu0.numCycles 1106984671 # number of cpu cycles simulated 56710585Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 56810585Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 56911374Ssteve.reinhardt@amd.comsystem.cpu0.committedInsts 488099503 # Number of instructions committed 57011374Ssteve.reinhardt@amd.comsystem.cpu0.committedOps 574418730 # Number of ops (including micro ops) committed 57111374Ssteve.reinhardt@amd.comsystem.cpu0.discardedOps 50785821 # Number of ops (including micro ops) which were discarded before commit 57211374Ssteve.reinhardt@amd.comsystem.cpu0.numFetchSuspends 5453 # Number of times Execute suspended instruction fetching 57311374Ssteve.reinhardt@amd.comsystem.cpu0.quiesceCycles 93802885102 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 57411374Ssteve.reinhardt@amd.comsystem.cpu0.cpi 2.267949 # CPI: cycles per instruction 57511374Ssteve.reinhardt@amd.comsystem.cpu0.ipc 0.440927 # IPC: instructions per cycle 57610585Sandreas.hansson@arm.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 57711374Ssteve.reinhardt@amd.comsystem.cpu0.kern.inst.quiesce 5643 # number of quiesce instructions executed 57811374Ssteve.reinhardt@amd.comsystem.cpu0.tickCycles 789747765 # Number of cycles that the object actually ticked 57911374Ssteve.reinhardt@amd.comsystem.cpu0.idleCycles 317236906 # Total number of cycles that the object has spent stopped 58011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.tags.replacements 6140209 # number of replacements 58111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.tags.tagsinuse 501.783411 # Cycle average of tags in use 58211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.tags.total_refs 169967706 # Total number of references to valid blocks. 58311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.tags.sampled_refs 6140721 # Sample count of references to valid blocks. 58411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.tags.avg_refs 27.678787 # Average number of references to valid blocks. 58511201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 7690769000 # Cycle when the warmup percentage was hit. 58611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 501.783411 # Average occupied blocks per requestor 58711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.980046 # Average percentage of cache occupancy 58811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.tags.occ_percent::total 0.980046 # Average percentage of cache occupancy 58911336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 59011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id 59111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 346 # Occupied blocks per task id 59211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id 59311336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 59411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.tags.tag_accesses 361643482 # Number of tag accesses 59511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.tags.data_accesses 361643482 # Number of data accesses 59611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 86800691 # number of ReadReq hits 59711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_hits::total 86800691 # number of ReadReq hits 59811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 78258675 # number of WriteReq hits 59911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_hits::total 78258675 # number of WriteReq hits 60011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 268918 # number of SoftPFReq hits 60111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.SoftPFReq_hits::total 268918 # number of SoftPFReq hits 60211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_hits::cpu0.data 127943 # number of WriteLineReq hits 60311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_hits::total 127943 # number of WriteLineReq hits 60411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1971519 # number of LoadLockedReq hits 60511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_hits::total 1971519 # number of LoadLockedReq hits 60611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 1943002 # number of StoreCondReq hits 60711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_hits::total 1943002 # number of StoreCondReq hits 60811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_hits::cpu0.data 165059366 # number of demand (read+write) hits 60911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_hits::total 165059366 # number of demand (read+write) hits 61011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_hits::cpu0.data 165328284 # number of overall hits 61111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_hits::total 165328284 # number of overall hits 61211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 3776237 # number of ReadReq misses 61311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_misses::total 3776237 # number of ReadReq misses 61411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 2642039 # number of WriteReq misses 61511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_misses::total 2642039 # number of WriteReq misses 61611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 748095 # number of SoftPFReq misses 61711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.SoftPFReq_misses::total 748095 # number of SoftPFReq misses 61811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_misses::cpu0.data 774634 # number of WriteLineReq misses 61911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_misses::total 774634 # number of WriteLineReq misses 62011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 182353 # number of LoadLockedReq misses 62111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_misses::total 182353 # number of LoadLockedReq misses 62211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 209431 # number of StoreCondReq misses 62311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_misses::total 209431 # number of StoreCondReq misses 62411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_misses::cpu0.data 6418276 # number of demand (read+write) misses 62511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_misses::total 6418276 # number of demand (read+write) misses 62611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_misses::cpu0.data 7166371 # number of overall misses 62711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_misses::total 7166371 # number of overall misses 62811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 71342778500 # number of ReadReq miss cycles 62911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_miss_latency::total 71342778500 # number of ReadReq miss cycles 63011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 67996340500 # number of WriteReq miss cycles 63111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_miss_latency::total 67996340500 # number of WriteReq miss cycles 63211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 46419090000 # number of WriteLineReq miss cycles 63311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_miss_latency::total 46419090000 # number of WriteLineReq miss cycles 63411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3111811500 # number of LoadLockedReq miss cycles 63511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 3111811500 # number of LoadLockedReq miss cycles 63611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5902963500 # number of StoreCondReq miss cycles 63711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 5902963500 # number of StoreCondReq miss cycles 63811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 7077000 # number of StoreCondFailReq miss cycles 63911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::total 7077000 # number of StoreCondFailReq miss cycles 64011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_miss_latency::cpu0.data 139339119000 # number of demand (read+write) miss cycles 64111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_miss_latency::total 139339119000 # number of demand (read+write) miss cycles 64211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_miss_latency::cpu0.data 139339119000 # number of overall miss cycles 64311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_miss_latency::total 139339119000 # number of overall miss cycles 64411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 90576928 # number of ReadReq accesses(hits+misses) 64511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_accesses::total 90576928 # number of ReadReq accesses(hits+misses) 64611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 80900714 # number of WriteReq accesses(hits+misses) 64711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_accesses::total 80900714 # number of WriteReq accesses(hits+misses) 64811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1017013 # number of SoftPFReq accesses(hits+misses) 64911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.SoftPFReq_accesses::total 1017013 # number of SoftPFReq accesses(hits+misses) 65011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_accesses::cpu0.data 902577 # number of WriteLineReq accesses(hits+misses) 65111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_accesses::total 902577 # number of WriteLineReq accesses(hits+misses) 65211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2153872 # number of LoadLockedReq accesses(hits+misses) 65311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 2153872 # number of LoadLockedReq accesses(hits+misses) 65411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2152433 # number of StoreCondReq accesses(hits+misses) 65511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_accesses::total 2152433 # number of StoreCondReq accesses(hits+misses) 65611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_accesses::cpu0.data 171477642 # number of demand (read+write) accesses 65711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_accesses::total 171477642 # number of demand (read+write) accesses 65811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_accesses::cpu0.data 172494655 # number of overall (read+write) accesses 65911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_accesses::total 172494655 # number of overall (read+write) accesses 66011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041691 # miss rate for ReadReq accesses 66111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.041691 # miss rate for ReadReq accesses 66211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032658 # miss rate for WriteReq accesses 66311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.032658 # miss rate for WriteReq accesses 66411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.735581 # miss rate for SoftPFReq accesses 66511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.735581 # miss rate for SoftPFReq accesses 66611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.858247 # miss rate for WriteLineReq accesses 66711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_miss_rate::total 0.858247 # miss rate for WriteLineReq accesses 66811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.084663 # miss rate for LoadLockedReq accesses 66911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.084663 # miss rate for LoadLockedReq accesses 67011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097300 # miss rate for StoreCondReq accesses 67111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.097300 # miss rate for StoreCondReq accesses 67211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.037429 # miss rate for demand accesses 67311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_miss_rate::total 0.037429 # miss rate for demand accesses 67411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.041545 # miss rate for overall accesses 67511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_miss_rate::total 0.041545 # miss rate for overall accesses 67611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18892.558518 # average ReadReq miss latency 67711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 18892.558518 # average ReadReq miss latency 67811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25736.312182 # average WriteReq miss latency 67911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 25736.312182 # average WriteReq miss latency 68011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 59923.899545 # average WriteLineReq miss latency 68111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::total 59923.899545 # average WriteLineReq miss latency 68211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 17064.767237 # average LoadLockedReq miss latency 68311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 17064.767237 # average LoadLockedReq miss latency 68411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28185.719879 # average StoreCondReq miss latency 68511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28185.719879 # average StoreCondReq miss latency 68610636Snilay@cs.wisc.edusystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 68710585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 68811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 21709.742460 # average overall miss latency 68911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_avg_miss_latency::total 21709.742460 # average overall miss latency 69011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19443.469924 # average overall miss latency 69111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_avg_miss_latency::total 19443.469924 # average overall miss latency 69210585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 69310585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 69410585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 69510585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 69610585Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 69710585Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 69810585Sandreas.hansson@arm.comsystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 69910585Sandreas.hansson@arm.comsystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 70011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.writebacks::writebacks 6140232 # number of writebacks 70111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.writebacks::total 6140232 # number of writebacks 70211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 470815 # number of ReadReq MSHR hits 70311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 470815 # number of ReadReq MSHR hits 70411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1099674 # number of WriteReq MSHR hits 70511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 1099674 # number of WriteReq MSHR hits 70611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 78 # number of WriteLineReq MSHR hits 70711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_mshr_hits::total 78 # number of WriteLineReq MSHR hits 70811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 45572 # number of LoadLockedReq MSHR hits 70911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 45572 # number of LoadLockedReq MSHR hits 71011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 53 # number of StoreCondReq MSHR hits 71111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_mshr_hits::total 53 # number of StoreCondReq MSHR hits 71211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_mshr_hits::cpu0.data 1570489 # number of demand (read+write) MSHR hits 71311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_mshr_hits::total 1570489 # number of demand (read+write) MSHR hits 71411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_mshr_hits::cpu0.data 1570489 # number of overall MSHR hits 71511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_mshr_hits::total 1570489 # number of overall MSHR hits 71611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3305422 # number of ReadReq MSHR misses 71711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 3305422 # number of ReadReq MSHR misses 71811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1542365 # number of WriteReq MSHR misses 71911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 1542365 # number of WriteReq MSHR misses 72011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 746538 # number of SoftPFReq MSHR misses 72111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::total 746538 # number of SoftPFReq MSHR misses 72211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 774556 # number of WriteLineReq MSHR misses 72311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::total 774556 # number of WriteLineReq MSHR misses 72411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 136781 # number of LoadLockedReq MSHR misses 72511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 136781 # number of LoadLockedReq MSHR misses 72611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 209378 # number of StoreCondReq MSHR misses 72711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 209378 # number of StoreCondReq MSHR misses 72811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.data 4847787 # number of demand (read+write) MSHR misses 72911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_mshr_misses::total 4847787 # number of demand (read+write) MSHR misses 73011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.data 5594325 # number of overall MSHR misses 73111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_mshr_misses::total 5594325 # number of overall MSHR misses 73211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15086 # number of ReadReq MSHR uncacheable 73311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::total 15086 # number of ReadReq MSHR uncacheable 73411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15976 # number of WriteReq MSHR uncacheable 73511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::total 15976 # number of WriteReq MSHR uncacheable 73611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 31062 # number of overall MSHR uncacheable misses 73711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::total 31062 # number of overall MSHR uncacheable misses 73811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 56024435500 # number of ReadReq MSHR miss cycles 73911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 56024435500 # number of ReadReq MSHR miss cycles 74011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 39191815000 # number of WriteReq MSHR miss cycles 74111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 39191815000 # number of WriteReq MSHR miss cycles 74211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 20208395000 # number of SoftPFReq MSHR miss cycles 74311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 20208395000 # number of SoftPFReq MSHR miss cycles 74411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 45637665000 # number of WriteLineReq MSHR miss cycles 74511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 45637665000 # number of WriteLineReq MSHR miss cycles 74611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 2043982500 # number of LoadLockedReq MSHR miss cycles 74711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2043982500 # number of LoadLockedReq MSHR miss cycles 74811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5689319500 # number of StoreCondReq MSHR miss cycles 74911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5689319500 # number of StoreCondReq MSHR miss cycles 75011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 6788500 # number of StoreCondFailReq MSHR miss cycles 75111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 6788500 # number of StoreCondFailReq MSHR miss cycles 75211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 95216250500 # number of demand (read+write) MSHR miss cycles 75311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 95216250500 # number of demand (read+write) MSHR miss cycles 75411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 115424645500 # number of overall MSHR miss cycles 75511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 115424645500 # number of overall MSHR miss cycles 75611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2640339000 # number of ReadReq MSHR uncacheable cycles 75711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2640339000 # number of ReadReq MSHR uncacheable cycles 75811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2747173500 # number of WriteReq MSHR uncacheable cycles 75911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2747173500 # number of WriteReq MSHR uncacheable cycles 76011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5387512500 # number of overall MSHR uncacheable cycles 76111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 5387512500 # number of overall MSHR uncacheable cycles 76211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036493 # mshr miss rate for ReadReq accesses 76311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036493 # mshr miss rate for ReadReq accesses 76411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019065 # mshr miss rate for WriteReq accesses 76511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019065 # mshr miss rate for WriteReq accesses 76611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.734050 # mshr miss rate for SoftPFReq accesses 76711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.734050 # mshr miss rate for SoftPFReq accesses 76811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.858161 # mshr miss rate for WriteLineReq accesses 76911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.858161 # mshr miss rate for WriteLineReq accesses 77011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063505 # mshr miss rate for LoadLockedReq accesses 77111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063505 # mshr miss rate for LoadLockedReq accesses 77211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097275 # mshr miss rate for StoreCondReq accesses 77311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097275 # mshr miss rate for StoreCondReq accesses 77411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028271 # mshr miss rate for demand accesses 77511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.028271 # mshr miss rate for demand accesses 77611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032432 # mshr miss rate for overall accesses 77711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.032432 # mshr miss rate for overall accesses 77811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16949.253530 # average ReadReq mshr miss latency 77911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16949.253530 # average ReadReq mshr miss latency 78011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25410.207701 # average WriteReq mshr miss latency 78111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25410.207701 # average WriteReq mshr miss latency 78211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 27069.479384 # average SoftPFReq mshr miss latency 78311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 27069.479384 # average SoftPFReq mshr miss latency 78411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 58921.065746 # average WriteLineReq mshr miss latency 78511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 58921.065746 # average WriteLineReq mshr miss latency 78611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14943.468026 # average LoadLockedReq mshr miss latency 78711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14943.468026 # average LoadLockedReq mshr miss latency 78811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27172.479917 # average StoreCondReq mshr miss latency 78911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27172.479917 # average StoreCondReq mshr miss latency 79010636Snilay@cs.wisc.edusystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 79110585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 79211374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19641.178645 # average overall mshr miss latency 79311374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 19641.178645 # average overall mshr miss latency 79411374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20632.452619 # average overall mshr miss latency 79511374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 20632.452619 # average overall mshr miss latency 79611374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 175019.156834 # average ReadReq mshr uncacheable latency 79711374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 175019.156834 # average ReadReq mshr uncacheable latency 79811374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171956.278167 # average WriteReq mshr uncacheable latency 79911374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171956.278167 # average WriteReq mshr uncacheable latency 80011374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 173443.838130 # average overall mshr uncacheable latency 80111374Ssteve.reinhardt@amd.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 173443.838130 # average overall mshr uncacheable latency 80210585Sandreas.hansson@arm.comsystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 80311374Ssteve.reinhardt@amd.comsystem.cpu0.icache.tags.replacements 9845680 # number of replacements 80411374Ssteve.reinhardt@amd.comsystem.cpu0.icache.tags.tagsinuse 511.897003 # Cycle average of tags in use 80511374Ssteve.reinhardt@amd.comsystem.cpu0.icache.tags.total_refs 254505668 # Total number of references to valid blocks. 80611374Ssteve.reinhardt@amd.comsystem.cpu0.icache.tags.sampled_refs 9846192 # Sample count of references to valid blocks. 80711374Ssteve.reinhardt@amd.comsystem.cpu0.icache.tags.avg_refs 25.848132 # Average number of references to valid blocks. 80811353Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 33055106000 # Cycle when the warmup percentage was hit. 80911374Ssteve.reinhardt@amd.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.897003 # Average occupied blocks per requestor 81011353Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999799 # Average percentage of cache occupancy 81111353Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999799 # Average percentage of cache occupancy 81210585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 81311374Ssteve.reinhardt@amd.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id 81411374Ssteve.reinhardt@amd.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id 81511374Ssteve.reinhardt@amd.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 205 # Occupied blocks per task id 81610585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 81711374Ssteve.reinhardt@amd.comsystem.cpu0.icache.tags.tag_accesses 538549912 # Number of tag accesses 81811374Ssteve.reinhardt@amd.comsystem.cpu0.icache.tags.data_accesses 538549912 # Number of data accesses 81911374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 254505668 # number of ReadReq hits 82011374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_hits::total 254505668 # number of ReadReq hits 82111374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_hits::cpu0.inst 254505668 # number of demand (read+write) hits 82211374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_hits::total 254505668 # number of demand (read+write) hits 82311374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_hits::cpu0.inst 254505668 # number of overall hits 82411374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_hits::total 254505668 # number of overall hits 82511374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 9846192 # number of ReadReq misses 82611374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_misses::total 9846192 # number of ReadReq misses 82711374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_misses::cpu0.inst 9846192 # number of demand (read+write) misses 82811374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_misses::total 9846192 # number of demand (read+write) misses 82911374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_misses::cpu0.inst 9846192 # number of overall misses 83011374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_misses::total 9846192 # number of overall misses 83111374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 104168962000 # number of ReadReq miss cycles 83211374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_miss_latency::total 104168962000 # number of ReadReq miss cycles 83311374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 104168962000 # number of demand (read+write) miss cycles 83411374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_miss_latency::total 104168962000 # number of demand (read+write) miss cycles 83511374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 104168962000 # number of overall miss cycles 83611374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_miss_latency::total 104168962000 # number of overall miss cycles 83711374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 264351860 # number of ReadReq accesses(hits+misses) 83811374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_accesses::total 264351860 # number of ReadReq accesses(hits+misses) 83911374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_accesses::cpu0.inst 264351860 # number of demand (read+write) accesses 84011374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_accesses::total 264351860 # number of demand (read+write) accesses 84111374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_accesses::cpu0.inst 264351860 # number of overall (read+write) accesses 84211374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_accesses::total 264351860 # number of overall (read+write) accesses 84311374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.037247 # miss rate for ReadReq accesses 84411374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.037247 # miss rate for ReadReq accesses 84511374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.037247 # miss rate for demand accesses 84611374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_miss_rate::total 0.037247 # miss rate for demand accesses 84711374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.037247 # miss rate for overall accesses 84811374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_miss_rate::total 0.037247 # miss rate for overall accesses 84911374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10579.619207 # average ReadReq miss latency 85011374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 10579.619207 # average ReadReq miss latency 85111374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10579.619207 # average overall miss latency 85211374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_avg_miss_latency::total 10579.619207 # average overall miss latency 85311374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10579.619207 # average overall miss latency 85411374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_avg_miss_latency::total 10579.619207 # average overall miss latency 85510585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 85610585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 85710585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 85810585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 85910585Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 86010585Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 86110585Sandreas.hansson@arm.comsystem.cpu0.icache.fast_writes 0 # number of fast writes performed 86210585Sandreas.hansson@arm.comsystem.cpu0.icache.cache_copies 0 # number of cache copies performed 86311374Ssteve.reinhardt@amd.comsystem.cpu0.icache.writebacks::writebacks 9845680 # number of writebacks 86411374Ssteve.reinhardt@amd.comsystem.cpu0.icache.writebacks::total 9845680 # number of writebacks 86511374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9846192 # number of ReadReq MSHR misses 86611374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_mshr_misses::total 9846192 # number of ReadReq MSHR misses 86711374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 9846192 # number of demand (read+write) MSHR misses 86811374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_mshr_misses::total 9846192 # number of demand (read+write) MSHR misses 86911374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 9846192 # number of overall MSHR misses 87011374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_mshr_misses::total 9846192 # number of overall MSHR misses 87111138Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable 87211138Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable 87311138Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses 87411138Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses 87511374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 99245866000 # number of ReadReq MSHR miss cycles 87611374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 99245866000 # number of ReadReq MSHR miss cycles 87711374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 99245866000 # number of demand (read+write) MSHR miss cycles 87811374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_mshr_miss_latency::total 99245866000 # number of demand (read+write) MSHR miss cycles 87911374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 99245866000 # number of overall MSHR miss cycles 88011374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_mshr_miss_latency::total 99245866000 # number of overall MSHR miss cycles 88111201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7414627000 # number of ReadReq MSHR uncacheable cycles 88211201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7414627000 # number of ReadReq MSHR uncacheable cycles 88311201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7414627000 # number of overall MSHR uncacheable cycles 88411201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::total 7414627000 # number of overall MSHR uncacheable cycles 88511374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.037247 # mshr miss rate for ReadReq accesses 88611374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.037247 # mshr miss rate for ReadReq accesses 88711374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.037247 # mshr miss rate for demand accesses 88811374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.037247 # mshr miss rate for demand accesses 88911374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.037247 # mshr miss rate for overall accesses 89011374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.037247 # mshr miss rate for overall accesses 89111374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10079.619207 # average ReadReq mshr miss latency 89211374Ssteve.reinhardt@amd.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10079.619207 # average ReadReq mshr miss latency 89311374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10079.619207 # average overall mshr miss latency 89411374Ssteve.reinhardt@amd.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 10079.619207 # average overall mshr miss latency 89511374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10079.619207 # average overall mshr miss latency 89611374Ssteve.reinhardt@amd.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 10079.619207 # average overall mshr miss latency 89711201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average ReadReq mshr uncacheable latency 89811201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141746.678392 # average ReadReq mshr uncacheable latency 89911201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average overall mshr uncacheable latency 90011201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141746.678392 # average overall mshr uncacheable latency 90110585Sandreas.hansson@arm.comsystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 90211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.prefetcher.num_hwpf_issued 8550248 # number of hwpf issued 90311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.prefetcher.pfIdentified 8550537 # number of prefetch candidates identified 90411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.prefetcher.pfBufferHit 256 # number of redundant prefetches already in prefetch queue 90510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 90610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 90711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.prefetcher.pfSpanPage 1111887 # number of prefetches not generated due to page crossing 90811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.replacements 3055162 # number of replacements 90911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.tagsinuse 16188.315469 # Cycle average of tags in use 91011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.total_refs 24712613 # Total number of references to valid blocks. 91111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.sampled_refs 3070855 # Sample count of references to valid blocks. 91211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.avg_refs 8.047470 # Average number of references to valid blocks. 91311353Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 8707838500 # Cycle when the warmup percentage was hit. 91411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 15276.749771 # Average occupied blocks per requestor 91511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 63.374129 # Average occupied blocks per requestor 91611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 61.193370 # Average occupied blocks per requestor 91711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 786.998198 # Average occupied blocks per requestor 91811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.932419 # Average percentage of cache occupancy 91911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003868 # Average percentage of cache occupancy 92011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003735 # Average percentage of cache occupancy 92111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.048035 # Average percentage of cache occupancy 92211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.occ_percent::total 0.988056 # Average percentage of cache occupancy 92311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1022 1100 # Occupied blocks per task id 92411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 82 # Occupied blocks per task id 92511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 14511 # Occupied blocks per task id 92611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::1 15 # Occupied blocks per task id 92711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::2 186 # Occupied blocks per task id 92811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::3 849 # Occupied blocks per task id 92911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::4 50 # Occupied blocks per task id 93011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 93111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 47 # Occupied blocks per task id 93211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 34 # Occupied blocks per task id 93311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id 93411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 880 # Occupied blocks per task id 93511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5451 # Occupied blocks per task id 93611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7600 # Occupied blocks per task id 93711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 443 # Occupied blocks per task id 93811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1022 0.067139 # Percentage of cache occupancy per task id 93911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005005 # Percentage of cache occupancy per task id 94011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.885681 # Percentage of cache occupancy per task id 94111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.tag_accesses 539634613 # Number of tag accesses 94211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.tags.data_accesses 539634613 # Number of data accesses 94311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 571667 # number of ReadReq hits 94411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 182910 # number of ReadReq hits 94511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_hits::total 754577 # number of ReadReq hits 94611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WritebackDirty_hits::writebacks 4024953 # number of WritebackDirty hits 94711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WritebackDirty_hits::total 4024953 # number of WritebackDirty hits 94811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WritebackClean_hits::writebacks 11958375 # number of WritebackClean hits 94911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WritebackClean_hits::total 11958375 # number of WritebackClean hits 95011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_hits::cpu0.data 880 # number of UpgradeReq hits 95111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_hits::total 880 # number of UpgradeReq hits 95211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 3 # number of SCUpgradeReq hits 95311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits 95411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 964239 # number of ReadExReq hits 95511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_hits::total 964239 # number of ReadExReq hits 95611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 9075218 # number of ReadCleanReq hits 95711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 9075218 # number of ReadCleanReq hits 95811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3054625 # number of ReadSharedReq hits 95911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 3054625 # number of ReadSharedReq hits 96011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_hits::cpu0.data 195729 # number of InvalidateReq hits 96111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_hits::total 195729 # number of InvalidateReq hits 96211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 571667 # number of demand (read+write) hits 96311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 182910 # number of demand (read+write) hits 96411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 9075218 # number of demand (read+write) hits 96511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_hits::cpu0.data 4018864 # number of demand (read+write) hits 96611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_hits::total 13848659 # number of demand (read+write) hits 96711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 571667 # number of overall hits 96811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 182910 # number of overall hits 96911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 9075218 # number of overall hits 97011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_hits::cpu0.data 4018864 # number of overall hits 97111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_hits::total 13848659 # number of overall hits 97211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 14134 # number of ReadReq misses 97311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10093 # number of ReadReq misses 97411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_misses::total 24227 # number of ReadReq misses 97511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses 97611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses 97711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 274802 # number of UpgradeReq misses 97811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_misses::total 274802 # number of UpgradeReq misses 97911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 209364 # number of SCUpgradeReq misses 98011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 209364 # number of SCUpgradeReq misses 98111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 11 # number of SCUpgradeFailReq misses 98211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::total 11 # number of SCUpgradeFailReq misses 98311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 311346 # number of ReadExReq misses 98411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_misses::total 311346 # number of ReadExReq misses 98511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 770973 # number of ReadCleanReq misses 98611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 770973 # number of ReadCleanReq misses 98711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1133829 # number of ReadSharedReq misses 98811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 1133829 # number of ReadSharedReq misses 98911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_misses::cpu0.data 576566 # number of InvalidateReq misses 99011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_misses::total 576566 # number of InvalidateReq misses 99111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 14134 # number of demand (read+write) misses 99211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 10093 # number of demand (read+write) misses 99311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 770973 # number of demand (read+write) misses 99411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_misses::cpu0.data 1445175 # number of demand (read+write) misses 99511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_misses::total 2240375 # number of demand (read+write) misses 99611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 14134 # number of overall misses 99711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 10093 # number of overall misses 99811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 770973 # number of overall misses 99911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_misses::cpu0.data 1445175 # number of overall misses 100011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_misses::total 2240375 # number of overall misses 100111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 807748500 # number of ReadReq miss cycles 100211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 660476500 # number of ReadReq miss cycles 100311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_miss_latency::total 1468225000 # number of ReadReq miss cycles 100411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3585176500 # number of UpgradeReq miss cycles 100511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::total 3585176500 # number of UpgradeReq miss cycles 100611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2077487000 # number of SCUpgradeReq miss cycles 100711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2077487000 # number of SCUpgradeReq miss cycles 100811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 6654497 # number of SCUpgradeFailReq miss cycles 100911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 6654497 # number of SCUpgradeFailReq miss cycles 101011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 20598931500 # number of ReadExReq miss cycles 101111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_miss_latency::total 20598931500 # number of ReadExReq miss cycles 101211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 29674847500 # number of ReadCleanReq miss cycles 101311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::total 29674847500 # number of ReadCleanReq miss cycles 101411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 51821822989 # number of ReadSharedReq miss cycles 101511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::total 51821822989 # number of ReadSharedReq miss cycles 101611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 441045000 # number of InvalidateReq miss cycles 101711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::total 441045000 # number of InvalidateReq miss cycles 101811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 807748500 # number of demand (read+write) miss cycles 101911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 660476500 # number of demand (read+write) miss cycles 102011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.inst 29674847500 # number of demand (read+write) miss cycles 102111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.data 72420754489 # number of demand (read+write) miss cycles 102211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_miss_latency::total 103563826989 # number of demand (read+write) miss cycles 102311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 807748500 # number of overall miss cycles 102411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 660476500 # number of overall miss cycles 102511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.inst 29674847500 # number of overall miss cycles 102611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.data 72420754489 # number of overall miss cycles 102711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_miss_latency::total 103563826989 # number of overall miss cycles 102811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 585801 # number of ReadReq accesses(hits+misses) 102911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 193003 # number of ReadReq accesses(hits+misses) 103011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_accesses::total 778804 # number of ReadReq accesses(hits+misses) 103111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WritebackDirty_accesses::writebacks 4024954 # number of WritebackDirty accesses(hits+misses) 103211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WritebackDirty_accesses::total 4024954 # number of WritebackDirty accesses(hits+misses) 103311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WritebackClean_accesses::writebacks 11958375 # number of WritebackClean accesses(hits+misses) 103411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WritebackClean_accesses::total 11958375 # number of WritebackClean accesses(hits+misses) 103511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 275682 # number of UpgradeReq accesses(hits+misses) 103611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 275682 # number of UpgradeReq accesses(hits+misses) 103711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 209367 # number of SCUpgradeReq accesses(hits+misses) 103811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 209367 # number of SCUpgradeReq accesses(hits+misses) 103911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 11 # number of SCUpgradeFailReq accesses(hits+misses) 104011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::total 11 # number of SCUpgradeFailReq accesses(hits+misses) 104111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1275585 # number of ReadExReq accesses(hits+misses) 104211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1275585 # number of ReadExReq accesses(hits+misses) 104311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9846191 # number of ReadCleanReq accesses(hits+misses) 104411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 9846191 # number of ReadCleanReq accesses(hits+misses) 104511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4188454 # number of ReadSharedReq accesses(hits+misses) 104611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 4188454 # number of ReadSharedReq accesses(hits+misses) 104711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 772295 # number of InvalidateReq accesses(hits+misses) 104811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_accesses::total 772295 # number of InvalidateReq accesses(hits+misses) 104911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 585801 # number of demand (read+write) accesses 105011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 193003 # number of demand (read+write) accesses 105111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 9846191 # number of demand (read+write) accesses 105211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 5464039 # number of demand (read+write) accesses 105311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_accesses::total 16089034 # number of demand (read+write) accesses 105411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 585801 # number of overall (read+write) accesses 105511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 193003 # number of overall (read+write) accesses 105611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 9846191 # number of overall (read+write) accesses 105711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 5464039 # number of overall (read+write) accesses 105811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_accesses::total 16089034 # number of overall (read+write) accesses 105911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.024128 # miss rate for ReadReq accesses 106011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052295 # miss rate for ReadReq accesses 106111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.031108 # miss rate for ReadReq accesses 106211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000000 # miss rate for WritebackDirty accesses 106311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000000 # miss rate for WritebackDirty accesses 106411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.996808 # miss rate for UpgradeReq accesses 106511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 0.996808 # miss rate for UpgradeReq accesses 106611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999986 # miss rate for SCUpgradeReq accesses 106711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999986 # miss rate for SCUpgradeReq accesses 106810636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 106910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 107011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.244081 # miss rate for ReadExReq accesses 107111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.244081 # miss rate for ReadExReq accesses 107211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.078302 # miss rate for ReadCleanReq accesses 107311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.078302 # miss rate for ReadCleanReq accesses 107411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.270703 # miss rate for ReadSharedReq accesses 107511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.270703 # miss rate for ReadSharedReq accesses 107611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.746562 # miss rate for InvalidateReq accesses 107711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::total 0.746562 # miss rate for InvalidateReq accesses 107811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.024128 # miss rate for demand accesses 107911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052295 # miss rate for demand accesses 108011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.078302 # miss rate for demand accesses 108111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.264488 # miss rate for demand accesses 108211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_miss_rate::total 0.139249 # miss rate for demand accesses 108311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.024128 # miss rate for overall accesses 108411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052295 # miss rate for overall accesses 108511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.078302 # miss rate for overall accesses 108611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.264488 # miss rate for overall accesses 108711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_miss_rate::total 0.139249 # miss rate for overall accesses 108811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 57149.320787 # average ReadReq miss latency 108911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 65439.066680 # average ReadReq miss latency 109011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::total 60602.839807 # average ReadReq miss latency 109111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13046.398862 # average UpgradeReq miss latency 109211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13046.398862 # average UpgradeReq miss latency 109311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 9922.847290 # average SCUpgradeReq miss latency 109411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 9922.847290 # average SCUpgradeReq miss latency 109511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 604954.272727 # average SCUpgradeFailReq miss latency 109611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 604954.272727 # average SCUpgradeFailReq miss latency 109711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 66160.899771 # average ReadExReq miss latency 109811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::total 66160.899771 # average ReadExReq miss latency 109911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 38490.125465 # average ReadCleanReq miss latency 110011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 38490.125465 # average ReadCleanReq miss latency 110111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 45705.148650 # average ReadSharedReq miss latency 110211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 45705.148650 # average ReadSharedReq miss latency 110311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 764.951454 # average InvalidateReq miss latency 110411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 764.951454 # average InvalidateReq miss latency 110511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 57149.320787 # average overall miss latency 110611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 65439.066680 # average overall miss latency 110711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38490.125465 # average overall miss latency 110811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 50112.100257 # average overall miss latency 110911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_avg_miss_latency::total 46226.112588 # average overall miss latency 111011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 57149.320787 # average overall miss latency 111111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 65439.066680 # average overall miss latency 111211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38490.125465 # average overall miss latency 111311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 50112.100257 # average overall miss latency 111411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_avg_miss_latency::total 46226.112588 # average overall miss latency 111511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 111610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 111711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 111810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 111911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 112010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 112110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.fast_writes 0 # number of fast writes performed 112210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.cache_copies 0 # number of cache copies performed 112311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.writebacks::writebacks 1773255 # number of writebacks 112411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.writebacks::total 1773255 # number of writebacks 112511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 3 # number of ReadReq MSHR hits 112611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits 112711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 9828 # number of ReadExReq MSHR hits 112811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::total 9828 # number of ReadExReq MSHR hits 112911353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 9 # number of ReadCleanReq MSHR hits 113011353Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits 113111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 1247 # number of ReadSharedReq MSHR hits 113211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::total 1247 # number of ReadSharedReq MSHR hits 113311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 3 # number of demand (read+write) MSHR hits 113411353Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.inst 9 # number of demand (read+write) MSHR hits 113511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.data 11075 # number of demand (read+write) MSHR hits 113611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_mshr_hits::total 11087 # number of demand (read+write) MSHR hits 113711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 3 # number of overall MSHR hits 113811353Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.inst 9 # number of overall MSHR hits 113911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.data 11075 # number of overall MSHR hits 114011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_hits::total 11087 # number of overall MSHR hits 114111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 14134 # number of ReadReq MSHR misses 114211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 10090 # number of ReadReq MSHR misses 114311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_mshr_misses::total 24224 # number of ReadReq MSHR misses 114411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 1 # number of WritebackDirty MSHR misses 114511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WritebackDirty_mshr_misses::total 1 # number of WritebackDirty MSHR misses 114611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 890747 # number of HardPFReq MSHR misses 114711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::total 890747 # number of HardPFReq MSHR misses 114811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 274802 # number of UpgradeReq MSHR misses 114911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::total 274802 # number of UpgradeReq MSHR misses 115011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 209364 # number of SCUpgradeReq MSHR misses 115111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 209364 # number of SCUpgradeReq MSHR misses 115211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 11 # number of SCUpgradeFailReq MSHR misses 115311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 11 # number of SCUpgradeFailReq MSHR misses 115411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 301518 # number of ReadExReq MSHR misses 115511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::total 301518 # number of ReadExReq MSHR misses 115611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 770964 # number of ReadCleanReq MSHR misses 115711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::total 770964 # number of ReadCleanReq MSHR misses 115811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1132582 # number of ReadSharedReq MSHR misses 115911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1132582 # number of ReadSharedReq MSHR misses 116011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 576566 # number of InvalidateReq MSHR misses 116111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::total 576566 # number of InvalidateReq MSHR misses 116211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 14134 # number of demand (read+write) MSHR misses 116311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 10090 # number of demand (read+write) MSHR misses 116411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.inst 770964 # number of demand (read+write) MSHR misses 116511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.data 1434100 # number of demand (read+write) MSHR misses 116611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_mshr_misses::total 2229288 # number of demand (read+write) MSHR misses 116711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 14134 # number of overall MSHR misses 116811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 10090 # number of overall MSHR misses 116911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.inst 770964 # number of overall MSHR misses 117011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.data 1434100 # number of overall MSHR misses 117111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 890747 # number of overall MSHR misses 117211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_misses::total 3120035 # number of overall MSHR misses 117311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable 117411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 15086 # number of ReadReq MSHR uncacheable 117511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::total 67395 # number of ReadReq MSHR uncacheable 117611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 15976 # number of WriteReq MSHR uncacheable 117711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::total 15976 # number of WriteReq MSHR uncacheable 117811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses 117911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 31062 # number of overall MSHR uncacheable misses 118011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::total 83371 # number of overall MSHR uncacheable misses 118111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 722944500 # number of ReadReq MSHR miss cycles 118211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 599881000 # number of ReadReq MSHR miss cycles 118311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1322825500 # number of ReadReq MSHR miss cycles 118411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 54995868600 # number of HardPFReq MSHR miss cycles 118511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 54995868600 # number of HardPFReq MSHR miss cycles 118611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 8223573999 # number of UpgradeReq MSHR miss cycles 118711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 8223573999 # number of UpgradeReq MSHR miss cycles 118811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 4114812496 # number of SCUpgradeReq MSHR miss cycles 118911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 4114812496 # number of SCUpgradeReq MSHR miss cycles 119011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 6132497 # number of SCUpgradeFailReq MSHR miss cycles 119111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 6132497 # number of SCUpgradeFailReq MSHR miss cycles 119211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 17351951000 # number of ReadExReq MSHR miss cycles 119311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 17351951000 # number of ReadExReq MSHR miss cycles 119411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 25048433000 # number of ReadCleanReq MSHR miss cycles 119511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 25048433000 # number of ReadCleanReq MSHR miss cycles 119611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 44909041489 # number of ReadSharedReq MSHR miss cycles 119711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 44909041489 # number of ReadSharedReq MSHR miss cycles 119811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 39596476000 # number of InvalidateReq MSHR miss cycles 119911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 39596476000 # number of InvalidateReq MSHR miss cycles 120011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 722944500 # number of demand (read+write) MSHR miss cycles 120111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 599881000 # number of demand (read+write) MSHR miss cycles 120211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 25048433000 # number of demand (read+write) MSHR miss cycles 120311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 62260992489 # number of demand (read+write) MSHR miss cycles 120411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_mshr_miss_latency::total 88632250989 # number of demand (read+write) MSHR miss cycles 120511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 722944500 # number of overall MSHR miss cycles 120611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 599881000 # number of overall MSHR miss cycles 120711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 25048433000 # number of overall MSHR miss cycles 120811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 62260992489 # number of overall MSHR miss cycles 120911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 54995868600 # number of overall MSHR miss cycles 121011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_miss_latency::total 143628119589 # number of overall MSHR miss cycles 121111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of ReadReq MSHR uncacheable cycles 121211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2519460500 # number of ReadReq MSHR uncacheable cycles 121311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9515615500 # number of ReadReq MSHR uncacheable cycles 121411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2627296000 # number of WriteReq MSHR uncacheable cycles 121511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2627296000 # number of WriteReq MSHR uncacheable cycles 121611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of overall MSHR uncacheable cycles 121711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5146756500 # number of overall MSHR uncacheable cycles 121811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12142911500 # number of overall MSHR uncacheable cycles 121911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.024128 # mshr miss rate for ReadReq accesses 122011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052279 # mshr miss rate for ReadReq accesses 122111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.031104 # mshr miss rate for ReadReq accesses 122211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackDirty accesses 122311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackDirty accesses 122410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 122510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 122611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.996808 # mshr miss rate for UpgradeReq accesses 122711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.996808 # mshr miss rate for UpgradeReq accesses 122811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999986 # mshr miss rate for SCUpgradeReq accesses 122911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999986 # mshr miss rate for SCUpgradeReq accesses 123010636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 123110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 123211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.236376 # mshr miss rate for ReadExReq accesses 123311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.236376 # mshr miss rate for ReadExReq accesses 123411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.078301 # mshr miss rate for ReadCleanReq accesses 123511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.078301 # mshr miss rate for ReadCleanReq accesses 123611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.270406 # mshr miss rate for ReadSharedReq accesses 123711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.270406 # mshr miss rate for ReadSharedReq accesses 123811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.746562 # mshr miss rate for InvalidateReq accesses 123911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.746562 # mshr miss rate for InvalidateReq accesses 124011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.024128 # mshr miss rate for demand accesses 124111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052279 # mshr miss rate for demand accesses 124211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.078301 # mshr miss rate for demand accesses 124311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.262462 # mshr miss rate for demand accesses 124411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_mshr_miss_rate::total 0.138559 # mshr miss rate for demand accesses 124511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.024128 # mshr miss rate for overall accesses 124611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052279 # mshr miss rate for overall accesses 124711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.078301 # mshr miss rate for overall accesses 124811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.262462 # mshr miss rate for overall accesses 124910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 125011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_mshr_miss_rate::total 0.193923 # mshr miss rate for overall accesses 125111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 51149.320787 # average ReadReq mshr miss latency 125211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 59453.022795 # average ReadReq mshr miss latency 125311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 54608.053996 # average ReadReq mshr miss latency 125411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61741.289726 # average HardPFReq mshr miss latency 125511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 61741.289726 # average HardPFReq mshr miss latency 125611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29925.451776 # average UpgradeReq mshr miss latency 125711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29925.451776 # average UpgradeReq mshr miss latency 125811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19653.868363 # average SCUpgradeReq mshr miss latency 125911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19653.868363 # average SCUpgradeReq mshr miss latency 126011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 557499.727273 # average SCUpgradeFailReq mshr miss latency 126111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 557499.727273 # average SCUpgradeFailReq mshr miss latency 126211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57548.640546 # average ReadExReq mshr miss latency 126311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57548.640546 # average ReadExReq mshr miss latency 126411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32489.756980 # average ReadCleanReq mshr miss latency 126511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32489.756980 # average ReadCleanReq mshr miss latency 126611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 39651.911728 # average ReadSharedReq mshr miss latency 126711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 39651.911728 # average ReadSharedReq mshr miss latency 126811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 68676.397845 # average InvalidateReq mshr miss latency 126911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 68676.397845 # average InvalidateReq mshr miss latency 127011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 51149.320787 # average overall mshr miss latency 127111374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 59453.022795 # average overall mshr miss latency 127211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32489.756980 # average overall mshr miss latency 127311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 43414.679931 # average overall mshr miss latency 127411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::total 39758.098096 # average overall mshr miss latency 127511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 51149.320787 # average overall mshr miss latency 127611374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 59453.022795 # average overall mshr miss latency 127711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32489.756980 # average overall mshr miss latency 127811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 43414.679931 # average overall mshr miss latency 127911374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61741.289726 # average overall mshr miss latency 128011374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46034.137306 # average overall mshr miss latency 128111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average ReadReq mshr uncacheable latency 128211374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167006.529232 # average ReadReq mshr uncacheable latency 128311374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 141191.713035 # average ReadReq mshr uncacheable latency 128411374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164452.679019 # average WriteReq mshr uncacheable latency 128511374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164452.679019 # average WriteReq mshr uncacheable latency 128611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average overall mshr uncacheable latency 128711374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 165693.017191 # average overall mshr uncacheable latency 128811374Ssteve.reinhardt@amd.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 145649.104605 # average overall mshr uncacheable latency 128910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 129011374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.snoop_filter.tot_requests 32897508 # Total number of requests made to the snoop filter. 129111374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_requests 16815136 # Number of requests hitting in the snoop filter with a single holder of the requested data. 129211374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2581 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 129311374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.snoop_filter.tot_snoops 2403341 # Total number of snoops made to the snoop filter. 129411374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2402836 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 129511374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 505 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 129611374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 933618 # Transaction distribution 129711374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 15066373 # Transaction distribution 129811374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 15977 # Transaction distribution 129911374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 15976 # Transaction distribution 130011374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::WritebackDirty 5804347 # Transaction distribution 130111374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::WritebackClean 11960956 # Transaction distribution 130211374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::CleanEvict 3276888 # Transaction distribution 130311374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::HardPFReq 1153420 # Transaction distribution 130411374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution 130511374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 478642 # Transaction distribution 130611374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 376774 # Transaction distribution 130711374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 550943 # Transaction distribution 130811374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 90 # Transaction distribution 130911374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::UpgradeFailResp 166 # Transaction distribution 131011374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1307095 # Transaction distribution 131111374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1283776 # Transaction distribution 131211374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 9846192 # Transaction distribution 131311374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 5335526 # Transaction distribution 131411374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::InvalidateReq 825564 # Transaction distribution 131511374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.trans_dist::InvalidateResp 772295 # Transaction distribution 131611374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 29642681 # Packet count per connected master and slave (bytes) 131711374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19817496 # Packet count per connected master and slave (bytes) 131811374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 405752 # Packet count per connected master and slave (bytes) 131911374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1239273 # Packet count per connected master and slave (bytes) 132011374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.pkt_count::total 51105202 # Packet count per connected master and slave (bytes) 132111374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1263627520 # Cumulative packet size per connected master and slave (bytes) 132211374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 749575419 # Cumulative packet size per connected master and slave (bytes) 132311374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1544024 # Cumulative packet size per connected master and slave (bytes) 132411374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4686408 # Cumulative packet size per connected master and slave (bytes) 132511374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.pkt_size::total 2019433371 # Cumulative packet size per connected master and slave (bytes) 132611374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.snoops 8071773 # Total snoops (count) 132711374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.snoop_fanout::samples 25329179 # Request fanout histogram 132811374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.snoop_fanout::mean 0.108588 # Request fanout histogram 132911374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.311185 # Request fanout histogram 133010585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 133111374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.snoop_fanout::0 22579246 89.14% 89.14% # Request fanout histogram 133211374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.snoop_fanout::1 2749428 10.85% 100.00% # Request fanout histogram 133311374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.snoop_fanout::2 505 0.00% 100.00% # Request fanout histogram 133410585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 133511138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 133610827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 133711374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.snoop_fanout::total 25329179 # Request fanout histogram 133811374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.reqLayer0.occupancy 32745453976 # Layer occupancy (ticks) 133911201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 134011374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.snoopLayer0.occupancy 192728655 # Layer occupancy (ticks) 134110585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 134211374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.respLayer0.occupancy 14851397186 # Layer occupancy (ticks) 134310585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 134411374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.respLayer1.occupancy 8851946898 # Layer occupancy (ticks) 134510585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 134611374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.respLayer2.occupancy 212824349 # Layer occupancy (ticks) 134710585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 134811374Ssteve.reinhardt@amd.comsystem.cpu0.toL2Bus.respLayer3.occupancy 653582276 # Layer occupancy (ticks) 134910585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 135011374Ssteve.reinhardt@amd.comsystem.cpu1.branchPred.lookups 143060728 # Number of BP lookups 135111374Ssteve.reinhardt@amd.comsystem.cpu1.branchPred.condPredicted 103431257 # Number of conditional branches predicted 135211374Ssteve.reinhardt@amd.comsystem.cpu1.branchPred.condIncorrect 6108949 # Number of conditional branches incorrect 135311374Ssteve.reinhardt@amd.comsystem.cpu1.branchPred.BTBLookups 108043566 # Number of BTB lookups 135411374Ssteve.reinhardt@amd.comsystem.cpu1.branchPred.BTBHits 80039888 # Number of BTB hits 135510585Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 135611374Ssteve.reinhardt@amd.comsystem.cpu1.branchPred.BTBHitPct 74.081124 # BTB Hit Percentage 135711374Ssteve.reinhardt@amd.comsystem.cpu1.branchPred.usedRAS 15973583 # Number of times the RAS was used to get a target. 135811374Ssteve.reinhardt@amd.comsystem.cpu1.branchPred.RASInCorrect 1078136 # Number of incorrect RAS predictions. 135910628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 136010628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 136110628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 136210628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 136310628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 136410628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 136510628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 136610628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 136710585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 136810585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 136910585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 137010585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 137110585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 137210585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 137310585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 137410585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 137510585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 137610585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 137710585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 137810585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 137910585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 138010585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 138110585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 138210585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 138310585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 138410585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 138510585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 138610585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 138710585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 138811374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walks 316205 # Table walker walks requested 138911374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walksLong 316205 # Table walker walks initiated with long descriptors 139011374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level2 13111 # Level at which table walker walks with long descriptors terminate 139111374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level3 102055 # Level at which table walker walks with long descriptors terminate 139211374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkWaitTime::samples 316205 # Table walker wait (enqueue to first request) latency 139311374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkWaitTime::0 316205 100.00% 100.00% # Table walker wait (enqueue to first request) latency 139411374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkWaitTime::total 316205 # Table walker wait (enqueue to first request) latency 139511374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkCompletionTime::samples 115166 # Table walker service (enqueue to completion) latency 139611374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkCompletionTime::mean 23006.933470 # Table walker service (enqueue to completion) latency 139711374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkCompletionTime::gmean 21361.362420 # Table walker service (enqueue to completion) latency 139811374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkCompletionTime::stdev 17841.956140 # Table walker service (enqueue to completion) latency 139911374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkCompletionTime::0-65535 114056 99.04% 99.04% # Table walker service (enqueue to completion) latency 140011374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkCompletionTime::65536-131071 145 0.13% 99.16% # Table walker service (enqueue to completion) latency 140111374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkCompletionTime::131072-196607 815 0.71% 99.87% # Table walker service (enqueue to completion) latency 140211374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkCompletionTime::196608-262143 40 0.03% 99.90% # Table walker service (enqueue to completion) latency 140311374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkCompletionTime::262144-327679 38 0.03% 99.94% # Table walker service (enqueue to completion) latency 140411374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.95% # Table walker service (enqueue to completion) latency 140511374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkCompletionTime::393216-458751 32 0.03% 99.98% # Table walker service (enqueue to completion) latency 140611374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkCompletionTime::458752-524287 14 0.01% 99.99% # Table walker service (enqueue to completion) latency 140711374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency 140811353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 140911374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 141011374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkCompletionTime::total 115166 # Table walker service (enqueue to completion) latency 141111353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::samples 1788277352 # Table walker pending requests distribution 141211353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::0 1788277352 100.00% 100.00% # Table walker pending requests distribution 141311353Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::total 1788277352 # Table walker pending requests distribution 141411374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkPageSizes::4K 102056 88.62% 88.62% # Table walker page sizes translated 141511374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkPageSizes::2M 13111 11.38% 100.00% # Table walker page sizes translated 141611374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkPageSizes::total 115167 # Table walker page sizes translated 141711374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 316205 # Table walker requests started/completed, data/inst 141810628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 141911374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 316205 # Table walker requests started/completed, data/inst 142011374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 115167 # Table walker requests started/completed, data/inst 142110628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 142211374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 115167 # Table walker requests started/completed, data/inst 142311374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 431372 # Table walker requests started/completed, data/inst 142410585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_hits 0 # ITB inst hits 142510585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_misses 0 # ITB inst misses 142611374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.read_hits 90416501 # DTB read hits 142711374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.read_misses 263668 # DTB read misses 142811374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.write_hits 78865175 # DTB write hits 142911374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.write_misses 52537 # DTB write misses 143011374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed 143110585Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 143211374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.flush_tlb_mva_asid 47226 # Number of times TLB was flushed by MVA & ASID 143311374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.flush_tlb_asid 1094 # Number of times TLB was flushed by ASID 143411374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.flush_entries 39779 # Number of entries that have been flushed from TLB 143511374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.align_faults 1900 # Number of TLB faults due to alignment restrictions 143611374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.prefetch_faults 9673 # Number of TLB faults due to prefetch 143710585Sandreas.hansson@arm.comsystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 143811374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.perms_faults 11862 # Number of TLB faults due to permissions restrictions 143911374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.read_accesses 90680169 # DTB read accesses 144011374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.write_accesses 78917712 # DTB write accesses 144110585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 144211374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.hits 169281676 # DTB hits 144311374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.misses 316205 # DTB misses 144411374Ssteve.reinhardt@amd.comsystem.cpu1.dtb.accesses 169597881 # DTB accesses 144510628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 144610628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 144710628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 144810628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 144910628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 145010628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 145110628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 145210628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 145310585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 145410585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 145510585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 145610585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 145710585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 145810585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 145910585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 146010585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 146110585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 146210585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 146310585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 146410585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 146510585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 146610585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 146710585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 146810585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 146910585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 147010585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 147110585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 147210585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 147310585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 147411374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walks 61623 # Table walker walks requested 147511374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walksLong 61623 # Table walker walks initiated with long descriptors 147611374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level2 682 # Level at which table walker walks with long descriptors terminate 147711374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level3 51951 # Level at which table walker walks with long descriptors terminate 147811374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkWaitTime::samples 61623 # Table walker wait (enqueue to first request) latency 147911374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkWaitTime::0 61623 100.00% 100.00% # Table walker wait (enqueue to first request) latency 148011374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkWaitTime::total 61623 # Table walker wait (enqueue to first request) latency 148111374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkCompletionTime::samples 52633 # Table walker service (enqueue to completion) latency 148211374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkCompletionTime::mean 26809.463644 # Table walker service (enqueue to completion) latency 148311374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkCompletionTime::gmean 23734.871548 # Table walker service (enqueue to completion) latency 148411374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkCompletionTime::stdev 24762.364644 # Table walker service (enqueue to completion) latency 148511374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkCompletionTime::0-65535 51446 97.74% 97.74% # Table walker service (enqueue to completion) latency 148611374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkCompletionTime::65536-131071 9 0.02% 97.76% # Table walker service (enqueue to completion) latency 148711374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkCompletionTime::131072-196607 1035 1.97% 99.73% # Table walker service (enqueue to completion) latency 148811374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkCompletionTime::196608-262143 54 0.10% 99.83% # Table walker service (enqueue to completion) latency 148911374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkCompletionTime::262144-327679 44 0.08% 99.91% # Table walker service (enqueue to completion) latency 149011374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkCompletionTime::327680-393215 33 0.06% 99.98% # Table walker service (enqueue to completion) latency 149111374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkCompletionTime::393216-458751 9 0.02% 99.99% # Table walker service (enqueue to completion) latency 149211374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 149311353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 149411374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkCompletionTime::total 52633 # Table walker service (enqueue to completion) latency 149511353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::samples 1787261852 # Table walker pending requests distribution 149611353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::0 1787261852 100.00% 100.00% # Table walker pending requests distribution 149711353Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::total 1787261852 # Table walker pending requests distribution 149811374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkPageSizes::4K 51951 98.70% 98.70% # Table walker page sizes translated 149911374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkPageSizes::2M 682 1.30% 100.00% # Table walker page sizes translated 150011374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkPageSizes::total 52633 # Table walker page sizes translated 150110628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 150211374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61623 # Table walker requests started/completed, data/inst 150311374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 61623 # Table walker requests started/completed, data/inst 150410628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 150511374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 52633 # Table walker requests started/completed, data/inst 150611374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 52633 # Table walker requests started/completed, data/inst 150711374Ssteve.reinhardt@amd.comsystem.cpu1.itb.walker.walkRequestOrigin::total 114256 # Table walker requests started/completed, data/inst 150811374Ssteve.reinhardt@amd.comsystem.cpu1.itb.inst_hits 255703249 # ITB inst hits 150911374Ssteve.reinhardt@amd.comsystem.cpu1.itb.inst_misses 61623 # ITB inst misses 151010585Sandreas.hansson@arm.comsystem.cpu1.itb.read_hits 0 # DTB read hits 151110585Sandreas.hansson@arm.comsystem.cpu1.itb.read_misses 0 # DTB read misses 151210585Sandreas.hansson@arm.comsystem.cpu1.itb.write_hits 0 # DTB write hits 151310585Sandreas.hansson@arm.comsystem.cpu1.itb.write_misses 0 # DTB write misses 151411374Ssteve.reinhardt@amd.comsystem.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed 151510585Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 151611374Ssteve.reinhardt@amd.comsystem.cpu1.itb.flush_tlb_mva_asid 47226 # Number of times TLB was flushed by MVA & ASID 151711374Ssteve.reinhardt@amd.comsystem.cpu1.itb.flush_tlb_asid 1094 # Number of times TLB was flushed by ASID 151811374Ssteve.reinhardt@amd.comsystem.cpu1.itb.flush_entries 28254 # Number of entries that have been flushed from TLB 151910585Sandreas.hansson@arm.comsystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 152010585Sandreas.hansson@arm.comsystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 152110585Sandreas.hansson@arm.comsystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 152211374Ssteve.reinhardt@amd.comsystem.cpu1.itb.perms_faults 225386 # Number of TLB faults due to permissions restrictions 152310585Sandreas.hansson@arm.comsystem.cpu1.itb.read_accesses 0 # DTB read accesses 152410585Sandreas.hansson@arm.comsystem.cpu1.itb.write_accesses 0 # DTB write accesses 152511374Ssteve.reinhardt@amd.comsystem.cpu1.itb.inst_accesses 255764872 # ITB inst accesses 152611374Ssteve.reinhardt@amd.comsystem.cpu1.itb.hits 255703249 # DTB hits 152711374Ssteve.reinhardt@amd.comsystem.cpu1.itb.misses 61623 # DTB misses 152811374Ssteve.reinhardt@amd.comsystem.cpu1.itb.accesses 255764872 # DTB accesses 152911374Ssteve.reinhardt@amd.comsystem.cpu1.numCycles 1013399126 # number of cpu cycles simulated 153010585Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 153110585Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 153211374Ssteve.reinhardt@amd.comsystem.cpu1.committedInsts 463476016 # Number of instructions committed 153311374Ssteve.reinhardt@amd.comsystem.cpu1.committedOps 544549672 # Number of ops (including micro ops) committed 153411374Ssteve.reinhardt@amd.comsystem.cpu1.discardedOps 51973590 # Number of ops (including micro ops) which were discarded before commit 153511374Ssteve.reinhardt@amd.comsystem.cpu1.numFetchSuspends 4681 # Number of times Execute suspended instruction fetching 153611374Ssteve.reinhardt@amd.comsystem.cpu1.quiesceCycles 93896343891 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 153711374Ssteve.reinhardt@amd.comsystem.cpu1.cpi 2.186519 # CPI: cycles per instruction 153811374Ssteve.reinhardt@amd.comsystem.cpu1.ipc 0.457348 # IPC: instructions per cycle 153910585Sandreas.hansson@arm.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 154011374Ssteve.reinhardt@amd.comsystem.cpu1.kern.inst.quiesce 13591 # number of quiesce instructions executed 154111374Ssteve.reinhardt@amd.comsystem.cpu1.tickCycles 759435347 # Number of cycles that the object actually ticked 154211374Ssteve.reinhardt@amd.comsystem.cpu1.idleCycles 253963779 # Total number of cycles that the object has spent stopped 154311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.tags.replacements 5640902 # number of replacements 154411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.tags.tagsinuse 433.747661 # Cycle average of tags in use 154511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.tags.total_refs 160682361 # Total number of references to valid blocks. 154611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.tags.sampled_refs 5641413 # Sample count of references to valid blocks. 154711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.tags.avg_refs 28.482645 # Average number of references to valid blocks. 154811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.tags.warmup_cycle 8381463375500 # Cycle when the warmup percentage was hit. 154911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 433.747661 # Average occupied blocks per requestor 155011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.847163 # Average percentage of cache occupancy 155111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.tags.occ_percent::total 0.847163 # Average percentage of cache occupancy 155211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 155311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id 155411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 397 # Occupied blocks per task id 155511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id 155611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 155711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.tags.tag_accesses 341448433 # Number of tag accesses 155811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.tags.data_accesses 341448433 # Number of data accesses 155911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 82699161 # number of ReadReq hits 156011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_hits::total 82699161 # number of ReadReq hits 156111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 73240702 # number of WriteReq hits 156211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_hits::total 73240702 # number of WriteReq hits 156311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 257576 # number of SoftPFReq hits 156411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.SoftPFReq_hits::total 257576 # number of SoftPFReq hits 156511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_hits::cpu1.data 197387 # number of WriteLineReq hits 156611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_hits::total 197387 # number of WriteLineReq hits 156711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1901357 # number of LoadLockedReq hits 156811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_hits::total 1901357 # number of LoadLockedReq hits 156911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 1855769 # number of StoreCondReq hits 157011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_hits::total 1855769 # number of StoreCondReq hits 157111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_hits::cpu1.data 155939863 # number of demand (read+write) hits 157211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_hits::total 155939863 # number of demand (read+write) hits 157311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_hits::cpu1.data 156197439 # number of overall hits 157411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_hits::total 156197439 # number of overall hits 157511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 3585243 # number of ReadReq misses 157611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_misses::total 3585243 # number of ReadReq misses 157711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 2523734 # number of WriteReq misses 157811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_misses::total 2523734 # number of WriteReq misses 157911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 738365 # number of SoftPFReq misses 158011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.SoftPFReq_misses::total 738365 # number of SoftPFReq misses 158111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_misses::cpu1.data 486988 # number of WriteLineReq misses 158211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_misses::total 486988 # number of WriteLineReq misses 158311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 162310 # number of LoadLockedReq misses 158411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_misses::total 162310 # number of LoadLockedReq misses 158511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 206438 # number of StoreCondReq misses 158611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_misses::total 206438 # number of StoreCondReq misses 158711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_misses::cpu1.data 6108977 # number of demand (read+write) misses 158811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_misses::total 6108977 # number of demand (read+write) misses 158911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_misses::cpu1.data 6847342 # number of overall misses 159011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_misses::total 6847342 # number of overall misses 159111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 60530715500 # number of ReadReq miss cycles 159211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_miss_latency::total 60530715500 # number of ReadReq miss cycles 159311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 58663605500 # number of WriteReq miss cycles 159411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_miss_latency::total 58663605500 # number of WriteReq miss cycles 159511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 22007902000 # number of WriteLineReq miss cycles 159611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_miss_latency::total 22007902000 # number of WriteLineReq miss cycles 159711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2738446000 # number of LoadLockedReq miss cycles 159811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 2738446000 # number of LoadLockedReq miss cycles 159911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5741911000 # number of StoreCondReq miss cycles 160011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 5741911000 # number of StoreCondReq miss cycles 160111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 7112000 # number of StoreCondFailReq miss cycles 160211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::total 7112000 # number of StoreCondFailReq miss cycles 160311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_miss_latency::cpu1.data 119194321000 # number of demand (read+write) miss cycles 160411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_miss_latency::total 119194321000 # number of demand (read+write) miss cycles 160511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_miss_latency::cpu1.data 119194321000 # number of overall miss cycles 160611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_miss_latency::total 119194321000 # number of overall miss cycles 160711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 86284404 # number of ReadReq accesses(hits+misses) 160811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_accesses::total 86284404 # number of ReadReq accesses(hits+misses) 160911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 75764436 # number of WriteReq accesses(hits+misses) 161011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_accesses::total 75764436 # number of WriteReq accesses(hits+misses) 161111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 995941 # number of SoftPFReq accesses(hits+misses) 161211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.SoftPFReq_accesses::total 995941 # number of SoftPFReq accesses(hits+misses) 161311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_accesses::cpu1.data 684375 # number of WriteLineReq accesses(hits+misses) 161411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_accesses::total 684375 # number of WriteLineReq accesses(hits+misses) 161511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2063667 # number of LoadLockedReq accesses(hits+misses) 161611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 2063667 # number of LoadLockedReq accesses(hits+misses) 161711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2062207 # number of StoreCondReq accesses(hits+misses) 161811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_accesses::total 2062207 # number of StoreCondReq accesses(hits+misses) 161911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_accesses::cpu1.data 162048840 # number of demand (read+write) accesses 162011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_accesses::total 162048840 # number of demand (read+write) accesses 162111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_accesses::cpu1.data 163044781 # number of overall (read+write) accesses 162211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_accesses::total 163044781 # number of overall (read+write) accesses 162311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.041551 # miss rate for ReadReq accesses 162411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.041551 # miss rate for ReadReq accesses 162511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.033310 # miss rate for WriteReq accesses 162611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.033310 # miss rate for WriteReq accesses 162711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.741374 # miss rate for SoftPFReq accesses 162811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.741374 # miss rate for SoftPFReq accesses 162911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.711581 # miss rate for WriteLineReq accesses 163011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_miss_rate::total 0.711581 # miss rate for WriteLineReq accesses 163111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078651 # miss rate for LoadLockedReq accesses 163211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078651 # miss rate for LoadLockedReq accesses 163311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100105 # miss rate for StoreCondReq accesses 163411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.100105 # miss rate for StoreCondReq accesses 163511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.037698 # miss rate for demand accesses 163611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_miss_rate::total 0.037698 # miss rate for demand accesses 163711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.041997 # miss rate for overall accesses 163811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_miss_rate::total 0.041997 # miss rate for overall accesses 163911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16883.295079 # average ReadReq miss latency 164011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 16883.295079 # average ReadReq miss latency 164111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23244.765692 # average WriteReq miss latency 164211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 23244.765692 # average WriteReq miss latency 164311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 45191.877418 # average WriteLineReq miss latency 164411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::total 45191.877418 # average WriteLineReq miss latency 164511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16871.702298 # average LoadLockedReq miss latency 164611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16871.702298 # average LoadLockedReq miss latency 164711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27814.215406 # average StoreCondReq miss latency 164811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27814.215406 # average StoreCondReq miss latency 164910636Snilay@cs.wisc.edusystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 165010585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 165111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19511.338969 # average overall miss latency 165211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_avg_miss_latency::total 19511.338969 # average overall miss latency 165311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17407.385377 # average overall miss latency 165411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_avg_miss_latency::total 17407.385377 # average overall miss latency 165510585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 165610585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 165710585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 165810585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 165910585Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 166010585Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 166110585Sandreas.hansson@arm.comsystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 166210585Sandreas.hansson@arm.comsystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 166311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.writebacks::writebacks 5640935 # number of writebacks 166411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.writebacks::total 5640935 # number of writebacks 166511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 429416 # number of ReadReq MSHR hits 166611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 429416 # number of ReadReq MSHR hits 166711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1043359 # number of WriteReq MSHR hits 166811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 1043359 # number of WriteReq MSHR hits 166911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 74 # number of WriteLineReq MSHR hits 167011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_mshr_hits::total 74 # number of WriteLineReq MSHR hits 167111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 42170 # number of LoadLockedReq MSHR hits 167211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 42170 # number of LoadLockedReq MSHR hits 167311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 72 # number of StoreCondReq MSHR hits 167411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_mshr_hits::total 72 # number of StoreCondReq MSHR hits 167511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_mshr_hits::cpu1.data 1472775 # number of demand (read+write) MSHR hits 167611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_mshr_hits::total 1472775 # number of demand (read+write) MSHR hits 167711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_mshr_hits::cpu1.data 1472775 # number of overall MSHR hits 167811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_mshr_hits::total 1472775 # number of overall MSHR hits 167911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3155827 # number of ReadReq MSHR misses 168011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 3155827 # number of ReadReq MSHR misses 168111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1480375 # number of WriteReq MSHR misses 168211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 1480375 # number of WriteReq MSHR misses 168311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 738082 # number of SoftPFReq MSHR misses 168411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::total 738082 # number of SoftPFReq MSHR misses 168511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 486914 # number of WriteLineReq MSHR misses 168611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::total 486914 # number of WriteLineReq MSHR misses 168711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 120140 # number of LoadLockedReq MSHR misses 168811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 120140 # number of LoadLockedReq MSHR misses 168911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 206366 # number of StoreCondReq MSHR misses 169011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 206366 # number of StoreCondReq MSHR misses 169111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.data 4636202 # number of demand (read+write) MSHR misses 169211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_mshr_misses::total 4636202 # number of demand (read+write) MSHR misses 169311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.data 5374284 # number of overall MSHR misses 169411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_mshr_misses::total 5374284 # number of overall MSHR misses 169511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 23242 # number of ReadReq MSHR uncacheable 169611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::total 23242 # number of ReadReq MSHR uncacheable 169711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 22236 # number of WriteReq MSHR uncacheable 169811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::total 22236 # number of WriteReq MSHR uncacheable 169911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 45478 # number of overall MSHR uncacheable misses 170011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::total 45478 # number of overall MSHR uncacheable misses 170111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 47412877500 # number of ReadReq MSHR miss cycles 170211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 47412877500 # number of ReadReq MSHR miss cycles 170311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 34746994000 # number of WriteReq MSHR miss cycles 170411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 34746994000 # number of WriteReq MSHR miss cycles 170511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 19660408500 # number of SoftPFReq MSHR miss cycles 170611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 19660408500 # number of SoftPFReq MSHR miss cycles 170711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 21514132500 # number of WriteLineReq MSHR miss cycles 170811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 21514132500 # number of WriteLineReq MSHR miss cycles 170911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1774236500 # number of LoadLockedReq MSHR miss cycles 171011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1774236500 # number of LoadLockedReq MSHR miss cycles 171111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5529988500 # number of StoreCondReq MSHR miss cycles 171211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5529988500 # number of StoreCondReq MSHR miss cycles 171311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 6729000 # number of StoreCondFailReq MSHR miss cycles 171411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 6729000 # number of StoreCondFailReq MSHR miss cycles 171511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 82159871500 # number of demand (read+write) MSHR miss cycles 171611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 82159871500 # number of demand (read+write) MSHR miss cycles 171711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 101820280000 # number of overall MSHR miss cycles 171811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 101820280000 # number of overall MSHR miss cycles 171911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4292810500 # number of ReadReq MSHR uncacheable cycles 172011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4292810500 # number of ReadReq MSHR uncacheable cycles 172111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 4172773000 # number of WriteReq MSHR uncacheable cycles 172211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 4172773000 # number of WriteReq MSHR uncacheable cycles 172311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 8465583500 # number of overall MSHR uncacheable cycles 172411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 8465583500 # number of overall MSHR uncacheable cycles 172511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036575 # mshr miss rate for ReadReq accesses 172611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036575 # mshr miss rate for ReadReq accesses 172711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019539 # mshr miss rate for WriteReq accesses 172811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019539 # mshr miss rate for WriteReq accesses 172911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.741090 # mshr miss rate for SoftPFReq accesses 173011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.741090 # mshr miss rate for SoftPFReq accesses 173111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.711473 # mshr miss rate for WriteLineReq accesses 173211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.711473 # mshr miss rate for WriteLineReq accesses 173311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058217 # mshr miss rate for LoadLockedReq accesses 173411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.058217 # mshr miss rate for LoadLockedReq accesses 173511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100070 # mshr miss rate for StoreCondReq accesses 173611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100070 # mshr miss rate for StoreCondReq accesses 173711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028610 # mshr miss rate for demand accesses 173811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.028610 # mshr miss rate for demand accesses 173911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032962 # mshr miss rate for overall accesses 174011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.032962 # mshr miss rate for overall accesses 174111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15023.915284 # average ReadReq mshr miss latency 174211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15023.915284 # average ReadReq mshr miss latency 174311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23471.751414 # average WriteReq mshr miss latency 174411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23471.751414 # average WriteReq mshr miss latency 174511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 26637.160234 # average SoftPFReq mshr miss latency 174611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 26637.160234 # average SoftPFReq mshr miss latency 174711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 44184.666081 # average WriteLineReq mshr miss latency 174811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 44184.666081 # average WriteLineReq mshr miss latency 174911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14768.074746 # average LoadLockedReq mshr miss latency 175011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14768.074746 # average LoadLockedReq mshr miss latency 175111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26796.994175 # average StoreCondReq mshr miss latency 175211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26796.994175 # average StoreCondReq mshr miss latency 175310636Snilay@cs.wisc.edusystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 175410585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 175511374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17721.374414 # average overall mshr miss latency 175611374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 17721.374414 # average overall mshr miss latency 175711374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18945.831668 # average overall mshr miss latency 175811374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 18945.831668 # average overall mshr miss latency 175911374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184700.563635 # average ReadReq mshr uncacheable latency 176011374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184700.563635 # average ReadReq mshr uncacheable latency 176111374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 187658.436769 # average WriteReq mshr uncacheable latency 176211374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 187658.436769 # average WriteReq mshr uncacheable latency 176311374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 186146.785259 # average overall mshr uncacheable latency 176411374Ssteve.reinhardt@amd.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 186146.785259 # average overall mshr uncacheable latency 176510585Sandreas.hansson@arm.comsystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 176611374Ssteve.reinhardt@amd.comsystem.cpu1.icache.tags.replacements 9253909 # number of replacements 176711374Ssteve.reinhardt@amd.comsystem.cpu1.icache.tags.tagsinuse 506.772073 # Cycle average of tags in use 176811374Ssteve.reinhardt@amd.comsystem.cpu1.icache.tags.total_refs 246217857 # Total number of references to valid blocks. 176911374Ssteve.reinhardt@amd.comsystem.cpu1.icache.tags.sampled_refs 9254421 # Sample count of references to valid blocks. 177011374Ssteve.reinhardt@amd.comsystem.cpu1.icache.tags.avg_refs 26.605431 # Average number of references to valid blocks. 177111374Ssteve.reinhardt@amd.comsystem.cpu1.icache.tags.warmup_cycle 8381293063000 # Cycle when the warmup percentage was hit. 177211374Ssteve.reinhardt@amd.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 506.772073 # Average occupied blocks per requestor 177311374Ssteve.reinhardt@amd.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.989789 # Average percentage of cache occupancy 177411374Ssteve.reinhardt@amd.comsystem.cpu1.icache.tags.occ_percent::total 0.989789 # Average percentage of cache occupancy 177510585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 177611374Ssteve.reinhardt@amd.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id 177711374Ssteve.reinhardt@amd.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 353 # Occupied blocks per task id 177811374Ssteve.reinhardt@amd.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id 177910585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 178011374Ssteve.reinhardt@amd.comsystem.cpu1.icache.tags.tag_accesses 520199009 # Number of tag accesses 178111374Ssteve.reinhardt@amd.comsystem.cpu1.icache.tags.data_accesses 520199009 # Number of data accesses 178211374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 246217857 # number of ReadReq hits 178311374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_hits::total 246217857 # number of ReadReq hits 178411374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_hits::cpu1.inst 246217857 # number of demand (read+write) hits 178511374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_hits::total 246217857 # number of demand (read+write) hits 178611374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_hits::cpu1.inst 246217857 # number of overall hits 178711374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_hits::total 246217857 # number of overall hits 178811374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 9254432 # number of ReadReq misses 178911374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_misses::total 9254432 # number of ReadReq misses 179011374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_misses::cpu1.inst 9254432 # number of demand (read+write) misses 179111374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_misses::total 9254432 # number of demand (read+write) misses 179211374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_misses::cpu1.inst 9254432 # number of overall misses 179311374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_misses::total 9254432 # number of overall misses 179411374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 97819295000 # number of ReadReq miss cycles 179511374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_miss_latency::total 97819295000 # number of ReadReq miss cycles 179611374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 97819295000 # number of demand (read+write) miss cycles 179711374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_miss_latency::total 97819295000 # number of demand (read+write) miss cycles 179811374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 97819295000 # number of overall miss cycles 179911374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_miss_latency::total 97819295000 # number of overall miss cycles 180011374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 255472289 # number of ReadReq accesses(hits+misses) 180111374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_accesses::total 255472289 # number of ReadReq accesses(hits+misses) 180211374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_accesses::cpu1.inst 255472289 # number of demand (read+write) accesses 180311374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_accesses::total 255472289 # number of demand (read+write) accesses 180411374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_accesses::cpu1.inst 255472289 # number of overall (read+write) accesses 180511374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_accesses::total 255472289 # number of overall (read+write) accesses 180611374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.036225 # miss rate for ReadReq accesses 180711374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.036225 # miss rate for ReadReq accesses 180811374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.036225 # miss rate for demand accesses 180911374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_miss_rate::total 0.036225 # miss rate for demand accesses 181011374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.036225 # miss rate for overall accesses 181111374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_miss_rate::total 0.036225 # miss rate for overall accesses 181211374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10569.994463 # average ReadReq miss latency 181311374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 10569.994463 # average ReadReq miss latency 181411374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10569.994463 # average overall miss latency 181511374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_avg_miss_latency::total 10569.994463 # average overall miss latency 181611374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10569.994463 # average overall miss latency 181711374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_avg_miss_latency::total 10569.994463 # average overall miss latency 181810585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 181910585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 182010585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 182110585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 182210585Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 182310585Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 182410585Sandreas.hansson@arm.comsystem.cpu1.icache.fast_writes 0 # number of fast writes performed 182510585Sandreas.hansson@arm.comsystem.cpu1.icache.cache_copies 0 # number of cache copies performed 182611374Ssteve.reinhardt@amd.comsystem.cpu1.icache.writebacks::writebacks 9253909 # number of writebacks 182711374Ssteve.reinhardt@amd.comsystem.cpu1.icache.writebacks::total 9253909 # number of writebacks 182811374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9254432 # number of ReadReq MSHR misses 182911374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_mshr_misses::total 9254432 # number of ReadReq MSHR misses 183011374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 9254432 # number of demand (read+write) MSHR misses 183111374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_mshr_misses::total 9254432 # number of demand (read+write) MSHR misses 183211374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 9254432 # number of overall MSHR misses 183311374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_mshr_misses::total 9254432 # number of overall MSHR misses 183411353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable 183511353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::total 93 # number of ReadReq MSHR uncacheable 183611353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses 183711353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::total 93 # number of overall MSHR uncacheable misses 183811374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 93192079500 # number of ReadReq MSHR miss cycles 183911374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 93192079500 # number of ReadReq MSHR miss cycles 184011374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 93192079500 # number of demand (read+write) MSHR miss cycles 184111374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_mshr_miss_latency::total 93192079500 # number of demand (read+write) MSHR miss cycles 184211374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 93192079500 # number of overall MSHR miss cycles 184311374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_mshr_miss_latency::total 93192079500 # number of overall MSHR miss cycles 184411353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13081000 # number of ReadReq MSHR uncacheable cycles 184511353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13081000 # number of ReadReq MSHR uncacheable cycles 184611353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13081000 # number of overall MSHR uncacheable cycles 184711353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::total 13081000 # number of overall MSHR uncacheable cycles 184811374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.036225 # mshr miss rate for ReadReq accesses 184911374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.036225 # mshr miss rate for ReadReq accesses 185011374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.036225 # mshr miss rate for demand accesses 185111374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.036225 # mshr miss rate for demand accesses 185211374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.036225 # mshr miss rate for overall accesses 185311374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.036225 # mshr miss rate for overall accesses 185411374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10069.994517 # average ReadReq mshr miss latency 185511374Ssteve.reinhardt@amd.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10069.994517 # average ReadReq mshr miss latency 185611374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10069.994517 # average overall mshr miss latency 185711374Ssteve.reinhardt@amd.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 10069.994517 # average overall mshr miss latency 185811374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10069.994517 # average overall mshr miss latency 185911374Ssteve.reinhardt@amd.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 10069.994517 # average overall mshr miss latency 186011353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 140655.913978 # average ReadReq mshr uncacheable latency 186111353Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 140655.913978 # average ReadReq mshr uncacheable latency 186211353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 140655.913978 # average overall mshr uncacheable latency 186311353Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 140655.913978 # average overall mshr uncacheable latency 186410585Sandreas.hansson@arm.comsystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 186511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.prefetcher.num_hwpf_issued 7972481 # number of hwpf issued 186611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.prefetcher.pfIdentified 7973767 # number of prefetch candidates identified 186711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.prefetcher.pfBufferHit 1132 # number of redundant prefetches already in prefetch queue 186810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 186910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 187011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.prefetcher.pfSpanPage 946401 # number of prefetches not generated due to page crossing 187111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.replacements 2682833 # number of replacements 187211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.tagsinuse 13443.137658 # Cycle average of tags in use 187311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.total_refs 23351564 # Total number of references to valid blocks. 187411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.sampled_refs 2698948 # Sample count of references to valid blocks. 187511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.avg_refs 8.652099 # Average number of references to valid blocks. 187611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.warmup_cycle 10051011039000 # Cycle when the warmup percentage was hit. 187711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 12664.163497 # Average occupied blocks per requestor 187811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 64.427658 # Average occupied blocks per requestor 187911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 52.788670 # Average occupied blocks per requestor 188011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 661.757834 # Average occupied blocks per requestor 188111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.772959 # Average percentage of cache occupancy 188211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003932 # Average percentage of cache occupancy 188311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003222 # Average percentage of cache occupancy 188411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.040390 # Average percentage of cache occupancy 188511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.occ_percent::total 0.820504 # Average percentage of cache occupancy 188611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1022 1261 # Occupied blocks per task id 188711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 46 # Occupied blocks per task id 188811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 14808 # Occupied blocks per task id 188911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::1 5 # Occupied blocks per task id 189011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::2 338 # Occupied blocks per task id 189111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::3 798 # Occupied blocks per task id 189211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::4 120 # Occupied blocks per task id 189311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 14 # Occupied blocks per task id 189411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 29 # Occupied blocks per task id 189511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 189611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id 189711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1053 # Occupied blocks per task id 189811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5404 # Occupied blocks per task id 189911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7290 # Occupied blocks per task id 190011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 973 # Occupied blocks per task id 190111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1022 0.076965 # Percentage of cache occupancy per task id 190211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002808 # Percentage of cache occupancy per task id 190311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903809 # Percentage of cache occupancy per task id 190411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.tag_accesses 504035480 # Number of tag accesses 190511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.tags.data_accesses 504035480 # Number of data accesses 190611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 619167 # number of ReadReq hits 190711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 157082 # number of ReadReq hits 190811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_hits::total 776249 # number of ReadReq hits 190911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WritebackDirty_hits::writebacks 3580112 # number of WritebackDirty hits 191011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WritebackDirty_hits::total 3580112 # number of WritebackDirty hits 191111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WritebackClean_hits::writebacks 11312106 # number of WritebackClean hits 191211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WritebackClean_hits::total 11312106 # number of WritebackClean hits 191311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_hits::cpu1.data 786 # number of UpgradeReq hits 191411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_hits::total 786 # number of UpgradeReq hits 191511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 968681 # number of ReadExReq hits 191611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_hits::total 968681 # number of ReadExReq hits 191711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8504758 # number of ReadCleanReq hits 191811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 8504758 # number of ReadCleanReq hits 191911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2930307 # number of ReadSharedReq hits 192011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 2930307 # number of ReadSharedReq hits 192111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_hits::cpu1.data 167226 # number of InvalidateReq hits 192211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_hits::total 167226 # number of InvalidateReq hits 192311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 619167 # number of demand (read+write) hits 192411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 157082 # number of demand (read+write) hits 192511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 8504758 # number of demand (read+write) hits 192611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_hits::cpu1.data 3898988 # number of demand (read+write) hits 192711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_hits::total 13179995 # number of demand (read+write) hits 192811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 619167 # number of overall hits 192911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 157082 # number of overall hits 193011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 8504758 # number of overall hits 193111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_hits::cpu1.data 3898988 # number of overall hits 193211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_hits::total 13179995 # number of overall hits 193311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 13008 # number of ReadReq misses 193411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8398 # number of ReadReq misses 193511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_misses::total 21406 # number of ReadReq misses 193611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WritebackDirty_misses::writebacks 3 # number of WritebackDirty misses 193711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WritebackDirty_misses::total 3 # number of WritebackDirty misses 193811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 242430 # number of UpgradeReq misses 193911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_misses::total 242430 # number of UpgradeReq misses 194011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 206357 # number of SCUpgradeReq misses 194111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 206357 # number of SCUpgradeReq misses 194211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 9 # number of SCUpgradeFailReq misses 194311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::total 9 # number of SCUpgradeFailReq misses 194411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 271269 # number of ReadExReq misses 194511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_misses::total 271269 # number of ReadExReq misses 194611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 749674 # number of ReadCleanReq misses 194711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 749674 # number of ReadCleanReq misses 194811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1083420 # number of ReadSharedReq misses 194911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 1083420 # number of ReadSharedReq misses 195011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_misses::cpu1.data 317410 # number of InvalidateReq misses 195111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_misses::total 317410 # number of InvalidateReq misses 195211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 13008 # number of demand (read+write) misses 195311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 8398 # number of demand (read+write) misses 195411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 749674 # number of demand (read+write) misses 195511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_misses::cpu1.data 1354689 # number of demand (read+write) misses 195611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_misses::total 2125769 # number of demand (read+write) misses 195711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 13008 # number of overall misses 195811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 8398 # number of overall misses 195911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 749674 # number of overall misses 196011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_misses::cpu1.data 1354689 # number of overall misses 196111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_misses::total 2125769 # number of overall misses 196211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 644553000 # number of ReadReq miss cycles 196311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 465440500 # number of ReadReq miss cycles 196411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_miss_latency::total 1109993500 # number of ReadReq miss cycles 196511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3394976000 # number of UpgradeReq miss cycles 196611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::total 3394976000 # number of UpgradeReq miss cycles 196711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 2059365000 # number of SCUpgradeReq miss cycles 196811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::total 2059365000 # number of SCUpgradeReq miss cycles 196911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 6608499 # number of SCUpgradeFailReq miss cycles 197011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 6608499 # number of SCUpgradeFailReq miss cycles 197111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 17354243497 # number of ReadExReq miss cycles 197211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_miss_latency::total 17354243497 # number of ReadExReq miss cycles 197311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 27964377000 # number of ReadCleanReq miss cycles 197411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::total 27964377000 # number of ReadCleanReq miss cycles 197511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 43468216991 # number of ReadSharedReq miss cycles 197611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::total 43468216991 # number of ReadSharedReq miss cycles 197711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 430263500 # number of InvalidateReq miss cycles 197811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::total 430263500 # number of InvalidateReq miss cycles 197911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 644553000 # number of demand (read+write) miss cycles 198011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 465440500 # number of demand (read+write) miss cycles 198111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.inst 27964377000 # number of demand (read+write) miss cycles 198211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.data 60822460488 # number of demand (read+write) miss cycles 198311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_miss_latency::total 89896830988 # number of demand (read+write) miss cycles 198411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 644553000 # number of overall miss cycles 198511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 465440500 # number of overall miss cycles 198611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.inst 27964377000 # number of overall miss cycles 198711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.data 60822460488 # number of overall miss cycles 198811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_miss_latency::total 89896830988 # number of overall miss cycles 198911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 632175 # number of ReadReq accesses(hits+misses) 199011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 165480 # number of ReadReq accesses(hits+misses) 199111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_accesses::total 797655 # number of ReadReq accesses(hits+misses) 199211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WritebackDirty_accesses::writebacks 3580115 # number of WritebackDirty accesses(hits+misses) 199311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WritebackDirty_accesses::total 3580115 # number of WritebackDirty accesses(hits+misses) 199411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WritebackClean_accesses::writebacks 11312106 # number of WritebackClean accesses(hits+misses) 199511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WritebackClean_accesses::total 11312106 # number of WritebackClean accesses(hits+misses) 199611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 243216 # number of UpgradeReq accesses(hits+misses) 199711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 243216 # number of UpgradeReq accesses(hits+misses) 199811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 206357 # number of SCUpgradeReq accesses(hits+misses) 199911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 206357 # number of SCUpgradeReq accesses(hits+misses) 200011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 9 # number of SCUpgradeFailReq accesses(hits+misses) 200111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::total 9 # number of SCUpgradeFailReq accesses(hits+misses) 200211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1239950 # number of ReadExReq accesses(hits+misses) 200311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_accesses::total 1239950 # number of ReadExReq accesses(hits+misses) 200411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 9254432 # number of ReadCleanReq accesses(hits+misses) 200511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 9254432 # number of ReadCleanReq accesses(hits+misses) 200611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4013727 # number of ReadSharedReq accesses(hits+misses) 200711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 4013727 # number of ReadSharedReq accesses(hits+misses) 200811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 484636 # number of InvalidateReq accesses(hits+misses) 200911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_accesses::total 484636 # number of InvalidateReq accesses(hits+misses) 201011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 632175 # number of demand (read+write) accesses 201111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 165480 # number of demand (read+write) accesses 201211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 9254432 # number of demand (read+write) accesses 201311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 5253677 # number of demand (read+write) accesses 201411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_accesses::total 15305764 # number of demand (read+write) accesses 201511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 632175 # number of overall (read+write) accesses 201611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 165480 # number of overall (read+write) accesses 201711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 9254432 # number of overall (read+write) accesses 201811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 5253677 # number of overall (read+write) accesses 201911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_accesses::total 15305764 # number of overall (read+write) accesses 202011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.020577 # miss rate for ReadReq accesses 202111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.050749 # miss rate for ReadReq accesses 202211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.026836 # miss rate for ReadReq accesses 202311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses 202411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses 202511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.996768 # miss rate for UpgradeReq accesses 202611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 0.996768 # miss rate for UpgradeReq accesses 202711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 202811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 202910636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 203010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 203111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.218774 # miss rate for ReadExReq accesses 203211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.218774 # miss rate for ReadExReq accesses 203311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.081007 # miss rate for ReadCleanReq accesses 203411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.081007 # miss rate for ReadCleanReq accesses 203511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.269929 # miss rate for ReadSharedReq accesses 203611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.269929 # miss rate for ReadSharedReq accesses 203711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.654945 # miss rate for InvalidateReq accesses 203811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::total 0.654945 # miss rate for InvalidateReq accesses 203911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.020577 # miss rate for demand accesses 204011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.050749 # miss rate for demand accesses 204111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.081007 # miss rate for demand accesses 204211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.257855 # miss rate for demand accesses 204311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_miss_rate::total 0.138887 # miss rate for demand accesses 204411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.020577 # miss rate for overall accesses 204511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.050749 # miss rate for overall accesses 204611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.081007 # miss rate for overall accesses 204711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.257855 # miss rate for overall accesses 204811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_miss_rate::total 0.138887 # miss rate for overall accesses 204911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 49550.507380 # average ReadReq miss latency 205011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 55422.779233 # average ReadReq miss latency 205111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::total 51854.316547 # average ReadReq miss latency 205211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 14003.943406 # average UpgradeReq miss latency 205311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 14003.943406 # average UpgradeReq miss latency 205411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 9979.622693 # average SCUpgradeReq miss latency 205511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 9979.622693 # average SCUpgradeReq miss latency 205611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 734277.666667 # average SCUpgradeFailReq miss latency 205711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 734277.666667 # average SCUpgradeFailReq miss latency 205811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 63974.296720 # average ReadExReq miss latency 205911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::total 63974.296720 # average ReadExReq miss latency 206011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 37302.049958 # average ReadCleanReq miss latency 206111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 37302.049958 # average ReadCleanReq miss latency 206211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 40121.298288 # average ReadSharedReq miss latency 206311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 40121.298288 # average ReadSharedReq miss latency 206411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1355.544879 # average InvalidateReq miss latency 206511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1355.544879 # average InvalidateReq miss latency 206611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 49550.507380 # average overall miss latency 206711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 55422.779233 # average overall miss latency 206811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 37302.049958 # average overall miss latency 206911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 44897.729655 # average overall miss latency 207011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_avg_miss_latency::total 42289.087379 # average overall miss latency 207111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 49550.507380 # average overall miss latency 207211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 55422.779233 # average overall miss latency 207311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 37302.049958 # average overall miss latency 207411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 44897.729655 # average overall miss latency 207511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_avg_miss_latency::total 42289.087379 # average overall miss latency 207611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.blocked_cycles::no_mshrs 34 # number of cycles access was blocked 207710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 207811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked 207910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 208011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked 208110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 208210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.fast_writes 0 # number of fast writes performed 208310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.cache_copies 0 # number of cache copies performed 208411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.writebacks::writebacks 1388382 # number of writebacks 208511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.writebacks::total 1388382 # number of writebacks 208611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 1 # number of ReadReq MSHR hits 208711353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 208811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 13745 # number of ReadExReq MSHR hits 208911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::total 13745 # number of ReadExReq MSHR hits 209011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 8 # number of ReadCleanReq MSHR hits 209111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_mshr_hits::total 8 # number of ReadCleanReq MSHR hits 209211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 1083 # number of ReadSharedReq MSHR hits 209311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::total 1083 # number of ReadSharedReq MSHR hits 209411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 4 # number of InvalidateReq MSHR hits 209511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_mshr_hits::total 4 # number of InvalidateReq MSHR hits 209611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 1 # number of demand (read+write) MSHR hits 209711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits 209811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.data 14828 # number of demand (read+write) MSHR hits 209911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_mshr_hits::total 14837 # number of demand (read+write) MSHR hits 210011353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 1 # number of overall MSHR hits 210111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits 210211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.data 14828 # number of overall MSHR hits 210311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_hits::total 14837 # number of overall MSHR hits 210411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 13008 # number of ReadReq MSHR misses 210511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8397 # number of ReadReq MSHR misses 210611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_mshr_misses::total 21405 # number of ReadReq MSHR misses 210711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 3 # number of WritebackDirty MSHR misses 210811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WritebackDirty_mshr_misses::total 3 # number of WritebackDirty MSHR misses 210911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 882624 # number of HardPFReq MSHR misses 211011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::total 882624 # number of HardPFReq MSHR misses 211111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 242430 # number of UpgradeReq MSHR misses 211211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::total 242430 # number of UpgradeReq MSHR misses 211311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 206357 # number of SCUpgradeReq MSHR misses 211411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 206357 # number of SCUpgradeReq MSHR misses 211511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 9 # number of SCUpgradeFailReq MSHR misses 211611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 9 # number of SCUpgradeFailReq MSHR misses 211711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 257524 # number of ReadExReq MSHR misses 211811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::total 257524 # number of ReadExReq MSHR misses 211911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 749666 # number of ReadCleanReq MSHR misses 212011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::total 749666 # number of ReadCleanReq MSHR misses 212111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 1082337 # number of ReadSharedReq MSHR misses 212211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::total 1082337 # number of ReadSharedReq MSHR misses 212311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 317406 # number of InvalidateReq MSHR misses 212411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::total 317406 # number of InvalidateReq MSHR misses 212511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 13008 # number of demand (read+write) MSHR misses 212611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8397 # number of demand (read+write) MSHR misses 212711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.inst 749666 # number of demand (read+write) MSHR misses 212811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.data 1339861 # number of demand (read+write) MSHR misses 212911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_mshr_misses::total 2110932 # number of demand (read+write) MSHR misses 213011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 13008 # number of overall MSHR misses 213111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8397 # number of overall MSHR misses 213211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.inst 749666 # number of overall MSHR misses 213311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.data 1339861 # number of overall MSHR misses 213411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 882624 # number of overall MSHR misses 213511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_misses::total 2993556 # number of overall MSHR misses 213611353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable 213711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 23242 # number of ReadReq MSHR uncacheable 213811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::total 23335 # number of ReadReq MSHR uncacheable 213911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 22236 # number of WriteReq MSHR uncacheable 214011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::total 22236 # number of WriteReq MSHR uncacheable 214111353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses 214211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 45478 # number of overall MSHR uncacheable misses 214311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::total 45571 # number of overall MSHR uncacheable misses 214411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 566505000 # number of ReadReq MSHR miss cycles 214511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 415038000 # number of ReadReq MSHR miss cycles 214611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::total 981543000 # number of ReadReq MSHR miss cycles 214711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 64551953809 # number of HardPFReq MSHR miss cycles 214811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 64551953809 # number of HardPFReq MSHR miss cycles 214911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 7440388995 # number of UpgradeReq MSHR miss cycles 215011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 7440388995 # number of UpgradeReq MSHR miss cycles 215111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3978239996 # number of SCUpgradeReq MSHR miss cycles 215211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3978239996 # number of SCUpgradeReq MSHR miss cycles 215311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 6134499 # number of SCUpgradeFailReq MSHR miss cycles 215411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 6134499 # number of SCUpgradeFailReq MSHR miss cycles 215511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 13620219997 # number of ReadExReq MSHR miss cycles 215611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 13620219997 # number of ReadExReq MSHR miss cycles 215711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 23466170000 # number of ReadCleanReq MSHR miss cycles 215811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 23466170000 # number of ReadCleanReq MSHR miss cycles 215911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 36889013991 # number of ReadSharedReq MSHR miss cycles 216011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 36889013991 # number of ReadSharedReq MSHR miss cycles 216111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 17653665500 # number of InvalidateReq MSHR miss cycles 216211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 17653665500 # number of InvalidateReq MSHR miss cycles 216311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 566505000 # number of demand (read+write) MSHR miss cycles 216411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 415038000 # number of demand (read+write) MSHR miss cycles 216511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 23466170000 # number of demand (read+write) MSHR miss cycles 216611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 50509233988 # number of demand (read+write) MSHR miss cycles 216711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_mshr_miss_latency::total 74956946988 # number of demand (read+write) MSHR miss cycles 216811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 566505000 # number of overall MSHR miss cycles 216911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 415038000 # number of overall MSHR miss cycles 217011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 23466170000 # number of overall MSHR miss cycles 217111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 50509233988 # number of overall MSHR miss cycles 217211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 64551953809 # number of overall MSHR miss cycles 217311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_miss_latency::total 139508900797 # number of overall MSHR miss cycles 217411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12337000 # number of ReadReq MSHR uncacheable cycles 217511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 4106803500 # number of ReadReq MSHR uncacheable cycles 217611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 4119140500 # number of ReadReq MSHR uncacheable cycles 217711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 4005950500 # number of WriteReq MSHR uncacheable cycles 217811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 4005950500 # number of WriteReq MSHR uncacheable cycles 217911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12337000 # number of overall MSHR uncacheable cycles 218011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 8112754000 # number of overall MSHR uncacheable cycles 218111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::total 8125091000 # number of overall MSHR uncacheable cycles 218211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020577 # mshr miss rate for ReadReq accesses 218311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.050743 # mshr miss rate for ReadReq accesses 218411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.026835 # mshr miss rate for ReadReq accesses 218511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses 218611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses 218710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 218810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 218911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.996768 # mshr miss rate for UpgradeReq accesses 219011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.996768 # mshr miss rate for UpgradeReq accesses 219111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 219211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 219310636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 219410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 219511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.207689 # mshr miss rate for ReadExReq accesses 219611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.207689 # mshr miss rate for ReadExReq accesses 219711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.081006 # mshr miss rate for ReadCleanReq accesses 219811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.081006 # mshr miss rate for ReadCleanReq accesses 219911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.269659 # mshr miss rate for ReadSharedReq accesses 220011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.269659 # mshr miss rate for ReadSharedReq accesses 220111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.654937 # mshr miss rate for InvalidateReq accesses 220211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.654937 # mshr miss rate for InvalidateReq accesses 220311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020577 # mshr miss rate for demand accesses 220411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.050743 # mshr miss rate for demand accesses 220511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.081006 # mshr miss rate for demand accesses 220611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.255033 # mshr miss rate for demand accesses 220711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_mshr_miss_rate::total 0.137917 # mshr miss rate for demand accesses 220811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020577 # mshr miss rate for overall accesses 220911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050743 # mshr miss rate for overall accesses 221011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.081006 # mshr miss rate for overall accesses 221111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.255033 # mshr miss rate for overall accesses 221210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 221311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_mshr_miss_rate::total 0.195584 # mshr miss rate for overall accesses 221411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 43550.507380 # average ReadReq mshr miss latency 221511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 49426.938192 # average ReadReq mshr miss latency 221611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 45855.781359 # average ReadReq mshr miss latency 221711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 73136.413477 # average HardPFReq mshr miss latency 221811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 73136.413477 # average HardPFReq mshr miss latency 221911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 30690.875696 # average UpgradeReq mshr miss latency 222011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30690.875696 # average UpgradeReq mshr miss latency 222111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19278.434926 # average SCUpgradeReq mshr miss latency 222211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19278.434926 # average SCUpgradeReq mshr miss latency 222311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 681611 # average SCUpgradeFailReq mshr miss latency 222411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 681611 # average SCUpgradeFailReq mshr miss latency 222511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 52889.128769 # average ReadExReq mshr miss latency 222611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 52889.128769 # average ReadExReq mshr miss latency 222711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31302.166565 # average ReadCleanReq mshr miss latency 222811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31302.166565 # average ReadCleanReq mshr miss latency 222911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 34082.743167 # average ReadSharedReq mshr miss latency 223011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 34082.743167 # average ReadSharedReq mshr miss latency 223111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 55618.562661 # average InvalidateReq mshr miss latency 223211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 55618.562661 # average InvalidateReq mshr miss latency 223311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 43550.507380 # average overall mshr miss latency 223411374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 49426.938192 # average overall mshr miss latency 223511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31302.166565 # average overall mshr miss latency 223611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 37697.368599 # average overall mshr miss latency 223711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::total 35508.934910 # average overall mshr miss latency 223811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 43550.507380 # average overall mshr miss latency 223911374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 49426.938192 # average overall mshr miss latency 224011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31302.166565 # average overall mshr miss latency 224111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 37697.368599 # average overall mshr miss latency 224211374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 73136.413477 # average overall mshr miss latency 224311374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::total 46603.070327 # average overall mshr miss latency 224411353Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132655.913978 # average ReadReq mshr uncacheable latency 224511374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176697.508820 # average ReadReq mshr uncacheable latency 224611374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 176521.984144 # average ReadReq mshr uncacheable latency 224711374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 180156.075733 # average WriteReq mshr uncacheable latency 224811374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 180156.075733 # average WriteReq mshr uncacheable latency 224911353Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132655.913978 # average overall mshr uncacheable latency 225011374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 178388.539514 # average overall mshr uncacheable latency 225111374Ssteve.reinhardt@amd.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 178295.209673 # average overall mshr uncacheable latency 225210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 225311374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.snoop_filter.tot_requests 30687781 # Total number of requests made to the snoop filter. 225411374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_requests 15695228 # Number of requests hitting in the snoop filter with a single holder of the requested data. 225511374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2622 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 225611374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.snoop_filter.tot_snoops 2305562 # Total number of snoops made to the snoop filter. 225711374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2305078 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 225811374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 484 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 225911374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 905031 # Transaction distribution 226011374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 14265709 # Transaction distribution 226111374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution 226211374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 22236 # Transaction distribution 226311374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 22236 # Transaction distribution 226411374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::WritebackDirty 4974934 # Transaction distribution 226511374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::WritebackClean 11314728 # Transaction distribution 226611374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::CleanEvict 3212624 # Transaction distribution 226711374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::HardPFReq 1143576 # Transaction distribution 226811374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 456570 # Transaction distribution 226911374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 371810 # Transaction distribution 227011374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 515155 # Transaction distribution 227111374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 96 # Transaction distribution 227211374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::UpgradeFailResp 166 # Transaction distribution 227311374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 1270102 # Transaction distribution 227411374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 1247161 # Transaction distribution 227511374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 9254432 # Transaction distribution 227611374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 5086529 # Transaction distribution 227711374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::InvalidateReq 540215 # Transaction distribution 227811374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.trans_dist::InvalidateResp 484636 # Transaction distribution 227911374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 27762958 # Packet count per connected master and slave (bytes) 228011374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18273152 # Packet count per connected master and slave (bytes) 228111374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 349398 # Packet count per connected master and slave (bytes) 228211374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1329953 # Packet count per connected master and slave (bytes) 228311374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.pkt_count::total 47715461 # Packet count per connected master and slave (bytes) 228411374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1184539712 # Cumulative packet size per connected master and slave (bytes) 228511374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 703787179 # Cumulative packet size per connected master and slave (bytes) 228611374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1323840 # Cumulative packet size per connected master and slave (bytes) 228711374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 5057400 # Cumulative packet size per connected master and slave (bytes) 228811374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.pkt_size::total 1894708131 # Cumulative packet size per connected master and slave (bytes) 228911374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.snoops 7537959 # Total snoops (count) 229011374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.snoop_fanout::samples 23658040 # Request fanout histogram 229111374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.snoop_fanout::mean 0.112405 # Request fanout histogram 229211374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.315929 # Request fanout histogram 229310585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 229411374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.snoop_fanout::0 20999234 88.76% 88.76% # Request fanout histogram 229511374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.snoop_fanout::1 2658322 11.24% 100.00% # Request fanout histogram 229611374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.snoop_fanout::2 484 0.00% 100.00% # Request fanout histogram 229710585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 229811138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 229910827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 230011374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.snoop_fanout::total 23658040 # Request fanout histogram 230111374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.reqLayer0.occupancy 30538190977 # Layer occupancy (ticks) 230211201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 230311374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.snoopLayer0.occupancy 182787124 # Layer occupancy (ticks) 230410585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 230511374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.respLayer0.occupancy 13885672200 # Layer occupancy (ticks) 230610585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 230711374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.respLayer1.occupancy 8385983653 # Layer occupancy (ticks) 230810585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 230911374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.respLayer2.occupancy 183975884 # Layer occupancy (ticks) 231010585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 231111374Ssteve.reinhardt@amd.comsystem.cpu1.toL2Bus.respLayer3.occupancy 697921212 # Layer occupancy (ticks) 231210585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 231311374Ssteve.reinhardt@amd.comsystem.iobus.trans_dist::ReadReq 40434 # Transaction distribution 231411374Ssteve.reinhardt@amd.comsystem.iobus.trans_dist::ReadResp 40434 # Transaction distribution 231511353Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 136979 # Transaction distribution 231611353Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 136979 # Transaction distribution 231711374Ssteve.reinhardt@amd.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47874 # Packet count per connected master and slave (bytes) 231810585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 231911245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 232010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 232110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 232210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 232310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 232410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 232510585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 232610585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 232710585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 232811353Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29756 # Packet count per connected master and slave (bytes) 232910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 233011374Ssteve.reinhardt@amd.comsystem.iobus.pkt_count_system.bridge.master::total 122964 # Packet count per connected master and slave (bytes) 233111374Ssteve.reinhardt@amd.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231782 # Packet count per connected master and slave (bytes) 233211374Ssteve.reinhardt@amd.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231782 # Packet count per connected master and slave (bytes) 233310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 233410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 233511374Ssteve.reinhardt@amd.comsystem.iobus.pkt_count::total 354826 # Packet count per connected master and slave (bytes) 233611374Ssteve.reinhardt@amd.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47894 # Cumulative packet size per connected master and slave (bytes) 233710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 233811245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 233910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 234010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 234110585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 234210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 234310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 234410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 234510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 234610585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 234711353Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17674 # Cumulative packet size per connected master and slave (bytes) 234810585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 234911374Ssteve.reinhardt@amd.comsystem.iobus.pkt_size_system.bridge.master::total 156002 # Cumulative packet size per connected master and slave (bytes) 235011374Ssteve.reinhardt@amd.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355480 # Cumulative packet size per connected master and slave (bytes) 235111374Ssteve.reinhardt@amd.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7355480 # Cumulative packet size per connected master and slave (bytes) 235210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 235310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 235411374Ssteve.reinhardt@amd.comsystem.iobus.pkt_size::total 7513568 # Cumulative packet size per connected master and slave (bytes) 235511374Ssteve.reinhardt@amd.comsystem.iobus.reqLayer0.occupancy 47273505 # Layer occupancy (ticks) 235610585Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 235711353Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) 235810585Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 235911374Ssteve.reinhardt@amd.comsystem.iobus.reqLayer2.occupancy 324000 # Layer occupancy (ticks) 236010585Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 236111353Sandreas.hansson@arm.comsystem.iobus.reqLayer3.occupancy 9000 # Layer occupancy (ticks) 236210585Sandreas.hansson@arm.comsystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 236311374Ssteve.reinhardt@amd.comsystem.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) 236411245Sandreas.sandberg@arm.comsystem.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 236511374Ssteve.reinhardt@amd.comsystem.iobus.reqLayer10.occupancy 8500 # Layer occupancy (ticks) 236610585Sandreas.hansson@arm.comsystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 236711353Sandreas.hansson@arm.comsystem.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) 236810585Sandreas.hansson@arm.comsystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 236911374Ssteve.reinhardt@amd.comsystem.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) 237010585Sandreas.hansson@arm.comsystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 237111374Ssteve.reinhardt@amd.comsystem.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 237210585Sandreas.hansson@arm.comsystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 237311353Sandreas.hansson@arm.comsystem.iobus.reqLayer16.occupancy 15000 # Layer occupancy (ticks) 237410585Sandreas.hansson@arm.comsystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 237511374Ssteve.reinhardt@amd.comsystem.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 237610585Sandreas.hansson@arm.comsystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 237711374Ssteve.reinhardt@amd.comsystem.iobus.reqLayer23.occupancy 26273501 # Layer occupancy (ticks) 237810585Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 237911374Ssteve.reinhardt@amd.comsystem.iobus.reqLayer24.occupancy 36398000 # Layer occupancy (ticks) 238010585Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 238111374Ssteve.reinhardt@amd.comsystem.iobus.reqLayer25.occupancy 568842992 # Layer occupancy (ticks) 238210585Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 238311374Ssteve.reinhardt@amd.comsystem.iobus.respLayer0.occupancy 92972000 # Layer occupancy (ticks) 238410585Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 238511374Ssteve.reinhardt@amd.comsystem.iobus.respLayer3.occupancy 148222000 # Layer occupancy (ticks) 238610585Sandreas.hansson@arm.comsystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 238710892Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 238810585Sandreas.hansson@arm.comsystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 238911374Ssteve.reinhardt@amd.comsystem.iocache.tags.replacements 115872 # number of replacements 239011374Ssteve.reinhardt@amd.comsystem.iocache.tags.tagsinuse 11.252872 # Cycle average of tags in use 239111336Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 239211374Ssteve.reinhardt@amd.comsystem.iocache.tags.sampled_refs 115888 # Sample count of references to valid blocks. 239311336Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 239411374Ssteve.reinhardt@amd.comsystem.iocache.tags.warmup_cycle 9138217056000 # Cycle when the warmup percentage was hit. 239511374Ssteve.reinhardt@amd.comsystem.iocache.tags.occ_blocks::realview.ethernet 3.833219 # Average occupied blocks per requestor 239611374Ssteve.reinhardt@amd.comsystem.iocache.tags.occ_blocks::realview.ide 7.419652 # Average occupied blocks per requestor 239711374Ssteve.reinhardt@amd.comsystem.iocache.tags.occ_percent::realview.ethernet 0.239576 # Average percentage of cache occupancy 239811374Ssteve.reinhardt@amd.comsystem.iocache.tags.occ_percent::realview.ide 0.463728 # Average percentage of cache occupancy 239911374Ssteve.reinhardt@amd.comsystem.iocache.tags.occ_percent::total 0.703304 # Average percentage of cache occupancy 240010585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 240110827Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 240210585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 240311374Ssteve.reinhardt@amd.comsystem.iocache.tags.tag_accesses 1043376 # Number of tag accesses 240411374Ssteve.reinhardt@amd.comsystem.iocache.tags.data_accesses 1043376 # Number of data accesses 240510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 240611374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_misses::realview.ide 8907 # number of ReadReq misses 240711374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_misses::total 8944 # number of ReadReq misses 240810585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 240910585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 241011336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses 241111336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses 241210585Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 241311374Ssteve.reinhardt@amd.comsystem.iocache.demand_misses::realview.ide 8907 # number of demand (read+write) misses 241411374Ssteve.reinhardt@amd.comsystem.iocache.demand_misses::total 8947 # number of demand (read+write) misses 241510585Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 241611374Ssteve.reinhardt@amd.comsystem.iocache.overall_misses::realview.ide 8907 # number of overall misses 241711374Ssteve.reinhardt@amd.comsystem.iocache.overall_misses::total 8947 # number of overall misses 241811374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5277000 # number of ReadReq miss cycles 241911374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_miss_latency::realview.ide 1705079977 # number of ReadReq miss cycles 242011374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_miss_latency::total 1710356977 # number of ReadReq miss cycles 242110726Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 242210726Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 242311374Ssteve.reinhardt@amd.comsystem.iocache.WriteLineReq_miss_latency::realview.ide 13558851015 # number of WriteLineReq miss cycles 242411374Ssteve.reinhardt@amd.comsystem.iocache.WriteLineReq_miss_latency::total 13558851015 # number of WriteLineReq miss cycles 242511374Ssteve.reinhardt@amd.comsystem.iocache.demand_miss_latency::realview.ethernet 5646000 # number of demand (read+write) miss cycles 242611374Ssteve.reinhardt@amd.comsystem.iocache.demand_miss_latency::realview.ide 1705079977 # number of demand (read+write) miss cycles 242711374Ssteve.reinhardt@amd.comsystem.iocache.demand_miss_latency::total 1710725977 # number of demand (read+write) miss cycles 242811374Ssteve.reinhardt@amd.comsystem.iocache.overall_miss_latency::realview.ethernet 5646000 # number of overall miss cycles 242911374Ssteve.reinhardt@amd.comsystem.iocache.overall_miss_latency::realview.ide 1705079977 # number of overall miss cycles 243011374Ssteve.reinhardt@amd.comsystem.iocache.overall_miss_latency::total 1710725977 # number of overall miss cycles 243110585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 243211374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_accesses::realview.ide 8907 # number of ReadReq accesses(hits+misses) 243311374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_accesses::total 8944 # number of ReadReq accesses(hits+misses) 243410585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 243510585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 243611201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) 243711201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) 243810585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 243911374Ssteve.reinhardt@amd.comsystem.iocache.demand_accesses::realview.ide 8907 # number of demand (read+write) accesses 244011374Ssteve.reinhardt@amd.comsystem.iocache.demand_accesses::total 8947 # number of demand (read+write) accesses 244110585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 244211374Ssteve.reinhardt@amd.comsystem.iocache.overall_accesses::realview.ide 8907 # number of overall (read+write) accesses 244311374Ssteve.reinhardt@amd.comsystem.iocache.overall_accesses::total 8947 # number of overall (read+write) accesses 244410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 244510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 244610585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 244710585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 244810585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 244911336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 245011336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 245110585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 245210585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 245310585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 245410585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 245510585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 245610585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 245711374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 142621.621622 # average ReadReq miss latency 245811374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 191431.455821 # average ReadReq miss latency 245911374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_avg_miss_latency::total 191229.536784 # average ReadReq miss latency 246010726Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 246110726Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 246211374Ssteve.reinhardt@amd.comsystem.iocache.WriteLineReq_avg_miss_latency::realview.ide 126737.185140 # average WriteLineReq miss latency 246311374Ssteve.reinhardt@amd.comsystem.iocache.WriteLineReq_avg_miss_latency::total 126737.185140 # average WriteLineReq miss latency 246411374Ssteve.reinhardt@amd.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 141150 # average overall miss latency 246511374Ssteve.reinhardt@amd.comsystem.iocache.demand_avg_miss_latency::realview.ide 191431.455821 # average overall miss latency 246611374Ssteve.reinhardt@amd.comsystem.iocache.demand_avg_miss_latency::total 191206.658880 # average overall miss latency 246711374Ssteve.reinhardt@amd.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 141150 # average overall miss latency 246811374Ssteve.reinhardt@amd.comsystem.iocache.overall_avg_miss_latency::realview.ide 191431.455821 # average overall miss latency 246911374Ssteve.reinhardt@amd.comsystem.iocache.overall_avg_miss_latency::total 191206.658880 # average overall miss latency 247011374Ssteve.reinhardt@amd.comsystem.iocache.blocked_cycles::no_mshrs 35119 # number of cycles access was blocked 247110585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 247211374Ssteve.reinhardt@amd.comsystem.iocache.blocked::no_mshrs 3508 # number of cycles access was blocked 247310585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 247411374Ssteve.reinhardt@amd.comsystem.iocache.avg_blocked_cycles::no_mshrs 10.011117 # average number of cycles each access was blocked 247510585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 247610585Sandreas.hansson@arm.comsystem.iocache.fast_writes 0 # number of fast writes performed 247710585Sandreas.hansson@arm.comsystem.iocache.cache_copies 0 # number of cache copies performed 247811336Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 106950 # number of writebacks 247911336Sandreas.hansson@arm.comsystem.iocache.writebacks::total 106950 # number of writebacks 248010585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 248111374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8907 # number of ReadReq MSHR misses 248211374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_mshr_misses::total 8944 # number of ReadReq MSHR misses 248310585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 248410585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 248511336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses 248611336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses 248710585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 248811374Ssteve.reinhardt@amd.comsystem.iocache.demand_mshr_misses::realview.ide 8907 # number of demand (read+write) MSHR misses 248911374Ssteve.reinhardt@amd.comsystem.iocache.demand_mshr_misses::total 8947 # number of demand (read+write) MSHR misses 249010585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 249111374Ssteve.reinhardt@amd.comsystem.iocache.overall_mshr_misses::realview.ide 8907 # number of overall MSHR misses 249211374Ssteve.reinhardt@amd.comsystem.iocache.overall_mshr_misses::total 8947 # number of overall MSHR misses 249311374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3427000 # number of ReadReq MSHR miss cycles 249411374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1259729977 # number of ReadReq MSHR miss cycles 249511374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_mshr_miss_latency::total 1263156977 # number of ReadReq MSHR miss cycles 249610892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 249710892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 249811374Ssteve.reinhardt@amd.comsystem.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8203408528 # number of WriteLineReq MSHR miss cycles 249911374Ssteve.reinhardt@amd.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 8203408528 # number of WriteLineReq MSHR miss cycles 250011374Ssteve.reinhardt@amd.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3646000 # number of demand (read+write) MSHR miss cycles 250111374Ssteve.reinhardt@amd.comsystem.iocache.demand_mshr_miss_latency::realview.ide 1259729977 # number of demand (read+write) MSHR miss cycles 250211374Ssteve.reinhardt@amd.comsystem.iocache.demand_mshr_miss_latency::total 1263375977 # number of demand (read+write) MSHR miss cycles 250311374Ssteve.reinhardt@amd.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3646000 # number of overall MSHR miss cycles 250411374Ssteve.reinhardt@amd.comsystem.iocache.overall_mshr_miss_latency::realview.ide 1259729977 # number of overall MSHR miss cycles 250511374Ssteve.reinhardt@amd.comsystem.iocache.overall_mshr_miss_latency::total 1263375977 # number of overall MSHR miss cycles 250610585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 250710585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 250810585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 250910585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 251010585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 251111336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 251211336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 251310585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 251410585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 251510585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 251610585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 251710585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 251810585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 251911374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 92621.621622 # average ReadReq mshr miss latency 252011374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141431.455821 # average ReadReq mshr miss latency 252111374Ssteve.reinhardt@amd.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 141229.536784 # average ReadReq mshr miss latency 252210892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 252310892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 252411374Ssteve.reinhardt@amd.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76678.835415 # average WriteLineReq mshr miss latency 252511374Ssteve.reinhardt@amd.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 76678.835415 # average WriteLineReq mshr miss latency 252611374Ssteve.reinhardt@amd.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 91150 # average overall mshr miss latency 252711374Ssteve.reinhardt@amd.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 141431.455821 # average overall mshr miss latency 252811374Ssteve.reinhardt@amd.comsystem.iocache.demand_avg_mshr_miss_latency::total 141206.658880 # average overall mshr miss latency 252911374Ssteve.reinhardt@amd.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 91150 # average overall mshr miss latency 253011374Ssteve.reinhardt@amd.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 141431.455821 # average overall mshr miss latency 253111374Ssteve.reinhardt@amd.comsystem.iocache.overall_avg_mshr_miss_latency::total 141206.658880 # average overall mshr miss latency 253210585Sandreas.hansson@arm.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 253311374Ssteve.reinhardt@amd.comsystem.l2c.tags.replacements 1736304 # number of replacements 253411374Ssteve.reinhardt@amd.comsystem.l2c.tags.tagsinuse 63595.107970 # Cycle average of tags in use 253511374Ssteve.reinhardt@amd.comsystem.l2c.tags.total_refs 7296515 # Total number of references to valid blocks. 253611374Ssteve.reinhardt@amd.comsystem.l2c.tags.sampled_refs 1796625 # Sample count of references to valid blocks. 253711374Ssteve.reinhardt@amd.comsystem.l2c.tags.avg_refs 4.061234 # Average number of references to valid blocks. 253811353Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 13283135500 # Cycle when the warmup percentage was hit. 253911374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_blocks::writebacks 21438.357602 # Average occupied blocks per requestor 254011374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 173.623523 # Average occupied blocks per requestor 254111374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 216.352807 # Average occupied blocks per requestor 254211374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_blocks::cpu0.inst 5273.180907 # Average occupied blocks per requestor 254311374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_blocks::cpu0.data 7402.273131 # Average occupied blocks per requestor 254411374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 10592.541457 # Average occupied blocks per requestor 254511374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 149.822853 # Average occupied blocks per requestor 254611374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 191.052659 # Average occupied blocks per requestor 254711374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_blocks::cpu1.inst 3264.316466 # Average occupied blocks per requestor 254811374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_blocks::cpu1.data 6229.486316 # Average occupied blocks per requestor 254911374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8664.100250 # Average occupied blocks per requestor 255011374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_percent::writebacks 0.327123 # Average percentage of cache occupancy 255111374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.002649 # Average percentage of cache occupancy 255211374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.003301 # Average percentage of cache occupancy 255311374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_percent::cpu0.inst 0.080462 # Average percentage of cache occupancy 255411374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_percent::cpu0.data 0.112950 # Average percentage of cache occupancy 255511374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.161629 # Average percentage of cache occupancy 255611374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.002286 # Average percentage of cache occupancy 255711374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.002915 # Average percentage of cache occupancy 255811374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_percent::cpu1.inst 0.049810 # Average percentage of cache occupancy 255911374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_percent::cpu1.data 0.095054 # Average percentage of cache occupancy 256011374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.132204 # Average percentage of cache occupancy 256111374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_percent::total 0.970384 # Average percentage of cache occupancy 256211374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_task_id_blocks::1022 8701 # Occupied blocks per task id 256311374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_task_id_blocks::1023 194 # Occupied blocks per task id 256411374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_task_id_blocks::1024 51426 # Occupied blocks per task id 256511374Ssteve.reinhardt@amd.comsystem.l2c.tags.age_task_id_blocks_1022::0 62 # Occupied blocks per task id 256611374Ssteve.reinhardt@amd.comsystem.l2c.tags.age_task_id_blocks_1022::1 67 # Occupied blocks per task id 256711374Ssteve.reinhardt@amd.comsystem.l2c.tags.age_task_id_blocks_1022::2 253 # Occupied blocks per task id 256811374Ssteve.reinhardt@amd.comsystem.l2c.tags.age_task_id_blocks_1022::3 1394 # Occupied blocks per task id 256911374Ssteve.reinhardt@amd.comsystem.l2c.tags.age_task_id_blocks_1022::4 6925 # Occupied blocks per task id 257011374Ssteve.reinhardt@amd.comsystem.l2c.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id 257111374Ssteve.reinhardt@amd.comsystem.l2c.tags.age_task_id_blocks_1023::4 186 # Occupied blocks per task id 257211374Ssteve.reinhardt@amd.comsystem.l2c.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id 257311374Ssteve.reinhardt@amd.comsystem.l2c.tags.age_task_id_blocks_1024::1 389 # Occupied blocks per task id 257411374Ssteve.reinhardt@amd.comsystem.l2c.tags.age_task_id_blocks_1024::2 2651 # Occupied blocks per task id 257511374Ssteve.reinhardt@amd.comsystem.l2c.tags.age_task_id_blocks_1024::3 12885 # Occupied blocks per task id 257611374Ssteve.reinhardt@amd.comsystem.l2c.tags.age_task_id_blocks_1024::4 35470 # Occupied blocks per task id 257711374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_task_id_percent::1022 0.132767 # Percentage of cache occupancy per task id 257811374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_task_id_percent::1023 0.002960 # Percentage of cache occupancy per task id 257911374Ssteve.reinhardt@amd.comsystem.l2c.tags.occ_task_id_percent::1024 0.784698 # Percentage of cache occupancy per task id 258011374Ssteve.reinhardt@amd.comsystem.l2c.tags.tag_accesses 90467673 # Number of tag accesses 258111374Ssteve.reinhardt@amd.comsystem.l2c.tags.data_accesses 90467673 # Number of data accesses 258211374Ssteve.reinhardt@amd.comsystem.l2c.WritebackDirty_hits::writebacks 3161640 # number of WritebackDirty hits 258311374Ssteve.reinhardt@amd.comsystem.l2c.WritebackDirty_hits::total 3161640 # number of WritebackDirty hits 258411374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_hits::cpu0.data 190042 # number of UpgradeReq hits 258511374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_hits::cpu1.data 150318 # number of UpgradeReq hits 258611374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_hits::total 340360 # number of UpgradeReq hits 258711374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 46175 # number of SCUpgradeReq hits 258811374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 40691 # number of SCUpgradeReq hits 258911374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_hits::total 86866 # number of SCUpgradeReq hits 259011374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_hits::cpu0.data 66080 # number of ReadExReq hits 259111374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_hits::cpu1.data 54849 # number of ReadExReq hits 259211374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_hits::total 120929 # number of ReadExReq hits 259311374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 7647 # number of ReadSharedReq hits 259411374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 4987 # number of ReadSharedReq hits 259511374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 699090 # number of ReadSharedReq hits 259611374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_hits::cpu0.data 694199 # number of ReadSharedReq hits 259711374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 343045 # number of ReadSharedReq hits 259811374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6831 # number of ReadSharedReq hits 259911374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 3980 # number of ReadSharedReq hits 260011374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 688497 # number of ReadSharedReq hits 260111374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_hits::cpu1.data 675339 # number of ReadSharedReq hits 260211374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 302251 # number of ReadSharedReq hits 260311374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_hits::total 3425866 # number of ReadSharedReq hits 260411374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_hits::cpu0.data 143577 # number of InvalidateReq hits 260511374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_hits::cpu1.data 133038 # number of InvalidateReq hits 260611374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_hits::total 276615 # number of InvalidateReq hits 260711374Ssteve.reinhardt@amd.comsystem.l2c.demand_hits::cpu0.dtb.walker 7647 # number of demand (read+write) hits 260811374Ssteve.reinhardt@amd.comsystem.l2c.demand_hits::cpu0.itb.walker 4987 # number of demand (read+write) hits 260911374Ssteve.reinhardt@amd.comsystem.l2c.demand_hits::cpu0.inst 699090 # number of demand (read+write) hits 261011374Ssteve.reinhardt@amd.comsystem.l2c.demand_hits::cpu0.data 760279 # number of demand (read+write) hits 261111374Ssteve.reinhardt@amd.comsystem.l2c.demand_hits::cpu0.l2cache.prefetcher 343045 # number of demand (read+write) hits 261211374Ssteve.reinhardt@amd.comsystem.l2c.demand_hits::cpu1.dtb.walker 6831 # number of demand (read+write) hits 261311374Ssteve.reinhardt@amd.comsystem.l2c.demand_hits::cpu1.itb.walker 3980 # number of demand (read+write) hits 261411374Ssteve.reinhardt@amd.comsystem.l2c.demand_hits::cpu1.inst 688497 # number of demand (read+write) hits 261511374Ssteve.reinhardt@amd.comsystem.l2c.demand_hits::cpu1.data 730188 # number of demand (read+write) hits 261611374Ssteve.reinhardt@amd.comsystem.l2c.demand_hits::cpu1.l2cache.prefetcher 302251 # number of demand (read+write) hits 261711374Ssteve.reinhardt@amd.comsystem.l2c.demand_hits::total 3546795 # number of demand (read+write) hits 261811374Ssteve.reinhardt@amd.comsystem.l2c.overall_hits::cpu0.dtb.walker 7647 # number of overall hits 261911374Ssteve.reinhardt@amd.comsystem.l2c.overall_hits::cpu0.itb.walker 4987 # number of overall hits 262011374Ssteve.reinhardt@amd.comsystem.l2c.overall_hits::cpu0.inst 699090 # number of overall hits 262111374Ssteve.reinhardt@amd.comsystem.l2c.overall_hits::cpu0.data 760279 # number of overall hits 262211374Ssteve.reinhardt@amd.comsystem.l2c.overall_hits::cpu0.l2cache.prefetcher 343045 # number of overall hits 262311374Ssteve.reinhardt@amd.comsystem.l2c.overall_hits::cpu1.dtb.walker 6831 # number of overall hits 262411374Ssteve.reinhardt@amd.comsystem.l2c.overall_hits::cpu1.itb.walker 3980 # number of overall hits 262511374Ssteve.reinhardt@amd.comsystem.l2c.overall_hits::cpu1.inst 688497 # number of overall hits 262611374Ssteve.reinhardt@amd.comsystem.l2c.overall_hits::cpu1.data 730188 # number of overall hits 262711374Ssteve.reinhardt@amd.comsystem.l2c.overall_hits::cpu1.l2cache.prefetcher 302251 # number of overall hits 262811374Ssteve.reinhardt@amd.comsystem.l2c.overall_hits::total 3546795 # number of overall hits 262911374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_misses::cpu0.data 66937 # number of UpgradeReq misses 263011374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_misses::cpu1.data 62230 # number of UpgradeReq misses 263111374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_misses::total 129167 # number of UpgradeReq misses 263211374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 13492 # number of SCUpgradeReq misses 263311374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 12585 # number of SCUpgradeReq misses 263411374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_misses::total 26077 # number of SCUpgradeReq misses 263511374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_misses::cpu0.data 88765 # number of ReadExReq misses 263611374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_misses::cpu1.data 66782 # number of ReadExReq misses 263711374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_misses::total 155547 # number of ReadExReq misses 263811374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 3643 # number of ReadSharedReq misses 263911374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 3291 # number of ReadSharedReq misses 264011374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 71874 # number of ReadSharedReq misses 264111374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_misses::cpu0.data 188609 # number of ReadSharedReq misses 264211374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 283713 # number of ReadSharedReq misses 264311374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2600 # number of ReadSharedReq misses 264411374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_misses::cpu1.itb.walker 2065 # number of ReadSharedReq misses 264511374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 61168 # number of ReadSharedReq misses 264611374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_misses::cpu1.data 131288 # number of ReadSharedReq misses 264711374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 331034 # number of ReadSharedReq misses 264811374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_misses::total 1079285 # number of ReadSharedReq misses 264911374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_misses::cpu0.data 420248 # number of InvalidateReq misses 265011374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_misses::cpu1.data 172062 # number of InvalidateReq misses 265111374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_misses::total 592310 # number of InvalidateReq misses 265211374Ssteve.reinhardt@amd.comsystem.l2c.demand_misses::cpu0.dtb.walker 3643 # number of demand (read+write) misses 265311374Ssteve.reinhardt@amd.comsystem.l2c.demand_misses::cpu0.itb.walker 3291 # number of demand (read+write) misses 265411374Ssteve.reinhardt@amd.comsystem.l2c.demand_misses::cpu0.inst 71874 # number of demand (read+write) misses 265511374Ssteve.reinhardt@amd.comsystem.l2c.demand_misses::cpu0.data 277374 # number of demand (read+write) misses 265611374Ssteve.reinhardt@amd.comsystem.l2c.demand_misses::cpu0.l2cache.prefetcher 283713 # number of demand (read+write) misses 265711374Ssteve.reinhardt@amd.comsystem.l2c.demand_misses::cpu1.dtb.walker 2600 # number of demand (read+write) misses 265811374Ssteve.reinhardt@amd.comsystem.l2c.demand_misses::cpu1.itb.walker 2065 # number of demand (read+write) misses 265911374Ssteve.reinhardt@amd.comsystem.l2c.demand_misses::cpu1.inst 61168 # number of demand (read+write) misses 266011374Ssteve.reinhardt@amd.comsystem.l2c.demand_misses::cpu1.data 198070 # number of demand (read+write) misses 266111374Ssteve.reinhardt@amd.comsystem.l2c.demand_misses::cpu1.l2cache.prefetcher 331034 # number of demand (read+write) misses 266211374Ssteve.reinhardt@amd.comsystem.l2c.demand_misses::total 1234832 # number of demand (read+write) misses 266311374Ssteve.reinhardt@amd.comsystem.l2c.overall_misses::cpu0.dtb.walker 3643 # number of overall misses 266411374Ssteve.reinhardt@amd.comsystem.l2c.overall_misses::cpu0.itb.walker 3291 # number of overall misses 266511374Ssteve.reinhardt@amd.comsystem.l2c.overall_misses::cpu0.inst 71874 # number of overall misses 266611374Ssteve.reinhardt@amd.comsystem.l2c.overall_misses::cpu0.data 277374 # number of overall misses 266711374Ssteve.reinhardt@amd.comsystem.l2c.overall_misses::cpu0.l2cache.prefetcher 283713 # number of overall misses 266811374Ssteve.reinhardt@amd.comsystem.l2c.overall_misses::cpu1.dtb.walker 2600 # number of overall misses 266911374Ssteve.reinhardt@amd.comsystem.l2c.overall_misses::cpu1.itb.walker 2065 # number of overall misses 267011374Ssteve.reinhardt@amd.comsystem.l2c.overall_misses::cpu1.inst 61168 # number of overall misses 267111374Ssteve.reinhardt@amd.comsystem.l2c.overall_misses::cpu1.data 198070 # number of overall misses 267211374Ssteve.reinhardt@amd.comsystem.l2c.overall_misses::cpu1.l2cache.prefetcher 331034 # number of overall misses 267311374Ssteve.reinhardt@amd.comsystem.l2c.overall_misses::total 1234832 # number of overall misses 267411374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_miss_latency::cpu0.data 1172514500 # number of UpgradeReq miss cycles 267511374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_miss_latency::cpu1.data 1079518500 # number of UpgradeReq miss cycles 267611374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_miss_latency::total 2252033000 # number of UpgradeReq miss cycles 267711374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_miss_latency::cpu0.data 202156500 # number of SCUpgradeReq miss cycles 267811374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_miss_latency::cpu1.data 215769000 # number of SCUpgradeReq miss cycles 267911374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_miss_latency::total 417925500 # number of SCUpgradeReq miss cycles 268011374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_miss_latency::cpu0.data 12242204500 # number of ReadExReq miss cycles 268111374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_miss_latency::cpu1.data 9216523500 # number of ReadExReq miss cycles 268211374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_miss_latency::total 21458728000 # number of ReadExReq miss cycles 268311374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 512308500 # number of ReadSharedReq miss cycles 268411374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 464071000 # number of ReadSharedReq miss cycles 268511374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.inst 9761528500 # number of ReadSharedReq miss cycles 268611374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.data 26674163500 # number of ReadSharedReq miss cycles 268711374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 48831200595 # number of ReadSharedReq miss cycles 268811374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 367906000 # number of ReadSharedReq miss cycles 268911374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 298172500 # number of ReadSharedReq miss cycles 269011374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.inst 8283610000 # number of ReadSharedReq miss cycles 269111374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.data 18924327000 # number of ReadSharedReq miss cycles 269211374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 58819146941 # number of ReadSharedReq miss cycles 269311374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_latency::total 172936434536 # number of ReadSharedReq miss cycles 269411374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_miss_latency::cpu0.data 151369500 # number of InvalidateReq miss cycles 269511374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_miss_latency::cpu1.data 160513500 # number of InvalidateReq miss cycles 269611374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_miss_latency::total 311883000 # number of InvalidateReq miss cycles 269711374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_latency::cpu0.dtb.walker 512308500 # number of demand (read+write) miss cycles 269811374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_latency::cpu0.itb.walker 464071000 # number of demand (read+write) miss cycles 269911374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_latency::cpu0.inst 9761528500 # number of demand (read+write) miss cycles 270011374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_latency::cpu0.data 38916368000 # number of demand (read+write) miss cycles 270111374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 48831200595 # number of demand (read+write) miss cycles 270211374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_latency::cpu1.dtb.walker 367906000 # number of demand (read+write) miss cycles 270311374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_latency::cpu1.itb.walker 298172500 # number of demand (read+write) miss cycles 270411374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_latency::cpu1.inst 8283610000 # number of demand (read+write) miss cycles 270511374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_latency::cpu1.data 28140850500 # number of demand (read+write) miss cycles 270611374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 58819146941 # number of demand (read+write) miss cycles 270711374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_latency::total 194395162536 # number of demand (read+write) miss cycles 270811374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_latency::cpu0.dtb.walker 512308500 # number of overall miss cycles 270911374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_latency::cpu0.itb.walker 464071000 # number of overall miss cycles 271011374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_latency::cpu0.inst 9761528500 # number of overall miss cycles 271111374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_latency::cpu0.data 38916368000 # number of overall miss cycles 271211374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 48831200595 # number of overall miss cycles 271311374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_latency::cpu1.dtb.walker 367906000 # number of overall miss cycles 271411374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_latency::cpu1.itb.walker 298172500 # number of overall miss cycles 271511374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_latency::cpu1.inst 8283610000 # number of overall miss cycles 271611374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_latency::cpu1.data 28140850500 # number of overall miss cycles 271711374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 58819146941 # number of overall miss cycles 271811374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_latency::total 194395162536 # number of overall miss cycles 271911374Ssteve.reinhardt@amd.comsystem.l2c.WritebackDirty_accesses::writebacks 3161640 # number of WritebackDirty accesses(hits+misses) 272011374Ssteve.reinhardt@amd.comsystem.l2c.WritebackDirty_accesses::total 3161640 # number of WritebackDirty accesses(hits+misses) 272111374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_accesses::cpu0.data 256979 # number of UpgradeReq accesses(hits+misses) 272211374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_accesses::cpu1.data 212548 # number of UpgradeReq accesses(hits+misses) 272311374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_accesses::total 469527 # number of UpgradeReq accesses(hits+misses) 272411374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 59667 # number of SCUpgradeReq accesses(hits+misses) 272511374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 53276 # number of SCUpgradeReq accesses(hits+misses) 272611374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_accesses::total 112943 # number of SCUpgradeReq accesses(hits+misses) 272711374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_accesses::cpu0.data 154845 # number of ReadExReq accesses(hits+misses) 272811374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_accesses::cpu1.data 121631 # number of ReadExReq accesses(hits+misses) 272911374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_accesses::total 276476 # number of ReadExReq accesses(hits+misses) 273011374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 11290 # number of ReadSharedReq accesses(hits+misses) 273111374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 8278 # number of ReadSharedReq accesses(hits+misses) 273211374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 770964 # number of ReadSharedReq accesses(hits+misses) 273311374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 882808 # number of ReadSharedReq accesses(hits+misses) 273411374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 626758 # number of ReadSharedReq accesses(hits+misses) 273511374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 9431 # number of ReadSharedReq accesses(hits+misses) 273611374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6045 # number of ReadSharedReq accesses(hits+misses) 273711374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 749665 # number of ReadSharedReq accesses(hits+misses) 273811374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 806627 # number of ReadSharedReq accesses(hits+misses) 273911374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 633285 # number of ReadSharedReq accesses(hits+misses) 274011374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_accesses::total 4505151 # number of ReadSharedReq accesses(hits+misses) 274111374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_accesses::cpu0.data 563825 # number of InvalidateReq accesses(hits+misses) 274211374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_accesses::cpu1.data 305100 # number of InvalidateReq accesses(hits+misses) 274311374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_accesses::total 868925 # number of InvalidateReq accesses(hits+misses) 274411374Ssteve.reinhardt@amd.comsystem.l2c.demand_accesses::cpu0.dtb.walker 11290 # number of demand (read+write) accesses 274511374Ssteve.reinhardt@amd.comsystem.l2c.demand_accesses::cpu0.itb.walker 8278 # number of demand (read+write) accesses 274611374Ssteve.reinhardt@amd.comsystem.l2c.demand_accesses::cpu0.inst 770964 # number of demand (read+write) accesses 274711374Ssteve.reinhardt@amd.comsystem.l2c.demand_accesses::cpu0.data 1037653 # number of demand (read+write) accesses 274811374Ssteve.reinhardt@amd.comsystem.l2c.demand_accesses::cpu0.l2cache.prefetcher 626758 # number of demand (read+write) accesses 274911374Ssteve.reinhardt@amd.comsystem.l2c.demand_accesses::cpu1.dtb.walker 9431 # number of demand (read+write) accesses 275011374Ssteve.reinhardt@amd.comsystem.l2c.demand_accesses::cpu1.itb.walker 6045 # number of demand (read+write) accesses 275111374Ssteve.reinhardt@amd.comsystem.l2c.demand_accesses::cpu1.inst 749665 # number of demand (read+write) accesses 275211374Ssteve.reinhardt@amd.comsystem.l2c.demand_accesses::cpu1.data 928258 # number of demand (read+write) accesses 275311374Ssteve.reinhardt@amd.comsystem.l2c.demand_accesses::cpu1.l2cache.prefetcher 633285 # number of demand (read+write) accesses 275411374Ssteve.reinhardt@amd.comsystem.l2c.demand_accesses::total 4781627 # number of demand (read+write) accesses 275511374Ssteve.reinhardt@amd.comsystem.l2c.overall_accesses::cpu0.dtb.walker 11290 # number of overall (read+write) accesses 275611374Ssteve.reinhardt@amd.comsystem.l2c.overall_accesses::cpu0.itb.walker 8278 # number of overall (read+write) accesses 275711374Ssteve.reinhardt@amd.comsystem.l2c.overall_accesses::cpu0.inst 770964 # number of overall (read+write) accesses 275811374Ssteve.reinhardt@amd.comsystem.l2c.overall_accesses::cpu0.data 1037653 # number of overall (read+write) accesses 275911374Ssteve.reinhardt@amd.comsystem.l2c.overall_accesses::cpu0.l2cache.prefetcher 626758 # number of overall (read+write) accesses 276011374Ssteve.reinhardt@amd.comsystem.l2c.overall_accesses::cpu1.dtb.walker 9431 # number of overall (read+write) accesses 276111374Ssteve.reinhardt@amd.comsystem.l2c.overall_accesses::cpu1.itb.walker 6045 # number of overall (read+write) accesses 276211374Ssteve.reinhardt@amd.comsystem.l2c.overall_accesses::cpu1.inst 749665 # number of overall (read+write) accesses 276311374Ssteve.reinhardt@amd.comsystem.l2c.overall_accesses::cpu1.data 928258 # number of overall (read+write) accesses 276411374Ssteve.reinhardt@amd.comsystem.l2c.overall_accesses::cpu1.l2cache.prefetcher 633285 # number of overall (read+write) accesses 276511374Ssteve.reinhardt@amd.comsystem.l2c.overall_accesses::total 4781627 # number of overall (read+write) accesses 276611374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.260477 # miss rate for UpgradeReq accesses 276711374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.292781 # miss rate for UpgradeReq accesses 276811374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_miss_rate::total 0.275100 # miss rate for UpgradeReq accesses 276911374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.226122 # miss rate for SCUpgradeReq accesses 277011374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.236223 # miss rate for SCUpgradeReq accesses 277111374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.230886 # miss rate for SCUpgradeReq accesses 277211374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.573251 # miss rate for ReadExReq accesses 277311374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.549054 # miss rate for ReadExReq accesses 277411374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_miss_rate::total 0.562606 # miss rate for ReadExReq accesses 277511374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.322675 # miss rate for ReadSharedReq accesses 277611374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.397560 # miss rate for ReadSharedReq accesses 277711374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.093226 # miss rate for ReadSharedReq accesses 277811374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.213647 # miss rate for ReadSharedReq accesses 277911374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.452668 # miss rate for ReadSharedReq accesses 278011374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.275687 # miss rate for ReadSharedReq accesses 278111374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.341605 # miss rate for ReadSharedReq accesses 278211374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.081594 # miss rate for ReadSharedReq accesses 278311374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.162762 # miss rate for ReadSharedReq accesses 278411374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.522725 # miss rate for ReadSharedReq accesses 278511374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_miss_rate::total 0.239567 # miss rate for ReadSharedReq accesses 278611374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_miss_rate::cpu0.data 0.745352 # miss rate for InvalidateReq accesses 278711374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_miss_rate::cpu1.data 0.563953 # miss rate for InvalidateReq accesses 278811374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_miss_rate::total 0.681658 # miss rate for InvalidateReq accesses 278911374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.322675 # miss rate for demand accesses 279011374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.397560 # miss rate for demand accesses 279111374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_rate::cpu0.inst 0.093226 # miss rate for demand accesses 279211374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_rate::cpu0.data 0.267309 # miss rate for demand accesses 279311374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.452668 # miss rate for demand accesses 279411374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.275687 # miss rate for demand accesses 279511374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.341605 # miss rate for demand accesses 279611374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_rate::cpu1.inst 0.081594 # miss rate for demand accesses 279711374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_rate::cpu1.data 0.213378 # miss rate for demand accesses 279811374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.522725 # miss rate for demand accesses 279911374Ssteve.reinhardt@amd.comsystem.l2c.demand_miss_rate::total 0.258245 # miss rate for demand accesses 280011374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.322675 # miss rate for overall accesses 280111374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.397560 # miss rate for overall accesses 280211374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_rate::cpu0.inst 0.093226 # miss rate for overall accesses 280311374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_rate::cpu0.data 0.267309 # miss rate for overall accesses 280411374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.452668 # miss rate for overall accesses 280511374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.275687 # miss rate for overall accesses 280611374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.341605 # miss rate for overall accesses 280711374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_rate::cpu1.inst 0.081594 # miss rate for overall accesses 280811374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_rate::cpu1.data 0.213378 # miss rate for overall accesses 280911374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.522725 # miss rate for overall accesses 281011374Ssteve.reinhardt@amd.comsystem.l2c.overall_miss_rate::total 0.258245 # miss rate for overall accesses 281111374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu0.data 17516.687333 # average UpgradeReq miss latency 281211374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17347.236060 # average UpgradeReq miss latency 281311374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_avg_miss_latency::total 17435.049200 # average UpgradeReq miss latency 281411374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 14983.434628 # average SCUpgradeReq miss latency 281511374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 17144.934446 # average SCUpgradeReq miss latency 281611374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_avg_miss_latency::total 16026.594317 # average SCUpgradeReq miss latency 281711374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_avg_miss_latency::cpu0.data 137917.022475 # average ReadExReq miss latency 281811374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_avg_miss_latency::cpu1.data 138009.096763 # average ReadExReq miss latency 281911374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_avg_miss_latency::total 137956.553325 # average ReadExReq miss latency 282011374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 140628.191051 # average ReadSharedReq miss latency 282111374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 141012.154360 # average ReadSharedReq miss latency 282211374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 135814.460027 # average ReadSharedReq miss latency 282311374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 141425.719345 # average ReadSharedReq miss latency 282411374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 172114.780059 # average ReadSharedReq miss latency 282511374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 141502.307692 # average ReadSharedReq miss latency 282611374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 144393.462470 # average ReadSharedReq miss latency 282711374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 135423.914465 # average ReadSharedReq miss latency 282811374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 144143.615563 # average ReadSharedReq miss latency 282911374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 177683.098839 # average ReadSharedReq miss latency 283011374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_miss_latency::total 160232.408063 # average ReadSharedReq miss latency 283111374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_avg_miss_latency::cpu0.data 360.190887 # average InvalidateReq miss latency 283211374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_avg_miss_latency::cpu1.data 932.881752 # average InvalidateReq miss latency 283311374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_avg_miss_latency::total 526.553663 # average InvalidateReq miss latency 283411374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_miss_latency::cpu0.dtb.walker 140628.191051 # average overall miss latency 283511374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_miss_latency::cpu0.itb.walker 141012.154360 # average overall miss latency 283611374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_miss_latency::cpu0.inst 135814.460027 # average overall miss latency 283711374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_miss_latency::cpu0.data 140302.869050 # average overall miss latency 283811374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 172114.780059 # average overall miss latency 283911374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_miss_latency::cpu1.dtb.walker 141502.307692 # average overall miss latency 284011374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_miss_latency::cpu1.itb.walker 144393.462470 # average overall miss latency 284111374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_miss_latency::cpu1.inst 135423.914465 # average overall miss latency 284211374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_miss_latency::cpu1.data 142075.278942 # average overall miss latency 284311374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 177683.098839 # average overall miss latency 284411374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_miss_latency::total 157426.404998 # average overall miss latency 284511374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_miss_latency::cpu0.dtb.walker 140628.191051 # average overall miss latency 284611374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_miss_latency::cpu0.itb.walker 141012.154360 # average overall miss latency 284711374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_miss_latency::cpu0.inst 135814.460027 # average overall miss latency 284811374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_miss_latency::cpu0.data 140302.869050 # average overall miss latency 284911374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 172114.780059 # average overall miss latency 285011374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_miss_latency::cpu1.dtb.walker 141502.307692 # average overall miss latency 285111374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_miss_latency::cpu1.itb.walker 144393.462470 # average overall miss latency 285211374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_miss_latency::cpu1.inst 135423.914465 # average overall miss latency 285311374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_miss_latency::cpu1.data 142075.278942 # average overall miss latency 285411374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 177683.098839 # average overall miss latency 285511374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_miss_latency::total 157426.404998 # average overall miss latency 285611374Ssteve.reinhardt@amd.comsystem.l2c.blocked_cycles::no_mshrs 1204 # number of cycles access was blocked 285710515SAli.Saidi@ARM.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 285811374Ssteve.reinhardt@amd.comsystem.l2c.blocked::no_mshrs 5 # number of cycles access was blocked 285910515SAli.Saidi@ARM.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 286011374Ssteve.reinhardt@amd.comsystem.l2c.avg_blocked_cycles::no_mshrs 240.800000 # average number of cycles each access was blocked 286110515SAli.Saidi@ARM.comsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 286210515SAli.Saidi@ARM.comsystem.l2c.fast_writes 0 # number of fast writes performed 286310515SAli.Saidi@ARM.comsystem.l2c.cache_copies 0 # number of cache copies performed 286411374Ssteve.reinhardt@amd.comsystem.l2c.writebacks::writebacks 1344961 # number of writebacks 286511374Ssteve.reinhardt@amd.comsystem.l2c.writebacks::total 1344961 # number of writebacks 286611374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadSharedReq MSHR hits 286711374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.inst 474 # number of ReadSharedReq MSHR hits 286811374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.data 106 # number of ReadSharedReq MSHR hits 286911374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.l2cache.prefetcher 35 # number of ReadSharedReq MSHR hits 287011374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.inst 389 # number of ReadSharedReq MSHR hits 287111374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.data 102 # number of ReadSharedReq MSHR hits 287211374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.l2cache.prefetcher 15 # number of ReadSharedReq MSHR hits 287311374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_hits::total 1122 # number of ReadSharedReq MSHR hits 287411374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits 287511374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_hits::cpu0.inst 474 # number of demand (read+write) MSHR hits 287611374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_hits::cpu0.data 106 # number of demand (read+write) MSHR hits 287711374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 35 # number of demand (read+write) MSHR hits 287811374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_hits::cpu1.inst 389 # number of demand (read+write) MSHR hits 287911374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_hits::cpu1.data 102 # number of demand (read+write) MSHR hits 288011374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 15 # number of demand (read+write) MSHR hits 288111374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_hits::total 1122 # number of demand (read+write) MSHR hits 288211374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits 288311374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_hits::cpu0.inst 474 # number of overall MSHR hits 288411374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_hits::cpu0.data 106 # number of overall MSHR hits 288511374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 35 # number of overall MSHR hits 288611374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_hits::cpu1.inst 389 # number of overall MSHR hits 288711374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_hits::cpu1.data 102 # number of overall MSHR hits 288811374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 15 # number of overall MSHR hits 288911374Ssteve.reinhardt@amd.comsystem.l2c.overall_mshr_hits::total 1122 # number of overall MSHR hits 289011374Ssteve.reinhardt@amd.comsystem.l2c.CleanEvict_mshr_misses::writebacks 71582 # number of CleanEvict MSHR misses 289111374Ssteve.reinhardt@amd.comsystem.l2c.CleanEvict_mshr_misses::total 71582 # number of CleanEvict MSHR misses 289211374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_mshr_misses::cpu0.data 66937 # number of UpgradeReq MSHR misses 289311374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_mshr_misses::cpu1.data 62230 # number of UpgradeReq MSHR misses 289411374Ssteve.reinhardt@amd.comsystem.l2c.UpgradeReq_mshr_misses::total 129167 # number of UpgradeReq MSHR misses 289511374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu0.data 13492 # number of SCUpgradeReq MSHR misses 289611374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu1.data 12585 # number of SCUpgradeReq MSHR misses 289711374Ssteve.reinhardt@amd.comsystem.l2c.SCUpgradeReq_mshr_misses::total 26077 # number of SCUpgradeReq MSHR misses 289811374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_mshr_misses::cpu0.data 88765 # number of ReadExReq MSHR misses 289911374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_mshr_misses::cpu1.data 66782 # number of ReadExReq MSHR misses 290011374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_mshr_misses::total 155547 # number of ReadExReq MSHR misses 290111374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 3642 # number of ReadSharedReq MSHR misses 290211374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3291 # number of ReadSharedReq MSHR misses 290311374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.inst 71400 # number of ReadSharedReq MSHR misses 290411374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.data 188503 # number of ReadSharedReq MSHR misses 290511374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 283678 # number of ReadSharedReq MSHR misses 290611374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2600 # number of ReadSharedReq MSHR misses 290711374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2065 # number of ReadSharedReq MSHR misses 290811374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.inst 60779 # number of ReadSharedReq MSHR misses 290911374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.data 131186 # number of ReadSharedReq MSHR misses 291011374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 331019 # number of ReadSharedReq MSHR misses 291111374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_misses::total 1078163 # number of ReadSharedReq MSHR misses 291211374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_mshr_misses::cpu0.data 420248 # number of InvalidateReq MSHR misses 291311374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_mshr_misses::cpu1.data 172062 # number of InvalidateReq MSHR misses 291411374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_mshr_misses::total 592310 # number of InvalidateReq MSHR misses 291511374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_misses::cpu0.dtb.walker 3642 # number of demand (read+write) MSHR misses 291611374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_misses::cpu0.itb.walker 3291 # number of demand (read+write) MSHR misses 291711374Ssteve.reinhardt@amd.comsystem.l2c.demand_mshr_misses::cpu0.inst 71400 # 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mshr miss rate for ReadSharedReq accesses 302111374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.092611 # mshr miss rate for ReadSharedReq accesses 302211374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.213527 # mshr miss rate for ReadSharedReq accesses 302311374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.452612 # mshr miss rate for ReadSharedReq accesses 302411374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.275687 # mshr miss rate for ReadSharedReq accesses 302511374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.341605 # mshr miss rate for ReadSharedReq accesses 302611374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.081075 # mshr miss rate for ReadSharedReq accesses 302711374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.162635 # mshr miss rate for ReadSharedReq accesses 302811374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.522701 # 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average SCUpgradeReq mshr miss latency 306111374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 127912.406083 # average ReadExReq mshr miss latency 306211374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 128004.597362 # average ReadExReq mshr miss latency 306311374Ssteve.reinhardt@amd.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 127951.987161 # average ReadExReq mshr miss latency 306411374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130627.550522 # average ReadSharedReq mshr miss latency 306511374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 131006.999696 # average ReadSharedReq mshr miss latency 306611374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 125916.416541 # average ReadSharedReq mshr miss latency 306711374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 131423.037819 # average ReadSharedReq mshr miss latency 306811374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162111.922712 # average ReadSharedReq mshr miss latency 306911374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 131497.893462 # average ReadSharedReq mshr miss latency 307011374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 134389.597094 # average ReadSharedReq mshr miss latency 307111374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 125525.953290 # average ReadSharedReq mshr miss latency 307211374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 134145.307792 # average ReadSharedReq mshr miss latency 307311374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 167680.055773 # average ReadSharedReq mshr miss latency 307411374Ssteve.reinhardt@amd.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::total 150265.373892 # average ReadSharedReq mshr miss latency 307511374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70087.808865 # average InvalidateReq mshr miss latency 307611374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69270.608839 # average InvalidateReq mshr miss latency 307711374Ssteve.reinhardt@amd.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::total 69850.417852 # average InvalidateReq mshr miss latency 307811374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130627.550522 # average overall mshr miss latency 307911374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131006.999696 # average overall mshr miss latency 308011374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125916.416541 # average overall mshr miss latency 308111374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 130299.138826 # average overall mshr miss latency 308211374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162111.922712 # average overall mshr miss latency 308311374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 131497.893462 # average overall mshr miss latency 308411374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 134389.597094 # average overall mshr miss latency 308511374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125525.953290 # average overall mshr miss latency 308611374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 132073.816824 # average overall mshr miss latency 308711374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 167680.055773 # average overall mshr miss latency 308811374Ssteve.reinhardt@amd.comsystem.l2c.demand_avg_mshr_miss_latency::total 147452.086842 # average overall mshr miss latency 308911374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130627.550522 # average overall mshr miss latency 309011374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131006.999696 # average overall mshr miss latency 309111374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125916.416541 # average overall mshr miss latency 309211374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 130299.138826 # average overall mshr miss latency 309311374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162111.922712 # average overall mshr miss latency 309411374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 131497.893462 # average overall mshr miss latency 309511374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 134389.597094 # average overall mshr miss latency 309611374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125525.953290 # average overall mshr miss latency 309711374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 132073.816824 # average overall mshr miss latency 309811374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 167680.055773 # average overall mshr miss latency 309911374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_mshr_miss_latency::total 147452.086842 # average overall mshr miss latency 310011201Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average ReadReq mshr uncacheable latency 310111374Ssteve.reinhardt@amd.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 148992.246785 # average ReadReq mshr uncacheable latency 310211353Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111650.537634 # average ReadReq mshr uncacheable latency 310311374Ssteve.reinhardt@amd.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158707.724699 # average ReadReq mshr uncacheable latency 310411374Ssteve.reinhardt@amd.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total 130545.300866 # average ReadReq mshr uncacheable latency 310511374Ssteve.reinhardt@amd.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147439.379444 # average WriteReq mshr uncacheable latency 310611374Ssteve.reinhardt@amd.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 163149.942166 # average WriteReq mshr uncacheable latency 310711374Ssteve.reinhardt@amd.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::total 156581.535643 # average WriteReq mshr uncacheable latency 310811201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average overall mshr uncacheable latency 310911374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 148193.566448 # average overall mshr uncacheable latency 311011353Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111650.537634 # average overall mshr uncacheable latency 311111374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 160879.796728 # average overall mshr uncacheable latency 311211374Ssteve.reinhardt@amd.comsystem.l2c.overall_avg_mshr_uncacheable_latency::total 138261.266457 # average overall mshr uncacheable latency 311310515SAli.Saidi@ARM.comsystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 311411374Ssteve.reinhardt@amd.comsystem.membus.trans_dist::ReadReq 90728 # Transaction distribution 311511374Ssteve.reinhardt@amd.comsystem.membus.trans_dist::ReadResp 1177835 # Transaction distribution 311611374Ssteve.reinhardt@amd.comsystem.membus.trans_dist::WriteReq 38212 # Transaction distribution 311711374Ssteve.reinhardt@amd.comsystem.membus.trans_dist::WriteResp 38212 # Transaction distribution 311811374Ssteve.reinhardt@amd.comsystem.membus.trans_dist::WritebackDirty 1451911 # Transaction distribution 311911374Ssteve.reinhardt@amd.comsystem.membus.trans_dist::CleanEvict 312799 # Transaction distribution 312011374Ssteve.reinhardt@amd.comsystem.membus.trans_dist::UpgradeReq 438732 # Transaction distribution 312111374Ssteve.reinhardt@amd.comsystem.membus.trans_dist::SCUpgradeReq 328709 # Transaction distribution 312211336Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 23 # Transaction distribution 312311374Ssteve.reinhardt@amd.comsystem.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution 312411374Ssteve.reinhardt@amd.comsystem.membus.trans_dist::ReadExReq 166722 # Transaction distribution 312511374Ssteve.reinhardt@amd.comsystem.membus.trans_dist::ReadExResp 150087 # Transaction distribution 312611374Ssteve.reinhardt@amd.comsystem.membus.trans_dist::ReadSharedReq 1087107 # Transaction distribution 312711374Ssteve.reinhardt@amd.comsystem.membus.trans_dist::InvalidateReq 695373 # Transaction distribution 312811374Ssteve.reinhardt@amd.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122964 # Packet count per connected master and slave (bytes) 312910585Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) 313011374Ssteve.reinhardt@amd.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24892 # Packet count per connected master and slave (bytes) 313111374Ssteve.reinhardt@amd.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5587054 # Packet count per connected master and slave (bytes) 313211374Ssteve.reinhardt@amd.comsystem.membus.pkt_count_system.l2c.mem_side::total 5734962 # Packet count per connected master and slave (bytes) 313311374Ssteve.reinhardt@amd.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238554 # Packet count per connected master and slave (bytes) 313411374Ssteve.reinhardt@amd.comsystem.membus.pkt_count_system.iocache.mem_side::total 238554 # Packet count per connected master and slave (bytes) 313511374Ssteve.reinhardt@amd.comsystem.membus.pkt_count::total 5973516 # Packet count per connected master and slave (bytes) 313611374Ssteve.reinhardt@amd.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156002 # Cumulative packet size per connected master and slave (bytes) 313710585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) 313811374Ssteve.reinhardt@amd.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49784 # Cumulative packet size per connected master and slave (bytes) 313911374Ssteve.reinhardt@amd.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 168012608 # Cumulative packet size per connected master and slave (bytes) 314011374Ssteve.reinhardt@amd.comsystem.membus.pkt_size_system.l2c.mem_side::total 168219718 # Cumulative packet size per connected master and slave (bytes) 314111374Ssteve.reinhardt@amd.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7276864 # Cumulative packet size per connected master and slave (bytes) 314211374Ssteve.reinhardt@amd.comsystem.membus.pkt_size_system.iocache.mem_side::total 7276864 # Cumulative packet size per connected master and slave (bytes) 314311374Ssteve.reinhardt@amd.comsystem.membus.pkt_size::total 175496582 # Cumulative packet size per connected master and slave (bytes) 314411374Ssteve.reinhardt@amd.comsystem.membus.snoops 622390 # Total snoops (count) 314511374Ssteve.reinhardt@amd.comsystem.membus.snoop_fanout::samples 4610336 # Request fanout histogram 314610585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 314710585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 314810585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 314910585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 315011374Ssteve.reinhardt@amd.comsystem.membus.snoop_fanout::1 4610336 100.00% 100.00% # Request fanout histogram 315110585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 315210585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 315310585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 315410585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 315511374Ssteve.reinhardt@amd.comsystem.membus.snoop_fanout::total 4610336 # Request fanout histogram 315611374Ssteve.reinhardt@amd.comsystem.membus.reqLayer0.occupancy 110366494 # Layer occupancy (ticks) 315710585Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 315810892Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks) 315910585Sandreas.hansson@arm.comsystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 316011374Ssteve.reinhardt@amd.comsystem.membus.reqLayer2.occupancy 20951999 # Layer occupancy (ticks) 316110585Sandreas.hansson@arm.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 316211374Ssteve.reinhardt@amd.comsystem.membus.reqLayer5.occupancy 10147074149 # Layer occupancy (ticks) 316310585Sandreas.hansson@arm.comsystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 316411374Ssteve.reinhardt@amd.comsystem.membus.respLayer2.occupancy 6858565377 # Layer occupancy (ticks) 316510585Sandreas.hansson@arm.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 316611374Ssteve.reinhardt@amd.comsystem.membus.respLayer3.occupancy 45617493 # Layer occupancy (ticks) 316710585Sandreas.hansson@arm.comsystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 316811239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 316911239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 317011239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 317111239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 317211239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 317311239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 317410515SAli.Saidi@ARM.comsystem.realview.ethernet.txBytes 966 # Bytes Transmitted 317510515SAli.Saidi@ARM.comsystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 317610515SAli.Saidi@ARM.comsystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 317710515SAli.Saidi@ARM.comsystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 317810515SAli.Saidi@ARM.comsystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 317910515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 318010515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 318110515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 318210515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 318311201Sandreas.hansson@arm.comsystem.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 318410515SAli.Saidi@ARM.comsystem.realview.ethernet.totPackets 3 # Total Packets 318510515SAli.Saidi@ARM.comsystem.realview.ethernet.totBytes 966 # Total Bytes 318610515SAli.Saidi@ARM.comsystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 318711201Sandreas.hansson@arm.comsystem.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 318810515SAli.Saidi@ARM.comsystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 318910515SAli.Saidi@ARM.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 319010515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 319110515SAli.Saidi@ARM.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 319210515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 319310515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 319410515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 319510515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 319610515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 319710515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 319810515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 319910515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 320010515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 320110515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 320210515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 320310515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 320410515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 320510515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 320610515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 320710515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 320810515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 320910515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 321010515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 321110515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 321210515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 321310515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 321410515SAli.Saidi@ARM.comsystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 321510515SAli.Saidi@ARM.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 321611239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 321711239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 321811239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 321911239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 322011374Ssteve.reinhardt@amd.comsystem.toL2Bus.snoop_filter.tot_requests 13817515 # Total number of requests made to the snoop filter. 322111374Ssteve.reinhardt@amd.comsystem.toL2Bus.snoop_filter.hit_single_requests 7477037 # Number of requests hitting in the snoop filter with a single holder of the requested data. 322211374Ssteve.reinhardt@amd.comsystem.toL2Bus.snoop_filter.hit_multi_requests 2215935 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 322311374Ssteve.reinhardt@amd.comsystem.toL2Bus.snoop_filter.tot_snoops 187202 # Total number of snoops made to the snoop filter. 322411374Ssteve.reinhardt@amd.comsystem.toL2Bus.snoop_filter.hit_single_snoops 169247 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 322511374Ssteve.reinhardt@amd.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 17955 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 322611374Ssteve.reinhardt@amd.comsystem.toL2Bus.trans_dist::ReadReq 90730 # Transaction distribution 322711374Ssteve.reinhardt@amd.comsystem.toL2Bus.trans_dist::ReadResp 5393978 # Transaction distribution 322811374Ssteve.reinhardt@amd.comsystem.toL2Bus.trans_dist::WriteReq 38212 # Transaction distribution 322911374Ssteve.reinhardt@amd.comsystem.toL2Bus.trans_dist::WriteResp 38212 # Transaction distribution 323011374Ssteve.reinhardt@amd.comsystem.toL2Bus.trans_dist::WritebackDirty 4613586 # Transaction distribution 323111374Ssteve.reinhardt@amd.comsystem.toL2Bus.trans_dist::CleanEvict 3368394 # Transaction distribution 323211374Ssteve.reinhardt@amd.comsystem.toL2Bus.trans_dist::UpgradeReq 769711 # Transaction distribution 323311374Ssteve.reinhardt@amd.comsystem.toL2Bus.trans_dist::SCUpgradeReq 415575 # Transaction distribution 323411374Ssteve.reinhardt@amd.comsystem.toL2Bus.trans_dist::UpgradeResp 1185286 # Transaction distribution 323511374Ssteve.reinhardt@amd.comsystem.toL2Bus.trans_dist::SCUpgradeFailReq 166 # Transaction distribution 323611374Ssteve.reinhardt@amd.comsystem.toL2Bus.trans_dist::UpgradeFailResp 166 # Transaction distribution 323711374Ssteve.reinhardt@amd.comsystem.toL2Bus.trans_dist::ReadExReq 331620 # Transaction distribution 323811374Ssteve.reinhardt@amd.comsystem.toL2Bus.trans_dist::ReadExResp 331620 # Transaction distribution 323911374Ssteve.reinhardt@amd.comsystem.toL2Bus.trans_dist::ReadSharedReq 5310492 # Transaction distribution 324011374Ssteve.reinhardt@amd.comsystem.toL2Bus.trans_dist::InvalidateReq 975909 # Transaction distribution 324111374Ssteve.reinhardt@amd.comsystem.toL2Bus.trans_dist::InvalidateResp 868925 # Transaction distribution 324211374Ssteve.reinhardt@amd.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10817825 # Packet count per connected master and slave (bytes) 324311374Ssteve.reinhardt@amd.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 9492092 # Packet count per connected master and slave (bytes) 324411374Ssteve.reinhardt@amd.comsystem.toL2Bus.pkt_count::total 20309917 # Packet count per connected master and slave (bytes) 324511374Ssteve.reinhardt@amd.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 274107435 # Cumulative packet size per connected master and slave (bytes) 324611374Ssteve.reinhardt@amd.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 237950875 # Cumulative packet size per connected master and slave (bytes) 324711374Ssteve.reinhardt@amd.comsystem.toL2Bus.pkt_size::total 512058310 # Cumulative packet size per connected master and slave (bytes) 324811374Ssteve.reinhardt@amd.comsystem.toL2Bus.snoops 3424368 # Total snoops (count) 324911374Ssteve.reinhardt@amd.comsystem.toL2Bus.snoop_fanout::samples 9784683 # Request fanout histogram 325011374Ssteve.reinhardt@amd.comsystem.toL2Bus.snoop_fanout::mean 0.340448 # Request fanout histogram 325111374Ssteve.reinhardt@amd.comsystem.toL2Bus.snoop_fanout::stdev 0.477717 # Request fanout histogram 325210515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 325311374Ssteve.reinhardt@amd.comsystem.toL2Bus.snoop_fanout::0 6471464 66.14% 66.14% # Request fanout histogram 325411374Ssteve.reinhardt@amd.comsystem.toL2Bus.snoop_fanout::1 3295264 33.68% 99.82% # Request fanout histogram 325511374Ssteve.reinhardt@amd.comsystem.toL2Bus.snoop_fanout::2 17955 0.18% 100.00% # Request fanout histogram 325610515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 325711138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 325810515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 325911374Ssteve.reinhardt@amd.comsystem.toL2Bus.snoop_fanout::total 9784683 # Request fanout histogram 326011374Ssteve.reinhardt@amd.comsystem.toL2Bus.reqLayer0.occupancy 10614903907 # Layer occupancy (ticks) 326110515SAli.Saidi@ARM.comsystem.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 326211374Ssteve.reinhardt@amd.comsystem.toL2Bus.snoopLayer0.occupancy 2624417 # Layer occupancy (ticks) 326310515SAli.Saidi@ARM.comsystem.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 326411374Ssteve.reinhardt@amd.comsystem.toL2Bus.respLayer0.occupancy 5004390482 # Layer occupancy (ticks) 326510515SAli.Saidi@ARM.comsystem.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 326611374Ssteve.reinhardt@amd.comsystem.toL2Bus.respLayer1.occupancy 4630478453 # Layer occupancy (ticks) 326710515SAli.Saidi@ARM.comsystem.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 326810515SAli.Saidi@ARM.com 326910515SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 3270