xref: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 47.496138                       # Number of seconds simulated
sim_ticks                                47496138032000                       # Number of ticks simulated
final_tick                               47496138032000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 287392                       # Simulator instruction rate (inst/s)
host_op_rate                                   338020                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            15163142641                       # Simulator tick rate (ticks/s)
host_mem_usage                                 759192                       # Number of bytes of host memory used
host_seconds                                  3132.34                       # Real time elapsed on the host
sim_insts                                   900209792                       # Number of instructions simulated
sim_ops                                    1058792792                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker       123968                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker        99904                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          7981184                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         13323912                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher     15275072                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       135168                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       122048                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          3081152                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         10821968                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher     12736320                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        446656                       # Number of bytes read from this memory
system.physmem.bytes_read::total             64147352                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      7981184                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      3081152                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total        11062336                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     76613760                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::total          76634344                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         1937                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         1561                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst            124706                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            208199                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       238673                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         2112                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         1907                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             48143                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            169106                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher       199005                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6979                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1002328                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1197090                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1199664                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          2610                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          2103                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              168039                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              280526                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher       321607                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          2846                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          2570                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               64872                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              227849                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       268155                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             9404                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1350580                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         168039                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          64872                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             232910                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1613052                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                433                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1613486                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1613052                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         2610                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         2103                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             168039                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             280960                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher       321607                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         2846                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         2570                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              64872                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             227850                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       268155                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            9404                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2964066                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1002328                       # Number of read requests accepted
system.physmem.writeReqs                      1199664                       # Number of write requests accepted
system.physmem.readBursts                     1002328                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1199664                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 64118976                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     30016                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  76632896                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  64147352                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               76634344                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      469                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2245                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               52312                       # Per bank write bursts
system.physmem.perBankRdBursts::1               66235                       # Per bank write bursts
system.physmem.perBankRdBursts::2               59334                       # Per bank write bursts
system.physmem.perBankRdBursts::3               65978                       # Per bank write bursts
system.physmem.perBankRdBursts::4               61446                       # Per bank write bursts
system.physmem.perBankRdBursts::5               69476                       # Per bank write bursts
system.physmem.perBankRdBursts::6               59128                       # Per bank write bursts
system.physmem.perBankRdBursts::7               60480                       # Per bank write bursts
system.physmem.perBankRdBursts::8               57677                       # Per bank write bursts
system.physmem.perBankRdBursts::9              110303                       # Per bank write bursts
system.physmem.perBankRdBursts::10              51521                       # Per bank write bursts
system.physmem.perBankRdBursts::11              60498                       # Per bank write bursts
system.physmem.perBankRdBursts::12              54125                       # Per bank write bursts
system.physmem.perBankRdBursts::13              57278                       # Per bank write bursts
system.physmem.perBankRdBursts::14              58648                       # Per bank write bursts
system.physmem.perBankRdBursts::15              57420                       # Per bank write bursts
system.physmem.perBankWrBursts::0               71344                       # Per bank write bursts
system.physmem.perBankWrBursts::1               78863                       # Per bank write bursts
system.physmem.perBankWrBursts::2               73221                       # Per bank write bursts
system.physmem.perBankWrBursts::3               79189                       # Per bank write bursts
system.physmem.perBankWrBursts::4               75543                       # Per bank write bursts
system.physmem.perBankWrBursts::5               82829                       # Per bank write bursts
system.physmem.perBankWrBursts::6               74512                       # Per bank write bursts
system.physmem.perBankWrBursts::7               77237                       # Per bank write bursts
system.physmem.perBankWrBursts::8               71961                       # Per bank write bursts
system.physmem.perBankWrBursts::9               73593                       # Per bank write bursts
system.physmem.perBankWrBursts::10              69363                       # Per bank write bursts
system.physmem.perBankWrBursts::11              76682                       # Per bank write bursts
system.physmem.perBankWrBursts::12              71227                       # Per bank write bursts
system.physmem.perBankWrBursts::13              74509                       # Per bank write bursts
system.physmem.perBankWrBursts::14              73049                       # Per bank write bursts
system.physmem.perBankWrBursts::15              74267                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          57                       # Number of times write queue was full causing retry
system.physmem.totGap                    47496135919500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1002298                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1197090                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    675393                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    118123                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     43619                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     33801                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                     29137                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                     27086                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                     24475                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     22026                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     18598                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      3546                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1664                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1196                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      985                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      727                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      426                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      352                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      286                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      223                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      119                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       69                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        8                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    31163                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    38080                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    51935                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    55190                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    60170                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    62406                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    65836                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    70016                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    72724                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    73495                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    74816                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    77871                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    75261                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    76182                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    84001                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    74766                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    69103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    66691                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     3873                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     2118                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     1475                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     1059                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      826                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      727                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      636                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      578                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      535                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      498                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      445                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      421                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      456                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      364                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      377                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      296                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      346                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      303                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      249                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      301                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      234                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      209                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      168                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      220                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      172                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      141                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      155                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      143                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       87                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      167                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       993836                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      141.624332                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean      96.550200                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     190.035765                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         676204     68.04%     68.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       192250     19.34%     87.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        44807      4.51%     91.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        21137      2.13%     94.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        15251      1.53%     95.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         9933      1.00%     96.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         5714      0.57%     97.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         4523      0.46%     97.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        24017      2.42%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         993836                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         62276                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        16.086984                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      158.174793                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          62273    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::25600-26623            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::29696-30719            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           62276                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         62276                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        19.227134                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.463029                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        8.016188                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           49891     80.11%     80.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23            5512      8.85%     88.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27            3034      4.87%     93.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31            1650      2.65%     96.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             463      0.74%     97.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             302      0.48%     97.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             265      0.43%     98.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              82      0.13%     98.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51             283      0.45%     98.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              77      0.12%     98.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              32      0.05%     98.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              49      0.08%     98.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             248      0.40%     99.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              39      0.06%     99.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              31      0.05%     99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79             106      0.17%     99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83             143      0.23%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               4      0.01%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               2      0.00%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               1      0.00%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             3      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             4      0.01%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             3      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             5      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             2      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             1      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            12      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             5      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             5      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147            11      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             4      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-243             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           62276                       # Writes before turning the bus around for reads
system.physmem.totQLat                    32552700191                       # Total ticks spent queuing
system.physmem.totMemAccLat               51337556441                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   5009295000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       32492.30                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  51242.30                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.35                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.61                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.35                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.61                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.13                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        23.36                       # Average write queue length when enqueuing
system.physmem.readRowHits                     748874                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    456536                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   74.75                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  38.13                       # Row buffer hit rate for writes
system.physmem.avgGap                     21569622.38                       # Average gap between requests
system.physmem.pageHitRate                      54.81                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 3877765920                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 2115844500                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                3856171800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               3970542240                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3102216508560                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1199773763640                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           27445246701750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             31761057298410                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.708277                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   45657180846254                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1586000260000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    252951953746                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 3635634240                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1983729000                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                3958266000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               3788538480                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3102216508560                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1194664304160                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           27449728675500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             31759975655940                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.685504                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   45664625089280                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1586000260000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    245507696970                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst          704                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          576                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data            8                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total          1324                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          704                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          576                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total         1280                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           11                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst            9                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             26                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           15                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           12                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               28                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           15                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           12                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           27                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           15                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           12                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              28                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1671                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6846976                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1674                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups              138061860                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         98120507                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          6229967                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups           103103324                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               75422199                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            73.152054                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS               16055942                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect           1103312                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                   287097                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               287097                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2         9253                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        79328                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples       287097                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0         287097    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       287097                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples        88581                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 23354.082704                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 21377.049680                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 19303.806083                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535        87487     98.76%     98.76% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071          212      0.24%     99.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607          756      0.85%     99.86% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143           30      0.03%     99.89% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679           31      0.03%     99.93% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215           18      0.02%     99.95% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751           29      0.03%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287           10      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::589824-655359            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total        88581                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples   -909613592                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0     -909613592    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total   -909613592                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        79328     89.55%     89.55% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M         9253     10.45%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total        88581                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       287097                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       287097                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        88581                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        88581                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       375678                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    87655759                       # DTB read hits
system.cpu0.dtb.read_misses                    237615                       # DTB read misses
system.cpu0.dtb.write_hits                   78096829                       # DTB write hits
system.cpu0.dtb.write_misses                    49482                       # DTB write misses
system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              42183                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                   1063                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   36184                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     2196                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  9698                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                    11726                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                87893374                       # DTB read accesses
system.cpu0.dtb.write_accesses               78146311                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        165752588                       # DTB hits
system.cpu0.dtb.misses                         287097                       # DTB misses
system.cpu0.dtb.accesses                    166039685                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                    66101                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                66101                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2          650                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        56681                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples        66101                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0          66101    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        66101                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        57331                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 26460.544906                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 23886.492389                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 21943.926110                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535        56305     98.21%     98.21% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071           11      0.02%     98.23% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607          903      1.58%     99.80% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143           44      0.08%     99.88% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679           42      0.07%     99.95% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215           14      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751            8      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-524287            3      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        57331                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples   -910742092                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     -910742092    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total   -910742092                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        56681     98.87%     98.87% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M          650      1.13%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        57331                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        66101                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        66101                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        57331                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        57331                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       123432                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   246672238                       # ITB inst hits
system.cpu0.itb.inst_misses                     66101                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              42183                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                   1063                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   25870                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                   211969                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               246738339                       # ITB inst accesses
system.cpu0.itb.hits                        246672238                       # DTB hits
system.cpu0.itb.misses                          66101                       # DTB misses
system.cpu0.itb.accesses                    246738339                       # DTB accesses
system.cpu0.numCycles                      1042581150                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                  455270721                       # Number of instructions committed
system.cpu0.committedOps                    534899361                       # Number of ops (including micro ops) committed
system.cpu0.discardedOps                     47095692                       # Number of ops (including micro ops) which were discarded before commit
system.cpu0.numFetchSuspends                     4288                       # Number of times Execute suspended instruction fetching
system.cpu0.quiesceCycles                 93950410811                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.cpi                              2.290025                       # CPI: cycles per instruction
system.cpu0.ipc                              0.436677                       # IPC: instructions per cycle
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   13221                       # number of quiesce instructions executed
system.cpu0.tickCycles                      736979138                       # Number of cycles that the object actually ticked
system.cpu0.idleCycles                      305602012                       # Total number of cycles that the object has spent stopped
system.cpu0.dcache.tags.replacements          5679788                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          503.382728                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          157129733                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          5680300                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            27.662224                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       7690769000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   503.382728                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.983169                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.983169                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           59                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          439                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           14                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        334387337                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       334387337                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     80268736                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       80268736                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     72233903                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      72233903                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       277349                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       277349                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       251788                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       251788                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1785654                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      1785654                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1744754                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      1744754                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    152502639                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       152502639                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    152779988                       # number of overall hits
system.cpu0.dcache.overall_hits::total      152779988                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      3412741                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      3412741                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      2489296                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      2489296                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       686937                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       686937                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       801634                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total       801634                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       154902                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       154902                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data       194385                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total       194385                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      5902037                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       5902037                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      6588974                       # number of overall misses
system.cpu0.dcache.overall_misses::total      6588974                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  58848858500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  58848858500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  63605542500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  63605542500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  48599001500                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  48599001500                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2502004000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   2502004000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   5451875000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total   5451875000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      6380500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      6380500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 122454401000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 122454401000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 122454401000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 122454401000                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     83681477                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     83681477                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     74723199                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     74723199                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       964286                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       964286                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data      1053422                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total      1053422                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1940556                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      1940556                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1939139                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      1939139                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    158404676                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    158404676                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    159368962                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    159368962                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.040783                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.040783                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.033314                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.033314                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.712379                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.712379                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.760981                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.760981                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.079824                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.079824                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.100243                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.100243                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.037259                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.037259                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.041344                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.041344                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17243.868931                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 17243.868931                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25551.618811                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 25551.618811                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 60624.925465                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 60624.925465                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16152.173632                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16152.173632                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28046.788590                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28046.788590                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20747.819948                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 20747.819948                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18584.744909                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 18584.744909                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      5679821                       # number of writebacks
system.cpu0.dcache.writebacks::total          5679821                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       423726                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       423726                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1038452                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1038452                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data           85                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total           85                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        41327                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        41327                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data           43                       # number of StoreCondReq MSHR hits
system.cpu0.dcache.StoreCondReq_mshr_hits::total           43                       # number of StoreCondReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1462178                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      1462178                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1462178                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      1462178                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2989015                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      2989015                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1450844                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      1450844                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       685285                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       685285                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       801549                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total       801549                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       113575                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       113575                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       194342                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total       194342                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      4439859                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      4439859                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      5125144                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      5125144                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        32143                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        32143                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        31553                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        31553                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        63696                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        63696                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  46000579500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  46000579500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  36719986000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  36719986000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  17989395000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  17989395000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  47789065000                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  47789065000                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1631247500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1631247500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   5254690500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   5254690500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      6005000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      6005000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  82720565500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  82720565500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 100709960500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 100709960500                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6124425500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6124425500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5931269500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5931269500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  12055695000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12055695000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.035719                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.035719                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019416                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019416                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.710666                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.710666                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.760900                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.760900                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.058527                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.058527                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.100221                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.100221                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028029                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.028029                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032159                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.032159                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15389.879107                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15389.879107                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25309.396462                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25309.396462                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26250.968575                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26250.968575                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 59620.890301                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 59620.890301                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14362.733876                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14362.733876                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27038.367929                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27038.367929                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18631.349667                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18631.349667                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19650.171878                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19650.171878                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190536.835392                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190536.835392                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 187977.989415                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 187977.989415                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 189269.263376                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 189269.263376                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          9549530                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.897064                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          236903550                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          9550042                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            24.806545                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      33055106000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.897064                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999799                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999799                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           95                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          311                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          106                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        502457255                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       502457255                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    236903550                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      236903550                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    236903550                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       236903550                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    236903550                       # number of overall hits
system.cpu0.icache.overall_hits::total      236903550                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      9550052                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      9550052                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      9550052                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       9550052                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      9550052                       # number of overall misses
system.cpu0.icache.overall_misses::total      9550052                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 101421985500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 101421985500                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 101421985500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 101421985500                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 101421985500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 101421985500                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    246453602                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    246453602                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    246453602                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    246453602                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    246453602                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    246453602                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.038750                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.038750                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.038750                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.038750                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.038750                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.038750                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10620.045367                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10620.045367                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10620.045367                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10620.045367                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10620.045367                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10620.045367                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks::writebacks      9549530                       # number of writebacks
system.cpu0.icache.writebacks::total          9549530                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      9550052                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      9550052                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      9550052                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      9550052                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      9550052                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      9550052                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        52309                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total        52309                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        52309                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total        52309                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  96646960000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  96646960000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  96646960000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  96646960000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  96646960000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  96646960000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   7414627000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   7414627000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   7414627000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   7414627000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.038750                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.038750                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.038750                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.038750                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.038750                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.038750                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10120.045420                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10120.045420                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10120.045420                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10120.045420                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10120.045420                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10120.045420                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141746.678392                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141746.678392                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued      7772165                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      7773534                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit         1208                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage       991570                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements         2865211                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16182.470551                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs          23591597                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs         2881428                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            8.187467                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle      8707838500                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 15283.265421                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    60.779936                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    54.474522                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   783.950672                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.932816                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003710                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.003325                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.047849                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.987700                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1265                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           55                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14897                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           23                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          535                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          649                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4           58                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            9                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           45                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            1                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           76                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1135                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         5291                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7937                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4          458                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.077209                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.003357                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.909241                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses       513878817                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses      513878817                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       534301                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       171000                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total        705301                       # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks      3781367                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total      3781367                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks     11445215                       # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total     11445215                       # number of WritebackClean hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data          428                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total          428                       # number of UpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       897370                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       897370                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      8796749                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      8796749                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2760570                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total      2760570                       # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       203097                       # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total       203097                       # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       534301                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker       171000                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      8796749                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data      3657940                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total       13159990                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       534301                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker       171000                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      8796749                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data      3657940                       # number of overall hits
system.cpu0.l2cache.overall_hits::total      13159990                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        12394                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         8896                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total        21290                       # number of ReadReq misses
system.cpu0.l2cache.WritebackDirty_misses::writebacks            2                       # number of WritebackDirty misses
system.cpu0.l2cache.WritebackDirty_misses::total            2                       # number of WritebackDirty misses
system.cpu0.l2cache.WritebackClean_misses::writebacks            1                       # number of WritebackClean misses
system.cpu0.l2cache.WritebackClean_misses::total            1                       # number of WritebackClean misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       263050                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total       263050                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       194335                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total       194335                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            7                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            7                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data       298989                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total       298989                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       753302                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total       753302                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data      1026998                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total      1026998                       # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       596103                       # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total       596103                       # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        12394                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker         8896                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       753302                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data      1325987                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total      2100579                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        12394                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker         8896                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       753302                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data      1325987                       # number of overall misses
system.cpu0.l2cache.overall_misses::total      2100579                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    543058500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    406297500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total    949356000                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   3394715000                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total   3394715000                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   1886445500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   1886445500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      5898999                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      5898999                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  19173654497                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total  19173654497                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  29218782500                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total  29218782500                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  41703375488                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total  41703375488                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data    451954500                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::total    451954500                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    543058500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    406297500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst  29218782500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data  60877029985                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total  91045168485                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    543058500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    406297500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst  29218782500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data  60877029985                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total  91045168485                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       546695                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       179896                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total       726591                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks      3781369                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total      3781369                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks     11445216                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total     11445216                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       263478                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total       263478                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       194335                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total       194335                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            7                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            7                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1196359                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total      1196359                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      9550051                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      9550051                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      3787568                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total      3787568                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       799200                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::total       799200                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       546695                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       179896                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      9550051                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data      4983927                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total     15260569                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       546695                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       179896                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      9550051                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data      4983927                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total     15260569                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.022671                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.049451                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.029301                       # miss rate for ReadReq accesses
system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks     0.000001                       # miss rate for WritebackDirty accesses
system.cpu0.l2cache.WritebackDirty_miss_rate::total     0.000001                       # miss rate for WritebackDirty accesses
system.cpu0.l2cache.WritebackClean_miss_rate::writebacks     0.000000                       # miss rate for WritebackClean accesses
system.cpu0.l2cache.WritebackClean_miss_rate::total     0.000000                       # miss rate for WritebackClean accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.998376                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.998376                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.249916                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.249916                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.078879                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.078879                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.271150                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.271150                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.745875                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.745875                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.022671                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.049451                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.078879                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.266053                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.137647                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.022671                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.049451                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.078879                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.266053                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.137647                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 43816.241730                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 45671.931205                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 44591.639267                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 12905.208135                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 12905.208135                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  9707.183472                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  9707.183472                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 842714.142857                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 842714.142857                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 64128.294007                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 64128.294007                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 38787.607759                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 38787.607759                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 40607.065922                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 40607.065922                       # average ReadSharedReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data   758.181891                       # average InvalidateReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total   758.181891                       # average InvalidateReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 43816.241730                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 45671.931205                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38787.607759                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 45910.729129                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 43342.891881                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 43816.241730                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 45671.931205                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38787.607759                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45910.729129                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 43342.891881                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks      1676207                       # number of writebacks
system.cpu0.l2cache.writebacks::total         1676207                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker            2                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total            2                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         9778                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         9778                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst            9                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total            9                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data         1426                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total         1426                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data            3                       # number of InvalidateReq MSHR hits
system.cpu0.l2cache.InvalidateReq_mshr_hits::total            3                       # number of InvalidateReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker            2                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst            9                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data        11204                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total        11215                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker            2                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst            9                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data        11204                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total        11215                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        12394                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         8894                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total        21288                       # number of ReadReq MSHR misses
system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks            2                       # number of WritebackDirty MSHR misses
system.cpu0.l2cache.WritebackDirty_mshr_misses::total            2                       # number of WritebackDirty MSHR misses
system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks            1                       # number of WritebackClean MSHR misses
system.cpu0.l2cache.WritebackClean_mshr_misses::total            1                       # number of WritebackClean MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       800672                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       800672                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       263050                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total       263050                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       194335                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       194335                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            7                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            7                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       289211                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total       289211                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       753293                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       753293                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data      1025572                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total      1025572                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       596100                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::total       596100                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        12394                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         8894                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       753293                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1314783                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total      2089364                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        12394                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         8894                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       753293                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1314783                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       800672                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total      2890036                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        52309                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        32143                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        84452                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        31553                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        31553                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        52309                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        63696                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total       116005                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    468694500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    352893500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    821588000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  47791541037                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  47791541037                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   7826601497                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   7826601497                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   3792362000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   3792362000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      5478999                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      5478999                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  16008058497                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  16008058497                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  24698519500                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  24698519500                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  35410416988                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  35410416988                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  41536789000                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  41536789000                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    468694500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    352893500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  24698519500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  51418475485                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total  76938582985                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    468694500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    352893500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  24698519500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  51418475485                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  47791541037                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 124730124022                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   6996155000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5867073000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total  12863228000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5694540000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5694540000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   6996155000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  11561613000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  18557768000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.022671                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.049440                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.029298                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks     0.000001                       # mshr miss rate for WritebackDirty accesses
system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total     0.000001                       # mshr miss rate for WritebackDirty accesses
system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for WritebackClean accesses
system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total     0.000000                       # mshr miss rate for WritebackClean accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.998376                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.998376                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.241743                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.241743                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.078878                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.078878                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.270773                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.270773                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.745871                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.745871                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.022671                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.049440                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.078878                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.263805                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.136913                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.022671                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.049440                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.078878                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.263805                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.189379                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 37816.241730                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 39677.704070                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38593.949643                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59689.287295                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 59689.287295                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29753.284535                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29753.284535                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19514.559909                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19514.559909                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 782714.142857                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 782714.142857                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 55350.794047                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 55350.794047                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32787.400786                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32787.400786                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 34527.480263                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 34527.480263                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 69680.907566                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69680.907566                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 37816.241730                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 39677.704070                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32787.400786                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 39107.955826                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36823.924881                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 37816.241730                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 39677.704070                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32787.400786                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 39107.955826                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59689.287295                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 43158.674848                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182530.348754                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 152314.071899                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 180475.390613                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 180475.390613                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 181512.386963                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 159973.863196                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.snoop_filter.tot_requests     31336515                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests     16003499                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         2764                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops      2238925                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops      2238443                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops          482                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.trans_dist::ReadReq        888197                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp     14329408                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        31554                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        31553                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty      5463883                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean     11447979                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict      3030252                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq      1046563                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq       472775                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       352055                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       529438                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           72                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          135                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq      1230630                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp      1206068                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      9550052                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4850843                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq       854414                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp       799200                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     28754250                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     18474160                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       377323                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1153011                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total         48758744                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side   1225720896                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    689935275                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1439168                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      4373560                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total        1921468899                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    7541383                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples     23989921                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.106643                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.308724                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0          21432051     89.34%     89.34% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1           2557388     10.66%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2               482      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total      23989921                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy   31215182485                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    206081920                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy  14406948660                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   8156637515                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy    197502349                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy    606443243                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.branchPred.lookups              134798362                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         95816419                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect          6051956                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups           100961028                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits               73848042                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            73.145097                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS               15861028                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect           1023147                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                   282723                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               282723                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        10766                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        86594                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples       282723                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0         282723    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       282723                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples        97360                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 23363.804437                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 21328.911362                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 20585.456118                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535        96095     98.70%     98.70% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071          182      0.19%     98.89% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607          912      0.94%     99.82% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143           29      0.03%     99.85% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679           42      0.04%     99.90% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215           31      0.03%     99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751           49      0.05%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287           15      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::786432-851967            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total        97360                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples   1788277352                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     1788277352    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   1788277352                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        86594     88.94%     88.94% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M        10766     11.06%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total        97360                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       282723                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       282723                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        97360                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        97360                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       380083                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    88221750                       # DTB read hits
system.cpu1.dtb.read_misses                    234611                       # DTB read misses
system.cpu1.dtb.write_hits                   76459163                       # DTB write hits
system.cpu1.dtb.write_misses                    48112                       # DTB write misses
system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              42183                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                   1063                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   39871                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                     1240                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  8073                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    11018                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                88456361                       # DTB read accesses
system.cpu1.dtb.write_accesses               76507275                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        164680913                       # DTB hits
system.cpu1.dtb.misses                         282723                       # DTB misses
system.cpu1.dtb.accesses                    164963636                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                    64693                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                64693                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2          526                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        55247                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples        64693                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0          64693    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        64693                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        55773                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 26679.495455                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 23706.173761                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 24561.580376                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535        54531     97.77%     97.77% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071            9      0.02%     97.79% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607         1101      1.97%     99.76% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143           35      0.06%     99.83% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679           52      0.09%     99.92% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215           31      0.06%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287            6      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        55773                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples   1787261852                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     1787261852    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   1787261852                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        55247     99.06%     99.06% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M          526      0.94%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        55773                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        64693                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        64693                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        55773                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        55773                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       120466                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   241355329                       # ITB inst hits
system.cpu1.itb.inst_misses                     64693                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              42183                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                   1063                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   28782                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                   214506                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               241420022                       # ITB inst accesses
system.cpu1.itb.hits                        241355329                       # DTB hits
system.cpu1.itb.misses                          64693                       # DTB misses
system.cpu1.itb.accesses                    241420022                       # DTB accesses
system.cpu1.numCycles                       943222184                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                  444939071                       # Number of instructions committed
system.cpu1.committedOps                    523893431                       # Number of ops (including micro ops) committed
system.cpu1.discardedOps                     46484386                       # Number of ops (including micro ops) which were discarded before commit
system.cpu1.numFetchSuspends                     5697                       # Number of times Execute suspended instruction fetching
system.cpu1.quiesceCycles                 94049904755                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.cpi                              2.119891                       # CPI: cycles per instruction
system.cpu1.ipc                              0.471722                       # IPC: instructions per cycle
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    5760                       # number of quiesce instructions executed
system.cpu1.tickCycles                      722277565                       # Number of cycles that the object actually ticked
system.cpu1.idleCycles                      220944619                       # Total number of cycles that the object has spent stopped
system.cpu1.dcache.tags.replacements          5315264                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          430.485039                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs          156623393                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs          5315774                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            29.463892                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     8391021559000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   430.485039                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.840791                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.840791                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0           22                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          221                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          267                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses        332053228                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses       332053228                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data     80890555                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       80890555                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data     71395384                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total      71395384                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data       230003                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total       230003                       # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data        70856                       # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total        70856                       # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1784180                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total      1784180                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1762697                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total      1762697                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data    152285939                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total       152285939                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data    152515942                       # number of overall hits
system.cpu1.dcache.overall_hits::total      152515942                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data      3470383                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total      3470383                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      2256465                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      2256465                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data       629037                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total       629037                       # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data       454847                       # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total       454847                       # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       178965                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total       178965                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data       198846                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total       198846                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      5726848                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       5726848                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      6355885                       # number of overall misses
system.cpu1.dcache.overall_misses::total      6355885                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  57691506500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total  57691506500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  50161466000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  50161466000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  17158564500                       # number of WriteLineReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::total  17158564500                       # number of WriteLineReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2980004000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total   2980004000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   5546868500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total   5546868500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      5779500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      5779500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 107852972500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 107852972500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 107852972500                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 107852972500                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data     84360938                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     84360938                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data     73651849                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total     73651849                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       859040                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       859040                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       525703                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total       525703                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1963145                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total      1963145                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1961543                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total      1961543                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data    158012787                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total    158012787                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data    158871827                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total    158871827                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.041137                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.041137                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.030637                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.030637                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.732256                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.732256                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.865217                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total     0.865217                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.091162                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.091162                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.101372                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.101372                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.036243                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.036243                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.040006                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.040006                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16623.959517                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 16623.959517                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22230.110372                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 22230.110372                       # average WriteReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 37723.815921                       # average WriteLineReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 37723.815921                       # average WriteLineReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16651.322884                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16651.322884                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27895.298372                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27895.298372                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18832.868010                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 18832.868010                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16968.993696                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 16968.993696                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks      5315289                       # number of writebacks
system.cpu1.dcache.writebacks::total          5315289                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       392143                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total       392143                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       920496                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total       920496                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data           60                       # number of WriteLineReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::total           60                       # number of WriteLineReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        44592                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        44592                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data           44                       # number of StoreCondReq MSHR hits
system.cpu1.dcache.StoreCondReq_mshr_hits::total           44                       # number of StoreCondReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data      1312639                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total      1312639                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data      1312639                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total      1312639                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      3078240                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total      3078240                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1335969                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total      1335969                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       628734                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total       628734                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       454787                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::total       454787                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       134373                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total       134373                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       198802                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total       198802                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data      4414209                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total      4414209                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data      5042943                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total      5042943                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         6731                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total         6731                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         7202                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total         7202                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        13933                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total        13933                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  46218671000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total  46218671000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  29907223500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total  29907223500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  14916352500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  14916352500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  16698306500                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  16698306500                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1935752000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1935752000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   5344630000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   5344630000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      5479500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      5479500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  76125894500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total  76125894500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  91042247000                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total  91042247000                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    839317500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    839317500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1016449500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   1016449500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1855767000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1855767000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036489                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036489                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018139                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018139                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.731903                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.731903                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.865103                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.865103                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.068448                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.068448                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.101350                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.101350                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027936                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.027936                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.031742                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.031742                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15014.641808                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15014.641808                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22386.165772                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22386.165772                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23724.424796                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23724.424796                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 36716.763012                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 36716.763012                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14405.810691                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14405.810691                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26884.186276                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26884.186276                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17245.647975                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17245.647975                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18053.396003                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18053.396003                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 124694.324766                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 124694.324766                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 141134.337684                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 141134.337684                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 133192.205555                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 133192.205555                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements          9419212                       # number of replacements
system.cpu1.icache.tags.tagsinuse          506.776997                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs          231714815                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          9419724                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            24.598896                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     8379179578000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   506.776997                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.989799                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.989799                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0          194                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          220                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2           98                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses        491688802                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses       491688802                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst    231714815                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total      231714815                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst    231714815                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total       231714815                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst    231714815                       # number of overall hits
system.cpu1.icache.overall_hits::total      231714815                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      9419724                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      9419724                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      9419724                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       9419724                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      9419724                       # number of overall misses
system.cpu1.icache.overall_misses::total      9419724                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  96182532500                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total  96182532500                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst  96182532500                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total  96182532500                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst  96182532500                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total  96182532500                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst    241134539                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total    241134539                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst    241134539                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total    241134539                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst    241134539                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total    241134539                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.039064                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.039064                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.039064                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.039064                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.039064                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.039064                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10210.759094                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 10210.759094                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10210.759094                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 10210.759094                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10210.759094                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 10210.759094                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.writebacks::writebacks      9419212                       # number of writebacks
system.cpu1.icache.writebacks::total          9419212                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      9419724                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total      9419724                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst      9419724                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total      9419724                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst      9419724                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total      9419724                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst           93                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total           93                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst           93                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total           93                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  91472670500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total  91472670500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  91472670500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total  91472670500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  91472670500                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total  91472670500                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     13081000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     13081000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     13081000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     13081000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.039064                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.039064                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.039064                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.039064                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.039064                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.039064                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  9710.759094                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  9710.759094                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  9710.759094                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  9710.759094                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  9710.759094                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  9710.759094                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 140655.913978                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 140655.913978                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 140655.913978                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 140655.913978                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued      7256046                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified      7256259                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit          183                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage       925773                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements         2304751                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       13454.881705                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs          23669466                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs         2320587                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs           10.199775                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle    9853632359500                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 12618.151234                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    61.761915                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    57.964405                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   717.004151                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.770151                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.003770                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.003538                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.043762                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.821221                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1043                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           71                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14722                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1            3                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          319                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          650                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4           71                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           45                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           24                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            2                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           22                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          391                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         5507                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         8143                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4          659                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.063660                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.004333                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.898560                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses       496871809                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses      496871809                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       551874                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       166024                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total        717898                       # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks      3295376                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total      3295376                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks     11437109                       # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total     11437109                       # number of WritebackClean hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data          567                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total          567                       # number of UpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data       865133                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total       865133                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      8732847                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total      8732847                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2873391                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total      2873391                       # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       191011                       # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total       191011                       # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       551874                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker       166024                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      8732847                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data      3738524                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total       13189269                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       551874                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker       166024                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      8732847                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data      3738524                       # number of overall hits
system.cpu1.l2cache.overall_hits::total      13189269                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        11967                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         8433                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        20400                       # number of ReadReq misses
system.cpu1.l2cache.WritebackDirty_misses::writebacks            1                       # number of WritebackDirty misses
system.cpu1.l2cache.WritebackDirty_misses::total            1                       # number of WritebackDirty misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       222957                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total       222957                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       198797                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total       198797                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            5                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            5                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data       249481                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total       249481                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       686877                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total       686877                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       967667                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total       967667                       # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       262059                       # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total       262059                       # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        11967                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker         8433                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       686877                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data      1217148                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total      1924425                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        11967                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker         8433                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       686877                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data      1217148                       # number of overall misses
system.cpu1.l2cache.overall_misses::total      1924425                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    548385000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    436726500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total    985111500                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   3348912000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total   3348912000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   1915512500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   1915512500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      5381000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      5381000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  13948272999                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total  13948272999                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  24574911500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total  24574911500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  38337752989                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total  38337752989                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data    401272000                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::total    401272000                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    548385000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    436726500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst  24574911500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data  52286025988                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total  77846048988                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    548385000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    436726500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst  24574911500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data  52286025988                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total  77846048988                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       563841                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       174457                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total       738298                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks      3295377                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total      3295377                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks     11437109                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total     11437109                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       223524                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total       223524                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       198797                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total       198797                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            5                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            5                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1114614                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total      1114614                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      9419724                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total      9419724                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3841058                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total      3841058                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       453070                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total       453070                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       563841                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       174457                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      9419724                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data      4955672                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total     15113694                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       563841                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       174457                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      9419724                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data      4955672                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total     15113694                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.021224                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.048339                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.027631                       # miss rate for ReadReq accesses
system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks     0.000000                       # miss rate for WritebackDirty accesses
system.cpu1.l2cache.WritebackDirty_miss_rate::total     0.000000                       # miss rate for WritebackDirty accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.997463                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.997463                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.223827                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.223827                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.072919                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.072919                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.251927                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.251927                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.578407                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.578407                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.021224                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.048339                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.072919                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.245607                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.127330                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.021224                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.048339                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.072919                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.245607                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.127330                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 45824.768112                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 51787.797937                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 48289.779412                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 15020.438919                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 15020.438919                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  9635.520154                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  9635.520154                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data      1076200                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total      1076200                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 55909.159411                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 55909.159411                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35777.746962                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35777.746962                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 39618.745900                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 39618.745900                       # average ReadSharedReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data  1531.227701                       # average InvalidateReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total  1531.227701                       # average InvalidateReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 45824.768112                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 51787.797937                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35777.746962                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 42957.821060                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 40451.588910                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 45824.768112                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 51787.797937                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35777.746962                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 42957.821060                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 40451.588910                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks      1133493                       # number of writebacks
system.cpu1.l2cache.writebacks::total         1133493                       # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker            1                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         6803                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total         6803                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            1                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          882                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          882                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data            3                       # number of InvalidateReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::total            3                       # number of InvalidateReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker            1                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            1                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data         7685                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total         7687                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker            1                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            1                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data         7685                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total         7687                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        11967                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         8432                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total        20399                       # number of ReadReq MSHR misses
system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks            1                       # number of WritebackDirty MSHR misses
system.cpu1.l2cache.WritebackDirty_mshr_misses::total            1                       # number of WritebackDirty MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       726483                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total       726483                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       222957                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total       222957                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       198797                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       198797                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            5                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            5                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       242678                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total       242678                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       686876                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       686876                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       966785                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       966785                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       262056                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::total       262056                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        11967                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         8432                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       686876                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1209463                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total      1916738                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        11967                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         8432                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       686876                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1209463                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       726483                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total      2643221                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst           93                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         6731                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         6824                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         7202                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         7202                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst           93                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        13933                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        14026                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    476583000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    386118000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    862701000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  38725078481                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  38725078481                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   7000085492                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   7000085492                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   3849189999                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   3849189999                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      4991000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      4991000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data  11472999499                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total  11472999499                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  20453639500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  20453639500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  32473658989                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  32473658989                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data  13075073000                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  13075073000                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    476583000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    386118000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  20453639500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  43946658488                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total  65262998988                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    476583000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    386118000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  20453639500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  43946658488                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  38725078481                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 103988077469                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     12337000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    785396000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    797733000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    962364500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    962364500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     12337000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1747760500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1760097500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.021224                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.048333                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.027630                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for WritebackDirty accesses
system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total     0.000000                       # mshr miss rate for WritebackDirty accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.997463                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.997463                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.217724                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.217724                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.072919                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.072919                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.251698                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.251698                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.578401                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.578401                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.021224                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.048333                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.072919                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.244056                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.126821                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.021224                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.048333                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.072919                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.244056                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.174889                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 39824.768112                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 45791.982922                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 42291.337811                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53304.865332                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 53304.865332                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31396.571949                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31396.571949                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19362.414921                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19362.414921                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       998200                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       998200                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 47276.636115                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 47276.636115                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29777.775756                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29777.775756                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 33589.328536                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33589.328536                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 49894.194371                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 49894.194371                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 39824.768112                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 45791.982922                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29777.775756                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 36335.678304                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 34048.993127                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 39824.768112                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 45791.982922                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29777.775756                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 36335.678304                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53304.865332                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 39341.423766                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132655.913978                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116683.405140                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 116901.084408                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 133624.618162                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 133624.618162                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132655.913978                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 125440.357425                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 125488.200485                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.snoop_filter.tot_requests     30305906                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests     15477606                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         2013                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops      2090955                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops      2090626                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops          329                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.trans_dist::ReadReq        826390                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp     14176907                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq         7202                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         7202                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty      4434109                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean     11439122                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict      2886028                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq       940232                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFResp            2                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq       438079                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       353355                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp       486110                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           75                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          135                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq      1143505                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp      1120857                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq      9419724                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4894979                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq       500608                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp       453070                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     28258846                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     17165188                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       367696                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1190168                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total         46981898                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side   1205697856                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    663528133                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1395656                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4510728                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total        1875132373                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                    6705692                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples     22548909                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.107052                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.309227                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0          20135326     89.30%     89.30% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1           2413254     10.70%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2               329      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total      22548909                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy   30147553476                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy    176219861                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy  14133264904                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy   7885730738                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy    193298381                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy    626482687                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40387                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40387                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136979                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136979                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47868                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29756                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122958                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231694                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231694                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  354732                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47888                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17674                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155996                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7355128                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7355128                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7513210                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             47188500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                11000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               327500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               15000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            26264003                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            36399000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           568799211                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92966000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           148134000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115828                       # number of replacements
system.iocache.tags.tagsinuse               11.305227                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115844                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         9138950806000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.834041                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     7.471186                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.239628                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.466949                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.706577                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1042980                       # Number of tag accesses
system.iocache.tags.data_accesses             1042980                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8863                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8900                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106984                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106984                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8863                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8903                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8863                       # number of overall misses
system.iocache.overall_misses::total             8903                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5197000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1710789963                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1715986963                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  13562248248                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  13562248248                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5566000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1710789963                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1716355963                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5566000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1710789963                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1716355963                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8863                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8900                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106984                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106984                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8863                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8903                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8863                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8903                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140459.459459                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 193026.059235                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 192807.523933                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126768.939729                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 126768.939729                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       139150                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 193026.059235                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 192784.001236                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       139150                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 193026.059235                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 192784.001236                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         35587                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3530                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    10.081303                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106950                       # number of writebacks
system.iocache.writebacks::total               106950                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8863                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8900                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106984                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106984                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8863                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8903                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8863                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8903                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3347000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1267639963                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1270986963                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8206832286                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   8206832286                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3566000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1267639963                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1271205963                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3566000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1267639963                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1271205963                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90459.459459                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 143026.059235                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 142807.523933                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76710.837938                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76710.837938                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        89150                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 143026.059235                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 142784.001236                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        89150                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 143026.059235                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 142784.001236                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                  1399797                       # number of replacements
system.l2c.tags.tagsinuse                63464.709741                       # Cycle average of tags in use
system.l2c.tags.total_refs                    6644913                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1460922                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     4.548438                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle              13283135500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   21707.053985                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   102.735345                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   115.995716                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4966.190479                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     4993.948919                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  6019.423287                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   241.036337                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   317.216521                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     3872.812023                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     8822.287754                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 12306.009376                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.331223                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001568                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.001770                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.075778                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.076202                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.091849                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.003678                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.004840                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.059094                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.134617                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.187775                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.968395                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        10216                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023          187                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        50722                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1            2                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          140                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         3377                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4         6697                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3           10                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          176                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           35                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          273                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2228                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3        13666                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        34520                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.155884                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.002853                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.773956                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 81151228                       # Number of tag accesses
system.l2c.tags.data_accesses                81151228                       # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks      2809703                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total         2809703                       # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data          181902                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data          125777                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total              307679                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data         42034                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data         42908                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total             84942                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            62506                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            50661                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               113167                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         7522                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker         5409                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst       680705                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       645150                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       332678                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         6067                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4079                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst       638595                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       567372                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       305148                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          3192725                       # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data       139615                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data       131240                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total           270855                       # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker          7522                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          5409                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              680705                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              707656                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher       332678                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          6067                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          4079                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              638595                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              618033                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher       305148                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 3305892                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         7522                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         5409                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             680705                       # number of overall hits
system.l2c.overall_hits::cpu0.data             707656                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher       332678                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         6067                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         4079                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             638595                       # number of overall hits
system.l2c.overall_hits::cpu1.data             618033                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher       305148                       # number of overall hits
system.l2c.overall_hits::total                3305892                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data         64206                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         62132                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total            126338                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data        12168                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data        12142                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total           24310                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          79720                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          52688                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             132408                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         1937                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker         1561                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        72587                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       131602                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       238730                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         2112                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker         1907                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst        48281                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data       118892                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       199183                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         816792                       # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data       443932                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data       119113                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total         563045                       # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker         1937                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         1561                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             72587                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            211322                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       238730                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         2112                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         1907                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             48281                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            171580                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher       199183                       # number of demand (read+write) misses
system.l2c.demand_misses::total                949200                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         1937                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         1561                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            72587                       # number of overall misses
system.l2c.overall_misses::cpu0.data           211322                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       238730                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         2112                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         1907                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            48281                       # number of overall misses
system.l2c.overall_misses::cpu1.data           171580                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher       199183                       # number of overall misses
system.l2c.overall_misses::total               949200                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data   1150609000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data   1077871000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total   2228480000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data    192622500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data    197330500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total    389953000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data  11022660500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   7093820500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  18116481000                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    272199000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    220485500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   9769762500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  18492608500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  41827968898                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    294211000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    267576500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst   6491475500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data  16608783999                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  33224201492                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 127469272889                       # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu0.data    140111000                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data    126265000                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total    266376000                       # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    272199000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    220485500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   9769762500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  29515269000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  41827968898                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    294211000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    267576500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   6491475500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  23702604499                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  33224201492                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total    145585753889                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    272199000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    220485500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   9769762500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  29515269000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  41827968898                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    294211000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    267576500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   6491475500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  23702604499                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  33224201492                       # number of overall miss cycles
system.l2c.overall_miss_latency::total   145585753889                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks      2809703                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total      2809703                       # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data       246108                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data       187909                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total          434017                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data        54202                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data        55050                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total        109252                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       142226                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       103349                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           245575                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         9459                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         6970                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst       753292                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       776752                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       571408                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         8179                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         5986                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst       686876                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       686264                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       504331                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      4009517                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data       583547                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data       250353                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total       833900                       # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         9459                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         6970                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          753292                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          918978                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       571408                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         8179                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         5986                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          686876                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          789613                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher       504331                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             4255092                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         9459                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         6970                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         753292                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         918978                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       571408                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         8179                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         5986                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         686876                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         789613                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher       504331                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            4255092                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.260885                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.330649                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.291090                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.224494                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.220563                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.222513                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.560516                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.509807                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.539175                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.204779                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.223960                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.096360                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.169426                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.417793                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.258222                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.318577                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.070291                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.173245                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.394945                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.203713                       # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data     0.760748                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data     0.475780                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total     0.675195                       # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.204779                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.223960                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.096360                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.229953                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.417793                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.258222                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.318577                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.070291                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.217296                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.394945                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.223074                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.204779                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.223960                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.096360                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.229953                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.417793                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.258222                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.318577                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.070291                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.217296                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.394945                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.223074                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 17920.583746                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17348.081504                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 17639.031804                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15830.251479                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 16251.894251                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 16040.847388                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 138267.191420                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 134638.257288                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 136823.160232                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 140526.071244                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 141246.316464                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 134593.832229                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 140519.205635                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 175210.358556                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 139304.450758                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 140312.794966                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134451.968683                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 139696.396721                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 166802.395245                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 156060.873379                       # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu0.data   315.613653                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data  1060.043824                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total   473.098953                       # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 140526.071244                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 141246.316464                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 134593.832229                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 139669.646322                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 175210.358556                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 139304.450758                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 140312.794966                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 134451.968683                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 138143.166447                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 166802.395245                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 153377.321838                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 140526.071244                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 141246.316464                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 134593.832229                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 139669.646322                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 175210.358556                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 139304.450758                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 140312.794966                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 134451.968683                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 138143.166447                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 166802.395245                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 153377.321838                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs              1015                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        9                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs    112.777778                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks             1090140                       # number of writebacks
system.l2c.writebacks::total                  1090140                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          179                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data           23                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          207                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data           18                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total          427                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst            179                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             23                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst            207                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             18                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                427                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst           179                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            23                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst           207                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            18                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               427                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks        54511                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total        54511                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        64206                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        62132                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total       126338                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data        12168                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data        12142                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total        24310                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        79720                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        52688                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        132408                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         1937                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         1561                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        72408                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       131579                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       238730                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         2112                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         1907                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        48074                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data       118874                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       199183                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       816365                       # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu0.data       443932                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data       119113                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total       563045                       # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         1937                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         1561                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        72408                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       211299                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       238730                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         2112                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         1907                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        48074                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       171562                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       199183                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           948773                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         1937                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         1561                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        72408                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       211299                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       238730                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         2112                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         1907                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        48074                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       171562                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       199183                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          948773                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        52309                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        32143                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst           93                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data         6729                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        91274                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        31553                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         7202                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        38755                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        52309                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        63696                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst           93                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        13931                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total       130029                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data   4544765997                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data   4377476492                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total   8922242489                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    896994500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    892131500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total   1789126000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  10225195953                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   6566674837                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  16791870790                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker    252817523                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker    204866519                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   9025630028                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  17172972916                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  39438396932                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    273086509                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    248503510                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   5986913295                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  15417511413                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  31231074499                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 119251773144                       # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data  31065864000                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   8291731997                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total  39357595997                       # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    252817523                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    204866519                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   9025630028                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  27398168869                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  39438396932                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    273086509                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    248503510                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   5986913295                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  21984186250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  31231074499                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 136043643934                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    252817523                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    204866519                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   9025630028                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  27398168869                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  39438396932                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    273086509                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    248503510                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   5986913295                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  21984186250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  31231074499                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 136043643934                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   5897666000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5288332558                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     10383500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    664180522                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total  11860562580                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   5157955518                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    839811556                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   5997767074                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   5897666000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data  10446288076                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     10383500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1503992078                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  17858329654                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.260885                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.330649                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.291090                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.224494                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.220563                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.222513                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.560516                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.509807                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.539175                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.204779                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.223960                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.096122                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.169396                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.417793                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.258222                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.318577                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.069989                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.173219                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.394945                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.203607                       # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.760748                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.475780                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total     0.675195                       # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.204779                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.223960                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.096122                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.229928                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.417793                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.258222                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.318577                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.069989                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.217274                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.394945                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.222974                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.204779                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.223960                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.096122                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.229928                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.417793                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.258222                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.318577                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.069989                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.217274                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.394945                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.222974                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70784.132277                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70454.459731                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70622.002003                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73717.496713                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73474.839400                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73596.297820                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 128263.872968                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 124633.215096                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 126819.155867                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130520.146102                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 131240.563101                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124649.624738                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 130514.541956                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 165200.841671                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 129302.324337                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 130311.227058                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124535.368286                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 129696.244873                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 156795.883680                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 146076.538245                       # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 69978.879648                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69612.317690                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69901.332925                       # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130520.146102                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131240.563101                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124649.624738                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 129665.397702                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 165200.841671                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 129302.324337                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130311.227058                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124535.368286                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 128141.349774                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 156795.883680                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 143389.033978                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130520.146102                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131240.563101                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124649.624738                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 129665.397702                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 165200.841671                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129302.324337                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130311.227058                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124535.368286                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 128141.349774                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 156795.883680                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 143389.033978                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164525.170581                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111650.537634                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 98704.194085                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 129944.590793                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 163469.575571                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 116608.102749                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 154761.116604                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164002.261932                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111650.537634                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 107960.094609                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 137341.128933                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               91274                       # Transaction distribution
system.membus.trans_dist::ReadResp             916539                       # Transaction distribution
system.membus.trans_dist::WriteReq              38755                       # Transaction distribution
system.membus.trans_dist::WriteResp             38755                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1197090                       # Transaction distribution
system.membus.trans_dist::CleanEvict           262945                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           440993                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq         308067                       # Transaction distribution
system.membus.trans_dist::UpgradeResp              23                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
system.membus.trans_dist::ReadExReq            144406                       # Transaction distribution
system.membus.trans_dist::ReadExResp           127298                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        825265                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        666679                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122958                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           52                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        27076                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4666640                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4816726                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       238694                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       238694                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                5055420                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155996                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1324                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        54152                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    133490240                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    133701712                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7291456                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7291456                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               140993168                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           609728                       # Total snoops (count)
system.membus.snoop_fanout::samples           3975535                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 3975535    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             3975535                       # Request fanout histogram
system.membus.reqLayer0.occupancy           110272997                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               33984                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            22907496                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          8443265855                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         5364054651                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           45386996                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             163                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              163                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests     12590063                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      6816351                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests      2112405                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops         136080                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops       123352                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops        12728                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq              91276                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           4889046                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             38755                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            38755                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty      4006843                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean            1                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         3033326                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          740212                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq        393009                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp        1133221                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq          135                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp          135                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           301958                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          301958                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      4804997                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq       940884                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp       833900                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     10292862                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      8190937                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              18483799                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    255537947                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    200300853                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              455838800                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         3066288                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          8826957                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.357421                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.482240                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                5684742     64.40%     64.40% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                3129487     35.45%     99.86% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                  12728      0.14%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            8826957                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         9586281743                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          2585661                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        4723415116                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        4064152578                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------