stats.txt revision 11239
110515SAli.Saidi@ARM.com 210515SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 311201Sandreas.hansson@arm.comsim_seconds 47.381663 # Number of seconds simulated 411201Sandreas.hansson@arm.comsim_ticks 47381662864000 # Number of ticks simulated 511201Sandreas.hansson@arm.comfinal_tick 47381662864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 711239Sandreas.sandberg@arm.comhost_inst_rate 132815 # Simulator instruction rate (inst/s) 811239Sandreas.sandberg@arm.comhost_op_rate 156205 # Simulator op (including micro ops) rate (op/s) 911239Sandreas.sandberg@arm.comhost_tick_rate 7502885455 # Simulator tick rate (ticks/s) 1011239Sandreas.sandberg@arm.comhost_mem_usage 760860 # Number of bytes of host memory used 1111239Sandreas.sandberg@arm.comhost_seconds 6315.13 # Real time elapsed on the host 1211201Sandreas.hansson@arm.comsim_insts 838745469 # Number of instructions simulated 1311201Sandreas.hansson@arm.comsim_ops 986455629 # Number of ops (including micro ops) simulated 1410515SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 42368 # Number of bytes read from this memory 1711201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 41792 # Number of bytes read from this memory 1811201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 6976384 # Number of bytes read from this memory 1911201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 35367624 # Number of bytes read from this memory 2011201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.l2cache.prefetcher 9096640 # Number of bytes read from this memory 2111201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 59520 # Number of bytes read from this memory 2211201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.itb.walker 61888 # Number of bytes read from this memory 2311201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 3056960 # Number of bytes read from this memory 2411201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 12429456 # Number of bytes read from this memory 2511201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.l2cache.prefetcher 7583744 # Number of bytes read from this memory 2611201Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 432640 # Number of bytes read from this memory 2711201Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 75149016 # Number of bytes read from this memory 2811201Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 6976384 # Number of instructions bytes read from this memory 2911201Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 3056960 # Number of instructions bytes read from this memory 3011201Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 10033344 # Number of instructions bytes read from this memory 3111201Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 59523200 # Number of bytes written to this memory 3210827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 3310636Snilay@cs.wisc.edusystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3411201Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 59543784 # Number of bytes written to this memory 3511201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 662 # Number of read requests responded to by this memory 3611201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.itb.walker 653 # Number of read requests responded to by this memory 3711201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 109006 # Number of read requests responded to by this memory 3811201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 552632 # Number of read requests responded to by this memory 3911201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.l2cache.prefetcher 142135 # Number of read requests responded to by this memory 4011201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 930 # Number of read requests responded to by this memory 4111201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.itb.walker 967 # Number of read requests responded to by this memory 4211201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 47765 # Number of read requests responded to by this memory 4311201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 194223 # Number of read requests responded to by this memory 4411201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.l2cache.prefetcher 118496 # Number of read requests responded to by this memory 4511201Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 6760 # Number of read requests responded to by this memory 4611201Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1174229 # Number of read requests responded to by this memory 4711201Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 930050 # Number of write requests responded to by this memory 4810827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 4910636Snilay@cs.wisc.edusystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 5011201Sandreas.hansson@arm.comsystem.physmem.num_writes::total 932624 # Number of write requests responded to by this memory 5111201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 894 # Total read bandwidth from this memory (bytes/s) 5211201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.itb.walker 882 # Total read bandwidth from this memory (bytes/s) 5311201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 147238 # Total read bandwidth from this memory (bytes/s) 5411201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 746441 # Total read bandwidth from this memory (bytes/s) 5511201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.l2cache.prefetcher 191987 # Total read bandwidth from this memory (bytes/s) 5611201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 1256 # Total read bandwidth from this memory (bytes/s) 5711201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.itb.walker 1306 # Total read bandwidth from this memory (bytes/s) 5811201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 64518 # Total read bandwidth from this memory (bytes/s) 5911201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 262326 # Total read bandwidth from this memory (bytes/s) 6011201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.l2cache.prefetcher 160057 # Total read bandwidth from this memory (bytes/s) 6111201Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 9131 # Total read bandwidth from this memory (bytes/s) 6211201Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1586036 # Total read bandwidth from this memory (bytes/s) 6311201Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 147238 # Instruction read bandwidth from this memory (bytes/s) 6411201Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 64518 # Instruction read bandwidth from this memory (bytes/s) 6511201Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 211756 # Instruction read bandwidth from this memory (bytes/s) 6611201Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 1256250 # Write bandwidth from this memory (bytes/s) 6711201Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) 6810636Snilay@cs.wisc.edusystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 6911201Sandreas.hansson@arm.comsystem.physmem.bw_write::total 1256684 # Write bandwidth from this memory (bytes/s) 7011201Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 1256250 # Total bandwidth to/from this memory (bytes/s) 7111201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 894 # Total bandwidth to/from this memory (bytes/s) 7211201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.itb.walker 882 # Total bandwidth to/from this memory (bytes/s) 7311201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 147238 # Total bandwidth to/from this memory (bytes/s) 7411201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 746876 # Total bandwidth to/from this memory (bytes/s) 7511201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.l2cache.prefetcher 191987 # Total bandwidth to/from this memory (bytes/s) 7611201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 1256 # Total bandwidth to/from this memory (bytes/s) 7711201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.itb.walker 1306 # Total bandwidth to/from this memory (bytes/s) 7811201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 64518 # Total bandwidth to/from this memory (bytes/s) 7911201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 262326 # Total bandwidth to/from this memory (bytes/s) 8011201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.l2cache.prefetcher 160057 # Total bandwidth to/from this memory (bytes/s) 8111201Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 9131 # Total bandwidth to/from this memory (bytes/s) 8211201Sandreas.hansson@arm.comsystem.physmem.bw_total::total 2842720 # Total bandwidth to/from this memory (bytes/s) 8311201Sandreas.hansson@arm.comsystem.physmem.readReqs 1174229 # Number of read requests accepted 8411201Sandreas.hansson@arm.comsystem.physmem.writeReqs 932624 # Number of write requests accepted 8511201Sandreas.hansson@arm.comsystem.physmem.readBursts 1174229 # Number of DRAM read bursts, including those serviced by the write queue 8611201Sandreas.hansson@arm.comsystem.physmem.writeBursts 932624 # Number of DRAM write bursts, including those merged in the write queue 8711201Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 75113152 # Total number of bytes read from DRAM 8811201Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 37504 # Total number of bytes read from write queue 8911201Sandreas.hansson@arm.comsystem.physmem.bytesWritten 59543040 # Total number of bytes written to DRAM 9011201Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 75149016 # Total read bytes from the system interface side 9111201Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 59543784 # Total written bytes from the system interface side 9211201Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 586 # Number of DRAM read bursts serviced by the write queue 9311201Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one 9411201Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 448232 # Number of requests that are neither read nor write 9511201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 71067 # Per bank write bursts 9611201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 73380 # Per bank write bursts 9711201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 69314 # Per bank write bursts 9811201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 74537 # Per bank write bursts 9911201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 66547 # Per bank write bursts 10011201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 79030 # Per bank write bursts 10111201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 66275 # Per bank write bursts 10211201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 68082 # Per bank write bursts 10311201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 68948 # Per bank write bursts 10411201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 127738 # Per bank write bursts 10511201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 63222 # Per bank write bursts 10611201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 73993 # Per bank write bursts 10711201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 67075 # Per bank write bursts 10811201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 69321 # Per bank write bursts 10911201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 63089 # Per bank write bursts 11011201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 72025 # Per bank write bursts 11111201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 57427 # Per bank write bursts 11211201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 61393 # Per bank write bursts 11311201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 59144 # Per bank write bursts 11411201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 61303 # Per bank write bursts 11511201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 56823 # Per bank write bursts 11611201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 63517 # Per bank write bursts 11711201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 54876 # Per bank write bursts 11811201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 56576 # Per bank write bursts 11911201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 56101 # Per bank write bursts 12011201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 62480 # Per bank write bursts 12111201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 54750 # Per bank write bursts 12211201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 61148 # Per bank write bursts 12311201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 54574 # Per bank write bursts 12411201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 57375 # Per bank write bursts 12511201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 53605 # Per bank write bursts 12611201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 59268 # Per bank write bursts 12710515SAli.Saidi@ARM.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 12811201Sandreas.hansson@arm.comsystem.physmem.numWrRetry 30 # Number of times write queue was full causing retry 12911201Sandreas.hansson@arm.comsystem.physmem.totGap 47381660751500 # Total gap between requests 13010515SAli.Saidi@ARM.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 13110515SAli.Saidi@ARM.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 13210515SAli.Saidi@ARM.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 13310827Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 25 # Read request sizes (log2) 13410515SAli.Saidi@ARM.comsystem.physmem.readPktSize::4 5 # Read request sizes (log2) 13510515SAli.Saidi@ARM.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 13611201Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 1174199 # Read request sizes (log2) 13710515SAli.Saidi@ARM.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 13810515SAli.Saidi@ARM.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 13910515SAli.Saidi@ARM.comsystem.physmem.writePktSize::2 2 # Write request sizes (log2) 14010827Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 14110515SAli.Saidi@ARM.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 14210515SAli.Saidi@ARM.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 14311201Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 930050 # Write request sizes (log2) 14411201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 756841 # What read queue length does an incoming req see 14511201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 295232 # What read queue length does an incoming req see 14611201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 26539 # What read queue length does an incoming req see 14711201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 19834 # What read queue length does an incoming req see 14811201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 17154 # What read queue length does an incoming req see 14911201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 15837 # What read queue length does an incoming req see 15011201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 14079 # What read queue length does an incoming req see 15111201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 12670 # What read queue length does an incoming req see 15211201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 10425 # What read queue length does an incoming req see 15311201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 1820 # What read queue length does an incoming req see 15411201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 989 # What read queue length does an incoming req see 15511201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 647 # What read queue length does an incoming req see 15611201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 492 # What read queue length does an incoming req see 15711201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 324 # What read queue length does an incoming req see 15811201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 175 # What read queue length does an incoming req see 15911201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 157 # What read queue length does an incoming req see 16011201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 142 # What read queue length does an incoming req see 16111201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 119 # What read queue length does an incoming req see 16211201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 92 # What read queue length does an incoming req see 16311201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 62 # What read queue length does an incoming req see 16411167Sjthestness@gmail.comsystem.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see 16511201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see 16611201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 16711103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 16810515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 16910515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 17010515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 17110515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 17210515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 17310515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 17410515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 17510515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 17610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 17710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 17810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 17910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 18010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 18110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 18210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 18310515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 18410515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 18510515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 18610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 18710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 18810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 18910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 19010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 19111201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 16213 # What write queue length does an incoming req see 19211201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 18671 # What write queue length does an incoming req see 19311201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 35561 # What write queue length does an incoming req see 19411201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 45390 # What write queue length does an incoming req see 19511201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 50223 # What write queue length does an incoming req see 19611201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 52287 # What write queue length does an incoming req see 19711201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 55018 # What write queue length does an incoming req see 19811201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 55938 # What write queue length does an incoming req see 19911201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 58169 # What write queue length does an incoming req see 20011201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 58483 # What write queue length does an incoming req see 20111201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 59754 # What write queue length does an incoming req see 20211201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 64501 # What write queue length does an incoming req see 20311201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 60072 # What write queue length does an incoming req see 20411201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 59690 # What write queue length does an incoming req see 20511201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 64110 # What write queue length does an incoming req see 20611201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 58190 # What write queue length does an incoming req see 20711201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 54561 # What write queue length does an incoming req see 20811201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 52990 # What write queue length does an incoming req see 20911201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 1468 # What write queue length does an incoming req see 21011201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 888 # What write queue length does an incoming req see 21111201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 738 # What write queue length does an incoming req see 21211201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 611 # What write queue length does an incoming req see 21311201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 522 # What write queue length does an incoming req see 21411201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 526 # What write queue length does an incoming req see 21511201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 421 # What write queue length does an incoming req see 21611201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 413 # What write queue length does an incoming req see 21711201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 365 # What write queue length does an incoming req see 21811201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 349 # What write queue length does an incoming req see 21911201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 340 # What write queue length does an incoming req see 22011201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 397 # What write queue length does an incoming req see 22111201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 295 # What write queue length does an incoming req see 22211201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 327 # What write queue length does an incoming req see 22311201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 308 # What write queue length does an incoming req see 22411201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 322 # What write queue length does an incoming req see 22511201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 341 # What write queue length does an incoming req see 22611201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 256 # What write queue length does an incoming req see 22711201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 207 # What write queue length does an incoming req see 22811201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 224 # What write queue length does an incoming req see 22911201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 214 # What write queue length does an incoming req see 23011201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 174 # What write queue length does an incoming req see 23111201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 168 # What write queue length does an incoming req see 23211201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 120 # What write queue length does an incoming req see 23311201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 93 # What write queue length does an incoming req see 23411201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 83 # What write queue length does an incoming req see 23511201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 103 # What write queue length does an incoming req see 23611201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 80 # What write queue length does an incoming req see 23711201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 76 # What write queue length does an incoming req see 23811201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 43 # What write queue length does an incoming req see 23911201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 70 # What write queue length does an incoming req see 24011201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 709891 # Bytes accessed per row activation 24111201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 189.684557 # Bytes accessed per row activation 24211201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 114.673344 # Bytes accessed per row activation 24311201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 252.164844 # Bytes accessed per row activation 24411201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 431942 60.85% 60.85% # Bytes accessed per row activation 24511201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 132623 18.68% 79.53% # Bytes accessed per row activation 24611201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 44376 6.25% 85.78% # Bytes accessed per row activation 24711201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 24102 3.40% 89.17% # Bytes accessed per row activation 24811201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 15088 2.13% 91.30% # Bytes accessed per row activation 24911201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 9957 1.40% 92.70% # Bytes accessed per row activation 25011201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 7669 1.08% 93.78% # Bytes accessed per row activation 25111201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 7642 1.08% 94.86% # Bytes accessed per row activation 25211201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 36492 5.14% 100.00% # Bytes accessed per row activation 25311201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 709891 # Bytes accessed per row activation 25411201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 51534 # Reads before turning the bus around for writes 25511201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 22.773974 # Reads before turning the bus around for writes 25611201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 380.344580 # Reads before turning the bus around for writes 25711201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-4095 51531 99.99% 99.99% # Reads before turning the bus around for writes 25810892Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes 25910892Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes 26011103Snilay@cs.wisc.edusystem.physmem.rdPerTurnAround::81920-86015 1 0.00% 100.00% # Reads before turning the bus around for writes 26111201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 51534 # Reads before turning the bus around for writes 26211201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 51534 # Writes before turning the bus around for reads 26311201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 18.053324 # Writes before turning the bus around for reads 26411201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 17.386136 # Writes before turning the bus around for reads 26511201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 7.764507 # Writes before turning the bus around for reads 26611201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16-19 48029 93.20% 93.20% # Writes before turning the bus around for reads 26711201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::20-23 1359 2.64% 95.84% # Writes before turning the bus around for reads 26811201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24-27 210 0.41% 96.24% # Writes before turning the bus around for reads 26911201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::28-31 316 0.61% 96.86% # Writes before turning the bus around for reads 27011201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32-35 77 0.15% 97.01% # Writes before turning the bus around for reads 27111201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::36-39 304 0.59% 97.60% # Writes before turning the bus around for reads 27211201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::40-43 196 0.38% 97.98% # Writes before turning the bus around for reads 27311201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::44-47 89 0.17% 98.15% # Writes before turning the bus around for reads 27411201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48-51 103 0.20% 98.35% # Writes before turning the bus around for reads 27511201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::52-55 90 0.17% 98.52% # Writes before turning the bus around for reads 27611201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::56-59 42 0.08% 98.60% # Writes before turning the bus around for reads 27711201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::60-63 57 0.11% 98.72% # Writes before turning the bus around for reads 27811201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::64-67 406 0.79% 99.50% # Writes before turning the bus around for reads 27911201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::68-71 44 0.09% 99.59% # Writes before turning the bus around for reads 28011201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::72-75 34 0.07% 99.65% # Writes before turning the bus around for reads 28111201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::76-79 103 0.20% 99.85% # Writes before turning the bus around for reads 28211201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::80-83 21 0.04% 99.90% # Writes before turning the bus around for reads 28311201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::84-87 3 0.01% 99.90% # Writes before turning the bus around for reads 28411201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::88-91 1 0.00% 99.90% # Writes before turning the bus around for reads 28511201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::92-95 3 0.01% 99.91% # Writes before turning the bus around for reads 28611201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::100-103 2 0.00% 99.91% # Writes before turning the bus around for reads 28711201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::104-107 2 0.00% 99.92% # Writes before turning the bus around for reads 28811201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::116-119 2 0.00% 99.92% # Writes before turning the bus around for reads 28911201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::120-123 3 0.01% 99.93% # Writes before turning the bus around for reads 29011201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::124-127 2 0.00% 99.93% # Writes before turning the bus around for reads 29111201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::128-131 20 0.04% 99.97% # Writes before turning the bus around for reads 29211201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::136-139 2 0.00% 99.97% # Writes before turning the bus around for reads 29311201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::140-143 2 0.00% 99.98% # Writes before turning the bus around for reads 29411201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::144-147 1 0.00% 99.98% # Writes before turning the bus around for reads 29511201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::152-155 6 0.01% 99.99% # Writes before turning the bus around for reads 29611201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads 29711167Sjthestness@gmail.comsystem.physmem.wrPerTurnAround::164-167 2 0.00% 100.00% # Writes before turning the bus around for reads 29811167Sjthestness@gmail.comsystem.physmem.wrPerTurnAround::168-171 1 0.00% 100.00% # Writes before turning the bus around for reads 29911201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 51534 # Writes before turning the bus around for reads 30011201Sandreas.hansson@arm.comsystem.physmem.totQLat 26583019130 # Total ticks spent queuing 30111201Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 48588825380 # Total ticks spent from burst creation until serviced by the DRAM 30211201Sandreas.hansson@arm.comsystem.physmem.totBusLat 5868215000 # Total ticks spent in databus transfers 30311201Sandreas.hansson@arm.comsystem.physmem.avgQLat 22650.00 # Average queueing delay per DRAM burst 30410515SAli.Saidi@ARM.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 30511201Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 41400.00 # Average memory access latency per DRAM burst 30611201Sandreas.hansson@arm.comsystem.physmem.avgRdBW 1.59 # Average DRAM read bandwidth in MiByte/s 30711201Sandreas.hansson@arm.comsystem.physmem.avgWrBW 1.26 # Average achieved write bandwidth in MiByte/s 30811201Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 1.59 # Average system read bandwidth in MiByte/s 30911201Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 1.26 # Average system write bandwidth in MiByte/s 31010515SAli.Saidi@ARM.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 31111201Sandreas.hansson@arm.comsystem.physmem.busUtil 0.02 # Data bus utilization in percentage 31211201Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 31310892Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 31411201Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 31511201Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 21.83 # Average write queue length when enqueuing 31611201Sandreas.hansson@arm.comsystem.physmem.readRowHits 952385 # Number of row buffer hits during reads 31711201Sandreas.hansson@arm.comsystem.physmem.writeRowHits 441721 # Number of row buffer hits during writes 31811201Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 81.15 # Row buffer hit rate for reads 31911201Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 47.48 # Row buffer hit rate for writes 32011201Sandreas.hansson@arm.comsystem.physmem.avgGap 22489305.50 # Average gap between requests 32111201Sandreas.hansson@arm.comsystem.physmem.pageHitRate 66.26 # Row buffer hit rate, read and write combined 32211201Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 2710380960 # Energy for activate commands per rank (pJ) 32311201Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 1478878500 # Energy for precharge commands per rank (pJ) 32411201Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 4432209600 # Energy for read commands per rank (pJ) 32511201Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 3052442880 # Energy for write commands per rank (pJ) 32611201Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 3094739659440 # Energy for refresh commands per rank (pJ) 32711201Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 1177500235590 # Energy for active background per rank (pJ) 32811201Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 27396100823250 # Energy for precharge background per rank (pJ) 32911201Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 31680014630220 # Total energy per rank (pJ) 33011201Sandreas.hansson@arm.comsystem.physmem_0.averagePower 668.613444 # Core power per rank (mW) 33111201Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 45575607610794 # Time in different power states 33211201Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 1582177740000 # Time in different power states 33310628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 33411201Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 223874273456 # Time in different power states 33510628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 33611201Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 2656364760 # Energy for activate commands per rank (pJ) 33711201Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 1449405375 # Energy for precharge commands per rank (pJ) 33811201Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 4722003000 # Energy for read commands per rank (pJ) 33911201Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 2976166800 # Energy for write commands per rank (pJ) 34011201Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 3094739659440 # Energy for refresh commands per rank (pJ) 34111201Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 1182079758375 # Energy for active background per rank (pJ) 34211201Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 27392083725750 # Energy for precharge background per rank (pJ) 34311201Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 31680707083500 # Total energy per rank (pJ) 34411201Sandreas.hansson@arm.comsystem.physmem_1.averagePower 668.628058 # Core power per rank (mW) 34511201Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 45568857815114 # Time in different power states 34611201Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 1582177740000 # Time in different power states 34710628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 34811201Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 230624127636 # Time in different power states 34910628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 35010636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory 35110636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 35210636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory 35310636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 35410515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory 35510515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory 35610515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory 35710515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory 35810636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory 35910636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 36010636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory 36110636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 36210515SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory 36310636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) 36410636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 36510515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s) 36610636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 36710515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s) 36810515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) 36910515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s) 37010515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) 37110636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) 37210636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 37310515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s) 37410636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 37510515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) 37610585Sandreas.hansson@arm.comsystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 37710585Sandreas.hansson@arm.comsystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 37810585Sandreas.hansson@arm.comsystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 37911201Sandreas.hansson@arm.comsystem.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. 38011201Sandreas.hansson@arm.comsystem.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. 38111201Sandreas.hansson@arm.comsystem.cf0.dma_write_txs 1674 # Number of DMA write transactions. 38211201Sandreas.hansson@arm.comsystem.cpu0.branchPred.lookups 125258409 # Number of BP lookups 38311201Sandreas.hansson@arm.comsystem.cpu0.branchPred.condPredicted 88001025 # Number of conditional branches predicted 38411201Sandreas.hansson@arm.comsystem.cpu0.branchPred.condIncorrect 5802079 # Number of conditional branches incorrect 38511201Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBLookups 93100413 # Number of BTB lookups 38611201Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBHits 67841086 # Number of BTB hits 38710585Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 38811201Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBHitPct 72.868727 # BTB Hit Percentage 38911201Sandreas.hansson@arm.comsystem.cpu0.branchPred.usedRAS 15085862 # Number of times the RAS was used to get a target. 39011201Sandreas.hansson@arm.comsystem.cpu0.branchPred.RASInCorrect 1028654 # Number of incorrect RAS predictions. 39110515SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 39210628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 39310628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 39410628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 39510628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 39610628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 39710628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 39810628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 39910628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 40010585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 40110585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 40210585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 40310585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 40410585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 40510585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 40610585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 40710585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 40810585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 40910585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 41010585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 41110585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 41210585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 41310585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 41410585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 41510585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 41610585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 41710585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 41810585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 41910585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 42010585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 42111201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walks 252652 # Table walker walks requested 42211201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLong 252652 # Table walker walks initiated with long descriptors 42311201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level2 7537 # Level at which table walker walks with long descriptors terminate 42411201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level3 66702 # Level at which table walker walks with long descriptors terminate 42511201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 252652 # Table walker wait (enqueue to first request) latency 42611201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0 252652 100.00% 100.00% # Table walker wait (enqueue to first request) latency 42711201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 252652 # Table walker wait (enqueue to first request) latency 42811201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::samples 74239 # Table walker service (enqueue to completion) latency 42911201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::mean 22181.016716 # Table walker service (enqueue to completion) latency 43011201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::gmean 20809.120487 # Table walker service (enqueue to completion) latency 43111201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::stdev 13879.929548 # Table walker service (enqueue to completion) latency 43211201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::0-65535 73678 99.24% 99.24% # Table walker service (enqueue to completion) latency 43311201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::65536-131071 179 0.24% 99.49% # Table walker service (enqueue to completion) latency 43411201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::131072-196607 332 0.45% 99.93% # Table walker service (enqueue to completion) latency 43511201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::196608-262143 14 0.02% 99.95% # Table walker service (enqueue to completion) latency 43611201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::262144-327679 15 0.02% 99.97% # Table walker service (enqueue to completion) latency 43711201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::327680-393215 8 0.01% 99.98% # Table walker service (enqueue to completion) latency 43811201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::393216-458751 9 0.01% 99.99% # Table walker service (enqueue to completion) latency 43911201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 44011201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 44111201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::total 74239 # Table walker service (enqueue to completion) latency 44211201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::samples -909613592 # Table walker pending requests distribution 44311201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::0 -909613592 100.00% 100.00% # Table walker pending requests distribution 44411201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::total -909613592 # Table walker pending requests distribution 44511201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 66702 89.85% 89.85% # Table walker page sizes translated 44611201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::2M 7537 10.15% 100.00% # Table walker page sizes translated 44711201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 74239 # Table walker page sizes translated 44811201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 252652 # Table walker requests started/completed, data/inst 44910628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 45011201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 252652 # Table walker requests started/completed, data/inst 45111201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 74239 # Table walker requests started/completed, data/inst 45210628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 45311201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 74239 # Table walker requests started/completed, data/inst 45411201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 326891 # Table walker requests started/completed, data/inst 45510585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_hits 0 # ITB inst hits 45610585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_misses 0 # ITB inst misses 45711201Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 81678885 # DTB read hits 45811201Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 209727 # DTB read misses 45911201Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 70936828 # DTB write hits 46011201Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 42925 # DTB write misses 46110585Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 46210585Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 46311201Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 37374 # Number of times TLB was flushed by MVA & ASID 46411201Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_asid 1001 # Number of times TLB was flushed by ASID 46511201Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_entries 33720 # Number of entries that have been flushed from TLB 46611201Sandreas.hansson@arm.comsystem.cpu0.dtb.align_faults 1491 # Number of TLB faults due to alignment restrictions 46711201Sandreas.hansson@arm.comsystem.cpu0.dtb.prefetch_faults 8048 # Number of TLB faults due to prefetch 46810585Sandreas.hansson@arm.comsystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 46911201Sandreas.hansson@arm.comsystem.cpu0.dtb.perms_faults 9709 # Number of TLB faults due to permissions restrictions 47011201Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 81888612 # DTB read accesses 47111201Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 70979753 # DTB write accesses 47210585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 47311201Sandreas.hansson@arm.comsystem.cpu0.dtb.hits 152615713 # DTB hits 47411201Sandreas.hansson@arm.comsystem.cpu0.dtb.misses 252652 # DTB misses 47511201Sandreas.hansson@arm.comsystem.cpu0.dtb.accesses 152868365 # DTB accesses 47610628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 47710628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 47810628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 47910628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 48010628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 48110628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 48210628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 48310628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 48410585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 48510585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 48610585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 48710585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 48810585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 48910585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 49010585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 49110585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 49210585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 49310585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 49410585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 49510585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 49610585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 49710585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 49810585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 49910585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 50010585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 50110585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 50210585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 50310585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 50410585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 50511201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walks 57977 # Table walker walks requested 50611201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLong 57977 # Table walker walks initiated with long descriptors 50711201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level2 503 # Level at which table walker walks with long descriptors terminate 50811201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level3 46742 # Level at which table walker walks with long descriptors terminate 50911201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 57977 # Table walker wait (enqueue to first request) latency 51011201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::0 57977 100.00% 100.00% # Table walker wait (enqueue to first request) latency 51111201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 57977 # Table walker wait (enqueue to first request) latency 51211201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::samples 47245 # Table walker service (enqueue to completion) latency 51311201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::mean 24873.087099 # Table walker service (enqueue to completion) latency 51411201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::gmean 23068.832563 # Table walker service (enqueue to completion) latency 51511201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::stdev 17067.215870 # Table walker service (enqueue to completion) latency 51611201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::0-32767 43882 92.88% 92.88% # Table walker service (enqueue to completion) latency 51711201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::32768-65535 2853 6.04% 98.92% # Table walker service (enqueue to completion) latency 51811201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::65536-98303 11 0.02% 98.94% # Table walker service (enqueue to completion) latency 51911201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::131072-163839 288 0.61% 99.55% # Table walker service (enqueue to completion) latency 52011201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::163840-196607 169 0.36% 99.91% # Table walker service (enqueue to completion) latency 52111201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::196608-229375 7 0.01% 99.93% # Table walker service (enqueue to completion) latency 52211201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::229376-262143 6 0.01% 99.94% # Table walker service (enqueue to completion) latency 52311201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::262144-294911 4 0.01% 99.95% # Table walker service (enqueue to completion) latency 52411201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::294912-327679 13 0.03% 99.97% # Table walker service (enqueue to completion) latency 52511201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::327680-360447 3 0.01% 99.98% # Table walker service (enqueue to completion) latency 52611201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency 52711201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 52811201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 52911201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::total 47245 # Table walker service (enqueue to completion) latency 53011201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::samples -910742092 # Table walker pending requests distribution 53111201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::0 -910742092 100.00% 100.00% # Table walker pending requests distribution 53211201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::total -910742092 # Table walker pending requests distribution 53311201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 46742 98.94% 98.94% # Table walker page sizes translated 53411201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::2M 503 1.06% 100.00% # Table walker page sizes translated 53511201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 47245 # Table walker page sizes translated 53610628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 53711201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 57977 # Table walker requests started/completed, data/inst 53811201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 57977 # Table walker requests started/completed, data/inst 53910628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 54011201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 47245 # Table walker requests started/completed, data/inst 54111201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 47245 # Table walker requests started/completed, data/inst 54211201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 105222 # Table walker requests started/completed, data/inst 54311201Sandreas.hansson@arm.comsystem.cpu0.itb.inst_hits 224840362 # ITB inst hits 54411201Sandreas.hansson@arm.comsystem.cpu0.itb.inst_misses 57977 # ITB inst misses 54510585Sandreas.hansson@arm.comsystem.cpu0.itb.read_hits 0 # DTB read hits 54610585Sandreas.hansson@arm.comsystem.cpu0.itb.read_misses 0 # DTB read misses 54710585Sandreas.hansson@arm.comsystem.cpu0.itb.write_hits 0 # DTB write hits 54810585Sandreas.hansson@arm.comsystem.cpu0.itb.write_misses 0 # DTB write misses 54910585Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 55010585Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 55111201Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 37374 # Number of times TLB was flushed by MVA & ASID 55211201Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_asid 1001 # Number of times TLB was flushed by ASID 55311201Sandreas.hansson@arm.comsystem.cpu0.itb.flush_entries 24328 # Number of entries that have been flushed from TLB 55410585Sandreas.hansson@arm.comsystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 55510585Sandreas.hansson@arm.comsystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 55610585Sandreas.hansson@arm.comsystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 55711201Sandreas.hansson@arm.comsystem.cpu0.itb.perms_faults 193753 # Number of TLB faults due to permissions restrictions 55810585Sandreas.hansson@arm.comsystem.cpu0.itb.read_accesses 0 # DTB read accesses 55910585Sandreas.hansson@arm.comsystem.cpu0.itb.write_accesses 0 # DTB write accesses 56011201Sandreas.hansson@arm.comsystem.cpu0.itb.inst_accesses 224898339 # ITB inst accesses 56111201Sandreas.hansson@arm.comsystem.cpu0.itb.hits 224840362 # DTB hits 56211201Sandreas.hansson@arm.comsystem.cpu0.itb.misses 57977 # DTB misses 56311201Sandreas.hansson@arm.comsystem.cpu0.itb.accesses 224898339 # DTB accesses 56411201Sandreas.hansson@arm.comsystem.cpu0.numCycles 954325944 # number of cpu cycles simulated 56510585Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 56610585Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 56711201Sandreas.hansson@arm.comsystem.cpu0.committedInsts 417810947 # Number of instructions committed 56811201Sandreas.hansson@arm.comsystem.cpu0.committedOps 490605107 # Number of ops (including micro ops) committed 56911201Sandreas.hansson@arm.comsystem.cpu0.discardedOps 41344261 # Number of ops (including micro ops) which were discarded before commit 57011201Sandreas.hansson@arm.comsystem.cpu0.numFetchSuspends 4694 # Number of times Execute suspended instruction fetching 57111201Sandreas.hansson@arm.comsystem.cpu0.quiesceCycles 93809718025 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 57211201Sandreas.hansson@arm.comsystem.cpu0.cpi 2.284109 # CPI: cycles per instruction 57311201Sandreas.hansson@arm.comsystem.cpu0.ipc 0.437807 # IPC: instructions per cycle 57410585Sandreas.hansson@arm.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 57511201Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 4756 # number of quiesce instructions executed 57611201Sandreas.hansson@arm.comsystem.cpu0.tickCycles 674001287 # Number of cycles that the object actually ticked 57711201Sandreas.hansson@arm.comsystem.cpu0.idleCycles 280324657 # Total number of cycles that the object has spent stopped 57811201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 5190067 # number of replacements 57911201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 482.757722 # Cycle average of tags in use 58011201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 144829115 # Total number of references to valid blocks. 58111201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 5190578 # Sample count of references to valid blocks. 58211201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 27.902310 # Average number of references to valid blocks. 58311201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 7690769000 # Cycle when the warmup percentage was hit. 58411201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 482.757722 # Average occupied blocks per requestor 58511201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.942886 # Average percentage of cache occupancy 58611201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.942886 # Average percentage of cache occupancy 58711201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 58811201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id 58911201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id 59011201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 45 # Occupied blocks per task id 59111201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 59211201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 307937411 # Number of tag accesses 59311201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 307937411 # Number of data accesses 59411201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 74836049 # number of ReadReq hits 59511201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 74836049 # number of ReadReq hits 59611201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 65744025 # number of WriteReq hits 59711201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 65744025 # number of WriteReq hits 59811201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 248898 # number of SoftPFReq hits 59911201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 248898 # number of SoftPFReq hits 60011201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::cpu0.data 135683 # number of WriteLineReq hits 60111201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::total 135683 # number of WriteLineReq hits 60211201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1688860 # number of LoadLockedReq hits 60311201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 1688860 # number of LoadLockedReq hits 60411201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 1659238 # number of StoreCondReq hits 60511201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 1659238 # number of StoreCondReq hits 60611201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 140580074 # number of demand (read+write) hits 60711201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 140580074 # number of demand (read+write) hits 60811201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 140828972 # number of overall hits 60911201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 140828972 # number of overall hits 61011201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 3204136 # number of ReadReq misses 61111201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 3204136 # number of ReadReq misses 61211201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 2171939 # number of WriteReq misses 61311201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 2171939 # number of WriteReq misses 61411201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 583430 # number of SoftPFReq misses 61511201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 583430 # number of SoftPFReq misses 61611201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::cpu0.data 728874 # number of WriteLineReq misses 61711201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::total 728874 # number of WriteLineReq misses 61811201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 150550 # number of LoadLockedReq misses 61911201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 150550 # number of LoadLockedReq misses 62011201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 178568 # number of StoreCondReq misses 62111201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 178568 # number of StoreCondReq misses 62211201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 5376075 # number of demand (read+write) misses 62311201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 5376075 # number of demand (read+write) misses 62411201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 5959505 # number of overall misses 62511201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 5959505 # number of overall misses 62611201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 51043675000 # number of ReadReq miss cycles 62711201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 51043675000 # number of ReadReq miss cycles 62811201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 55065851500 # number of WriteReq miss cycles 62911201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 55065851500 # number of WriteReq miss cycles 63011201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 67163849000 # number of WriteLineReq miss cycles 63111201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::total 67163849000 # number of WriteLineReq miss cycles 63211201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2254990500 # number of LoadLockedReq miss cycles 63311201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 2254990500 # number of LoadLockedReq miss cycles 63411201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5008928500 # number of StoreCondReq miss cycles 63511201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 5008928500 # number of StoreCondReq miss cycles 63611201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5076500 # number of StoreCondFailReq miss cycles 63711201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::total 5076500 # number of StoreCondFailReq miss cycles 63811201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::cpu0.data 106109526500 # number of demand (read+write) miss cycles 63911201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::total 106109526500 # number of demand (read+write) miss cycles 64011201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::cpu0.data 106109526500 # number of overall miss cycles 64111201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::total 106109526500 # number of overall miss cycles 64211201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 78040185 # number of ReadReq accesses(hits+misses) 64311201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 78040185 # number of ReadReq accesses(hits+misses) 64411201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 67915964 # number of WriteReq accesses(hits+misses) 64511201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 67915964 # number of WriteReq accesses(hits+misses) 64611201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 832328 # number of SoftPFReq accesses(hits+misses) 64711201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 832328 # number of SoftPFReq accesses(hits+misses) 64811201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::cpu0.data 864557 # number of WriteLineReq accesses(hits+misses) 64911201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::total 864557 # number of WriteLineReq accesses(hits+misses) 65011201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1839410 # number of LoadLockedReq accesses(hits+misses) 65111201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 1839410 # number of LoadLockedReq accesses(hits+misses) 65211201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1837806 # number of StoreCondReq accesses(hits+misses) 65311201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 1837806 # number of StoreCondReq accesses(hits+misses) 65411201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 145956149 # number of demand (read+write) accesses 65511201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 145956149 # number of demand (read+write) accesses 65611201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 146788477 # number of overall (read+write) accesses 65711201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 146788477 # number of overall (read+write) accesses 65811201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041058 # miss rate for ReadReq accesses 65911201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.041058 # miss rate for ReadReq accesses 66011201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031980 # miss rate for WriteReq accesses 66111201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.031980 # miss rate for WriteReq accesses 66211201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.700962 # miss rate for SoftPFReq accesses 66311201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.700962 # miss rate for SoftPFReq accesses 66411201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.843061 # miss rate for WriteLineReq accesses 66511201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::total 0.843061 # miss rate for WriteLineReq accesses 66611201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.081847 # miss rate for LoadLockedReq accesses 66711201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.081847 # miss rate for LoadLockedReq accesses 66811201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097164 # miss rate for StoreCondReq accesses 66911201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.097164 # miss rate for StoreCondReq accesses 67011201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.036833 # miss rate for demand accesses 67111201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.036833 # miss rate for demand accesses 67211201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.040599 # miss rate for overall accesses 67311201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.040599 # miss rate for overall accesses 67411201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15930.558191 # average ReadReq miss latency 67511201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 15930.558191 # average ReadReq miss latency 67611201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25353.314020 # average WriteReq miss latency 67711201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 25353.314020 # average WriteReq miss latency 67811201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 92147.406822 # average WriteLineReq miss latency 67911201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::total 92147.406822 # average WriteLineReq miss latency 68011201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14978.349386 # average LoadLockedReq miss latency 68111201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14978.349386 # average LoadLockedReq miss latency 68211201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28050.538170 # average StoreCondReq miss latency 68311201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28050.538170 # average StoreCondReq miss latency 68410636Snilay@cs.wisc.edusystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 68510585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 68611201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19737.359784 # average overall miss latency 68711201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 19737.359784 # average overall miss latency 68811201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17805.090607 # average overall miss latency 68911201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 17805.090607 # average overall miss latency 69010585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 69110585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 69210585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 69310585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 69410585Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 69510585Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 69610585Sandreas.hansson@arm.comsystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 69710585Sandreas.hansson@arm.comsystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 69811201Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 5190079 # number of writebacks 69911201Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 5190079 # number of writebacks 70011201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 389569 # number of ReadReq MSHR hits 70111201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 389569 # number of ReadReq MSHR hits 70211201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 893829 # number of WriteReq MSHR hits 70311201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 893829 # number of WriteReq MSHR hits 70411201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 64 # number of WriteLineReq MSHR hits 70511201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_hits::total 64 # number of WriteLineReq MSHR hits 70611201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 40085 # number of LoadLockedReq MSHR hits 70711201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 40085 # number of LoadLockedReq MSHR hits 70811201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 63 # number of StoreCondReq MSHR hits 70911201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_hits::total 63 # number of StoreCondReq MSHR hits 71011201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::cpu0.data 1283398 # number of demand (read+write) MSHR hits 71111201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::total 1283398 # number of demand (read+write) MSHR hits 71211201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::cpu0.data 1283398 # number of overall MSHR hits 71311201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::total 1283398 # number of overall MSHR hits 71411201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2814567 # number of ReadReq MSHR misses 71511201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 2814567 # number of ReadReq MSHR misses 71611201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1278110 # number of WriteReq MSHR misses 71711201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 1278110 # number of WriteReq MSHR misses 71811201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 581694 # number of SoftPFReq MSHR misses 71911201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::total 581694 # number of SoftPFReq MSHR misses 72011201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 728810 # number of WriteLineReq MSHR misses 72111201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::total 728810 # number of WriteLineReq MSHR misses 72211201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 110465 # number of LoadLockedReq MSHR misses 72311201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 110465 # number of LoadLockedReq MSHR misses 72411201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 178505 # number of StoreCondReq MSHR misses 72511201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 178505 # number of StoreCondReq MSHR misses 72611201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.data 4092677 # number of demand (read+write) MSHR misses 72711201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 4092677 # number of demand (read+write) MSHR misses 72811201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.data 4674371 # number of overall MSHR misses 72911201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 4674371 # number of overall MSHR misses 73011201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16748 # number of ReadReq MSHR uncacheable 73111201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::total 16748 # number of ReadReq MSHR uncacheable 73211201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 18251 # number of WriteReq MSHR uncacheable 73311201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::total 18251 # number of WriteReq MSHR uncacheable 73411201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34999 # number of overall MSHR uncacheable misses 73511201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::total 34999 # number of overall MSHR uncacheable misses 73611201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 40095557000 # number of ReadReq MSHR miss cycles 73711201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 40095557000 # number of ReadReq MSHR miss cycles 73811201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 32063318500 # number of WriteReq MSHR miss cycles 73911201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 32063318500 # number of WriteReq MSHR miss cycles 74011201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14032843000 # number of SoftPFReq MSHR miss cycles 74111201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14032843000 # number of SoftPFReq MSHR miss cycles 74211201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 66427837000 # number of WriteLineReq MSHR miss cycles 74311201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 66427837000 # number of WriteLineReq MSHR miss cycles 74411201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1488538500 # number of LoadLockedReq MSHR miss cycles 74511201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1488538500 # number of LoadLockedReq MSHR miss cycles 74611201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4826102000 # number of StoreCondReq MSHR miss cycles 74711201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4826102000 # number of StoreCondReq MSHR miss cycles 74811201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4518500 # number of StoreCondFailReq MSHR miss cycles 74911201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4518500 # number of StoreCondFailReq MSHR miss cycles 75011201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 72158875500 # number of demand (read+write) MSHR miss cycles 75111201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 72158875500 # number of demand (read+write) MSHR miss cycles 75211201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 86191718500 # number of overall MSHR miss cycles 75311201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 86191718500 # number of overall MSHR miss cycles 75411201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3021431000 # number of ReadReq MSHR uncacheable cycles 75511201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3021431000 # number of ReadReq MSHR uncacheable cycles 75611201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3257996500 # number of WriteReq MSHR uncacheable cycles 75711201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3257996500 # number of WriteReq MSHR uncacheable cycles 75811201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6279427500 # number of overall MSHR uncacheable cycles 75911201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 6279427500 # number of overall MSHR uncacheable cycles 76011201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036066 # mshr miss rate for ReadReq accesses 76111201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036066 # mshr miss rate for ReadReq accesses 76211201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018819 # mshr miss rate for WriteReq accesses 76311201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018819 # mshr miss rate for WriteReq accesses 76411201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.698876 # mshr miss rate for SoftPFReq accesses 76511201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.698876 # mshr miss rate for SoftPFReq accesses 76611201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.842987 # mshr miss rate for WriteLineReq accesses 76711201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.842987 # mshr miss rate for WriteLineReq accesses 76811201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060055 # mshr miss rate for LoadLockedReq accesses 76911201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060055 # mshr miss rate for LoadLockedReq accesses 77011201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097129 # mshr miss rate for StoreCondReq accesses 77111201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097129 # mshr miss rate for StoreCondReq accesses 77211201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028040 # mshr miss rate for demand accesses 77311201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.028040 # mshr miss rate for demand accesses 77411201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031844 # mshr miss rate for overall accesses 77511201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.031844 # mshr miss rate for overall accesses 77611201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14245.728384 # average ReadReq mshr miss latency 77711201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14245.728384 # average ReadReq mshr miss latency 77811201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25086.509377 # average WriteReq mshr miss latency 77911201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25086.509377 # average WriteReq mshr miss latency 78011201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24124.097893 # average SoftPFReq mshr miss latency 78111201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24124.097893 # average SoftPFReq mshr miss latency 78211201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 91145.616827 # average WriteLineReq mshr miss latency 78311201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 91145.616827 # average WriteLineReq mshr miss latency 78411201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13475.204816 # average LoadLockedReq mshr miss latency 78511201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13475.204816 # average LoadLockedReq mshr miss latency 78611201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27036.228677 # average StoreCondReq mshr miss latency 78711201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27036.228677 # average StoreCondReq mshr miss latency 78810636Snilay@cs.wisc.edusystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 78910585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 79011201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17631.216805 # average overall mshr miss latency 79111201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 17631.216805 # average overall mshr miss latency 79211201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18439.212142 # average overall mshr miss latency 79311201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 18439.212142 # average overall mshr miss latency 79411201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180405.481251 # average ReadReq mshr uncacheable latency 79511201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 180405.481251 # average ReadReq mshr uncacheable latency 79611201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 178510.574763 # average WriteReq mshr uncacheable latency 79711201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 178510.574763 # average WriteReq mshr uncacheable latency 79811201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 179417.340495 # average overall mshr uncacheable latency 79911201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 179417.340495 # average overall mshr uncacheable latency 80010585Sandreas.hansson@arm.comsystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 80111201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 8911456 # number of replacements 80211201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.890744 # Cycle average of tags in use 80311201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 215729294 # Total number of references to valid blocks. 80411201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 8911968 # Sample count of references to valid blocks. 80511201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 24.206695 # Average number of references to valid blocks. 80611201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 40343615000 # Cycle when the warmup percentage was hit. 80711201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.890744 # Average occupied blocks per requestor 80811201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999787 # Average percentage of cache occupancy 80911201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999787 # Average percentage of cache occupancy 81010585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 81111201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id 81211201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 330 # Occupied blocks per task id 81311201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id 81410585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 81511201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 458194521 # Number of tag accesses 81611201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 458194521 # Number of data accesses 81711201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 215729294 # number of ReadReq hits 81811201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 215729294 # number of ReadReq hits 81911201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 215729294 # number of demand (read+write) hits 82011201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 215729294 # number of demand (read+write) hits 82111201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 215729294 # number of overall hits 82211201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 215729294 # number of overall hits 82311201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 8911978 # number of ReadReq misses 82411201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 8911978 # number of ReadReq misses 82511201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 8911978 # number of demand (read+write) misses 82611201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 8911978 # number of demand (read+write) misses 82711201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 8911978 # number of overall misses 82811201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 8911978 # number of overall misses 82911201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 92482342000 # number of ReadReq miss cycles 83011201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 92482342000 # number of ReadReq miss cycles 83111201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 92482342000 # number of demand (read+write) miss cycles 83211201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::total 92482342000 # number of demand (read+write) miss cycles 83311201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 92482342000 # number of overall miss cycles 83411201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::total 92482342000 # number of overall miss cycles 83511201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 224641272 # number of ReadReq accesses(hits+misses) 83611201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 224641272 # number of ReadReq accesses(hits+misses) 83711201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 224641272 # number of demand (read+write) accesses 83811201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 224641272 # number of demand (read+write) accesses 83911201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 224641272 # number of overall (read+write) accesses 84011201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 224641272 # number of overall (read+write) accesses 84111201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039672 # miss rate for ReadReq accesses 84211201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.039672 # miss rate for ReadReq accesses 84311201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.039672 # miss rate for demand accesses 84411201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.039672 # miss rate for demand accesses 84511201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.039672 # miss rate for overall accesses 84611201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.039672 # miss rate for overall accesses 84711201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10377.308158 # average ReadReq miss latency 84811201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 10377.308158 # average ReadReq miss latency 84911201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10377.308158 # average overall miss latency 85011201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 10377.308158 # average overall miss latency 85111201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10377.308158 # average overall miss latency 85211201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 10377.308158 # average overall miss latency 85310585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 85410585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 85510585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 85610585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 85710585Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 85810585Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 85910585Sandreas.hansson@arm.comsystem.cpu0.icache.fast_writes 0 # number of fast writes performed 86010585Sandreas.hansson@arm.comsystem.cpu0.icache.cache_copies 0 # number of cache copies performed 86111201Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::writebacks 8911456 # number of writebacks 86211201Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::total 8911456 # number of writebacks 86311201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8911978 # number of ReadReq MSHR misses 86411201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 8911978 # number of ReadReq MSHR misses 86511201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 8911978 # number of demand (read+write) MSHR misses 86611201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::total 8911978 # number of demand (read+write) MSHR misses 86711201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 8911978 # number of overall MSHR misses 86811201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::total 8911978 # number of overall MSHR misses 86911138Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable 87011138Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable 87111138Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses 87211138Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses 87311201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 88026353500 # number of ReadReq MSHR miss cycles 87411201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 88026353500 # number of ReadReq MSHR miss cycles 87511201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 88026353500 # number of demand (read+write) MSHR miss cycles 87611201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 88026353500 # number of demand (read+write) MSHR miss cycles 87711201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 88026353500 # number of overall MSHR miss cycles 87811201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 88026353500 # number of overall MSHR miss cycles 87911201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7414627000 # number of ReadReq MSHR uncacheable cycles 88011201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7414627000 # number of ReadReq MSHR uncacheable cycles 88111201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7414627000 # number of overall MSHR uncacheable cycles 88211201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::total 7414627000 # number of overall MSHR uncacheable cycles 88311201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039672 # mshr miss rate for ReadReq accesses 88411201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039672 # mshr miss rate for ReadReq accesses 88511201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039672 # mshr miss rate for demand accesses 88611201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.039672 # mshr miss rate for demand accesses 88711201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039672 # mshr miss rate for overall accesses 88811201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.039672 # mshr miss rate for overall accesses 88911201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9877.308214 # average ReadReq mshr miss latency 89011201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9877.308214 # average ReadReq mshr miss latency 89111201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9877.308214 # average overall mshr miss latency 89211201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 9877.308214 # average overall mshr miss latency 89311201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9877.308214 # average overall mshr miss latency 89411201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 9877.308214 # average overall mshr miss latency 89511201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average ReadReq mshr uncacheable latency 89611201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141746.678392 # average ReadReq mshr uncacheable latency 89711201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average overall mshr uncacheable latency 89811201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141746.678392 # average overall mshr uncacheable latency 89910585Sandreas.hansson@arm.comsystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 90011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.num_hwpf_issued 7009428 # number of hwpf issued 90111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfIdentified 7009488 # number of prefetch candidates identified 90211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfBufferHit 54 # number of redundant prefetches already in prefetch queue 90310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 90410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 90511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfSpanPage 921168 # number of prefetches not generated due to page crossing 90611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.replacements 2475518 # number of replacements 90711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tagsinuse 16200.233462 # Cycle average of tags in use 90811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.total_refs 22065601 # Total number of references to valid blocks. 90911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.sampled_refs 2491662 # Sample count of references to valid blocks. 91011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.avg_refs 8.855776 # Average number of references to valid blocks. 91111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 9049945000 # Cycle when the warmup percentage was hit. 91211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 15248.600129 # Average occupied blocks per requestor 91311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 44.173698 # Average occupied blocks per requestor 91411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 44.219033 # Average occupied blocks per requestor 91511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 863.240603 # Average occupied blocks per requestor 91611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.930701 # Average percentage of cache occupancy 91711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002696 # Average percentage of cache occupancy 91811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.002699 # Average percentage of cache occupancy 91911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.052688 # Average percentage of cache occupancy 92011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.988784 # Average percentage of cache occupancy 92111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1022 1264 # Occupied blocks per task id 92211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 48 # Occupied blocks per task id 92311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 14832 # Occupied blocks per task id 92411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id 92511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::2 796 # Occupied blocks per task id 92611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::3 176 # Occupied blocks per task id 92711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::4 279 # Occupied blocks per task id 92811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id 92911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 32 # Occupied blocks per task id 93011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id 93111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id 93211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1045 # Occupied blocks per task id 93311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5479 # Occupied blocks per task id 93411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6042 # Occupied blocks per task id 93511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2161 # Occupied blocks per task id 93611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1022 0.077148 # Percentage of cache occupancy per task id 93711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.002930 # Percentage of cache occupancy per task id 93811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.905273 # Percentage of cache occupancy per task id 93911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tag_accesses 474836128 # Number of tag accesses 94011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.data_accesses 474836128 # Number of data accesses 94111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 472021 # number of ReadReq hits 94211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 147981 # number of ReadReq hits 94311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 620002 # number of ReadReq hits 94411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::writebacks 3408595 # number of WritebackDirty hits 94511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::total 3408595 # number of WritebackDirty hits 94611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_hits::writebacks 10690717 # number of WritebackClean hits 94711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_hits::total 10690717 # number of WritebackClean hits 94811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::cpu0.data 115 # number of UpgradeReq hits 94911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::total 115 # number of UpgradeReq hits 95011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 789207 # number of ReadExReq hits 95111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 789207 # number of ReadExReq hits 95211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 8250320 # number of ReadCleanReq hits 95311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 8250320 # number of ReadCleanReq hits 95411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2605662 # number of ReadSharedReq hits 95511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 2605662 # number of ReadSharedReq hits 95611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::cpu0.data 165539 # number of InvalidateReq hits 95711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::total 165539 # number of InvalidateReq hits 95811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 472021 # number of demand (read+write) hits 95911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 147981 # number of demand (read+write) hits 96011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 8250320 # number of demand (read+write) hits 96111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 3394869 # number of demand (read+write) hits 96211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::total 12265191 # number of demand (read+write) hits 96311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 472021 # number of overall hits 96411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 147981 # number of overall hits 96511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 8250320 # number of overall hits 96611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 3394869 # number of overall hits 96711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::total 12265191 # number of overall hits 96811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10450 # number of ReadReq misses 96911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7208 # number of ReadReq misses 97011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 17658 # number of ReadReq misses 97111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses 97211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses 97311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 242851 # number of UpgradeReq misses 97411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 242851 # number of UpgradeReq misses 97511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 178501 # number of SCUpgradeReq misses 97611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 178501 # number of SCUpgradeReq misses 97711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses 97811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses 97911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 254335 # number of ReadExReq misses 98011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 254335 # number of ReadExReq misses 98111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 661657 # number of ReadCleanReq misses 98211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 661657 # number of ReadCleanReq misses 98311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 900762 # number of ReadSharedReq misses 98411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 900762 # number of ReadSharedReq misses 98511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::cpu0.data 561341 # number of InvalidateReq misses 98611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::total 561341 # number of InvalidateReq misses 98711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10450 # number of demand (read+write) misses 98811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 7208 # number of demand (read+write) misses 98911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 661657 # number of demand (read+write) misses 99011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 1155097 # number of demand (read+write) misses 99111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::total 1834412 # number of demand (read+write) misses 99211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10450 # number of overall misses 99311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 7208 # number of overall misses 99411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 661657 # number of overall misses 99511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 1155097 # number of overall misses 99611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::total 1834412 # number of overall misses 99711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 323189500 # number of ReadReq miss cycles 99811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 243712500 # number of ReadReq miss cycles 99911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::total 566902000 # number of ReadReq miss cycles 100011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3278340000 # number of UpgradeReq miss cycles 100111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::total 3278340000 # number of UpgradeReq miss cycles 100211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1776981500 # number of SCUpgradeReq miss cycles 100311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1776981500 # number of SCUpgradeReq miss cycles 100411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 4439499 # number of SCUpgradeFailReq miss cycles 100511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 4439499 # number of SCUpgradeFailReq miss cycles 100611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 15942119997 # number of ReadExReq miss cycles 100711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::total 15942119997 # number of ReadExReq miss cycles 100811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 24805875000 # number of ReadCleanReq miss cycles 100911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::total 24805875000 # number of ReadCleanReq miss cycles 101011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 33147375490 # number of ReadSharedReq miss cycles 101111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::total 33147375490 # number of ReadSharedReq miss cycles 101211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 64101878000 # number of InvalidateReq miss cycles 101311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::total 64101878000 # number of InvalidateReq miss cycles 101411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 323189500 # number of demand (read+write) miss cycles 101511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 243712500 # number of demand (read+write) miss cycles 101611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.inst 24805875000 # number of demand (read+write) miss cycles 101711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.data 49089495487 # number of demand (read+write) miss cycles 101811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::total 74462272487 # number of demand (read+write) miss cycles 101911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 323189500 # number of overall miss cycles 102011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 243712500 # number of overall miss cycles 102111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.inst 24805875000 # number of overall miss cycles 102211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.data 49089495487 # number of overall miss cycles 102311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::total 74462272487 # number of overall miss cycles 102411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 482471 # number of ReadReq accesses(hits+misses) 102511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 155189 # number of ReadReq accesses(hits+misses) 102611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 637660 # number of ReadReq accesses(hits+misses) 102711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::writebacks 3408595 # number of WritebackDirty accesses(hits+misses) 102811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::total 3408595 # number of WritebackDirty accesses(hits+misses) 102911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::writebacks 10690718 # number of WritebackClean accesses(hits+misses) 103011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::total 10690718 # number of WritebackClean accesses(hits+misses) 103111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 242966 # number of UpgradeReq accesses(hits+misses) 103211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 242966 # number of UpgradeReq accesses(hits+misses) 103311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 178501 # number of SCUpgradeReq accesses(hits+misses) 103411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 178501 # number of SCUpgradeReq accesses(hits+misses) 103511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 4 # number of SCUpgradeFailReq accesses(hits+misses) 103611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) 103711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1043542 # number of ReadExReq accesses(hits+misses) 103811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1043542 # number of ReadExReq accesses(hits+misses) 103911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 8911977 # number of ReadCleanReq accesses(hits+misses) 104011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 8911977 # number of ReadCleanReq accesses(hits+misses) 104111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3506424 # number of ReadSharedReq accesses(hits+misses) 104211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 3506424 # number of ReadSharedReq accesses(hits+misses) 104311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 726880 # number of InvalidateReq accesses(hits+misses) 104411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::total 726880 # number of InvalidateReq accesses(hits+misses) 104511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 482471 # number of demand (read+write) accesses 104611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 155189 # number of demand (read+write) accesses 104711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 8911977 # number of demand (read+write) accesses 104811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 4549966 # number of demand (read+write) accesses 104911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::total 14099603 # number of demand (read+write) accesses 105011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 482471 # number of overall (read+write) accesses 105111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 155189 # number of overall (read+write) accesses 105211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 8911977 # number of overall (read+write) accesses 105311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 4549966 # number of overall (read+write) accesses 105411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::total 14099603 # number of overall (read+write) accesses 105511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.021659 # miss rate for ReadReq accesses 105611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.046447 # miss rate for ReadReq accesses 105711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.027692 # miss rate for ReadReq accesses 105811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses 105911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses 106011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999527 # miss rate for UpgradeReq accesses 106111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999527 # miss rate for UpgradeReq accesses 106211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 106311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 106410636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 106510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 106611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.243723 # miss rate for ReadExReq accesses 106711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.243723 # miss rate for ReadExReq accesses 106811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.074244 # miss rate for ReadCleanReq accesses 106911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.074244 # miss rate for ReadCleanReq accesses 107011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.256889 # miss rate for ReadSharedReq accesses 107111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.256889 # miss rate for ReadSharedReq accesses 107211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.772261 # miss rate for InvalidateReq accesses 107311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::total 0.772261 # miss rate for InvalidateReq accesses 107411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.021659 # miss rate for demand accesses 107511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.046447 # miss rate for demand accesses 107611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.074244 # miss rate for demand accesses 107711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.253869 # miss rate for demand accesses 107811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.130104 # miss rate for demand accesses 107911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.021659 # miss rate for overall accesses 108011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.046447 # miss rate for overall accesses 108111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.074244 # miss rate for overall accesses 108211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.253869 # miss rate for overall accesses 108311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.130104 # miss rate for overall accesses 108411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 30927.224880 # average ReadReq miss latency 108511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 33811.390122 # average ReadReq miss latency 108611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::total 32104.541851 # average ReadReq miss latency 108711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13499.388514 # average UpgradeReq miss latency 108811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13499.388514 # average UpgradeReq miss latency 108911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 9955.022661 # average SCUpgradeReq miss latency 109011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 9955.022661 # average SCUpgradeReq miss latency 109111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 1109874.750000 # average SCUpgradeFailReq miss latency 109211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1109874.750000 # average SCUpgradeFailReq miss latency 109311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 62681.581367 # average ReadExReq miss latency 109411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::total 62681.581367 # average ReadExReq miss latency 109511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 37490.535126 # average ReadCleanReq miss latency 109611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 37490.535126 # average ReadCleanReq miss latency 109711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 36799.260504 # average ReadSharedReq miss latency 109811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 36799.260504 # average ReadSharedReq miss latency 109911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 114194.184996 # average InvalidateReq miss latency 110011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 114194.184996 # average InvalidateReq miss latency 110111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 30927.224880 # average overall miss latency 110211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 33811.390122 # average overall miss latency 110311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37490.535126 # average overall miss latency 110411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42498.158585 # average overall miss latency 110511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::total 40591.902194 # average overall miss latency 110611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 30927.224880 # average overall miss latency 110711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 33811.390122 # average overall miss latency 110811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37490.535126 # average overall miss latency 110911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42498.158585 # average overall miss latency 111011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::total 40591.902194 # average overall miss latency 111111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 111210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 111311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 111410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 111511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 111610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 111710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.fast_writes 0 # number of fast writes performed 111810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.cache_copies 0 # number of cache copies performed 111911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::writebacks 1435569 # number of writebacks 112011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::total 1435569 # number of writebacks 112111167Sjthestness@gmail.comsystem.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 2 # number of ReadReq MSHR hits 112211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits 112311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 4123 # number of ReadExReq MSHR hits 112411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::total 4123 # number of ReadExReq MSHR hits 112511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 7 # number of ReadCleanReq MSHR hits 112611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_hits::total 7 # number of ReadCleanReq MSHR hits 112711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 932 # number of ReadSharedReq MSHR hits 112811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::total 932 # number of ReadSharedReq MSHR hits 112911167Sjthestness@gmail.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 2 # number of demand (read+write) MSHR hits 113011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits 113111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.data 5055 # number of demand (read+write) MSHR hits 113211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::total 5064 # number of demand (read+write) MSHR hits 113311167Sjthestness@gmail.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 2 # number of overall MSHR hits 113411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits 113511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.data 5055 # number of overall MSHR hits 113611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::total 5064 # number of overall MSHR hits 113711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 10450 # number of ReadReq MSHR misses 113811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 7206 # number of ReadReq MSHR misses 113911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::total 17656 # number of ReadReq MSHR misses 114011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses 114111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses 114211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 688849 # number of HardPFReq MSHR misses 114311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::total 688849 # number of HardPFReq MSHR misses 114411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 242851 # number of UpgradeReq MSHR misses 114511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::total 242851 # number of UpgradeReq MSHR misses 114611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 178501 # number of SCUpgradeReq MSHR misses 114711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 178501 # number of SCUpgradeReq MSHR misses 114811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 4 # number of SCUpgradeFailReq MSHR misses 114911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses 115011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 250212 # number of ReadExReq MSHR misses 115111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::total 250212 # number of ReadExReq MSHR misses 115211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 661650 # number of ReadCleanReq MSHR misses 115311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::total 661650 # number of ReadCleanReq MSHR misses 115411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 899830 # number of ReadSharedReq MSHR misses 115511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::total 899830 # number of ReadSharedReq MSHR misses 115611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 561341 # number of InvalidateReq MSHR misses 115711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::total 561341 # number of InvalidateReq MSHR misses 115811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 10450 # number of demand (read+write) MSHR misses 115911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 7206 # number of demand (read+write) MSHR misses 116011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.inst 661650 # number of demand (read+write) MSHR misses 116111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.data 1150042 # number of demand (read+write) MSHR misses 116211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::total 1829348 # number of demand (read+write) MSHR misses 116311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 10450 # number of overall MSHR misses 116411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 7206 # number of overall MSHR misses 116511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.inst 661650 # number of overall MSHR misses 116611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.data 1150042 # number of overall MSHR misses 116711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 688849 # number of overall MSHR misses 116811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::total 2518197 # number of overall MSHR misses 116911138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable 117011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 16748 # number of ReadReq MSHR uncacheable 117111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::total 69057 # number of ReadReq MSHR uncacheable 117211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 18251 # number of WriteReq MSHR uncacheable 117311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::total 18251 # number of WriteReq MSHR uncacheable 117411138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses 117511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 34999 # number of overall MSHR uncacheable misses 117611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::total 87308 # number of overall MSHR uncacheable misses 117711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 260489500 # number of ReadReq MSHR miss cycles 117811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 200447500 # number of ReadReq MSHR miss cycles 117911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::total 460937000 # number of ReadReq MSHR miss cycles 118011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 28313104052 # number of HardPFReq MSHR miss cycles 118111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 28313104052 # number of HardPFReq MSHR miss cycles 118211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7480349995 # number of UpgradeReq MSHR miss cycles 118311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7480349995 # number of UpgradeReq MSHR miss cycles 118411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3483043000 # number of SCUpgradeReq MSHR miss cycles 118511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3483043000 # number of SCUpgradeReq MSHR miss cycles 118611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4127499 # number of SCUpgradeFailReq MSHR miss cycles 118711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4127499 # number of SCUpgradeFailReq MSHR miss cycles 118811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 13883735997 # number of ReadExReq MSHR miss cycles 118911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 13883735997 # number of ReadExReq MSHR miss cycles 119011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 20835719500 # number of ReadCleanReq MSHR miss cycles 119111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 20835719500 # number of ReadCleanReq MSHR miss cycles 119211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 27673983990 # number of ReadSharedReq MSHR miss cycles 119311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 27673983990 # number of ReadSharedReq MSHR miss cycles 119411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 60733832000 # number of InvalidateReq MSHR miss cycles 119511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 60733832000 # number of InvalidateReq MSHR miss cycles 119611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 260489500 # number of demand (read+write) MSHR miss cycles 119711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 200447500 # number of demand (read+write) MSHR miss cycles 119811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 20835719500 # number of demand (read+write) MSHR miss cycles 119911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 41557719987 # number of demand (read+write) MSHR miss cycles 120011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::total 62854376487 # number of demand (read+write) MSHR miss cycles 120111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 260489500 # number of overall MSHR miss cycles 120211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 200447500 # number of overall MSHR miss cycles 120311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 20835719500 # number of overall MSHR miss cycles 120411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 41557719987 # number of overall MSHR miss cycles 120511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 28313104052 # number of overall MSHR miss cycles 120611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::total 91167480539 # number of overall MSHR miss cycles 120711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of ReadReq MSHR uncacheable cycles 120811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2887260500 # number of ReadReq MSHR uncacheable cycles 120911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9883415500 # number of ReadReq MSHR uncacheable cycles 121011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3121073500 # number of WriteReq MSHR uncacheable cycles 121111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3121073500 # number of WriteReq MSHR uncacheable cycles 121211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of overall MSHR uncacheable cycles 121311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6008334000 # number of overall MSHR uncacheable cycles 121411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::total 13004489000 # number of overall MSHR uncacheable cycles 121511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021659 # mshr miss rate for ReadReq accesses 121611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.046434 # mshr miss rate for ReadReq accesses 121711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.027689 # mshr miss rate for ReadReq accesses 121811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses 121911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses 122010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 122110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 122211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999527 # mshr miss rate for UpgradeReq accesses 122311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999527 # mshr miss rate for UpgradeReq accesses 122411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 122511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 122610636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 122710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 122811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.239772 # mshr miss rate for ReadExReq accesses 122911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.239772 # mshr miss rate for ReadExReq accesses 123011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.074243 # mshr miss rate for ReadCleanReq accesses 123111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.074243 # mshr miss rate for ReadCleanReq accesses 123211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.256623 # mshr miss rate for ReadSharedReq accesses 123311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.256623 # mshr miss rate for ReadSharedReq accesses 123411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.772261 # mshr miss rate for InvalidateReq accesses 123511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.772261 # mshr miss rate for InvalidateReq accesses 123611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021659 # mshr miss rate for demand accesses 123711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.046434 # mshr miss rate for demand accesses 123811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.074243 # mshr miss rate for demand accesses 123911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.252758 # mshr miss rate for demand accesses 124011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::total 0.129745 # mshr miss rate for demand accesses 124111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021659 # mshr miss rate for overall accesses 124211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.046434 # mshr miss rate for overall accesses 124311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.074243 # mshr miss rate for overall accesses 124411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.252758 # mshr miss rate for overall accesses 124510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 124611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::total 0.178601 # mshr miss rate for overall accesses 124711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24927.224880 # average ReadReq mshr miss latency 124811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 27816.749931 # average ReadReq mshr miss latency 124911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26106.536022 # average ReadReq mshr miss latency 125011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41102.047113 # average HardPFReq mshr miss latency 125111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41102.047113 # average HardPFReq mshr miss latency 125211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 30802.220271 # average UpgradeReq mshr miss latency 125311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30802.220271 # average UpgradeReq mshr miss latency 125411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19512.736623 # average SCUpgradeReq mshr miss latency 125511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19512.736623 # average SCUpgradeReq mshr miss latency 125611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 1031874.750000 # average SCUpgradeFailReq mshr miss latency 125711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1031874.750000 # average SCUpgradeFailReq mshr miss latency 125811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 55487.890257 # average ReadExReq mshr miss latency 125911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 55487.890257 # average ReadExReq mshr miss latency 126011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31490.545606 # average ReadCleanReq mshr miss latency 126111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31490.545606 # average ReadCleanReq mshr miss latency 126211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 30754.680317 # average ReadSharedReq mshr miss latency 126311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30754.680317 # average ReadSharedReq mshr miss latency 126411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 108194.184996 # average InvalidateReq mshr miss latency 126511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 108194.184996 # average InvalidateReq mshr miss latency 126611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24927.224880 # average overall mshr miss latency 126711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 27816.749931 # average overall mshr miss latency 126811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31490.545606 # average overall mshr miss latency 126911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36135.828071 # average overall mshr miss latency 127011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34358.895348 # average overall mshr miss latency 127111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24927.224880 # average overall mshr miss latency 127211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 27816.749931 # average overall mshr miss latency 127311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31490.545606 # average overall mshr miss latency 127411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36135.828071 # average overall mshr miss latency 127511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41102.047113 # average overall mshr miss latency 127611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36203.474366 # average overall mshr miss latency 127711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average ReadReq mshr uncacheable latency 127811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172394.345594 # average ReadReq mshr uncacheable latency 127911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 143119.676499 # average ReadReq mshr uncacheable latency 128011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171008.355707 # average WriteReq mshr uncacheable latency 128111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 171008.355707 # average WriteReq mshr uncacheable latency 128211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average overall mshr uncacheable latency 128311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 171671.590617 # average overall mshr uncacheable latency 128411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 148949.569341 # average overall mshr uncacheable latency 128510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 128611201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_requests 29004574 # Total number of requests made to the snoop filter. 128711201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_requests 14815953 # Number of requests hitting in the snoop filter with a single holder of the requested data. 128811201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2223 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 128911201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_snoops 1990994 # Total number of snoops made to the snoop filter. 129011201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1990568 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 129111201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 426 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 129211201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 781840 # Transaction distribution 129311201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 13286786 # Transaction distribution 129411201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 18251 # Transaction distribution 129511201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 18251 # Transaction distribution 129611201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackDirty 4847792 # Transaction distribution 129711201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackClean 10690718 # Transaction distribution 129811201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::CleanEvict 2645908 # Transaction distribution 129911201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::HardPFReq 891756 # Transaction distribution 130011201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 444613 # Transaction distribution 130111201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 320296 # Transaction distribution 130211201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 480335 # Transaction distribution 130311201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 85 # Transaction distribution 130411201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution 130511201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1119465 # Transaction distribution 130611201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1052013 # Transaction distribution 130711201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 8911978 # Transaction distribution 130811201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 4503059 # Transaction distribution 130911201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateReq 735449 # Transaction distribution 131011201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateResp 726880 # Transaction distribution 131111201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 26838850 # Packet count per connected master and slave (bytes) 131211201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16809682 # Packet count per connected master and slave (bytes) 131311201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 328338 # Packet count per connected master and slave (bytes) 131411201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1022103 # Packet count per connected master and slave (bytes) 131511201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count::total 44998973 # Packet count per connected master and slave (bytes) 131611201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1143972032 # Cumulative packet size per connected master and slave (bytes) 131711201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 629474552 # Cumulative packet size per connected master and slave (bytes) 131811201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1241512 # Cumulative packet size per connected master and slave (bytes) 131911201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3859768 # Cumulative packet size per connected master and slave (bytes) 132011201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size::total 1778547864 # Cumulative packet size per connected master and slave (bytes) 132111201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoops 6630650 # Total snoops (count) 132211201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 21811897 # Request fanout histogram 132311201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 0.104823 # Request fanout histogram 132411201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.306390 # Request fanout histogram 132510585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 132611201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 19525925 89.52% 89.52% # Request fanout histogram 132711201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 2285546 10.48% 100.00% # Request fanout histogram 132811201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 426 0.00% 100.00% # Request fanout histogram 132910585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 133011138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 133110827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 133211201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 21811897 # Request fanout histogram 133311201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.reqLayer0.occupancy 28866629481 # Layer occupancy (ticks) 133411201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 133511201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopLayer0.occupancy 172367004 # Layer occupancy (ticks) 133610585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 133711201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer0.occupancy 13449935466 # Layer occupancy (ticks) 133810585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 133911201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer1.occupancy 7428549534 # Layer occupancy (ticks) 134010585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 134111201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer2.occupancy 173196405 # Layer occupancy (ticks) 134210585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 134311201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer3.occupancy 539756748 # Layer occupancy (ticks) 134410585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 134511201Sandreas.hansson@arm.comsystem.cpu1.branchPred.lookups 127068265 # Number of BP lookups 134611201Sandreas.hansson@arm.comsystem.cpu1.branchPred.condPredicted 89752795 # Number of conditional branches predicted 134711201Sandreas.hansson@arm.comsystem.cpu1.branchPred.condIncorrect 6099791 # Number of conditional branches incorrect 134811201Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBLookups 94409743 # Number of BTB lookups 134911201Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBHits 68319168 # Number of BTB hits 135010585Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 135111201Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBHitPct 72.364531 # BTB Hit Percentage 135211201Sandreas.hansson@arm.comsystem.cpu1.branchPred.usedRAS 15069899 # Number of times the RAS was used to get a target. 135311201Sandreas.hansson@arm.comsystem.cpu1.branchPred.RASInCorrect 999135 # Number of incorrect RAS predictions. 135410628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 135510628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 135610628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 135710628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 135810628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 135910628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 136010628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 136110628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 136210585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 136310585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 136410585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 136510585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 136610585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 136710585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 136810585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 136910585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 137010585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 137110585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 137210585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 137310585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 137410585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 137510585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 137610585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 137710585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 137810585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 137910585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 138010585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 138110585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 138210585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 138311201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walks 271482 # Table walker walks requested 138411201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLong 271482 # Table walker walks initiated with long descriptors 138511201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level2 7964 # Level at which table walker walks with long descriptors terminate 138611201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level3 78105 # Level at which table walker walks with long descriptors terminate 138711201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 271482 # Table walker wait (enqueue to first request) latency 138811201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0 271482 100.00% 100.00% # Table walker wait (enqueue to first request) latency 138911201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 271482 # Table walker wait (enqueue to first request) latency 139011201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::samples 86069 # Table walker service (enqueue to completion) latency 139111201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::mean 22755.010515 # Table walker service (enqueue to completion) latency 139211201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::gmean 21243.396519 # Table walker service (enqueue to completion) latency 139311201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::stdev 15660.005020 # Table walker service (enqueue to completion) latency 139411201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::0-65535 85331 99.14% 99.14% # Table walker service (enqueue to completion) latency 139511201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::65536-131071 168 0.20% 99.34% # Table walker service (enqueue to completion) latency 139611201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::131072-196607 495 0.58% 99.91% # Table walker service (enqueue to completion) latency 139711201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::196608-262143 14 0.02% 99.93% # Table walker service (enqueue to completion) latency 139811201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::262144-327679 20 0.02% 99.95% # Table walker service (enqueue to completion) latency 139911201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::327680-393215 15 0.02% 99.97% # Table walker service (enqueue to completion) latency 140011201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::393216-458751 22 0.03% 100.00% # Table walker service (enqueue to completion) latency 140111201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 140211201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 140311201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 140411201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::total 86069 # Table walker service (enqueue to completion) latency 140511201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::samples 527505760 # Table walker pending requests distribution 140611201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::0 527505760 100.00% 100.00% # Table walker pending requests distribution 140711201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::total 527505760 # Table walker pending requests distribution 140811201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 78105 90.75% 90.75% # Table walker page sizes translated 140911201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::2M 7964 9.25% 100.00% # Table walker page sizes translated 141011201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 86069 # Table walker page sizes translated 141111201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 271482 # Table walker requests started/completed, data/inst 141210628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 141311201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 271482 # Table walker requests started/completed, data/inst 141411201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 86069 # Table walker requests started/completed, data/inst 141510628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 141611201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 86069 # Table walker requests started/completed, data/inst 141711201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 357551 # Table walker requests started/completed, data/inst 141810585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_hits 0 # ITB inst hits 141910585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_misses 0 # ITB inst misses 142011201Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 82675138 # DTB read hits 142111201Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 225741 # DTB read misses 142211201Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 73180273 # DTB write hits 142311201Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 45741 # DTB write misses 142410585Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 142510585Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 142611201Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 37374 # Number of times TLB was flushed by MVA & ASID 142711201Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_asid 1001 # Number of times TLB was flushed by ASID 142811201Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_entries 37272 # Number of entries that have been flushed from TLB 142911201Sandreas.hansson@arm.comsystem.cpu1.dtb.align_faults 1666 # Number of TLB faults due to alignment restrictions 143011201Sandreas.hansson@arm.comsystem.cpu1.dtb.prefetch_faults 8268 # Number of TLB faults due to prefetch 143110585Sandreas.hansson@arm.comsystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 143211201Sandreas.hansson@arm.comsystem.cpu1.dtb.perms_faults 11369 # Number of TLB faults due to permissions restrictions 143311201Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 82900879 # DTB read accesses 143411201Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 73226014 # DTB write accesses 143510585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 143611201Sandreas.hansson@arm.comsystem.cpu1.dtb.hits 155855411 # DTB hits 143711201Sandreas.hansson@arm.comsystem.cpu1.dtb.misses 271482 # DTB misses 143811201Sandreas.hansson@arm.comsystem.cpu1.dtb.accesses 156126893 # DTB accesses 143910628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 144010628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 144110628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 144210628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 144310628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 144410628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 144510628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 144610628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 144710585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 144810585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 144910585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 145010585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 145110585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 145210585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 145310585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 145410585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 145510585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 145610585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 145710585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 145810585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 145910585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 146010585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 146110585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 146210585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 146310585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 146410585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 146510585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 146610585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 146710585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 146811201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walks 69604 # Table walker walks requested 146911201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLong 69604 # Table walker walks initiated with long descriptors 147011201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level2 666 # Level at which table walker walks with long descriptors terminate 147111201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level3 61994 # Level at which table walker walks with long descriptors terminate 147211201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 69604 # Table walker wait (enqueue to first request) latency 147311201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::0 69604 100.00% 100.00% # Table walker wait (enqueue to first request) latency 147411201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 69604 # Table walker wait (enqueue to first request) latency 147511201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::samples 62660 # Table walker service (enqueue to completion) latency 147611201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::mean 25321.249601 # Table walker service (enqueue to completion) latency 147711201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::gmean 23483.555874 # Table walker service (enqueue to completion) latency 147811201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::stdev 17582.582178 # Table walker service (enqueue to completion) latency 147911201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::0-65535 61881 98.76% 98.76% # Table walker service (enqueue to completion) latency 148011201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::65536-131071 12 0.02% 98.78% # Table walker service (enqueue to completion) latency 148111201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::131072-196607 712 1.14% 99.91% # Table walker service (enqueue to completion) latency 148211201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::196608-262143 23 0.04% 99.95% # Table walker service (enqueue to completion) latency 148311201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::262144-327679 20 0.03% 99.98% # Table walker service (enqueue to completion) latency 148411201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::327680-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency 148511201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::393216-458751 6 0.01% 100.00% # Table walker service (enqueue to completion) latency 148611167Sjthestness@gmail.comsystem.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 148711201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::total 62660 # Table walker service (enqueue to completion) latency 148811201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::samples 526611260 # Table walker pending requests distribution 148911201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::0 526611260 100.00% 100.00% # Table walker pending requests distribution 149011201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::total 526611260 # Table walker pending requests distribution 149111201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 61994 98.94% 98.94% # Table walker page sizes translated 149211201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::2M 666 1.06% 100.00% # Table walker page sizes translated 149311201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 62660 # Table walker page sizes translated 149410628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 149511201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 69604 # Table walker requests started/completed, data/inst 149611201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 69604 # Table walker requests started/completed, data/inst 149710628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 149811201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 62660 # Table walker requests started/completed, data/inst 149911201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 62660 # Table walker requests started/completed, data/inst 150011201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 132264 # Table walker requests started/completed, data/inst 150111201Sandreas.hansson@arm.comsystem.cpu1.itb.inst_hits 226404999 # ITB inst hits 150211201Sandreas.hansson@arm.comsystem.cpu1.itb.inst_misses 69604 # ITB inst misses 150310585Sandreas.hansson@arm.comsystem.cpu1.itb.read_hits 0 # DTB read hits 150410585Sandreas.hansson@arm.comsystem.cpu1.itb.read_misses 0 # DTB read misses 150510585Sandreas.hansson@arm.comsystem.cpu1.itb.write_hits 0 # DTB write hits 150610585Sandreas.hansson@arm.comsystem.cpu1.itb.write_misses 0 # DTB write misses 150710585Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 150810585Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 150911201Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 37374 # Number of times TLB was flushed by MVA & ASID 151011201Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_asid 1001 # Number of times TLB was flushed by ASID 151111201Sandreas.hansson@arm.comsystem.cpu1.itb.flush_entries 26762 # Number of entries that have been flushed from TLB 151210585Sandreas.hansson@arm.comsystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 151310585Sandreas.hansson@arm.comsystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 151410585Sandreas.hansson@arm.comsystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 151511201Sandreas.hansson@arm.comsystem.cpu1.itb.perms_faults 203402 # Number of TLB faults due to permissions restrictions 151610585Sandreas.hansson@arm.comsystem.cpu1.itb.read_accesses 0 # DTB read accesses 151710585Sandreas.hansson@arm.comsystem.cpu1.itb.write_accesses 0 # DTB write accesses 151811201Sandreas.hansson@arm.comsystem.cpu1.itb.inst_accesses 226474603 # ITB inst accesses 151911201Sandreas.hansson@arm.comsystem.cpu1.itb.hits 226404999 # DTB hits 152011201Sandreas.hansson@arm.comsystem.cpu1.itb.misses 69604 # DTB misses 152111201Sandreas.hansson@arm.comsystem.cpu1.itb.accesses 226474603 # DTB accesses 152211201Sandreas.hansson@arm.comsystem.cpu1.numCycles 896249910 # number of cpu cycles simulated 152310585Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 152410585Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 152511201Sandreas.hansson@arm.comsystem.cpu1.committedInsts 420934522 # Number of instructions committed 152611201Sandreas.hansson@arm.comsystem.cpu1.committedOps 495850522 # Number of ops (including micro ops) committed 152711201Sandreas.hansson@arm.comsystem.cpu1.discardedOps 42911431 # Number of ops (including micro ops) which were discarded before commit 152811201Sandreas.hansson@arm.comsystem.cpu1.numFetchSuspends 4588 # Number of times Execute suspended instruction fetching 152911201Sandreas.hansson@arm.comsystem.cpu1.quiesceCycles 93867828238 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 153011201Sandreas.hansson@arm.comsystem.cpu1.cpi 2.129191 # CPI: cycles per instruction 153111201Sandreas.hansson@arm.comsystem.cpu1.ipc 0.469662 # IPC: instructions per cycle 153210585Sandreas.hansson@arm.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 153311201Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 13511 # number of quiesce instructions executed 153411201Sandreas.hansson@arm.comsystem.cpu1.tickCycles 680922299 # Number of cycles that the object actually ticked 153511201Sandreas.hansson@arm.comsystem.cpu1.idleCycles 215327611 # Total number of cycles that the object has spent stopped 153611201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 4921419 # number of replacements 153711201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 458.899025 # Cycle average of tags in use 153811201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 148299852 # Total number of references to valid blocks. 153911201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 4921931 # Sample count of references to valid blocks. 154011201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 30.130421 # Average number of references to valid blocks. 154111201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 8388824602000 # Cycle when the warmup percentage was hit. 154211201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 458.899025 # Average occupied blocks per requestor 154311201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.896287 # Average percentage of cache occupancy 154411201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.896287 # Average percentage of cache occupancy 154511167Sjthestness@gmail.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 154611201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id 154711201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id 154811201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id 154911167Sjthestness@gmail.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 155011201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 313981831 # Number of tag accesses 155111201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 313981831 # Number of data accesses 155211201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 76035057 # number of ReadReq hits 155311201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 76035057 # number of ReadReq hits 155411201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 68321160 # number of WriteReq hits 155511201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 68321160 # number of WriteReq hits 155611201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 232478 # number of SoftPFReq hits 155711201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 232478 # number of SoftPFReq hits 155811201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::cpu1.data 184182 # number of WriteLineReq hits 155911201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::total 184182 # number of WriteLineReq hits 156011201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1549703 # number of LoadLockedReq hits 156111201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 1549703 # number of LoadLockedReq hits 156211201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 1524262 # number of StoreCondReq hits 156311201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 1524262 # number of StoreCondReq hits 156411201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 144356217 # number of demand (read+write) hits 156511201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 144356217 # number of demand (read+write) hits 156611201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 144588695 # number of overall hits 156711201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 144588695 # number of overall hits 156811201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 3124160 # number of ReadReq misses 156911201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 3124160 # number of ReadReq misses 157011201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 2104338 # number of WriteReq misses 157111201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 2104338 # number of WriteReq misses 157211201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 561771 # number of SoftPFReq misses 157311201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 561771 # number of SoftPFReq misses 157411201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::cpu1.data 510720 # number of WriteLineReq misses 157511201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::total 510720 # number of WriteLineReq misses 157611201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 156544 # number of LoadLockedReq misses 157711201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 156544 # number of LoadLockedReq misses 157811201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 180437 # number of StoreCondReq misses 157911201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 180437 # number of StoreCondReq misses 158011201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 5228498 # number of demand (read+write) misses 158111201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 5228498 # number of demand (read+write) misses 158211201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 5790269 # number of overall misses 158311201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 5790269 # number of overall misses 158411201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 48221817000 # number of ReadReq miss cycles 158511201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 48221817000 # number of ReadReq miss cycles 158611201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 44559226500 # number of WriteReq miss cycles 158711201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 44559226500 # number of WriteReq miss cycles 158811201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 19302885000 # number of WriteLineReq miss cycles 158911201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::total 19302885000 # number of WriteLineReq miss cycles 159011201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2427765500 # number of LoadLockedReq miss cycles 159111201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 2427765500 # number of LoadLockedReq miss cycles 159211201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5104015500 # number of StoreCondReq miss cycles 159311201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 5104015500 # number of StoreCondReq miss cycles 159411201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 7589000 # number of StoreCondFailReq miss cycles 159511201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::total 7589000 # number of StoreCondFailReq miss cycles 159611201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::cpu1.data 92781043500 # number of demand (read+write) miss cycles 159711201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::total 92781043500 # number of demand (read+write) miss cycles 159811201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::cpu1.data 92781043500 # number of overall miss cycles 159911201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::total 92781043500 # number of overall miss cycles 160011201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 79159217 # number of ReadReq accesses(hits+misses) 160111201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 79159217 # number of ReadReq accesses(hits+misses) 160211201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 70425498 # number of WriteReq accesses(hits+misses) 160311201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 70425498 # number of WriteReq accesses(hits+misses) 160411201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 794249 # number of SoftPFReq accesses(hits+misses) 160511201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 794249 # number of SoftPFReq accesses(hits+misses) 160611201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::cpu1.data 694902 # number of WriteLineReq accesses(hits+misses) 160711201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::total 694902 # number of WriteLineReq accesses(hits+misses) 160811201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1706247 # number of LoadLockedReq accesses(hits+misses) 160911201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 1706247 # number of LoadLockedReq accesses(hits+misses) 161011201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1704699 # number of StoreCondReq accesses(hits+misses) 161111201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 1704699 # number of StoreCondReq accesses(hits+misses) 161211201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 149584715 # number of demand (read+write) accesses 161311201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 149584715 # number of demand (read+write) accesses 161411201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 150378964 # number of overall (read+write) accesses 161511201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 150378964 # number of overall (read+write) accesses 161611201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.039467 # miss rate for ReadReq accesses 161711201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.039467 # miss rate for ReadReq accesses 161811201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029880 # miss rate for WriteReq accesses 161911201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.029880 # miss rate for WriteReq accesses 162011201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.707298 # miss rate for SoftPFReq accesses 162111201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.707298 # miss rate for SoftPFReq accesses 162211201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.734953 # miss rate for WriteLineReq accesses 162311201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::total 0.734953 # miss rate for WriteLineReq accesses 162411201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.091748 # miss rate for LoadLockedReq accesses 162511201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.091748 # miss rate for LoadLockedReq accesses 162611201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105847 # miss rate for StoreCondReq accesses 162711201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.105847 # miss rate for StoreCondReq accesses 162811201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.034953 # miss rate for demand accesses 162911201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.034953 # miss rate for demand accesses 163011201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.038505 # miss rate for overall accesses 163111201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.038505 # miss rate for overall accesses 163211201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15435.130403 # average ReadReq miss latency 163311201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 15435.130403 # average ReadReq miss latency 163411201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21174.937914 # average WriteReq miss latency 163511201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 21174.937914 # average WriteReq miss latency 163611201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 37795.435855 # average WriteLineReq miss latency 163711201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::total 37795.435855 # average WriteLineReq miss latency 163811201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15508.518372 # average LoadLockedReq miss latency 163911201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15508.518372 # average LoadLockedReq miss latency 164011201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28286.967196 # average StoreCondReq miss latency 164111201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28286.967196 # average StoreCondReq miss latency 164210636Snilay@cs.wisc.edusystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 164310585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 164411201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17745.257529 # average overall miss latency 164511201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 17745.257529 # average overall miss latency 164611201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16023.615397 # average overall miss latency 164711201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 16023.615397 # average overall miss latency 164810585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 164910585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 165010585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 165110585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 165210585Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 165310585Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 165410585Sandreas.hansson@arm.comsystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 165510585Sandreas.hansson@arm.comsystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 165611201Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 4921438 # number of writebacks 165711201Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 4921438 # number of writebacks 165811201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 336855 # number of ReadReq MSHR hits 165911201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 336855 # number of ReadReq MSHR hits 166011201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 865157 # number of WriteReq MSHR hits 166111201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 865157 # number of WriteReq MSHR hits 166211201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 99 # number of WriteLineReq MSHR hits 166311201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_hits::total 99 # number of WriteLineReq MSHR hits 166411201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 39963 # number of LoadLockedReq MSHR hits 166511201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 39963 # number of LoadLockedReq MSHR hits 166611201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 44 # number of StoreCondReq MSHR hits 166711201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_hits::total 44 # number of StoreCondReq MSHR hits 166811201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::cpu1.data 1202012 # number of demand (read+write) MSHR hits 166911201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::total 1202012 # number of demand (read+write) MSHR hits 167011201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::cpu1.data 1202012 # number of overall MSHR hits 167111201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::total 1202012 # number of overall MSHR hits 167211201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2787305 # number of ReadReq MSHR misses 167311201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 2787305 # number of ReadReq MSHR misses 167411201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1239181 # number of WriteReq MSHR misses 167511201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 1239181 # number of WriteReq MSHR misses 167611201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 561309 # number of SoftPFReq MSHR misses 167711201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::total 561309 # number of SoftPFReq MSHR misses 167811201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 510621 # number of WriteLineReq MSHR misses 167911201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::total 510621 # number of WriteLineReq MSHR misses 168011201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 116581 # number of LoadLockedReq MSHR misses 168111201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 116581 # number of LoadLockedReq MSHR misses 168211201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 180393 # number of StoreCondReq MSHR misses 168311201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 180393 # number of StoreCondReq MSHR misses 168411201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.data 4026486 # number of demand (read+write) MSHR misses 168511201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 4026486 # number of demand (read+write) MSHR misses 168611201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.data 4587795 # number of overall MSHR misses 168711201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 4587795 # number of overall MSHR misses 168811201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 20902 # number of ReadReq MSHR uncacheable 168911201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::total 20902 # number of ReadReq MSHR uncacheable 169011201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 19312 # number of WriteReq MSHR uncacheable 169111201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::total 19312 # number of WriteReq MSHR uncacheable 169211201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 40214 # number of overall MSHR uncacheable misses 169311201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::total 40214 # number of overall MSHR uncacheable misses 169411201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38841507500 # number of ReadReq MSHR miss cycles 169511201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 38841507500 # number of ReadReq MSHR miss cycles 169611201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 26434060500 # number of WriteReq MSHR miss cycles 169711201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 26434060500 # number of WriteReq MSHR miss cycles 169811201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12644921000 # number of SoftPFReq MSHR miss cycles 169911201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12644921000 # number of SoftPFReq MSHR miss cycles 170011201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 18783135000 # number of WriteLineReq MSHR miss cycles 170111201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 18783135000 # number of WriteLineReq MSHR miss cycles 170211201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1568875000 # number of LoadLockedReq MSHR miss cycles 170311201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1568875000 # number of LoadLockedReq MSHR miss cycles 170411201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4920605000 # number of StoreCondReq MSHR miss cycles 170511201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4920605000 # number of StoreCondReq MSHR miss cycles 170611201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 7128000 # number of StoreCondFailReq MSHR miss cycles 170711201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 7128000 # number of StoreCondFailReq MSHR miss cycles 170811201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 65275568000 # number of demand (read+write) MSHR miss cycles 170911201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 65275568000 # number of demand (read+write) MSHR miss cycles 171011201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 77920489000 # number of overall MSHR miss cycles 171111201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 77920489000 # number of overall MSHR miss cycles 171211201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3868216000 # number of ReadReq MSHR uncacheable cycles 171311201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3868216000 # number of ReadReq MSHR uncacheable cycles 171411201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3618681000 # number of WriteReq MSHR uncacheable cycles 171511201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3618681000 # number of WriteReq MSHR uncacheable cycles 171611201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 7486897000 # number of overall MSHR uncacheable cycles 171711201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 7486897000 # number of overall MSHR uncacheable cycles 171811201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035211 # mshr miss rate for ReadReq accesses 171911201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035211 # mshr miss rate for ReadReq accesses 172011201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017596 # mshr miss rate for WriteReq accesses 172111201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017596 # mshr miss rate for WriteReq accesses 172211201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.706717 # mshr miss rate for SoftPFReq accesses 172311201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.706717 # mshr miss rate for SoftPFReq accesses 172411201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.734810 # mshr miss rate for WriteLineReq accesses 172511201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.734810 # mshr miss rate for WriteLineReq accesses 172611201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068326 # mshr miss rate for LoadLockedReq accesses 172711201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068326 # mshr miss rate for LoadLockedReq accesses 172811201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105821 # mshr miss rate for StoreCondReq accesses 172911201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105821 # mshr miss rate for StoreCondReq accesses 173011201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026918 # mshr miss rate for demand accesses 173111201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.026918 # mshr miss rate for demand accesses 173211201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030508 # mshr miss rate for overall accesses 173311201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.030508 # mshr miss rate for overall accesses 173411201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13935.147930 # average ReadReq mshr miss latency 173511201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13935.147930 # average ReadReq mshr miss latency 173611201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21331.880089 # average WriteReq mshr miss latency 173711201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21331.880089 # average WriteReq mshr miss latency 173811201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22527.557905 # average SoftPFReq mshr miss latency 173911201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22527.557905 # average SoftPFReq mshr miss latency 174011201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 36784.885463 # average WriteLineReq mshr miss latency 174111201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 36784.885463 # average WriteLineReq mshr miss latency 174211201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13457.381563 # average LoadLockedReq mshr miss latency 174311201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13457.381563 # average LoadLockedReq mshr miss latency 174411201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 27277.139357 # average StoreCondReq mshr miss latency 174511201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27277.139357 # average StoreCondReq mshr miss latency 174610636Snilay@cs.wisc.edusystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 174710585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 174811201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16211.547240 # average overall mshr miss latency 174911201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 16211.547240 # average overall mshr miss latency 175011201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16984.300519 # average overall mshr miss latency 175111201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 16984.300519 # average overall mshr miss latency 175211201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 185064.395752 # average ReadReq mshr uncacheable latency 175311201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185064.395752 # average ReadReq mshr uncacheable latency 175411201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 187379.919221 # average WriteReq mshr uncacheable latency 175511201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 187379.919221 # average WriteReq mshr uncacheable latency 175611201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 186176.381360 # average overall mshr uncacheable latency 175711201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 186176.381360 # average overall mshr uncacheable latency 175810585Sandreas.hansson@arm.comsystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 175911201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 9409188 # number of replacements 176011201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 506.684863 # Cycle average of tags in use 176111201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 216784534 # Total number of references to valid blocks. 176211201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 9409700 # Sample count of references to valid blocks. 176311201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 23.038411 # Average number of references to valid blocks. 176411201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 8388652871500 # Cycle when the warmup percentage was hit. 176511201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 506.684863 # Average occupied blocks per requestor 176611201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.989619 # Average percentage of cache occupancy 176711201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.989619 # Average percentage of cache occupancy 176810585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 176911201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id 177011201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 281 # Occupied blocks per task id 177111201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id 177210585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 177311201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 461798168 # Number of tag accesses 177411201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 461798168 # Number of data accesses 177511201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 216784534 # number of ReadReq hits 177611201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 216784534 # number of ReadReq hits 177711201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 216784534 # number of demand (read+write) hits 177811201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 216784534 # number of demand (read+write) hits 177911201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 216784534 # number of overall hits 178011201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 216784534 # number of overall hits 178111201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 9409700 # number of ReadReq misses 178211201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 9409700 # number of ReadReq misses 178311201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 9409700 # number of demand (read+write) misses 178411201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 9409700 # number of demand (read+write) misses 178511201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 9409700 # number of overall misses 178611201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 9409700 # number of overall misses 178711201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 95979801000 # number of ReadReq miss cycles 178811201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 95979801000 # number of ReadReq miss cycles 178911201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 95979801000 # number of demand (read+write) miss cycles 179011201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::total 95979801000 # number of demand (read+write) miss cycles 179111201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 95979801000 # number of overall miss cycles 179211201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::total 95979801000 # number of overall miss cycles 179311201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 226194234 # number of ReadReq accesses(hits+misses) 179411201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 226194234 # number of ReadReq accesses(hits+misses) 179511201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 226194234 # number of demand (read+write) accesses 179611201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 226194234 # number of demand (read+write) accesses 179711201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 226194234 # number of overall (read+write) accesses 179811201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 226194234 # number of overall (read+write) accesses 179911201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.041600 # miss rate for ReadReq accesses 180011201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.041600 # miss rate for ReadReq accesses 180111201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.041600 # miss rate for demand accesses 180211201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.041600 # miss rate for demand accesses 180311201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.041600 # miss rate for overall accesses 180411201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.041600 # miss rate for overall accesses 180511201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10200.091501 # average ReadReq miss latency 180611201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 10200.091501 # average ReadReq miss latency 180711201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10200.091501 # average overall miss latency 180811201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 10200.091501 # average overall miss latency 180911201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10200.091501 # average overall miss latency 181011201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 10200.091501 # average overall miss latency 181110585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 181210585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 181310585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 181410585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 181510585Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 181610585Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 181710585Sandreas.hansson@arm.comsystem.cpu1.icache.fast_writes 0 # number of fast writes performed 181810585Sandreas.hansson@arm.comsystem.cpu1.icache.cache_copies 0 # number of cache copies performed 181911201Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::writebacks 9409188 # number of writebacks 182011201Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::total 9409188 # number of writebacks 182111201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9409700 # number of ReadReq MSHR misses 182211201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 9409700 # number of ReadReq MSHR misses 182311201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 9409700 # number of demand (read+write) MSHR misses 182411201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::total 9409700 # number of demand (read+write) MSHR misses 182511201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 9409700 # number of overall MSHR misses 182611201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::total 9409700 # number of overall MSHR misses 182711138Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 92 # number of ReadReq MSHR uncacheable 182811138Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::total 92 # number of ReadReq MSHR uncacheable 182911138Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses 183011138Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::total 92 # number of overall MSHR uncacheable misses 183111201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 91274951000 # number of ReadReq MSHR miss cycles 183211201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 91274951000 # number of ReadReq MSHR miss cycles 183311201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 91274951000 # number of demand (read+write) MSHR miss cycles 183411201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 91274951000 # number of demand (read+write) MSHR miss cycles 183511201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 91274951000 # number of overall MSHR miss cycles 183611201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 91274951000 # number of overall MSHR miss cycles 183711201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12950500 # number of ReadReq MSHR uncacheable cycles 183811201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 12950500 # number of ReadReq MSHR uncacheable cycles 183911201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 12950500 # number of overall MSHR uncacheable cycles 184011201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::total 12950500 # number of overall MSHR uncacheable cycles 184111201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.041600 # mshr miss rate for ReadReq accesses 184211201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.041600 # mshr miss rate for ReadReq accesses 184311201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.041600 # mshr miss rate for demand accesses 184411201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.041600 # mshr miss rate for demand accesses 184511201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.041600 # mshr miss rate for overall accesses 184611201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.041600 # mshr miss rate for overall accesses 184711201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9700.091501 # average ReadReq mshr miss latency 184811201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9700.091501 # average ReadReq mshr miss latency 184911201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9700.091501 # average overall mshr miss latency 185011201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 9700.091501 # average overall mshr miss latency 185111201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9700.091501 # average overall mshr miss latency 185211201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 9700.091501 # average overall mshr miss latency 185311201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 140766.304348 # average ReadReq mshr uncacheable latency 185411201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 140766.304348 # average ReadReq mshr uncacheable latency 185511201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 140766.304348 # average overall mshr uncacheable latency 185611201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 140766.304348 # average overall mshr uncacheable latency 185710585Sandreas.hansson@arm.comsystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 185811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.num_hwpf_issued 6599308 # number of hwpf issued 185911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfIdentified 6600409 # number of prefetch candidates identified 186011167Sjthestness@gmail.comsystem.cpu1.l2cache.prefetcher.pfBufferHit 970 # number of redundant prefetches already in prefetch queue 186110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 186210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 186311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfSpanPage 793623 # number of prefetches not generated due to page crossing 186411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.replacements 2151198 # number of replacements 186511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tagsinuse 13377.061252 # Cycle average of tags in use 186611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.total_refs 23203065 # Total number of references to valid blocks. 186711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.sampled_refs 2166951 # Sample count of references to valid blocks. 186811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.avg_refs 10.707702 # Average number of references to valid blocks. 186911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 9986150274500 # Cycle when the warmup percentage was hit. 187011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 12523.259690 # Average occupied blocks per requestor 187111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 66.377906 # Average occupied blocks per requestor 187211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 74.184237 # Average occupied blocks per requestor 187311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 713.239419 # Average occupied blocks per requestor 187411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.764359 # Average percentage of cache occupancy 187511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004051 # Average percentage of cache occupancy 187611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004528 # Average percentage of cache occupancy 187711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.043533 # Average percentage of cache occupancy 187811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.816471 # Average percentage of cache occupancy 187911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1022 985 # Occupied blocks per task id 188011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 109 # Occupied blocks per task id 188111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 14659 # Occupied blocks per task id 188211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id 188311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id 188411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::2 173 # Occupied blocks per task id 188511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::3 750 # Occupied blocks per task id 188611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::4 51 # Occupied blocks per task id 188711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id 188811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 59 # Occupied blocks per task id 188911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 46 # Occupied blocks per task id 189011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id 189111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id 189211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1249 # Occupied blocks per task id 189311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4750 # Occupied blocks per task id 189411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8044 # Occupied blocks per task id 189511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 438 # Occupied blocks per task id 189611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1022 0.060120 # Percentage of cache occupancy per task id 189711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006653 # Percentage of cache occupancy per task id 189811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.894714 # Percentage of cache occupancy per task id 189911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tag_accesses 482635734 # Number of tag accesses 190011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.data_accesses 482635734 # Number of data accesses 190111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 517404 # number of ReadReq hits 190211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 182303 # number of ReadReq hits 190311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 699707 # number of ReadReq hits 190411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::writebacks 3095740 # number of WritebackDirty hits 190511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::total 3095740 # number of WritebackDirty hits 190611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_hits::writebacks 11232116 # number of WritebackClean hits 190711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_hits::total 11232116 # number of WritebackClean hits 190811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::cpu1.data 197 # number of UpgradeReq hits 190911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::total 197 # number of UpgradeReq hits 191011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 799662 # number of ReadExReq hits 191111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 799662 # number of ReadExReq hits 191211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8718417 # number of ReadCleanReq hits 191311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 8718417 # number of ReadCleanReq hits 191411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2602566 # number of ReadSharedReq hits 191511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 2602566 # number of ReadSharedReq hits 191611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::cpu1.data 242267 # number of InvalidateReq hits 191711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::total 242267 # number of InvalidateReq hits 191811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 517404 # number of demand (read+write) hits 191911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 182303 # number of demand (read+write) hits 192011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 8718417 # number of demand (read+write) hits 192111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 3402228 # number of demand (read+write) hits 192211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::total 12820352 # number of demand (read+write) hits 192311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 517404 # number of overall hits 192411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 182303 # number of overall hits 192511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 8718417 # number of overall hits 192611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 3402228 # number of overall hits 192711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::total 12820352 # number of overall hits 192811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 10447 # number of ReadReq misses 192911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7725 # number of ReadReq misses 193011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 18172 # number of ReadReq misses 193111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 203082 # number of UpgradeReq misses 193211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 203082 # number of UpgradeReq misses 193311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 180388 # number of SCUpgradeReq misses 193411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 180388 # number of SCUpgradeReq misses 193511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses 193611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses 193711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 239405 # number of ReadExReq misses 193811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 239405 # number of ReadExReq misses 193911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 691283 # number of ReadCleanReq misses 194011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 691283 # number of ReadCleanReq misses 194111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 862205 # number of ReadSharedReq misses 194211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 862205 # number of ReadSharedReq misses 194311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::cpu1.data 266022 # number of InvalidateReq misses 194411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::total 266022 # number of InvalidateReq misses 194511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 10447 # number of demand (read+write) misses 194611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 7725 # number of demand (read+write) misses 194711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 691283 # number of demand (read+write) misses 194811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 1101610 # number of demand (read+write) misses 194911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::total 1811065 # number of demand (read+write) misses 195011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 10447 # number of overall misses 195111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 7725 # number of overall misses 195211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 691283 # number of overall misses 195311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 1101610 # number of overall misses 195411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::total 1811065 # number of overall misses 195511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 361003500 # number of ReadReq miss cycles 195611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 296858500 # number of ReadReq miss cycles 195711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::total 657862000 # number of ReadReq miss cycles 195811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3343793000 # number of UpgradeReq miss cycles 195911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::total 3343793000 # number of UpgradeReq miss cycles 196011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1815465000 # number of SCUpgradeReq miss cycles 196111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1815465000 # number of SCUpgradeReq miss cycles 196211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 7003999 # number of SCUpgradeFailReq miss cycles 196311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 7003999 # number of SCUpgradeFailReq miss cycles 196411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11577465998 # number of ReadExReq miss cycles 196511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::total 11577465998 # number of ReadExReq miss cycles 196611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 24488845500 # number of ReadCleanReq miss cycles 196711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::total 24488845500 # number of ReadCleanReq miss cycles 196811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 30668978480 # number of ReadSharedReq miss cycles 196911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::total 30668978480 # number of ReadSharedReq miss cycles 197011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 16284255500 # number of InvalidateReq miss cycles 197111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::total 16284255500 # number of InvalidateReq miss cycles 197211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 361003500 # number of demand (read+write) miss cycles 197311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 296858500 # number of demand (read+write) miss cycles 197411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.inst 24488845500 # number of demand (read+write) miss cycles 197511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.data 42246444478 # number of demand (read+write) miss cycles 197611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::total 67393151978 # number of demand (read+write) miss cycles 197711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 361003500 # number of overall miss cycles 197811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 296858500 # number of overall miss cycles 197911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.inst 24488845500 # number of overall miss cycles 198011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.data 42246444478 # number of overall miss cycles 198111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::total 67393151978 # number of overall miss cycles 198211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 527851 # number of ReadReq accesses(hits+misses) 198311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 190028 # number of ReadReq accesses(hits+misses) 198411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 717879 # number of ReadReq accesses(hits+misses) 198511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::writebacks 3095740 # number of WritebackDirty accesses(hits+misses) 198611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::total 3095740 # number of WritebackDirty accesses(hits+misses) 198711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::writebacks 11232116 # number of WritebackClean accesses(hits+misses) 198811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::total 11232116 # number of WritebackClean accesses(hits+misses) 198911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 203279 # number of UpgradeReq accesses(hits+misses) 199011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 203279 # number of UpgradeReq accesses(hits+misses) 199111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 180388 # number of SCUpgradeReq accesses(hits+misses) 199211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 180388 # number of SCUpgradeReq accesses(hits+misses) 199311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5 # number of SCUpgradeFailReq accesses(hits+misses) 199411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) 199511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1039067 # number of ReadExReq accesses(hits+misses) 199611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 1039067 # number of ReadExReq accesses(hits+misses) 199711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 9409700 # number of ReadCleanReq accesses(hits+misses) 199811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 9409700 # number of ReadCleanReq accesses(hits+misses) 199911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3464771 # number of ReadSharedReq accesses(hits+misses) 200011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 3464771 # number of ReadSharedReq accesses(hits+misses) 200111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 508289 # number of InvalidateReq accesses(hits+misses) 200211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::total 508289 # number of InvalidateReq accesses(hits+misses) 200311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 527851 # number of demand (read+write) accesses 200411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 190028 # number of demand (read+write) accesses 200511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 9409700 # number of demand (read+write) accesses 200611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 4503838 # number of demand (read+write) accesses 200711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::total 14631417 # number of demand (read+write) accesses 200811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 527851 # number of overall (read+write) accesses 200911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 190028 # number of overall (read+write) accesses 201011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 9409700 # number of overall (read+write) accesses 201111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 4503838 # number of overall (read+write) accesses 201211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::total 14631417 # number of overall (read+write) accesses 201311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.019792 # miss rate for ReadReq accesses 201411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.040652 # miss rate for ReadReq accesses 201511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.025313 # miss rate for ReadReq accesses 201611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999031 # miss rate for UpgradeReq accesses 201711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999031 # miss rate for UpgradeReq accesses 201811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 201911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 202010636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 202110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 202211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.230404 # miss rate for ReadExReq accesses 202311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.230404 # miss rate for ReadExReq accesses 202411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.073465 # miss rate for ReadCleanReq accesses 202511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.073465 # miss rate for ReadCleanReq accesses 202611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.248849 # miss rate for ReadSharedReq accesses 202711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.248849 # miss rate for ReadSharedReq accesses 202811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.523368 # miss rate for InvalidateReq accesses 202911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::total 0.523368 # miss rate for InvalidateReq accesses 203011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.019792 # miss rate for demand accesses 203111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.040652 # miss rate for demand accesses 203211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.073465 # miss rate for demand accesses 203311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.244594 # miss rate for demand accesses 203411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.123779 # miss rate for demand accesses 203511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.019792 # miss rate for overall accesses 203611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.040652 # miss rate for overall accesses 203711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.073465 # miss rate for overall accesses 203811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.244594 # miss rate for overall accesses 203911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.123779 # miss rate for overall accesses 204011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 34555.709773 # average ReadReq miss latency 204111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 38428.284790 # average ReadReq miss latency 204211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::total 36201.959058 # average ReadReq miss latency 204311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 16465.235718 # average UpgradeReq miss latency 204411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 16465.235718 # average UpgradeReq miss latency 204511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 10064.222676 # average SCUpgradeReq miss latency 204611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 10064.222676 # average SCUpgradeReq miss latency 204711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 1400799.800000 # average SCUpgradeFailReq miss latency 204811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1400799.800000 # average SCUpgradeFailReq miss latency 204911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 48359.332503 # average ReadExReq miss latency 205011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::total 48359.332503 # average ReadExReq miss latency 205111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35425.210080 # average ReadCleanReq miss latency 205211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35425.210080 # average ReadCleanReq miss latency 205311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 35570.402027 # average ReadSharedReq miss latency 205411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 35570.402027 # average ReadSharedReq miss latency 205511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 61213.942832 # average InvalidateReq miss latency 205611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 61213.942832 # average InvalidateReq miss latency 205711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 34555.709773 # average overall miss latency 205811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 38428.284790 # average overall miss latency 205911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35425.210080 # average overall miss latency 206011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 38349.728559 # average overall miss latency 206111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::total 37211.890229 # average overall miss latency 206211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 34555.709773 # average overall miss latency 206311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 38428.284790 # average overall miss latency 206411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35425.210080 # average overall miss latency 206511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 38349.728559 # average overall miss latency 206611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::total 37211.890229 # average overall miss latency 206710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 206810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 206910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 207010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 207110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 207210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 207310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.fast_writes 0 # number of fast writes performed 207410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.cache_copies 0 # number of cache copies performed 207511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::writebacks 1042577 # number of writebacks 207611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::total 1042577 # number of writebacks 207711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 1 # number of ReadReq MSHR hits 207811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 207911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 4272 # number of ReadExReq MSHR hits 208011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::total 4272 # number of ReadExReq MSHR hits 208111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 7 # number of ReadCleanReq MSHR hits 208211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_hits::total 7 # number of ReadCleanReq MSHR hits 208311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 1142 # number of ReadSharedReq MSHR hits 208411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::total 1142 # number of ReadSharedReq MSHR hits 208511138Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 1 # number of demand (read+write) MSHR hits 208611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits 208711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.data 5414 # number of demand (read+write) MSHR hits 208811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::total 5422 # number of demand (read+write) MSHR hits 208911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 1 # number of overall MSHR hits 209011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.inst 7 # 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number of ReadCleanReq MSHR misses 210811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 861063 # number of ReadSharedReq MSHR misses 210911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::total 861063 # number of ReadSharedReq MSHR misses 211011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 266022 # number of InvalidateReq MSHR misses 211111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::total 266022 # number of InvalidateReq MSHR misses 211211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 10447 # number of demand (read+write) MSHR misses 211311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 7724 # number of demand (read+write) MSHR misses 211411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.inst 691276 # number of demand (read+write) MSHR misses 211511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.data 1096196 # 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number of ReadReq MSHR uncacheable 212411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 20902 # number of ReadReq MSHR uncacheable 212511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::total 20994 # number of ReadReq MSHR uncacheable 212611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 19312 # number of WriteReq MSHR uncacheable 212711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::total 19312 # number of WriteReq MSHR uncacheable 212811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses 212911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 40214 # number of overall MSHR uncacheable misses 213011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::total 40306 # number of overall MSHR uncacheable misses 213111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 298321500 # number of ReadReq MSHR miss cycles 213211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 250498000 # number of ReadReq MSHR miss cycles 213311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::total 548819500 # number of ReadReq MSHR miss cycles 213411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 24534893187 # number of HardPFReq MSHR miss cycles 213511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 24534893187 # number of HardPFReq MSHR miss cycles 213611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 6599396497 # number of UpgradeReq MSHR miss cycles 213711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 6599396497 # number of UpgradeReq MSHR miss cycles 213811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3563733500 # number of SCUpgradeReq MSHR miss cycles 213911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3563733500 # 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number of overall MSHR miss cycles 216111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12214500 # number of ReadReq MSHR uncacheable cycles 216211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3700892500 # number of ReadReq MSHR uncacheable cycles 216311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3713107000 # number of ReadReq MSHR uncacheable cycles 216411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 3473788500 # number of WriteReq MSHR uncacheable cycles 216511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3473788500 # number of WriteReq MSHR uncacheable cycles 216611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12214500 # number of overall MSHR uncacheable cycles 216711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 7174681000 # number of overall MSHR uncacheable cycles 216811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::total 7186895500 # number of overall MSHR uncacheable cycles 216911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.019792 # mshr miss rate for ReadReq accesses 217011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.040647 # mshr miss rate for ReadReq accesses 217111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.025312 # mshr miss rate for ReadReq accesses 217210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 217310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 217411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.999031 # mshr miss rate for UpgradeReq accesses 217511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.999031 # mshr miss rate for UpgradeReq accesses 217611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 217711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 217810636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 217910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 218011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.226292 # mshr miss rate for ReadExReq accesses 218111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.226292 # mshr miss rate for ReadExReq accesses 218211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.073464 # mshr miss rate for ReadCleanReq accesses 218311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.073464 # mshr miss rate for ReadCleanReq accesses 218411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.248519 # mshr miss rate for ReadSharedReq accesses 218511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248519 # mshr miss rate for ReadSharedReq accesses 218611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.523368 # mshr miss rate for InvalidateReq accesses 218711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.523368 # mshr miss rate for InvalidateReq accesses 218811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.019792 # mshr miss rate for demand accesses 218911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.040647 # mshr miss rate for demand accesses 219011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.073464 # mshr miss rate for demand accesses 219111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.243392 # mshr miss rate for demand accesses 219211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::total 0.123409 # mshr miss rate for demand accesses 219311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.019792 # mshr miss rate for overall accesses 219411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.040647 # mshr miss rate for overall accesses 219511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.073464 # mshr miss rate for overall accesses 219611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.243392 # mshr miss rate for overall accesses 219710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 219811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::total 0.169835 # mshr miss rate for overall accesses 219911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 28555.709773 # average ReadReq mshr miss latency 220011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 32431.123770 # average ReadReq mshr miss latency 220111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30203.043311 # average ReadReq mshr miss latency 220211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36118.703029 # average HardPFReq mshr miss latency 220311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36118.703029 # average HardPFReq mshr miss latency 220411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 32496.215800 # average UpgradeReq mshr miss latency 220511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32496.215800 # average UpgradeReq mshr miss latency 220611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19755.934430 # average SCUpgradeReq mshr miss latency 220711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19755.934430 # average SCUpgradeReq mshr miss latency 220811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1303599.800000 # average SCUpgradeFailReq mshr miss latency 220911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1303599.800000 # average SCUpgradeFailReq mshr miss latency 221011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 40767.089256 # average ReadExReq mshr miss latency 221111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 40767.089256 # average ReadExReq mshr miss latency 221211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29425.314202 # average ReadCleanReq mshr miss latency 221311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29425.314202 # average ReadCleanReq mshr miss latency 221411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 29525.390105 # average ReadSharedReq mshr miss latency 221511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29525.390105 # average ReadSharedReq mshr miss latency 221611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 55213.942832 # average InvalidateReq mshr miss latency 221711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 55213.942832 # average InvalidateReq mshr miss latency 221811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 28555.709773 # average overall mshr miss latency 221911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 32431.123770 # average overall mshr miss latency 222011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29425.314202 # average overall mshr miss latency 222111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31936.723887 # average overall mshr miss latency 222211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::total 30957.803939 # average overall mshr miss latency 222311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 28555.709773 # average overall mshr miss latency 222411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 32431.123770 # average overall mshr miss latency 222511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29425.314202 # average overall mshr miss latency 222611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31936.723887 # average overall mshr miss latency 222711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36118.703029 # average overall mshr miss latency 222811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32368.597869 # average overall mshr miss latency 222911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132766.304348 # average ReadReq mshr uncacheable latency 223011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177059.252703 # average ReadReq mshr uncacheable latency 223111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 176865.151948 # average ReadReq mshr uncacheable latency 223211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 179877.200704 # average WriteReq mshr uncacheable latency 223311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 179877.200704 # average WriteReq mshr uncacheable latency 223411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132766.304348 # average overall mshr uncacheable latency 223511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 178412.518029 # average overall mshr uncacheable latency 223611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 178308.328785 # average overall mshr uncacheable latency 223710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 223811201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_requests 29428527 # Total number of requests made to the snoop filter. 223911201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_requests 15006964 # Number of requests hitting in the snoop filter with a single holder of the requested data. 224011201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2768 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 224111201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_snoops 1972954 # Total number of snoops made to the snoop filter. 224211201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1972589 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 224311201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 365 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 224411201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 814249 # Transaction distribution 224511201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 13775310 # Transaction distribution 224611201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution 224711201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 19312 # Transaction distribution 224811201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 19312 # Transaction distribution 224911201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackDirty 4142105 # Transaction distribution 225011201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackClean 11232116 # Transaction distribution 225111201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::CleanEvict 2703238 # Transaction distribution 225211201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFReq 874176 # Transaction distribution 225311138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 225411201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 401941 # Transaction distribution 225511201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 322763 # Transaction distribution 225611201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 444037 # Transaction distribution 225711201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 57 # Transaction distribution 225811201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution 225911201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 1114947 # Transaction distribution 226011201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 1047219 # Transaction distribution 226111201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 9409700 # Transaction distribution 226211201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 4456605 # Transaction distribution 226311201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateReq 514166 # Transaction distribution 226411201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateResp 508289 # Transaction distribution 226511201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 28226960 # Packet count per connected master and slave (bytes) 226611201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15947748 # Packet count per connected master and slave (bytes) 226711201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 397923 # Packet count per connected master and slave (bytes) 226811201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1113211 # Packet count per connected master and slave (bytes) 226911201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count::total 45685842 # Packet count per connected master and slave (bytes) 227011201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1204298752 # Cumulative packet size per connected master and slave (bytes) 227111201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 609360975 # Cumulative packet size per connected master and slave (bytes) 227211201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1520224 # Cumulative packet size per connected master and slave (bytes) 227311201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4222808 # Cumulative packet size per connected master and slave (bytes) 227411201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size::total 1819402759 # Cumulative packet size per connected master and slave (bytes) 227511201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoops 6269077 # Total snoops (count) 227611201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 21677519 # Request fanout histogram 227711201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 0.104647 # Request fanout histogram 227811201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.306153 # Request fanout histogram 227910585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 228011201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 19409393 89.54% 89.54% # Request fanout histogram 228111201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 2267761 10.46% 100.00% # Request fanout histogram 228211201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 365 0.00% 100.00% # Request fanout histogram 228310585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 228411138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 228510827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 228611201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 21677519 # Request fanout histogram 228711201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.reqLayer0.occupancy 29325134974 # Layer occupancy (ticks) 228811201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 228911201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopLayer0.occupancy 172530424 # Layer occupancy (ticks) 229010585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 229111201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer0.occupancy 14118247362 # Layer occupancy (ticks) 229210585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 229311201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer1.occupancy 7236066136 # Layer occupancy (ticks) 229410585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 229511201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer2.occupancy 207955878 # Layer occupancy (ticks) 229610585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 229711201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer3.occupancy 585496227 # Layer occupancy (ticks) 229810585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 229911201Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 40404 # Transaction distribution 230011201Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 40404 # Transaction distribution 230111201Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 136972 # Transaction distribution 230211201Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 136972 # Transaction distribution 230311201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47770 # Packet count per connected master and slave (bytes) 230410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 230510585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 230610585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 230710585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 230810585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 230910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 231010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 231110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 231210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 231311201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) 231410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 231510585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 231610585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 231710585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 231811201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122912 # Packet count per connected master and slave (bytes) 231911201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231760 # Packet count per connected master and slave (bytes) 232011201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231760 # Packet count per connected master and slave (bytes) 232110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 232210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 232311201Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 354752 # Packet count per connected master and slave (bytes) 232411201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47790 # Cumulative packet size per connected master and slave (bytes) 232510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 232610585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 232710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 232810585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 232910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 233010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 233110585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 233210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 233310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 233411201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) 233510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 233610585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 233710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 233810585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 233911201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 155927 # Cumulative packet size per connected master and slave (bytes) 234011201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355392 # Cumulative packet size per connected master and slave (bytes) 234111201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7355392 # Cumulative packet size per connected master and slave (bytes) 234210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 234310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 234411201Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 7513405 # Cumulative packet size per connected master and slave (bytes) 234511201Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 47202500 # Layer occupancy (ticks) 234610585Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 234711201Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) 234810585Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 234911201Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) 235010585Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 235111201Sandreas.hansson@arm.comsystem.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks) 235210585Sandreas.hansson@arm.comsystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 235311201Sandreas.hansson@arm.comsystem.iobus.reqLayer10.occupancy 9000 # Layer occupancy (ticks) 235410585Sandreas.hansson@arm.comsystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 235511201Sandreas.hansson@arm.comsystem.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) 235610585Sandreas.hansson@arm.comsystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 235711201Sandreas.hansson@arm.comsystem.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) 235810585Sandreas.hansson@arm.comsystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 235911201Sandreas.hansson@arm.comsystem.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) 236010585Sandreas.hansson@arm.comsystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 236111201Sandreas.hansson@arm.comsystem.iobus.reqLayer16.occupancy 15500 # Layer occupancy (ticks) 236210585Sandreas.hansson@arm.comsystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 236311201Sandreas.hansson@arm.comsystem.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 236410585Sandreas.hansson@arm.comsystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 236511201Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 25874502 # Layer occupancy (ticks) 236610585Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 236711201Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 168500 # Layer occupancy (ticks) 236810585Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 236911201Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 36406501 # Layer occupancy (ticks) 237010585Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 237111201Sandreas.hansson@arm.comsystem.iobus.reqLayer26.occupancy 123500 # Layer occupancy (ticks) 237210585Sandreas.hansson@arm.comsystem.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 237311201Sandreas.hansson@arm.comsystem.iobus.reqLayer27.occupancy 566812397 # Layer occupancy (ticks) 237410585Sandreas.hansson@arm.comsystem.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 237511201Sandreas.hansson@arm.comsystem.iobus.reqLayer28.occupancy 31500 # Layer occupancy (ticks) 237610585Sandreas.hansson@arm.comsystem.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 237711201Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 92927000 # Layer occupancy (ticks) 237810585Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 237911201Sandreas.hansson@arm.comsystem.iobus.respLayer3.occupancy 148200000 # Layer occupancy (ticks) 238010585Sandreas.hansson@arm.comsystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 238110892Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 238210585Sandreas.hansson@arm.comsystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 238311201Sandreas.hansson@arm.comsystem.iocache.tags.replacements 115872 # number of replacements 238411201Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 11.264501 # Cycle average of tags in use 238511201Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 6 # Total number of references to valid blocks. 238611201Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 115888 # Sample count of references to valid blocks. 238711201Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0.000052 # Average number of references to valid blocks. 238811201Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 9145998133000 # Cycle when the warmup percentage was hit. 238911201Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 7.414921 # Average occupied blocks per requestor 239011201Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 3.849581 # Average occupied blocks per requestor 239111201Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.463433 # Average percentage of cache occupancy 239211201Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.240599 # Average percentage of cache occupancy 239311201Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.704031 # Average percentage of cache occupancy 239410585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 239510827Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 239610585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 239711201Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 1043272 # Number of tag accesses 239811201Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 1043272 # Number of data accesses 239911201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_hits::realview.ide 2 # number of WriteLineReq hits 240011201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_hits::total 2 # number of WriteLineReq hits 240110585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 240211201Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ide 8896 # number of ReadReq misses 240311201Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 8933 # number of ReadReq misses 240410585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 240510585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 240611201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106982 # number of WriteLineReq misses 240711201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 106982 # number of WriteLineReq misses 240810585Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 240911201Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ide 8896 # number of demand (read+write) misses 241011201Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 8936 # number of demand (read+write) misses 241110585Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 241211201Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ide 8896 # number of overall misses 241311201Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 8936 # number of overall misses 241411201Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5261000 # number of ReadReq miss cycles 241511201Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ide 1700094991 # number of ReadReq miss cycles 241611201Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 1705355991 # number of ReadReq miss cycles 241710726Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 241810726Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 241911201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::realview.ide 14013428406 # number of WriteLineReq miss cycles 242011201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::total 14013428406 # number of WriteLineReq miss cycles 242111201Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ethernet 5630000 # number of demand (read+write) miss cycles 242211201Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ide 1700094991 # number of demand (read+write) miss cycles 242311201Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 1705724991 # number of demand (read+write) miss cycles 242411201Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ethernet 5630000 # number of overall miss cycles 242511201Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ide 1700094991 # number of overall miss cycles 242611201Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 1705724991 # number of overall miss cycles 242710585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 242811201Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8896 # number of ReadReq accesses(hits+misses) 242911201Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 8933 # number of ReadReq accesses(hits+misses) 243010585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 243110585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 243211201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) 243311201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) 243410585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 243511201Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ide 8896 # number of demand (read+write) accesses 243611201Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 8936 # number of demand (read+write) accesses 243710585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 243811201Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 8896 # number of overall (read+write) accesses 243911201Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 8936 # number of overall (read+write) accesses 244010585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 244110585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 244210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 244310585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 244410585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 244511201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 0.999981 # miss rate for WriteLineReq accesses 244611201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 0.999981 # miss rate for WriteLineReq accesses 244710585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 244810585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 244910585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 245010585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 245110585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 245210585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 245311201Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 142189.189189 # average ReadReq miss latency 245411201Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 191107.800247 # average ReadReq miss latency 245511201Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 190905.182022 # average ReadReq miss latency 245610726Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 245710726Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 245811201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::realview.ide 130988.656092 # average WriteLineReq miss latency 245911201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 130988.656092 # average WriteLineReq miss latency 246011201Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 140750 # average overall miss latency 246111201Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ide 191107.800247 # average overall miss latency 246211201Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 190882.384848 # average overall miss latency 246311201Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 140750 # average overall miss latency 246411201Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ide 191107.800247 # average overall miss latency 246511201Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 190882.384848 # average overall miss latency 246611201Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 36149 # number of cycles access was blocked 246710585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 246811201Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 3721 # number of cycles access was blocked 246910585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 247011201Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 9.714862 # average number of cycles each access was blocked 247110585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 247210585Sandreas.hansson@arm.comsystem.iocache.fast_writes 0 # number of fast writes performed 247310585Sandreas.hansson@arm.comsystem.iocache.cache_copies 0 # number of cache copies performed 247411201Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 106948 # number of writebacks 247511201Sandreas.hansson@arm.comsystem.iocache.writebacks::total 106948 # number of writebacks 247610585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 247711201Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8896 # number of ReadReq MSHR misses 247811201Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::total 8933 # number of ReadReq MSHR misses 247910585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 248010585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 248111201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::realview.ide 106982 # number of WriteLineReq MSHR misses 248211201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 106982 # number of WriteLineReq MSHR misses 248310585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 248411201Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ide 8896 # number of demand (read+write) MSHR misses 248511201Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::total 8936 # number of demand (read+write) MSHR misses 248610585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 248711201Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ide 8896 # number of overall MSHR misses 248811201Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::total 8936 # number of overall MSHR misses 248911201Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3411000 # number of ReadReq MSHR miss cycles 249011201Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1255294991 # number of ReadReq MSHR miss cycles 249111201Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 1258705991 # number of ReadReq MSHR miss cycles 249210892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 249310892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 249411201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8664328406 # number of WriteLineReq MSHR miss cycles 249511201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 8664328406 # number of WriteLineReq MSHR miss cycles 249611201Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3630000 # number of demand (read+write) MSHR miss cycles 249711201Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ide 1255294991 # number of demand (read+write) MSHR miss cycles 249811201Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 1258924991 # number of demand (read+write) MSHR miss cycles 249911201Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3630000 # number of overall MSHR miss cycles 250011201Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ide 1255294991 # number of overall MSHR miss cycles 250111201Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 1258924991 # number of overall MSHR miss cycles 250210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 250310585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 250410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 250510585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 250610585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 250711201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.999981 # mshr miss rate for WriteLineReq accesses 250811201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 0.999981 # mshr miss rate for WriteLineReq accesses 250910585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 251010585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 251110585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 251210585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 251310585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 251410585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 251511201Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 92189.189189 # average ReadReq mshr miss latency 251611201Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141107.800247 # average ReadReq mshr miss latency 251711201Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 140905.182022 # average ReadReq mshr miss latency 251810892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 251910892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 252011201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80988.656092 # average WriteLineReq mshr miss latency 252111201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 80988.656092 # average WriteLineReq mshr miss latency 252211201Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 90750 # average overall mshr miss latency 252311201Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 141107.800247 # average overall mshr miss latency 252411201Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 140882.384848 # average overall mshr miss latency 252511201Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 90750 # average overall mshr miss latency 252611201Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 141107.800247 # average overall mshr miss latency 252711201Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 140882.384848 # average overall mshr miss latency 252810585Sandreas.hansson@arm.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 252911201Sandreas.hansson@arm.comsystem.l2c.tags.replacements 1047057 # number of replacements 253011201Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 63052.180525 # Cycle average of tags in use 253111201Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 6067910 # Total number of references to valid blocks. 253211201Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 1106756 # Sample count of references to valid blocks. 253311201Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 5.482609 # Average number of references to valid blocks. 253410892Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 253511201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 25661.598067 # Average occupied blocks per requestor 253611201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 59.549817 # Average occupied blocks per requestor 253711201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 63.820457 # Average occupied blocks per requestor 253811201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 6721.957431 # Average occupied blocks per requestor 253911201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 5596.771487 # Average occupied blocks per requestor 254011201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 5304.396230 # Average occupied blocks per requestor 254111201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 138.527549 # Average occupied blocks per requestor 254211201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 206.635310 # Average occupied blocks per requestor 254311201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 5419.027786 # Average occupied blocks per requestor 254411201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 6651.679849 # Average occupied blocks per requestor 254511201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 7228.216543 # Average occupied blocks per requestor 254611201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.391565 # Average percentage of cache occupancy 254711201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.000909 # Average percentage of cache occupancy 254811201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.000974 # Average percentage of cache occupancy 254911201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.102569 # Average percentage of cache occupancy 255011201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.085400 # Average percentage of cache occupancy 255111201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.080939 # Average percentage of cache occupancy 255211201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.002114 # Average percentage of cache occupancy 255311201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.003153 # Average percentage of cache occupancy 255411201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.082688 # Average percentage of cache occupancy 255511201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.101497 # Average percentage of cache occupancy 255611201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.110294 # Average percentage of cache occupancy 255711201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.962100 # Average percentage of cache occupancy 255811201Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1022 9310 # Occupied blocks per task id 255911201Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 176 # Occupied blocks per task id 256011201Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 50213 # Occupied blocks per task id 256111201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::0 61 # Occupied blocks per task id 256211201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::1 427 # Occupied blocks per task id 256311201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::2 684 # Occupied blocks per task id 256411201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::3 1579 # Occupied blocks per task id 256511201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::4 6559 # Occupied blocks per task id 256611201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 256711201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id 256811201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 158 # Occupied blocks per task id 256911201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 257011201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id 257111201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 2614 # Occupied blocks per task id 257211201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 11152 # Occupied blocks per task id 257311201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 36045 # Occupied blocks per task id 257411201Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1022 0.142059 # Percentage of cache occupancy per task id 257511201Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.002686 # Percentage of cache occupancy per task id 257611201Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.766190 # Percentage of cache occupancy per task id 257711201Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 72230268 # Number of tag accesses 257811201Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 72230268 # Number of data accesses 257911201Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::writebacks 2478146 # number of WritebackDirty hits 258011201Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::total 2478146 # number of WritebackDirty hits 258111201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 154381 # number of UpgradeReq hits 258211201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 128604 # number of UpgradeReq hits 258311201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 282985 # number of UpgradeReq hits 258411201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 37860 # number of SCUpgradeReq hits 258511201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 40612 # number of SCUpgradeReq hits 258611201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 78472 # number of SCUpgradeReq hits 258711201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 167086 # number of ReadExReq hits 258811201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 187378 # number of ReadExReq hits 258911201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 354464 # number of ReadExReq hits 259011201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 5729 # number of ReadSharedReq hits 259111201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 3917 # number of ReadSharedReq hits 259211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 604815 # number of ReadSharedReq hits 259311201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 555526 # number of ReadSharedReq hits 259411201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 312245 # number of ReadSharedReq hits 259511201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6550 # number of ReadSharedReq hits 259611201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 4876 # number of ReadSharedReq hits 259711201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 643471 # number of ReadSharedReq hits 259811201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 544206 # number of ReadSharedReq hits 259911201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 332267 # number of ReadSharedReq hits 260011201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::total 3013602 # number of ReadSharedReq hits 260111201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 5729 # number of demand (read+write) hits 260211201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 3917 # number of demand (read+write) hits 260311201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 604815 # number of demand (read+write) hits 260411201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 722612 # number of demand (read+write) hits 260511201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.l2cache.prefetcher 312245 # number of demand (read+write) hits 260611201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 6550 # number of demand (read+write) hits 260711201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 4876 # number of demand (read+write) hits 260811201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 643471 # number of demand (read+write) hits 260911201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 731584 # number of demand (read+write) hits 261011201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.l2cache.prefetcher 332267 # number of demand (read+write) hits 261111201Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 3368066 # number of demand (read+write) hits 261211201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 5729 # number of overall hits 261311201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 3917 # number of overall hits 261411201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 604815 # number of overall hits 261511201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 722612 # number of overall hits 261611201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.l2cache.prefetcher 312245 # number of overall hits 261711201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 6550 # number of overall hits 261811201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 4876 # number of overall hits 261911201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 643471 # number of overall hits 262011201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 731584 # number of overall hits 262111201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.l2cache.prefetcher 332267 # number of overall hits 262211201Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 3368066 # number of overall hits 262311201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 61102 # number of UpgradeReq misses 262411201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 58240 # number of UpgradeReq misses 262511201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 119342 # number of UpgradeReq misses 262611201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 10859 # number of SCUpgradeReq misses 262711201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 11400 # number of SCUpgradeReq misses 262811201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 22259 # number of SCUpgradeReq misses 262911201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 464077 # number of ReadExReq misses 263011201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 119615 # number of ReadExReq misses 263111201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 583692 # number of ReadExReq misses 263211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 662 # number of ReadSharedReq misses 263311201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 653 # number of ReadSharedReq misses 263411201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 56835 # number of ReadSharedReq misses 263511201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 93190 # number of ReadSharedReq misses 263611201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 142344 # number of ReadSharedReq misses 263711201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.dtb.walker 930 # number of ReadSharedReq misses 263811201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.itb.walker 967 # number of ReadSharedReq misses 263911201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 47805 # number of ReadSharedReq misses 264011201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 79816 # number of ReadSharedReq misses 264111201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 118522 # number of ReadSharedReq misses 264211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::total 541724 # number of ReadSharedReq misses 264311201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 662 # number of demand (read+write) misses 264411201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 653 # number of demand (read+write) misses 264511201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 56835 # number of demand (read+write) misses 264611201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 557267 # number of demand (read+write) misses 264711201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.l2cache.prefetcher 142344 # number of demand (read+write) misses 264811201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 930 # number of demand (read+write) misses 264911201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.itb.walker 967 # number of demand (read+write) misses 265011201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 47805 # number of demand (read+write) misses 265111201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 199431 # number of demand (read+write) misses 265211201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.l2cache.prefetcher 118522 # number of demand (read+write) misses 265311201Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 1125416 # number of demand (read+write) misses 265411201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 662 # number of overall misses 265511201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 653 # number of overall misses 265611201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 56835 # number of overall misses 265711201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 557267 # number of overall misses 265811201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.l2cache.prefetcher 142344 # number of overall misses 265911201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 930 # number of overall misses 266011201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.itb.walker 967 # number of overall misses 266111201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 47805 # number of overall misses 266211201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 199431 # number of overall misses 266311201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.l2cache.prefetcher 118522 # number of overall misses 266411201Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 1125416 # number of overall misses 266511201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu0.data 1103543500 # number of UpgradeReq miss cycles 266611201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu1.data 1130362500 # number of UpgradeReq miss cycles 266711201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::total 2233906000 # number of UpgradeReq miss cycles 266811201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu0.data 187676500 # number of SCUpgradeReq miss cycles 266911201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu1.data 195172500 # number of SCUpgradeReq miss cycles 267011201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::total 382849000 # number of SCUpgradeReq miss cycles 267111201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu0.data 64543141999 # number of ReadExReq miss cycles 267211201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu1.data 16037903000 # number of ReadExReq miss cycles 267311201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::total 80581044999 # number of ReadExReq miss cycles 267411201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 90596000 # number of ReadSharedReq miss cycles 267511201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 90566500 # number of ReadSharedReq miss cycles 267611201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.inst 7555639500 # number of ReadSharedReq miss cycles 267711201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.data 12682874000 # number of ReadSharedReq miss cycles 267811201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 22835971280 # number of ReadSharedReq miss cycles 267911201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 127343000 # number of ReadSharedReq miss cycles 268011201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 132126000 # number of ReadSharedReq miss cycles 268111201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.inst 6369869500 # number of ReadSharedReq miss cycles 268211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.data 10891833000 # number of ReadSharedReq miss cycles 268311201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 18778961423 # number of ReadSharedReq miss cycles 268411201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::total 79555780203 # number of ReadSharedReq miss cycles 268511201Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.dtb.walker 90596000 # number of demand (read+write) miss cycles 268611201Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.itb.walker 90566500 # number of demand (read+write) miss cycles 268711201Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.inst 7555639500 # number of demand (read+write) miss cycles 268811201Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.data 77226015999 # number of demand (read+write) miss cycles 268911201Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 22835971280 # number of demand (read+write) miss cycles 269011201Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.dtb.walker 127343000 # number of demand (read+write) miss cycles 269111201Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.itb.walker 132126000 # number of demand (read+write) miss cycles 269211201Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.inst 6369869500 # number of demand (read+write) miss cycles 269311201Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.data 26929736000 # number of demand (read+write) miss cycles 269411201Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 18778961423 # number of demand (read+write) miss cycles 269511201Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::total 160136825202 # number of demand (read+write) miss cycles 269611201Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.dtb.walker 90596000 # number of overall miss cycles 269711201Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.itb.walker 90566500 # number of overall miss cycles 269811201Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.inst 7555639500 # number of overall miss cycles 269911201Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.data 77226015999 # number of overall miss cycles 270011201Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 22835971280 # number of overall miss cycles 270111201Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.dtb.walker 127343000 # number of overall miss cycles 270211201Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.itb.walker 132126000 # number of overall miss cycles 270311201Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.inst 6369869500 # number of overall miss cycles 270411201Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.data 26929736000 # number of overall miss cycles 270511201Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 18778961423 # number of overall miss cycles 270611201Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::total 160136825202 # number of overall miss cycles 270711201Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 2478146 # number of WritebackDirty accesses(hits+misses) 270811201Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::total 2478146 # number of WritebackDirty accesses(hits+misses) 270911201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 215483 # number of UpgradeReq accesses(hits+misses) 271011201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 186844 # number of UpgradeReq accesses(hits+misses) 271111201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 402327 # number of UpgradeReq accesses(hits+misses) 271211201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 48719 # number of SCUpgradeReq accesses(hits+misses) 271311201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 52012 # number of SCUpgradeReq accesses(hits+misses) 271411201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 100731 # number of SCUpgradeReq accesses(hits+misses) 271511201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 631163 # number of ReadExReq accesses(hits+misses) 271611201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 306993 # number of ReadExReq accesses(hits+misses) 271711201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 938156 # number of ReadExReq accesses(hits+misses) 271811201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 6391 # number of ReadSharedReq accesses(hits+misses) 271911201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 4570 # number of ReadSharedReq accesses(hits+misses) 272011201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 661650 # number of ReadSharedReq accesses(hits+misses) 272111201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 648716 # number of ReadSharedReq accesses(hits+misses) 272211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 454589 # number of ReadSharedReq accesses(hits+misses) 272311201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 7480 # number of ReadSharedReq accesses(hits+misses) 272411201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 5843 # number of ReadSharedReq accesses(hits+misses) 272511201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 691276 # number of ReadSharedReq accesses(hits+misses) 272611201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 624022 # number of ReadSharedReq accesses(hits+misses) 272711201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 450789 # number of ReadSharedReq accesses(hits+misses) 272811201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::total 3555326 # number of ReadSharedReq accesses(hits+misses) 272911201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 6391 # number of demand (read+write) accesses 273011201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 4570 # number of demand (read+write) accesses 273111201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 661650 # number of demand (read+write) accesses 273211201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 1279879 # number of demand (read+write) accesses 273311201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.l2cache.prefetcher 454589 # number of demand (read+write) accesses 273411201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 7480 # number of demand (read+write) accesses 273511201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 5843 # number of demand (read+write) accesses 273611201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 691276 # number of demand (read+write) accesses 273711201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 931015 # number of demand (read+write) accesses 273811201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.l2cache.prefetcher 450789 # number of demand (read+write) accesses 273911201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 4493482 # number of demand (read+write) accesses 274011201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 6391 # number of overall (read+write) accesses 274111201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 4570 # number of overall (read+write) accesses 274211201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 661650 # number of overall (read+write) accesses 274311201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 1279879 # number of overall (read+write) accesses 274411201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.l2cache.prefetcher 454589 # number of overall (read+write) accesses 274511201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 7480 # number of overall (read+write) accesses 274611201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 5843 # number of overall (read+write) accesses 274711201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 691276 # number of overall (read+write) accesses 274811201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 931015 # number of overall (read+write) accesses 274911201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.l2cache.prefetcher 450789 # number of overall (read+write) accesses 275011201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 4493482 # number of overall (read+write) accesses 275111201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.283558 # miss rate for UpgradeReq accesses 275211201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.311704 # miss rate for UpgradeReq accesses 275311201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.296629 # miss rate for UpgradeReq accesses 275411201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.222890 # miss rate for SCUpgradeReq accesses 275511201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.219180 # miss rate for SCUpgradeReq accesses 275611201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.220975 # miss rate for SCUpgradeReq accesses 275711201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.735273 # miss rate for ReadExReq accesses 275811201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.389634 # miss rate for ReadExReq accesses 275911201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.622169 # miss rate for ReadExReq accesses 276011201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.103583 # miss rate for ReadSharedReq accesses 276111201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.142888 # miss rate for ReadSharedReq accesses 276211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.085899 # miss rate for ReadSharedReq accesses 276311201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.143653 # miss rate for ReadSharedReq accesses 276411201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.313127 # miss rate for ReadSharedReq accesses 276511201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.124332 # miss rate for ReadSharedReq accesses 276611201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.165497 # miss rate for ReadSharedReq accesses 276711201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.069155 # miss rate for ReadSharedReq accesses 276811201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.127906 # miss rate for ReadSharedReq accesses 276911201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.262921 # miss rate for ReadSharedReq accesses 277011201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.152370 # miss rate for ReadSharedReq accesses 277111201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.103583 # miss rate for demand accesses 277211201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.142888 # miss rate for demand accesses 277311201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.085899 # miss rate for demand accesses 277411201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.435406 # miss rate for demand accesses 277511201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.313127 # miss rate for demand accesses 277611201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.124332 # miss rate for demand accesses 277711201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.165497 # miss rate for demand accesses 277811201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.069155 # miss rate for demand accesses 277911201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.214208 # miss rate for demand accesses 278011201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.262921 # miss rate for demand accesses 278111201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.250455 # miss rate for demand accesses 278211201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.103583 # miss rate for overall accesses 278311201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.142888 # miss rate for overall accesses 278411201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.085899 # miss rate for overall accesses 278511201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.435406 # miss rate for overall accesses 278611201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.313127 # miss rate for overall accesses 278711201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.124332 # miss rate for overall accesses 278811201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.165497 # miss rate for overall accesses 278911201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.069155 # miss rate for overall accesses 279011201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.214208 # miss rate for overall accesses 279111201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.262921 # miss rate for overall accesses 279211201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.250455 # miss rate for overall accesses 279311201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu0.data 18060.677228 # average UpgradeReq miss latency 279411201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu1.data 19408.696772 # average UpgradeReq miss latency 279511201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::total 18718.523236 # average UpgradeReq miss latency 279611201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 17283.037112 # average SCUpgradeReq miss latency 279711201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 17120.394737 # average SCUpgradeReq miss latency 279811201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::total 17199.739431 # average SCUpgradeReq miss latency 279911201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu0.data 139078.519295 # average ReadExReq miss latency 280011201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu1.data 134079.362956 # average ReadExReq miss latency 280111201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::total 138054.050765 # average ReadExReq miss latency 280211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 136851.963746 # average ReadSharedReq miss latency 280311201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 138692.955590 # average ReadSharedReq miss latency 280411201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 132939.904988 # average ReadSharedReq miss latency 280511201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136096.941732 # average ReadSharedReq miss latency 280611201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 160428.056539 # average ReadSharedReq miss latency 280711201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 136927.956989 # average ReadSharedReq miss latency 280811201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 136634.953464 # average ReadSharedReq miss latency 280911201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 133246.930237 # average ReadSharedReq miss latency 281011201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 136461.774582 # average ReadSharedReq miss latency 281111201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 158442.832748 # average ReadSharedReq miss latency 281211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::total 146856.665392 # average ReadSharedReq miss latency 281311201Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.dtb.walker 136851.963746 # average overall miss latency 281411201Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.itb.walker 138692.955590 # average overall miss latency 281511201Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.inst 132939.904988 # average overall miss latency 281611201Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.data 138579.919498 # average overall miss latency 281711201Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 160428.056539 # average overall miss latency 281811201Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.dtb.walker 136927.956989 # average overall miss latency 281911201Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.itb.walker 136634.953464 # average overall miss latency 282011201Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.inst 133246.930237 # average overall miss latency 282111201Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.data 135032.848454 # average overall miss latency 282211201Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 158442.832748 # average overall miss latency 282311201Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::total 142291.228490 # average overall miss latency 282411201Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.dtb.walker 136851.963746 # average overall miss latency 282511201Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.itb.walker 138692.955590 # average overall miss latency 282611201Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.inst 132939.904988 # average overall miss latency 282711201Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.data 138579.919498 # average overall miss latency 282811201Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 160428.056539 # average overall miss latency 282911201Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.dtb.walker 136927.956989 # average overall miss latency 283011201Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.itb.walker 136634.953464 # average overall miss latency 283111201Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.inst 133246.930237 # average overall miss latency 283211201Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.data 135032.848454 # average overall miss latency 283311201Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 158442.832748 # average overall miss latency 283411201Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::total 142291.228490 # average overall miss latency 283511201Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_mshrs 1036 # number of cycles access was blocked 283610515SAli.Saidi@ARM.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 283711201Sandreas.hansson@arm.comsystem.l2c.blocked::no_mshrs 8 # number of cycles access was blocked 283810515SAli.Saidi@ARM.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 283911201Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs 129.500000 # average number of cycles each access was blocked 284010515SAli.Saidi@ARM.comsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 284110515SAli.Saidi@ARM.comsystem.l2c.fast_writes 0 # number of fast writes performed 284210515SAli.Saidi@ARM.comsystem.l2c.cache_copies 0 # number of cache copies performed 284311201Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 823102 # number of writebacks 284411201Sandreas.hansson@arm.comsystem.l2c.writebacks::total 823102 # number of writebacks 284511201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.inst 112 # number of ReadSharedReq MSHR hits 284611201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.data 15 # number of ReadSharedReq MSHR hits 284711201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.inst 123 # number of ReadSharedReq MSHR hits 284811201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.data 13 # number of ReadSharedReq MSHR hits 284911201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::total 263 # number of ReadSharedReq MSHR hits 285011201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu0.inst 112 # number of demand (read+write) MSHR hits 285111201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu0.data 15 # number of demand (read+write) MSHR hits 285211201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.inst 123 # number of demand (read+write) MSHR hits 285311201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.data 13 # number of demand (read+write) MSHR hits 285411201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::total 263 # number of demand (read+write) MSHR hits 285511201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu0.inst 112 # number of overall MSHR hits 285611201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu0.data 15 # number of overall MSHR hits 285711201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.inst 123 # number of overall MSHR hits 285811201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.data 13 # number of overall MSHR hits 285911201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::total 263 # number of overall MSHR hits 286011201Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_misses::writebacks 35269 # number of CleanEvict MSHR misses 286111201Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_misses::total 35269 # number of CleanEvict MSHR misses 286211201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu0.data 61102 # number of UpgradeReq MSHR misses 286311201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu1.data 58240 # number of UpgradeReq MSHR misses 286411201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::total 119342 # number of UpgradeReq MSHR misses 286511201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu0.data 10859 # number of SCUpgradeReq MSHR misses 286611201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11400 # number of SCUpgradeReq MSHR misses 286711201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::total 22259 # number of SCUpgradeReq MSHR misses 286811201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu0.data 464077 # number of ReadExReq MSHR misses 286911201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu1.data 119615 # number of ReadExReq MSHR misses 287011201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::total 583692 # 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mshr miss rate for ReadSharedReq accesses 299111201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.127885 # mshr miss rate for ReadSharedReq accesses 299211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.262921 # mshr miss rate for ReadSharedReq accesses 299311201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::total 0.152296 # mshr miss rate for ReadSharedReq accesses 299411201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.103583 # mshr miss rate for demand accesses 299511201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.142888 # mshr miss rate for demand accesses 299611201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.085730 # mshr miss rate for demand accesses 299711201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.data 0.435394 # mshr miss rate for demand accesses 299811201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.313127 # mshr miss rate for demand accesses 299911201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.124332 # mshr miss rate for demand accesses 300011201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.165497 # mshr miss rate for demand accesses 300111201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.068977 # mshr miss rate for demand accesses 300211201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.data 0.214194 # mshr miss rate for demand accesses 300311201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.262921 # mshr miss rate for demand accesses 300411201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::total 0.250397 # mshr miss rate for demand accesses 300511201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.103583 # mshr miss rate for overall accesses 300611201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.142888 # mshr miss rate for overall accesses 300711201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.085730 # mshr miss rate for overall accesses 300811201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.data 0.435394 # mshr miss rate for overall accesses 300911201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.313127 # mshr miss rate for overall accesses 301011201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.124332 # mshr miss rate for overall accesses 301111201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.165497 # mshr miss rate for overall accesses 301211201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.068977 # mshr miss rate for overall accesses 301311201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.data 0.214194 # mshr miss rate for overall accesses 301411201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.262921 # mshr miss rate for overall accesses 301511201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::total 0.250397 # mshr miss rate for overall accesses 301611201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73405.101388 # average UpgradeReq mshr miss latency 301711201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73447.407332 # average UpgradeReq mshr miss latency 301811201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 73425.747080 # average UpgradeReq mshr miss latency 301911201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76522.838199 # average SCUpgradeReq mshr miss latency 302011201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76478.421053 # average SCUpgradeReq mshr miss latency 302111201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76500.089851 # average SCUpgradeReq mshr miss latency 302211201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129078.519295 # average ReadExReq mshr miss latency 302311201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 124079.362956 # average ReadExReq mshr miss latency 302411201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 128054.050765 # average ReadExReq mshr miss latency 302511201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 126851.963746 # average ReadSharedReq mshr miss latency 302611201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 128692.955590 # average ReadSharedReq mshr miss latency 302711201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 122985.737708 # average ReadSharedReq mshr miss latency 302811201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126097.370539 # average ReadSharedReq mshr miss latency 302911201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 150428.056539 # average ReadSharedReq mshr miss latency 303011201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 126927.956989 # average ReadSharedReq mshr miss latency 303111201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 126634.953464 # average ReadSharedReq mshr miss latency 303211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123319.428715 # average ReadSharedReq mshr miss latency 303311201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 126467.494956 # average ReadSharedReq mshr miss latency 303411201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148442.832748 # average ReadSharedReq mshr miss latency 303511201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::total 136875.285945 # average ReadSharedReq mshr miss latency 303611201Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 126851.963746 # average overall mshr miss latency 303711201Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128692.955590 # average overall mshr miss latency 303811201Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122985.737708 # average overall mshr miss latency 303911201Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 128580.058033 # average overall mshr miss latency 304011201Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 150428.056539 # average overall mshr miss latency 304111201Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 126927.956989 # average overall mshr miss latency 304211201Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 126634.953464 # average overall mshr miss latency 304311201Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123319.428715 # average overall mshr miss latency 304411201Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 125035.044479 # average overall mshr miss latency 304511201Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148442.832748 # average overall mshr miss latency 304611201Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 132299.122166 # average overall mshr miss latency 304711201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 126851.963746 # average overall mshr miss latency 304811201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128692.955590 # average overall mshr miss latency 304911201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122985.737708 # average overall mshr miss latency 305011201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 128580.058033 # average overall mshr miss latency 305111201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 150428.056539 # average overall mshr miss latency 305211201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 126927.956989 # average overall mshr miss latency 305311201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 126634.953464 # average overall mshr miss latency 305411201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123319.428715 # average overall mshr miss latency 305511201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 125035.044479 # average overall mshr miss latency 305611201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148442.832748 # average overall mshr miss latency 305711201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 132299.122166 # average overall mshr miss latency 305811201Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average ReadReq mshr uncacheable latency 305911201Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154383.299498 # average ReadReq mshr uncacheable latency 306011201Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111728.260870 # average ReadReq mshr uncacheable latency 306111201Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 159070.933014 # average ReadReq mshr uncacheable latency 306211201Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131241.202012 # average ReadReq mshr uncacheable latency 306311201Sandreas.hansson@arm.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 153993.698975 # average WriteReq mshr uncacheable latency 306411201Sandreas.hansson@arm.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162871.815452 # average WriteReq mshr uncacheable latency 306511201Sandreas.hansson@arm.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::total 158558.142321 # average WriteReq mshr uncacheable latency 306611201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average overall mshr uncacheable latency 306711201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 154180.133718 # average overall mshr uncacheable latency 306811201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111728.260870 # average overall mshr uncacheable latency 306911201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 160896.324480 # average overall mshr uncacheable latency 307011201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::total 139282.030687 # average overall mshr uncacheable latency 307110515SAli.Saidi@ARM.comsystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 307211201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 90049 # Transaction distribution 307311201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 640443 # Transaction distribution 307411201Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 37563 # Transaction distribution 307511201Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 37563 # Transaction distribution 307611201Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty 930050 # Transaction distribution 307711201Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 190296 # Transaction distribution 307811201Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 413026 # Transaction distribution 307911201Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 280293 # Transaction distribution 308011201Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 150977 # Transaction distribution 308111201Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution 308211201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 593740 # Transaction distribution 308311201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 574320 # Transaction distribution 308411201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 550394 # Transaction distribution 308511201Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 106981 # Transaction distribution 308611201Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 106981 # Transaction distribution 308711201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122912 # Packet count per connected master and slave (bytes) 308810585Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) 308911201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 22290 # Packet count per connected master and slave (bytes) 309011201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4211327 # Packet count per connected master and slave (bytes) 309111201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 4356581 # Packet count per connected master and slave (bytes) 309211201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 343179 # Packet count per connected master and slave (bytes) 309311201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 343179 # Packet count per connected master and slave (bytes) 309411201Sandreas.hansson@arm.comsystem.membus.pkt_count::total 4699760 # Packet count per connected master and slave (bytes) 309511201Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155927 # Cumulative packet size per connected master and slave (bytes) 309610585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) 309711201Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 44580 # Cumulative packet size per connected master and slave (bytes) 309811201Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 127415488 # Cumulative packet size per connected master and slave (bytes) 309911201Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 127617319 # Cumulative packet size per connected master and slave (bytes) 310011201Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7277312 # Cumulative packet size per connected master and slave (bytes) 310111201Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7277312 # Cumulative packet size per connected master and slave (bytes) 310211201Sandreas.hansson@arm.comsystem.membus.pkt_size::total 134894631 # Cumulative packet size per connected master and slave (bytes) 310311201Sandreas.hansson@arm.comsystem.membus.snoops 564682 # Total snoops (count) 310411201Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 3194785 # Request fanout histogram 310510585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 310610585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 310710585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 310810585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 310911201Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 3194785 100.00% 100.00% # Request fanout histogram 311010585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 311110585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 311210585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 311310585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 311411201Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 3194785 # Request fanout histogram 311511201Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 109901497 # Layer occupancy (ticks) 311610585Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 311710892Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks) 311810585Sandreas.hansson@arm.comsystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 311911201Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 18632000 # Layer occupancy (ticks) 312010585Sandreas.hansson@arm.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 312111201Sandreas.hansson@arm.comsystem.membus.reqLayer5.occupancy 6680198838 # Layer occupancy (ticks) 312210585Sandreas.hansson@arm.comsystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 312311201Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 6549107858 # Layer occupancy (ticks) 312410585Sandreas.hansson@arm.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 312511201Sandreas.hansson@arm.comsystem.membus.respLayer3.occupancy 229362666 # Layer occupancy (ticks) 312610585Sandreas.hansson@arm.comsystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 312711239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 312811239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 312911239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 313011239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 313111239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 313211239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 313310515SAli.Saidi@ARM.comsystem.realview.ethernet.txBytes 966 # Bytes Transmitted 313410515SAli.Saidi@ARM.comsystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 313510515SAli.Saidi@ARM.comsystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 313610515SAli.Saidi@ARM.comsystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 313710515SAli.Saidi@ARM.comsystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 313810515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 313910515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 314010515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 314110515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 314211201Sandreas.hansson@arm.comsystem.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 314310515SAli.Saidi@ARM.comsystem.realview.ethernet.totPackets 3 # Total Packets 314410515SAli.Saidi@ARM.comsystem.realview.ethernet.totBytes 966 # Total Bytes 314510515SAli.Saidi@ARM.comsystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 314611201Sandreas.hansson@arm.comsystem.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 314710515SAli.Saidi@ARM.comsystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 314810515SAli.Saidi@ARM.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 314910515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 315010515SAli.Saidi@ARM.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 315110515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 315210515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 315310515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 315410515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 315510515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 315610515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 315710515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 315810515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 315910515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 316010515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 316110515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 316210515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 316310515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 316410515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 316510515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 316610515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 316710515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 316810515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 316910515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 317010515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 317110515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 317210515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 317310515SAli.Saidi@ARM.comsystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 317410515SAli.Saidi@ARM.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 317511239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 317611239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 317711239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 317811239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 317911201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_requests 11369480 # Total number of requests made to the snoop filter. 318011201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 6166084 # Number of requests hitting in the snoop filter with a single holder of the requested data. 318111201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 1983565 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 318211201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 99756 # Total number of snoops made to the snoop filter. 318311201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 89163 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 318411201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 10593 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 318511201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 90051 # Transaction distribution 318611201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 4379282 # Transaction distribution 318711201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 37563 # Transaction distribution 318811201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 37563 # Transaction distribution 318911201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 3408225 # Transaction distribution 319011201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::CleanEvict 1479469 # Transaction distribution 319111201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 686639 # Transaction distribution 319211201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 358765 # Transaction distribution 319311201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 1045403 # Transaction distribution 319411201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeFailReq 133 # Transaction distribution 319511201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution 319611201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 1072017 # Transaction distribution 319711201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 1072017 # Transaction distribution 319811201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 4296486 # Transaction distribution 319911201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::InvalidateReq 106981 # Transaction distribution 320011201Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8273345 # Packet count per connected master and slave (bytes) 320111201Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7109938 # Packet count per connected master and slave (bytes) 320211201Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 15383283 # Packet count per connected master and slave (bytes) 320311201Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 249443752 # Cumulative packet size per connected master and slave (bytes) 320411201Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 200422911 # Cumulative packet size per connected master and slave (bytes) 320511201Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 449866663 # Cumulative packet size per connected master and slave (bytes) 320611201Sandreas.hansson@arm.comsystem.toL2Bus.snoops 2689125 # Total snoops (count) 320711201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 7811601 # Request fanout histogram 320811201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 0.375584 # Request fanout histogram 320911201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.487066 # Request fanout histogram 321010515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 321111201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::0 4888281 62.58% 62.58% # Request fanout histogram 321211201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 2912727 37.29% 99.86% # Request fanout histogram 321311201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 10593 0.14% 100.00% # Request fanout histogram 321410515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 321511138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 321610515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 321711201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 7811601 # Request fanout histogram 321811201Sandreas.hansson@arm.comsystem.toL2Bus.reqLayer0.occupancy 8585712934 # Layer occupancy (ticks) 321910515SAli.Saidi@ARM.comsystem.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 322011201Sandreas.hansson@arm.comsystem.toL2Bus.snoopLayer0.occupancy 2584443 # Layer occupancy (ticks) 322110515SAli.Saidi@ARM.comsystem.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 322211201Sandreas.hansson@arm.comsystem.toL2Bus.respLayer0.occupancy 4648327252 # Layer occupancy (ticks) 322310515SAli.Saidi@ARM.comsystem.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 322411201Sandreas.hansson@arm.comsystem.toL2Bus.respLayer1.occupancy 4065319209 # Layer occupancy (ticks) 322510515SAli.Saidi@ARM.comsystem.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 322610515SAli.Saidi@ARM.com 322710515SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 3228