xref: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 47.411962                       # Number of seconds simulated
sim_ticks                                47411962285000                       # Number of ticks simulated
final_tick                               47411962285000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 167928                       # Simulator instruction rate (inst/s)
host_op_rate                                   197524                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             9366197696                       # Simulator tick rate (ticks/s)
host_mem_usage                                 719564                       # Number of bytes of host memory used
host_seconds                                  5062.03                       # Real time elapsed on the host
sim_insts                                   850056300                       # Number of instructions simulated
sim_ops                                     999871495                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker        75328                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker        71168                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          7498816                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         38111304                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher     10728384                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker        51264                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker        47808                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          2878784                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         12174608                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher      7747264                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        431104                       # Number of bytes read from this memory
system.physmem.bytes_read::total             79815832                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      7498816                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      2878784                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total        10377600                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     62807296                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::total          62827880                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         1177                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         1112                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst            117169                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            595502                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       167631                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker          801                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker          747                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             44981                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            190241                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher       121051                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6736                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1247148                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          981364                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               983938                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          1589                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          1501                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              158163                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              803833                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher       226280                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          1081                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          1008                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               60719                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              256783                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       163403                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             9093                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1683453                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         158163                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          60719                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             218881                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1324714                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                434                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1325148                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1324714                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         1589                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         1501                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             158163                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             804267                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher       226280                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         1081                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         1008                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              60719                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             256784                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       163403                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            9093                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3008602                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1247148                       # Number of read requests accepted
system.physmem.writeReqs                       983938                       # Number of write requests accepted
system.physmem.readBursts                     1247148                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     983938                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 79775360                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     42112                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  62826240                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  79815832                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               62827880                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      658                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2247                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs         218244                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               71187                       # Per bank write bursts
system.physmem.perBankRdBursts::1               77028                       # Per bank write bursts
system.physmem.perBankRdBursts::2               72273                       # Per bank write bursts
system.physmem.perBankRdBursts::3               78219                       # Per bank write bursts
system.physmem.perBankRdBursts::4               70385                       # Per bank write bursts
system.physmem.perBankRdBursts::5               81119                       # Per bank write bursts
system.physmem.perBankRdBursts::6               72267                       # Per bank write bursts
system.physmem.perBankRdBursts::7               76746                       # Per bank write bursts
system.physmem.perBankRdBursts::8               71370                       # Per bank write bursts
system.physmem.perBankRdBursts::9              123762                       # Per bank write bursts
system.physmem.perBankRdBursts::10              72044                       # Per bank write bursts
system.physmem.perBankRdBursts::11              80747                       # Per bank write bursts
system.physmem.perBankRdBursts::12              73100                       # Per bank write bursts
system.physmem.perBankRdBursts::13              79351                       # Per bank write bursts
system.physmem.perBankRdBursts::14              74612                       # Per bank write bursts
system.physmem.perBankRdBursts::15              72280                       # Per bank write bursts
system.physmem.perBankWrBursts::0               58860                       # Per bank write bursts
system.physmem.perBankWrBursts::1               62909                       # Per bank write bursts
system.physmem.perBankWrBursts::2               59749                       # Per bank write bursts
system.physmem.perBankWrBursts::3               64358                       # Per bank write bursts
system.physmem.perBankWrBursts::4               59245                       # Per bank write bursts
system.physmem.perBankWrBursts::5               66477                       # Per bank write bursts
system.physmem.perBankWrBursts::6               59553                       # Per bank write bursts
system.physmem.perBankWrBursts::7               62082                       # Per bank write bursts
system.physmem.perBankWrBursts::8               58790                       # Per bank write bursts
system.physmem.perBankWrBursts::9               60994                       # Per bank write bursts
system.physmem.perBankWrBursts::10              60508                       # Per bank write bursts
system.physmem.perBankWrBursts::11              63849                       # Per bank write bursts
system.physmem.perBankWrBursts::12              60193                       # Per bank write bursts
system.physmem.perBankWrBursts::13              63756                       # Per bank write bursts
system.physmem.perBankWrBursts::14              60310                       # Per bank write bursts
system.physmem.perBankWrBursts::15              60027                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          30                       # Number of times write queue was full causing retry
system.physmem.totGap                    47411960356500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1247118                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 981364                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    795503                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    313068                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     30154                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     22514                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                     19326                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                     17861                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                     16010                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     13834                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     11987                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      2659                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1157                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      695                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      515                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      367                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      206                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      171                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      146                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      131                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       98                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       69                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       10                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    14920                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    17590                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    38389                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    48185                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    52683                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    54849                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    56160                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    59815                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    60639                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    63775                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    62891                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    64447                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    62663                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    63620                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    68672                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    63414                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    59849                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    57038                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1401                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      972                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      930                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      645                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      537                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      549                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      489                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      454                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      550                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      413                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      377                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      350                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      279                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      406                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      433                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      383                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      292                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      288                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      333                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      315                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      273                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      211                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      286                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      168                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      147                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      136                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      123                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      112                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       80                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       59                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       86                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       737647                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      193.317834                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     117.156586                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     253.851861                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         435526     59.04%     59.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       146539     19.87%     78.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        49058      6.65%     85.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        25178      3.41%     88.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        15871      2.15%     91.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        10341      1.40%     92.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         7959      1.08%     93.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         8404      1.14%     94.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        38771      5.26%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         737647                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         55115                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        22.615186                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      363.032286                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-4095          55112     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::24576-28671            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::77824-81919            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           55115                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         55115                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.811122                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.212895                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        7.489514                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23           52725     95.66%     95.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31             682      1.24%     96.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39             764      1.39%     98.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47             154      0.28%     98.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55              76      0.14%     98.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63              61      0.11%     98.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71             472      0.86%     99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79             111      0.20%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87              10      0.02%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95               1      0.00%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103              8      0.01%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119             1      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127             1      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135            31      0.06%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143             2      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151             7      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167             4      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183             3      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::264-271             2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           55115                       # Writes before turning the bus around for reads
system.physmem.totQLat                    32865022462                       # Total ticks spent queuing
system.physmem.totMemAccLat               56236709962                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   6232450000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       26366.05                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  45116.05                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.68                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.33                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.68                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.33                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        23.59                       # Average write queue length when enqueuing
system.physmem.readRowHits                    1009662                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    480836                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   81.00                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  48.98                       # Row buffer hit rate for writes
system.physmem.avgGap                     21250619.81                       # Average gap between requests
system.physmem.pageHitRate                      66.89                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 2808479520                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 1532404500                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                4673861400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               3196149840                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3096718466400                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1173181763970                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           27418066728000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             31700177853630                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.611477                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   45611956984095                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1583189400000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    216810169905                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 2768124240                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1510385250                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                5048596800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               3165006960                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3096718466400                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1175060323800                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           27416418868500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             31700689771950                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.622274                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   45609169557313                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1583189400000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    219597434187                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst          704                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          576                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data            8                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total          1324                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          704                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          576                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total         1280                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           11                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst            9                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             26                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           15                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           12                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               28                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           15                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           12                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           27                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           15                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           12                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              28                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1671                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6846976                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1674                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups              130279608                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         91518189                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          6235368                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            97695080                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               70156250                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            71.811446                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS               15568853                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect           1041049                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                   272738                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               272738                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2         8357                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        77299                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples       272738                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0         272738    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       272738                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples        85656                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 20319.907537                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 18687.643521                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 12933.686898                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535        84887     99.10%     99.10% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071          657      0.77%     99.87% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607           28      0.03%     99.90% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143           42      0.05%     99.95% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679           27      0.03%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215           12      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total        85656                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples    669754704                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0      669754704    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total    669754704                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        77299     90.24%     90.24% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M         8357      9.76%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total        85656                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       272738                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       272738                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        85656                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        85656                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       358394                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    83911764                       # DTB read hits
system.cpu0.dtb.read_misses                    226051                       # DTB read misses
system.cpu0.dtb.write_hits                   74892635                       # DTB write hits
system.cpu0.dtb.write_misses                    46687                       # DTB write misses
system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              38178                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                   1015                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   35474                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     1932                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  8858                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                    11487                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                84137815                       # DTB read accesses
system.cpu0.dtb.write_accesses               74939322                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        158804399                       # DTB hits
system.cpu0.dtb.misses                         272738                       # DTB misses
system.cpu0.dtb.accesses                    159077137                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                    68078                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                68078                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2          722                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        61066                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples        68078                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0          68078    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        68078                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        61788                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 22737.489480                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 21008.732396                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 13692.086470                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-32767        57025     92.29%     92.29% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-65535         3907      6.32%     98.61% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-98303          284      0.46%     99.07% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::98304-131071          503      0.81%     99.89% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-163839           12      0.02%     99.91% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::163840-196607            9      0.01%     99.92% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-229375           25      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::229376-262143            7      0.01%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-294911            3      0.00%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::294912-327679            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-360447            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::360448-393215            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        61788                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples    669040204                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0      669040204    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total    669040204                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        61066     98.83%     98.83% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M          722      1.17%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        61788                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        68078                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        68078                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        61788                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        61788                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       129866                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   232943519                       # ITB inst hits
system.cpu0.itb.inst_misses                     68078                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              38178                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                   1015                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   25164                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                   198596                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               233011597                       # ITB inst accesses
system.cpu0.itb.hits                        232943519                       # DTB hits
system.cpu0.itb.misses                          68078                       # DTB misses
system.cpu0.itb.accesses                    233011597                       # DTB accesses
system.cpu0.numCycles                       944358949                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                  433389926                       # Number of instructions committed
system.cpu0.committedOps                    509312382                       # Number of ops (including micro ops) committed
system.cpu0.discardedOps                     43329563                       # Number of ops (including micro ops) which were discarded before commit
system.cpu0.numFetchSuspends                     4813                       # Number of times Execute suspended instruction fetching
system.cpu0.quiesceCycles                 93880363578                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.cpi                              2.179005                       # CPI: cycles per instruction
system.cpu0.ipc                              0.458925                       # IPC: instructions per cycle
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   13422                       # number of quiesce instructions executed
system.cpu0.tickCycles                      695520331                       # Number of cycles that the object actually ticked
system.cpu0.idleCycles                      248838618                       # Total number of cycles that the object has spent stopped
system.cpu0.dcache.tags.replacements          5405789                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          500.914885                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          150600436                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          5406301                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            27.856465                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       4974406000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   500.914885                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.978349                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.978349                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           75                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          405                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           32                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        320300004                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       320300004                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     77010804                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       77010804                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     69515704                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      69515704                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       254236                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       254236                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       165535                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       165535                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1598340                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      1598340                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1577518                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      1577518                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    146526508                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       146526508                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    146780744                       # number of overall hits
system.cpu0.dcache.overall_hits::total      146780744                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      3243116                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      3243116                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      2266198                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      2266198                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       618205                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       618205                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       821296                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total       821296                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       155401                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       155401                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data       174722                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total       174722                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      5509314                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       5509314                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      6127519                       # number of overall misses
system.cpu0.dcache.overall_misses::total      6127519                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  48375468500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  48375468500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  42499797000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  42499797000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  51670537000                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  51670537000                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2317304500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   2317304500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   3678685500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total   3678685500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      2406500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      2406500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  90875265500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  90875265500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  90875265500                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  90875265500                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     80253920                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     80253920                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     71781902                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     71781902                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       872441                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       872441                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       986831                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total       986831                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1753741                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      1753741                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1752240                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      1752240                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    152035822                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    152035822                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    152908263                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    152908263                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.040411                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.040411                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.031571                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.031571                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.708592                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.708592                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.832256                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.832256                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.088611                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.088611                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.099714                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.099714                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.036237                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.036237                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.040073                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.040073                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14916.354672                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14916.354672                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18753.788063                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 18753.788063                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 62913.416113                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 62913.416113                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14911.773412                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14911.773412                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21054.506588                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21054.506588                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16494.842280                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 16494.842280                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14830.678697                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 14830.678697                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      3720174                       # number of writebacks
system.cpu0.dcache.writebacks::total          3720174                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       395501                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       395501                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       949612                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total       949612                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data           96                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total           96                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        41791                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        41791                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data           77                       # number of StoreCondReq MSHR hits
system.cpu0.dcache.StoreCondReq_mshr_hits::total           77                       # number of StoreCondReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1345113                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      1345113                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1345113                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      1345113                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2847615                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      2847615                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1316586                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      1316586                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       612491                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       612491                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       821200                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total       821200                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       113610                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       113610                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       174645                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total       174645                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      4164201                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      4164201                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      4776692                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      4776692                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        30167                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        30167                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        29885                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        29885                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60052                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60052                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  38218904500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  38218904500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  23577025500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  23577025500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  13456556000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  13456556000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  50843266000                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  50843266000                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1513106500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1513106500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   3501575000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   3501575000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      2054500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2054500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  61795930000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  61795930000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  75252486000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  75252486000                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5426212000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5426212000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5134567500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5134567500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  10560779500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10560779500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.035483                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.035483                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018341                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018341                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.702043                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.702043                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.832159                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.832159                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.064782                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.064782                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.099670                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.099670                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.027390                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.027390                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.031239                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.031239                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13421.373500                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13421.373500                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17907.698775                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17907.698775                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21970.210175                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21970.210175                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 61913.377983                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 61913.377983                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13318.427075                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13318.427075                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20049.672192                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20049.672192                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14839.804803                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14839.804803                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15754.100537                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15754.100537                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 179872.443398                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 179872.443398                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171810.858290                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171810.858290                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 175860.579165                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 175860.579165                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          9471710                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.926461                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          223265309                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          9472222                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            23.570532                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      29829927000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.926461                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999856                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999856                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          346                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           62                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        474947313                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       474947313                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    223265309                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      223265309                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    223265309                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       223265309                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    223265309                       # number of overall hits
system.cpu0.icache.overall_hits::total      223265309                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      9472232                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      9472232                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      9472232                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       9472232                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      9472232                       # number of overall misses
system.cpu0.icache.overall_misses::total      9472232                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  93317915500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  93317915500                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  93317915500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  93317915500                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  93317915500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  93317915500                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    232737541                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    232737541                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    232737541                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    232737541                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    232737541                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    232737541                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.040699                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.040699                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.040699                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.040699                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.040699                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.040699                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9851.734575                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  9851.734575                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9851.734575                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  9851.734575                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9851.734575                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  9851.734575                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      9472232                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      9472232                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      9472232                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      9472232                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      9472232                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      9472232                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        52292                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total        52292                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        52292                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total        52292                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  88581800000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  88581800000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  88581800000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  88581800000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  88581800000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  88581800000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   4777780500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   4777780500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   4777780500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   4777780500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.040699                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.040699                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.040699                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.040699                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.040699                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.040699                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9351.734628                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9351.734628                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9351.734628                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total  9351.734628                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9351.734628                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total  9351.734628                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91367.331523                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 91367.331523                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91367.331523                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 91367.331523                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued      7001248                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      7002240                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit          870                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage       934040                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements         2602937                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16189.396586                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs          26055882                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs         2619045                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            9.948619                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle     27364878000                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks  6164.786775                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    75.653187                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    79.660205                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  5461.877118                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data  3523.510222                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   883.909079                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.376269                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.004618                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.004862                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.333367                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.215058                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.053950                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.988122                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1484                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           72                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14552                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           26                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          652                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          737                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4           69                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           15                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           56                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            1                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          126                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1133                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         5245                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7645                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4          403                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.090576                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.004395                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.888184                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses       499794711                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses      499794711                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       477670                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       164902                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total        642572                       # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks      3720171                       # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total      3720171                       # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data       100086                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total       100086                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        33531                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total        33531                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       842117                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       842117                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      8718803                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      8718803                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2638824                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total      2638824                       # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       235281                       # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total       235281                       # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       477670                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker       164902                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      8718803                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data      3480941                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total       12842316                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       477670                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker       164902                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      8718803                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data      3480941                       # number of overall hits
system.cpu0.l2cache.overall_hits::total      12842316                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        10606                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         7872                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total        18478                       # number of ReadReq misses
system.cpu0.l2cache.Writeback_misses::writebacks            1                       # number of Writeback misses
system.cpu0.l2cache.Writeback_misses::total            1                       # number of Writeback misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       123653                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total       123653                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       141112                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total       141112                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            2                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            2                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data       262527                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total       262527                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       753428                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total       753428                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       934617                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total       934617                       # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       584428                       # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total       584428                       # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        10606                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker         7872                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       753428                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data      1197144                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total      1969050                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        10606                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker         7872                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       753428                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data      1197144                       # number of overall misses
system.cpu0.l2cache.overall_misses::total      1969050                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    328744000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    264590000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total    593334000                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   2720179500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total   2720179500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   2942818999                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   2942818999                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      1986000                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      1986000                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  12019318999                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total  12019318999                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  22377694500                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total  22377694500                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  30534644990                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total  30534644990                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data  47939774000                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::total  47939774000                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    328744000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    264590000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst  22377694500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data  42553963989                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total  65524992489                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    328744000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    264590000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst  22377694500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data  42553963989                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total  65524992489                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       488276                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       172774                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total       661050                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks      3720172                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total      3720172                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       223739                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total       223739                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       174643                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total       174643                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            2                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            2                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1104644                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total      1104644                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      9472231                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      9472231                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      3573441                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total      3573441                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       819709                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::total       819709                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       488276                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       172774                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      9472231                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data      4678085                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total     14811366                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       488276                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       172774                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      9472231                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data      4678085                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total     14811366                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.021721                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.045562                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.027952                       # miss rate for ReadReq accesses
system.cpu0.l2cache.Writeback_miss_rate::writebacks     0.000000                       # miss rate for Writeback accesses
system.cpu0.l2cache.Writeback_miss_rate::total     0.000000                       # miss rate for Writeback accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.552666                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.552666                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.808003                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.808003                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.237658                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.237658                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.079541                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.079541                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.261545                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.261545                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.712970                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.712970                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.021721                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.045562                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.079541                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.255905                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.132942                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.021721                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.045562                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.079541                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.255905                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.132942                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 30996.039977                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 33611.534553                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32110.293322                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21998.491747                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21998.491747                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20854.491461                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20854.491461                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       993000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       993000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 45783.172775                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 45783.172775                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 29701.171844                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 29701.171844                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32670.757102                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32670.757102                       # average ReadSharedReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 82028.537305                       # average InvalidateReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 82028.537305                       # average InvalidateReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 30996.039977                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 33611.534553                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 29701.171844                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35546.236701                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 33277.465016                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 30996.039977                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 33611.534553                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 29701.171844                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35546.236701                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 33277.465016                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks      1330364                       # number of writebacks
system.cpu0.l2cache.writebacks::total         1330364                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker            2                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total            2                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         5123                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         5123                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           12                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           12                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          628                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          628                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data            2                       # number of InvalidateReq MSHR hits
system.cpu0.l2cache.InvalidateReq_mshr_hits::total            2                       # number of InvalidateReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker            2                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           12                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         5751                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         5765                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker            2                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           12                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         5751                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         5765                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        10606                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         7870                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total        18476                       # number of ReadReq MSHR misses
system.cpu0.l2cache.Writeback_mshr_misses::writebacks            1                       # number of Writeback MSHR misses
system.cpu0.l2cache.Writeback_mshr_misses::total            1                       # number of Writeback MSHR misses
system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks       106526                       # number of CleanEvict MSHR misses
system.cpu0.l2cache.CleanEvict_mshr_misses::total       106526                       # number of CleanEvict MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       667181                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       667181                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       123653                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total       123653                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       141112                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       141112                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            2                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            2                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       257404                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total       257404                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       753416                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       753416                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       933989                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       933989                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       584426                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::total       584426                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        10606                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         7870                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       753416                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1191393                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total      1963285                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        10606                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         7870                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       753416                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1191393                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       667181                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total      2630466                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        52292                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        30167                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        82459                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        29885                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        29885                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        52292                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60052                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total       112344                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    265108000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    217332000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    482440000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  24692938914                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  24692938914                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   2507267996                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   2507267996                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2173502999                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   2173502999                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1716000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1716000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   9909956499                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   9909956499                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  17856881500                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  17856881500                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  24870500990                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  24870500990                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  44433114500                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  44433114500                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    265108000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    217332000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  17856881500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  34780457489                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total  53119778989                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    265108000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    217332000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  17856881500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  34780457489                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  24692938914                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  77812717903                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   4359444500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5184743000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   9544187500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   4910404000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   4910404000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   4359444500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  10095147000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  14454591500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.021721                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.045551                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.027949                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for Writeback accesses
system.cpu0.l2cache.Writeback_mshr_miss_rate::total     0.000000                       # mshr miss rate for Writeback accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.552666                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.552666                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.808003                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.808003                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.233020                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.233020                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.079539                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.079539                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.261370                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.261370                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.712968                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.712968                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.021721                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.045551                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.079539                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.254675                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.132553                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.021721                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.045551                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.079539                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.254675                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.177598                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24996.039977                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 27615.247776                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26111.712492                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 37010.854497                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 37010.854497                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20276.645096                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20276.645096                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15402.680134                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15402.680134                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       858000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       858000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38499.621214                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38499.621214                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 23701.224158                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 23701.224158                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26628.258994                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26628.258994                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 76028.640923                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 76028.640923                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24996.039977                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 27615.247776                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23701.224158                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29193.102099                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27056.580674                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24996.039977                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 27615.247776                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23701.224158                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29193.102099                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 37010.854497                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 29581.343345                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83367.331523                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171868.034607                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 115744.642792                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164309.988288                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164309.988288                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83367.331523                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 168106.757477                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 128663.671402                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq        876246                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp     14005082                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        38305                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        29885                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback      6885213                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict     13979886                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       878417                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq       473566                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       319318                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       460407                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           62                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          105                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq      1465787                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp      1113779                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      9472232                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq      5781099                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq       926693                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp       819709                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     28518742                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     17480007                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       376075                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1070420                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total         47445244                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    609569408                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    544120273                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1382192                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      3906208                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total        1158978081                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                   10243316                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples     41099849                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       1.261354                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.439372                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1          30358253     73.86%     73.86% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2          10741596     26.14%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total      41099849                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy   19306972981                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    182073987                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy  14288744572                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   7674112954                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy    203313475                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy    582176435                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.branchPred.lookups              125904408                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         89122664                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect          5902634                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups            94266188                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits               68486701                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            72.652456                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS               15015861                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect           1004863                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                   261999                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               261999                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         7478                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        69980                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples       261999                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0         261999    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       261999                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples        77458                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 19301.763536                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 17918.383858                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 10994.886931                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-32767        74315     95.94%     95.94% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-65535         2659      3.43%     99.38% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-98303          247      0.32%     99.69% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-131071          165      0.21%     99.91% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-163839           17      0.02%     99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::163840-196607            5      0.01%     99.94% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-229375           16      0.02%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::229376-262143            8      0.01%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-294911           10      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::294912-327679            9      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-360447            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::360448-393215            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-425983            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total        77458                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  -1501931648                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0    -1501931648    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  -1501931648                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        69980     90.35%     90.35% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M         7478      9.65%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total        77458                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       261999                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       261999                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        77458                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        77458                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       339457                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    82663207                       # DTB read hits
system.cpu1.dtb.read_misses                    218762                       # DTB read misses
system.cpu1.dtb.write_hits                   71167787                       # DTB write hits
system.cpu1.dtb.write_misses                    43237                       # DTB write misses
system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              38178                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                   1015                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   35788                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      902                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  6887                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                     9904                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                82881969                       # DTB read accesses
system.cpu1.dtb.write_accesses               71211024                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        153830994                       # DTB hits
system.cpu1.dtb.misses                         261999                       # DTB misses
system.cpu1.dtb.accesses                    154092993                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                    59152                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                59152                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2          461                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        48561                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples        59152                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0          59152    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        59152                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        49022                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 21340.612378                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 19735.982166                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 12453.289543                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-32767        45897     93.63%     93.63% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-65535         2624      5.35%     98.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-98303          160      0.33%     99.30% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::98304-131071          295      0.60%     99.91% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-163839           12      0.02%     99.93% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::163840-196607            9      0.02%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-229375           10      0.02%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::229376-262143            5      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-294911            2      0.00%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::294912-327679            3      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-360447            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::360448-393215            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        49022                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples  -1502514148                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0    -1502514148    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  -1502514148                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        48561     99.06%     99.06% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M          461      0.94%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        49022                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        59152                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        59152                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        49022                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        49022                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       108174                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   225695696                       # ITB inst hits
system.cpu1.itb.inst_misses                     59152                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              38178                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                   1015                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   25916                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                   201769                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               225754848                       # ITB inst accesses
system.cpu1.itb.hits                        225695696                       # DTB hits
system.cpu1.itb.misses                          59152                       # DTB misses
system.cpu1.itb.accesses                    225754848                       # DTB accesses
system.cpu1.numCycles                       837975509                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                  416666374                       # Number of instructions committed
system.cpu1.committedOps                    490559113                       # Number of ops (including micro ops) committed
system.cpu1.discardedOps                     42698463                       # Number of ops (including micro ops) which were discarded before commit
system.cpu1.numFetchSuspends                     4659                       # Number of times Execute suspended instruction fetching
system.cpu1.quiesceCycles                 93986622085                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.cpi                              2.011143                       # CPI: cycles per instruction
system.cpu1.ipc                              0.497230                       # IPC: instructions per cycle
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    5009                       # number of quiesce instructions executed
system.cpu1.tickCycles                      670350336                       # Number of cycles that the object actually ticked
system.cpu1.idleCycles                      167625173                       # Total number of cycles that the object has spent stopped
system.cpu1.dcache.tags.replacements          4806043                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          444.186980                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs          146495712                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs          4806555                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            30.478318                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     8387638822500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   444.186980                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.867553                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.867553                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0          141                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          320                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2           51                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses        309963007                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses       309963007                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data     75874550                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       75874550                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data     66435000                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total      66435000                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data       232604                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total       232604                       # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data       157450                       # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total       157450                       # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1693988                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total      1693988                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1671438                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total      1671438                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data    142309550                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total       142309550                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data    142542154                       # number of overall hits
system.cpu1.dcache.overall_hits::total      142542154                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data      3161753                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total      3161753                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      1996683                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      1996683                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data       552089                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total       552089                       # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data       421817                       # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total       421817                       # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       158395                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total       158395                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data       179133                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total       179133                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      5158436                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       5158436                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      5710525                       # number of overall misses
system.cpu1.dcache.overall_misses::total      5710525                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  43703345000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total  43703345000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  33230827500                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  33230827500                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  13699084500                       # number of WriteLineReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::total  13699084500                       # number of WriteLineReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2222797000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total   2222797000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   3749543500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total   3749543500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      3215500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      3215500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  76934172500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  76934172500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  76934172500                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  76934172500                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data     79036303                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     79036303                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data     68431683                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total     68431683                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       784693                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       784693                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       579267                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total       579267                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1852383                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total      1852383                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1850571                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total      1850571                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data    147467986                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total    147467986                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data    148252679                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total    148252679                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.040004                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.040004                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.029178                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.029178                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.703573                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.703573                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.728191                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total     0.728191                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.085509                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.085509                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.096799                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.096799                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.034980                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.034980                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.038519                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.038519                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13822.504478                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 13822.504478                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16643.016192                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 16643.016192                       # average WriteReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 32476.368899                       # average WriteLineReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 32476.368899                       # average WriteLineReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14033.252312                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14033.252312                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20931.617848                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20931.617848                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14914.243872                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 14914.243872                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13472.346676                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 13472.346676                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks      3028608                       # number of writebacks
system.cpu1.dcache.writebacks::total          3028608                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       352163                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total       352163                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       814004                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total       814004                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data           58                       # number of WriteLineReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::total           58                       # number of WriteLineReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        37997                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        37997                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data           57                       # number of StoreCondReq MSHR hits
system.cpu1.dcache.StoreCondReq_mshr_hits::total           57                       # number of StoreCondReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data      1166167                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total      1166167                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data      1166167                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total      1166167                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2809590                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total      2809590                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1182679                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total      1182679                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       551754                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total       551754                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       421759                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::total       421759                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       120398                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total       120398                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       179076                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total       179076                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data      3992269                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total      3992269                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data      4544023                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total      4544023                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         8249                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total         8249                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         8420                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total         8420                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        16669                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total        16669                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  35216853500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total  35216853500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  19067594000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total  19067594000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  11091696000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  11091696000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  13273963000                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  13273963000                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1514299000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1514299000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   3568894000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   3568894000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      2841500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      2841500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  54284447500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total  54284447500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  65376143500                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total  65376143500                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   1096081500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   1096081500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1226588000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   1226588000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   2322669500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   2322669500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035548                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035548                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.017283                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.017283                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.703146                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.703146                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.728091                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.728091                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.064996                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.064996                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.096768                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.096768                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027072                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.027072                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.030651                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.030651                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12534.516958                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12534.516958                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16122.374710                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16122.374710                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20102.610946                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20102.610946                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 31472.862464                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 31472.862464                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12577.443147                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12577.443147                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19929.493623                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19929.493623                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13597.392235                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13597.392235                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14387.282701                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14387.282701                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 132874.469633                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 132874.469633                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145675.534442                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 145675.534442                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 139340.662307                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 139340.662307                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements          8962341                       # number of replacements
system.cpu1.icache.tags.tagsinuse          506.974355                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs          216525917                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          8962853                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            24.158147                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     8375817756000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   506.974355                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.990184                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.990184                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0          109                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          351                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2           52                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses        459940393                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses       459940393                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst    216525917                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total      216525917                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst    216525917                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total       216525917                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst    216525917                       # number of overall hits
system.cpu1.icache.overall_hits::total      216525917                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      8962853                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      8962853                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      8962853                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       8962853                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      8962853                       # number of overall misses
system.cpu1.icache.overall_misses::total      8962853                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  87475415500                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total  87475415500                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst  87475415500                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total  87475415500                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst  87475415500                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total  87475415500                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst    225488770                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total    225488770                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst    225488770                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total    225488770                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst    225488770                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total    225488770                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.039749                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.039749                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.039749                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.039749                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.039749                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.039749                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9759.773534                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  9759.773534                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9759.773534                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  9759.773534                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9759.773534                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  9759.773534                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      8962853                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total      8962853                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst      8962853                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total      8962853                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst      8962853                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total      8962853                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst           93                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total           93                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst           93                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total           93                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  82993989000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total  82993989000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  82993989000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total  82993989000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  82993989000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total  82993989000                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8742000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8742000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8742000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      8742000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.039749                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.039749                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.039749                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.039749                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.039749                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.039749                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  9259.773534                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  9259.773534                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  9259.773534                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  9259.773534                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  9259.773534                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  9259.773534                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst        94000                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total        94000                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst        94000                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total        94000                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued      6768411                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified      6768469                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit           54                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage       863435                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements         2141720                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       13540.912612                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs          24731326                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs         2157705                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs           11.461866                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle    9851161667500                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks  5143.146487                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    72.763483                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    75.029020                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  4350.990102                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3012.175036                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   886.808482                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.313913                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004441                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.004579                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.265563                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.183849                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.054126                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.826472                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1213                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           83                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14689                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::0            5                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           25                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          401                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          707                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4           75                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            3                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           53                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           26                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            1                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          117                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          662                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         5268                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         8016                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4          626                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.074036                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005066                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.896545                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses       461861904                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses      461861904                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       450787                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       134849                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total        585636                       # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks      3028606                       # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total      3028606                       # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        55878                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total        55878                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        34341                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total        34341                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data       766672                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total       766672                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      8228059                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total      8228059                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2592448                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total      2592448                       # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       167873                       # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total       167873                       # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       450787                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker       134849                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      8228059                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data      3359120                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total       12172815                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       450787                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker       134849                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      8228059                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data      3359120                       # number of overall hits
system.cpu1.l2cache.overall_hits::total      12172815                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        10577                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         7168                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        17745                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       137373                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total       137373                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       144729                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total       144729                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            6                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            6                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data       224779                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total       224779                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       734794                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total       734794                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       888888                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total       888888                       # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       252467                       # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total       252467                       # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        10577                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker         7168                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       734794                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data      1113667                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total      1866206                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        10577                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker         7168                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       734794                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data      1113667                       # number of overall misses
system.cpu1.l2cache.overall_misses::total      1866206                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    295249500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    216312000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total    511561500                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   2960853000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total   2960853000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   2990715499                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   2990715499                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      2750499                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      2750499                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   8344875497                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   8344875497                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  20496216000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total  20496216000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  25619176492                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total  25619176492                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data  11469563500                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::total  11469563500                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    295249500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    216312000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst  20496216000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data  33964051989                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total  54971829489                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    295249500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    216312000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst  20496216000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data  33964051989                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total  54971829489                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       461364                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       142017                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total       603381                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks      3028606                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total      3028606                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       193251                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total       193251                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       179070                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total       179070                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            6                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            6                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data       991451                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total       991451                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      8962853                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total      8962853                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3481336                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total      3481336                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       420340                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total       420340                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       461364                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       142017                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      8962853                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data      4472787                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total     14039021                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       461364                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       142017                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      8962853                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data      4472787                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total     14039021                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.022925                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.050473                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.029409                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.710853                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.710853                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.808226                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.808226                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.226717                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.226717                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.081982                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.081982                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.255330                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.255330                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.600626                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.600626                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.022925                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.050473                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.081982                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.248987                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.132930                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.022925                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.050473                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.081982                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.248987                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.132930                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 27914.295169                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 30177.455357                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 28828.486898                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21553.383853                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21553.383853                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20664.244892                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20664.244892                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 458416.500000                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 458416.500000                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 37124.800346                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 37124.800346                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 27893.826025                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 27893.826025                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 28821.602375                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 28821.602375                       # average ReadSharedReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 45429.951241                       # average InvalidateReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 45429.951241                       # average InvalidateReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 27914.295169                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 30177.455357                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 27893.826025                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 30497.493406                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 29456.463804                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 27914.295169                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 30177.455357                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 27893.826025                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 30497.493406                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 29456.463804                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks       853283                       # number of writebacks
system.cpu1.l2cache.writebacks::total          853283                       # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker            2                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total            2                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         3653                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total         3653                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            5                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            5                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          365                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          365                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker            2                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            5                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data         4018                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total         4025                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker            2                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            5                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data         4018                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total         4025                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        10577                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         7166                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total        17743                       # number of ReadReq MSHR misses
system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks       103597                       # number of CleanEvict MSHR misses
system.cpu1.l2cache.CleanEvict_mshr_misses::total       103597                       # number of CleanEvict MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       615258                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total       615258                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       137373                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total       137373                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       144729                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       144729                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            6                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            6                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       221126                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total       221126                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       734789                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       734789                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       888523                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       888523                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       252467                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::total       252467                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        10577                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         7166                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       734789                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1109649                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total      1862181                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        10577                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         7166                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       734789                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1109649                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       615258                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total      2477439                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst           93                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         8249                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         8342                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         8420                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         8420                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst           93                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        16669                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        16762                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    231787500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    173284500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    405072000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  18848278545                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  18848278545                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   2780289998                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   2780289998                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2207149499                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2207149499                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      2390499                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2390499                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   6581571997                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   6581571997                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  16087394500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  16087394500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  20254649492                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  20254649492                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data   9954761500                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total   9954761500                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    231787500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    173284500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  16087394500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  26836221489                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total  43328687989                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    231787500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    173284500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  16087394500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  26836221489                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  18848278545                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total  62176966534                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      7998000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   1030068000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   1038066000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   1163435000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   1163435000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      7998000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   2193503000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   2201501000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.022925                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.050459                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.029406                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.710853                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.710853                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.808226                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.808226                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.223033                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.223033                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.081982                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.081982                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.255225                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.255225                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.600626                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.600626                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.022925                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.050459                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.081982                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.248089                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.132643                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.022925                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.050459                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.081982                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.248089                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.176468                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 21914.295169                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 24181.481998                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 22829.961111                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30634.755737                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 30634.755737                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20238.984356                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20238.984356                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15250.222823                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15250.222823                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 398416.500000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 398416.500000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29763.899302                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29763.899302                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 21893.896751                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 21893.896751                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 22795.864026                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 22795.864026                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 39429.951241                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 39429.951241                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 21914.295169                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 24181.481998                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21893.896751                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24184.423623                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23267.710276                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 21914.295169                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 24181.481998                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21893.896751                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24184.423623                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30634.755737                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25097.274457                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst        86000                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 124871.863256                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 124438.503956                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 138175.178147                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 138175.178147                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst        86000                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 131591.757154                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 131338.802052                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq        832335                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp     13281124                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq        38305                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         8420                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback      6193652                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict     13562835                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq       802874                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFResp            2                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq       426908                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       320139                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp       432313                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           51                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          105                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq      1723284                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp       998712                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq      8962853                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq      5808138                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq       527324                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp       420340                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     26886674                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     15523980                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       318688                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1026227                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total         43755569                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    573628544                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    486175782                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1136136                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      3690912                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total        1064631374                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                   10738560                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples     39200977                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       1.285389                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.451600                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1          28013450     71.46%     71.46% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2          11187527     28.54%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total      39200977                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy   17410316483                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy    171564976                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy  13446378573                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy   7120820957                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy    176677986                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy    564893937                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40371                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40371                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136979                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136979                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47802                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29808                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122944                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231676                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231676                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  354700                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47822                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17703                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155959                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7355056                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7355056                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7513101                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36314000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            22142000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           570865133                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92952000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           148116000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115819                       # number of replacements
system.iocache.tags.tagsinuse               11.287255                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115835                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         9174218723000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.836610                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     7.450645                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.239788                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.465665                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.705453                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1042899                       # Number of tag accesses
system.iocache.tags.data_accesses             1042899                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8854                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8891                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106984                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106984                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8854                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8894                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8854                       # number of overall misses
system.iocache.overall_misses::total             8894                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5195000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1658968057                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1664163057                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  12654105076                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  12654105076                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5564000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1658968057                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1664532057                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5564000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1658968057                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1664532057                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8854                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8891                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106984                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106984                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8854                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8894                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8854                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8894                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 187369.331037                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 187173.890114                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118280.351043                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118280.351043                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       139100                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 187369.331037                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 187152.243872                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       139100                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 187369.331037                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 187152.243872                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         32802                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3449                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.510583                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106950                       # number of writebacks
system.iocache.writebacks::total               106950                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8854                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8891                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106984                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106984                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8854                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8894                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8854                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8894                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3345000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1216268057                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1219613057                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7304905076                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   7304905076                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3564000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1216268057                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1219832057                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3564000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1216268057                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1219832057                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137369.331037                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 137173.890114                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68280.351043                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68280.351043                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        89100                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 137369.331037                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 137152.243872                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        89100                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 137369.331037                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 137152.243872                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                  1146599                       # number of replacements
system.l2c.tags.tagsinuse                63894.227459                       # Cycle average of tags in use
system.l2c.tags.total_refs                    5787888                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1208030                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     4.791179                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   20522.379023                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   161.905583                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   188.170352                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     7049.393840                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data    11329.558347                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 10071.994886                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    91.721739                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   112.803397                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     4897.031985                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     4344.569454                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  5124.698853                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.313147                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002470                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.002871                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.107565                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.172875                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.153686                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.001400                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.001721                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.074723                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.066293                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.078197                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.974949                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        10689                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023          178                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        50564                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1            8                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          577                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         2554                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4         7550                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            6                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          172                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          271                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         1822                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3        12846                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        35586                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.163101                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.002716                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.771545                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 67839853                       # Number of tag accesses
system.l2c.tags.data_accesses                67839853                       # Number of data accesses
system.l2c.Writeback_hits::writebacks         2183647                       # number of Writeback hits
system.l2c.Writeback_hits::total              2183647                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data           31153                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data           25605                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               56758                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data          6308                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data          5360                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total             11668                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           179937                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data           157833                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               337770                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         6619                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker         4994                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst       688403                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       550904                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       317834                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         5630                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker         3645                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst       689738                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       516463                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       301818                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          3086048                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker          6619                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          4994                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              688403                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              730841                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher       317834                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          5630                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          3645                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              689738                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              674296                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher       301818                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 3423818                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         6619                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         4994                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             688403                       # number of overall hits
system.l2c.overall_hits::cpu0.data             730841                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher       317834                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         5630                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         3645                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             689738                       # number of overall hits
system.l2c.overall_hits::cpu1.data             674296                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher       301818                       # number of overall hits
system.l2c.overall_hits::total                3423818                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data         42274                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         44615                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             86889                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data         8694                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         8260                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total           16954                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         478873                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data         118092                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             596965                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         1177                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker         1112                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        65012                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       121116                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       167688                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker          801                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker          747                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst        45048                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data        75565                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       121227                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         599493                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker         1177                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         1112                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             65012                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            599989                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       167688                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker          801                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker          747                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             45048                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            193657                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher       121227                       # number of demand (read+write) misses
system.l2c.demand_misses::total               1196458                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         1177                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         1112                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            65012                       # number of overall misses
system.l2c.overall_misses::cpu0.data           599989                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       167688                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker          801                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker          747                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            45048                       # number of overall misses
system.l2c.overall_misses::cpu1.data           193657                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher       121227                       # number of overall misses
system.l2c.overall_misses::total              1196458                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data    285461500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    257633000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    543094500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data     50714500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data     48938500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total     99653000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data  44986860000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   9946118500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  54932978500                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    102808500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker     98262500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   5348800500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  10715307000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  19492330795                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker     71359500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker     66724500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst   3695471500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data   6552252500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  13803765015                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  59947082310                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    102808500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker     98262500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   5348800500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  55702167000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  19492330795                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker     71359500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker     66724500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   3695471500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  16498371000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  13803765015                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total    114880060810                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    102808500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker     98262500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   5348800500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  55702167000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  19492330795                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker     71359500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker     66724500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   3695471500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  16498371000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  13803765015                       # number of overall miss cycles
system.l2c.overall_miss_latency::total   114880060810                       # number of overall miss cycles
system.l2c.Writeback_accesses::writebacks      2183647                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          2183647                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        73427                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data        70220                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total          143647                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data        15002                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data        13620                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total         28622                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       658810                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       275925                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           934735                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         7796                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         6106                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst       753415                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       672020                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       485522                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         6431                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         4392                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst       734786                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       592028                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       423045                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      3685541                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         7796                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         6106                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          753415                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         1330830                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       485522                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         6431                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         4392                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          734786                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          867953                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher       423045                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             4620276                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         7796                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         6106                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         753415                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        1330830                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       485522                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         6431                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         4392                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         734786                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         867953                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher       423045                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            4620276                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.575728                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.635360                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.604879                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.579523                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.606461                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.592342                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.726876                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.427986                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.638646                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.150975                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.182116                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.086290                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.180227                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.345377                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.124553                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.170082                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.061308                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.127638                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.286558                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.162661                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.150975                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.182116                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.086290                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.450838                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.345377                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.124553                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.170082                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.061308                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.223119                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.286558                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.258958                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.150975                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.182116                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.086290                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.450838                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.345377                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.124553                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.170082                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.061308                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.223119                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.286558                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.258958                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  6752.649383                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  5774.582540                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  6250.440217                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5833.275822                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5924.757869                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  5877.845936                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 93943.195795                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 84223.474071                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 92020.434196                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 87347.918437                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 88365.557554                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 82274.049406                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88471.440602                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 116241.655903                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 89088.014981                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 89323.293173                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82034.085864                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 86710.150202                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 113867.084189                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 99996.300724                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 87347.918437                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 88365.557554                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 82274.049406                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 92838.647042                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 116241.655903                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89088.014981                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89323.293173                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 82034.085864                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 85193.775593                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 113867.084189                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 96016.793577                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 87347.918437                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 88365.557554                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 82274.049406                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 92838.647042                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 116241.655903                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89088.014981                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89323.293173                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 82034.085864                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 85193.775593                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 113867.084189                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 96016.793577                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs               272                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        3                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs     90.666667                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks              874415                       # number of writebacks
system.l2c.writebacks::total                   874415                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          124                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data            6                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          136                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data           15                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total          281                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst            124                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data              6                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst            136                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             15                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                281                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst           124                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data             6                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst           136                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            15                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               281                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks        39767                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total        39767                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        42274                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        44615                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        86889                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data         8694                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         8260                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total        16954                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       478873                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data       118092                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        596965                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         1177                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         1112                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        64888                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       121110                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       167688                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker          801                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker          747                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        44912                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data        75550                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       121227                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       599212                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         1177                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         1112                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        64888                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       599983                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       167688                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker          801                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker          747                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        44912                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       193642                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       121227                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total          1196177                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         1177                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         1112                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        64888                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       599983                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       167688                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker          801                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker          747                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        44912                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       193642                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       121227                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total         1196177                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        52292                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        30167                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst           93                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data         8247                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        90799                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        29885                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         8420                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        38305                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        52292                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        60052                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst           93                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        16667                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total       129104                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    877451504                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    925962001                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total   1803413505                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    180795000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    171889500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total    352684500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  40198130000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   8765198500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  48963328500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker     91038500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker     87142500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   4691111500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data   9503861000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  17815450795                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker     63349500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker     59254500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   3237260500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   5795509500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  12591495015                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  53935473310                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker     91038500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker     87142500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   4691111500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  49701991000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  17815450795                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker     63349500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker     59254500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   3237260500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  14560708000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  12591495015                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 102898801810                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker     91038500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker     87142500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   4691111500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  49701991000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  17815450795                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker     63349500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker     59254500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   3237260500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  14560708000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  12591495015                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 102898801810                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   3261312500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   4641716000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      6042500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    881581500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   8790652500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4402307500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   1020289500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   5422597000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   3261312500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   9044023500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      6042500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1901871000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  14213249500                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.575728                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.635360                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.604879                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.579523                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.606461                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.592342                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.726876                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.427986                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.638646                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.150975                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.182116                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.086125                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.180218                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.345377                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.124553                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.170082                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.061123                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.127612                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.286558                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.162585                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.150975                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.182116                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.086125                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.450834                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.345377                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.124553                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.170082                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.061123                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.223102                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.286558                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.258897                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.150975                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.182116                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.086125                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.450834                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.345377                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.124553                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.170082                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.061123                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.223102                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.286558                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.258897                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20756.292378                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20754.499630                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20755.371854                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20795.376121                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20809.866828                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20802.436003                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 83943.195795                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74223.474071                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 82020.434196                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 77347.918437                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 78365.557554                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 72295.516891                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78472.966724                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106241.655903                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79088.014981                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 79323.293173                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72080.078821                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 76710.913302                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103867.084189                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 90010.669529                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77347.918437                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78365.557554                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72295.516891                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82838.998772                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106241.655903                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79088.014981                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79323.293173                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72080.078821                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75193.955857                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103867.084189                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 86023.056630                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77347.918437                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78365.557554                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72295.516891                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82838.998772                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106241.655903                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79088.014981                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79323.293173                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72080.078821                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75193.955857                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103867.084189                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 86023.056630                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62367.331523                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 153867.338482                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64973.118280                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 106897.235358                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 96814.419762                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147308.265016                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 121174.524941                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141563.686203                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62367.331523                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 150603.202225                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64973.118280                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 114109.977800                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 110091.472766                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               90799                       # Transaction distribution
system.membus.trans_dist::ReadResp             698902                       # Transaction distribution
system.membus.trans_dist::WriteReq              38305                       # Transaction distribution
system.membus.trans_dist::WriteResp             38305                       # Transaction distribution
system.membus.trans_dist::Writeback            981364                       # Transaction distribution
system.membus.trans_dist::CleanEvict           209019                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           434160                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq         274076                       # Transaction distribution
system.membus.trans_dist::UpgradeResp          111283                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
system.membus.trans_dist::ReadExReq            609626                       # Transaction distribution
system.membus.trans_dist::ReadExResp           589528                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        608103                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        106984                       # Transaction distribution
system.membus.trans_dist::InvalidateResp       106984                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122944                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           52                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        25274                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4403229                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4551499                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       343039                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       343039                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4894538                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155959                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1324                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        50548                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    135367808                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    135575639                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7275904                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7275904                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               142851543                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           619953                       # Total snoops (count)
system.membus.snoop_fanout::samples           3354848                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 3354848    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             3354848                       # Request fanout histogram
system.membus.reqLayer0.occupancy           109588500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               33984                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            21072500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          6982752656                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         6858580357                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          229669194                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             163                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              163                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.trans_dist::ReadReq              90801                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           4609563                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             38305                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            38305                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback          3165042                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         1502795                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          483481                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq        285744                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         769225                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq          105                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp          105                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq          1092976                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp         1092976                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      4526002                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq       106984                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8264892                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6572319                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              14837211                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    254099969                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    185036822                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              439136791                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         2966852                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples         12598332                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.109406                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.312147                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1               11220005     89.06%     89.06% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                1378327     10.94%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total           12598332                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         8167142441                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          2478499                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        4888169243                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        4052371405                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------