xref: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 47.477179                       # Number of seconds simulated
sim_ticks                                47477179149500                       # Number of ticks simulated
final_tick                               47477179149500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 181000                       # Simulator instruction rate (inst/s)
host_op_rate                                   212908                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             9614368962                       # Simulator tick rate (ticks/s)
host_mem_usage                                 772236                       # Number of bytes of host memory used
host_seconds                                  4938.15                       # Real time elapsed on the host
sim_insts                                   893806699                       # Number of instructions simulated
sim_ops                                    1051369194                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker       125376                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       108736                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          7965248                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         14333320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher     15086080                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       149568                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       136256                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          3627008                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         11510096                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher     14847104                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        436288                       # Number of bytes read from this memory
system.physmem.bytes_read::total             68325080                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      7965248                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      3627008                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total        11592256                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     80335616                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::total          80356200                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         1959                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         1699                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst            124457                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            223971                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       235720                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         2337                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         2129                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             56672                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            179858                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher       231986                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6817                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1067605                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1255244                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1257818                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          2641                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          2290                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              167770                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              301899                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher       317754                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          3150                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          2870                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               76395                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              242434                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       312721                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             9189                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1439114                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         167770                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          76395                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             244165                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1692089                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                433                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1692523                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1692089                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         2641                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         2290                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             167770                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             302333                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher       317754                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         3150                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         2870                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              76395                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             242434                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       312721                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            9189                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3131637                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1067605                       # Number of read requests accepted
system.physmem.writeReqs                      1929186                       # Number of write requests accepted
system.physmem.readBursts                     1067605                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1929186                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 68309056                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     17664                       # Total number of bytes read from write queue
system.physmem.bytesWritten                 120257344                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  68325080                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys              123323752                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      276                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                   50133                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs         117648                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               62386                       # Per bank write bursts
system.physmem.perBankRdBursts::1               65796                       # Per bank write bursts
system.physmem.perBankRdBursts::2               60427                       # Per bank write bursts
system.physmem.perBankRdBursts::3               63507                       # Per bank write bursts
system.physmem.perBankRdBursts::4               66319                       # Per bank write bursts
system.physmem.perBankRdBursts::5               73621                       # Per bank write bursts
system.physmem.perBankRdBursts::6               69221                       # Per bank write bursts
system.physmem.perBankRdBursts::7               63591                       # Per bank write bursts
system.physmem.perBankRdBursts::8               61143                       # Per bank write bursts
system.physmem.perBankRdBursts::9              115825                       # Per bank write bursts
system.physmem.perBankRdBursts::10              59973                       # Per bank write bursts
system.physmem.perBankRdBursts::11              66407                       # Per bank write bursts
system.physmem.perBankRdBursts::12              58867                       # Per bank write bursts
system.physmem.perBankRdBursts::13              61123                       # Per bank write bursts
system.physmem.perBankRdBursts::14              58743                       # Per bank write bursts
system.physmem.perBankRdBursts::15              60380                       # Per bank write bursts
system.physmem.perBankWrBursts::0              115877                       # Per bank write bursts
system.physmem.perBankWrBursts::1              122877                       # Per bank write bursts
system.physmem.perBankWrBursts::2              115996                       # Per bank write bursts
system.physmem.perBankWrBursts::3              119851                       # Per bank write bursts
system.physmem.perBankWrBursts::4              119313                       # Per bank write bursts
system.physmem.perBankWrBursts::5              126432                       # Per bank write bursts
system.physmem.perBankWrBursts::6              119028                       # Per bank write bursts
system.physmem.perBankWrBursts::7              120185                       # Per bank write bursts
system.physmem.perBankWrBursts::8              118113                       # Per bank write bursts
system.physmem.perBankWrBursts::9              119452                       # Per bank write bursts
system.physmem.perBankWrBursts::10             113141                       # Per bank write bursts
system.physmem.perBankWrBursts::11             117109                       # Per bank write bursts
system.physmem.perBankWrBursts::12             112676                       # Per bank write bursts
system.physmem.perBankWrBursts::13             113553                       # Per bank write bursts
system.physmem.perBankWrBursts::14             112771                       # Per bank write bursts
system.physmem.perBankWrBursts::15             112647                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                         226                       # Number of times write queue was full causing retry
system.physmem.totGap                    47477177227000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1067575                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1926612                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    704225                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    128672                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     50762                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     38076                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                     32557                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                     29624                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                     27261                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     24554                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     21025                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      5650                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1457                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      974                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      763                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      566                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      319                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      265                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      210                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      190                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      103                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       70                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    45205                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    65288                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    93465                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                   105702                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                   113971                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                   112162                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                   108444                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                   104050                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                   100974                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    97727                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    97663                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                   116214                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                   104741                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                   100206                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                   114790                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                   102548                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    96204                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    91928                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     7498                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     6040                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     6647                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     7551                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     7971                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     7109                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     6845                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     7426                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     5746                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     5672                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     5351                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     5487                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                     4631                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                     3871                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                     3873                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                     3174                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                     2570                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                     1610                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                     1389                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      919                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                     1025                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      778                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      627                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      635                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      623                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      556                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      443                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      391                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      338                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                      256                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      704                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      1080190                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      174.567156                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     106.861850                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     244.135229                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         694007     64.25%     64.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       206792     19.14%     83.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        51978      4.81%     88.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        24974      2.31%     90.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        18580      1.72%     92.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        11712      1.08%     93.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         8387      0.78%     94.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         7821      0.72%     94.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        55939      5.18%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        1080190                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         83578                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        12.770071                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      136.461901                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          83575    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::25600-26623            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::28672-29695            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           83578                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         83578                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        22.482244                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       19.955849                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       20.755182                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-31            75860     90.77%     90.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-63            5202      6.22%     96.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-95            1276      1.53%     98.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-127            755      0.90%     99.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-159           241      0.29%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-191           100      0.12%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-223            48      0.06%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-255             8      0.01%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-287             9      0.01%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::288-319            10      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::320-351            17      0.02%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::352-383            25      0.03%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::384-415             5      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::416-447             1      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::448-479             5      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::480-511             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::512-543             5      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::544-575             3      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::640-671             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::672-703             3      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::992-1023            1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1056-1087            1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           83578                       # Writes before turning the bus around for reads
system.physmem.totQLat                    40962619238                       # Total ticks spent queuing
system.physmem.totMemAccLat               60975037988                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   5336645000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       38378.62                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  57128.62                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.44                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.53                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.44                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.60                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.20                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        23.74                       # Average write queue length when enqueuing
system.physmem.readRowHits                     799066                       # Number of row buffer hits during reads
system.physmem.writeRowHits                   1067089                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   74.87                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  56.79                       # Row buffer hit rate for writes
system.physmem.avgGap                     15842672.12                       # Average gap between requests
system.physmem.pageHitRate                      63.34                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 4225820760                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 2305755375                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                4093954800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               6217942320                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3100978164960                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1196990920755                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           27436312080750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             31751124639720                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.766110                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   45642284556030                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1585367160000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    249523460470                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 3940415640                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 2150028375                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                4231125600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               5958113760                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3100978164960                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1192295919105                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           27440430503250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             31749984270690                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.742090                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   45649112064952                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1585367160000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    242698243548                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst          704                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          576                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data            8                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total          1324                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          704                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          576                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total         1280                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           11                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst            9                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             26                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           15                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           12                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               28                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           15                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           12                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           27                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           15                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           12                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              28                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups              146228375                       # Number of BP lookups
system.cpu0.branchPred.condPredicted        102974776                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          6711039                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups           109409110                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               78811291                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            72.033573                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS               17518133                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect           1190785                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                   302414                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               302414                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2         9161                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        80364                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples       302414                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0         302414    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       302414                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples        89525                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 18873.046300                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 17079.714221                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 14739.219535                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535        88579     98.94%     98.94% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071          783      0.87%     99.82% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607           49      0.05%     99.87% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143           43      0.05%     99.92% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679           44      0.05%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215           15      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751            7      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total        89525                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples    788586204                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0      788586204    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total    788586204                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        80364     89.77%     89.77% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M         9161     10.23%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total        89525                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       302414                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       302414                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        89525                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        89525                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       391939                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    94852147                       # DTB read hits
system.cpu0.dtb.read_misses                    252189                       # DTB read misses
system.cpu0.dtb.write_hits                   83443537                       # DTB write hits
system.cpu0.dtb.write_misses                    50225                       # DTB write misses
system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              43363                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                   1048                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   36113                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     2068                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  9574                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                    10663                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                95104336                       # DTB read accesses
system.cpu0.dtb.write_accesses               83493762                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        178295684                       # DTB hits
system.cpu0.dtb.misses                         302414                       # DTB misses
system.cpu0.dtb.accesses                    178598098                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                    66598                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                66598                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2          516                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        54284                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples        66598                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0          66598    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        66598                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        54800                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 21262.637080                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 19017.155066                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 16721.874177                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535        53728     98.04%     98.04% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071          946      1.73%     99.77% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607           48      0.09%     99.86% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143           54      0.10%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679           12      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215            9      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        54800                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples    787865704                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0      787865704    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total    787865704                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        54284     99.06%     99.06% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M          516      0.94%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        54800                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        66598                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        66598                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        54800                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        54800                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       121398                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   261387859                       # ITB inst hits
system.cpu0.itb.inst_misses                     66598                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              43363                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                   1048                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   25865                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                   223375                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               261454457                       # ITB inst accesses
system.cpu0.itb.hits                        261387859                       # DTB hits
system.cpu0.itb.misses                          66598                       # DTB misses
system.cpu0.itb.accesses                    261454457                       # DTB accesses
system.cpu0.numCycles                      1029830596                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                  487755400                       # Number of instructions committed
system.cpu0.committedOps                    573075495                       # Number of ops (including micro ops) committed
system.cpu0.discardedOps                     47715438                       # Number of ops (including micro ops) which were discarded before commit
system.cpu0.numFetchSuspends                     4391                       # Number of times Execute suspended instruction fetching
system.cpu0.quiesceCycles                 93925247519                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.cpi                              2.111367                       # CPI: cycles per instruction
system.cpu0.ipc                              0.473627                       # IPC: instructions per cycle
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   13314                       # number of quiesce instructions executed
system.cpu0.tickCycles                      777849504                       # Number of cycles that the object actually ticked
system.cpu0.idleCycles                      251981092                       # Total number of cycles that the object has spent stopped
system.cpu0.dcache.tags.replacements          5902107                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          475.000126                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          169363182                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          5902609                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            28.692936                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       5093256500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   475.000126                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.927735                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.927735                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          502                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          111                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          238                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2          153                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024     0.980469                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        359562725                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       359562725                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     86974547                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       86974547                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     77401946                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      77401946                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       298185                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       298185                       # number of SoftPFReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       275916                       # number of WriteInvalidateReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::total       275916                       # number of WriteInvalidateReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1961524                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      1961524                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1923644                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      1923644                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    164376493                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       164376493                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    164674678                       # number of overall hits
system.cpu0.dcache.overall_hits::total      164674678                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      3650210                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      3650210                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      2435892                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      2435892                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       670224                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       670224                       # number of SoftPFReq misses
system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data       817849                       # number of WriteInvalidateReq misses
system.cpu0.dcache.WriteInvalidateReq_misses::total       817849                       # number of WriteInvalidateReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       165967                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       165967                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data       202383                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total       202383                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      6086102                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       6086102                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      6756326                       # number of overall misses
system.cpu0.dcache.overall_misses::total      6756326                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  55969500387                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  55969500387                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  47032436273                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  47032436273                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data  33507618312                       # number of WriteInvalidateReq miss cycles
system.cpu0.dcache.WriteInvalidateReq_miss_latency::total  33507618312                       # number of WriteInvalidateReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2441854002                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   2441854002                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4283229947                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total   4283229947                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      1855000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      1855000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 103001936660                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 103001936660                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 103001936660                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 103001936660                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     90624757                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     90624757                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     79837838                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     79837838                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       968409                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       968409                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data      1093765                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::total      1093765                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2127491                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      2127491                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2126027                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      2126027                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    170462595                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    170462595                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    171431004                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    171431004                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.040278                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.040278                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.030510                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.030510                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.692088                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.692088                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data     0.747737                       # miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.747737                       # miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.078011                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.078011                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.095193                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.095193                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.035703                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.035703                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.039411                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.039411                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15333.227509                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15333.227509                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19308.095873                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 19308.095873                       # average WriteReq miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 40970.421572                       # average WriteInvalidateReq miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 40970.421572                       # average WriteInvalidateReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14712.888719                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14712.888719                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21163.980903                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21163.980903                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16924.122642                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 16924.122642                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15245.258541                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 15245.258541                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      3966592                       # number of writebacks
system.cpu0.dcache.writebacks::total          3966592                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       443574                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       443574                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1010368                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1010368                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data          102                       # number of WriteInvalidateReq MSHR hits
system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total          102                       # number of WriteInvalidateReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        43626                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        43626                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data           27                       # number of StoreCondReq MSHR hits
system.cpu0.dcache.StoreCondReq_mshr_hits::total           27                       # number of StoreCondReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1453942                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      1453942                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1453942                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      1453942                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3206636                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      3206636                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1425524                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      1425524                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       664815                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       664815                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data       817747                       # number of WriteInvalidateReq MSHR misses
system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total       817747                       # number of WriteInvalidateReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       122341                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       122341                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       202356                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total       202356                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      4632160                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      4632160                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      5296975                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      5296975                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31604                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31604                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        30977                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        30977                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        62581                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        62581                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  42580313466                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  42580313466                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  25667045166                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  25667045166                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  14837829930                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  14837829930                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  32271814438                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  32271814438                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1568491891                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1568491891                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   3969414040                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   3969414040                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      1696000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      1696000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  68247358632                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  68247358632                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  83085188562                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  83085188562                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5612600750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5612600750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5285393252                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5285393252                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  10897994002                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10897994002                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.035384                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.035384                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.017855                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017855                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.686502                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.686502                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.747644                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.747644                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.057505                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.057505                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.095180                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.095180                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.027174                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.027174                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.030899                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.030899                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13278.811024                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13278.811024                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18005.340609                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18005.340609                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22318.735182                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22318.735182                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39464.301842                       # average WriteInvalidateReq mshr miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39464.301842                       # average WriteInvalidateReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12820.656125                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12820.656125                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19615.993793                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19615.993793                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14733.376790                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14733.376790                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15685.403190                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15685.403190                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177591.467852                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 177591.467852                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170623.147884                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 170623.147884                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 174142.215720                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 174142.215720                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements         10289736                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.930282                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          250868144                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs         10290248                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            24.379213                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      24018555250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.930282                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999864                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999864                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          266                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          233                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           13                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        532607059                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       532607059                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    250868144                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      250868144                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    250868144                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       250868144                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    250868144                       # number of overall hits
system.cpu0.icache.overall_hits::total      250868144                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst     10290257                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total     10290257                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst     10290257                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total      10290257                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst     10290257                       # number of overall misses
system.cpu0.icache.overall_misses::total     10290257                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 101454150461                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 101454150461                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 101454150461                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 101454150461                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 101454150461                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 101454150461                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    261158401                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    261158401                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    261158401                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    261158401                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    261158401                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    261158401                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.039402                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.039402                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.039402                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.039402                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.039402                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.039402                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9859.243599                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  9859.243599                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9859.243599                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  9859.243599                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9859.243599                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  9859.243599                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst     10290257                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total     10290257                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst     10290257                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total     10290257                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst     10290257                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total     10290257                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        52307                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total        52307                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        52307                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total        52307                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  91134485035                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  91134485035                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  91134485035                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  91134485035                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  91134485035                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  91134485035                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   4833897250                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   4833897250                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   4833897250                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   4833897250                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.039402                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.039402                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.039402                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.039402                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.039402                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.039402                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  8856.385709                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  8856.385709                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  8856.385709                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total  8856.385709                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  8856.385709                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total  8856.385709                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92413.964670                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92413.964670                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92413.964670                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92413.964670                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued      8031555                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      8035489                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit         3395                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage      1023103                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements         2858654                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16072.506631                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs          16359356                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs         2874620                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            5.690963                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle      5820437500                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks  7531.283903                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    82.699151                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    79.479413                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4176.151665                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data  3206.986567                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   995.905932                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.459673                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.005048                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.004851                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.254892                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.195739                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.060785                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.980988                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1379                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           78                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14509                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          349                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          790                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          240                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            4                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           24                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           40                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           10                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          168                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          671                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4595                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         6778                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2297                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.084167                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.004761                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.885559                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses       347615506                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses      347615506                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       522089                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       157285                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.inst      9486915                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.data      2945564                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total      13111853                       # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks      3966591                       # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total      3966591                       # number of Writeback hits
system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data       220070                       # number of WriteInvalidateReq hits
system.cpu0.l2cache.WriteInvalidateReq_hits::total       220070                       # number of WriteInvalidateReq hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data       104135                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total       104135                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        36121                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total        36121                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       927424                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       927424                       # number of ReadExReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       522089                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker       157285                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      9486915                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data      3872988                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total       14039277                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       522089                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker       157285                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      9486915                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data      3872988                       # number of overall hits
system.cpu0.l2cache.overall_hits::total      14039277                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        12017                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         8240                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.inst       803341                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.data      1047943                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total      1871541                       # number of ReadReq misses
system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data       596217                       # number of WriteInvalidateReq misses
system.cpu0.l2cache.WriteInvalidateReq_misses::total       596217                       # number of WriteInvalidateReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       136954                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total       136954                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       166233                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total       166233                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            2                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            2                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data       268888                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total       268888                       # number of ReadExReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        12017                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker         8240                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       803341                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data      1316831                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total      2140429                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        12017                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker         8240                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       803341                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data      1316831                       # number of overall misses
system.cpu0.l2cache.overall_misses::total      2140429                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    431373212                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    321871478                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst  24275854446                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data  35706676401                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total  60735775537                       # number of ReadReq miss cycles
system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data    217330162                       # number of WriteInvalidateReq miss cycles
system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total    217330162                       # number of WriteInvalidateReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   2999502703                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total   2999502703                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   3447611393                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   3447611393                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      1659499                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      1659499                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  13657276886                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total  13657276886                       # number of ReadExReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    431373212                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    321871478                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst  24275854446                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data  49363953287                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total  74393052423                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    431373212                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    321871478                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst  24275854446                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data  49363953287                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total  74393052423                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       534106                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       165525                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.inst     10290256                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.data      3993507                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total     14983394                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks      3966591                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total      3966591                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data       816287                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.l2cache.WriteInvalidateReq_accesses::total       816287                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       241089                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total       241089                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       202354                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total       202354                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            2                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            2                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1196312                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total      1196312                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       534106                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       165525                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst     10290256                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data      5189819                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total     16179706                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       534106                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       165525                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst     10290256                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data      5189819                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total     16179706                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.022499                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.049781                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.078068                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.262412                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.124908                       # miss rate for ReadReq accesses
system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data     0.730401                       # miss rate for WriteInvalidateReq accesses
system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total     0.730401                       # miss rate for WriteInvalidateReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.568064                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.568064                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.821496                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.821496                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.224764                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.224764                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.022499                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.049781                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.078068                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.253734                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.132291                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.022499                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.049781                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.078068                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.253734                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.132291                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35896.913706                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 39062.072573                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30218.617556                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 34073.109321                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32452.281589                       # average ReadReq miss latency
system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data   364.515205                       # average WriteInvalidateReq miss latency
system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total   364.515205                       # average WriteInvalidateReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21901.534114                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21901.534114                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20739.632883                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20739.632883                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 829749.500000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 829749.500000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50791.693516                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50791.693516                       # average ReadExReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35896.913706                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 39062.072573                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30218.617556                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 37486.931343                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 34756.141139                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35896.913706                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 39062.072573                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30218.617556                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 37486.931343                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 34756.141139                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs          127                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               1                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          127                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks      1439553                       # number of writebacks
system.cpu0.l2cache.writebacks::total         1439553                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker            3                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst           11                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data         1023                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total         1037                       # number of ReadReq MSHR hits
system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.data           27                       # number of WriteInvalidateReq MSHR hits
system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total           27                       # number of WriteInvalidateReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         8712                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         8712                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker            3                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           11                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         9735                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         9749                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker            3                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           11                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         9735                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         9749                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        12017                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         8237                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst       803330                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data      1046920                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total      1870504                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       757617                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       757617                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data       596190                       # number of WriteInvalidateReq MSHR misses
system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total       596190                       # number of WriteInvalidateReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       136954                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total       136954                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       166233                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       166233                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            2                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            2                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       260176                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total       260176                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        12017                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         8237                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       803330                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1307096                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total      2130680                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        12017                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         8237                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       803330                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1307096                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       757617                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total      2888297                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        52307                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        31604                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        83911                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        30977                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        30977                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        52307                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        62581                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total       114888                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    352675786                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    267790036                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst  19027435054                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data  28762264327                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total  48410165203                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  36487468285                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  36487468285                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  26018290315                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total  26018290315                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   2786437286                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   2786437286                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2450969244                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   2450969244                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1425499                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1425499                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  10771329997                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  10771329997                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    352675786                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    267790036                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  19027435054                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  39533594324                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total  59181495200                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    352675786                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    267790036                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  19027435054                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  39533594324                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  36487468285                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  95668963485                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   4391070750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5359743750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   9750814500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5053047499                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5053047499                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   4391070750                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  10412791249                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  14803861999                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.022499                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.049763                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.078067                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.262156                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.124838                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.730368                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.730368                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.568064                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.568064                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.821496                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.821496                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.217482                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.217482                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.022499                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.049763                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.078067                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.251858                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.131688                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.022499                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.049763                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.078067                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.251858                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.178514                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29348.072397                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 32510.627170                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23685.702083                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 27473.220807                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25880.813515                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48160.836260                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 48160.836260                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 43640.937143                       # average WriteInvalidateReq mshr miss latency
system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 43640.937143                       # average WriteInvalidateReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20345.789725                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20345.789725                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14744.179820                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14744.179820                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 712749.500000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 712749.500000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41400.167567                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41400.167567                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29348.072397                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 32510.627170                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23685.702083                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30245.364016                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27775.872116                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29348.072397                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 32510.627170                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23685.702083                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30245.364016                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48160.836260                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33122.966054                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83948.051886                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 169590.676813                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 116204.246166                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 163122.558640                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163122.558640                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83948.051886                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 166389.019814                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 128854.728074                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq      17664917                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp     15307376                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        38492                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        30977                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback      3966591                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq      1103078                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFResp            1                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq      1166462                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp       816287                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq       481802                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       368927                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       516230                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           30                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           64                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq      1338230                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp      1206066                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     20685127                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     17177406                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       364539                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1170846                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total         39397918                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    661924032                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    645723507                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1324200                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      4272848                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total        1313244587                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    4794163                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples     26128529                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       1.203121                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.402322                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1          20821287     79.69%     79.69% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2           5307242     20.31%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total      26128529                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy   15626998682                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    207003480                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy  15540735463                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   8534595583                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy    199309237                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy    637104704                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.branchPred.lookups              125576312                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         90437850                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect          5588126                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups            96414800                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits               70448335                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            73.067968                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS               14240452                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect            921306                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                   267188                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               267188                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        10577                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        85745                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples       267188                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0         267188    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       267188                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples        96322                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 19417.832759                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 17582.202051                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 14852.958051                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-32767        91721     95.22%     95.22% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-65535         3398      3.53%     98.75% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-98303          602      0.62%     99.38% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-131071          416      0.43%     99.81% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-163839           24      0.02%     99.83% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::163840-196607           24      0.02%     99.86% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-229375           36      0.04%     99.90% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::229376-262143           19      0.02%     99.91% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-294911           31      0.03%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::294912-327679           34      0.04%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-360447            8      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::360448-393215            3      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-425983            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::425984-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total        96322                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples   1244507444                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     1244507444    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   1244507444                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        85745     89.02%     89.02% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M        10577     10.98%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total        96322                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       267188                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       267188                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        96322                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        96322                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       363510                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    79480191                       # DTB read hits
system.cpu1.dtb.read_misses                    220503                       # DTB read misses
system.cpu1.dtb.write_hits                   69950509                       # DTB write hits
system.cpu1.dtb.write_misses                    46685                       # DTB write misses
system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              43363                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                   1048                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   40279                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                     1007                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  7671                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    12807                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                79700694                       # DTB read accesses
system.cpu1.dtb.write_accesses               69997194                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        149430700                       # DTB hits
system.cpu1.dtb.misses                         267188                       # DTB misses
system.cpu1.dtb.accesses                    149697888                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                    64917                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                64917                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2          645                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        55496                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples        64917                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0          64917    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        64917                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        56141                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 22418.994977                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 19682.840516                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 19289.014659                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535        54677     97.39%     97.39% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071         1297      2.31%     99.70% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607           47      0.08%     99.79% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143           81      0.14%     99.93% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679           18      0.03%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215           16      0.03%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751            1      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287            3      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        56141                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples   1243919944                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     1243919944    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   1243919944                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        55496     98.85%     98.85% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M          645      1.15%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        56141                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        64917                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        64917                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        56141                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        56141                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       121058                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   225481249                       # ITB inst hits
system.cpu1.itb.inst_misses                     64917                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              43363                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                   1048                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   28543                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                   202570                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               225546166                       # ITB inst accesses
system.cpu1.itb.hits                        225481249                       # DTB hits
system.cpu1.itb.misses                          64917                       # DTB misses
system.cpu1.itb.accesses                    225546166                       # DTB accesses
system.cpu1.numCycles                       849119079                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                  406051299                       # Number of instructions committed
system.cpu1.committedOps                    478293699                       # Number of ops (including micro ops) committed
system.cpu1.discardedOps                     46606937                       # Number of ops (including micro ops) which were discarded before commit
system.cpu1.numFetchSuspends                     5644                       # Number of times Execute suspended instruction fetching
system.cpu1.quiesceCycles                 94106060514                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.cpi                              2.091162                       # CPI: cycles per instruction
system.cpu1.ipc                              0.478203                       # IPC: instructions per cycle
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    5757                       # number of quiesce instructions executed
system.cpu1.tickCycles                      666946808                       # Number of cycles that the object actually ticked
system.cpu1.idleCycles                      182172271                       # Total number of cycles that the object has spent stopped
system.cpu1.dcache.tags.replacements          5052284                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          457.990994                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs          141727438                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs          5052796                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            28.049309                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     8380007678500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   457.990994                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.894514                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.894514                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0           95                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          359                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2           58                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses        301466109                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses       301466109                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data     72704936                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       72704936                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data     65165576                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total      65165576                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data       206723                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total       206723                       # number of SoftPFReq hits
system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data        46881                       # number of WriteInvalidateReq hits
system.cpu1.dcache.WriteInvalidateReq_hits::total        46881                       # number of WriteInvalidateReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1586345                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total      1586345                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1544117                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total      1544117                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data    137870512                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total       137870512                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data    138077235                       # number of overall hits
system.cpu1.dcache.overall_hits::total      138077235                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data      3207186                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total      3207186                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      2249159                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      2249159                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data       660232                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total       660232                       # number of SoftPFReq misses
system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data       426407                       # number of WriteInvalidateReq misses
system.cpu1.dcache.WriteInvalidateReq_misses::total       426407                       # number of WriteInvalidateReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       160976                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total       160976                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data       201965                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total       201965                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      5456345                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       5456345                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      6116577                       # number of overall misses
system.cpu1.dcache.overall_misses::total      6116577                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  49733165026                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total  49733165026                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  39916128019                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  39916128019                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data  12105984043                       # number of WriteInvalidateReq miss cycles
system.cpu1.dcache.WriteInvalidateReq_miss_latency::total  12105984043                       # number of WriteInvalidateReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2535632453                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total   2535632453                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4276755567                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total   4276755567                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1256500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1256500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  89649293045                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  89649293045                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  89649293045                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  89649293045                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data     75912122                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     75912122                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data     67414735                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total     67414735                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       866955                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       866955                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data       473288                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.dcache.WriteInvalidateReq_accesses::total       473288                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1747321                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total      1747321                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1746082                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total      1746082                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data    143326857                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total    143326857                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data    144193812                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total    144193812                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.042249                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.042249                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.033363                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.033363                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.761553                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.761553                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data     0.900946                       # miss rate for WriteInvalidateReq accesses
system.cpu1.dcache.WriteInvalidateReq_miss_rate::total     0.900946                       # miss rate for WriteInvalidateReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.092127                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.092127                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.115668                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.115668                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.038069                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.038069                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.042419                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.042419                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15506.791632                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15506.791632                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17747.134826                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 17747.134826                       # average WriteReq miss latency
system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 28390.678490                       # average WriteInvalidateReq miss latency
system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 28390.678490                       # average WriteInvalidateReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15751.617962                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15751.617962                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21175.726324                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21175.726324                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16430.283101                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 16430.283101                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14656.775030                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 14656.775030                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks      3294639                       # number of writebacks
system.cpu1.dcache.writebacks::total          3294639                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       376716                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total       376716                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       934861                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total       934861                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data           50                       # number of WriteInvalidateReq MSHR hits
system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total           50                       # number of WriteInvalidateReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        39920                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        39920                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data           26                       # number of StoreCondReq MSHR hits
system.cpu1.dcache.StoreCondReq_mshr_hits::total           26                       # number of StoreCondReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data      1311577                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total      1311577                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data      1311577                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total      1311577                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2830470                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total      2830470                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1314298                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total      1314298                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       659943                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total       659943                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data       426357                       # number of WriteInvalidateReq MSHR misses
system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total       426357                       # number of WriteInvalidateReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       121056                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total       121056                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       201939                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total       201939                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data      4144768                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total      4144768                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data      4804711                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total      4804711                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         7026                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total         7026                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         7515                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total         7515                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        14541                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total        14541                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  38398702439                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total  38398702439                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  21764603493                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total  21764603493                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  13372610673                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  13372610673                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data  11459992206                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total  11459992206                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1620200910                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1620200910                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   3963729421                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   3963729421                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1148000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1148000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  60163305932                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total  60163305932                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  73535916605                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total  73535916605                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    828088750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    828088750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    987688750                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    987688750                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1815777500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1815777500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.037286                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.037286                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.019496                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.019496                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.761219                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.761219                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.900841                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.900841                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.069281                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.069281                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.115653                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.115653                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.028918                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.028918                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.033321                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.033321                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13566.193049                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13566.193049                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16559.869598                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16559.869598                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20263.281333                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20263.281333                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 26878.864909                       # average WriteInvalidateReq mshr miss latency
system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 26878.864909                       # average WriteInvalidateReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13383.895966                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13383.895966                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19628.350249                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19628.350249                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14515.482153                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14515.482153                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15304.961444                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15304.961444                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117860.624822                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 117860.624822                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 131428.975383                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 131428.975383                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 124872.945465                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 124872.945465                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements          8512500                       # number of replacements
system.cpu1.icache.tags.tagsinuse          507.044267                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs          216759728                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          8513012                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            25.462166                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     8369990866500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   507.044267                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.990321                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.990321                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0          217                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          252                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2           43                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses        459058494                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses       459058494                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst    216759728                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total      216759728                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst    216759728                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total       216759728                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst    216759728                       # number of overall hits
system.cpu1.icache.overall_hits::total      216759728                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      8513013                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      8513013                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      8513013                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       8513013                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      8513013                       # number of overall misses
system.cpu1.icache.overall_misses::total      8513013                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  85304905568                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total  85304905568                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst  85304905568                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total  85304905568                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst  85304905568                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total  85304905568                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst    225272741                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total    225272741                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst    225272741                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total    225272741                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst    225272741                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total    225272741                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.037790                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.037790                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.037790                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.037790                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.037790                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.037790                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10020.530401                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 10020.530401                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10020.530401                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 10020.530401                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10020.530401                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 10020.530401                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      8513013                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total      8513013                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst      8513013                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total      8513013                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst      8513013                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total      8513013                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst           90                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total           90                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst           90                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total           90                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  76768195856                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total  76768195856                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  76768195856                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total  76768195856                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  76768195856                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total  76768195856                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8107000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8107000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8107000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      8107000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.037790                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.037790                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.037790                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.037790                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.037790                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.037790                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  9017.746814                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  9017.746814                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  9017.746814                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  9017.746814                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  9017.746814                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  9017.746814                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90077.777778                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90077.777778                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90077.777778                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90077.777778                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued      7158191                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified      7159863                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit         1351                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage       847001                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements         2383886                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       13587.340153                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs          13938188                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs         2400056                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs            5.807443                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle    10048790087250                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks  4939.758457                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    75.017087                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    74.049784                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  4551.314512                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3187.549823                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   759.650489                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.301499                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004579                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.004520                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.277790                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.194553                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.046365                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.829305                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1323                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           67                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14780                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           42                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          286                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          433                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          562                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::0            1                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           40                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            5                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           21                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          187                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1093                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         4947                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         2638                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         5915                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.080750                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.004089                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.902100                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses       292928618                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses      292928618                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       489959                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       155192                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.inst      7753793                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.data      2612837                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total      11011781                       # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks      3294638                       # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total      3294638                       # number of Writeback hits
system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data       173190                       # number of WriteInvalidateReq hits
system.cpu1.l2cache.WriteInvalidateReq_hits::total       173190                       # number of WriteInvalidateReq hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        70896                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total        70896                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        35338                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total        35338                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data       862674                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total       862674                       # number of ReadExReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       489959                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker       155192                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      7753793                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data      3475511                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total       11874455                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       489959                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker       155192                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      7753793                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data      3475511                       # number of overall hits
system.cpu1.l2cache.overall_hits::total      11874455                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        11727                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         8782                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.inst       759220                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.data       998421                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total      1778150                       # number of ReadReq misses
system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data       251764                       # number of WriteInvalidateReq misses
system.cpu1.l2cache.WriteInvalidateReq_misses::total       251764                       # number of WriteInvalidateReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       136318                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total       136318                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       166600                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total       166600                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            1                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data       246181                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total       246181                       # number of ReadExReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        11727                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker         8782                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       759220                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data      1244602                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total      2024331                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        11727                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker         8782                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       759220                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data      1244602                       # number of overall misses
system.cpu1.l2cache.overall_misses::total      2024331                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    449146209                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    373707270                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst  22071218543                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data  32673719778                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total  55567791800                       # number of ReadReq miss cycles
system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data    216255594                       # number of WriteInvalidateReq miss cycles
system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total    216255594                       # number of WriteInvalidateReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   2967566092                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total   2967566092                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   3447328545                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   3447328545                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1119500                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1119500                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  10839077173                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total  10839077173                       # number of ReadExReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    449146209                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    373707270                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst  22071218543                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data  43512796951                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total  66406868973                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    449146209                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    373707270                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst  22071218543                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data  43512796951                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total  66406868973                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       501686                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       163974                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst      8513013                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.data      3611258                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total     12789931                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks      3294638                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total      3294638                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data       424954                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.l2cache.WriteInvalidateReq_accesses::total       424954                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       207214                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total       207214                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       201938                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total       201938                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1108855                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total      1108855                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       501686                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       163974                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      8513013                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data      4720113                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total     13898786                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       501686                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       163974                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      8513013                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data      4720113                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total     13898786                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.023375                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.053557                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.089183                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.276475                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.139027                       # miss rate for ReadReq accesses
system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data     0.592450                       # miss rate for WriteInvalidateReq accesses
system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total     0.592450                       # miss rate for WriteInvalidateReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.657861                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.657861                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.825006                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.825006                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.222014                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.222014                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.023375                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.053557                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.089183                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.263681                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.145648                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.023375                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.053557                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.089183                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.263681                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.145648                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 38300.179841                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 42553.777044                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 29070.912967                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 32725.393174                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 31250.339848                       # average ReadReq miss latency
system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data   858.961543                       # average WriteInvalidateReq miss latency
system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total   858.961543                       # average WriteInvalidateReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21769.436846                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21769.436846                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20692.248169                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20692.248169                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data      1119500                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total      1119500                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44028.894078                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44028.894078                       # average ReadExReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 38300.179841                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 42553.777044                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29070.912967                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34961.214068                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 32804.353129                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 38300.179841                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 42553.777044                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29070.912967                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34961.214068                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 32804.353129                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks      1051021                       # number of writebacks
system.cpu1.l2cache.writebacks::total         1051021                       # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst            2                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data          699                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total          701                       # number of ReadReq MSHR hits
system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data            6                       # number of WriteInvalidateReq MSHR hits
system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total            6                       # number of WriteInvalidateReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         8312                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total         8312                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            2                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data         9011                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total         9013                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            2                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data         9011                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total         9013                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        11727                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         8782                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst       759218                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data       997722                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total      1777449                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       732693                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total       732693                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data       251758                       # number of WriteInvalidateReq MSHR misses
system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total       251758                       # number of WriteInvalidateReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       136318                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total       136318                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       166600                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       166600                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       237869                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total       237869                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        11727                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         8782                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       759218                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1235591                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total      2015318                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        11727                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         8782                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       759218                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1235591                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       732693                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total      2748011                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst           90                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         7026                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         7116                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         7515                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         7515                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst           90                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        14541                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        14631                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    372203283                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    315988754                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst  17115860957                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data  26083443690                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total  43887496684                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  35590505004                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  35590505004                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data   8154289208                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total   8154289208                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   2662634544                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   2662634544                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2448254099                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2448254099                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       937500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       937500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   8085398810                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   8085398810                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    372203283                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    315988754                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  17115860957                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  34168842500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total  51972895494                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    372203283                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    315988754                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  17115860957                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  34168842500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  35590505004                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total  87563400498                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      7349000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    771832750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    779181750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    931317500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    931317500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      7349000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1703150250                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1710499250                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.023375                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.053557                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.089183                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.276281                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.138973                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.592436                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.592436                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.657861                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.657861                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.825006                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.825006                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.214518                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.214518                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.023375                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.053557                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.089183                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.261771                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.145000                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.023375                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.053557                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.089183                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.261771                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.197716                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31739.002558                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35981.411296                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22544.066338                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26142.997438                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 24691.283229                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48574.921562                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 48574.921562                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32389.394609                       # average WriteInvalidateReq mshr miss latency
system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32389.394609                       # average WriteInvalidateReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19532.523541                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19532.523541                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14695.402755                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14695.402755                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       937500                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       937500                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33990.973225                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33990.973225                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31739.002558                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35981.411296                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22544.066338                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27653.845407                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25788.930330                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31739.002558                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35981.411296                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22544.066338                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27653.845407                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48574.921562                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31864.283112                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81655.555556                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 109853.793054                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 109497.154300                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 123927.811045                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 123927.811045                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81655.555556                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 117127.449969                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 116909.250906                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq      15573132                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp     13012901                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq        38492                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         7515                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback      3294638                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq      1065592                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFResp            3                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq      1119456                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp       424954                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq       452600                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       368137                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp       473527                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           37                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           64                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq      1269149                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp      1115295                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     17026205                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     14595450                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       357835                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1096931                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total         33076421                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    544838528                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    546511254                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1311792                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4013488                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total        1096675062                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                    5302361                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples     23181233                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       1.250406                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.433247                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1          17376502     74.96%     74.96% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2           5804731     25.04%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total      23181233                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy   12806281931                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy    180531485                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy  12781520856                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy   7568960857                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy    194234943                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy    595690418                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40349                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40349                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136610                       # Transaction distribution
system.iobus.trans_dist::WriteResp              29882                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp       106728                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47640                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122574                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231264                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231264                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353918                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47660                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155681                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7339072                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7339072                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7496839                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36172000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            21986000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           607512131                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92695000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           148588668                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170500                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115637                       # number of replacements
system.iocache.tags.tagsinuse               11.310069                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115653                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         9129457632000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     7.399895                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     3.910174                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.462493                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.244386                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.706879                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1041045                       # Number of tag accesses
system.iocache.tags.data_accesses             1041045                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8904                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8941                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide       106728                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total       106728                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8904                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8944                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8904                       # number of overall misses
system.iocache.overall_misses::total             8944                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5195500                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1622865167                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1628060667                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide  19842621296                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total  19842621296                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5564500                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1622865167                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1628429667                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5564500                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1622865167                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1628429667                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8904                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8941                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide       106728                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total       106728                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8904                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8944                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8904                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8944                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 182262.485063                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 182089.326362                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185917.671989                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 185917.671989                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 182262.485063                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 182069.506597                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 182262.485063                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 182069.506597                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        110288                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                16227                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     6.796574                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106703                       # number of writebacks
system.iocache.writebacks::total               106703                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8904                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8941                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106728                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total       106728                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8904                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8944                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8904                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8944                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3270500                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1158690425                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1161960925                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       213000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       213000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  14292687374                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total  14292687374                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3483500                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1158690425                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1162173925                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3483500                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1158690425                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1162173925                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88391.891892                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130131.449349                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 129958.721060                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        71000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        71000                       # average WriteReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133916.941890                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133916.941890                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 130131.449349                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 129938.945103                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 130131.449349                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 129938.945103                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                  1500558                       # number of replacements
system.l2c.tags.tagsinuse                64423.791175                       # Cycle average of tags in use
system.l2c.tags.total_refs                    5010724                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1561220                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     3.209493                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle               8774171000                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   18406.054563                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   163.983954                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   204.641755                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4710.197783                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     8659.570147                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 11639.948556                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   186.392680                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   219.831325                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     3870.715230                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     6776.772016                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  9585.683167                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.280854                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002502                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.003123                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.071872                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.132135                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.177612                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002844                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.003354                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.059062                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.103405                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.146266                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.983029                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022         9890                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023          240                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        50532                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1            8                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2           96                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3          403                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4         9383                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          240                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           45                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          178                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         1652                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5116                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        43541                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.150909                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.003662                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.771057                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 65146304                       # Number of tag accesses
system.l2c.tags.data_accesses                65146304                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker         6273                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         4042                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             730934                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             606426                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher       316069                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker         6330                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         4616                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             702346                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             568034                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher       305702                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                3250772                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks         2490573                       # number of Writeback hits
system.l2c.Writeback_hits::total              2490573                       # number of Writeback hits
system.l2c.WriteInvalidateReq_hits::cpu0.data       135019                       # number of WriteInvalidateReq hits
system.l2c.WriteInvalidateReq_hits::cpu1.data       128371                       # number of WriteInvalidateReq hits
system.l2c.WriteInvalidateReq_hits::total       263390                       # number of WriteInvalidateReq hits
system.l2c.UpgradeReq_hits::cpu0.data           28214                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data           29967                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               58181                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data          6140                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data          6184                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total             12324                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            50287                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            53122                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               103409                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker          6273                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          4042                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              730934                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              656713                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher       316069                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          6330                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          4616                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              702346                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              621156                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher       305702                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 3354181                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         6273                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         4042                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             730934                       # number of overall hits
system.l2c.overall_hits::cpu0.data             656713                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher       316069                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         6330                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         4616                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             702346                       # number of overall hits
system.l2c.overall_hits::cpu1.data             621156                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher       305702                       # number of overall hits
system.l2c.overall_hits::total                3354181                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker         1959                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker         1699                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst            72396                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data           144803                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher       235787                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker         2337                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker         2129                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst            56871                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data           125845                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher       232153                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               875979                       # number of ReadReq misses
system.l2c.WriteInvalidateReq_misses::cpu0.data       452629                       # number of WriteInvalidateReq misses
system.l2c.WriteInvalidateReq_misses::cpu1.data       114950                       # number of WriteInvalidateReq misses
system.l2c.WriteInvalidateReq_misses::total       567579                       # number of WriteInvalidateReq misses
system.l2c.UpgradeReq_misses::cpu0.data         49085                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         42979                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             92064                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data         9286                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         8933                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total           18219                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          81593                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          56532                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             138125                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker         1959                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         1699                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             72396                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            226396                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       235787                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         2337                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         2129                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             56871                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            182377                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher       232153                       # number of demand (read+write) misses
system.l2c.demand_misses::total               1014104                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         1959                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         1699                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            72396                       # number of overall misses
system.l2c.overall_misses::cpu0.data           226396                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       235787                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         2337                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         2129                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            56871                       # number of overall misses
system.l2c.overall_misses::cpu1.data           182377                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher       232153                       # number of overall misses
system.l2c.overall_misses::total              1014104                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    183693028                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker    155473534                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst   6124405792                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data  13529784764                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher  31415388170                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    209221515                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker    197082496                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst   4800216916                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data  11513015623                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher  30700473496                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    98828755334                       # number of ReadReq miss cycles
system.l2c.WriteInvalidateReq_miss_latency::cpu0.data     50831909                       # number of WriteInvalidateReq miss cycles
system.l2c.WriteInvalidateReq_miss_latency::cpu1.data     41081201                       # number of WriteInvalidateReq miss cycles
system.l2c.WriteInvalidateReq_miss_latency::total     91913110                       # number of WriteInvalidateReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data    314052545                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    253554995                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    567607540                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data     59571609                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data     53385310                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total    112956919                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   7326457212                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   4778922810                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  12105380022                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    183693028                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    155473534                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   6124405792                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  20856241976                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  31415388170                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    209221515                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    197082496                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   4800216916                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  16291938433                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  30700473496                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total    110934135356                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    183693028                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    155473534                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   6124405792                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  20856241976                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  31415388170                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    209221515                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    197082496                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   4800216916                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  16291938433                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  30700473496                       # number of overall miss cycles
system.l2c.overall_miss_latency::total   110934135356                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker         8232                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         5741                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         803330                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         751229                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher       551856                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker         8667                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         6745                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         759217                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         693879                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher       537855                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            4126751                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks      2490573                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          2490573                       # number of Writeback accesses(hits+misses)
system.l2c.WriteInvalidateReq_accesses::cpu0.data       587648                       # number of WriteInvalidateReq accesses(hits+misses)
system.l2c.WriteInvalidateReq_accesses::cpu1.data       243321                       # number of WriteInvalidateReq accesses(hits+misses)
system.l2c.WriteInvalidateReq_accesses::total       830969                       # number of WriteInvalidateReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        77299                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data        72946                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total          150245                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data        15426                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data        15117                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total         30543                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       131880                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       109654                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           241534                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         8232                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         5741                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          803330                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          883109                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       551856                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         8667                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         6745                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          759217                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          803533                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher       537855                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             4368285                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         8232                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         5741                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         803330                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         883109                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       551856                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         8667                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         6745                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         759217                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         803533                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher       537855                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            4368285                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.237974                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.295941                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.090120                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.192755                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.427262                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.269643                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.315641                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.074907                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.181364                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.431627                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.212268                       # miss rate for ReadReq accesses
system.l2c.WriteInvalidateReq_miss_rate::cpu0.data     0.770238                       # miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_miss_rate::cpu1.data     0.472421                       # miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_miss_rate::total     0.683033                       # miss rate for WriteInvalidateReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.635002                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.589189                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.612759                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.601971                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.590924                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.596503                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.618691                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.515549                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.571866                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.237974                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.295941                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.090120                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.256362                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.427262                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.269643                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.315641                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.074907                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.226969                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.431627                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.232152                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.237974                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.295941                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.090120                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.256362                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.427262                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.269643                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.315641                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.074907                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.226969                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.431627                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.232152                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 93768.773864                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 91508.848735                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 84595.914028                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 93435.804258                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 133236.302977                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 89525.680359                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 92570.453734                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 84405.354504                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 91485.681775                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 132242.415545                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 112820.918463                       # average ReadReq miss latency
system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data   112.303695                       # average WriteInvalidateReq miss latency
system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data   357.383219                       # average WriteInvalidateReq miss latency
system.l2c.WriteInvalidateReq_avg_miss_latency::total   161.938884                       # average WriteInvalidateReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  6398.136804                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  5899.508946                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  6165.358229                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  6415.206655                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5976.190529                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  6199.951644                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 89792.717660                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 84534.826470                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 87640.760340                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 93768.773864                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 91508.848735                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 84595.914028                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 92122.837753                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 133236.302977                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89525.680359                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 92570.453734                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 84405.354504                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 89331.102239                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 132242.415545                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 109391.280733                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 93768.773864                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 91508.848735                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 84595.914028                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 92122.837753                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 133236.302977                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89525.680359                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 92570.453734                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 84405.354504                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 89331.102239                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 132242.415545                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 109391.280733                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs              1791                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                       28                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs     63.964286                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks             1148541                       # number of writebacks
system.l2c.writebacks::total                  1148541                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst           220                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data            34                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst           280                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data            31                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total               565                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst            220                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             34                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst            280                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             31                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                565                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst           220                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            34                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst           280                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            31                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               565                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         1959                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         1699                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst        72176                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data       144769                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       235787                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         2337                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         2129                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst        56591                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data       125814                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher       232153                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          875414                       # number of ReadReq MSHR misses
system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data       452629                       # number of WriteInvalidateReq MSHR misses
system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data       114950                       # number of WriteInvalidateReq MSHR misses
system.l2c.WriteInvalidateReq_mshr_misses::total       567579                       # number of WriteInvalidateReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        49085                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        42979                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        92064                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data         9286                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         8933                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total        18219                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        81593                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        56532                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        138125                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         1959                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         1699                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        72176                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       226362                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       235787                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         2337                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         2129                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        56591                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       182346                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       232153                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total          1013539                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         1959                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         1699                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        72176                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       226362                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       235787                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         2337                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         2129                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        56591                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       182346                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       232153                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total         1013539                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        52307                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        31604                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst           90                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data         7024                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        91025                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        30977                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         7515                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        38492                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        52307                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        62581                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst           90                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        14539                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total       129517                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker    158938472                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker    134003964                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst   5203434958                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data  11714509236                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher  28520645338                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker    179744471                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker    170218000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst   4069447334                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data   9933395627                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher  27845565280                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total  87929902680                       # number of ReadReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data  15184820591                       # number of WriteInvalidateReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data   3681276299                       # number of WriteInvalidateReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::total  18866096890                       # number of WriteInvalidateReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    873684340                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    765163234                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total   1638847574                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    165173761                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    159092905                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total    324266666                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   6306752788                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   4071633688                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  10378386476                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    158938472                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    134003964                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   5203434958                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  18021262024                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  28520645338                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    179744471                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    170218000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   4069447334                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  14005029315                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  27845565280                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  98308289156                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    158938472                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    134003964                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   5203434958                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  18021262024                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  28520645338                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    179744471                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    170218000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   4069447334                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  14005029315                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  27845565280                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  98308289156                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   3188012750                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   4742528250                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      5282500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    634028250                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   8569851750                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4479331501                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    791938501                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   5271270002                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   3188012750                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   9221859751                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      5282500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1425966751                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  13841121752                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.237974                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.295941                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.089846                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.192710                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.427262                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.269643                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.315641                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.074539                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.181320                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.431627                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.212132                       # mshr miss rate for ReadReq accesses
system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.770238                       # mshr miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.472421                       # mshr miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_mshr_miss_rate::total     0.683033                       # mshr miss rate for WriteInvalidateReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.635002                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.589189                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.612759                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.601971                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.590924                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.596503                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.618691                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.515549                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.571866                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.237974                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.295941                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.089846                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.256324                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.427262                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.269643                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.315641                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.074539                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.226930                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.431627                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.232022                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.237974                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.295941                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.089846                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.256324                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.427262                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.269643                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.315641                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.074539                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.226930                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.431627                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.232022                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 81132.451251                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 78872.256622                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72093.700926                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 80918.630618                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 120959.363061                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76912.482242                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 79952.090183                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71909.797212                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 78953.022931                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119944.886691                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 100443.793085                       # average ReadReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33548.050591                       # average WriteInvalidateReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32025.022175                       # average WriteInvalidateReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 33239.596409                       # average WriteInvalidateReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17799.416115                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17803.188394                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17801.177159                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17787.396188                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17809.571812                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17798.269170                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 77295.267829                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72023.520979                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 75137.639645                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 81132.451251                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78872.256622                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72093.700926                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79612.576422                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 120959.363061                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76912.482242                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79952.090183                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71909.797212                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 76804.697197                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119944.886691                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 96995.072864                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 81132.451251                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78872.256622                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72093.700926                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79612.576422                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 120959.363061                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76912.482242                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79952.090183                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71909.797212                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 76804.697197                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119944.886691                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 96995.072864                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60948.109240                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 150061.012846                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 58694.444444                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 90265.980923                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 94148.330129                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 144601.849792                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 105381.038057                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 136944.559961                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60948.109240                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 147358.779038                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 58694.444444                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 98078.736571                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 106867.220149                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              975380                       # Transaction distribution
system.membus.trans_dist::ReadResp             975380                       # Transaction distribution
system.membus.trans_dist::WriteReq              38492                       # Transaction distribution
system.membus.trans_dist::WriteResp             38492                       # Transaction distribution
system.membus.trans_dist::Writeback           1255244                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq       671368                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp       671368                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           435292                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq         320448                       # Transaction distribution
system.membus.trans_dist::UpgradeResp          117663                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq           19                       # Transaction distribution
system.membus.trans_dist::ReadExReq            151367                       # Transaction distribution
system.membus.trans_dist::ReadExResp           133687                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122574                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           52                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        26446                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5296349                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      5445421                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       335920                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       335920                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                5781341                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155681                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1324                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        52892                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    177552960                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    177762857                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14095872                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total     14095872                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               191858729                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           658635                       # Total snoops (count)
system.membus.snoop_fanout::samples           3847839                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 3847839    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             3847839                       # Request fanout histogram
system.membus.reqLayer0.occupancy           109654500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               33484                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            21898998                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy         11397821385                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         6506682845                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          152058832                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             163                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              163                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.toL2Bus.trans_dist::ReadReq            5105910                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           5098639                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             38492                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            38492                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback          2490573                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq       937823                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateResp       830969                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          486096                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq        332772                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         818868                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           64                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           64                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           302211                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          302211                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8322623                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6766752                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              15089375                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    277489443                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    218349254                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              495838697                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         1695482                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          9694113                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.011945                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.108639                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                9578315     98.81%     98.81% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                 115798      1.19%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            9694113                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         8435746901                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          2506500                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        4797228870                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        4287100444                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------