stats.txt revision 10636
110515SAli.Saidi@ARM.com 210515SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 310628Sandreas.hansson@arm.comsim_seconds 47.355615 # Number of seconds simulated 410628Sandreas.hansson@arm.comsim_ticks 47355615197500 # Number of ticks simulated 510628Sandreas.hansson@arm.comfinal_tick 47355615197500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 710636Snilay@cs.wisc.eduhost_inst_rate 119180 # Simulator instruction rate (inst/s) 810636Snilay@cs.wisc.eduhost_op_rate 140167 # Simulator op (including micro ops) rate (op/s) 910636Snilay@cs.wisc.eduhost_tick_rate 6305360463 # Simulator tick rate (ticks/s) 1010636Snilay@cs.wisc.eduhost_mem_usage 747912 # Number of bytes of host memory used 1110636Snilay@cs.wisc.eduhost_seconds 7510.37 # Real time elapsed on the host 1210628Sandreas.hansson@arm.comsim_insts 895084962 # Number of instructions simulated 1310628Sandreas.hansson@arm.comsim_ops 1052703090 # Number of ops (including micro ops) simulated 1410515SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610628Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 106496 # Number of bytes read from this memory 1710628Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 83264 # Number of bytes read from this memory 1810636Snilay@cs.wisc.edusystem.physmem.bytes_read::cpu0.inst 8104128 # Number of bytes read from this memory 1910636Snilay@cs.wisc.edusystem.physmem.bytes_read::cpu0.data 10821016 # Number of bytes read from this memory 2010628Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.l2cache.prefetcher 17557952 # Number of bytes read from this memory 2110628Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 158592 # Number of bytes read from this memory 2210628Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.itb.walker 147776 # Number of bytes read from this memory 2310636Snilay@cs.wisc.edusystem.physmem.bytes_read::cpu1.inst 3589696 # Number of bytes read from this memory 2410636Snilay@cs.wisc.edusystem.physmem.bytes_read::cpu1.data 10178208 # Number of bytes read from this memory 2510628Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.l2cache.prefetcher 16399360 # Number of bytes read from this memory 2610628Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 427968 # Number of bytes read from this memory 2710628Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 67574456 # Number of bytes read from this memory 2810628Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 8104128 # Number of instructions bytes read from this memory 2910628Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 3589696 # Number of instructions bytes read from this memory 3010628Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 11693824 # Number of instructions bytes read from this memory 3110628Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 78266240 # Number of bytes written to this memory 3210636Snilay@cs.wisc.edusystem.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory 3310636Snilay@cs.wisc.edusystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3410628Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 78287056 # Number of bytes written to this memory 3510628Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 1664 # Number of read requests responded to by this memory 3610628Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.itb.walker 1301 # Number of read requests responded to by this memory 3710636Snilay@cs.wisc.edusystem.physmem.num_reads::cpu0.inst 126627 # Number of read requests responded to by this memory 3810636Snilay@cs.wisc.edusystem.physmem.num_reads::cpu0.data 169100 # Number of read requests responded to by this memory 3910628Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.l2cache.prefetcher 274343 # Number of read requests responded to by this memory 4010628Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 2478 # Number of read requests responded to by this memory 4110628Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.itb.walker 2309 # Number of read requests responded to by this memory 4210636Snilay@cs.wisc.edusystem.physmem.num_reads::cpu1.inst 56089 # Number of read requests responded to by this memory 4310636Snilay@cs.wisc.edusystem.physmem.num_reads::cpu1.data 159049 # Number of read requests responded to by this memory 4410628Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.l2cache.prefetcher 256240 # Number of read requests responded to by this memory 4510628Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 6687 # Number of read requests responded to by this memory 4610628Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1055887 # Number of read requests responded to by this memory 4710628Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 1222910 # Number of write requests responded to by this memory 4810636Snilay@cs.wisc.edusystem.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory 4910636Snilay@cs.wisc.edusystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 5010628Sandreas.hansson@arm.comsystem.physmem.num_writes::total 1225513 # Number of write requests responded to by this memory 5110628Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 2249 # Total read bandwidth from this memory (bytes/s) 5210628Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.itb.walker 1758 # Total read bandwidth from this memory (bytes/s) 5310636Snilay@cs.wisc.edusystem.physmem.bw_read::cpu0.inst 171133 # Total read bandwidth from this memory (bytes/s) 5410636Snilay@cs.wisc.edusystem.physmem.bw_read::cpu0.data 228505 # Total read bandwidth from this memory (bytes/s) 5510628Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.l2cache.prefetcher 370768 # Total read bandwidth from this memory (bytes/s) 5610628Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 3349 # Total read bandwidth from this memory (bytes/s) 5710628Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.itb.walker 3121 # Total read bandwidth from this memory (bytes/s) 5810636Snilay@cs.wisc.edusystem.physmem.bw_read::cpu1.inst 75803 # Total read bandwidth from this memory (bytes/s) 5910636Snilay@cs.wisc.edusystem.physmem.bw_read::cpu1.data 214931 # Total read bandwidth from this memory (bytes/s) 6010628Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.l2cache.prefetcher 346302 # Total read bandwidth from this memory (bytes/s) 6110628Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 9037 # Total read bandwidth from this memory (bytes/s) 6210628Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1426958 # Total read bandwidth from this memory (bytes/s) 6310628Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 171133 # Instruction read bandwidth from this memory (bytes/s) 6410628Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 75803 # Instruction read bandwidth from this memory (bytes/s) 6510628Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 246936 # Instruction read bandwidth from this memory (bytes/s) 6610628Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 1652734 # Write bandwidth from this memory (bytes/s) 6710636Snilay@cs.wisc.edusystem.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s) 6810636Snilay@cs.wisc.edusystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 6910628Sandreas.hansson@arm.comsystem.physmem.bw_write::total 1653174 # Write bandwidth from this memory (bytes/s) 7010628Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 1652734 # Total bandwidth to/from this memory (bytes/s) 7110628Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 2249 # Total bandwidth to/from this memory (bytes/s) 7210628Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.itb.walker 1758 # Total bandwidth to/from this memory (bytes/s) 7310636Snilay@cs.wisc.edusystem.physmem.bw_total::cpu0.inst 171133 # Total bandwidth to/from this memory (bytes/s) 7410636Snilay@cs.wisc.edusystem.physmem.bw_total::cpu0.data 228945 # Total bandwidth to/from this memory (bytes/s) 7510628Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.l2cache.prefetcher 370768 # Total bandwidth to/from this memory (bytes/s) 7610628Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 3349 # Total bandwidth to/from this memory (bytes/s) 7710628Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.itb.walker 3121 # Total bandwidth to/from this memory (bytes/s) 7810636Snilay@cs.wisc.edusystem.physmem.bw_total::cpu1.inst 75803 # Total bandwidth to/from this memory (bytes/s) 7910636Snilay@cs.wisc.edusystem.physmem.bw_total::cpu1.data 214931 # Total bandwidth to/from this memory (bytes/s) 8010628Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.l2cache.prefetcher 346302 # Total bandwidth to/from this memory (bytes/s) 8110628Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 9037 # Total bandwidth to/from this memory (bytes/s) 8210628Sandreas.hansson@arm.comsystem.physmem.bw_total::total 3080131 # Total bandwidth to/from this memory (bytes/s) 8310628Sandreas.hansson@arm.comsystem.physmem.readReqs 1055887 # Number of read requests accepted 8410628Sandreas.hansson@arm.comsystem.physmem.writeReqs 1888199 # Number of write requests accepted 8510628Sandreas.hansson@arm.comsystem.physmem.readBursts 1055887 # Number of DRAM read bursts, including those serviced by the write queue 8610628Sandreas.hansson@arm.comsystem.physmem.writeBursts 1888199 # Number of DRAM write bursts, including those merged in the write queue 8710628Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 67557888 # Total number of bytes read from DRAM 8810628Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 18880 # Total number of bytes read from write queue 8910628Sandreas.hansson@arm.comsystem.physmem.bytesWritten 120408192 # Total number of bytes written to DRAM 9010628Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 67574456 # Total read bytes from the system interface side 9110628Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 120698960 # Total written bytes from the system interface side 9210628Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 295 # Number of DRAM read bursts serviced by the write queue 9310628Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 6789 # Number of DRAM write bursts merged with an existing one 9410628Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 114993 # Number of requests that are neither read nor write 9510628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 58784 # Per bank write bursts 9610628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 68771 # Per bank write bursts 9710628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 59130 # Per bank write bursts 9810628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 67531 # Per bank write bursts 9910628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 66855 # Per bank write bursts 10010628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 75133 # Per bank write bursts 10110628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 65903 # Per bank write bursts 10210628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 67407 # Per bank write bursts 10310628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 54196 # Per bank write bursts 10410628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 110706 # Per bank write bursts 10510628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 54461 # Per bank write bursts 10610628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 64104 # Per bank write bursts 10710628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 57097 # Per bank write bursts 10810628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 66166 # Per bank write bursts 10910628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 60751 # Per bank write bursts 11010628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 58597 # Per bank write bursts 11110628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 116651 # Per bank write bursts 11210628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 125865 # Per bank write bursts 11310628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 118664 # Per bank write bursts 11410628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 124773 # Per bank write bursts 11510628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 121001 # Per bank write bursts 11610628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 125597 # Per bank write bursts 11710628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 113710 # Per bank write bursts 11810628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 116980 # Per bank write bursts 11910628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 110183 # Per bank write bursts 12010628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 114411 # Per bank write bursts 12110628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 109841 # Per bank write bursts 12210628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 116847 # Per bank write bursts 12310628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 116927 # Per bank write bursts 12410628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 118874 # Per bank write bursts 12510628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 112844 # Per bank write bursts 12610628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 118210 # Per bank write bursts 12710515SAli.Saidi@ARM.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 12810628Sandreas.hansson@arm.comsystem.physmem.numWrRetry 5 # Number of times write queue was full causing retry 12910628Sandreas.hansson@arm.comsystem.physmem.totGap 47355613259000 # Total gap between requests 13010515SAli.Saidi@ARM.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 13110515SAli.Saidi@ARM.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 13210515SAli.Saidi@ARM.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 13310515SAli.Saidi@ARM.comsystem.physmem.readPktSize::3 37 # Read request sizes (log2) 13410515SAli.Saidi@ARM.comsystem.physmem.readPktSize::4 5 # Read request sizes (log2) 13510515SAli.Saidi@ARM.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 13610628Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 1055845 # Read request sizes (log2) 13710515SAli.Saidi@ARM.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 13810515SAli.Saidi@ARM.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 13910515SAli.Saidi@ARM.comsystem.physmem.writePktSize::2 2 # Write request sizes (log2) 14010515SAli.Saidi@ARM.comsystem.physmem.writePktSize::3 2601 # Write request sizes (log2) 14110515SAli.Saidi@ARM.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 14210515SAli.Saidi@ARM.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 14310628Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 1885596 # Write request sizes (log2) 14410628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 695873 # What read queue length does an incoming req see 14510628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 103690 # What read queue length does an incoming req see 14610628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 49130 # What read queue length does an incoming req see 14710628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 41556 # What read queue length does an incoming req see 14810628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 38114 # What read queue length does an incoming req see 14910628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 34076 # What read queue length does an incoming req see 15010628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 30233 # What read queue length does an incoming req see 15110628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 25733 # What read queue length does an incoming req see 15210628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 21396 # What read queue length does an incoming req see 15310628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 5411 # What read queue length does an incoming req see 15410628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 3052 # What read queue length does an incoming req see 15510628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 2413 # What read queue length does an incoming req see 15610628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 1873 # What read queue length does an incoming req see 15710628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 1458 # What read queue length does an incoming req see 15810628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 532 # What read queue length does an incoming req see 15910628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 364 # What read queue length does an incoming req see 16010628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 274 # What read queue length does an incoming req see 16110628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 225 # What read queue length does an incoming req see 16210628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 107 # What read queue length does an incoming req see 16310628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 80 # What read queue length does an incoming req see 16410628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see 16510628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 16610628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 16710628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 16810515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 16910515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 17010515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 17110515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 17210515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 17310515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 17410515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 17510515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 17610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 17710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 17810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 17910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 18010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 18110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 18210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 18310515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 18410515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 18510515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 18610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 18710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 18810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 18910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 19010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 19110628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 41751 # What write queue length does an incoming req see 19210628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 61472 # What write queue length does an incoming req see 19310628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 87023 # What write queue length does an incoming req see 19410628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 107335 # What write queue length does an incoming req see 19510628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 120415 # What write queue length does an incoming req see 19610628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 125723 # What write queue length does an incoming req see 19710628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 127870 # What write queue length does an incoming req see 19810628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 127803 # What write queue length does an incoming req see 19910628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 120389 # What write queue length does an incoming req see 20010628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 118443 # What write queue length does an incoming req see 20110628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 115533 # What write queue length does an incoming req see 20210628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 109052 # What write queue length does an incoming req see 20310628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 105629 # What write queue length does an incoming req see 20410628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 105973 # What write queue length does an incoming req see 20510628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 96497 # What write queue length does an incoming req see 20610628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 93321 # What write queue length does an incoming req see 20710628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 90489 # What write queue length does an incoming req see 20810628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 85925 # What write queue length does an incoming req see 20910628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 6797 # What write queue length does an incoming req see 21010628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 5240 # What write queue length does an incoming req see 21110628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 4118 # What write queue length does an incoming req see 21210628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 3375 # What write queue length does an incoming req see 21310628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 2886 # What write queue length does an incoming req see 21410628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 2547 # What write queue length does an incoming req see 21510628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 2242 # What write queue length does an incoming req see 21610628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 2060 # What write queue length does an incoming req see 21710628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 1788 # What write queue length does an incoming req see 21810628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 1506 # What write queue length does an incoming req see 21910628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 1337 # What write queue length does an incoming req see 22010628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 1130 # What write queue length does an incoming req see 22110628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 995 # What write queue length does an incoming req see 22210628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 819 # What write queue length does an incoming req see 22310628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 707 # What write queue length does an incoming req see 22410628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 610 # What write queue length does an incoming req see 22510628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 539 # What write queue length does an incoming req see 22610628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 455 # What write queue length does an incoming req see 22710628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 369 # What write queue length does an incoming req see 22810628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 308 # What write queue length does an incoming req see 22910628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 249 # What write queue length does an incoming req see 23010628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 191 # What write queue length does an incoming req see 23110585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 151 # What write queue length does an incoming req see 23210628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 129 # What write queue length does an incoming req see 23310628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 76 # What write queue length does an incoming req see 23410628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 44 # What write queue length does an incoming req see 23510628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 21 # What write queue length does an incoming req see 23610628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 16 # What write queue length does an incoming req see 23710628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 17 # What write queue length does an incoming req see 23810628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 18 # What write queue length does an incoming req see 23910628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 12 # What write queue length does an incoming req see 24010628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 1046123 # Bytes accessed per row activation 24110628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 179.678328 # Bytes accessed per row activation 24210628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 108.587927 # Bytes accessed per row activation 24310628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 250.922876 # Bytes accessed per row activation 24410628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 666099 63.67% 63.67% # Bytes accessed per row activation 24510628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 200536 19.17% 82.84% # Bytes accessed per row activation 24610628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 50293 4.81% 87.65% # Bytes accessed per row activation 24710628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 24222 2.32% 89.97% # Bytes accessed per row activation 24810628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 17786 1.70% 91.67% # Bytes accessed per row activation 24910628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 12328 1.18% 92.84% # Bytes accessed per row activation 25010628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 8853 0.85% 93.69% # Bytes accessed per row activation 25110628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 7558 0.72% 94.41% # Bytes accessed per row activation 25210628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 58448 5.59% 100.00% # Bytes accessed per row activation 25310628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 1046123 # Bytes accessed per row activation 25410628Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 79224 # Reads before turning the bus around for writes 25510628Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 13.323930 # Reads before turning the bus around for writes 25610628Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 140.057237 # Reads before turning the bus around for writes 25710628Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-1023 79222 100.00% 100.00% # Reads before turning the bus around for writes 25810585Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 25910628Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes 26010628Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 79224 # Reads before turning the bus around for writes 26110628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 79224 # Writes before turning the bus around for reads 26210628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 23.747576 # Writes before turning the bus around for reads 26310628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 20.323530 # Writes before turning the bus around for reads 26410628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 23.901705 # Writes before turning the bus around for reads 26510628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16-23 65925 83.21% 83.21% # Writes before turning the bus around for reads 26610628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24-31 5556 7.01% 90.23% # Writes before turning the bus around for reads 26710628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32-39 2071 2.61% 92.84% # Writes before turning the bus around for reads 26810628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::40-47 1166 1.47% 94.31% # Writes before turning the bus around for reads 26910628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48-55 1087 1.37% 95.68% # Writes before turning the bus around for reads 27010628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::56-63 456 0.58% 96.26% # Writes before turning the bus around for reads 27110628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::64-71 393 0.50% 96.76% # Writes before turning the bus around for reads 27210628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::72-79 290 0.37% 97.12% # Writes before turning the bus around for reads 27310628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::80-87 329 0.42% 97.54% # Writes before turning the bus around for reads 27410628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::88-95 179 0.23% 97.76% # Writes before turning the bus around for reads 27510628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::96-103 294 0.37% 98.13% # Writes before turning the bus around for reads 27610628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::104-111 101 0.13% 98.26% # Writes before turning the bus around for reads 27710628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::112-119 139 0.18% 98.44% # Writes before turning the bus around for reads 27810628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::120-127 103 0.13% 98.57% # Writes before turning the bus around for reads 27910628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::128-135 155 0.20% 98.76% # Writes before turning the bus around for reads 28010628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::136-143 83 0.10% 98.87% # Writes before turning the bus around for reads 28110628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::144-151 89 0.11% 98.98% # Writes before turning the bus around for reads 28210628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::152-159 58 0.07% 99.05% # Writes before turning the bus around for reads 28310628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::160-167 57 0.07% 99.13% # Writes before turning the bus around for reads 28410628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::168-175 65 0.08% 99.21% # Writes before turning the bus around for reads 28510628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::176-183 66 0.08% 99.29% # Writes before turning the bus around for reads 28610628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::184-191 81 0.10% 99.39% # Writes before turning the bus around for reads 28710628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::192-199 58 0.07% 99.47% # Writes before turning the bus around for reads 28810628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::200-207 58 0.07% 99.54% # Writes before turning the bus around for reads 28910628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::208-215 69 0.09% 99.63% # Writes before turning the bus around for reads 29010628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::216-223 72 0.09% 99.72% # Writes before turning the bus around for reads 29110628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::224-231 57 0.07% 99.79% # Writes before turning the bus around for reads 29210628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::232-239 44 0.06% 99.84% # Writes before turning the bus around for reads 29310628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::240-247 31 0.04% 99.88% # Writes before turning the bus around for reads 29410628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::248-255 21 0.03% 99.91% # Writes before turning the bus around for reads 29510628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::256-263 22 0.03% 99.94% # Writes before turning the bus around for reads 29610628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::264-271 15 0.02% 99.96% # Writes before turning the bus around for reads 29710628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::272-279 7 0.01% 99.97% # Writes before turning the bus around for reads 29810628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::280-287 6 0.01% 99.97% # Writes before turning the bus around for reads 29910628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::288-295 3 0.00% 99.98% # Writes before turning the bus around for reads 30010628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::296-303 1 0.00% 99.98% # Writes before turning the bus around for reads 30110628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::304-311 3 0.00% 99.98% # Writes before turning the bus around for reads 30210628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::312-319 1 0.00% 99.98% # Writes before turning the bus around for reads 30310628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::320-327 1 0.00% 99.98% # Writes before turning the bus around for reads 30410628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::328-335 1 0.00% 99.99% # Writes before turning the bus around for reads 30510628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::336-343 1 0.00% 99.99% # Writes before turning the bus around for reads 30610628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::344-351 1 0.00% 99.99% # Writes before turning the bus around for reads 30710628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::352-359 2 0.00% 99.99% # Writes before turning the bus around for reads 30810628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::360-367 1 0.00% 99.99% # Writes before turning the bus around for reads 30910628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::368-375 1 0.00% 99.99% # Writes before turning the bus around for reads 31010628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::376-383 1 0.00% 99.99% # Writes before turning the bus around for reads 31110628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::384-391 2 0.00% 100.00% # Writes before turning the bus around for reads 31210628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::456-463 1 0.00% 100.00% # Writes before turning the bus around for reads 31310628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::496-503 1 0.00% 100.00% # Writes before turning the bus around for reads 31410628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 79224 # Writes before turning the bus around for reads 31510628Sandreas.hansson@arm.comsystem.physmem.totQLat 39480003252 # Total ticks spent queuing 31610628Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 59272353252 # Total ticks spent from burst creation until serviced by the DRAM 31710628Sandreas.hansson@arm.comsystem.physmem.totBusLat 5277960000 # Total ticks spent in databus transfers 31810628Sandreas.hansson@arm.comsystem.physmem.avgQLat 37400.82 # Average queueing delay per DRAM burst 31910515SAli.Saidi@ARM.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 32010628Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 56150.82 # Average memory access latency per DRAM burst 32110628Sandreas.hansson@arm.comsystem.physmem.avgRdBW 1.43 # Average DRAM read bandwidth in MiByte/s 32210628Sandreas.hansson@arm.comsystem.physmem.avgWrBW 2.54 # Average achieved write bandwidth in MiByte/s 32310628Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 1.43 # Average system read bandwidth in MiByte/s 32410628Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 2.55 # Average system write bandwidth in MiByte/s 32510515SAli.Saidi@ARM.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 32610515SAli.Saidi@ARM.comsystem.physmem.busUtil 0.03 # Data bus utilization in percentage 32710628Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 32810515SAli.Saidi@ARM.comsystem.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 32910628Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 33010628Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 24.00 # Average write queue length when enqueuing 33110628Sandreas.hansson@arm.comsystem.physmem.readRowHits 797783 # Number of row buffer hits during reads 33210628Sandreas.hansson@arm.comsystem.physmem.writeRowHits 1093063 # Number of row buffer hits during writes 33310628Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 75.58 # Row buffer hit rate for reads 33410628Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 58.10 # Row buffer hit rate for writes 33510628Sandreas.hansson@arm.comsystem.physmem.avgGap 16084996.59 # Average gap between requests 33610628Sandreas.hansson@arm.comsystem.physmem.pageHitRate 64.38 # Row buffer hit rate, read and write combined 33710628Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 4126437000 # Energy for activate commands per rank (pJ) 33810628Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 2251528125 # Energy for precharge commands per rank (pJ) 33910628Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 4130209200 # Energy for read commands per rank (pJ) 34010628Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 6241801680 # Energy for write commands per rank (pJ) 34110628Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 3093038526240 # Energy for refresh commands per rank (pJ) 34210628Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 1193820708150 # Energy for active background per rank (pJ) 34310628Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 27366157608000 # Energy for precharge background per rank (pJ) 34410628Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 31669766818395 # Total energy per rank (pJ) 34510628Sandreas.hansson@arm.comsystem.physmem_0.averagePower 668.764772 # Core power per rank (mW) 34610628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 45525574397500 # Time in different power states 34710628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 1581308040000 # Time in different power states 34810628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 34910628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 248732168750 # Time in different power states 35010628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 35110628Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 3782252880 # Energy for activate commands per rank (pJ) 35210628Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 2063729250 # Energy for precharge commands per rank (pJ) 35310628Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 4103353800 # Energy for read commands per rank (pJ) 35410628Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 5949527760 # Energy for write commands per rank (pJ) 35510628Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 3093038526240 # Energy for refresh commands per rank (pJ) 35610628Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 1183965961905 # Energy for active background per rank (pJ) 35710628Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 27374802122250 # Energy for precharge background per rank (pJ) 35810628Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 31667705474085 # Total energy per rank (pJ) 35910628Sandreas.hansson@arm.comsystem.physmem_1.averagePower 668.721243 # Core power per rank (mW) 36010628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 45539970549502 # Time in different power states 36110628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 1581308040000 # Time in different power states 36210628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 36310628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 234336016748 # Time in different power states 36410628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 36510636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory 36610636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 36710636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory 36810636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 36910515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory 37010515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory 37110515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory 37210515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory 37310636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory 37410636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 37510636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory 37610636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 37710515SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory 37810636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) 37910636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 38010515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s) 38110636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 38210515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s) 38310515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) 38410515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s) 38510515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) 38610636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) 38710636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 38810515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s) 38910636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 39010515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) 39110585Sandreas.hansson@arm.comsystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 39210585Sandreas.hansson@arm.comsystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 39310585Sandreas.hansson@arm.comsystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 39410585Sandreas.hansson@arm.comsystem.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 39510585Sandreas.hansson@arm.comsystem.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 39610585Sandreas.hansson@arm.comsystem.cf0.dma_write_txs 1670 # Number of DMA write transactions. 39710628Sandreas.hansson@arm.comsystem.cpu0.branchPred.lookups 131272413 # Number of BP lookups 39810628Sandreas.hansson@arm.comsystem.cpu0.branchPred.condPredicted 92904470 # Number of conditional branches predicted 39910628Sandreas.hansson@arm.comsystem.cpu0.branchPred.condIncorrect 6038757 # Number of conditional branches incorrect 40010628Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBLookups 98925935 # Number of BTB lookups 40110628Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBHits 71271707 # Number of BTB hits 40210585Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 40310628Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBHitPct 72.045523 # BTB Hit Percentage 40410628Sandreas.hansson@arm.comsystem.cpu0.branchPred.usedRAS 15434878 # Number of times the RAS was used to get a target. 40510628Sandreas.hansson@arm.comsystem.cpu0.branchPred.RASInCorrect 1076370 # Number of incorrect RAS predictions. 40610515SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 40710628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 40810628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 40910628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 41010628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 41110628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 41210628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 41310628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 41410628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 41510585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 41610585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 41710585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 41810585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 41910585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 42010585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 42110585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 42210585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 42310585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 42410585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 42510585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 42610585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 42710585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 42810585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 42910585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 43010585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 43110585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 43210585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 43310585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 43410585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 43510585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 43610628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walks 271399 # Table walker walks requested 43710628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLong 271399 # Table walker walks initiated with long descriptors 43810628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8182 # Level at which table walker walks with long descriptors terminate 43910628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level3 72706 # Level at which table walker walks with long descriptors terminate 44010628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 271399 # Table walker wait (enqueue to first request) latency 44110628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0 271399 100.00% 100.00% # Table walker wait (enqueue to first request) latency 44210628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 271399 # Table walker wait (enqueue to first request) latency 44310628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::samples 80888 # Table walker service (enqueue to completion) latency 44410628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::mean 17168.766430 # Table walker service (enqueue to completion) latency 44510628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::gmean 15272.701717 # Table walker service (enqueue to completion) latency 44610628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::stdev 12980.054286 # Table walker service (enqueue to completion) latency 44710628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::0-32767 77350 95.63% 95.63% # Table walker service (enqueue to completion) latency 44810628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::32768-65535 2802 3.46% 99.09% # Table walker service (enqueue to completion) latency 44910628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::65536-98303 370 0.46% 99.55% # Table walker service (enqueue to completion) latency 45010628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::98304-131071 250 0.31% 99.86% # Table walker service (enqueue to completion) latency 45110628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::131072-163839 18 0.02% 99.88% # Table walker service (enqueue to completion) latency 45210628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::163840-196607 21 0.03% 99.90% # Table walker service (enqueue to completion) latency 45310628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::196608-229375 23 0.03% 99.93% # Table walker service (enqueue to completion) latency 45410628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::229376-262143 10 0.01% 99.95% # Table walker service (enqueue to completion) latency 45510628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::262144-294911 23 0.03% 99.97% # Table walker service (enqueue to completion) latency 45610628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::294912-327679 5 0.01% 99.98% # Table walker service (enqueue to completion) latency 45710628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency 45810628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency 45910628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 46010628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 46110628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 46210628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::total 80888 # Table walker service (enqueue to completion) latency 46310628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::samples 644436704 # Table walker pending requests distribution 46410628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::0 644436704 100.00% 100.00% # Table walker pending requests distribution 46510628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::total 644436704 # Table walker pending requests distribution 46610628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 72706 89.88% 89.88% # Table walker page sizes translated 46710628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::2M 8182 10.12% 100.00% # Table walker page sizes translated 46810628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 80888 # Table walker page sizes translated 46910628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 271399 # Table walker requests started/completed, data/inst 47010628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 47110628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 271399 # Table walker requests started/completed, data/inst 47210628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 80888 # Table walker requests started/completed, data/inst 47310628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 47410628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 80888 # Table walker requests started/completed, data/inst 47510628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 352287 # Table walker requests started/completed, data/inst 47610585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_hits 0 # ITB inst hits 47710585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_misses 0 # ITB inst misses 47810628Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 83830376 # DTB read hits 47910628Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 224800 # DTB read misses 48010628Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 74836136 # DTB write hits 48110628Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 46599 # DTB write misses 48210585Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 48310585Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 48410628Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 42371 # Number of times TLB was flushed by MVA & ASID 48510628Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID 48610628Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_entries 31986 # Number of entries that have been flushed from TLB 48710628Sandreas.hansson@arm.comsystem.cpu0.dtb.align_faults 2076 # Number of TLB faults due to alignment restrictions 48810628Sandreas.hansson@arm.comsystem.cpu0.dtb.prefetch_faults 8713 # Number of TLB faults due to prefetch 48910585Sandreas.hansson@arm.comsystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 49010628Sandreas.hansson@arm.comsystem.cpu0.dtb.perms_faults 10302 # Number of TLB faults due to permissions restrictions 49110628Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 84055176 # DTB read accesses 49210628Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 74882735 # DTB write accesses 49310585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 49410628Sandreas.hansson@arm.comsystem.cpu0.dtb.hits 158666512 # DTB hits 49510628Sandreas.hansson@arm.comsystem.cpu0.dtb.misses 271399 # DTB misses 49610628Sandreas.hansson@arm.comsystem.cpu0.dtb.accesses 158937911 # DTB accesses 49710628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 49810628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 49910628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 50010628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 50110628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 50210628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 50310628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 50410628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 50510585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 50610585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 50710585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 50810585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 50910585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 51010585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 51110585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 51210585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 51310585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 51410585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 51510585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 51610585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 51710585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 51810585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 51910585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 52010585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 52110585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 52210585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 52310585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 52410585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 52510585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 52610628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walks 59516 # Table walker walks requested 52710628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLong 59516 # Table walker walks initiated with long descriptors 52810628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level2 630 # Level at which table walker walks with long descriptors terminate 52910628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level3 51758 # Level at which table walker walks with long descriptors terminate 53010628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 59516 # Table walker wait (enqueue to first request) latency 53110628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::0 59516 100.00% 100.00% # Table walker wait (enqueue to first request) latency 53210628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 59516 # Table walker wait (enqueue to first request) latency 53310628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::samples 52388 # Table walker service (enqueue to completion) latency 53410628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::mean 19494.417176 # Table walker service (enqueue to completion) latency 53510628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::gmean 17354.171367 # Table walker service (enqueue to completion) latency 53610628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::stdev 14602.329148 # Table walker service (enqueue to completion) latency 53710628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::0-32767 48500 92.58% 92.58% # Table walker service (enqueue to completion) latency 53810628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::32768-65535 3085 5.89% 98.47% # Table walker service (enqueue to completion) latency 53910628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::65536-98303 277 0.53% 99.00% # Table walker service (enqueue to completion) latency 54010628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::98304-131071 436 0.83% 99.83% # Table walker service (enqueue to completion) latency 54110628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::131072-163839 18 0.03% 99.86% # Table walker service (enqueue to completion) latency 54210628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::163840-196607 13 0.02% 99.89% # Table walker service (enqueue to completion) latency 54310628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::196608-229375 31 0.06% 99.95% # Table walker service (enqueue to completion) latency 54410628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::229376-262143 7 0.01% 99.96% # Table walker service (enqueue to completion) latency 54510628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.97% # Table walker service (enqueue to completion) latency 54610628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.98% # Table walker service (enqueue to completion) latency 54710628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency 54810628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency 54910628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 55010628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 55110628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 55210628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::total 52388 # Table walker service (enqueue to completion) latency 55310628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::samples 643764704 # Table walker pending requests distribution 55410628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::0 643764704 100.00% 100.00% # Table walker pending requests distribution 55510628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::total 643764704 # Table walker pending requests distribution 55610628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 51758 98.80% 98.80% # Table walker page sizes translated 55710628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::2M 630 1.20% 100.00% # Table walker page sizes translated 55810628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 52388 # Table walker page sizes translated 55910628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 56010628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 59516 # Table walker requests started/completed, data/inst 56110628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 59516 # Table walker requests started/completed, data/inst 56210628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 56310628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52388 # Table walker requests started/completed, data/inst 56410628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 52388 # Table walker requests started/completed, data/inst 56510628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 111904 # Table walker requests started/completed, data/inst 56610628Sandreas.hansson@arm.comsystem.cpu0.itb.inst_hits 234493726 # ITB inst hits 56710628Sandreas.hansson@arm.comsystem.cpu0.itb.inst_misses 59516 # ITB inst misses 56810585Sandreas.hansson@arm.comsystem.cpu0.itb.read_hits 0 # DTB read hits 56910585Sandreas.hansson@arm.comsystem.cpu0.itb.read_misses 0 # DTB read misses 57010585Sandreas.hansson@arm.comsystem.cpu0.itb.write_hits 0 # DTB write hits 57110585Sandreas.hansson@arm.comsystem.cpu0.itb.write_misses 0 # DTB write misses 57210585Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 57310585Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 57410628Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 42371 # Number of times TLB was flushed by MVA & ASID 57510628Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID 57610628Sandreas.hansson@arm.comsystem.cpu0.itb.flush_entries 22765 # Number of entries that have been flushed from TLB 57710585Sandreas.hansson@arm.comsystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 57810585Sandreas.hansson@arm.comsystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 57910585Sandreas.hansson@arm.comsystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 58010628Sandreas.hansson@arm.comsystem.cpu0.itb.perms_faults 197741 # Number of TLB faults due to permissions restrictions 58110585Sandreas.hansson@arm.comsystem.cpu0.itb.read_accesses 0 # DTB read accesses 58210585Sandreas.hansson@arm.comsystem.cpu0.itb.write_accesses 0 # DTB write accesses 58310628Sandreas.hansson@arm.comsystem.cpu0.itb.inst_accesses 234553242 # ITB inst accesses 58410628Sandreas.hansson@arm.comsystem.cpu0.itb.hits 234493726 # DTB hits 58510628Sandreas.hansson@arm.comsystem.cpu0.itb.misses 59516 # DTB misses 58610628Sandreas.hansson@arm.comsystem.cpu0.itb.accesses 234553242 # DTB accesses 58710628Sandreas.hansson@arm.comsystem.cpu0.numCycles 936626399 # number of cpu cycles simulated 58810585Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 58910585Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 59010628Sandreas.hansson@arm.comsystem.cpu0.committedInsts 433367687 # Number of instructions committed 59110628Sandreas.hansson@arm.comsystem.cpu0.committedOps 509515701 # Number of ops (including micro ops) committed 59210628Sandreas.hansson@arm.comsystem.cpu0.discardedOps 43981618 # Number of ops (including micro ops) which were discarded before commit 59310628Sandreas.hansson@arm.comsystem.cpu0.numFetchSuspends 3754 # Number of times Execute suspended instruction fetching 59410628Sandreas.hansson@arm.comsystem.cpu0.quiesceCycles 93775213530 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 59510628Sandreas.hansson@arm.comsystem.cpu0.cpi 2.161274 # CPI: cycles per instruction 59610628Sandreas.hansson@arm.comsystem.cpu0.ipc 0.462690 # IPC: instructions per cycle 59710585Sandreas.hansson@arm.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 59810628Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 12643 # number of quiesce instructions executed 59910628Sandreas.hansson@arm.comsystem.cpu0.tickCycles 703108983 # Number of cycles that the object actually ticked 60010628Sandreas.hansson@arm.comsystem.cpu0.idleCycles 233517416 # Total number of cycles that the object has spent stopped 60110628Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 5387052 # number of replacements 60210628Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 501.034252 # Cycle average of tags in use 60310628Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 150576282 # Total number of references to valid blocks. 60410628Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 5387564 # Sample count of references to valid blocks. 60510628Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 27.948862 # Average number of references to valid blocks. 60610628Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 4951668000 # Cycle when the warmup percentage was hit. 60710636Snilay@cs.wisc.edusystem.cpu0.dcache.tags.occ_blocks::cpu0.data 501.034252 # Average occupied blocks per requestor 60810636Snilay@cs.wisc.edusystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.978583 # Average percentage of cache occupancy 60910628Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.978583 # Average percentage of cache occupancy 61010585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 61110628Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id 61210628Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id 61310628Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id 61410585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 61510628Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 320066517 # Number of tag accesses 61610628Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 320066517 # Number of data accesses 61710636Snilay@cs.wisc.edusystem.cpu0.dcache.ReadReq_hits::cpu0.data 77114778 # number of ReadReq hits 61810628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 77114778 # number of ReadReq hits 61910636Snilay@cs.wisc.edusystem.cpu0.dcache.WriteReq_hits::cpu0.data 69351990 # number of WriteReq hits 62010628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 69351990 # number of WriteReq hits 62110636Snilay@cs.wisc.edusystem.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 251432 # number of WriteInvalidateReq hits 62210628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_hits::total 251432 # number of WriteInvalidateReq hits 62310636Snilay@cs.wisc.edusystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1745310 # number of LoadLockedReq hits 62410628Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 1745310 # number of LoadLockedReq hits 62510636Snilay@cs.wisc.edusystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 1668274 # number of StoreCondReq hits 62610628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 1668274 # number of StoreCondReq hits 62710636Snilay@cs.wisc.edusystem.cpu0.dcache.demand_hits::cpu0.data 146466768 # number of demand (read+write) hits 62810628Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 146466768 # number of demand (read+write) hits 62910636Snilay@cs.wisc.edusystem.cpu0.dcache.overall_hits::cpu0.data 146466768 # number of overall hits 63010628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 146466768 # number of overall hits 63110636Snilay@cs.wisc.edusystem.cpu0.dcache.ReadReq_misses::cpu0.data 3852692 # number of ReadReq misses 63210628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 3852692 # number of ReadReq misses 63310636Snilay@cs.wisc.edusystem.cpu0.dcache.WriteReq_misses::cpu0.data 2255601 # number of WriteReq misses 63410628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 2255601 # number of WriteReq misses 63510636Snilay@cs.wisc.edusystem.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 766100 # number of WriteInvalidateReq misses 63610628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_misses::total 766100 # number of WriteInvalidateReq misses 63710636Snilay@cs.wisc.edusystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 104059 # number of LoadLockedReq misses 63810628Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 104059 # number of LoadLockedReq misses 63910636Snilay@cs.wisc.edusystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 180014 # number of StoreCondReq misses 64010628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 180014 # number of StoreCondReq misses 64110636Snilay@cs.wisc.edusystem.cpu0.dcache.demand_misses::cpu0.data 6108293 # number of demand (read+write) misses 64210628Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 6108293 # number of demand (read+write) misses 64310636Snilay@cs.wisc.edusystem.cpu0.dcache.overall_misses::cpu0.data 6108293 # number of overall misses 64410628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 6108293 # number of overall misses 64510636Snilay@cs.wisc.edusystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 54452724607 # number of ReadReq miss cycles 64610628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 54452724607 # number of ReadReq miss cycles 64710636Snilay@cs.wisc.edusystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 41906959422 # number of WriteReq miss cycles 64810628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 41906959422 # number of WriteReq miss cycles 64910636Snilay@cs.wisc.edusystem.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 27296991314 # number of WriteInvalidateReq miss cycles 65010628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_miss_latency::total 27296991314 # number of WriteInvalidateReq miss cycles 65110636Snilay@cs.wisc.edusystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 1502404735 # number of LoadLockedReq miss cycles 65210628Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 1502404735 # number of LoadLockedReq miss cycles 65310636Snilay@cs.wisc.edusystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3769027814 # number of StoreCondReq miss cycles 65410628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 3769027814 # number of StoreCondReq miss cycles 65510636Snilay@cs.wisc.edusystem.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2840500 # number of StoreCondFailReq miss cycles 65610628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::total 2840500 # number of StoreCondFailReq miss cycles 65710636Snilay@cs.wisc.edusystem.cpu0.dcache.demand_miss_latency::cpu0.data 96359684029 # number of demand (read+write) miss cycles 65810628Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::total 96359684029 # number of demand (read+write) miss cycles 65910636Snilay@cs.wisc.edusystem.cpu0.dcache.overall_miss_latency::cpu0.data 96359684029 # number of overall miss cycles 66010628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::total 96359684029 # number of overall miss cycles 66110636Snilay@cs.wisc.edusystem.cpu0.dcache.ReadReq_accesses::cpu0.data 80967470 # number of ReadReq accesses(hits+misses) 66210628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 80967470 # number of ReadReq accesses(hits+misses) 66310636Snilay@cs.wisc.edusystem.cpu0.dcache.WriteReq_accesses::cpu0.data 71607591 # number of WriteReq accesses(hits+misses) 66410628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 71607591 # number of WriteReq accesses(hits+misses) 66510636Snilay@cs.wisc.edusystem.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1017532 # number of WriteInvalidateReq accesses(hits+misses) 66610628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_accesses::total 1017532 # number of WriteInvalidateReq accesses(hits+misses) 66710636Snilay@cs.wisc.edusystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1849369 # number of LoadLockedReq accesses(hits+misses) 66810628Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 1849369 # number of LoadLockedReq accesses(hits+misses) 66910636Snilay@cs.wisc.edusystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1848288 # number of StoreCondReq accesses(hits+misses) 67010628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 1848288 # number of StoreCondReq accesses(hits+misses) 67110636Snilay@cs.wisc.edusystem.cpu0.dcache.demand_accesses::cpu0.data 152575061 # number of demand (read+write) accesses 67210628Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 152575061 # number of demand (read+write) accesses 67310636Snilay@cs.wisc.edusystem.cpu0.dcache.overall_accesses::cpu0.data 152575061 # number of overall (read+write) accesses 67410628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 152575061 # number of overall (read+write) accesses 67510636Snilay@cs.wisc.edusystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.047583 # miss rate for ReadReq accesses 67610628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.047583 # miss rate for ReadReq accesses 67710636Snilay@cs.wisc.edusystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031499 # miss rate for WriteReq accesses 67810628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.031499 # miss rate for WriteReq accesses 67910636Snilay@cs.wisc.edusystem.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.752900 # miss rate for WriteInvalidateReq accesses 68010628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.752900 # miss rate for WriteInvalidateReq accesses 68110636Snilay@cs.wisc.edusystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056267 # miss rate for LoadLockedReq accesses 68210628Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056267 # miss rate for LoadLockedReq accesses 68310636Snilay@cs.wisc.edusystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097395 # miss rate for StoreCondReq accesses 68410628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.097395 # miss rate for StoreCondReq accesses 68510636Snilay@cs.wisc.edusystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.040035 # miss rate for demand accesses 68610628Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.040035 # miss rate for demand accesses 68710636Snilay@cs.wisc.edusystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.040035 # miss rate for overall accesses 68810628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.040035 # miss rate for overall accesses 68910636Snilay@cs.wisc.edusystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14133.682269 # average ReadReq miss latency 69010628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 14133.682269 # average ReadReq miss latency 69110636Snilay@cs.wisc.edusystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18579.065811 # average WriteReq miss latency 69210628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 18579.065811 # average WriteReq miss latency 69310636Snilay@cs.wisc.edusystem.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 35631.107315 # average WriteInvalidateReq miss latency 69410628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 35631.107315 # average WriteInvalidateReq miss latency 69510636Snilay@cs.wisc.edusystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14438.008582 # average LoadLockedReq miss latency 69610628Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14438.008582 # average LoadLockedReq miss latency 69710636Snilay@cs.wisc.edusystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 20937.414946 # average StoreCondReq miss latency 69810628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20937.414946 # average StoreCondReq miss latency 69910636Snilay@cs.wisc.edusystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 70010585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 70110636Snilay@cs.wisc.edusystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15775.222968 # average overall miss latency 70210628Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 15775.222968 # average overall miss latency 70310636Snilay@cs.wisc.edusystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15775.222968 # average overall miss latency 70410628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 15775.222968 # average overall miss latency 70510585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 70610585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 70710585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 70810585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 70910585Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 71010585Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 71110585Sandreas.hansson@arm.comsystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 71210585Sandreas.hansson@arm.comsystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 71310628Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 3733142 # number of writebacks 71410628Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 3733142 # number of writebacks 71510636Snilay@cs.wisc.edusystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 361487 # number of ReadReq MSHR hits 71610628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 361487 # number of ReadReq MSHR hits 71710636Snilay@cs.wisc.edusystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 935411 # number of WriteReq MSHR hits 71810628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 935411 # number of WriteReq MSHR hits 71910636Snilay@cs.wisc.edusystem.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 100 # number of WriteInvalidateReq MSHR hits 72010628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 100 # number of WriteInvalidateReq MSHR hits 72110636Snilay@cs.wisc.edusystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 34 # number of LoadLockedReq MSHR hits 72210628Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 34 # number of LoadLockedReq MSHR hits 72310636Snilay@cs.wisc.edusystem.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 67 # number of StoreCondReq MSHR hits 72410628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_hits::total 67 # number of StoreCondReq MSHR hits 72510636Snilay@cs.wisc.edusystem.cpu0.dcache.demand_mshr_hits::cpu0.data 1296898 # number of demand (read+write) MSHR hits 72610628Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::total 1296898 # number of demand (read+write) MSHR hits 72710636Snilay@cs.wisc.edusystem.cpu0.dcache.overall_mshr_hits::cpu0.data 1296898 # number of overall MSHR hits 72810628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::total 1296898 # number of overall MSHR hits 72910636Snilay@cs.wisc.edusystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3491205 # number of ReadReq MSHR misses 73010628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 3491205 # number of ReadReq MSHR misses 73110636Snilay@cs.wisc.edusystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1320190 # number of WriteReq MSHR misses 73210628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 1320190 # number of WriteReq MSHR misses 73310636Snilay@cs.wisc.edusystem.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 766000 # number of WriteInvalidateReq MSHR misses 73410628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 766000 # number of WriteInvalidateReq MSHR misses 73510636Snilay@cs.wisc.edusystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 104025 # number of LoadLockedReq MSHR misses 73610628Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 104025 # number of LoadLockedReq MSHR misses 73710636Snilay@cs.wisc.edusystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 179947 # number of StoreCondReq MSHR misses 73810628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 179947 # number of StoreCondReq MSHR misses 73910636Snilay@cs.wisc.edusystem.cpu0.dcache.demand_mshr_misses::cpu0.data 4811395 # number of demand (read+write) MSHR misses 74010628Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 4811395 # number of demand (read+write) MSHR misses 74110636Snilay@cs.wisc.edusystem.cpu0.dcache.overall_mshr_misses::cpu0.data 4811395 # number of overall MSHR misses 74210628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 4811395 # number of overall MSHR misses 74310636Snilay@cs.wisc.edusystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 42113152704 # number of ReadReq MSHR miss cycles 74410628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 42113152704 # number of ReadReq MSHR miss cycles 74510636Snilay@cs.wisc.edusystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 22270249828 # number of WriteReq MSHR miss cycles 74610628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 22270249828 # number of WriteReq MSHR miss cycles 74710636Snilay@cs.wisc.edusystem.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 25755951436 # number of WriteInvalidateReq MSHR miss cycles 74810628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 25755951436 # number of WriteInvalidateReq MSHR miss cycles 74910636Snilay@cs.wisc.edusystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1293404753 # number of LoadLockedReq MSHR miss cycles 75010628Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1293404753 # number of LoadLockedReq MSHR miss cycles 75110636Snilay@cs.wisc.edusystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3399276642 # number of StoreCondReq MSHR miss cycles 75210628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3399276642 # number of StoreCondReq MSHR miss cycles 75310636Snilay@cs.wisc.edusystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2291500 # number of StoreCondFailReq MSHR miss cycles 75410628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2291500 # number of StoreCondFailReq MSHR miss cycles 75510636Snilay@cs.wisc.edusystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 64383402532 # number of demand (read+write) MSHR miss cycles 75610628Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 64383402532 # number of demand (read+write) MSHR miss cycles 75710636Snilay@cs.wisc.edusystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 64383402532 # number of overall MSHR miss cycles 75810628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 64383402532 # number of overall MSHR miss cycles 75910636Snilay@cs.wisc.edusystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5824362996 # number of ReadReq MSHR uncacheable cycles 76010628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5824362996 # number of ReadReq MSHR uncacheable cycles 76110636Snilay@cs.wisc.edusystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5586865743 # number of WriteReq MSHR uncacheable cycles 76210628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5586865743 # number of WriteReq MSHR uncacheable cycles 76310636Snilay@cs.wisc.edusystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11411228739 # number of overall MSHR uncacheable cycles 76410628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 11411228739 # number of overall MSHR uncacheable cycles 76510636Snilay@cs.wisc.edusystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.043119 # mshr miss rate for ReadReq accesses 76610628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.043119 # mshr miss rate for ReadReq accesses 76710636Snilay@cs.wisc.edusystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018436 # mshr miss rate for WriteReq accesses 76810628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018436 # mshr miss rate for WriteReq accesses 76910636Snilay@cs.wisc.edusystem.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.752802 # mshr miss rate for WriteInvalidateReq accesses 77010628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.752802 # mshr miss rate for WriteInvalidateReq accesses 77110636Snilay@cs.wisc.edusystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056249 # mshr miss rate for LoadLockedReq accesses 77210628Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056249 # mshr miss rate for LoadLockedReq accesses 77310636Snilay@cs.wisc.edusystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097359 # mshr miss rate for StoreCondReq accesses 77410628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097359 # mshr miss rate for StoreCondReq accesses 77510636Snilay@cs.wisc.edusystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.031535 # mshr miss rate for demand accesses 77610628Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.031535 # mshr miss rate for demand accesses 77710636Snilay@cs.wisc.edusystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031535 # mshr miss rate for overall accesses 77810628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.031535 # mshr miss rate for overall accesses 77910636Snilay@cs.wisc.edusystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12062.641038 # average ReadReq mshr miss latency 78010628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12062.641038 # average ReadReq mshr miss latency 78110636Snilay@cs.wisc.edusystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16868.973275 # average WriteReq mshr miss latency 78210628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16868.973275 # average WriteReq mshr miss latency 78310636Snilay@cs.wisc.edusystem.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33623.957488 # average WriteInvalidateReq mshr miss latency 78410628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 33623.957488 # average WriteInvalidateReq mshr miss latency 78510636Snilay@cs.wisc.edusystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12433.595318 # average LoadLockedReq mshr miss latency 78610628Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12433.595318 # average LoadLockedReq mshr miss latency 78710636Snilay@cs.wisc.edusystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 18890.432416 # average StoreCondReq mshr miss latency 78810628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18890.432416 # average StoreCondReq mshr miss latency 78910636Snilay@cs.wisc.edusystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 79010585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 79110636Snilay@cs.wisc.edusystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13381.441875 # average overall mshr miss latency 79210628Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 13381.441875 # average overall mshr miss latency 79310636Snilay@cs.wisc.edusystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13381.441875 # average overall mshr miss latency 79410628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 13381.441875 # average overall mshr miss latency 79510636Snilay@cs.wisc.edusystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 79610585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 79710636Snilay@cs.wisc.edusystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 79810585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 79910636Snilay@cs.wisc.edusystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 80010585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 80110585Sandreas.hansson@arm.comsystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 80210628Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 9463678 # number of replacements 80310628Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.932976 # Cycle average of tags in use 80410628Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 224826074 # Total number of references to valid blocks. 80510628Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 9464190 # Sample count of references to valid blocks. 80610628Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 23.755448 # Average number of references to valid blocks. 80710628Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 21621868750 # Cycle when the warmup percentage was hit. 80810628Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.932976 # Average occupied blocks per requestor 80910628Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999869 # Average percentage of cache occupancy 81010628Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999869 # Average percentage of cache occupancy 81110585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 81210628Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id 81310628Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id 81410628Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 72 # Occupied blocks per task id 81510585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 81610628Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 478044747 # Number of tag accesses 81710628Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 478044747 # Number of data accesses 81810628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 224826074 # number of ReadReq hits 81910628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 224826074 # number of ReadReq hits 82010628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 224826074 # number of demand (read+write) hits 82110628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 224826074 # number of demand (read+write) hits 82210628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 224826074 # number of overall hits 82310628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 224826074 # number of overall hits 82410628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 9464200 # number of ReadReq misses 82510628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 9464200 # number of ReadReq misses 82610628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 9464200 # number of demand (read+write) misses 82710628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 9464200 # number of demand (read+write) misses 82810628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 9464200 # number of overall misses 82910628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 9464200 # number of overall misses 83010628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 93878607487 # number of ReadReq miss cycles 83110628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 93878607487 # number of ReadReq miss cycles 83210628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 93878607487 # number of demand (read+write) miss cycles 83310628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::total 93878607487 # number of demand (read+write) miss cycles 83410628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 93878607487 # number of overall miss cycles 83510628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::total 93878607487 # number of overall miss cycles 83610628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 234290274 # number of ReadReq accesses(hits+misses) 83710628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 234290274 # number of ReadReq accesses(hits+misses) 83810628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 234290274 # number of demand (read+write) accesses 83910628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 234290274 # number of demand (read+write) accesses 84010628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 234290274 # number of overall (read+write) accesses 84110628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 234290274 # number of overall (read+write) accesses 84210628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.040395 # miss rate for ReadReq accesses 84310628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.040395 # miss rate for ReadReq accesses 84410628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.040395 # miss rate for demand accesses 84510628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.040395 # miss rate for demand accesses 84610628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.040395 # miss rate for overall accesses 84710628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.040395 # miss rate for overall accesses 84810628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9919.338928 # average ReadReq miss latency 84910628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 9919.338928 # average ReadReq miss latency 85010628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9919.338928 # average overall miss latency 85110628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 9919.338928 # average overall miss latency 85210628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9919.338928 # average overall miss latency 85310628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 9919.338928 # average overall miss latency 85410585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 85510585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 85610585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 85710585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 85810585Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 85910585Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 86010585Sandreas.hansson@arm.comsystem.cpu0.icache.fast_writes 0 # number of fast writes performed 86110585Sandreas.hansson@arm.comsystem.cpu0.icache.cache_copies 0 # number of cache copies performed 86210628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9464200 # number of ReadReq MSHR misses 86310628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 9464200 # number of ReadReq MSHR misses 86410628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 9464200 # number of demand (read+write) MSHR misses 86510628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::total 9464200 # number of demand (read+write) MSHR misses 86610628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 9464200 # number of overall MSHR misses 86710628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::total 9464200 # number of overall MSHR misses 86810628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 79648587963 # number of ReadReq MSHR miss cycles 86910628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 79648587963 # number of ReadReq MSHR miss cycles 87010628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 79648587963 # number of demand (read+write) MSHR miss cycles 87110628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 79648587963 # number of demand (read+write) MSHR miss cycles 87210628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 79648587963 # number of overall MSHR miss cycles 87310628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 79648587963 # number of overall MSHR miss cycles 87410585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4713229500 # number of ReadReq MSHR uncacheable cycles 87510585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4713229500 # number of ReadReq MSHR uncacheable cycles 87610585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4713229500 # number of overall MSHR uncacheable cycles 87710585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::total 4713229500 # number of overall MSHR uncacheable cycles 87810628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.040395 # mshr miss rate for ReadReq accesses 87910628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.040395 # mshr miss rate for ReadReq accesses 88010628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.040395 # mshr miss rate for demand accesses 88110628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.040395 # mshr miss rate for demand accesses 88210628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.040395 # mshr miss rate for overall accesses 88310628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.040395 # mshr miss rate for overall accesses 88410628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8415.776079 # average ReadReq mshr miss latency 88510628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8415.776079 # average ReadReq mshr miss latency 88610628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8415.776079 # average overall mshr miss latency 88710628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 8415.776079 # average overall mshr miss latency 88810628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8415.776079 # average overall mshr miss latency 88910628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 8415.776079 # average overall mshr miss latency 89010585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 89110585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 89210585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 89310585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 89410585Sandreas.hansson@arm.comsystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 89510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.num_hwpf_issued 11128158 # number of hwpf issued 89610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfIdentified 11136239 # number of prefetch candidates identified 89710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfBufferHit 7035 # number of redundant prefetches already in prefetch queue 89810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 89910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 90010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfSpanPage 1270201 # number of prefetches not generated due to page crossing 90110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.replacements 2736028 # number of replacements 90210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tagsinuse 16197.540138 # Cycle average of tags in use 90310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.total_refs 15248127 # Total number of references to valid blocks. 90410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.sampled_refs 2752162 # Sample count of references to valid blocks. 90510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.avg_refs 5.540418 # Average number of references to valid blocks. 90610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 5578143500 # Cycle when the warmup percentage was hit. 90710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 4129.920995 # Average occupied blocks per requestor 90810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 42.114006 # Average occupied blocks per requestor 90910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 24.266127 # Average occupied blocks per requestor 91010636Snilay@cs.wisc.edusystem.cpu0.l2cache.tags.occ_blocks::cpu0.inst 6921.151423 # Average occupied blocks per requestor 91110636Snilay@cs.wisc.edusystem.cpu0.l2cache.tags.occ_blocks::cpu0.data 2517.491382 # Average occupied blocks per requestor 91210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 2562.596205 # Average occupied blocks per requestor 91310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.252070 # Average percentage of cache occupancy 91410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002570 # Average percentage of cache occupancy 91510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001481 # Average percentage of cache occupancy 91610636Snilay@cs.wisc.edusystem.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.422434 # Average percentage of cache occupancy 91710636Snilay@cs.wisc.edusystem.cpu0.l2cache.tags.occ_percent::cpu0.data 0.153655 # Average percentage of cache occupancy 91810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.156408 # Average percentage of cache occupancy 91910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.988619 # Average percentage of cache occupancy 92010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1022 2519 # Occupied blocks per task id 92110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 71 # Occupied blocks per task id 92210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 13544 # Occupied blocks per task id 92310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::1 133 # Occupied blocks per task id 92410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::2 367 # Occupied blocks per task id 92510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::3 1060 # Occupied blocks per task id 92610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::4 959 # Occupied blocks per task id 92710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 92810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 10 # Occupied blocks per task id 92910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 25 # Occupied blocks per task id 93010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 35 # Occupied blocks per task id 93110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id 93210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1002 # Occupied blocks per task id 93310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2423 # Occupied blocks per task id 93410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4868 # Occupied blocks per task id 93510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 5129 # Occupied blocks per task id 93610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1022 0.153748 # Percentage of cache occupancy per task id 93710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004333 # Percentage of cache occupancy per task id 93810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.826660 # Percentage of cache occupancy per task id 93910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tag_accesses 319708402 # Number of tag accesses 94010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.data_accesses 319708402 # Number of data accesses 94110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 463342 # number of ReadReq hits 94210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 138212 # number of ReadReq hits 94310636Snilay@cs.wisc.edusystem.cpu0.l2cache.ReadReq_hits::cpu0.inst 8698965 # number of ReadReq hits 94410636Snilay@cs.wisc.edusystem.cpu0.l2cache.ReadReq_hits::cpu0.data 2911592 # number of ReadReq hits 94510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 12212111 # number of ReadReq hits 94610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_hits::writebacks 3733141 # number of Writeback hits 94710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_hits::total 3733141 # number of Writeback hits 94810636Snilay@cs.wisc.edusystem.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 193768 # number of WriteInvalidateReq hits 94910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_hits::total 193768 # number of WriteInvalidateReq hits 95010636Snilay@cs.wisc.edusystem.cpu0.l2cache.UpgradeReq_hits::cpu0.data 68627 # number of UpgradeReq hits 95110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::total 68627 # number of UpgradeReq hits 95210636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 33597 # number of SCUpgradeReq hits 95310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_hits::total 33597 # number of SCUpgradeReq hits 95410636Snilay@cs.wisc.edusystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 855771 # number of ReadExReq hits 95510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 855771 # number of ReadExReq hits 95610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 463342 # number of demand (read+write) hits 95710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 138212 # number of demand (read+write) hits 95810636Snilay@cs.wisc.edusystem.cpu0.l2cache.demand_hits::cpu0.inst 8698965 # number of demand (read+write) hits 95910636Snilay@cs.wisc.edusystem.cpu0.l2cache.demand_hits::cpu0.data 3767363 # number of demand (read+write) hits 96010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::total 13067882 # number of demand (read+write) hits 96110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 463342 # number of overall hits 96210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 138212 # number of overall hits 96310636Snilay@cs.wisc.edusystem.cpu0.l2cache.overall_hits::cpu0.inst 8698965 # number of overall hits 96410636Snilay@cs.wisc.edusystem.cpu0.l2cache.overall_hits::cpu0.data 3767363 # number of overall hits 96510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::total 13067882 # number of overall hits 96610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11843 # number of ReadReq misses 96710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8238 # number of ReadReq misses 96810636Snilay@cs.wisc.edusystem.cpu0.l2cache.ReadReq_misses::cpu0.inst 765234 # number of ReadReq misses 96910636Snilay@cs.wisc.edusystem.cpu0.l2cache.ReadReq_misses::cpu0.data 683379 # number of ReadReq misses 97010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 1468694 # number of ReadReq misses 97110636Snilay@cs.wisc.edusystem.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 570757 # number of WriteInvalidateReq misses 97210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_misses::total 570757 # number of WriteInvalidateReq misses 97310636Snilay@cs.wisc.edusystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 126856 # number of UpgradeReq misses 97410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 126856 # number of UpgradeReq misses 97510636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 146340 # number of SCUpgradeReq misses 97610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 146340 # number of SCUpgradeReq misses 97710636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 10 # number of SCUpgradeFailReq misses 97810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::total 10 # number of SCUpgradeFailReq misses 97910636Snilay@cs.wisc.edusystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 270676 # number of ReadExReq misses 98010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 270676 # number of ReadExReq misses 98110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11843 # number of demand (read+write) misses 98210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 8238 # number of demand (read+write) misses 98310636Snilay@cs.wisc.edusystem.cpu0.l2cache.demand_misses::cpu0.inst 765234 # number of demand (read+write) misses 98410636Snilay@cs.wisc.edusystem.cpu0.l2cache.demand_misses::cpu0.data 954055 # number of demand (read+write) misses 98510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::total 1739370 # number of demand (read+write) misses 98610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11843 # number of overall misses 98710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 8238 # number of overall misses 98810636Snilay@cs.wisc.edusystem.cpu0.l2cache.overall_misses::cpu0.inst 765234 # number of overall misses 98910636Snilay@cs.wisc.edusystem.cpu0.l2cache.overall_misses::cpu0.data 954055 # number of overall misses 99010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::total 1739370 # number of overall misses 99110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 383176229 # number of ReadReq miss cycles 99210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 279750987 # number of ReadReq miss cycles 99310636Snilay@cs.wisc.edusystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 22688045273 # number of ReadReq miss cycles 99410636Snilay@cs.wisc.edusystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 22235459859 # number of ReadReq miss cycles 99510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::total 45586432348 # number of ReadReq miss cycles 99610636Snilay@cs.wisc.edusystem.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 223595615 # number of WriteInvalidateReq miss cycles 99710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 223595615 # number of WriteInvalidateReq miss cycles 99810636Snilay@cs.wisc.edusystem.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2548596996 # number of UpgradeReq miss cycles 99910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::total 2548596996 # number of UpgradeReq miss cycles 100010636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2948593769 # number of SCUpgradeReq miss cycles 100110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2948593769 # number of SCUpgradeReq miss cycles 100210636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2234000 # number of SCUpgradeFailReq miss cycles 100310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2234000 # number of SCUpgradeFailReq miss cycles 100410636Snilay@cs.wisc.edusystem.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 12372799630 # number of ReadExReq miss cycles 100510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::total 12372799630 # number of ReadExReq miss cycles 100610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 383176229 # number of demand (read+write) miss cycles 100710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 279750987 # number of demand (read+write) miss cycles 100810636Snilay@cs.wisc.edusystem.cpu0.l2cache.demand_miss_latency::cpu0.inst 22688045273 # number of demand (read+write) miss cycles 100910636Snilay@cs.wisc.edusystem.cpu0.l2cache.demand_miss_latency::cpu0.data 34608259489 # number of demand (read+write) miss cycles 101010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::total 57959231978 # number of demand (read+write) miss cycles 101110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 383176229 # number of overall miss cycles 101210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 279750987 # number of overall miss cycles 101310636Snilay@cs.wisc.edusystem.cpu0.l2cache.overall_miss_latency::cpu0.inst 22688045273 # number of overall miss cycles 101410636Snilay@cs.wisc.edusystem.cpu0.l2cache.overall_miss_latency::cpu0.data 34608259489 # number of overall miss cycles 101510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::total 57959231978 # number of overall miss cycles 101610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 475185 # number of ReadReq accesses(hits+misses) 101710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 146450 # number of ReadReq accesses(hits+misses) 101810636Snilay@cs.wisc.edusystem.cpu0.l2cache.ReadReq_accesses::cpu0.inst 9464199 # number of ReadReq accesses(hits+misses) 101910636Snilay@cs.wisc.edusystem.cpu0.l2cache.ReadReq_accesses::cpu0.data 3594971 # number of ReadReq accesses(hits+misses) 102010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 13680805 # number of ReadReq accesses(hits+misses) 102110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_accesses::writebacks 3733141 # number of Writeback accesses(hits+misses) 102210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_accesses::total 3733141 # number of Writeback accesses(hits+misses) 102310636Snilay@cs.wisc.edusystem.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 764525 # number of WriteInvalidateReq accesses(hits+misses) 102410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_accesses::total 764525 # number of WriteInvalidateReq accesses(hits+misses) 102510636Snilay@cs.wisc.edusystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 195483 # number of UpgradeReq accesses(hits+misses) 102610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 195483 # number of UpgradeReq accesses(hits+misses) 102710636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 179937 # number of SCUpgradeReq accesses(hits+misses) 102810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 179937 # number of SCUpgradeReq accesses(hits+misses) 102910636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 10 # number of SCUpgradeFailReq accesses(hits+misses) 103010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::total 10 # number of SCUpgradeFailReq accesses(hits+misses) 103110636Snilay@cs.wisc.edusystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1126447 # number of ReadExReq accesses(hits+misses) 103210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1126447 # number of ReadExReq accesses(hits+misses) 103310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 475185 # number of demand (read+write) accesses 103410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 146450 # number of demand (read+write) accesses 103510636Snilay@cs.wisc.edusystem.cpu0.l2cache.demand_accesses::cpu0.inst 9464199 # number of demand (read+write) accesses 103610636Snilay@cs.wisc.edusystem.cpu0.l2cache.demand_accesses::cpu0.data 4721418 # number of demand (read+write) accesses 103710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::total 14807252 # number of demand (read+write) accesses 103810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 475185 # number of overall (read+write) accesses 103910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 146450 # number of overall (read+write) accesses 104010636Snilay@cs.wisc.edusystem.cpu0.l2cache.overall_accesses::cpu0.inst 9464199 # number of overall (read+write) accesses 104110636Snilay@cs.wisc.edusystem.cpu0.l2cache.overall_accesses::cpu0.data 4721418 # number of overall (read+write) accesses 104210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::total 14807252 # number of overall (read+write) accesses 104310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.024923 # miss rate for ReadReq accesses 104410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.056251 # miss rate for ReadReq accesses 104510636Snilay@cs.wisc.edusystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.080856 # miss rate for ReadReq accesses 104610636Snilay@cs.wisc.edusystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.190093 # miss rate for ReadReq accesses 104710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.107354 # miss rate for ReadReq accesses 104810636Snilay@cs.wisc.edusystem.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.746551 # miss rate for WriteInvalidateReq accesses 104910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.746551 # miss rate for WriteInvalidateReq accesses 105010636Snilay@cs.wisc.edusystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.648936 # miss rate for UpgradeReq accesses 105110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 0.648936 # miss rate for UpgradeReq accesses 105210636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.813285 # miss rate for SCUpgradeReq accesses 105310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.813285 # miss rate for SCUpgradeReq accesses 105410636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 105510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 105610636Snilay@cs.wisc.edusystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.240292 # miss rate for ReadExReq accesses 105710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.240292 # miss rate for ReadExReq accesses 105810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.024923 # miss rate for demand accesses 105910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.056251 # miss rate for demand accesses 106010636Snilay@cs.wisc.edusystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.080856 # miss rate for demand accesses 106110636Snilay@cs.wisc.edusystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.202070 # miss rate for demand accesses 106210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.117467 # miss rate for demand accesses 106310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.024923 # miss rate for overall accesses 106410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.056251 # miss rate for overall accesses 106510636Snilay@cs.wisc.edusystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.080856 # miss rate for overall accesses 106610636Snilay@cs.wisc.edusystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.202070 # miss rate for overall accesses 106710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.117467 # miss rate for overall accesses 106810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32354.659208 # average ReadReq miss latency 106910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 33958.604880 # average ReadReq miss latency 107010636Snilay@cs.wisc.edusystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 29648.506565 # average ReadReq miss latency 107110636Snilay@cs.wisc.edusystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 32537.522896 # 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number of demand (read+write) MSHR hits 111410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::total 13062 # number of demand (read+write) MSHR hits 111510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits 111610636Snilay@cs.wisc.edusystem.cpu0.l2cache.overall_mshr_hits::cpu0.inst 8 # number of overall MSHR hits 111710636Snilay@cs.wisc.edusystem.cpu0.l2cache.overall_mshr_hits::cpu0.data 13053 # number of overall MSHR hits 111810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::total 13062 # number of overall MSHR hits 111910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 11843 # number of ReadReq MSHR misses 112010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8237 # number of ReadReq MSHR misses 112110636Snilay@cs.wisc.edusystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 765226 # number of ReadReq MSHR misses 112210636Snilay@cs.wisc.edusystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 679984 # number of ReadReq MSHR misses 112310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::total 1465290 # number of ReadReq MSHR misses 112410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 1036981 # number of HardPFReq MSHR misses 112510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::total 1036981 # number of HardPFReq MSHR misses 112610636Snilay@cs.wisc.edusystem.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 570601 # number of WriteInvalidateReq MSHR misses 112710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 570601 # number of WriteInvalidateReq MSHR misses 112810636Snilay@cs.wisc.edusystem.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 126856 # number of UpgradeReq MSHR misses 112910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::total 126856 # number of UpgradeReq MSHR misses 113010636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 146340 # 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number of demand (read+write) MSHR misses 113910636Snilay@cs.wisc.edusystem.cpu0.l2cache.demand_mshr_misses::cpu0.data 941002 # number of demand (read+write) MSHR misses 114010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::total 1726308 # number of demand (read+write) MSHR misses 114110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 11843 # number of overall MSHR misses 114210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8237 # number of overall MSHR misses 114310636Snilay@cs.wisc.edusystem.cpu0.l2cache.overall_mshr_misses::cpu0.inst 765226 # number of overall MSHR misses 114410636Snilay@cs.wisc.edusystem.cpu0.l2cache.overall_mshr_misses::cpu0.data 941002 # number of overall MSHR misses 114510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 1036981 # number of overall MSHR misses 114610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::total 2763289 # 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number of WriteInvalidateReq MSHR miss cycles 115510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 20034543782 # number of WriteInvalidateReq MSHR miss cycles 115610636Snilay@cs.wisc.edusystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2151275072 # number of UpgradeReq MSHR miss cycles 115710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2151275072 # number of UpgradeReq MSHR miss cycles 115810636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 1993779824 # number of SCUpgradeReq MSHR miss cycles 115910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 1993779824 # number of SCUpgradeReq MSHR miss cycles 116010636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1835000 # number of SCUpgradeFailReq MSHR miss cycles 116110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1835000 # number of SCUpgradeFailReq MSHR miss cycles 116210636Snilay@cs.wisc.edusystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 9532664011 # number of ReadExReq MSHR miss cycles 116310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 9532664011 # number of ReadExReq MSHR miss cycles 116410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 299835249 # number of demand (read+write) MSHR miss cycles 116510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 221721501 # number of demand (read+write) MSHR miss cycles 116610636Snilay@cs.wisc.edusystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 17303340727 # number of demand (read+write) MSHR miss cycles 116710636Snilay@cs.wisc.edusystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 26585104533 # number of demand (read+write) MSHR miss cycles 116810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::total 44410002010 # number of demand (read+write) MSHR miss cycles 116910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 299835249 # number of overall MSHR miss cycles 117010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 221721501 # number of overall MSHR miss cycles 117110636Snilay@cs.wisc.edusystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 17303340727 # number of overall MSHR miss cycles 117210636Snilay@cs.wisc.edusystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 26585104533 # number of overall MSHR miss cycles 117310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 47311809533 # number of overall MSHR miss cycles 117410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::total 91721811543 # number of overall MSHR miss cycles 117510636Snilay@cs.wisc.edusystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4113621500 # number of ReadReq MSHR uncacheable cycles 117610636Snilay@cs.wisc.edusystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5558383242 # number of ReadReq MSHR uncacheable cycles 117710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9672004742 # number of ReadReq MSHR uncacheable cycles 117810636Snilay@cs.wisc.edusystem.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5338553005 # number of WriteReq MSHR uncacheable cycles 117910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5338553005 # number of WriteReq MSHR uncacheable cycles 118010636Snilay@cs.wisc.edusystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4113621500 # number of overall MSHR uncacheable cycles 118110636Snilay@cs.wisc.edusystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10896936247 # number of overall MSHR uncacheable cycles 118210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15010557747 # number of overall MSHR uncacheable cycles 118310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.024923 # mshr miss rate for ReadReq accesses 118410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.056244 # mshr miss rate for ReadReq accesses 118510636Snilay@cs.wisc.edusystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.080855 # mshr miss rate for ReadReq accesses 118610636Snilay@cs.wisc.edusystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.189149 # mshr miss rate for ReadReq accesses 118710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.107106 # mshr miss rate for ReadReq accesses 118810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 118910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 119010636Snilay@cs.wisc.edusystem.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.746347 # mshr miss rate for WriteInvalidateReq accesses 119110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.746347 # mshr miss rate for WriteInvalidateReq accesses 119210636Snilay@cs.wisc.edusystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.648936 # mshr miss rate for UpgradeReq accesses 119310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.648936 # mshr miss rate for UpgradeReq accesses 119410636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.813285 # mshr miss rate for SCUpgradeReq accesses 119510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.813285 # mshr miss rate for SCUpgradeReq accesses 119610636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 119710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 119810636Snilay@cs.wisc.edusystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.231718 # mshr miss rate for ReadExReq accesses 119910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.231718 # mshr miss rate for ReadExReq accesses 120010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.024923 # mshr miss rate for demand accesses 120110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.056244 # mshr miss rate for demand accesses 120210636Snilay@cs.wisc.edusystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.080855 # mshr miss rate for demand accesses 120310636Snilay@cs.wisc.edusystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.199305 # mshr miss rate for demand accesses 120410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::total 0.116585 # mshr miss rate for demand accesses 120510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.024923 # mshr miss rate for overall accesses 120610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.056244 # mshr miss rate for overall accesses 120710636Snilay@cs.wisc.edusystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.080855 # mshr miss rate for overall accesses 120810636Snilay@cs.wisc.edusystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.199305 # mshr miss rate for overall accesses 120910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 121010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::total 0.186617 # mshr miss rate for overall accesses 121110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25317.508148 # average ReadReq mshr miss latency 121210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 26917.749302 # average ReadReq mshr miss latency 121310636Snilay@cs.wisc.edusystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22612.065882 # average ReadReq mshr miss latency 121410636Snilay@cs.wisc.edusystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 25077.708478 # average ReadReq mshr miss latency 121510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23802.344928 # average ReadReq mshr miss latency 121610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45624.567406 # average HardPFReq mshr miss latency 121710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45624.567406 # average HardPFReq mshr miss latency 121810636Snilay@cs.wisc.edusystem.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 35111.301561 # average WriteInvalidateReq mshr miss latency 121910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 35111.301561 # average WriteInvalidateReq mshr miss latency 122010636Snilay@cs.wisc.edusystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16958.402220 # average UpgradeReq mshr miss latency 122110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16958.402220 # average UpgradeReq mshr miss latency 122210636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13624.298374 # average SCUpgradeReq mshr miss latency 122310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13624.298374 # average SCUpgradeReq mshr miss latency 122410636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 183500 # average SCUpgradeFailReq mshr miss latency 122510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 183500 # average SCUpgradeFailReq mshr miss latency 122610636Snilay@cs.wisc.edusystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 36521.098204 # average ReadExReq mshr miss latency 122710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36521.098204 # average ReadExReq mshr miss latency 122810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25317.508148 # average overall mshr miss latency 122910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 26917.749302 # average overall mshr miss latency 123010636Snilay@cs.wisc.edusystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22612.065882 # average overall mshr miss latency 123110636Snilay@cs.wisc.edusystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28251.910764 # average overall mshr miss latency 123210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25725.422121 # average overall mshr miss latency 123310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25317.508148 # average overall mshr miss latency 123410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 26917.749302 # average overall mshr miss latency 123510636Snilay@cs.wisc.edusystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22612.065882 # average overall mshr miss latency 123610636Snilay@cs.wisc.edusystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28251.910764 # average overall mshr miss latency 123710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45624.567406 # average overall mshr miss latency 123810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33192.985440 # average overall mshr miss latency 123910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 124010636Snilay@cs.wisc.edusystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 124110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 124210636Snilay@cs.wisc.edusystem.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 124310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 124410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 124510636Snilay@cs.wisc.edusystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 124610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 124710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 124810628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 16482247 # Transaction distribution 124910628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 13994677 # Transaction distribution 125010628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 33105 # Transaction distribution 125110628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 33105 # Transaction distribution 125210628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::Writeback 3733141 # Transaction distribution 125310628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::HardPFReq 1450559 # Transaction distribution 125410628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 125510628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1135277 # Transaction distribution 125610628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 764525 # Transaction distribution 125710628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 439100 # Transaction distribution 125810628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 331866 # Transaction distribution 125910628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 445825 # Transaction distribution 126010628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 56 # Transaction distribution 126110628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution 126210628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1265717 # Transaction distribution 126310628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1135924 # Transaction distribution 126410628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 19032980 # Packet count per connected master and slave (bytes) 126510628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15771109 # Packet count per connected master and slave (bytes) 126610628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 324159 # Packet count per connected master and slave (bytes) 126710628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1044893 # Packet count per connected master and slave (bytes) 126810628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count::total 36173141 # Packet count per connected master and slave (bytes) 126910628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 609055296 # Cumulative packet size per connected master and slave (bytes) 127010628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 597396947 # Cumulative packet size per connected master and slave (bytes) 127110628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1171600 # Cumulative packet size per connected master and slave (bytes) 127210628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3801480 # Cumulative packet size per connected master and slave (bytes) 127310628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size::total 1211425323 # Cumulative packet size per connected master and slave (bytes) 127410628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoops 5254625 # Total snoops (count) 127510628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 24752436 # Request fanout histogram 127610628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 5.199831 # Request fanout histogram 127710628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.399873 # Request fanout histogram 127810585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 127910585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 128010585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 128110585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 128210585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 128310585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 128410628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::5 19806132 80.02% 80.02% # Request fanout histogram 128510628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::6 4946304 19.98% 100.00% # Request fanout histogram 128610585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 128710585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 128810585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 128910628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 24752436 # Request fanout histogram 129010628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.reqLayer0.occupancy 14477877088 # Layer occupancy (ticks) 129110585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 129210628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopLayer0.occupancy 203336996 # Layer occupancy (ticks) 129310585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 129410628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer0.occupancy 14303799012 # Layer occupancy (ticks) 129510585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 129610628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer1.occupancy 7760036291 # Layer occupancy (ticks) 129710585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 129810628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer2.occupancy 177959354 # Layer occupancy (ticks) 129910585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 130010628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer3.occupancy 570171512 # Layer occupancy (ticks) 130110585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 130210628Sandreas.hansson@arm.comsystem.cpu1.branchPred.lookups 141025153 # Number of BP lookups 130310628Sandreas.hansson@arm.comsystem.cpu1.branchPred.condPredicted 100933183 # Number of conditional branches predicted 130410628Sandreas.hansson@arm.comsystem.cpu1.branchPred.condIncorrect 6236213 # Number of conditional branches incorrect 130510628Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBLookups 106937612 # Number of BTB lookups 130610628Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBHits 78176713 # Number of BTB hits 130710585Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 130810628Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBHitPct 73.104974 # BTB Hit Percentage 130910628Sandreas.hansson@arm.comsystem.cpu1.branchPred.usedRAS 16283768 # Number of times the RAS was used to get a target. 131010628Sandreas.hansson@arm.comsystem.cpu1.branchPred.RASInCorrect 1021605 # Number of incorrect RAS predictions. 131110628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 131210628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 131310628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 131410628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 131510628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 131610628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 131710628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 131810628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 131910585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 132010585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 132110585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 132210585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 132310585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 132410585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 132510585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 132610585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 132710585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 132810585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 132910585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 133010585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 133110585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 133210585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 133310585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 133410585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 133510585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 133610585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 133710585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 133810585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 133910585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 134010628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walks 298651 # Table walker walks requested 134110628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLong 298651 # Table walker walks initiated with long descriptors 134210628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11560 # Level at which table walker walks with long descriptors terminate 134310628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level3 94332 # Level at which table walker walks with long descriptors terminate 134410628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 298651 # Table walker wait (enqueue to first request) latency 134510628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0 298651 100.00% 100.00% # Table walker wait (enqueue to first request) latency 134610628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 298651 # Table walker wait (enqueue to first request) latency 134710628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::samples 105892 # Table walker service (enqueue to completion) latency 134810628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::mean 17805.770634 # Table walker service (enqueue to completion) latency 134910628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::gmean 15803.828904 # Table walker service (enqueue to completion) latency 135010628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::stdev 14966.928967 # Table walker service (enqueue to completion) latency 135110628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::0-65535 104531 98.71% 98.71% # Table walker service (enqueue to completion) latency 135210628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::65536-131071 1148 1.08% 99.80% # Table walker service (enqueue to completion) latency 135310628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::131072-196607 61 0.06% 99.86% # Table walker service (enqueue to completion) latency 135410628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::196608-262143 60 0.06% 99.91% # Table walker service (enqueue to completion) latency 135510628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::262144-327679 63 0.06% 99.97% # Table walker service (enqueue to completion) latency 135610628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::327680-393215 16 0.02% 99.99% # Table walker service (enqueue to completion) latency 135710628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::393216-458751 5 0.00% 99.99% # Table walker service (enqueue to completion) latency 135810628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 135910628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 136010628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::total 105892 # Table walker service (enqueue to completion) latency 136110628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::samples -1172907556 # Table walker pending requests distribution 136210628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::0 -1172907556 100.00% 100.00% # Table walker pending requests distribution 136310628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::total -1172907556 # Table walker pending requests distribution 136410628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 94332 89.08% 89.08% # Table walker page sizes translated 136510628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::2M 11560 10.92% 100.00% # Table walker page sizes translated 136610628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 105892 # Table walker page sizes translated 136710628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 298651 # Table walker requests started/completed, data/inst 136810628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 136910628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 298651 # Table walker requests started/completed, data/inst 137010628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 105892 # Table walker requests started/completed, data/inst 137110628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 137210628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 105892 # Table walker requests started/completed, data/inst 137310628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 404543 # Table walker requests started/completed, data/inst 137410585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_hits 0 # ITB inst hits 137510585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_misses 0 # ITB inst misses 137610628Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 90905034 # DTB read hits 137710628Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 248418 # DTB read misses 137810628Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 78767149 # DTB write hits 137910628Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 50233 # DTB write misses 138010585Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 138110585Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 138210628Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 42371 # Number of times TLB was flushed by MVA & ASID 138310628Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID 138410628Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_entries 43819 # Number of entries that have been flushed from TLB 138510628Sandreas.hansson@arm.comsystem.cpu1.dtb.align_faults 923 # Number of TLB faults due to alignment restrictions 138610628Sandreas.hansson@arm.comsystem.cpu1.dtb.prefetch_faults 8321 # Number of TLB faults due to prefetch 138710585Sandreas.hansson@arm.comsystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 138810628Sandreas.hansson@arm.comsystem.cpu1.dtb.perms_faults 12272 # Number of TLB faults due to permissions restrictions 138910628Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 91153452 # DTB read accesses 139010628Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 78817382 # DTB write accesses 139110585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 139210628Sandreas.hansson@arm.comsystem.cpu1.dtb.hits 169672183 # DTB hits 139310628Sandreas.hansson@arm.comsystem.cpu1.dtb.misses 298651 # DTB misses 139410628Sandreas.hansson@arm.comsystem.cpu1.dtb.accesses 169970834 # DTB accesses 139510628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 139610628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 139710628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 139810628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 139910628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 140010628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 140110628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 140210628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 140310585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 140410585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 140510585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 140610585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 140710585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 140810585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 140910585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 141010585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 141110585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 141210585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 141310585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 141410585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 141510585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 141610585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 141710585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 141810585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 141910585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 142010585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 142110585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 142210585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 142310585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 142410628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walks 67610 # Table walker walks requested 142510628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLong 67610 # Table walker walks initiated with long descriptors 142610628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level2 497 # Level at which table walker walks with long descriptors terminate 142710628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level3 58418 # Level at which table walker walks with long descriptors terminate 142810628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 67610 # Table walker wait (enqueue to first request) latency 142910628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::0 67610 100.00% 100.00% # Table walker wait (enqueue to first request) latency 143010628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 67610 # Table walker wait (enqueue to first request) latency 143110628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::samples 58915 # Table walker service (enqueue to completion) latency 143210628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::mean 20253.386778 # Table walker service (enqueue to completion) latency 143310628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::gmean 17562.612185 # Table walker service (enqueue to completion) latency 143410628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::stdev 17511.554701 # Table walker service (enqueue to completion) latency 143510628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::0-65535 57403 97.43% 97.43% # Table walker service (enqueue to completion) latency 143610628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::65536-131071 1356 2.30% 99.74% # Table walker service (enqueue to completion) latency 143710628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::131072-196607 66 0.11% 99.85% # Table walker service (enqueue to completion) latency 143810628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::196608-262143 56 0.10% 99.94% # Table walker service (enqueue to completion) latency 143910628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::262144-327679 19 0.03% 99.97% # Table walker service (enqueue to completion) latency 144010628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::327680-393215 10 0.02% 99.99% # Table walker service (enqueue to completion) latency 144110628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.01% 100.00% # Table walker service (enqueue to completion) latency 144210628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 144310628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 144410628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::total 58915 # Table walker service (enqueue to completion) latency 144510628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::samples -1173450056 # Table walker pending requests distribution 144610628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::0 -1173450056 100.00% 100.00% # Table walker pending requests distribution 144710628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::total -1173450056 # Table walker pending requests distribution 144810628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 58418 99.16% 99.16% # Table walker page sizes translated 144910628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::2M 497 0.84% 100.00% # Table walker page sizes translated 145010628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 58915 # Table walker page sizes translated 145110628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 145210628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 67610 # Table walker requests started/completed, data/inst 145310628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 67610 # Table walker requests started/completed, data/inst 145410628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 145510628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 58915 # Table walker requests started/completed, data/inst 145610628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 58915 # Table walker requests started/completed, data/inst 145710628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 126525 # Table walker requests started/completed, data/inst 145810628Sandreas.hansson@arm.comsystem.cpu1.itb.inst_hits 252933263 # ITB inst hits 145910628Sandreas.hansson@arm.comsystem.cpu1.itb.inst_misses 67610 # ITB inst misses 146010585Sandreas.hansson@arm.comsystem.cpu1.itb.read_hits 0 # DTB read hits 146110585Sandreas.hansson@arm.comsystem.cpu1.itb.read_misses 0 # DTB read misses 146210585Sandreas.hansson@arm.comsystem.cpu1.itb.write_hits 0 # DTB write hits 146310585Sandreas.hansson@arm.comsystem.cpu1.itb.write_misses 0 # DTB write misses 146410585Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 146510585Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 146610628Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 42371 # Number of times TLB was flushed by MVA & ASID 146710628Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID 146810628Sandreas.hansson@arm.comsystem.cpu1.itb.flush_entries 31594 # Number of entries that have been flushed from TLB 146910585Sandreas.hansson@arm.comsystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 147010585Sandreas.hansson@arm.comsystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 147110585Sandreas.hansson@arm.comsystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 147210628Sandreas.hansson@arm.comsystem.cpu1.itb.perms_faults 222493 # Number of TLB faults due to permissions restrictions 147310585Sandreas.hansson@arm.comsystem.cpu1.itb.read_accesses 0 # DTB read accesses 147410585Sandreas.hansson@arm.comsystem.cpu1.itb.write_accesses 0 # DTB write accesses 147510628Sandreas.hansson@arm.comsystem.cpu1.itb.inst_accesses 253000873 # ITB inst accesses 147610628Sandreas.hansson@arm.comsystem.cpu1.itb.hits 252933263 # DTB hits 147710628Sandreas.hansson@arm.comsystem.cpu1.itb.misses 67610 # DTB misses 147810628Sandreas.hansson@arm.comsystem.cpu1.itb.accesses 253000873 # DTB accesses 147910628Sandreas.hansson@arm.comsystem.cpu1.numCycles 943783669 # number of cpu cycles simulated 148010585Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 148110585Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 148210628Sandreas.hansson@arm.comsystem.cpu1.committedInsts 461717275 # Number of instructions committed 148310628Sandreas.hansson@arm.comsystem.cpu1.committedOps 543187389 # Number of ops (including micro ops) committed 148410628Sandreas.hansson@arm.comsystem.cpu1.discardedOps 49256164 # Number of ops (including micro ops) which were discarded before commit 148510628Sandreas.hansson@arm.comsystem.cpu1.numFetchSuspends 5826 # Number of times Execute suspended instruction fetching 148610628Sandreas.hansson@arm.comsystem.cpu1.quiesceCycles 93768369123 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 148710628Sandreas.hansson@arm.comsystem.cpu1.cpi 2.044073 # CPI: cycles per instruction 148810628Sandreas.hansson@arm.comsystem.cpu1.ipc 0.489219 # IPC: instructions per cycle 148910585Sandreas.hansson@arm.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 149010628Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 5890 # number of quiesce instructions executed 149110628Sandreas.hansson@arm.comsystem.cpu1.tickCycles 748189458 # Number of cycles that the object actually ticked 149210628Sandreas.hansson@arm.comsystem.cpu1.idleCycles 195594211 # Total number of cycles that the object has spent stopped 149310628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 5624476 # number of replacements 149410628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 426.107402 # Cycle average of tags in use 149510628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 161270449 # Total number of references to valid blocks. 149610628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 5624987 # Sample count of references to valid blocks. 149710628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 28.670368 # Average number of references to valid blocks. 149810628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 8377201144000 # Cycle when the warmup percentage was hit. 149910636Snilay@cs.wisc.edusystem.cpu1.dcache.tags.occ_blocks::cpu1.data 426.107402 # Average occupied blocks per requestor 150010636Snilay@cs.wisc.edusystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.832241 # Average percentage of cache occupancy 150110628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.832241 # Average percentage of cache occupancy 150210628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 150310628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id 150410628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id 150510628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 209 # Occupied blocks per task id 150610628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 150710628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 342291215 # Number of tag accesses 150810628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 342291215 # Number of data accesses 150910636Snilay@cs.wisc.edusystem.cpu1.dcache.ReadReq_hits::cpu1.data 83489779 # number of ReadReq hits 151010628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 83489779 # number of ReadReq hits 151110636Snilay@cs.wisc.edusystem.cpu1.dcache.WriteReq_hits::cpu1.data 73474609 # number of WriteReq hits 151210628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 73474609 # number of WriteReq hits 151310636Snilay@cs.wisc.edusystem.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 71990 # number of WriteInvalidateReq hits 151410628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_hits::total 71990 # number of WriteInvalidateReq hits 151510636Snilay@cs.wisc.edusystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1908367 # number of LoadLockedReq hits 151610628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 1908367 # number of LoadLockedReq hits 151710636Snilay@cs.wisc.edusystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 1854336 # number of StoreCondReq hits 151810628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 1854336 # number of StoreCondReq hits 151910636Snilay@cs.wisc.edusystem.cpu1.dcache.demand_hits::cpu1.data 156964388 # number of demand (read+write) hits 152010628Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 156964388 # number of demand (read+write) hits 152110636Snilay@cs.wisc.edusystem.cpu1.dcache.overall_hits::cpu1.data 156964388 # number of overall hits 152210628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 156964388 # number of overall hits 152310636Snilay@cs.wisc.edusystem.cpu1.dcache.ReadReq_misses::cpu1.data 4311289 # number of ReadReq misses 152410628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 4311289 # number of ReadReq misses 152510636Snilay@cs.wisc.edusystem.cpu1.dcache.WriteReq_misses::cpu1.data 2366929 # number of WriteReq misses 152610628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 2366929 # number of WriteReq misses 152710636Snilay@cs.wisc.edusystem.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 476593 # number of WriteInvalidateReq misses 152810628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_misses::total 476593 # number of WriteInvalidateReq misses 152910636Snilay@cs.wisc.edusystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 141331 # number of LoadLockedReq misses 153010628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 141331 # number of LoadLockedReq misses 153110636Snilay@cs.wisc.edusystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 193852 # number of StoreCondReq misses 153210628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 193852 # number of StoreCondReq misses 153310636Snilay@cs.wisc.edusystem.cpu1.dcache.demand_misses::cpu1.data 6678218 # number of demand (read+write) misses 153410628Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 6678218 # number of demand (read+write) misses 153510636Snilay@cs.wisc.edusystem.cpu1.dcache.overall_misses::cpu1.data 6678218 # number of overall misses 153610628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 6678218 # number of overall misses 153710636Snilay@cs.wisc.edusystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 60722587231 # number of ReadReq miss cycles 153810628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 60722587231 # number of ReadReq miss cycles 153910636Snilay@cs.wisc.edusystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 38093191666 # number of WriteReq miss cycles 154010628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 38093191666 # number of WriteReq miss cycles 154110636Snilay@cs.wisc.edusystem.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 11613108236 # number of WriteInvalidateReq miss cycles 154210628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_miss_latency::total 11613108236 # number of WriteInvalidateReq miss cycles 154310636Snilay@cs.wisc.edusystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 1977833980 # number of LoadLockedReq miss cycles 154410628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 1977833980 # number of LoadLockedReq miss cycles 154510636Snilay@cs.wisc.edusystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3982712056 # number of StoreCondReq miss cycles 154610628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 3982712056 # number of StoreCondReq miss cycles 154710636Snilay@cs.wisc.edusystem.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2357000 # number of StoreCondFailReq miss cycles 154810628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::total 2357000 # number of StoreCondFailReq miss cycles 154910636Snilay@cs.wisc.edusystem.cpu1.dcache.demand_miss_latency::cpu1.data 98815778897 # number of demand (read+write) miss cycles 155010628Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::total 98815778897 # number of demand (read+write) miss cycles 155110636Snilay@cs.wisc.edusystem.cpu1.dcache.overall_miss_latency::cpu1.data 98815778897 # number of overall miss cycles 155210628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::total 98815778897 # number of overall miss cycles 155310636Snilay@cs.wisc.edusystem.cpu1.dcache.ReadReq_accesses::cpu1.data 87801068 # number of ReadReq accesses(hits+misses) 155410628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 87801068 # number of ReadReq accesses(hits+misses) 155510636Snilay@cs.wisc.edusystem.cpu1.dcache.WriteReq_accesses::cpu1.data 75841538 # number of WriteReq accesses(hits+misses) 155610628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 75841538 # number of WriteReq accesses(hits+misses) 155710636Snilay@cs.wisc.edusystem.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 548583 # number of WriteInvalidateReq accesses(hits+misses) 155810628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_accesses::total 548583 # number of WriteInvalidateReq accesses(hits+misses) 155910636Snilay@cs.wisc.edusystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2049698 # number of LoadLockedReq accesses(hits+misses) 156010628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 2049698 # number of LoadLockedReq accesses(hits+misses) 156110636Snilay@cs.wisc.edusystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2048188 # number of StoreCondReq accesses(hits+misses) 156210628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 2048188 # number of StoreCondReq accesses(hits+misses) 156310636Snilay@cs.wisc.edusystem.cpu1.dcache.demand_accesses::cpu1.data 163642606 # number of demand (read+write) accesses 156410628Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 163642606 # number of demand (read+write) accesses 156510636Snilay@cs.wisc.edusystem.cpu1.dcache.overall_accesses::cpu1.data 163642606 # number of overall (read+write) accesses 156610628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 163642606 # number of overall (read+write) accesses 156710636Snilay@cs.wisc.edusystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049103 # miss rate for ReadReq accesses 156810628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.049103 # miss rate for ReadReq accesses 156910636Snilay@cs.wisc.edusystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.031209 # miss rate for WriteReq accesses 157010628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.031209 # miss rate for WriteReq accesses 157110636Snilay@cs.wisc.edusystem.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.868771 # miss rate for WriteInvalidateReq accesses 157210628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.868771 # miss rate for WriteInvalidateReq accesses 157310636Snilay@cs.wisc.edusystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.068952 # miss rate for LoadLockedReq accesses 157410628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.068952 # miss rate for LoadLockedReq accesses 157510636Snilay@cs.wisc.edusystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.094646 # miss rate for StoreCondReq accesses 157610628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.094646 # miss rate for StoreCondReq accesses 157710636Snilay@cs.wisc.edusystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.040810 # miss rate for demand accesses 157810628Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.040810 # miss rate for demand accesses 157910636Snilay@cs.wisc.edusystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.040810 # miss rate for overall accesses 158010628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.040810 # miss rate for overall accesses 158110636Snilay@cs.wisc.edusystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14084.555044 # average ReadReq miss latency 158210628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 14084.555044 # average ReadReq miss latency 158310636Snilay@cs.wisc.edusystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16093.930856 # average WriteReq miss latency 158410628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 16093.930856 # average WriteReq miss latency 158510636Snilay@cs.wisc.edusystem.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 24366.929930 # average WriteInvalidateReq miss latency 158610628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 24366.929930 # average WriteInvalidateReq miss latency 158710636Snilay@cs.wisc.edusystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13994.339388 # average LoadLockedReq miss latency 158810628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13994.339388 # average LoadLockedReq miss latency 158910636Snilay@cs.wisc.edusystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20545.117182 # average StoreCondReq miss latency 159010628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20545.117182 # average StoreCondReq miss latency 159110636Snilay@cs.wisc.edusystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 159210585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 159310636Snilay@cs.wisc.edusystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14796.728543 # average overall miss latency 159410628Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 14796.728543 # average overall miss latency 159510636Snilay@cs.wisc.edusystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14796.728543 # average overall miss latency 159610628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 14796.728543 # average overall miss latency 159710585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 159810585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 159910585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 160010585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 160110585Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 160210585Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 160310585Sandreas.hansson@arm.comsystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 160410585Sandreas.hansson@arm.comsystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 160510628Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 3711348 # number of writebacks 160610628Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 3711348 # number of writebacks 160710636Snilay@cs.wisc.edusystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 397792 # number of ReadReq MSHR hits 160810628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 397792 # number of ReadReq MSHR hits 160910636Snilay@cs.wisc.edusystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 970938 # number of WriteReq MSHR hits 161010628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 970938 # number of WriteReq MSHR hits 161110636Snilay@cs.wisc.edusystem.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 60 # number of WriteInvalidateReq MSHR hits 161210628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 60 # number of WriteInvalidateReq MSHR hits 161310636Snilay@cs.wisc.edusystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 47 # number of LoadLockedReq MSHR hits 161410628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 47 # number of LoadLockedReq MSHR hits 161510636Snilay@cs.wisc.edusystem.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 68 # number of StoreCondReq MSHR hits 161610628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_hits::total 68 # number of StoreCondReq MSHR hits 161710636Snilay@cs.wisc.edusystem.cpu1.dcache.demand_mshr_hits::cpu1.data 1368730 # number of demand (read+write) MSHR hits 161810628Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::total 1368730 # number of demand (read+write) MSHR hits 161910636Snilay@cs.wisc.edusystem.cpu1.dcache.overall_mshr_hits::cpu1.data 1368730 # number of overall MSHR hits 162010628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::total 1368730 # number of overall MSHR hits 162110636Snilay@cs.wisc.edusystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3913497 # number of ReadReq MSHR misses 162210628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 3913497 # number of ReadReq MSHR misses 162310636Snilay@cs.wisc.edusystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1395991 # number of WriteReq MSHR misses 162410628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 1395991 # number of WriteReq MSHR misses 162510636Snilay@cs.wisc.edusystem.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 476533 # number of WriteInvalidateReq MSHR misses 162610628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 476533 # number of WriteInvalidateReq MSHR misses 162710636Snilay@cs.wisc.edusystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 141284 # number of LoadLockedReq MSHR misses 162810628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 141284 # number of LoadLockedReq MSHR misses 162910636Snilay@cs.wisc.edusystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193784 # number of StoreCondReq MSHR misses 163010628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 193784 # number of StoreCondReq MSHR misses 163110636Snilay@cs.wisc.edusystem.cpu1.dcache.demand_mshr_misses::cpu1.data 5309488 # number of demand (read+write) MSHR misses 163210628Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 5309488 # number of demand (read+write) MSHR misses 163310636Snilay@cs.wisc.edusystem.cpu1.dcache.overall_mshr_misses::cpu1.data 5309488 # number of overall MSHR misses 163410628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 5309488 # number of overall MSHR misses 163510636Snilay@cs.wisc.edusystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 46779736993 # number of ReadReq MSHR miss cycles 163610628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 46779736993 # number of ReadReq MSHR miss cycles 163710636Snilay@cs.wisc.edusystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 20386885918 # number of WriteReq MSHR miss cycles 163810628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 20386885918 # number of WriteReq MSHR miss cycles 163910636Snilay@cs.wisc.edusystem.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 10653380764 # number of WriteInvalidateReq MSHR miss cycles 164010628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 10653380764 # number of WriteInvalidateReq MSHR miss cycles 164110636Snilay@cs.wisc.edusystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1693632498 # number of LoadLockedReq MSHR miss cycles 164210628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1693632498 # number of LoadLockedReq MSHR miss cycles 164310636Snilay@cs.wisc.edusystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3584420895 # number of StoreCondReq MSHR miss cycles 164410628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3584420895 # number of StoreCondReq MSHR miss cycles 164510636Snilay@cs.wisc.edusystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1830000 # number of StoreCondFailReq MSHR miss cycles 164610628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1830000 # number of StoreCondFailReq MSHR miss cycles 164710636Snilay@cs.wisc.edusystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 67166622911 # number of demand (read+write) MSHR miss cycles 164810628Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 67166622911 # number of demand (read+write) MSHR miss cycles 164910636Snilay@cs.wisc.edusystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 67166622911 # number of overall MSHR miss cycles 165010628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 67166622911 # number of overall MSHR miss cycles 165110636Snilay@cs.wisc.edusystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 548139751 # number of ReadReq MSHR uncacheable cycles 165210628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 548139751 # number of ReadReq MSHR uncacheable cycles 165310636Snilay@cs.wisc.edusystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 613571252 # number of WriteReq MSHR uncacheable cycles 165410628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 613571252 # number of WriteReq MSHR uncacheable cycles 165510636Snilay@cs.wisc.edusystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1161711003 # number of overall MSHR uncacheable cycles 165610628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 1161711003 # number of overall MSHR uncacheable cycles 165710636Snilay@cs.wisc.edusystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.044572 # mshr miss rate for ReadReq accesses 165810628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.044572 # mshr miss rate for ReadReq accesses 165910636Snilay@cs.wisc.edusystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018407 # mshr miss rate for WriteReq accesses 166010628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018407 # mshr miss rate for WriteReq accesses 166110636Snilay@cs.wisc.edusystem.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.868662 # mshr miss rate for WriteInvalidateReq accesses 166210628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.868662 # mshr miss rate for WriteInvalidateReq accesses 166310636Snilay@cs.wisc.edusystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068929 # mshr miss rate for LoadLockedReq accesses 166410628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068929 # mshr miss rate for LoadLockedReq accesses 166510636Snilay@cs.wisc.edusystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.094612 # mshr miss rate for StoreCondReq accesses 166610628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.094612 # mshr miss rate for StoreCondReq accesses 166710636Snilay@cs.wisc.edusystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032446 # mshr miss rate for demand accesses 166810628Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.032446 # mshr miss rate for demand accesses 166910636Snilay@cs.wisc.edusystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032446 # mshr miss rate for overall accesses 167010628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.032446 # mshr miss rate for overall accesses 167110636Snilay@cs.wisc.edusystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11953.436273 # average ReadReq mshr miss latency 167210628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11953.436273 # average ReadReq mshr miss latency 167310636Snilay@cs.wisc.edusystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14603.880625 # average WriteReq mshr miss latency 167410628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14603.880625 # average WriteReq mshr miss latency 167510636Snilay@cs.wisc.edusystem.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 22356.018920 # average WriteInvalidateReq mshr miss latency 167610628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 22356.018920 # average WriteInvalidateReq mshr miss latency 167710636Snilay@cs.wisc.edusystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11987.433099 # average LoadLockedReq mshr miss latency 167810628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11987.433099 # average LoadLockedReq mshr miss latency 167910636Snilay@cs.wisc.edusystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 18496.990954 # average StoreCondReq mshr miss latency 168010628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18496.990954 # average StoreCondReq mshr miss latency 168110636Snilay@cs.wisc.edusystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 168210585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 168310636Snilay@cs.wisc.edusystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12650.301293 # average overall mshr miss latency 168410628Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 12650.301293 # average overall mshr miss latency 168510636Snilay@cs.wisc.edusystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12650.301293 # average overall mshr miss latency 168610628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 12650.301293 # average overall mshr miss latency 168710636Snilay@cs.wisc.edusystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 168810585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 168910636Snilay@cs.wisc.edusystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 169010585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 169110636Snilay@cs.wisc.edusystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 169210585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 169310585Sandreas.hansson@arm.comsystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 169410628Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 9215030 # number of replacements 169510628Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 507.228865 # Cycle average of tags in use 169610628Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 243489253 # Total number of references to valid blocks. 169710628Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 9215542 # Sample count of references to valid blocks. 169810628Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 26.421588 # Average number of references to valid blocks. 169910628Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 8367568177500 # Cycle when the warmup percentage was hit. 170010628Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 507.228865 # Average occupied blocks per requestor 170110628Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.990681 # Average percentage of cache occupancy 170210628Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.990681 # Average percentage of cache occupancy 170310585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 170410628Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 256 # Occupied blocks per task id 170510628Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id 170610628Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id 170710585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 170810628Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 514625132 # Number of tag accesses 170910628Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 514625132 # Number of data accesses 171010628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 243489253 # number of ReadReq hits 171110628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 243489253 # number of ReadReq hits 171210628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 243489253 # number of demand (read+write) hits 171310628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 243489253 # number of demand (read+write) hits 171410628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 243489253 # number of overall hits 171510628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 243489253 # number of overall hits 171610628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 9215542 # number of ReadReq misses 171710628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 9215542 # number of ReadReq misses 171810628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 9215542 # number of demand (read+write) misses 171910628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 9215542 # number of demand (read+write) misses 172010628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 9215542 # number of overall misses 172110628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 9215542 # number of overall misses 172210628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 91468274167 # number of ReadReq miss cycles 172310628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 91468274167 # number of ReadReq miss cycles 172410628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 91468274167 # number of demand (read+write) miss cycles 172510628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::total 91468274167 # number of demand (read+write) miss cycles 172610628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 91468274167 # number of overall miss cycles 172710628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::total 91468274167 # number of overall miss cycles 172810628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 252704795 # number of ReadReq accesses(hits+misses) 172910628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 252704795 # number of ReadReq accesses(hits+misses) 173010628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 252704795 # number of demand (read+write) accesses 173110628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 252704795 # number of demand (read+write) accesses 173210628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 252704795 # number of overall (read+write) accesses 173310628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 252704795 # number of overall (read+write) accesses 173410628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.036468 # miss rate for ReadReq accesses 173510628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.036468 # miss rate for ReadReq accesses 173610628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.036468 # miss rate for demand accesses 173710628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.036468 # miss rate for demand accesses 173810628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.036468 # miss rate for overall accesses 173910628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.036468 # miss rate for overall accesses 174010628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9925.436200 # average ReadReq miss latency 174110628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 9925.436200 # average ReadReq miss latency 174210628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9925.436200 # average overall miss latency 174310628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 9925.436200 # average overall miss latency 174410628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9925.436200 # average overall miss latency 174510628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 9925.436200 # average overall miss latency 174610585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 174710585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 174810585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 174910585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 175010585Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 175110585Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 175210585Sandreas.hansson@arm.comsystem.cpu1.icache.fast_writes 0 # number of fast writes performed 175310585Sandreas.hansson@arm.comsystem.cpu1.icache.cache_copies 0 # number of cache copies performed 175410628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9215542 # number of ReadReq MSHR misses 175510628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 9215542 # number of ReadReq MSHR misses 175610628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 9215542 # number of demand (read+write) MSHR misses 175710628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::total 9215542 # number of demand (read+write) MSHR misses 175810628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 9215542 # number of overall MSHR misses 175910628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::total 9215542 # number of overall MSHR misses 176010628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 77617743273 # number of ReadReq MSHR miss cycles 176110628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 77617743273 # number of ReadReq MSHR miss cycles 176210628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 77617743273 # number of demand (read+write) MSHR miss cycles 176310628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 77617743273 # number of demand (read+write) MSHR miss cycles 176410628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 77617743273 # number of overall MSHR miss cycles 176510628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 77617743273 # number of overall MSHR miss cycles 176610628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8388750 # number of ReadReq MSHR uncacheable cycles 176710628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8388750 # number of ReadReq MSHR uncacheable cycles 176810628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8388750 # number of overall MSHR uncacheable cycles 176910628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::total 8388750 # number of overall MSHR uncacheable cycles 177010628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.036468 # mshr miss rate for ReadReq accesses 177110628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.036468 # mshr miss rate for ReadReq accesses 177210628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.036468 # mshr miss rate for demand accesses 177310628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.036468 # mshr miss rate for demand accesses 177410628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.036468 # mshr miss rate for overall accesses 177510628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.036468 # mshr miss rate for overall accesses 177610628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8422.482722 # average ReadReq mshr miss latency 177710628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8422.482722 # average ReadReq mshr miss latency 177810628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8422.482722 # average overall mshr miss latency 177910628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 8422.482722 # average overall mshr miss latency 178010628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8422.482722 # average overall mshr miss latency 178110628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 8422.482722 # average overall mshr miss latency 178210585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 178310585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 178410585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 178510585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 178610585Sandreas.hansson@arm.comsystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 178710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.num_hwpf_issued 11995647 # number of hwpf issued 178810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfIdentified 12001276 # number of prefetch candidates identified 178910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfBufferHit 4903 # number of redundant prefetches already in prefetch queue 179010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 179110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 179210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfSpanPage 1360052 # number of prefetches not generated due to page crossing 179310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.replacements 2569302 # number of replacements 179410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tagsinuse 13533.660217 # Cycle average of tags in use 179510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.total_refs 15700970 # Total number of references to valid blocks. 179610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.sampled_refs 2584965 # Sample count of references to valid blocks. 179710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.avg_refs 6.073958 # Average number of references to valid blocks. 179810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 9611078525000 # Cycle when the warmup percentage was hit. 179910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 5526.220513 # Average occupied blocks per requestor 180010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 77.627317 # Average occupied blocks per requestor 180110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 76.256480 # Average occupied blocks per requestor 180210636Snilay@cs.wisc.edusystem.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3620.154380 # Average occupied blocks per requestor 180310636Snilay@cs.wisc.edusystem.cpu1.l2cache.tags.occ_blocks::cpu1.data 2817.959604 # Average occupied blocks per requestor 180410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1415.441924 # Average occupied blocks per requestor 180510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.337294 # Average percentage of cache occupancy 180610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004738 # Average percentage of cache occupancy 180710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004654 # Average percentage of cache occupancy 180810636Snilay@cs.wisc.edusystem.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.220957 # Average percentage of cache occupancy 180910636Snilay@cs.wisc.edusystem.cpu1.l2cache.tags.occ_percent::cpu1.data 0.171995 # Average percentage of cache occupancy 181010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.086392 # Average percentage of cache occupancy 181110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.826029 # Average percentage of cache occupancy 181210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1022 2491 # Occupied blocks per task id 181310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 92 # Occupied blocks per task id 181410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 13080 # Occupied blocks per task id 181510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id 181610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::2 600 # Occupied blocks per task id 181710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1302 # Occupied blocks per task id 181810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::4 576 # Occupied blocks per task id 181910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id 182010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id 182110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 72 # Occupied blocks per task id 182210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id 182310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 182410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id 182510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id 182610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4875 # Occupied blocks per task id 182710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5316 # Occupied blocks per task id 182810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2499 # Occupied blocks per task id 182910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1022 0.152039 # Percentage of cache occupancy per task id 183010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005615 # Percentage of cache occupancy per task id 183110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.798340 # Percentage of cache occupancy per task id 183210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tag_accesses 321109712 # Number of tag accesses 183310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.data_accesses 321109712 # Number of data accesses 183410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 544517 # number of ReadReq hits 183510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 158528 # number of ReadReq hits 183610636Snilay@cs.wisc.edusystem.cpu1.l2cache.ReadReq_hits::cpu1.inst 8400098 # number of ReadReq hits 183710636Snilay@cs.wisc.edusystem.cpu1.l2cache.ReadReq_hits::cpu1.data 3278512 # number of ReadReq hits 183810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 12381655 # number of ReadReq hits 183910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_hits::writebacks 3711345 # number of Writeback hits 184010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_hits::total 3711345 # number of Writeback hits 184110636Snilay@cs.wisc.edusystem.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 202419 # number of WriteInvalidateReq hits 184210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_hits::total 202419 # number of WriteInvalidateReq hits 184310636Snilay@cs.wisc.edusystem.cpu1.l2cache.UpgradeReq_hits::cpu1.data 77280 # number of UpgradeReq hits 184410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::total 77280 # number of UpgradeReq hits 184510636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 41809 # number of SCUpgradeReq hits 184610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_hits::total 41809 # number of SCUpgradeReq hits 184710636Snilay@cs.wisc.edusystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 939119 # number of ReadExReq hits 184810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 939119 # number of ReadExReq hits 184910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 544517 # number of demand (read+write) hits 185010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 158528 # number of demand (read+write) hits 185110636Snilay@cs.wisc.edusystem.cpu1.l2cache.demand_hits::cpu1.inst 8400098 # number of demand (read+write) hits 185210636Snilay@cs.wisc.edusystem.cpu1.l2cache.demand_hits::cpu1.data 4217631 # number of demand (read+write) hits 185310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::total 13320774 # number of demand (read+write) hits 185410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 544517 # number of overall hits 185510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 158528 # number of overall hits 185610636Snilay@cs.wisc.edusystem.cpu1.l2cache.overall_hits::cpu1.inst 8400098 # number of overall hits 185710636Snilay@cs.wisc.edusystem.cpu1.l2cache.overall_hits::cpu1.data 4217631 # number of overall hits 185810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::total 13320774 # number of overall hits 185910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12561 # number of ReadReq misses 186010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8870 # number of ReadReq misses 186110636Snilay@cs.wisc.edusystem.cpu1.l2cache.ReadReq_misses::cpu1.inst 815444 # number of ReadReq misses 186210636Snilay@cs.wisc.edusystem.cpu1.l2cache.ReadReq_misses::cpu1.data 775983 # number of ReadReq misses 186310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 1612858 # number of ReadReq misses 186410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses 186510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses 186610636Snilay@cs.wisc.edusystem.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 272843 # number of WriteInvalidateReq misses 186710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_misses::total 272843 # number of WriteInvalidateReq misses 186810636Snilay@cs.wisc.edusystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 137034 # number of UpgradeReq misses 186910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 137034 # number of UpgradeReq misses 187010636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 151974 # number of SCUpgradeReq misses 187110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 151974 # number of SCUpgradeReq misses 187210636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses 187310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses 187410636Snilay@cs.wisc.edusystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 244121 # number of ReadExReq misses 187510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 244121 # number of ReadExReq misses 187610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12561 # number of demand (read+write) misses 187710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 8870 # number of demand (read+write) misses 187810636Snilay@cs.wisc.edusystem.cpu1.l2cache.demand_misses::cpu1.inst 815444 # number of demand (read+write) misses 187910636Snilay@cs.wisc.edusystem.cpu1.l2cache.demand_misses::cpu1.data 1020104 # number of demand (read+write) misses 188010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::total 1856979 # number of demand (read+write) misses 188110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12561 # number of overall misses 188210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 8870 # number of overall misses 188310636Snilay@cs.wisc.edusystem.cpu1.l2cache.overall_misses::cpu1.inst 815444 # number of overall misses 188410636Snilay@cs.wisc.edusystem.cpu1.l2cache.overall_misses::cpu1.data 1020104 # number of overall misses 188510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::total 1856979 # number of overall misses 188610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 455863233 # number of ReadReq miss cycles 188710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 358991737 # number of ReadReq miss cycles 188810636Snilay@cs.wisc.edusystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 22574174788 # number of ReadReq miss cycles 188910636Snilay@cs.wisc.edusystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 24632424000 # number of ReadReq miss cycles 189010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::total 48021453758 # number of ReadReq miss cycles 189110636Snilay@cs.wisc.edusystem.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 213581444 # number of WriteInvalidateReq miss cycles 189210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 213581444 # number of WriteInvalidateReq miss cycles 189310636Snilay@cs.wisc.edusystem.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2792930491 # number of UpgradeReq miss cycles 189410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::total 2792930491 # number of UpgradeReq miss cycles 189510636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3071034580 # number of SCUpgradeReq miss cycles 189610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3071034580 # number of SCUpgradeReq miss cycles 189710636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1783500 # number of SCUpgradeFailReq miss cycles 189810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1783500 # number of SCUpgradeFailReq miss cycles 189910636Snilay@cs.wisc.edusystem.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 9626384839 # number of ReadExReq miss cycles 190010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::total 9626384839 # number of ReadExReq miss cycles 190110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 455863233 # number of demand (read+write) miss cycles 190210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 358991737 # number of demand (read+write) miss cycles 190310636Snilay@cs.wisc.edusystem.cpu1.l2cache.demand_miss_latency::cpu1.inst 22574174788 # number of demand (read+write) miss cycles 190410636Snilay@cs.wisc.edusystem.cpu1.l2cache.demand_miss_latency::cpu1.data 34258808839 # number of demand (read+write) miss cycles 190510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::total 57647838597 # number of demand (read+write) miss cycles 190610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 455863233 # number of overall miss cycles 190710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 358991737 # number of overall miss cycles 190810636Snilay@cs.wisc.edusystem.cpu1.l2cache.overall_miss_latency::cpu1.inst 22574174788 # number of overall miss cycles 190910636Snilay@cs.wisc.edusystem.cpu1.l2cache.overall_miss_latency::cpu1.data 34258808839 # number of overall miss cycles 191010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::total 57647838597 # number of overall miss cycles 191110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 557078 # number of ReadReq accesses(hits+misses) 191210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 167398 # number of ReadReq accesses(hits+misses) 191310636Snilay@cs.wisc.edusystem.cpu1.l2cache.ReadReq_accesses::cpu1.inst 9215542 # number of ReadReq accesses(hits+misses) 191410636Snilay@cs.wisc.edusystem.cpu1.l2cache.ReadReq_accesses::cpu1.data 4054495 # number of ReadReq accesses(hits+misses) 191510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 13994513 # number of ReadReq accesses(hits+misses) 191610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_accesses::writebacks 3711346 # number of Writeback accesses(hits+misses) 191710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_accesses::total 3711346 # number of Writeback accesses(hits+misses) 191810636Snilay@cs.wisc.edusystem.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 475262 # number of WriteInvalidateReq accesses(hits+misses) 191910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_accesses::total 475262 # number of WriteInvalidateReq accesses(hits+misses) 192010636Snilay@cs.wisc.edusystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 214314 # number of UpgradeReq accesses(hits+misses) 192110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 214314 # number of UpgradeReq accesses(hits+misses) 192210636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 193783 # number of SCUpgradeReq accesses(hits+misses) 192310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 193783 # number of SCUpgradeReq accesses(hits+misses) 192410636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) 192510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) 192610636Snilay@cs.wisc.edusystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1183240 # number of ReadExReq accesses(hits+misses) 192710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 1183240 # number of ReadExReq accesses(hits+misses) 192810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 557078 # number of demand (read+write) accesses 192910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 167398 # number of demand (read+write) accesses 193010636Snilay@cs.wisc.edusystem.cpu1.l2cache.demand_accesses::cpu1.inst 9215542 # number of demand (read+write) accesses 193110636Snilay@cs.wisc.edusystem.cpu1.l2cache.demand_accesses::cpu1.data 5237735 # number of demand (read+write) accesses 193210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::total 15177753 # number of demand (read+write) accesses 193310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 557078 # number of overall (read+write) accesses 193410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 167398 # number of overall (read+write) accesses 193510636Snilay@cs.wisc.edusystem.cpu1.l2cache.overall_accesses::cpu1.inst 9215542 # number of overall (read+write) accesses 193610636Snilay@cs.wisc.edusystem.cpu1.l2cache.overall_accesses::cpu1.data 5237735 # number of overall (read+write) accesses 193710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::total 15177753 # number of overall (read+write) accesses 193810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.022548 # miss rate for ReadReq accesses 193910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.052987 # miss rate for ReadReq accesses 194010636Snilay@cs.wisc.edusystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.088486 # miss rate for ReadReq accesses 194110636Snilay@cs.wisc.edusystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.191388 # miss rate for ReadReq accesses 194210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.115249 # miss rate for ReadReq accesses 194310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses 194410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses 194510636Snilay@cs.wisc.edusystem.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.574090 # miss rate for WriteInvalidateReq accesses 194610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.574090 # miss rate for WriteInvalidateReq accesses 194710636Snilay@cs.wisc.edusystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.639408 # miss rate for UpgradeReq accesses 194810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 0.639408 # miss rate for UpgradeReq accesses 194910636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.784248 # miss rate for SCUpgradeReq accesses 195010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.784248 # miss rate for SCUpgradeReq accesses 195110636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 195210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 195310636Snilay@cs.wisc.edusystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.206316 # miss rate for ReadExReq accesses 195410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.206316 # miss rate for ReadExReq accesses 195510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.022548 # miss rate for demand accesses 195610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.052987 # miss rate for demand accesses 195710636Snilay@cs.wisc.edusystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.088486 # miss rate for demand accesses 195810636Snilay@cs.wisc.edusystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.194761 # miss rate for demand accesses 195910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.122349 # miss rate for demand accesses 196010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.022548 # miss rate for overall accesses 196110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.052987 # miss rate for overall accesses 196210636Snilay@cs.wisc.edusystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.088486 # miss rate for overall accesses 196310636Snilay@cs.wisc.edusystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.194761 # miss rate for overall accesses 196410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.122349 # miss rate for overall accesses 196510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 36291.953905 # average ReadReq miss latency 196610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 40472.574634 # average ReadReq miss latency 196710636Snilay@cs.wisc.edusystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 27683.292523 # average ReadReq miss latency 196810636Snilay@cs.wisc.edusystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 31743.509845 # average ReadReq miss latency 196910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::total 29774.136197 # average ReadReq miss latency 197010636Snilay@cs.wisc.edusystem.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 782.799793 # average WriteInvalidateReq miss latency 197110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 782.799793 # average WriteInvalidateReq miss latency 197210636Snilay@cs.wisc.edusystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 20381.295817 # average UpgradeReq miss latency 197310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 20381.295817 # average UpgradeReq miss latency 197410636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20207.631437 # average SCUpgradeReq miss latency 197510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20207.631437 # average SCUpgradeReq miss latency 197610636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 1783500 # average SCUpgradeFailReq miss latency 197710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1783500 # average SCUpgradeFailReq miss latency 197810636Snilay@cs.wisc.edusystem.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39432.842070 # average ReadExReq miss latency 197910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39432.842070 # average ReadExReq miss latency 198010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 36291.953905 # average overall miss latency 198110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 40472.574634 # average overall miss latency 198210636Snilay@cs.wisc.edusystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 27683.292523 # average overall miss latency 198310636Snilay@cs.wisc.edusystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33583.643275 # average overall miss latency 198410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::total 31043.882886 # average overall miss latency 198510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 36291.953905 # average overall miss latency 198610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 40472.574634 # average overall miss latency 198710636Snilay@cs.wisc.edusystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 27683.292523 # average overall miss latency 198810636Snilay@cs.wisc.edusystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33583.643275 # average overall miss latency 198910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::total 31043.882886 # average overall miss latency 199010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 199110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 199210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 199310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 199410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 199510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 199610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.fast_writes 0 # number of fast writes performed 199710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.cache_copies 0 # number of cache copies performed 199810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::writebacks 1092301 # number of writebacks 199910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::total 1092301 # number of writebacks 200010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 1 # number of ReadReq MSHR hits 200110636Snilay@cs.wisc.edusystem.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits 200210636Snilay@cs.wisc.edusystem.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 1804 # number of ReadReq MSHR hits 200310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::total 1806 # number of ReadReq MSHR hits 200410636Snilay@cs.wisc.edusystem.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data 45 # number of WriteInvalidateReq MSHR hits 200510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total 45 # number of WriteInvalidateReq MSHR hits 200610636Snilay@cs.wisc.edusystem.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 7072 # number of ReadExReq MSHR hits 200710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::total 7072 # number of ReadExReq MSHR hits 200810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 1 # number of demand (read+write) MSHR hits 200910636Snilay@cs.wisc.edusystem.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits 201010636Snilay@cs.wisc.edusystem.cpu1.l2cache.demand_mshr_hits::cpu1.data 8876 # number of demand (read+write) MSHR hits 201110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::total 8878 # number of demand (read+write) MSHR hits 201210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 1 # number of overall MSHR hits 201310636Snilay@cs.wisc.edusystem.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits 201410636Snilay@cs.wisc.edusystem.cpu1.l2cache.overall_mshr_hits::cpu1.data 8876 # number of overall MSHR hits 201510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::total 8878 # number of overall MSHR hits 201610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 12561 # number of ReadReq MSHR misses 201710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8869 # number of ReadReq MSHR misses 201810636Snilay@cs.wisc.edusystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 815443 # number of ReadReq MSHR misses 201910636Snilay@cs.wisc.edusystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 774179 # number of ReadReq MSHR misses 202010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::total 1611052 # number of ReadReq MSHR misses 202110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses 202210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses 202310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 1032302 # number of HardPFReq MSHR misses 202410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::total 1032302 # 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number of overall MSHR misses 204110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8869 # number of overall MSHR misses 204210636Snilay@cs.wisc.edusystem.cpu1.l2cache.overall_mshr_misses::cpu1.inst 815443 # number of overall MSHR misses 204310636Snilay@cs.wisc.edusystem.cpu1.l2cache.overall_mshr_misses::cpu1.data 1011228 # number of overall MSHR misses 204410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 1032302 # number of overall MSHR misses 204510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::total 2880403 # number of overall MSHR misses 204610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 367223255 # number of ReadReq MSHR miss cycles 204710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 296231251 # number of ReadReq MSHR miss cycles 204810636Snilay@cs.wisc.edusystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 16845762712 # number of ReadReq MSHR miss cycles 204910636Snilay@cs.wisc.edusystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 19051693106 # number of ReadReq MSHR miss cycles 205010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::total 36560910324 # number of ReadReq MSHR miss cycles 205110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 41289088164 # number of HardPFReq MSHR miss cycles 205210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 41289088164 # number of HardPFReq MSHR miss cycles 205310636Snilay@cs.wisc.edusystem.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 7103244766 # number of WriteInvalidateReq MSHR miss cycles 205410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 7103244766 # number of WriteInvalidateReq MSHR miss cycles 205510636Snilay@cs.wisc.edusystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2312644672 # number of UpgradeReq MSHR miss cycles 205610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2312644672 # number of UpgradeReq MSHR miss cycles 205710636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2076231085 # number of SCUpgradeReq MSHR miss cycles 205810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2076231085 # number of SCUpgradeReq MSHR miss cycles 205910636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1461500 # number of SCUpgradeFailReq MSHR miss cycles 206010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1461500 # number of SCUpgradeFailReq MSHR miss cycles 206110636Snilay@cs.wisc.edusystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7288633813 # number of ReadExReq MSHR miss cycles 206210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7288633813 # number of ReadExReq MSHR miss cycles 206310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 367223255 # number of demand (read+write) MSHR miss cycles 206410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 296231251 # number of demand (read+write) MSHR miss cycles 206510636Snilay@cs.wisc.edusystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 16845762712 # number of demand (read+write) MSHR miss cycles 206610636Snilay@cs.wisc.edusystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 26340326919 # number of demand (read+write) MSHR miss cycles 206710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::total 43849544137 # number of demand (read+write) MSHR miss cycles 206810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 367223255 # number of overall MSHR miss cycles 206910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 296231251 # number of overall MSHR miss cycles 207010636Snilay@cs.wisc.edusystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 16845762712 # number of overall MSHR miss cycles 207110636Snilay@cs.wisc.edusystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 26340326919 # number of overall MSHR miss cycles 207210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 41289088164 # number of overall MSHR miss cycles 207310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::total 85138632301 # number of overall MSHR miss cycles 207410636Snilay@cs.wisc.edusystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7364250 # number of ReadReq MSHR uncacheable cycles 207510636Snilay@cs.wisc.edusystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 506877748 # number of ReadReq MSHR uncacheable cycles 207610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 514241998 # number of ReadReq MSHR uncacheable cycles 207710636Snilay@cs.wisc.edusystem.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 574249999 # number of WriteReq MSHR uncacheable cycles 207810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 574249999 # number of WriteReq MSHR uncacheable cycles 207910636Snilay@cs.wisc.edusystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7364250 # number of overall MSHR uncacheable cycles 208010636Snilay@cs.wisc.edusystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1081127747 # number of overall MSHR uncacheable cycles 208110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1088491997 # number of overall MSHR uncacheable cycles 208210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022548 # mshr miss rate for ReadReq accesses 208310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.052982 # mshr miss rate for ReadReq accesses 208410636Snilay@cs.wisc.edusystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.088486 # mshr miss rate for ReadReq accesses 208510636Snilay@cs.wisc.edusystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.190943 # mshr miss rate for ReadReq accesses 208610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.115120 # mshr miss rate for ReadReq accesses 208710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses 208810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses 208910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 209010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 209110636Snilay@cs.wisc.edusystem.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.573995 # mshr miss rate for WriteInvalidateReq accesses 209210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.573995 # mshr miss rate for WriteInvalidateReq accesses 209310636Snilay@cs.wisc.edusystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.639408 # mshr miss rate for UpgradeReq accesses 209410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.639408 # mshr miss rate for UpgradeReq accesses 209510636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.784248 # mshr miss rate for SCUpgradeReq accesses 209610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.784248 # mshr miss rate for SCUpgradeReq accesses 209710636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 209810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 209910636Snilay@cs.wisc.edusystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.200339 # mshr miss rate for ReadExReq accesses 210010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.200339 # mshr miss rate for ReadExReq accesses 210110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022548 # mshr miss rate for demand accesses 210210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.052982 # mshr miss rate for demand accesses 210310636Snilay@cs.wisc.edusystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.088486 # mshr miss rate for demand accesses 210410636Snilay@cs.wisc.edusystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.193066 # mshr miss rate for demand accesses 210510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::total 0.121764 # mshr miss rate for demand accesses 210610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022548 # mshr miss rate for overall accesses 210710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.052982 # mshr miss rate for overall accesses 210810636Snilay@cs.wisc.edusystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.088486 # mshr miss rate for overall accesses 210910636Snilay@cs.wisc.edusystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.193066 # mshr miss rate for overall accesses 211010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 211110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::total 0.189778 # mshr miss rate for overall accesses 211210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660 # average ReadReq mshr miss latency 211310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 33400.749915 # average ReadReq mshr miss latency 211410636Snilay@cs.wisc.edusystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 20658.418445 # average ReadReq mshr miss latency 211510636Snilay@cs.wisc.edusystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 24608.899371 # average ReadReq mshr miss latency 211610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 22693.811450 # average ReadReq mshr miss latency 211710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39997.101782 # average HardPFReq mshr miss latency 211810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39997.101782 # average HardPFReq mshr miss latency 211910636Snilay@cs.wisc.edusystem.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 26038.478163 # average WriteInvalidateReq mshr miss latency 212010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 26038.478163 # average WriteInvalidateReq mshr miss latency 212110636Snilay@cs.wisc.edusystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16876.429733 # average UpgradeReq mshr miss latency 212210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16876.429733 # average UpgradeReq mshr miss latency 212310636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13661.751912 # average SCUpgradeReq mshr miss latency 212410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13661.751912 # average SCUpgradeReq mshr miss latency 212510636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1461500 # average SCUpgradeFailReq mshr miss latency 212610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1461500 # average SCUpgradeFailReq mshr miss latency 212710636Snilay@cs.wisc.edusystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30747.372117 # average ReadExReq mshr miss latency 212810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30747.372117 # average ReadExReq mshr miss latency 212910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660 # average overall mshr miss latency 213010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 33400.749915 # average overall mshr miss latency 213110636Snilay@cs.wisc.edusystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 20658.418445 # average overall mshr miss latency 213210636Snilay@cs.wisc.edusystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26047.861530 # average overall mshr miss latency 213310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23726.811542 # average overall mshr miss latency 213410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660 # average overall mshr miss latency 213510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 33400.749915 # average overall mshr miss latency 213610636Snilay@cs.wisc.edusystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 20658.418445 # average overall mshr miss latency 213710636Snilay@cs.wisc.edusystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26047.861530 # average overall mshr miss latency 213810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39997.101782 # average overall mshr miss latency 213910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29557.889053 # average overall mshr miss latency 214010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 214110636Snilay@cs.wisc.edusystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 214210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 214310636Snilay@cs.wisc.edusystem.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 214410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 214510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 214610636Snilay@cs.wisc.edusystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 214710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 214810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 214910628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 16597851 # Transaction distribution 215010628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 14230777 # Transaction distribution 215110628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 5242 # Transaction distribution 215210628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 5242 # Transaction distribution 215310628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::Writeback 3711346 # Transaction distribution 215410628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFReq 1418597 # Transaction distribution 215510628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 215610628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1143341 # Transaction distribution 215710628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 475262 # Transaction distribution 215810628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 452039 # Transaction distribution 215910628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 340076 # Transaction distribution 216010628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 470072 # Transaction distribution 216110628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 58 # Transaction distribution 216210628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution 216310628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 1342662 # Transaction distribution 216410628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 1189275 # Transaction distribution 216510628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18431264 # Packet count per connected master and slave (bytes) 216610628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16132557 # Packet count per connected master and slave (bytes) 216710628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 369420 # Packet count per connected master and slave (bytes) 216810628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1220438 # Packet count per connected master and slave (bytes) 216910628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count::total 36153679 # Packet count per connected master and slave (bytes) 217010628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 589800448 # Cumulative packet size per connected master and slave (bytes) 217110628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 609347251 # Cumulative packet size per connected master and slave (bytes) 217210628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1339184 # Cumulative packet size per connected master and slave (bytes) 217310628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4456624 # Cumulative packet size per connected master and slave (bytes) 217410628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size::total 1204943507 # Cumulative packet size per connected master and slave (bytes) 217510628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoops 5386490 # Total snoops (count) 217610628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 25000724 # Request fanout histogram 217710628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 5.203488 # Request fanout histogram 217810628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.402593 # Request fanout histogram 217910585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 218010585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 218110585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 218210585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 218310585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 218410585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 218510628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::5 19913365 79.65% 79.65% # Request fanout histogram 218610628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::6 5087359 20.35% 100.00% # Request fanout histogram 218710585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 218810585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 218910585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 219010628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 25000724 # Request fanout histogram 219110628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.reqLayer0.occupancy 14152090513 # Layer occupancy (ticks) 219210585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 219310628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopLayer0.occupancy 175296997 # Layer occupancy (ticks) 219410585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 219510628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer0.occupancy 13837074197 # Layer occupancy (ticks) 219610585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 219710628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer1.occupancy 8360530852 # Layer occupancy (ticks) 219810585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 219910628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer2.occupancy 202402154 # Layer occupancy (ticks) 220010585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 220110628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer3.occupancy 663973984 # Layer occupancy (ticks) 220210585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 220310628Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 40424 # Transaction distribution 220410628Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 40424 # Transaction distribution 220510628Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 136766 # Transaction distribution 220610628Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 30038 # Transaction distribution 220710585Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution 220810628Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48186 # Packet count per connected master and slave (bytes) 220910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 221010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 221110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 221210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 221310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 221410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 221510585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 221610585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 221710585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 221810585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 221910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 222010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 222110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 222210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 222310628Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 123068 # Packet count per connected master and slave (bytes) 222410628Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231232 # Packet count per connected master and slave (bytes) 222510628Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231232 # Packet count per connected master and slave (bytes) 222610585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 222710585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 222810628Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 354380 # Packet count per connected master and slave (bytes) 222910628Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48206 # Cumulative packet size per connected master and slave (bytes) 223010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 223110585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 223210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 223310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 223410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 223510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 223610585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 223710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 223810585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 223910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 224010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 224110585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 224210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 224310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 224410628Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 156198 # Cumulative packet size per connected master and slave (bytes) 224510628Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338944 # Cumulative packet size per connected master and slave (bytes) 224610628Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7338944 # Cumulative packet size per connected master and slave (bytes) 224710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 224810585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 224910628Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 7497228 # Cumulative packet size per connected master and slave (bytes) 225010628Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 36614000 # Layer occupancy (ticks) 225110585Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 225210585Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 225310585Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 225410585Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 225510585Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 225610585Sandreas.hansson@arm.comsystem.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 225710585Sandreas.hansson@arm.comsystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 225810585Sandreas.hansson@arm.comsystem.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 225910585Sandreas.hansson@arm.comsystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 226010585Sandreas.hansson@arm.comsystem.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 226110585Sandreas.hansson@arm.comsystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 226210585Sandreas.hansson@arm.comsystem.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 226310585Sandreas.hansson@arm.comsystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 226410585Sandreas.hansson@arm.comsystem.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 226510585Sandreas.hansson@arm.comsystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 226610585Sandreas.hansson@arm.comsystem.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 226710585Sandreas.hansson@arm.comsystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 226810585Sandreas.hansson@arm.comsystem.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 226910585Sandreas.hansson@arm.comsystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 227010585Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) 227110585Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 227210585Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 227310585Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 227410585Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 227510585Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 227610585Sandreas.hansson@arm.comsystem.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 227710585Sandreas.hansson@arm.comsystem.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 227810628Sandreas.hansson@arm.comsystem.iobus.reqLayer27.occupancy 1043031468 # Layer occupancy (ticks) 227910585Sandreas.hansson@arm.comsystem.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 228010585Sandreas.hansson@arm.comsystem.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 228110585Sandreas.hansson@arm.comsystem.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 228210628Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 93033000 # Layer occupancy (ticks) 228310585Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 228410628Sandreas.hansson@arm.comsystem.iobus.respLayer3.occupancy 179210230 # Layer occupancy (ticks) 228510585Sandreas.hansson@arm.comsystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 228610585Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) 228710585Sandreas.hansson@arm.comsystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 228810628Sandreas.hansson@arm.comsystem.iocache.tags.replacements 115597 # number of replacements 228910628Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 11.297216 # Cycle average of tags in use 229010585Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 229110628Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 115613 # Sample count of references to valid blocks. 229210585Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 229310628Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 9126956441000 # Cycle when the warmup percentage was hit. 229410628Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 3.841188 # Average occupied blocks per requestor 229510628Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 7.456028 # Average occupied blocks per requestor 229610628Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.240074 # Average percentage of cache occupancy 229710628Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.466002 # Average percentage of cache occupancy 229810628Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.706076 # Average percentage of cache occupancy 229910585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 230010585Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 230110585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 230210628Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 1040901 # Number of tag accesses 230310628Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 1040901 # Number of data accesses 230410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 230510628Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ide 8888 # number of ReadReq misses 230610628Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 8925 # number of ReadReq misses 230710585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 230810585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 230910585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses 231010585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses 231110585Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 231210628Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ide 8888 # number of demand (read+write) misses 231310628Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 8928 # number of demand (read+write) misses 231410585Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 231510628Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ide 8888 # number of overall misses 231610628Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 8928 # number of overall misses 231710628Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5659000 # number of ReadReq miss cycles 231810628Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ide 1934548608 # number of ReadReq miss cycles 231910628Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 1940207608 # number of ReadReq miss cycles 232010585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::realview.ethernet 357000 # number of WriteReq miss cycles 232110585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::total 357000 # number of WriteReq miss cycles 232210628Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_latency::realview.ide 28977416630 # number of WriteInvalidateReq miss cycles 232310628Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_latency::total 28977416630 # number of WriteInvalidateReq miss cycles 232410628Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ethernet 6016000 # number of demand (read+write) miss cycles 232510628Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ide 1934548608 # number of demand (read+write) miss cycles 232610628Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 1940564608 # number of demand (read+write) miss cycles 232710628Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ethernet 6016000 # number of overall miss cycles 232810628Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ide 1934548608 # number of overall miss cycles 232910628Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 1940564608 # number of overall miss cycles 233010585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 233110628Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8888 # number of ReadReq accesses(hits+misses) 233210628Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 8925 # number of ReadReq accesses(hits+misses) 233310585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 233410585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 233510585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) 233610585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) 233710585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 233810628Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ide 8888 # number of demand (read+write) accesses 233910628Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 8928 # number of demand (read+write) accesses 234010585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 234110628Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 8888 # number of overall (read+write) accesses 234210628Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 8928 # number of overall (read+write) accesses 234310585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 234410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 234510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 234610585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 234710585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 234810585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 234910585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 235010585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 235110585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 235210585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 235310585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 235410585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 235510585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 235610628Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 152945.945946 # average ReadReq miss latency 235710628Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 217658.484248 # average ReadReq miss latency 235810628Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 217390.208179 # average ReadReq miss latency 235910585Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency 236010585Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency 236110628Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271507.164287 # average WriteInvalidateReq miss latency 236210628Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_avg_miss_latency::total 271507.164287 # average WriteInvalidateReq miss latency 236310628Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 150400 # average overall miss latency 236410628Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ide 217658.484248 # average overall miss latency 236510628Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 217357.146953 # average overall miss latency 236610628Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 150400 # average overall miss latency 236710628Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ide 217658.484248 # average overall miss latency 236810628Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 217357.146953 # average overall miss latency 236910628Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 228934 # number of cycles access was blocked 237010585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 237110628Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 27737 # number of cycles access was blocked 237210585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 237310628Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 8.253740 # average number of cycles each access was blocked 237410585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 237510585Sandreas.hansson@arm.comsystem.iocache.fast_writes 0 # number of fast writes performed 237610585Sandreas.hansson@arm.comsystem.iocache.cache_copies 0 # number of cache copies performed 237710585Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 106694 # number of writebacks 237810585Sandreas.hansson@arm.comsystem.iocache.writebacks::total 106694 # number of writebacks 237910585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 238010628Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8888 # number of ReadReq MSHR misses 238110628Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::total 8925 # number of ReadReq MSHR misses 238210585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 238310585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 238410585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses 238510585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses 238610585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 238710628Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ide 8888 # number of demand (read+write) MSHR misses 238810628Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::total 8928 # number of demand (read+write) MSHR misses 238910585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 239010628Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ide 8888 # number of overall MSHR misses 239110628Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::total 8928 # number of overall MSHR misses 239210628Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3735000 # number of ReadReq MSHR miss cycles 239310628Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1472256614 # number of ReadReq MSHR miss cycles 239410628Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 1475991614 # number of ReadReq MSHR miss cycles 239510585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 239610585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 239710628Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23427107084 # number of WriteInvalidateReq MSHR miss cycles 239810628Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_miss_latency::total 23427107084 # number of WriteInvalidateReq MSHR miss cycles 239910628Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3936000 # number of demand (read+write) MSHR miss cycles 240010628Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ide 1472256614 # number of demand (read+write) MSHR miss cycles 240110628Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 1476192614 # number of demand (read+write) MSHR miss cycles 240210628Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3936000 # number of overall MSHR miss cycles 240310628Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ide 1472256614 # number of overall MSHR miss cycles 240410628Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 1476192614 # number of overall MSHR miss cycles 240510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 240610585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 240710585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 240810585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 240910585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 241010585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 241110585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 241210585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 241310585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 241410585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 241510585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 241610585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 241710585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 241810628Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 100945.945946 # average ReadReq mshr miss latency 241910628Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 165645.433618 # average ReadReq mshr miss latency 242010628Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 165377.211653 # average ReadReq mshr miss latency 242110585Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 242210585Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 242310628Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219502.914737 # average WriteInvalidateReq mshr miss latency 242410628Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219502.914737 # average WriteInvalidateReq mshr miss latency 242510628Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 98400 # average overall mshr miss latency 242610628Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 165645.433618 # average overall mshr miss latency 242710628Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 165344.154794 # average overall mshr miss latency 242810628Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 98400 # average overall mshr miss latency 242910628Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 165645.433618 # average overall mshr miss latency 243010628Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 165344.154794 # average overall mshr miss latency 243110585Sandreas.hansson@arm.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 243210628Sandreas.hansson@arm.comsystem.l2c.tags.replacements 1473453 # number of replacements 243310628Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 64480.086956 # Cycle average of tags in use 243410628Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 5089807 # Total number of references to valid blocks. 243510628Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 1533812 # Sample count of references to valid blocks. 243610628Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 3.318403 # Average number of references to valid blocks. 243710628Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 8003493500 # Cycle when the warmup percentage was hit. 243810628Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 16627.933383 # Average occupied blocks per requestor 243910628Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 13.809416 # Average occupied blocks per requestor 244010628Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 10.076521 # Average occupied blocks per requestor 244110636Snilay@cs.wisc.edusystem.l2c.tags.occ_blocks::cpu0.inst 4159.600580 # Average occupied blocks per requestor 244210636Snilay@cs.wisc.edusystem.l2c.tags.occ_blocks::cpu0.data 3523.314031 # Average occupied blocks per requestor 244310628Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 5733.726218 # Average occupied blocks per requestor 244410628Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 373.789781 # Average occupied blocks per requestor 244510628Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 460.262003 # Average occupied blocks per requestor 244610636Snilay@cs.wisc.edusystem.l2c.tags.occ_blocks::cpu1.inst 3670.846899 # Average occupied blocks per requestor 244710636Snilay@cs.wisc.edusystem.l2c.tags.occ_blocks::cpu1.data 10690.974499 # Average occupied blocks per requestor 244810628Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 19215.753624 # Average occupied blocks per requestor 244910628Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.253722 # Average percentage of cache occupancy 245010628Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.000211 # Average percentage of cache occupancy 245110628Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.000154 # Average percentage of cache occupancy 245210636Snilay@cs.wisc.edusystem.l2c.tags.occ_percent::cpu0.inst 0.063470 # Average percentage of cache occupancy 245310636Snilay@cs.wisc.edusystem.l2c.tags.occ_percent::cpu0.data 0.053762 # Average percentage of cache occupancy 245410628Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.087490 # Average percentage of cache occupancy 245510628Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.005704 # Average percentage of cache occupancy 245610628Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.007023 # Average percentage of cache occupancy 245710636Snilay@cs.wisc.edusystem.l2c.tags.occ_percent::cpu1.inst 0.056013 # Average percentage of cache occupancy 245810636Snilay@cs.wisc.edusystem.l2c.tags.occ_percent::cpu1.data 0.163131 # Average percentage of cache occupancy 245910628Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.293209 # Average percentage of cache occupancy 246010628Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.983888 # Average percentage of cache occupancy 246110628Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1022 14505 # Occupied blocks per task id 246210628Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 200 # Occupied blocks per task id 246310628Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 45654 # Occupied blocks per task id 246410628Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::2 147 # Occupied blocks per task id 246510628Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::3 696 # Occupied blocks per task id 246610628Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::4 13662 # Occupied blocks per task id 246710628Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 200 # Occupied blocks per task id 246810628Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id 246910628Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id 247010628Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 1737 # Occupied blocks per task id 247110628Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 4894 # Occupied blocks per task id 247210628Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 38831 # Occupied blocks per task id 247310628Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1022 0.221329 # Percentage of cache occupancy per task id 247410628Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.003052 # Percentage of cache occupancy per task id 247510628Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.696625 # Percentage of cache occupancy per task id 247610628Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 65568567 # Number of tag accesses 247710628Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 65568567 # Number of data accesses 247810628Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.dtb.walker 6731 # number of ReadReq hits 247910628Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.itb.walker 4742 # number of ReadReq hits 248010636Snilay@cs.wisc.edusystem.l2c.ReadReq_hits::cpu0.inst 690690 # number of ReadReq hits 248110636Snilay@cs.wisc.edusystem.l2c.ReadReq_hits::cpu0.data 361152 # number of ReadReq hits 248210628Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 521850 # number of ReadReq hits 248310628Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.dtb.walker 6817 # number of ReadReq hits 248410628Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.itb.walker 4499 # number of ReadReq hits 248510636Snilay@cs.wisc.edusystem.l2c.ReadReq_hits::cpu1.inst 759258 # number of ReadReq hits 248610636Snilay@cs.wisc.edusystem.l2c.ReadReq_hits::cpu1.data 428313 # number of ReadReq hits 248710628Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 530462 # number of ReadReq hits 248810628Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::total 3314514 # number of ReadReq hits 248910628Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::writebacks 2491671 # number of Writeback hits 249010628Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::total 2491671 # number of Writeback hits 249110636Snilay@cs.wisc.edusystem.l2c.WriteInvalidateReq_hits::cpu0.data 125819 # number of WriteInvalidateReq hits 249210636Snilay@cs.wisc.edusystem.l2c.WriteInvalidateReq_hits::cpu1.data 140505 # number of WriteInvalidateReq hits 249310628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_hits::total 266324 # number of WriteInvalidateReq hits 249410636Snilay@cs.wisc.edusystem.l2c.UpgradeReq_hits::cpu0.data 29765 # number of UpgradeReq hits 249510636Snilay@cs.wisc.edusystem.l2c.UpgradeReq_hits::cpu1.data 32403 # number of UpgradeReq hits 249610628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 62168 # number of UpgradeReq hits 249710636Snilay@cs.wisc.edusystem.l2c.SCUpgradeReq_hits::cpu0.data 5875 # number of SCUpgradeReq hits 249810636Snilay@cs.wisc.edusystem.l2c.SCUpgradeReq_hits::cpu1.data 6386 # number of SCUpgradeReq hits 249910628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 12261 # number of SCUpgradeReq hits 250010636Snilay@cs.wisc.edusystem.l2c.ReadExReq_hits::cpu0.data 56397 # number of ReadExReq hits 250110636Snilay@cs.wisc.edusystem.l2c.ReadExReq_hits::cpu1.data 53337 # number of ReadExReq hits 250210628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 109734 # number of ReadExReq hits 250310628Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 6731 # number of demand (read+write) hits 250410628Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 4742 # number of demand (read+write) hits 250510636Snilay@cs.wisc.edusystem.l2c.demand_hits::cpu0.inst 690690 # number of demand (read+write) hits 250610636Snilay@cs.wisc.edusystem.l2c.demand_hits::cpu0.data 417549 # number of demand (read+write) hits 250710628Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.l2cache.prefetcher 521850 # number of demand (read+write) hits 250810628Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 6817 # number of demand (read+write) hits 250910628Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 4499 # number of demand (read+write) hits 251010636Snilay@cs.wisc.edusystem.l2c.demand_hits::cpu1.inst 759258 # number of demand (read+write) hits 251110636Snilay@cs.wisc.edusystem.l2c.demand_hits::cpu1.data 481650 # number of demand (read+write) hits 251210628Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.l2cache.prefetcher 530462 # number of demand (read+write) hits 251310628Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 3424248 # number of demand (read+write) hits 251410628Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 6731 # number of overall hits 251510628Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 4742 # number of overall hits 251610636Snilay@cs.wisc.edusystem.l2c.overall_hits::cpu0.inst 690690 # number of overall hits 251710636Snilay@cs.wisc.edusystem.l2c.overall_hits::cpu0.data 417549 # number of overall hits 251810628Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.l2cache.prefetcher 521850 # number of overall hits 251910628Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 6817 # number of overall hits 252010628Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 4499 # number of overall hits 252110636Snilay@cs.wisc.edusystem.l2c.overall_hits::cpu1.inst 759258 # number of overall hits 252210636Snilay@cs.wisc.edusystem.l2c.overall_hits::cpu1.data 481650 # number of overall hits 252310628Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.l2cache.prefetcher 530462 # number of overall hits 252410628Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 3424248 # number of overall hits 252510628Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.dtb.walker 1664 # number of ReadReq misses 252610628Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.itb.walker 1301 # number of ReadReq misses 252710636Snilay@cs.wisc.edusystem.l2c.ReadReq_misses::cpu0.inst 74535 # number of ReadReq misses 252810636Snilay@cs.wisc.edusystem.l2c.ReadReq_misses::cpu0.data 94558 # number of ReadReq misses 252910628Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 274703 # number of ReadReq misses 253010628Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.dtb.walker 2478 # number of ReadReq misses 253110628Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.itb.walker 2309 # number of ReadReq misses 253210636Snilay@cs.wisc.edusystem.l2c.ReadReq_misses::cpu1.inst 56185 # number of ReadReq misses 253310636Snilay@cs.wisc.edusystem.l2c.ReadReq_misses::cpu1.data 106038 # number of ReadReq misses 253410628Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 256515 # number of ReadReq misses 253510628Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::total 870286 # number of ReadReq misses 253610636Snilay@cs.wisc.edusystem.l2c.WriteInvalidateReq_misses::cpu0.data 435530 # number of WriteInvalidateReq misses 253710636Snilay@cs.wisc.edusystem.l2c.WriteInvalidateReq_misses::cpu1.data 123517 # number of WriteInvalidateReq misses 253810628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_misses::total 559047 # number of WriteInvalidateReq misses 253910636Snilay@cs.wisc.edusystem.l2c.UpgradeReq_misses::cpu0.data 44959 # number of UpgradeReq misses 254010636Snilay@cs.wisc.edusystem.l2c.UpgradeReq_misses::cpu1.data 45474 # number of UpgradeReq misses 254110628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 90433 # number of UpgradeReq misses 254210636Snilay@cs.wisc.edusystem.l2c.SCUpgradeReq_misses::cpu0.data 8261 # number of SCUpgradeReq misses 254310636Snilay@cs.wisc.edusystem.l2c.SCUpgradeReq_misses::cpu1.data 9038 # number of SCUpgradeReq misses 254410628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 17299 # number of SCUpgradeReq misses 254510636Snilay@cs.wisc.edusystem.l2c.ReadExReq_misses::cpu0.data 76639 # number of ReadExReq misses 254610636Snilay@cs.wisc.edusystem.l2c.ReadExReq_misses::cpu1.data 55158 # number of ReadExReq misses 254710628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 131797 # number of ReadExReq misses 254810628Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 1664 # number of demand (read+write) misses 254910628Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 1301 # number of demand (read+write) misses 255010636Snilay@cs.wisc.edusystem.l2c.demand_misses::cpu0.inst 74535 # number of demand (read+write) misses 255110636Snilay@cs.wisc.edusystem.l2c.demand_misses::cpu0.data 171197 # number of demand (read+write) misses 255210628Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.l2cache.prefetcher 274703 # number of demand (read+write) misses 255310628Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 2478 # number of demand (read+write) misses 255410628Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.itb.walker 2309 # number of demand (read+write) misses 255510636Snilay@cs.wisc.edusystem.l2c.demand_misses::cpu1.inst 56185 # number of demand (read+write) misses 255610636Snilay@cs.wisc.edusystem.l2c.demand_misses::cpu1.data 161196 # number of demand (read+write) misses 255710628Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.l2cache.prefetcher 256515 # number of demand (read+write) misses 255810628Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 1002083 # number of demand (read+write) misses 255910628Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 1664 # number of overall misses 256010628Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 1301 # number of overall misses 256110636Snilay@cs.wisc.edusystem.l2c.overall_misses::cpu0.inst 74535 # number of overall misses 256210636Snilay@cs.wisc.edusystem.l2c.overall_misses::cpu0.data 171197 # number of overall misses 256310628Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.l2cache.prefetcher 274703 # number of overall misses 256410628Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 2478 # number of overall misses 256510628Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.itb.walker 2309 # number of overall misses 256610636Snilay@cs.wisc.edusystem.l2c.overall_misses::cpu1.inst 56185 # number of overall misses 256710636Snilay@cs.wisc.edusystem.l2c.overall_misses::cpu1.data 161196 # number of overall misses 256810628Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.l2cache.prefetcher 256515 # number of overall misses 256910628Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 1002083 # number of overall misses 257010628Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu0.dtb.walker 138961746 # number of ReadReq miss cycles 257110628Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu0.itb.walker 111055248 # number of ReadReq miss cycles 257210636Snilay@cs.wisc.edusystem.l2c.ReadReq_miss_latency::cpu0.inst 5745942443 # number of ReadReq miss cycles 257310636Snilay@cs.wisc.edusystem.l2c.ReadReq_miss_latency::cpu0.data 7810089637 # number of ReadReq miss cycles 257410628Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 37505012849 # number of ReadReq miss cycles 257510628Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu1.dtb.walker 202393999 # number of ReadReq miss cycles 257610628Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu1.itb.walker 185177500 # number of ReadReq miss cycles 257710636Snilay@cs.wisc.edusystem.l2c.ReadReq_miss_latency::cpu1.inst 4301130982 # number of ReadReq miss cycles 257810636Snilay@cs.wisc.edusystem.l2c.ReadReq_miss_latency::cpu1.data 8460963468 # number of ReadReq miss cycles 257910628Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 31520804985 # number of ReadReq miss cycles 258010628Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::total 95981532857 # number of ReadReq miss cycles 258110636Snilay@cs.wisc.edusystem.l2c.WriteInvalidateReq_miss_latency::cpu0.data 36612963 # number of WriteInvalidateReq miss cycles 258210636Snilay@cs.wisc.edusystem.l2c.WriteInvalidateReq_miss_latency::cpu1.data 35758482 # number of WriteInvalidateReq miss cycles 258310628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_miss_latency::total 72371445 # number of WriteInvalidateReq miss cycles 258410636Snilay@cs.wisc.edusystem.l2c.UpgradeReq_miss_latency::cpu0.data 213542030 # number of UpgradeReq miss cycles 258510636Snilay@cs.wisc.edusystem.l2c.UpgradeReq_miss_latency::cpu1.data 216684315 # number of UpgradeReq miss cycles 258610628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::total 430226345 # number of UpgradeReq miss cycles 258710636Snilay@cs.wisc.edusystem.l2c.SCUpgradeReq_miss_latency::cpu0.data 36699987 # number of SCUpgradeReq miss cycles 258810636Snilay@cs.wisc.edusystem.l2c.SCUpgradeReq_miss_latency::cpu1.data 41305269 # number of SCUpgradeReq miss cycles 258910628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::total 78005256 # number of SCUpgradeReq miss cycles 259010636Snilay@cs.wisc.edusystem.l2c.ReadExReq_miss_latency::cpu0.data 6278532917 # number of ReadExReq miss cycles 259110636Snilay@cs.wisc.edusystem.l2c.ReadExReq_miss_latency::cpu1.data 4207751582 # number of ReadExReq miss cycles 259210628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::total 10486284499 # number of ReadExReq miss cycles 259310628Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.dtb.walker 138961746 # number of demand (read+write) miss cycles 259410628Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.itb.walker 111055248 # number of demand (read+write) miss cycles 259510636Snilay@cs.wisc.edusystem.l2c.demand_miss_latency::cpu0.inst 5745942443 # number of demand (read+write) miss cycles 259610636Snilay@cs.wisc.edusystem.l2c.demand_miss_latency::cpu0.data 14088622554 # number of demand (read+write) miss cycles 259710628Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 37505012849 # number of demand (read+write) miss cycles 259810628Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.dtb.walker 202393999 # number of demand (read+write) miss cycles 259910628Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.itb.walker 185177500 # number of demand (read+write) miss cycles 260010636Snilay@cs.wisc.edusystem.l2c.demand_miss_latency::cpu1.inst 4301130982 # number of demand (read+write) miss cycles 260110636Snilay@cs.wisc.edusystem.l2c.demand_miss_latency::cpu1.data 12668715050 # number of demand (read+write) miss cycles 260210628Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 31520804985 # number of demand (read+write) miss cycles 260310628Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::total 106467817356 # number of demand (read+write) miss cycles 260410628Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.dtb.walker 138961746 # number of overall miss cycles 260510628Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.itb.walker 111055248 # number of overall miss cycles 260610636Snilay@cs.wisc.edusystem.l2c.overall_miss_latency::cpu0.inst 5745942443 # number of overall miss cycles 260710636Snilay@cs.wisc.edusystem.l2c.overall_miss_latency::cpu0.data 14088622554 # number of overall miss cycles 260810628Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 37505012849 # number of overall miss cycles 260910628Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.dtb.walker 202393999 # number of overall miss cycles 261010628Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.itb.walker 185177500 # number of overall miss cycles 261110636Snilay@cs.wisc.edusystem.l2c.overall_miss_latency::cpu1.inst 4301130982 # number of overall miss cycles 261210636Snilay@cs.wisc.edusystem.l2c.overall_miss_latency::cpu1.data 12668715050 # number of overall miss cycles 261310628Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 31520804985 # number of overall miss cycles 261410628Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::total 106467817356 # number of overall miss cycles 261510628Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.dtb.walker 8395 # number of ReadReq accesses(hits+misses) 261610628Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.itb.walker 6043 # number of ReadReq accesses(hits+misses) 261710636Snilay@cs.wisc.edusystem.l2c.ReadReq_accesses::cpu0.inst 765225 # number of ReadReq accesses(hits+misses) 261810636Snilay@cs.wisc.edusystem.l2c.ReadReq_accesses::cpu0.data 455710 # number of ReadReq accesses(hits+misses) 261910628Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 796553 # number of ReadReq accesses(hits+misses) 262010628Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.dtb.walker 9295 # number of ReadReq accesses(hits+misses) 262110628Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.itb.walker 6808 # number of ReadReq accesses(hits+misses) 262210636Snilay@cs.wisc.edusystem.l2c.ReadReq_accesses::cpu1.inst 815443 # number of ReadReq accesses(hits+misses) 262310636Snilay@cs.wisc.edusystem.l2c.ReadReq_accesses::cpu1.data 534351 # number of ReadReq accesses(hits+misses) 262410628Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 786977 # number of ReadReq accesses(hits+misses) 262510628Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::total 4184800 # number of ReadReq accesses(hits+misses) 262610628Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::writebacks 2491671 # number of Writeback accesses(hits+misses) 262710628Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::total 2491671 # number of Writeback accesses(hits+misses) 262810636Snilay@cs.wisc.edusystem.l2c.WriteInvalidateReq_accesses::cpu0.data 561349 # number of WriteInvalidateReq accesses(hits+misses) 262910636Snilay@cs.wisc.edusystem.l2c.WriteInvalidateReq_accesses::cpu1.data 264022 # number of WriteInvalidateReq accesses(hits+misses) 263010628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_accesses::total 825371 # number of WriteInvalidateReq accesses(hits+misses) 263110636Snilay@cs.wisc.edusystem.l2c.UpgradeReq_accesses::cpu0.data 74724 # number of UpgradeReq accesses(hits+misses) 263210636Snilay@cs.wisc.edusystem.l2c.UpgradeReq_accesses::cpu1.data 77877 # number of UpgradeReq accesses(hits+misses) 263310628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 152601 # number of UpgradeReq accesses(hits+misses) 263410636Snilay@cs.wisc.edusystem.l2c.SCUpgradeReq_accesses::cpu0.data 14136 # number of SCUpgradeReq accesses(hits+misses) 263510636Snilay@cs.wisc.edusystem.l2c.SCUpgradeReq_accesses::cpu1.data 15424 # number of SCUpgradeReq accesses(hits+misses) 263610628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 29560 # number of SCUpgradeReq accesses(hits+misses) 263710636Snilay@cs.wisc.edusystem.l2c.ReadExReq_accesses::cpu0.data 133036 # number of ReadExReq accesses(hits+misses) 263810636Snilay@cs.wisc.edusystem.l2c.ReadExReq_accesses::cpu1.data 108495 # number of ReadExReq accesses(hits+misses) 263910628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 241531 # number of ReadExReq accesses(hits+misses) 264010628Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 8395 # number of demand (read+write) accesses 264110628Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 6043 # number of demand (read+write) accesses 264210636Snilay@cs.wisc.edusystem.l2c.demand_accesses::cpu0.inst 765225 # number of demand (read+write) accesses 264310636Snilay@cs.wisc.edusystem.l2c.demand_accesses::cpu0.data 588746 # number of demand (read+write) accesses 264410628Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.l2cache.prefetcher 796553 # number of demand (read+write) accesses 264510628Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 9295 # number of demand (read+write) accesses 264610628Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 6808 # number of demand (read+write) accesses 264710636Snilay@cs.wisc.edusystem.l2c.demand_accesses::cpu1.inst 815443 # number of demand (read+write) accesses 264810636Snilay@cs.wisc.edusystem.l2c.demand_accesses::cpu1.data 642846 # number of demand (read+write) accesses 264910628Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.l2cache.prefetcher 786977 # number of demand (read+write) accesses 265010628Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 4426331 # number of demand (read+write) accesses 265110628Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 8395 # number of overall (read+write) accesses 265210628Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 6043 # number of overall (read+write) accesses 265310636Snilay@cs.wisc.edusystem.l2c.overall_accesses::cpu0.inst 765225 # number of overall (read+write) accesses 265410636Snilay@cs.wisc.edusystem.l2c.overall_accesses::cpu0.data 588746 # number of overall (read+write) accesses 265510628Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.l2cache.prefetcher 796553 # number of overall (read+write) accesses 265610628Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 9295 # number of overall (read+write) accesses 265710628Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 6808 # number of overall (read+write) accesses 265810636Snilay@cs.wisc.edusystem.l2c.overall_accesses::cpu1.inst 815443 # number of overall (read+write) accesses 265910636Snilay@cs.wisc.edusystem.l2c.overall_accesses::cpu1.data 642846 # number of overall (read+write) accesses 266010628Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.l2cache.prefetcher 786977 # number of overall (read+write) accesses 266110628Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 4426331 # number of overall (read+write) accesses 266210628Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.198213 # miss rate for ReadReq accesses 266310628Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.215290 # miss rate for ReadReq accesses 266410636Snilay@cs.wisc.edusystem.l2c.ReadReq_miss_rate::cpu0.inst 0.097403 # miss rate for ReadReq accesses 266510636Snilay@cs.wisc.edusystem.l2c.ReadReq_miss_rate::cpu0.data 0.207496 # miss rate for ReadReq accesses 266610628Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.344865 # miss rate for ReadReq accesses 266710628Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.266595 # miss rate for ReadReq accesses 266810628Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.339160 # miss rate for ReadReq accesses 266910636Snilay@cs.wisc.edusystem.l2c.ReadReq_miss_rate::cpu1.inst 0.068901 # miss rate for ReadReq accesses 267010636Snilay@cs.wisc.edusystem.l2c.ReadReq_miss_rate::cpu1.data 0.198443 # miss rate for ReadReq accesses 267110628Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.325950 # miss rate for ReadReq accesses 267210628Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::total 0.207964 # miss rate for ReadReq accesses 267310636Snilay@cs.wisc.edusystem.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.775863 # miss rate for WriteInvalidateReq accesses 267410636Snilay@cs.wisc.edusystem.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.467828 # miss rate for WriteInvalidateReq accesses 267510628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_miss_rate::total 0.677328 # miss rate for WriteInvalidateReq accesses 267610636Snilay@cs.wisc.edusystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.601667 # miss rate for UpgradeReq accesses 267710636Snilay@cs.wisc.edusystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.583921 # miss rate for UpgradeReq accesses 267810628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.592611 # miss rate for UpgradeReq accesses 267910636Snilay@cs.wisc.edusystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.584394 # miss rate for SCUpgradeReq accesses 268010636Snilay@cs.wisc.edusystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.585970 # miss rate for SCUpgradeReq accesses 268110628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.585217 # miss rate for SCUpgradeReq accesses 268210636Snilay@cs.wisc.edusystem.l2c.ReadExReq_miss_rate::cpu0.data 0.576077 # miss rate for ReadExReq accesses 268310636Snilay@cs.wisc.edusystem.l2c.ReadExReq_miss_rate::cpu1.data 0.508392 # miss rate for ReadExReq accesses 268410628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.545673 # miss rate for ReadExReq accesses 268510628Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.198213 # miss rate for demand accesses 268610628Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.215290 # miss rate for demand accesses 268710636Snilay@cs.wisc.edusystem.l2c.demand_miss_rate::cpu0.inst 0.097403 # miss rate for demand accesses 268810636Snilay@cs.wisc.edusystem.l2c.demand_miss_rate::cpu0.data 0.290782 # miss rate for demand accesses 268910628Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.344865 # miss rate for demand accesses 269010628Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.266595 # miss rate for demand accesses 269110628Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.339160 # miss rate for demand accesses 269210636Snilay@cs.wisc.edusystem.l2c.demand_miss_rate::cpu1.inst 0.068901 # miss rate for demand accesses 269310636Snilay@cs.wisc.edusystem.l2c.demand_miss_rate::cpu1.data 0.250754 # miss rate for demand accesses 269410628Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.325950 # miss rate for demand accesses 269510628Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.226391 # miss rate for demand accesses 269610628Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.198213 # miss rate for overall accesses 269710628Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.215290 # miss rate for overall accesses 269810636Snilay@cs.wisc.edusystem.l2c.overall_miss_rate::cpu0.inst 0.097403 # miss rate for overall accesses 269910636Snilay@cs.wisc.edusystem.l2c.overall_miss_rate::cpu0.data 0.290782 # miss rate for overall accesses 270010628Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.344865 # miss rate for overall accesses 270110628Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.266595 # miss rate for overall accesses 270210628Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.339160 # miss rate for overall accesses 270310636Snilay@cs.wisc.edusystem.l2c.overall_miss_rate::cpu1.inst 0.068901 # miss rate for overall accesses 270410636Snilay@cs.wisc.edusystem.l2c.overall_miss_rate::cpu1.data 0.250754 # miss rate for overall accesses 270510628Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.325950 # miss rate for overall accesses 270610628Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.226391 # miss rate for overall accesses 270710628Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 83510.664663 # average ReadReq miss latency 270810628Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 85361.451191 # average ReadReq miss latency 270910636Snilay@cs.wisc.edusystem.l2c.ReadReq_avg_miss_latency::cpu0.inst 77090.527175 # average ReadReq miss latency 271010636Snilay@cs.wisc.edusystem.l2c.ReadReq_avg_miss_latency::cpu0.data 82595.757493 # average ReadReq miss latency 271110628Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 136529.316567 # average ReadReq miss latency 271210628Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 81676.351493 # average ReadReq miss latency 271310628Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 80198.137722 # average ReadReq miss latency 271410636Snilay@cs.wisc.edusystem.l2c.ReadReq_avg_miss_latency::cpu1.inst 76553.012049 # average ReadReq miss latency 271510636Snilay@cs.wisc.edusystem.l2c.ReadReq_avg_miss_latency::cpu1.data 79791.805466 # average ReadReq miss latency 271610628Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 122880.942576 # average ReadReq miss latency 271710628Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::total 110287.345605 # average ReadReq miss latency 271810636Snilay@cs.wisc.edusystem.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 84.065307 # average WriteInvalidateReq miss latency 271910636Snilay@cs.wisc.edusystem.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 289.502514 # average WriteInvalidateReq miss latency 272010628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_avg_miss_latency::total 129.455028 # average WriteInvalidateReq miss latency 272110636Snilay@cs.wisc.edusystem.l2c.UpgradeReq_avg_miss_latency::cpu0.data 4749.705954 # average UpgradeReq miss latency 272210636Snilay@cs.wisc.edusystem.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4765.015503 # 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number of demand (read+write) MSHR miss cycles 285310636Snilay@cs.wisc.edusystem.l2c.demand_mshr_miss_latency::cpu1.data 10643687564 # number of demand (read+write) MSHR miss cycles 285410628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 28363294485 # number of demand (read+write) MSHR miss cycles 285510628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::total 93996922312 # number of demand (read+write) MSHR miss cycles 285610628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 118167746 # number of overall MSHR miss cycles 285710628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.itb.walker 94777748 # number of overall MSHR miss cycles 285810636Snilay@cs.wisc.edusystem.l2c.overall_mshr_miss_latency::cpu0.inst 4793355973 # number of overall MSHR miss cycles 285910636Snilay@cs.wisc.edusystem.l2c.overall_mshr_miss_latency::cpu0.data 11937119710 # number of overall MSHR miss cycles 286010628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 34136893349 # number of overall MSHR miss cycles 286110628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 171330499 # number of overall MSHR miss cycles 286210628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.itb.walker 156241500 # number of overall MSHR miss cycles 286310636Snilay@cs.wisc.edusystem.l2c.overall_mshr_miss_latency::cpu1.inst 3582053738 # number of overall MSHR miss cycles 286410636Snilay@cs.wisc.edusystem.l2c.overall_mshr_miss_latency::cpu1.data 10643687564 # number of overall MSHR miss cycles 286510628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 28363294485 # number of overall MSHR miss cycles 286610628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::total 93996922312 # number of overall MSHR miss cycles 286710636Snilay@cs.wisc.edusystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2759400500 # number of ReadReq MSHR uncacheable cycles 286810636Snilay@cs.wisc.edusystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4958794248 # number of ReadReq MSHR uncacheable cycles 286910636Snilay@cs.wisc.edusystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5045750 # number of ReadReq MSHR uncacheable cycles 287010636Snilay@cs.wisc.edusystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 413259748 # number of ReadReq MSHR uncacheable cycles 287110628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::total 8136500246 # number of ReadReq MSHR uncacheable cycles 287210636Snilay@cs.wisc.edusystem.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4773990997 # number of WriteReq MSHR uncacheable cycles 287310636Snilay@cs.wisc.edusystem.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 484709502 # number of WriteReq MSHR uncacheable cycles 287410628Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable_latency::total 5258700499 # number of WriteReq MSHR uncacheable cycles 287510636Snilay@cs.wisc.edusystem.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2759400500 # number of overall MSHR uncacheable cycles 287610636Snilay@cs.wisc.edusystem.l2c.overall_mshr_uncacheable_latency::cpu0.data 9732785245 # number of overall MSHR uncacheable cycles 287710636Snilay@cs.wisc.edusystem.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5045750 # number of overall MSHR uncacheable cycles 287810636Snilay@cs.wisc.edusystem.l2c.overall_mshr_uncacheable_latency::cpu1.data 897969250 # number of overall MSHR uncacheable cycles 287910628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::total 13395200745 # number of overall MSHR uncacheable cycles 288010628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.198213 # mshr miss rate for ReadReq accesses 288110628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.215290 # mshr miss rate for ReadReq accesses 288210636Snilay@cs.wisc.edusystem.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.097157 # mshr miss rate for ReadReq accesses 288310636Snilay@cs.wisc.edusystem.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.207448 # mshr miss rate for ReadReq accesses 288410628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.344865 # mshr miss rate for ReadReq accesses 288510628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.266595 # mshr miss rate for ReadReq accesses 288610628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.339160 # mshr miss rate for ReadReq accesses 288710636Snilay@cs.wisc.edusystem.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.068703 # mshr miss rate for ReadReq accesses 288810636Snilay@cs.wisc.edusystem.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.198415 # mshr miss rate for ReadReq accesses 288910628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.325950 # mshr miss rate for ReadReq accesses 289010628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::total 0.207871 # mshr miss rate for ReadReq accesses 289110636Snilay@cs.wisc.edusystem.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.775863 # mshr miss rate for WriteInvalidateReq accesses 289210636Snilay@cs.wisc.edusystem.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.467828 # mshr miss rate for WriteInvalidateReq accesses 289310628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.677328 # mshr miss rate for WriteInvalidateReq accesses 289410636Snilay@cs.wisc.edusystem.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.601667 # mshr miss rate for UpgradeReq accesses 289510636Snilay@cs.wisc.edusystem.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.583921 # mshr miss rate for UpgradeReq accesses 289610628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::total 0.592611 # mshr miss rate for UpgradeReq accesses 289710636Snilay@cs.wisc.edusystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.584394 # mshr miss rate for SCUpgradeReq accesses 289810636Snilay@cs.wisc.edusystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.585970 # mshr miss rate for SCUpgradeReq accesses 289910628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::total 0.585217 # mshr miss rate for SCUpgradeReq accesses 290010636Snilay@cs.wisc.edusystem.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.576077 # mshr miss rate for ReadExReq accesses 290110636Snilay@cs.wisc.edusystem.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.508392 # mshr miss rate for ReadExReq accesses 290210628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::total 0.545673 # mshr miss rate for ReadExReq accesses 290310628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.198213 # mshr miss rate for demand accesses 290410628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.215290 # mshr miss rate for demand accesses 290510636Snilay@cs.wisc.edusystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.097157 # mshr miss rate for demand accesses 290610636Snilay@cs.wisc.edusystem.l2c.demand_mshr_miss_rate::cpu0.data 0.290745 # mshr miss rate for demand accesses 290710628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.344865 # mshr miss rate for demand accesses 290810628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.266595 # mshr miss rate for demand accesses 290910628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.339160 # mshr miss rate for demand accesses 291010636Snilay@cs.wisc.edusystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.068703 # mshr miss rate for demand accesses 291110636Snilay@cs.wisc.edusystem.l2c.demand_mshr_miss_rate::cpu1.data 0.250730 # mshr miss rate for demand accesses 291210628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.325950 # mshr miss rate for demand accesses 291310628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::total 0.226304 # mshr miss rate for demand accesses 291410628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.198213 # mshr miss rate for overall accesses 291510628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.215290 # mshr miss rate for overall accesses 291610636Snilay@cs.wisc.edusystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.097157 # mshr miss rate for overall accesses 291710636Snilay@cs.wisc.edusystem.l2c.overall_mshr_miss_rate::cpu0.data 0.290745 # mshr miss rate for overall accesses 291810628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.344865 # mshr miss rate for overall accesses 291910628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.266595 # mshr miss rate for overall accesses 292010628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.339160 # mshr miss rate for overall accesses 292110636Snilay@cs.wisc.edusystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.068703 # mshr miss rate for overall accesses 292210636Snilay@cs.wisc.edusystem.l2c.overall_mshr_miss_rate::cpu1.data 0.250730 # mshr miss rate for overall accesses 292310628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.325950 # mshr miss rate for overall accesses 292410628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::total 0.226304 # mshr miss rate for overall accesses 292510628Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 71014.270433 # average ReadReq mshr miss latency 292610628Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 72849.921599 # average ReadReq mshr miss latency 292710636Snilay@cs.wisc.edusystem.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 64472.755767 # average ReadReq mshr miss latency 292810636Snilay@cs.wisc.edusystem.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 70044.958587 # average ReadReq mshr miss latency 292910628Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 124268.367470 # average ReadReq mshr miss latency 293010628Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 69140.637207 # average ReadReq mshr miss latency 293110628Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 67666.305760 # average ReadReq mshr miss latency 293210636Snilay@cs.wisc.edusystem.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 63938.984667 # average ReadReq mshr miss latency 293310636Snilay@cs.wisc.edusystem.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67263.713741 # average ReadReq mshr miss latency 293410628Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960 # average ReadReq mshr miss latency 293510628Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::total 97907.212176 # average ReadReq mshr miss latency 293610636Snilay@cs.wisc.edusystem.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 22469.301798 # average WriteInvalidateReq mshr miss latency 293710636Snilay@cs.wisc.edusystem.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 20366.746845 # average WriteInvalidateReq mshr miss latency 293810628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 22004.758959 # average WriteInvalidateReq mshr miss latency 293910636Snilay@cs.wisc.edusystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10131.989012 # average UpgradeReq mshr miss latency 294010636Snilay@cs.wisc.edusystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10134.836676 # average UpgradeReq mshr miss latency 294110628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 10133.420953 # average UpgradeReq mshr miss latency 294210636Snilay@cs.wisc.edusystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10275.715047 # average SCUpgradeReq mshr miss latency 294310636Snilay@cs.wisc.edusystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10220.729033 # average SCUpgradeReq mshr miss latency 294410628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10246.987167 # average SCUpgradeReq mshr miss latency 294510636Snilay@cs.wisc.edusystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 69355.674069 # average ReadExReq mshr miss latency 294610636Snilay@cs.wisc.edusystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63675.021611 # average ReadExReq mshr miss latency 294710628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 66978.279832 # average ReadExReq mshr miss latency 294810628Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71014.270433 # average overall mshr miss latency 294910628Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 72849.921599 # average overall mshr miss latency 295010636Snilay@cs.wisc.edusystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64472.755767 # average overall mshr miss latency 295110636Snilay@cs.wisc.edusystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 69736.349993 # average overall mshr miss latency 295210628Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 124268.367470 # average overall mshr miss latency 295310628Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 69140.637207 # average overall mshr miss latency 295410628Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 67666.305760 # average overall mshr miss latency 295510636Snilay@cs.wisc.edusystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63938.984667 # average overall mshr miss latency 295610636Snilay@cs.wisc.edusystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 66035.621841 # average overall mshr miss latency 295710628Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960 # average overall mshr miss latency 295810628Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 93837.773448 # average overall mshr miss latency 295910628Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71014.270433 # average overall mshr miss latency 296010628Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 72849.921599 # average overall mshr miss latency 296110636Snilay@cs.wisc.edusystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64472.755767 # average overall mshr miss latency 296210636Snilay@cs.wisc.edusystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 69736.349993 # average overall mshr miss latency 296310628Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 124268.367470 # average overall mshr miss latency 296410628Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 69140.637207 # average overall mshr miss latency 296510628Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 67666.305760 # average overall mshr miss latency 296610636Snilay@cs.wisc.edusystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63938.984667 # average overall mshr miss latency 296710636Snilay@cs.wisc.edusystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 66035.621841 # average overall mshr miss latency 296810628Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960 # average overall mshr miss latency 296910628Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 93837.773448 # average overall mshr miss latency 297010515SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 297110636Snilay@cs.wisc.edusystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 297210515SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 297310636Snilay@cs.wisc.edusystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 297410515SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 297510636Snilay@cs.wisc.edusystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 297610636Snilay@cs.wisc.edusystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 297710515SAli.Saidi@ARM.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 297810515SAli.Saidi@ARM.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 297910636Snilay@cs.wisc.edusystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 298010515SAli.Saidi@ARM.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 298110636Snilay@cs.wisc.edusystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 298210515SAli.Saidi@ARM.comsystem.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 298310515SAli.Saidi@ARM.comsystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 298410628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 969598 # Transaction distribution 298510628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 969598 # Transaction distribution 298610628Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 38347 # Transaction distribution 298710628Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 38347 # Transaction distribution 298810628Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 1222910 # Transaction distribution 298910628Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteInvalidateReq 662686 # Transaction distribution 299010628Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteInvalidateResp 662686 # Transaction distribution 299110628Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 426453 # Transaction distribution 299210628Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 285961 # Transaction distribution 299310628Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 115017 # Transaction distribution 299410628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 144468 # Transaction distribution 299510628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 127604 # Transaction distribution 299610628Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123068 # Packet count per connected master and slave (bytes) 299710585Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) 299810628Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25110 # Packet count per connected master and slave (bytes) 299910628Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5176712 # Packet count per connected master and slave (bytes) 300010628Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 5324942 # Packet count per connected master and slave (bytes) 300110628Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335765 # Packet count per connected master and slave (bytes) 300210628Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 335765 # Packet count per connected master and slave (bytes) 300310628Sandreas.hansson@arm.comsystem.membus.pkt_count::total 5660707 # Packet count per connected master and slave (bytes) 300410628Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156198 # Cumulative packet size per connected master and slave (bytes) 300510585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) 300610628Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50220 # Cumulative packet size per connected master and slave (bytes) 300710628Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 174186440 # Cumulative packet size per connected master and slave (bytes) 300810628Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 174394182 # Cumulative packet size per connected master and slave (bytes) 300910628Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14086976 # Cumulative packet size per connected master and slave (bytes) 301010628Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 14086976 # Cumulative packet size per connected master and slave (bytes) 301110628Sandreas.hansson@arm.comsystem.membus.pkt_size::total 188481158 # Cumulative packet size per connected master and slave (bytes) 301210628Sandreas.hansson@arm.comsystem.membus.snoops 617229 # Total snoops (count) 301310628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 3621307 # Request fanout histogram 301410585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 301510585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 301610585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 301710585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 301810628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 3621307 100.00% 100.00% # Request fanout histogram 301910585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 302010585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 302110585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 302210585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 302310628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 3621307 # Request fanout histogram 302410628Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 109998990 # Layer occupancy (ticks) 302510585Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 302610585Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 34484 # Layer occupancy (ticks) 302710585Sandreas.hansson@arm.comsystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 302810628Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 20906994 # Layer occupancy (ticks) 302910585Sandreas.hansson@arm.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 303010628Sandreas.hansson@arm.comsystem.membus.reqLayer5.occupancy 18632739306 # Layer occupancy (ticks) 303110585Sandreas.hansson@arm.comsystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 303210628Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 10660858032 # Layer occupancy (ticks) 303310585Sandreas.hansson@arm.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 303410628Sandreas.hansson@arm.comsystem.membus.respLayer3.occupancy 187340770 # Layer occupancy (ticks) 303510585Sandreas.hansson@arm.comsystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 303610515SAli.Saidi@ARM.comsystem.realview.ethernet.txBytes 966 # Bytes Transmitted 303710515SAli.Saidi@ARM.comsystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 303810515SAli.Saidi@ARM.comsystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 303910515SAli.Saidi@ARM.comsystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 304010515SAli.Saidi@ARM.comsystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 304110515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 304210515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 304310515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 304410515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 304510515SAli.Saidi@ARM.comsystem.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 304610515SAli.Saidi@ARM.comsystem.realview.ethernet.totPackets 3 # Total Packets 304710515SAli.Saidi@ARM.comsystem.realview.ethernet.totBytes 966 # Total Bytes 304810515SAli.Saidi@ARM.comsystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 304910515SAli.Saidi@ARM.comsystem.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 305010515SAli.Saidi@ARM.comsystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 305110515SAli.Saidi@ARM.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 305210515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 305310515SAli.Saidi@ARM.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 305410515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 305510515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 305610515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 305710515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 305810515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 305910515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 306010515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 306110515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 306210515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 306310515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 306410515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 306510515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 306610515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 306710515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 306810515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 306910515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 307010515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 307110515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 307210515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 307310515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 307410515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 307510515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 307610515SAli.Saidi@ARM.comsystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 307710515SAli.Saidi@ARM.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 307810628Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 5129422 # Transaction distribution 307910628Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 5122206 # Transaction distribution 308010628Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 38347 # Transaction distribution 308110628Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 38347 # Transaction distribution 308210628Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::Writeback 2491671 # Transaction distribution 308310628Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteInvalidateReq 932101 # Transaction distribution 308410628Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteInvalidateResp 825371 # Transaction distribution 308510628Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 481339 # Transaction distribution 308610628Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 298222 # Transaction distribution 308710628Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 779561 # Transaction distribution 308810628Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeFailReq 103 # Transaction distribution 308910628Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution 309010628Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 298688 # Transaction distribution 309110628Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 298688 # Transaction distribution 309210628Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8006212 # Packet count per connected master and slave (bytes) 309310628Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7112719 # Packet count per connected master and slave (bytes) 309410628Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 15118931 # Packet count per connected master and slave (bytes) 309510628Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 267664595 # Cumulative packet size per connected master and slave (bytes) 309610628Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 231600691 # Cumulative packet size per connected master and slave (bytes) 309710628Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 499265286 # Cumulative packet size per connected master and slave (bytes) 309810628Sandreas.hansson@arm.comsystem.toL2Bus.snoops 1616950 # Total snoops (count) 309910628Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 9541409 # Request fanout histogram 310010628Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 1.012122 # Request fanout histogram 310110628Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.109429 # Request fanout histogram 310210515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 310310515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 310410628Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 9425751 98.79% 98.79% # Request fanout histogram 310510628Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 115658 1.21% 100.00% # Request fanout histogram 310610515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 310710515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 310810515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 310910628Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 9541409 # Request fanout histogram 311010628Sandreas.hansson@arm.comsystem.toL2Bus.reqLayer0.occupancy 18624671874 # Layer occupancy (ticks) 311110515SAli.Saidi@ARM.comsystem.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 311210628Sandreas.hansson@arm.comsystem.toL2Bus.snoopLayer0.occupancy 7692000 # Layer occupancy (ticks) 311310515SAli.Saidi@ARM.comsystem.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 311410628Sandreas.hansson@arm.comsystem.toL2Bus.respLayer0.occupancy 12569931680 # Layer occupancy (ticks) 311510515SAli.Saidi@ARM.comsystem.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 311610628Sandreas.hansson@arm.comsystem.toL2Bus.respLayer1.occupancy 12640622488 # Layer occupancy (ticks) 311710515SAli.Saidi@ARM.comsystem.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 311810515SAli.Saidi@ARM.com 311910515SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 3120