stats.txt revision 10585
110515SAli.Saidi@ARM.com 210515SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 310585Sandreas.hansson@arm.comsim_seconds 47.349389 # Number of seconds simulated 410585Sandreas.hansson@arm.comsim_ticks 47349388766500 # Number of ticks simulated 510585Sandreas.hansson@arm.comfinal_tick 47349388766500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 710585Sandreas.hansson@arm.comhost_inst_rate 148460 # Simulator instruction rate (inst/s) 810585Sandreas.hansson@arm.comhost_op_rate 174619 # Simulator op (including micro ops) rate (op/s) 910585Sandreas.hansson@arm.comhost_tick_rate 7799944718 # Simulator tick rate (ticks/s) 1010585Sandreas.hansson@arm.comhost_mem_usage 883812 # Number of bytes of host memory used 1110585Sandreas.hansson@arm.comhost_seconds 6070.48 # Real time elapsed on the host 1210585Sandreas.hansson@arm.comsim_insts 901223526 # Number of instructions simulated 1310585Sandreas.hansson@arm.comsim_ops 1060022042 # Number of ops (including micro ops) simulated 1410515SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610585Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 126592 # Number of bytes read from this memory 1710585Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 108352 # Number of bytes read from this memory 1810585Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 12219800 # Number of bytes read from this memory 1910585Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.l2cache.prefetcher 55224576 # Number of bytes read from this memory 2010585Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 171840 # Number of bytes read from this memory 2110585Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.itb.walker 160768 # Number of bytes read from this memory 2210585Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 11630176 # Number of bytes read from this memory 2310585Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.l2cache.prefetcher 36221056 # Number of bytes read from this memory 2410585Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 451968 # Number of bytes read from this memory 2510585Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 116315128 # Number of bytes read from this memory 2610585Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 4075008 # Number of instructions bytes read from this memory 2710585Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 659840 # Number of instructions bytes read from this memory 2810585Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 4734848 # Number of instructions bytes read from this memory 2910585Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 84862912 # Number of bytes written to this memory 3010585Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.inst 20812 # Number of bytes written to this memory 3110585Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu1.inst 4 # Number of bytes written to this memory 3210585Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 84883728 # Number of bytes written to this memory 3310585Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 1978 # Number of read requests responded to by this memory 3410585Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.itb.walker 1693 # Number of read requests responded to by this memory 3510585Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 190956 # Number of read requests responded to by this memory 3610585Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.l2cache.prefetcher 862884 # Number of read requests responded to by this memory 3710585Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 2685 # Number of read requests responded to by this memory 3810585Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.itb.walker 2512 # Number of read requests responded to by this memory 3910585Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 181736 # Number of read requests responded to by this memory 4010585Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.l2cache.prefetcher 565954 # Number of read requests responded to by this memory 4110585Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 7062 # Number of read requests responded to by this memory 4210585Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1817460 # Number of read requests responded to by this memory 4310585Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 1325983 # Number of write requests responded to by this memory 4410585Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.inst 2602 # Number of write requests responded to by this memory 4510585Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu1.inst 1 # Number of write requests responded to by this memory 4610585Sandreas.hansson@arm.comsystem.physmem.num_writes::total 1328586 # Number of write requests responded to by this memory 4710585Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 2674 # Total read bandwidth from this memory (bytes/s) 4810585Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.itb.walker 2288 # Total read bandwidth from this memory (bytes/s) 4910585Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 258077 # Total read bandwidth from this memory (bytes/s) 5010585Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.l2cache.prefetcher 1166321 # Total read bandwidth from this memory (bytes/s) 5110585Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 3629 # Total read bandwidth from this memory (bytes/s) 5210585Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.itb.walker 3395 # Total read bandwidth from this memory (bytes/s) 5310585Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 245625 # Total read bandwidth from this memory (bytes/s) 5410585Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.l2cache.prefetcher 764974 # Total read bandwidth from this memory (bytes/s) 5510585Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 9545 # Total read bandwidth from this memory (bytes/s) 5610585Sandreas.hansson@arm.comsystem.physmem.bw_read::total 2456529 # Total read bandwidth from this memory (bytes/s) 5710585Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 86063 # Instruction read bandwidth from this memory (bytes/s) 5810585Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 13936 # Instruction read bandwidth from this memory (bytes/s) 5910585Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 99998 # Instruction read bandwidth from this memory (bytes/s) 6010585Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 1792270 # Write bandwidth from this memory (bytes/s) 6110585Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu0.inst 440 # Write bandwidth from this memory (bytes/s) 6210585Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu1.inst 0 # Write bandwidth from this memory (bytes/s) 6310585Sandreas.hansson@arm.comsystem.physmem.bw_write::total 1792710 # Write bandwidth from this memory (bytes/s) 6410585Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 1792270 # Total bandwidth to/from this memory (bytes/s) 6510585Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 2674 # Total bandwidth to/from this memory (bytes/s) 6610585Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.itb.walker 2288 # Total bandwidth to/from this memory (bytes/s) 6710585Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 258517 # Total bandwidth to/from this memory (bytes/s) 6810585Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.l2cache.prefetcher 1166321 # Total bandwidth to/from this memory (bytes/s) 6910585Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 3629 # Total bandwidth to/from this memory (bytes/s) 7010585Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.itb.walker 3395 # Total bandwidth to/from this memory (bytes/s) 7110585Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 245625 # Total bandwidth to/from this memory (bytes/s) 7210585Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.l2cache.prefetcher 764974 # Total bandwidth to/from this memory (bytes/s) 7310585Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 9545 # Total bandwidth to/from this memory (bytes/s) 7410585Sandreas.hansson@arm.comsystem.physmem.bw_total::total 4249239 # Total bandwidth to/from this memory (bytes/s) 7510585Sandreas.hansson@arm.comsystem.physmem.readReqs 1817460 # Number of read requests accepted 7610585Sandreas.hansson@arm.comsystem.physmem.writeReqs 1459105 # Number of write requests accepted 7710585Sandreas.hansson@arm.comsystem.physmem.readBursts 1817460 # Number of DRAM read bursts, including those serviced by the write queue 7810585Sandreas.hansson@arm.comsystem.physmem.writeBursts 1459105 # Number of DRAM write bursts, including those merged in the write queue 7910585Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 116259968 # Total number of bytes read from DRAM 8010585Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 57472 # Total number of bytes read from write queue 8110585Sandreas.hansson@arm.comsystem.physmem.bytesWritten 92884608 # Total number of bytes written to DRAM 8210585Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 116315128 # Total read bytes from the system interface side 8310585Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 93236944 # Total written bytes from the system interface side 8410585Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 898 # Number of DRAM read bursts serviced by the write queue 8510585Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 7766 # Number of DRAM write bursts merged with an existing one 8610585Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 92270 # Number of requests that are neither read nor write 8710585Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 109521 # Per bank write bursts 8810585Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 125500 # Per bank write bursts 8910585Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 109858 # Per bank write bursts 9010585Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 118807 # Per bank write bursts 9110585Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 114750 # Per bank write bursts 9210585Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 133958 # Per bank write bursts 9310585Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 108183 # Per bank write bursts 9410585Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 109296 # Per bank write bursts 9510585Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 104951 # Per bank write bursts 9610585Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 157608 # Per bank write bursts 9710585Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 96466 # Per bank write bursts 9810585Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 111139 # Per bank write bursts 9910585Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 103753 # Per bank write bursts 10010585Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 116262 # Per bank write bursts 10110585Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 95073 # Per bank write bursts 10210585Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 101437 # Per bank write bursts 10310585Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 88391 # Per bank write bursts 10410585Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 94888 # Per bank write bursts 10510585Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 89089 # Per bank write bursts 10610585Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 94540 # Per bank write bursts 10710585Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 92096 # Per bank write bursts 10810585Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 104028 # Per bank write bursts 10910585Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 87215 # Per bank write bursts 11010585Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 89925 # Per bank write bursts 11110585Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 85891 # Per bank write bursts 11210585Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 90043 # Per bank write bursts 11310585Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 85085 # Per bank write bursts 11410585Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 94536 # Per bank write bursts 11510585Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 86659 # Per bank write bursts 11610585Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 94890 # Per bank write bursts 11710585Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 85144 # Per bank write bursts 11810585Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 88902 # Per bank write bursts 11910515SAli.Saidi@ARM.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 12010515SAli.Saidi@ARM.comsystem.physmem.numWrRetry 10 # Number of times write queue was full causing retry 12110585Sandreas.hansson@arm.comsystem.physmem.totGap 47349386828500 # Total gap between requests 12210515SAli.Saidi@ARM.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 12310515SAli.Saidi@ARM.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 12410515SAli.Saidi@ARM.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 12510515SAli.Saidi@ARM.comsystem.physmem.readPktSize::3 37 # Read request sizes (log2) 12610515SAli.Saidi@ARM.comsystem.physmem.readPktSize::4 5 # Read request sizes (log2) 12710515SAli.Saidi@ARM.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 12810585Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 1817418 # Read request sizes (log2) 12910515SAli.Saidi@ARM.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 13010515SAli.Saidi@ARM.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 13110515SAli.Saidi@ARM.comsystem.physmem.writePktSize::2 2 # Write request sizes (log2) 13210515SAli.Saidi@ARM.comsystem.physmem.writePktSize::3 2601 # Write request sizes (log2) 13310515SAli.Saidi@ARM.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 13410515SAli.Saidi@ARM.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 13510585Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 1456502 # Write request sizes (log2) 13610585Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 724796 # What read queue length does an incoming req see 13710585Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 275224 # What read queue length does an incoming req see 13810585Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 218778 # What read queue length does an incoming req see 13910585Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 130576 # What read queue length does an incoming req see 14010585Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 121480 # What read queue length does an incoming req see 14110585Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 92297 # What read queue length does an incoming req see 14210585Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 78276 # What read queue length does an incoming req see 14310585Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 67824 # What read queue length does an incoming req see 14410585Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 54542 # What read queue length does an incoming req see 14510585Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 29215 # What read queue length does an incoming req see 14610585Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 6539 # What read queue length does an incoming req see 14710585Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 4680 # What read queue length does an incoming req see 14810585Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 3658 # What read queue length does an incoming req see 14910585Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 2988 # What read queue length does an incoming req see 15010585Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 2241 # What read queue length does an incoming req see 15110585Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 1701 # What read queue length does an incoming req see 15210585Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 695 # What read queue length does an incoming req see 15310585Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 500 # What read queue length does an incoming req see 15410585Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 325 # What read queue length does an incoming req see 15510585Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 212 # What read queue length does an incoming req see 15610585Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see 15710585Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see 15810585Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see 15910585Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see 16010515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 16110515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 16210515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 16310515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 16410515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 16510515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 16610515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 16710515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 16810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 16910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 17010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 17110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 17210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 17310515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 17410515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 17510515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 17610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 17710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 17810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 17910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 18010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 18110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 18210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 18310585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 20715 # What write queue length does an incoming req see 18410585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 26374 # What write queue length does an incoming req see 18510585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 37146 # What write queue length does an incoming req see 18610585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 48711 # What write queue length does an incoming req see 18710585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 55470 # What write queue length does an incoming req see 18810585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 62560 # What write queue length does an incoming req see 18910585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 67793 # What write queue length does an incoming req see 19010585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 75025 # What write queue length does an incoming req see 19110585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 82665 # What write queue length does an incoming req see 19210585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 93812 # What write queue length does an incoming req see 19310585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 97796 # What write queue length does an incoming req see 19410585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 101866 # What write queue length does an incoming req see 19510585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 103500 # What write queue length does an incoming req see 19610585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 107192 # What write queue length does an incoming req see 19710585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 100425 # What write queue length does an incoming req see 19810585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 103030 # What write queue length does an incoming req see 19910585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 105997 # What write queue length does an incoming req see 20010585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 102597 # What write queue length does an incoming req see 20110585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 17377 # What write queue length does an incoming req see 20210585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 13177 # What write queue length does an incoming req see 20310585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 9215 # What write queue length does an incoming req see 20410585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 5577 # What write queue length does an incoming req see 20510585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 2562 # What write queue length does an incoming req see 20610585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 1460 # What write queue length does an incoming req see 20710585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 1101 # What write queue length does an incoming req see 20810585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 881 # What write queue length does an incoming req see 20910585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 790 # What write queue length does an incoming req see 21010585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 689 # What write queue length does an incoming req see 21110585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 632 # What write queue length does an incoming req see 21210585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 612 # What write queue length does an incoming req see 21310585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 557 # What write queue length does an incoming req see 21410585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 530 # What write queue length does an incoming req see 21510585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 487 # What write queue length does an incoming req see 21610585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 467 # What write queue length does an incoming req see 21710585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 457 # What write queue length does an incoming req see 21810585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 413 # What write queue length does an incoming req see 21910585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 360 # What write queue length does an incoming req see 22010585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 293 # What write queue length does an incoming req see 22110585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 254 # What write queue length does an incoming req see 22210585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 234 # What write queue length does an incoming req see 22310585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 151 # What write queue length does an incoming req see 22410585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 108 # What write queue length does an incoming req see 22510585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 69 # What write queue length does an incoming req see 22610585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 46 # What write queue length does an incoming req see 22710585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 47 # What write queue length does an incoming req see 22810585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 43 # What write queue length does an incoming req see 22910585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 27 # What write queue length does an incoming req see 23010585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see 23110585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 11 # What write queue length does an incoming req see 23210585Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 894898 # Bytes accessed per row activation 23310585Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 233.707153 # Bytes accessed per row activation 23410585Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 136.846498 # Bytes accessed per row activation 23510585Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 284.283402 # Bytes accessed per row activation 23610585Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 463489 51.79% 51.79% # Bytes accessed per row activation 23710585Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 185877 20.77% 72.56% # Bytes accessed per row activation 23810585Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 67737 7.57% 80.13% # Bytes accessed per row activation 23910585Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 36988 4.13% 84.27% # Bytes accessed per row activation 24010585Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 29329 3.28% 87.54% # Bytes accessed per row activation 24110585Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 22133 2.47% 90.02% # Bytes accessed per row activation 24210585Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 15835 1.77% 91.79% # Bytes accessed per row activation 24310585Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 13649 1.53% 93.31% # Bytes accessed per row activation 24410585Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 59861 6.69% 100.00% # Bytes accessed per row activation 24510585Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 894898 # Bytes accessed per row activation 24610585Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 77790 # Reads before turning the bus around for writes 24710585Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 23.351999 # Reads before turning the bus around for writes 24810585Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 144.403085 # Reads before turning the bus around for writes 24910585Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-1023 77788 100.00% 100.00% # Reads before turning the bus around for writes 25010585Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 25110585Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes 25210585Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 77790 # Reads before turning the bus around for writes 25310585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 77790 # Writes before turning the bus around for reads 25410585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 18.656922 # Writes before turning the bus around for reads 25510585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 17.550932 # Writes before turning the bus around for reads 25610585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 11.537959 # Writes before turning the bus around for reads 25710585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16-23 73893 94.99% 94.99% # Writes before turning the bus around for reads 25810585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24-31 1079 1.39% 96.38% # Writes before turning the bus around for reads 25910585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32-39 616 0.79% 97.17% # Writes before turning the bus around for reads 26010585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::40-47 255 0.33% 97.50% # Writes before turning the bus around for reads 26110585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48-55 611 0.79% 98.28% # Writes before turning the bus around for reads 26210585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::56-63 159 0.20% 98.49% # Writes before turning the bus around for reads 26310585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::64-71 204 0.26% 98.75% # Writes before turning the bus around for reads 26410585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::72-79 127 0.16% 98.91% # Writes before turning the bus around for reads 26510585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::80-87 198 0.25% 99.17% # Writes before turning the bus around for reads 26610585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::88-95 57 0.07% 99.24% # Writes before turning the bus around for reads 26710585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::96-103 225 0.29% 99.53% # Writes before turning the bus around for reads 26810585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::104-111 47 0.06% 99.59% # Writes before turning the bus around for reads 26910585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::112-119 57 0.07% 99.66% # Writes before turning the bus around for reads 27010585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::120-127 49 0.06% 99.73% # Writes before turning the bus around for reads 27110585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::128-135 102 0.13% 99.86% # Writes before turning the bus around for reads 27210585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::136-143 22 0.03% 99.89% # Writes before turning the bus around for reads 27310585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::144-151 26 0.03% 99.92% # Writes before turning the bus around for reads 27410585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::152-159 10 0.01% 99.93% # Writes before turning the bus around for reads 27510585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::160-167 13 0.02% 99.95% # Writes before turning the bus around for reads 27610585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::168-175 6 0.01% 99.96% # Writes before turning the bus around for reads 27710585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::176-183 9 0.01% 99.97% # Writes before turning the bus around for reads 27810585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::184-191 5 0.01% 99.97% # Writes before turning the bus around for reads 27910585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::192-199 3 0.00% 99.98% # Writes before turning the bus around for reads 28010585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::200-207 2 0.00% 99.98% # Writes before turning the bus around for reads 28110585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::208-215 2 0.00% 99.98% # Writes before turning the bus around for reads 28210585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::216-223 2 0.00% 99.99% # Writes before turning the bus around for reads 28310585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::224-231 5 0.01% 99.99% # Writes before turning the bus around for reads 28410585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::240-247 1 0.00% 99.99% # Writes before turning the bus around for reads 28510585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::248-255 4 0.01% 100.00% # Writes before turning the bus around for reads 28610585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::272-279 1 0.00% 100.00% # Writes before turning the bus around for reads 28710585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 77790 # Writes before turning the bus around for reads 28810585Sandreas.hansson@arm.comsystem.physmem.totQLat 101322311265 # Total ticks spent queuing 28910585Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 135382848765 # Total ticks spent from burst creation until serviced by the DRAM 29010585Sandreas.hansson@arm.comsystem.physmem.totBusLat 9082810000 # Total ticks spent in databus transfers 29110585Sandreas.hansson@arm.comsystem.physmem.avgQLat 55776.96 # Average queueing delay per DRAM burst 29210515SAli.Saidi@ARM.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 29310585Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 74526.96 # Average memory access latency per DRAM burst 29410585Sandreas.hansson@arm.comsystem.physmem.avgRdBW 2.46 # Average DRAM read bandwidth in MiByte/s 29510585Sandreas.hansson@arm.comsystem.physmem.avgWrBW 1.96 # Average achieved write bandwidth in MiByte/s 29610585Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 2.46 # Average system read bandwidth in MiByte/s 29710585Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 1.97 # Average system write bandwidth in MiByte/s 29810515SAli.Saidi@ARM.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 29910515SAli.Saidi@ARM.comsystem.physmem.busUtil 0.03 # Data bus utilization in percentage 30010585Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 30110515SAli.Saidi@ARM.comsystem.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 30210515SAli.Saidi@ARM.comsystem.physmem.avgRdQLen 1.40 # Average read queue length when enqueuing 30310585Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 27.53 # Average write queue length when enqueuing 30410585Sandreas.hansson@arm.comsystem.physmem.readRowHits 1479200 # Number of row buffer hits during reads 30510585Sandreas.hansson@arm.comsystem.physmem.writeRowHits 893785 # Number of row buffer hits during writes 30610585Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 81.43 # Row buffer hit rate for reads 30710585Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 61.58 # Row buffer hit rate for writes 30810585Sandreas.hansson@arm.comsystem.physmem.avgGap 14450922.48 # Average gap between requests 30910585Sandreas.hansson@arm.comsystem.physmem.pageHitRate 72.61 # Row buffer hit rate, read and write combined 31010585Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::IDLE 45452153624500 # Time in different power states 31110585Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::REF 1581100040000 # Time in different power states 31210515SAli.Saidi@ARM.comsystem.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 31310585Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::ACT 316134376000 # Time in different power states 31410515SAli.Saidi@ARM.comsystem.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 31510585Sandreas.hansson@arm.comsystem.physmem.actEnergy::0 3577346640 # Energy for activate commands per rank (pJ) 31610585Sandreas.hansson@arm.comsystem.physmem.actEnergy::1 3188082240 # Energy for activate commands per rank (pJ) 31710585Sandreas.hansson@arm.comsystem.physmem.preEnergy::0 1951925250 # Energy for precharge commands per rank (pJ) 31810585Sandreas.hansson@arm.comsystem.physmem.preEnergy::1 1739529000 # Energy for precharge commands per rank (pJ) 31910585Sandreas.hansson@arm.comsystem.physmem.readEnergy::0 7253009400 # Energy for read commands per rank (pJ) 32010585Sandreas.hansson@arm.comsystem.physmem.readEnergy::1 6916111800 # Energy for read commands per rank (pJ) 32110585Sandreas.hansson@arm.comsystem.physmem.writeEnergy::0 4796314560 # Energy for write commands per rank (pJ) 32210585Sandreas.hansson@arm.comsystem.physmem.writeEnergy::1 4608252000 # Energy for write commands per rank (pJ) 32310585Sandreas.hansson@arm.comsystem.physmem.refreshEnergy::0 3092631678240 # Energy for refresh commands per rank (pJ) 32410585Sandreas.hansson@arm.comsystem.physmem.refreshEnergy::1 3092631678240 # Energy for refresh commands per rank (pJ) 32510585Sandreas.hansson@arm.comsystem.physmem.actBackEnergy::0 1196963299980 # Energy for active background per rank (pJ) 32610585Sandreas.hansson@arm.comsystem.physmem.actBackEnergy::1 1185023558430 # Energy for active background per rank (pJ) 32710585Sandreas.hansson@arm.comsystem.physmem.preBackEnergy::0 27359663548500 # Energy for precharge background per rank (pJ) 32810585Sandreas.hansson@arm.comsystem.physmem.preBackEnergy::1 27370137006000 # Energy for precharge background per rank (pJ) 32910585Sandreas.hansson@arm.comsystem.physmem.totalEnergy::0 31666837122570 # Total energy per rank (pJ) 33010585Sandreas.hansson@arm.comsystem.physmem.totalEnergy::1 31664244217710 # Total energy per rank (pJ) 33110585Sandreas.hansson@arm.comsystem.physmem.averagePower::0 668.790877 # Core power per rank (mW) 33210585Sandreas.hansson@arm.comsystem.physmem.averagePower::1 668.736116 # Core power per rank (mW) 33310515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::cpu0.inst 740 # Number of bytes read from this memory 33410515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::cpu1.inst 584 # Number of bytes read from this memory 33510515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory 33610515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory 33710515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory 33810515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory 33910515SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::cpu0.inst 16 # Number of read requests responded to by this memory 34010515SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory 34110515SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory 34210515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu0.inst 16 # Total read bandwidth from this memory (bytes/s) 34310515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s) 34410515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s) 34510515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) 34610515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s) 34710515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) 34810515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu0.inst 16 # Total bandwidth to/from this memory (bytes/s) 34910515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s) 35010515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) 35110585Sandreas.hansson@arm.comsystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 35210585Sandreas.hansson@arm.comsystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 35310585Sandreas.hansson@arm.comsystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 35410585Sandreas.hansson@arm.comsystem.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 35510585Sandreas.hansson@arm.comsystem.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 35610585Sandreas.hansson@arm.comsystem.cf0.dma_write_txs 1670 # Number of DMA write transactions. 35710585Sandreas.hansson@arm.comsystem.cpu0.branchPred.lookups 127854962 # Number of BP lookups 35810585Sandreas.hansson@arm.comsystem.cpu0.branchPred.condPredicted 91169153 # Number of conditional branches predicted 35910585Sandreas.hansson@arm.comsystem.cpu0.branchPred.condIncorrect 5795491 # Number of conditional branches incorrect 36010585Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBLookups 97464931 # Number of BTB lookups 36110585Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBHits 70565780 # Number of BTB hits 36210585Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 36310585Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBHitPct 72.401200 # BTB Hit Percentage 36410585Sandreas.hansson@arm.comsystem.cpu0.branchPred.usedRAS 14662444 # Number of times the RAS was used to get a target. 36510585Sandreas.hansson@arm.comsystem.cpu0.branchPred.RASInCorrect 979053 # Number of incorrect RAS predictions. 36610515SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 36710585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 36810585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 36910585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 37010585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 37110585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 37210585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 37310585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 37410585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 37510585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 37610585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 37710585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 37810585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 37910585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 38010585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 38110585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 38210585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 38310585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 38410585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 38510585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 38610585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 38710585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 38810585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_hits 0 # ITB inst hits 38910585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_misses 0 # ITB inst misses 39010585Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 80634882 # DTB read hits 39110585Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 217470 # DTB read misses 39210585Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 71942682 # DTB write hits 39310585Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 47848 # DTB write misses 39410585Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 39510585Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 39610585Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 42758 # Number of times TLB was flushed by MVA & ASID 39710585Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_asid 1054 # Number of times TLB was flushed by ASID 39810585Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_entries 34852 # Number of entries that have been flushed from TLB 39910585Sandreas.hansson@arm.comsystem.cpu0.dtb.align_faults 1874 # Number of TLB faults due to alignment restrictions 40010585Sandreas.hansson@arm.comsystem.cpu0.dtb.prefetch_faults 8493 # Number of TLB faults due to prefetch 40110585Sandreas.hansson@arm.comsystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 40210585Sandreas.hansson@arm.comsystem.cpu0.dtb.perms_faults 11561 # Number of TLB faults due to permissions restrictions 40310585Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 80852352 # DTB read accesses 40410585Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 71990530 # DTB write accesses 40510585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 40610585Sandreas.hansson@arm.comsystem.cpu0.dtb.hits 152577564 # DTB hits 40710585Sandreas.hansson@arm.comsystem.cpu0.dtb.misses 265318 # DTB misses 40810585Sandreas.hansson@arm.comsystem.cpu0.dtb.accesses 152842882 # DTB accesses 40910585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 41010585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 41110585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 41210585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 41310585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 41410585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 41510585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 41610585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 41710585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 41810585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 41910585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 42010585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 42110585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 42210585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 42310585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 42410585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 42510585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 42610585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 42710585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 42810585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 42910585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 43010585Sandreas.hansson@arm.comsystem.cpu0.itb.inst_hits 228743332 # ITB inst hits 43110585Sandreas.hansson@arm.comsystem.cpu0.itb.inst_misses 63317 # ITB inst misses 43210585Sandreas.hansson@arm.comsystem.cpu0.itb.read_hits 0 # DTB read hits 43310585Sandreas.hansson@arm.comsystem.cpu0.itb.read_misses 0 # DTB read misses 43410585Sandreas.hansson@arm.comsystem.cpu0.itb.write_hits 0 # DTB write hits 43510585Sandreas.hansson@arm.comsystem.cpu0.itb.write_misses 0 # DTB write misses 43610585Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 43710585Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 43810585Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 42758 # Number of times TLB was flushed by MVA & ASID 43910585Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_asid 1054 # Number of times TLB was flushed by ASID 44010585Sandreas.hansson@arm.comsystem.cpu0.itb.flush_entries 24510 # Number of entries that have been flushed from TLB 44110585Sandreas.hansson@arm.comsystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 44210585Sandreas.hansson@arm.comsystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 44310585Sandreas.hansson@arm.comsystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 44410585Sandreas.hansson@arm.comsystem.cpu0.itb.perms_faults 202277 # Number of TLB faults due to permissions restrictions 44510585Sandreas.hansson@arm.comsystem.cpu0.itb.read_accesses 0 # DTB read accesses 44610585Sandreas.hansson@arm.comsystem.cpu0.itb.write_accesses 0 # DTB write accesses 44710585Sandreas.hansson@arm.comsystem.cpu0.itb.inst_accesses 228806649 # ITB inst accesses 44810585Sandreas.hansson@arm.comsystem.cpu0.itb.hits 228743332 # DTB hits 44910585Sandreas.hansson@arm.comsystem.cpu0.itb.misses 63317 # DTB misses 45010585Sandreas.hansson@arm.comsystem.cpu0.itb.accesses 228806649 # DTB accesses 45110585Sandreas.hansson@arm.comsystem.cpu0.numCycles 867293351 # number of cpu cycles simulated 45210585Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 45310585Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 45410585Sandreas.hansson@arm.comsystem.cpu0.committedInsts 417325536 # Number of instructions committed 45510585Sandreas.hansson@arm.comsystem.cpu0.committedOps 490736323 # Number of ops (including micro ops) committed 45610585Sandreas.hansson@arm.comsystem.cpu0.discardedOps 44793539 # Number of ops (including micro ops) which were discarded before commit 45710585Sandreas.hansson@arm.comsystem.cpu0.numFetchSuspends 4342 # Number of times Execute suspended instruction fetching 45810585Sandreas.hansson@arm.comsystem.cpu0.quiesceCycles 93832115526 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 45910585Sandreas.hansson@arm.comsystem.cpu0.cpi 2.078218 # CPI: cycles per instruction 46010585Sandreas.hansson@arm.comsystem.cpu0.ipc 0.481182 # IPC: instructions per cycle 46110585Sandreas.hansson@arm.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 46210585Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 4790 # number of quiesce instructions executed 46310585Sandreas.hansson@arm.comsystem.cpu0.tickCycles 682045150 # Number of cycles that the object actually ticked 46410585Sandreas.hansson@arm.comsystem.cpu0.idleCycles 185248201 # Total number of cycles that the object has spent stopped 46510585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 5375859 # number of replacements 46610585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 504.387778 # Cycle average of tags in use 46710585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 144555742 # Total number of references to valid blocks. 46810585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 5376371 # Sample count of references to valid blocks. 46910585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 26.887233 # Average number of references to valid blocks. 47010585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 4951320000 # Cycle when the warmup percentage was hit. 47110585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.inst 504.387778 # Average occupied blocks per requestor 47210585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.inst 0.985132 # Average percentage of cache occupancy 47310585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.985132 # Average percentage of cache occupancy 47410585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 47510585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id 47610585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 377 # Occupied blocks per task id 47710585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id 47810585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 47910585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 308078040 # Number of tag accesses 48010585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 308078040 # Number of data accesses 48110585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.inst 74032777 # number of ReadReq hits 48210585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 74032777 # number of ReadReq hits 48310585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.inst 66638302 # number of WriteReq hits 48410585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 66638302 # number of WriteReq hits 48510585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_hits::cpu0.inst 115191 # number of WriteInvalidateReq hits 48610585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_hits::total 115191 # number of WriteInvalidateReq hits 48710585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 1688442 # number of LoadLockedReq hits 48810585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 1688442 # number of LoadLockedReq hits 48910585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.inst 1614699 # number of StoreCondReq hits 49010585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 1614699 # number of StoreCondReq hits 49110585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.inst 140671079 # number of demand (read+write) hits 49210585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 140671079 # number of demand (read+write) hits 49310585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.inst 140671079 # number of overall hits 49410585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 140671079 # number of overall hits 49510585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.inst 3863790 # number of ReadReq misses 49610585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 3863790 # number of ReadReq misses 49710585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.inst 2319255 # number of WriteReq misses 49810585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 2319255 # number of WriteReq misses 49910585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_misses::cpu0.inst 742685 # number of WriteInvalidateReq misses 50010585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_misses::total 742685 # number of WriteInvalidateReq misses 50110585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 105957 # number of LoadLockedReq misses 50210585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 105957 # number of LoadLockedReq misses 50310585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.inst 178436 # number of StoreCondReq misses 50410585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 178436 # number of StoreCondReq misses 50510585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.inst 6183045 # number of demand (read+write) misses 50610585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 6183045 # number of demand (read+write) misses 50710585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.inst 6183045 # number of overall misses 50810585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 6183045 # number of overall misses 50910585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 54382834533 # number of ReadReq miss cycles 51010585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 54382834533 # number of ReadReq miss cycles 51110585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 36195221997 # number of WriteReq miss cycles 51210585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 36195221997 # number of WriteReq miss cycles 51310585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.inst 21037893950 # number of WriteInvalidateReq miss cycles 51410585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_miss_latency::total 21037893950 # number of WriteInvalidateReq miss cycles 51510585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 1466052740 # number of LoadLockedReq miss cycles 51610585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 1466052740 # number of LoadLockedReq miss cycles 51710585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 3737583856 # number of StoreCondReq miss cycles 51810585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 3737583856 # number of StoreCondReq miss cycles 51910585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 3062000 # number of StoreCondFailReq miss cycles 52010585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::total 3062000 # number of StoreCondFailReq miss cycles 52110585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::cpu0.inst 90578056530 # number of demand (read+write) miss cycles 52210585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::total 90578056530 # number of demand (read+write) miss cycles 52310585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::cpu0.inst 90578056530 # number of overall miss cycles 52410585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::total 90578056530 # number of overall miss cycles 52510585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.inst 77896567 # number of ReadReq accesses(hits+misses) 52610585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 77896567 # number of ReadReq accesses(hits+misses) 52710585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.inst 68957557 # number of WriteReq accesses(hits+misses) 52810585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 68957557 # number of WriteReq accesses(hits+misses) 52910585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.inst 857876 # number of WriteInvalidateReq accesses(hits+misses) 53010585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_accesses::total 857876 # number of WriteInvalidateReq accesses(hits+misses) 53110585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 1794399 # number of LoadLockedReq accesses(hits+misses) 53210585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 1794399 # number of LoadLockedReq accesses(hits+misses) 53310585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 1793135 # number of StoreCondReq accesses(hits+misses) 53410585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 1793135 # number of StoreCondReq accesses(hits+misses) 53510585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.inst 146854124 # number of demand (read+write) accesses 53610585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 146854124 # number of demand (read+write) accesses 53710585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.inst 146854124 # number of overall (read+write) accesses 53810585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 146854124 # number of overall (read+write) accesses 53910585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.049602 # miss rate for ReadReq accesses 54010585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.049602 # miss rate for ReadReq accesses 54110585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.033633 # miss rate for WriteReq accesses 54210585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.033633 # miss rate for WriteReq accesses 54310585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.inst 0.865725 # miss rate for WriteInvalidateReq accesses 54410585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.865725 # miss rate for WriteInvalidateReq accesses 54510585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.059049 # miss rate for LoadLockedReq accesses 54610585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059049 # miss rate for LoadLockedReq accesses 54710585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.099511 # miss rate for StoreCondReq accesses 54810585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.099511 # miss rate for StoreCondReq accesses 54910585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.inst 0.042103 # miss rate for demand accesses 55010585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.042103 # miss rate for demand accesses 55110585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.inst 0.042103 # miss rate for overall accesses 55210585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.042103 # miss rate for overall accesses 55310585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 14074.997485 # average ReadReq miss latency 55410585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 14074.997485 # average ReadReq miss latency 55510585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15606.400330 # average WriteReq miss latency 55610585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 15606.400330 # average WriteReq miss latency 55710585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.inst 28326.806048 # average WriteInvalidateReq miss latency 55810585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 28326.806048 # average WriteInvalidateReq miss latency 55910585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 13836.299065 # average LoadLockedReq miss latency 56010585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13836.299065 # average LoadLockedReq miss latency 56110585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 20946.355309 # average StoreCondReq miss latency 56210585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20946.355309 # average StoreCondReq miss latency 56310585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency 56410585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 56510585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 14649.425409 # average overall miss latency 56610585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 14649.425409 # average overall miss latency 56710585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 14649.425409 # average overall miss latency 56810585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 14649.425409 # average overall miss latency 56910585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 57010585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 57110585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 57210585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 57310585Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 57410585Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 57510585Sandreas.hansson@arm.comsystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 57610585Sandreas.hansson@arm.comsystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 57710585Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 3741617 # number of writebacks 57810585Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 3741617 # number of writebacks 57910585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 374932 # number of ReadReq MSHR hits 58010585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 374932 # number of ReadReq MSHR hits 58110585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 967778 # number of WriteReq MSHR hits 58210585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 967778 # number of WriteReq MSHR hits 58310585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.inst 26 # number of WriteInvalidateReq MSHR hits 58410585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 26 # number of WriteInvalidateReq MSHR hits 58510585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 53 # number of LoadLockedReq MSHR hits 58610585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 53 # number of LoadLockedReq MSHR hits 58710585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.inst 76 # number of StoreCondReq MSHR hits 58810585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_hits::total 76 # number of StoreCondReq MSHR hits 58910585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::cpu0.inst 1342710 # number of demand (read+write) MSHR hits 59010585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::total 1342710 # number of demand (read+write) MSHR hits 59110585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::cpu0.inst 1342710 # number of overall MSHR hits 59210585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::total 1342710 # number of overall MSHR hits 59310585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 3488858 # number of ReadReq MSHR misses 59410585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 3488858 # number of ReadReq MSHR misses 59510585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 1351477 # number of WriteReq MSHR misses 59610585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 1351477 # number of WriteReq MSHR misses 59710585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.inst 742659 # number of WriteInvalidateReq MSHR misses 59810585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 742659 # number of WriteInvalidateReq MSHR misses 59910585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 105904 # number of LoadLockedReq MSHR misses 60010585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 105904 # number of LoadLockedReq MSHR misses 60110585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 178360 # number of StoreCondReq MSHR misses 60210585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 178360 # number of StoreCondReq MSHR misses 60310585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.inst 4840335 # number of demand (read+write) MSHR misses 60410585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 4840335 # number of demand (read+write) MSHR misses 60510585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.inst 4840335 # number of overall MSHR misses 60610585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 4840335 # number of overall MSHR misses 60710585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 42020078260 # number of ReadReq MSHR miss cycles 60810585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 42020078260 # number of ReadReq MSHR miss cycles 60910585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 19120911908 # number of WriteReq MSHR miss cycles 61010585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 19120911908 # number of WriteReq MSHR miss cycles 61110585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 19537847050 # number of WriteInvalidateReq MSHR miss cycles 61210585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 19537847050 # number of WriteInvalidateReq MSHR miss cycles 61310585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 1252614238 # number of LoadLockedReq MSHR miss cycles 61410585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1252614238 # number of LoadLockedReq MSHR miss cycles 61510585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 3369767592 # number of StoreCondReq MSHR miss cycles 61610585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3369767592 # number of StoreCondReq MSHR miss cycles 61710585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 2341000 # number of StoreCondFailReq MSHR miss cycles 61810585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2341000 # number of StoreCondFailReq MSHR miss cycles 61910585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 61140990168 # number of demand (read+write) MSHR miss cycles 62010585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 61140990168 # number of demand (read+write) MSHR miss cycles 62110585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 61140990168 # number of overall MSHR miss cycles 62210585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 61140990168 # number of overall MSHR miss cycles 62310585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2949307890 # number of ReadReq MSHR uncacheable cycles 62410585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2949307890 # number of ReadReq MSHR uncacheable cycles 62510585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 3070097397 # number of WriteReq MSHR uncacheable cycles 62610585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3070097397 # number of WriteReq MSHR uncacheable cycles 62710585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 6019405287 # number of overall MSHR uncacheable cycles 62810585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 6019405287 # number of overall MSHR uncacheable cycles 62910585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.044788 # mshr miss rate for ReadReq accesses 63010585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.044788 # mshr miss rate for ReadReq accesses 63110585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.019599 # mshr miss rate for WriteReq accesses 63210585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019599 # mshr miss rate for WriteReq accesses 63310585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.inst 0.865695 # mshr miss rate for WriteInvalidateReq accesses 63410585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.865695 # mshr miss rate for WriteInvalidateReq accesses 63510585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.059019 # mshr miss rate for LoadLockedReq accesses 63610585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059019 # mshr miss rate for LoadLockedReq accesses 63710585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.099468 # mshr miss rate for StoreCondReq accesses 63810585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.099468 # mshr miss rate for StoreCondReq accesses 63910585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.032960 # mshr miss rate for demand accesses 64010585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.032960 # mshr miss rate for demand accesses 64110585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.032960 # mshr miss rate for overall accesses 64210585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.032960 # mshr miss rate for overall accesses 64310585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12044.078108 # average ReadReq mshr miss latency 64410585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12044.078108 # average ReadReq mshr miss latency 64510585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14148.159316 # average WriteReq mshr miss latency 64610585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14148.159316 # average WriteReq mshr miss latency 64710585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 26307.965096 # average WriteInvalidateReq mshr miss latency 64810585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 26307.965096 # average WriteInvalidateReq mshr miss latency 64910585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 11827.827447 # average LoadLockedReq mshr miss latency 65010585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11827.827447 # average LoadLockedReq mshr miss latency 65110585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 18893.067908 # average StoreCondReq mshr miss latency 65210585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18893.067908 # average StoreCondReq mshr miss latency 65310585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency 65410585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 65510585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 12631.561693 # average overall mshr miss latency 65610585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 12631.561693 # average overall mshr miss latency 65710585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 12631.561693 # average overall mshr miss latency 65810585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 12631.561693 # average overall mshr miss latency 65910585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 66010585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 66110585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 66210585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 66310585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 66410585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 66510585Sandreas.hansson@arm.comsystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 66610585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 8781546 # number of replacements 66710585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.937582 # Cycle average of tags in use 66810585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 219752565 # Total number of references to valid blocks. 66910585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 8782058 # Sample count of references to valid blocks. 67010585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 25.022901 # Average number of references to valid blocks. 67110585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 16633914000 # Cycle when the warmup percentage was hit. 67210585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.937582 # Average occupied blocks per requestor 67310585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999878 # Average percentage of cache occupancy 67410585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999878 # Average percentage of cache occupancy 67510585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 67610585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id 67710585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 390 # Occupied blocks per task id 67810585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id 67910585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 68010585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 465851331 # Number of tag accesses 68110585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 465851331 # Number of data accesses 68210585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 219752565 # number of ReadReq hits 68310585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 219752565 # number of ReadReq hits 68410585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 219752565 # number of demand (read+write) hits 68510585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 219752565 # number of demand (read+write) hits 68610585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 219752565 # number of overall hits 68710585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 219752565 # number of overall hits 68810585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 8782067 # number of ReadReq misses 68910585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 8782067 # number of ReadReq misses 69010585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 8782067 # number of demand (read+write) misses 69110585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 8782067 # number of demand (read+write) misses 69210585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 8782067 # number of overall misses 69310585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 8782067 # number of overall misses 69410585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 75181971221 # number of ReadReq miss cycles 69510585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 75181971221 # number of ReadReq miss cycles 69610585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 75181971221 # number of demand (read+write) miss cycles 69710585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::total 75181971221 # number of demand (read+write) miss cycles 69810585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 75181971221 # number of overall miss cycles 69910585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::total 75181971221 # number of overall miss cycles 70010585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 228534632 # number of ReadReq accesses(hits+misses) 70110585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 228534632 # number of ReadReq accesses(hits+misses) 70210585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 228534632 # number of demand (read+write) accesses 70310585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 228534632 # number of demand (read+write) accesses 70410585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 228534632 # number of overall (read+write) accesses 70510585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 228534632 # number of overall (read+write) accesses 70610585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.038428 # miss rate for ReadReq accesses 70710585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.038428 # miss rate for ReadReq accesses 70810585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.038428 # miss rate for demand accesses 70910585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.038428 # miss rate for demand accesses 71010585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.038428 # miss rate for overall accesses 71110585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.038428 # miss rate for overall accesses 71210585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8560.851474 # average ReadReq miss latency 71310585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 8560.851474 # average ReadReq miss latency 71410585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8560.851474 # average overall miss latency 71510585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 8560.851474 # average overall miss latency 71610585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8560.851474 # average overall miss latency 71710585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 8560.851474 # average overall miss latency 71810585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 71910585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 72010585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 72110585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 72210585Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 72310585Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 72410585Sandreas.hansson@arm.comsystem.cpu0.icache.fast_writes 0 # number of fast writes performed 72510585Sandreas.hansson@arm.comsystem.cpu0.icache.cache_copies 0 # number of cache copies performed 72610585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8782067 # number of ReadReq MSHR misses 72710585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 8782067 # number of ReadReq MSHR misses 72810585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 8782067 # number of demand (read+write) MSHR misses 72910585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::total 8782067 # number of demand (read+write) MSHR misses 73010585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 8782067 # number of overall MSHR misses 73110585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::total 8782067 # number of overall MSHR misses 73210585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 61997855741 # number of ReadReq MSHR miss cycles 73310585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 61997855741 # number of ReadReq MSHR miss cycles 73410585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 61997855741 # number of demand (read+write) MSHR miss cycles 73510585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 61997855741 # number of demand (read+write) MSHR miss cycles 73610585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 61997855741 # number of overall MSHR miss cycles 73710585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 61997855741 # number of overall MSHR miss cycles 73810585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4713229500 # number of ReadReq MSHR uncacheable cycles 73910585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4713229500 # number of ReadReq MSHR uncacheable cycles 74010585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4713229500 # number of overall MSHR uncacheable cycles 74110585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::total 4713229500 # number of overall MSHR uncacheable cycles 74210585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.038428 # mshr miss rate for ReadReq accesses 74310585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.038428 # mshr miss rate for ReadReq accesses 74410585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.038428 # mshr miss rate for demand accesses 74510585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.038428 # mshr miss rate for demand accesses 74610585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.038428 # mshr miss rate for overall accesses 74710585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.038428 # mshr miss rate for overall accesses 74810585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7059.597216 # average ReadReq mshr miss latency 74910585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7059.597216 # average ReadReq mshr miss latency 75010585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7059.597216 # average overall mshr miss latency 75110585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 7059.597216 # average overall mshr miss latency 75210585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7059.597216 # average overall mshr miss latency 75310585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 7059.597216 # average overall mshr miss latency 75410585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 75510585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 75610585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 75710585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 75810585Sandreas.hansson@arm.comsystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 75910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 84003023 # number of hwpf identified 76010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 4398912 # number of hwpf that were already in mshr 76110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 74572645 # number of hwpf that were already in the cache 76210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 1090360 # number of hwpf that were already in the prefetch queue 76310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 76410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 154166 # number of hwpf removed because MSHR allocated 76510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 3786940 # number of hwpf issued 76610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 6742713 # number of hwpf spanning a virtual page 76710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 76810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.replacements 4037603 # number of replacements 76910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tagsinuse 16229.874548 # Cycle average of tags in use 77010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.total_refs 15269588 # Total number of references to valid blocks. 77110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.sampled_refs 4053811 # Sample count of references to valid blocks. 77210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.avg_refs 3.766724 # Average number of references to valid blocks. 77310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 14918796500 # Cycle when the warmup percentage was hit. 77410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 3465.639505 # Average occupied blocks per requestor 77510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 40.958286 # Average occupied blocks per requestor 77610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 27.625357 # Average occupied blocks per requestor 77710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2577.016988 # Average occupied blocks per requestor 77810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 10118.634411 # Average occupied blocks per requestor 77910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.211526 # Average percentage of cache occupancy 78010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002500 # Average percentage of cache occupancy 78110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001686 # Average percentage of cache occupancy 78210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.157289 # Average percentage of cache occupancy 78310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.617592 # Average percentage of cache occupancy 78410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.990593 # Average percentage of cache occupancy 78510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1022 10250 # Occupied blocks per task id 78610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 92 # Occupied blocks per task id 78710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 5866 # Occupied blocks per task id 78810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::0 116 # Occupied blocks per task id 78910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::1 1048 # Occupied blocks per task id 79010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::2 4016 # Occupied blocks per task id 79110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::3 3415 # Occupied blocks per task id 79210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1655 # Occupied blocks per task id 79310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::1 22 # Occupied blocks per task id 79410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 40 # Occupied blocks per task id 79510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 23 # Occupied blocks per task id 79610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id 79710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 79810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 525 # Occupied blocks per task id 79910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2441 # Occupied blocks per task id 80010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 1975 # Occupied blocks per task id 80110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 887 # Occupied blocks per task id 80210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1022 0.625610 # Percentage of cache occupancy per task id 80310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005615 # Percentage of cache occupancy per task id 80410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.358032 # Percentage of cache occupancy per task id 80510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tag_accesses 311163440 # Number of tag accesses 80610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.data_accesses 311163440 # Number of data accesses 80710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 470272 # number of ReadReq hits 80810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 147367 # number of ReadReq hits 80910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.inst 11429450 # number of ReadReq hits 81010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 12047089 # number of ReadReq hits 81110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_hits::writebacks 3741617 # number of Writeback hits 81210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_hits::total 3741617 # number of Writeback hits 81310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.inst 295044 # number of WriteInvalidateReq hits 81410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_hits::total 295044 # number of WriteInvalidateReq hits 81510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 86443 # number of UpgradeReq hits 81610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::total 86443 # number of UpgradeReq hits 81710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 36465 # number of SCUpgradeReq hits 81810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_hits::total 36465 # number of SCUpgradeReq hits 81910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.inst 911350 # number of ReadExReq hits 82010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 911350 # number of ReadExReq hits 82110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 470272 # number of demand (read+write) hits 82210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 147367 # number of demand (read+write) hits 82310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 12340800 # number of demand (read+write) hits 82410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::total 12958439 # number of demand (read+write) hits 82510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 470272 # number of overall hits 82610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 147367 # number of overall hits 82710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 12340800 # number of overall hits 82810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::total 12958439 # number of overall hits 82910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 13865 # number of ReadReq misses 83010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10088 # number of ReadReq misses 83110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.inst 947171 # number of ReadReq misses 83210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 971124 # number of ReadReq misses 83310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.inst 446451 # number of WriteInvalidateReq misses 83410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_misses::total 446451 # number of WriteInvalidateReq misses 83510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 123568 # number of UpgradeReq misses 83610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 123568 # number of UpgradeReq misses 83710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 141888 # number of SCUpgradeReq misses 83810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 141888 # number of SCUpgradeReq misses 83910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.inst 7 # number of SCUpgradeFailReq misses 84010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses 84110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.inst 231493 # number of ReadExReq misses 84210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 231493 # number of ReadExReq misses 84310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 13865 # number of demand (read+write) misses 84410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 10088 # number of demand (read+write) misses 84510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 1178664 # number of demand (read+write) misses 84610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::total 1202617 # number of demand (read+write) misses 84710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 13865 # number of overall misses 84810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 10088 # number of overall misses 84910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 1178664 # number of overall misses 85010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::total 1202617 # number of overall misses 85110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 459903131 # number of ReadReq miss cycles 85210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 354751936 # number of ReadReq miss cycles 85310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 28411115925 # number of ReadReq miss cycles 85410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::total 29225770992 # number of ReadReq miss cycles 85510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.inst 15916059245 # number of WriteInvalidateReq miss cycles 85610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 15916059245 # number of WriteInvalidateReq miss cycles 85710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 2454108805 # number of UpgradeReq miss cycles 85810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::total 2454108805 # number of UpgradeReq miss cycles 85910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 2872469472 # number of SCUpgradeReq miss cycles 86010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2872469472 # number of SCUpgradeReq miss cycles 86110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 2284000 # number of SCUpgradeFailReq miss cycles 86210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2284000 # number of SCUpgradeFailReq miss cycles 86310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 8822124839 # number of ReadExReq miss cycles 86410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::total 8822124839 # number of ReadExReq miss cycles 86510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 459903131 # number of demand (read+write) miss cycles 86610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 354751936 # number of demand (read+write) miss cycles 86710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.inst 37233240764 # number of demand (read+write) miss cycles 86810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::total 38047895831 # number of demand (read+write) miss cycles 86910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 459903131 # number of overall miss cycles 87010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 354751936 # number of overall miss cycles 87110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.inst 37233240764 # number of overall miss cycles 87210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::total 38047895831 # number of overall miss cycles 87310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 484137 # number of ReadReq accesses(hits+misses) 87410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 157455 # number of ReadReq accesses(hits+misses) 87510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.inst 12376621 # number of ReadReq accesses(hits+misses) 87610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 13018213 # number of ReadReq accesses(hits+misses) 87710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_accesses::writebacks 3741617 # number of Writeback accesses(hits+misses) 87810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_accesses::total 3741617 # number of Writeback accesses(hits+misses) 87910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.inst 741495 # number of WriteInvalidateReq accesses(hits+misses) 88010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_accesses::total 741495 # number of WriteInvalidateReq accesses(hits+misses) 88110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 210011 # number of UpgradeReq accesses(hits+misses) 88210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 210011 # number of UpgradeReq accesses(hits+misses) 88310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 178353 # number of SCUpgradeReq accesses(hits+misses) 88410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 178353 # number of SCUpgradeReq accesses(hits+misses) 88510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.inst 7 # number of SCUpgradeFailReq accesses(hits+misses) 88610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses) 88710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 1142843 # number of ReadExReq accesses(hits+misses) 88810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1142843 # number of ReadExReq accesses(hits+misses) 88910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 484137 # number of demand (read+write) accesses 89010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 157455 # number of demand (read+write) accesses 89110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 13519464 # number of demand (read+write) accesses 89210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::total 14161056 # number of demand (read+write) accesses 89310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 484137 # number of overall (read+write) accesses 89410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 157455 # number of overall (read+write) accesses 89510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 13519464 # number of overall (read+write) accesses 89610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::total 14161056 # number of overall (read+write) accesses 89710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.028639 # miss rate for ReadReq accesses 89810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.064069 # miss rate for ReadReq accesses 89910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.076529 # miss rate for ReadReq accesses 90010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.074597 # miss rate for ReadReq accesses 90110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.inst 0.602096 # miss rate for WriteInvalidateReq accesses 90210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.602096 # miss rate for WriteInvalidateReq accesses 90310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.588388 # miss rate for UpgradeReq accesses 90410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 0.588388 # miss rate for UpgradeReq accesses 90510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.795546 # miss rate for SCUpgradeReq accesses 90610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.795546 # miss rate for SCUpgradeReq accesses 90710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.inst 1 # miss rate for SCUpgradeFailReq accesses 90810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 90910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.202559 # miss rate for ReadExReq accesses 91010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.202559 # miss rate for ReadExReq accesses 91110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.028639 # miss rate for demand accesses 91210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.064069 # miss rate for demand accesses 91310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.087183 # miss rate for demand accesses 91410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.084924 # miss rate for demand accesses 91510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.028639 # miss rate for overall accesses 91610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.064069 # miss rate for overall accesses 91710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.087183 # miss rate for overall accesses 91810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.084924 # miss rate for overall accesses 91910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 33170.077966 # average ReadReq miss latency 92010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 35165.735131 # average ReadReq miss latency 92110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 29995.762038 # average ReadReq miss latency 92210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::total 30094.788093 # average ReadReq miss latency 92310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.inst 35650.181644 # average WriteInvalidateReq miss latency 92410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 35650.181644 # average WriteInvalidateReq miss latency 92510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 19860.391080 # average UpgradeReq miss latency 92610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 19860.391080 # average UpgradeReq miss latency 92710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 20244.625846 # average SCUpgradeReq miss latency 92810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20244.625846 # average SCUpgradeReq miss latency 92910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst 326285.714286 # average SCUpgradeFailReq miss latency 93010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 326285.714286 # average SCUpgradeFailReq miss latency 93110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 38109.682967 # average ReadExReq miss latency 93210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::total 38109.682967 # average ReadExReq miss latency 93310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 33170.077966 # average overall miss latency 93410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 35165.735131 # average overall miss latency 93510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 31589.359448 # average overall miss latency 93610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::total 31637.583562 # average overall miss latency 93710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 33170.077966 # average overall miss latency 93810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 35165.735131 # average overall miss latency 93910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 31589.359448 # average overall miss latency 94010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::total 31637.583562 # average overall miss latency 94110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_mshrs 196093 # number of cycles access was blocked 94210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 94310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_mshrs 2541 # number of cycles access was blocked 94410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 94510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs 77.171586 # average number of cycles each access was blocked 94610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 94710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.fast_writes 0 # number of fast writes performed 94810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.cache_copies 0 # number of cache copies performed 94910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::writebacks 1602519 # number of writebacks 95010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::total 1602519 # number of writebacks 95110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 2 # number of ReadReq MSHR hits 95210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 5 # number of ReadReq MSHR hits 95310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 79969 # number of ReadReq MSHR hits 95410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::total 79976 # number of ReadReq MSHR hits 95510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.inst 383227 # number of WriteInvalidateReq MSHR hits 95610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total 383227 # number of WriteInvalidateReq MSHR hits 95710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 9177 # number of ReadExReq MSHR hits 95810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::total 9177 # number of ReadExReq MSHR hits 95910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 2 # number of demand (read+write) MSHR hits 96010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 5 # number of demand (read+write) MSHR hits 96110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.inst 89146 # number of demand (read+write) MSHR hits 96210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::total 89153 # number of demand (read+write) MSHR hits 96310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 2 # number of overall MSHR hits 96410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 5 # number of overall MSHR hits 96510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.inst 89146 # number of overall MSHR hits 96610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::total 89153 # number of overall MSHR hits 96710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 13863 # number of ReadReq MSHR misses 96810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 10083 # number of ReadReq MSHR misses 96910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 867202 # number of ReadReq MSHR misses 97010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::total 891148 # number of ReadReq MSHR misses 97110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 3786879 # number of HardPFReq MSHR misses 97210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::total 3786879 # number of HardPFReq MSHR misses 97310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.inst 63224 # number of WriteInvalidateReq MSHR misses 97410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 63224 # number of WriteInvalidateReq MSHR misses 97510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 123568 # number of UpgradeReq MSHR misses 97610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::total 123568 # number of UpgradeReq MSHR misses 97710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 141888 # number of SCUpgradeReq MSHR misses 97810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 141888 # number of SCUpgradeReq MSHR misses 97910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.inst 7 # number of SCUpgradeFailReq MSHR misses 98010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses 98110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 222316 # number of ReadExReq MSHR misses 98210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::total 222316 # number of ReadExReq MSHR misses 98310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 13863 # number of demand (read+write) MSHR misses 98410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 10083 # number of demand (read+write) MSHR misses 98510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.inst 1089518 # number of demand (read+write) MSHR misses 98610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::total 1113464 # number of demand (read+write) MSHR misses 98710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 13863 # number of overall MSHR misses 98810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 10083 # number of overall MSHR misses 98910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.inst 1089518 # number of overall MSHR misses 99010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 3786879 # number of overall MSHR misses 99110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::total 4900343 # number of overall MSHR misses 99210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 362187797 # number of ReadReq MSHR miss cycles 99310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 283585554 # number of ReadReq MSHR miss cycles 99410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 20498207280 # number of ReadReq MSHR miss cycles 99510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::total 21143980631 # number of ReadReq MSHR miss cycles 99610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 168439656794 # number of HardPFReq MSHR miss cycles 99710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 168439656794 # number of HardPFReq MSHR miss cycles 99810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 1410635970 # number of WriteInvalidateReq MSHR miss cycles 99910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 1410635970 # number of WriteInvalidateReq MSHR miss cycles 100010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 2082130886 # number of UpgradeReq MSHR miss cycles 100110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2082130886 # number of UpgradeReq MSHR miss cycles 100210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 1980278880 # number of SCUpgradeReq MSHR miss cycles 100310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 1980278880 # number of SCUpgradeReq MSHR miss cycles 100410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst 1885000 # number of SCUpgradeFailReq MSHR miss cycles 100510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1885000 # number of SCUpgradeFailReq MSHR miss cycles 100610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 6408519883 # number of ReadExReq MSHR miss cycles 100710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 6408519883 # number of ReadExReq MSHR miss cycles 100810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 362187797 # number of demand (read+write) MSHR miss cycles 100910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 283585554 # number of demand (read+write) MSHR miss cycles 101010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 26906727163 # number of demand (read+write) MSHR miss cycles 101110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::total 27552500514 # number of demand (read+write) MSHR miss cycles 101210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 362187797 # number of overall MSHR miss cycles 101310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 283585554 # number of overall MSHR miss cycles 101410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 26906727163 # number of overall MSHR miss cycles 101510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 168439656794 # number of overall MSHR miss cycles 101610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::total 195992157308 # number of overall MSHR miss cycles 101710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6920870357 # number of ReadReq MSHR uncacheable cycles 101810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6920870357 # number of ReadReq MSHR uncacheable cycles 101910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 2922560102 # number of WriteReq MSHR uncacheable cycles 102010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2922560102 # number of WriteReq MSHR uncacheable cycles 102110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 9843430459 # number of overall MSHR uncacheable cycles 102210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9843430459 # number of overall MSHR uncacheable cycles 102310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.028634 # mshr miss rate for ReadReq accesses 102410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.064037 # mshr miss rate for ReadReq accesses 102510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.070068 # mshr miss rate for ReadReq accesses 102610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.068454 # mshr miss rate for ReadReq accesses 102710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 102810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 102910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.inst 0.085266 # mshr miss rate for WriteInvalidateReq accesses 103010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.085266 # mshr miss rate for WriteInvalidateReq accesses 103110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.588388 # mshr miss rate for UpgradeReq accesses 103210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.588388 # mshr miss rate for UpgradeReq accesses 103310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.795546 # mshr miss rate for SCUpgradeReq accesses 103410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.795546 # mshr miss rate for SCUpgradeReq accesses 103510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst 1 # mshr miss rate for SCUpgradeFailReq accesses 103610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 103710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.194529 # mshr miss rate for ReadExReq accesses 103810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.194529 # mshr miss rate for ReadExReq accesses 103910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.028634 # mshr miss rate for demand accesses 104010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.064037 # mshr miss rate for demand accesses 104110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.080589 # mshr miss rate for demand accesses 104210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::total 0.078629 # mshr miss rate for demand accesses 104310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.028634 # mshr miss rate for overall accesses 104410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.064037 # mshr miss rate for overall accesses 104510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.080589 # mshr miss rate for overall accesses 104610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 104710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::total 0.346044 # mshr miss rate for overall accesses 104810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26126.220659 # average ReadReq mshr miss latency 104910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28125.116929 # average ReadReq mshr miss latency 105010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23637.177128 # average ReadReq mshr miss latency 105110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23726.676861 # average ReadReq mshr miss latency 105210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 44479.809572 # average HardPFReq mshr miss latency 105310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 44479.809572 # average HardPFReq mshr miss latency 105410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 22311.716595 # average WriteInvalidateReq mshr miss latency 105510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 22311.716595 # average WriteInvalidateReq mshr miss latency 105610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 16850.081623 # average UpgradeReq mshr miss latency 105710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16850.081623 # average UpgradeReq mshr miss latency 105810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13956.633965 # average SCUpgradeReq mshr miss latency 105910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13956.633965 # average SCUpgradeReq mshr miss latency 106010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 269285.714286 # average SCUpgradeFailReq mshr miss latency 106110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 269285.714286 # average SCUpgradeFailReq mshr miss latency 106210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 28826.174828 # average ReadExReq mshr miss latency 106310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 28826.174828 # average ReadExReq mshr miss latency 106410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26126.220659 # average overall mshr miss latency 106510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 28125.116929 # average overall mshr miss latency 106610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24695.991404 # average overall mshr miss latency 106710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::total 24744.850767 # average overall mshr miss latency 106810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26126.220659 # average overall mshr miss latency 106910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 28125.116929 # average overall mshr miss latency 107010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24695.991404 # average overall mshr miss latency 107110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 44479.809572 # average overall mshr miss latency 107210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::total 39995.599759 # average overall mshr miss latency 107310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 107410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 107510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 107610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 107710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 107810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 107910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 108010585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 17406363 # Transaction distribution 108110585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 13329872 # Transaction distribution 108210585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 19688 # Transaction distribution 108310585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 19687 # Transaction distribution 108410585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::Writeback 3741617 # Transaction distribution 108510585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::HardPFReq 5530609 # Transaction distribution 108610585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 862152 # Transaction distribution 108710585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 741495 # Transaction distribution 108810585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 486160 # Transaction distribution 108910585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 325301 # Transaction distribution 109010585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 465486 # Transaction distribution 109110585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 67 # Transaction distribution 109210585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeFailResp 117 # Transaction distribution 109310585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1278141 # Transaction distribution 109410585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1152631 # Transaction distribution 109510585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 17668715 # Packet count per connected master and slave (bytes) 109610585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15752783 # Packet count per connected master and slave (bytes) 109710585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 346532 # Packet count per connected master and slave (bytes) 109810585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1063511 # Packet count per connected master and slave (bytes) 109910585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count::total 34831541 # Packet count per connected master and slave (bytes) 110010585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 565398848 # Cumulative packet size per connected master and slave (bytes) 110110585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 598192623 # Cumulative packet size per connected master and slave (bytes) 110210585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1259640 # Cumulative packet size per connected master and slave (bytes) 110310585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3873096 # Cumulative packet size per connected master and slave (bytes) 110410585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size::total 1168724207 # Cumulative packet size per connected master and slave (bytes) 110510585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoops 10729638 # Total snoops (count) 110610585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 29561564 # Request fanout histogram 110710585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 5.351841 # Request fanout histogram 110810585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.477545 # Request fanout histogram 110910585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 111010585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 111110585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 111210585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 111310585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 111410585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 111510585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::5 19160579 64.82% 64.82% # Request fanout histogram 111610585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::6 10400985 35.18% 100.00% # Request fanout histogram 111710585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 111810585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 111910585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 112010585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 29561564 # Request fanout histogram 112110585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.reqLayer0.occupancy 14119794312 # Layer occupancy (ticks) 112210585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 112310585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopLayer0.occupancy 225496496 # Layer occupancy (ticks) 112410585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 112510585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer0.occupancy 13269247990 # Layer occupancy (ticks) 112610585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 112710585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer1.occupancy 7748577182 # Layer occupancy (ticks) 112810585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 112910585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer2.occupancy 189385144 # Layer occupancy (ticks) 113010585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 113110585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer3.occupancy 579874631 # Layer occupancy (ticks) 113210585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 113310585Sandreas.hansson@arm.comsystem.cpu1.branchPred.lookups 146637664 # Number of BP lookups 113410585Sandreas.hansson@arm.comsystem.cpu1.branchPred.condPredicted 104244557 # Number of conditional branches predicted 113510585Sandreas.hansson@arm.comsystem.cpu1.branchPred.condIncorrect 6464776 # Number of conditional branches incorrect 113610585Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBLookups 109760718 # Number of BTB lookups 113710585Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBHits 80092874 # Number of BTB hits 113810585Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 113910585Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBHitPct 72.970436 # BTB Hit Percentage 114010585Sandreas.hansson@arm.comsystem.cpu1.branchPred.usedRAS 17287162 # Number of times the RAS was used to get a target. 114110585Sandreas.hansson@arm.comsystem.cpu1.branchPred.RASInCorrect 1125459 # Number of incorrect RAS predictions. 114210585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 114310585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 114410585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 114510585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 114610585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 114710585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 114810585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 114910585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 115010585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 115110585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 115210585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 115310585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 115410585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 115510585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 115610585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 115710585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 115810585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 115910585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 116010585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 116110585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 116210585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 116310585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_hits 0 # ITB inst hits 116410585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_misses 0 # ITB inst misses 116510585Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 95196820 # DTB read hits 116610585Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 258683 # DTB read misses 116710585Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 82774540 # DTB write hits 116810585Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 48918 # DTB write misses 116910585Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 117010585Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 117110585Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 42758 # Number of times TLB was flushed by MVA & ASID 117210585Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_asid 1054 # Number of times TLB was flushed by ASID 117310585Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_entries 40938 # Number of entries that have been flushed from TLB 117410585Sandreas.hansson@arm.comsystem.cpu1.dtb.align_faults 1166 # Number of TLB faults due to alignment restrictions 117510585Sandreas.hansson@arm.comsystem.cpu1.dtb.prefetch_faults 8454 # Number of TLB faults due to prefetch 117610585Sandreas.hansson@arm.comsystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 117710585Sandreas.hansson@arm.comsystem.cpu1.dtb.perms_faults 11190 # Number of TLB faults due to permissions restrictions 117810585Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 95455503 # DTB read accesses 117910585Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 82823458 # DTB write accesses 118010585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 118110585Sandreas.hansson@arm.comsystem.cpu1.dtb.hits 177971360 # DTB hits 118210585Sandreas.hansson@arm.comsystem.cpu1.dtb.misses 307601 # DTB misses 118310585Sandreas.hansson@arm.comsystem.cpu1.dtb.accesses 178278961 # DTB accesses 118410585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 118510585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 118610585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 118710585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 118810585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 118910585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 119010585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 119110585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 119210585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 119310585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 119410585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 119510585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 119610585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 119710585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 119810585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 119910585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 120010585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 120110585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 120210585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 120310585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 120410585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 120510585Sandreas.hansson@arm.comsystem.cpu1.itb.inst_hits 262373201 # ITB inst hits 120610585Sandreas.hansson@arm.comsystem.cpu1.itb.inst_misses 66107 # ITB inst misses 120710585Sandreas.hansson@arm.comsystem.cpu1.itb.read_hits 0 # DTB read hits 120810585Sandreas.hansson@arm.comsystem.cpu1.itb.read_misses 0 # DTB read misses 120910585Sandreas.hansson@arm.comsystem.cpu1.itb.write_hits 0 # DTB write hits 121010585Sandreas.hansson@arm.comsystem.cpu1.itb.write_misses 0 # DTB write misses 121110585Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 121210585Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 121310585Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 42758 # Number of times TLB was flushed by MVA & ASID 121410585Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_asid 1054 # Number of times TLB was flushed by ASID 121510585Sandreas.hansson@arm.comsystem.cpu1.itb.flush_entries 29545 # Number of entries that have been flushed from TLB 121610585Sandreas.hansson@arm.comsystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 121710585Sandreas.hansson@arm.comsystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 121810585Sandreas.hansson@arm.comsystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 121910585Sandreas.hansson@arm.comsystem.cpu1.itb.perms_faults 222220 # Number of TLB faults due to permissions restrictions 122010585Sandreas.hansson@arm.comsystem.cpu1.itb.read_accesses 0 # DTB read accesses 122110585Sandreas.hansson@arm.comsystem.cpu1.itb.write_accesses 0 # DTB write accesses 122210585Sandreas.hansson@arm.comsystem.cpu1.itb.inst_accesses 262439308 # ITB inst accesses 122310585Sandreas.hansson@arm.comsystem.cpu1.itb.hits 262373201 # DTB hits 122410585Sandreas.hansson@arm.comsystem.cpu1.itb.misses 66107 # DTB misses 122510585Sandreas.hansson@arm.comsystem.cpu1.itb.accesses 262439308 # DTB accesses 122610585Sandreas.hansson@arm.comsystem.cpu1.numCycles 965776076 # number of cpu cycles simulated 122710585Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 122810585Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 122910585Sandreas.hansson@arm.comsystem.cpu1.committedInsts 483897990 # Number of instructions committed 123010585Sandreas.hansson@arm.comsystem.cpu1.committedOps 569285719 # Number of ops (including micro ops) committed 123110585Sandreas.hansson@arm.comsystem.cpu1.discardedOps 49152054 # Number of ops (including micro ops) which were discarded before commit 123210585Sandreas.hansson@arm.comsystem.cpu1.numFetchSuspends 5850 # Number of times Execute suspended instruction fetching 123310585Sandreas.hansson@arm.comsystem.cpu1.quiesceCycles 93733878410 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 123410585Sandreas.hansson@arm.comsystem.cpu1.cpi 1.995826 # CPI: cycles per instruction 123510585Sandreas.hansson@arm.comsystem.cpu1.ipc 0.501046 # IPC: instructions per cycle 123610585Sandreas.hansson@arm.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 123710585Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 14403 # number of quiesce instructions executed 123810585Sandreas.hansson@arm.comsystem.cpu1.tickCycles 777604637 # Number of cycles that the object actually ticked 123910585Sandreas.hansson@arm.comsystem.cpu1.idleCycles 188171439 # Total number of cycles that the object has spent stopped 124010585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 5691678 # number of replacements 124110585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 432.252247 # Cycle average of tags in use 124210585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 169393329 # Total number of references to valid blocks. 124310585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 5692190 # Sample count of references to valid blocks. 124410585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 29.758903 # Average number of references to valid blocks. 124510585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 8364525946500 # Cycle when the warmup percentage was hit. 124610585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.inst 432.252247 # Average occupied blocks per requestor 124710585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.inst 0.844243 # Average percentage of cache occupancy 124810585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.844243 # Average percentage of cache occupancy 124910585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 125010585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id 125110585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id 125210585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id 125310585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 125410585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 358720623 # Number of tag accesses 125510585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 358720623 # Number of data accesses 125610585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.inst 87552380 # number of ReadReq hits 125710585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 87552380 # number of ReadReq hits 125810585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.inst 77214593 # number of WriteReq hits 125910585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 77214593 # number of WriteReq hits 126010585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_hits::cpu1.inst 211985 # number of WriteInvalidateReq hits 126110585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_hits::total 211985 # number of WriteInvalidateReq hits 126210585Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 1994962 # number of LoadLockedReq hits 126310585Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 1994962 # number of LoadLockedReq hits 126410585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.inst 1944639 # number of StoreCondReq hits 126510585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 1944639 # number of StoreCondReq hits 126610585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.inst 164766973 # number of demand (read+write) hits 126710585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 164766973 # number of demand (read+write) hits 126810585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.inst 164766973 # number of overall hits 126910585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 164766973 # number of overall hits 127010585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.inst 4362572 # number of ReadReq misses 127110585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 4362572 # number of ReadReq misses 127210585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.inst 2362737 # number of WriteReq misses 127310585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 2362737 # number of WriteReq misses 127410585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_misses::cpu1.inst 497251 # number of WriteInvalidateReq misses 127510585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_misses::total 497251 # number of WriteInvalidateReq misses 127610585Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 139927 # number of LoadLockedReq misses 127710585Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 139927 # number of LoadLockedReq misses 127810585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.inst 188742 # number of StoreCondReq misses 127910585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 188742 # number of StoreCondReq misses 128010585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.inst 6725309 # number of demand (read+write) misses 128110585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 6725309 # number of demand (read+write) misses 128210585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.inst 6725309 # number of overall misses 128310585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 6725309 # number of overall misses 128410585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 63153941750 # number of ReadReq miss cycles 128510585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 63153941750 # number of ReadReq miss cycles 128610585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 37295206516 # number of WriteReq miss cycles 128710585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 37295206516 # number of WriteReq miss cycles 128810585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.inst 9223332559 # number of WriteInvalidateReq miss cycles 128910585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_miss_latency::total 9223332559 # number of WriteInvalidateReq miss cycles 129010585Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 1921743254 # number of LoadLockedReq miss cycles 129110585Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 1921743254 # number of LoadLockedReq miss cycles 129210585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 3886161820 # number of StoreCondReq miss cycles 129310585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 3886161820 # number of StoreCondReq miss cycles 129410585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 3267000 # number of StoreCondFailReq miss cycles 129510585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::total 3267000 # number of StoreCondFailReq miss cycles 129610585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::cpu1.inst 100449148266 # number of demand (read+write) miss cycles 129710585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::total 100449148266 # number of demand (read+write) miss cycles 129810585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::cpu1.inst 100449148266 # number of overall miss cycles 129910585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::total 100449148266 # number of overall miss cycles 130010585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.inst 91914952 # number of ReadReq accesses(hits+misses) 130110585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 91914952 # number of ReadReq accesses(hits+misses) 130210585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.inst 79577330 # number of WriteReq accesses(hits+misses) 130310585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 79577330 # number of WriteReq accesses(hits+misses) 130410585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.inst 709236 # number of WriteInvalidateReq accesses(hits+misses) 130510585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_accesses::total 709236 # number of WriteInvalidateReq accesses(hits+misses) 130610585Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 2134889 # number of LoadLockedReq accesses(hits+misses) 130710585Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 2134889 # number of LoadLockedReq accesses(hits+misses) 130810585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 2133381 # number of StoreCondReq accesses(hits+misses) 130910585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 2133381 # number of StoreCondReq accesses(hits+misses) 131010585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.inst 171492282 # number of demand (read+write) accesses 131110585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 171492282 # number of demand (read+write) accesses 131210585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.inst 171492282 # number of overall (read+write) accesses 131310585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 171492282 # number of overall (read+write) accesses 131410585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.047463 # miss rate for ReadReq accesses 131510585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.047463 # miss rate for ReadReq accesses 131610585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.029691 # miss rate for WriteReq accesses 131710585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.029691 # miss rate for WriteReq accesses 131810585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.inst 0.701108 # miss rate for WriteInvalidateReq accesses 131910585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.701108 # miss rate for WriteInvalidateReq accesses 132010585Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.065543 # miss rate for LoadLockedReq accesses 132110585Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.065543 # miss rate for LoadLockedReq accesses 132210585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.088471 # miss rate for StoreCondReq accesses 132310585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.088471 # miss rate for StoreCondReq accesses 132410585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.inst 0.039216 # miss rate for demand accesses 132510585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.039216 # miss rate for demand accesses 132610585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.inst 0.039216 # miss rate for overall accesses 132710585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.039216 # miss rate for overall accesses 132810585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14476.309331 # average ReadReq miss latency 132910585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 14476.309331 # average ReadReq miss latency 133010585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 15784.747315 # average WriteReq miss latency 133110585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 15784.747315 # average WriteReq miss latency 133210585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.inst 18548.645571 # average WriteInvalidateReq miss latency 133310585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 18548.645571 # average WriteInvalidateReq miss latency 133410585Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 13733.898776 # average LoadLockedReq miss latency 133510585Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13733.898776 # average LoadLockedReq miss latency 133610585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 20589.809475 # average StoreCondReq miss latency 133710585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20589.809475 # average StoreCondReq miss latency 133810585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency 133910585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 134010585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 14935.990044 # average overall miss latency 134110585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 14935.990044 # average overall miss latency 134210585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 14935.990044 # average overall miss latency 134310585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 14935.990044 # average overall miss latency 134410585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 134510585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 134610585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 134710585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 134810585Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 134910585Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 135010585Sandreas.hansson@arm.comsystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 135110585Sandreas.hansson@arm.comsystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 135210585Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 3739270 # number of writebacks 135310585Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 3739270 # number of writebacks 135410585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 400087 # number of ReadReq MSHR hits 135510585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 400087 # number of ReadReq MSHR hits 135610585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 959724 # number of WriteReq MSHR hits 135710585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 959724 # number of WriteReq MSHR hits 135810585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.inst 47 # number of WriteInvalidateReq MSHR hits 135910585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 47 # number of WriteInvalidateReq MSHR hits 136010585Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst 67 # number of LoadLockedReq MSHR hits 136110585Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 67 # number of LoadLockedReq MSHR hits 136210585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.inst 75 # number of StoreCondReq MSHR hits 136310585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_hits::total 75 # number of StoreCondReq MSHR hits 136410585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::cpu1.inst 1359811 # number of demand (read+write) MSHR hits 136510585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::total 1359811 # number of demand (read+write) MSHR hits 136610585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::cpu1.inst 1359811 # number of overall MSHR hits 136710585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::total 1359811 # number of overall MSHR hits 136810585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 3962485 # number of ReadReq MSHR misses 136910585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 3962485 # number of ReadReq MSHR misses 137010585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 1403013 # number of WriteReq MSHR misses 137110585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 1403013 # number of WriteReq MSHR misses 137210585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.inst 497204 # number of WriteInvalidateReq MSHR misses 137310585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 497204 # number of WriteInvalidateReq MSHR misses 137410585Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 139860 # number of LoadLockedReq MSHR misses 137510585Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 139860 # number of LoadLockedReq MSHR misses 137610585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 188667 # number of StoreCondReq MSHR misses 137710585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 188667 # number of StoreCondReq MSHR misses 137810585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.inst 5365498 # number of demand (read+write) MSHR misses 137910585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 5365498 # number of demand (read+write) MSHR misses 138010585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.inst 5365498 # number of overall MSHR misses 138110585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 5365498 # number of overall MSHR misses 138210585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 49100377691 # number of ReadReq MSHR miss cycles 138310585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 49100377691 # number of ReadReq MSHR miss cycles 138410585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 20233474919 # number of WriteReq MSHR miss cycles 138510585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 20233474919 # number of WriteReq MSHR miss cycles 138610585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.inst 8220345441 # number of WriteInvalidateReq MSHR miss cycles 138710585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 8220345441 # number of WriteInvalidateReq MSHR miss cycles 138810585Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 1640188222 # number of LoadLockedReq MSHR miss cycles 138910585Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1640188222 # number of LoadLockedReq MSHR miss cycles 139010585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 3498307132 # number of StoreCondReq MSHR miss cycles 139110585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3498307132 # number of StoreCondReq MSHR miss cycles 139210585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 2504000 # number of StoreCondFailReq MSHR miss cycles 139310585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2504000 # number of StoreCondFailReq MSHR miss cycles 139410585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 69333852610 # number of demand (read+write) MSHR miss cycles 139510585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 69333852610 # number of demand (read+write) MSHR miss cycles 139610585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 69333852610 # number of overall MSHR miss cycles 139710585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 69333852610 # number of overall MSHR miss cycles 139810585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3411173732 # number of ReadReq MSHR uncacheable cycles 139910585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3411173732 # number of ReadReq MSHR uncacheable cycles 140010585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 3123925989 # number of WriteReq MSHR uncacheable cycles 140110585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3123925989 # number of WriteReq MSHR uncacheable cycles 140210585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 6535099721 # number of overall MSHR uncacheable cycles 140310585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 6535099721 # number of overall MSHR uncacheable cycles 140410585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.043110 # mshr miss rate for ReadReq accesses 140510585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043110 # mshr miss rate for ReadReq accesses 140610585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.017631 # mshr miss rate for WriteReq accesses 140710585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017631 # mshr miss rate for WriteReq accesses 140810585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.inst 0.701042 # mshr miss rate for WriteInvalidateReq accesses 140910585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.701042 # mshr miss rate for WriteInvalidateReq accesses 141010585Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.065512 # mshr miss rate for LoadLockedReq accesses 141110585Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.065512 # mshr miss rate for LoadLockedReq accesses 141210585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.088436 # mshr miss rate for StoreCondReq accesses 141310585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.088436 # mshr miss rate for StoreCondReq accesses 141410585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.031287 # mshr miss rate for demand accesses 141510585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.031287 # mshr miss rate for demand accesses 141610585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.031287 # mshr miss rate for overall accesses 141710585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.031287 # mshr miss rate for overall accesses 141810585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12391.309416 # average ReadReq mshr miss latency 141910585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12391.309416 # average ReadReq mshr miss latency 142010585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 14421.445075 # average WriteReq mshr miss latency 142110585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14421.445075 # average WriteReq mshr miss latency 142210585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 16533.144225 # average WriteInvalidateReq mshr miss latency 142310585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 16533.144225 # average WriteInvalidateReq mshr miss latency 142410585Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 11727.357515 # average LoadLockedReq mshr miss latency 142510585Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11727.357515 # average LoadLockedReq mshr miss latency 142610585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 18542.231190 # average StoreCondReq mshr miss latency 142710585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18542.231190 # average StoreCondReq mshr miss latency 142810585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency 142910585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 143010585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 12922.165400 # average overall mshr miss latency 143110585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 12922.165400 # average overall mshr miss latency 143210585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 12922.165400 # average overall mshr miss latency 143310585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 12922.165400 # average overall mshr miss latency 143410585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 143510585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 143610585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 143710585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 143810585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 143910585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 144010585Sandreas.hansson@arm.comsystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 144110585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 10003641 # number of replacements 144210585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 507.113561 # Cycle average of tags in use 144310585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 252141010 # Total number of references to valid blocks. 144410585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 10004153 # Sample count of references to valid blocks. 144510585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 25.203634 # Average number of references to valid blocks. 144610585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 8364450905000 # Cycle when the warmup percentage was hit. 144710585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 507.113561 # Average occupied blocks per requestor 144810585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.990456 # Average percentage of cache occupancy 144910585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.990456 # Average percentage of cache occupancy 145010585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 145110585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 148 # Occupied blocks per task id 145210585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id 145310585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id 145410585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 145510585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 534294484 # Number of tag accesses 145610585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 534294484 # Number of data accesses 145710585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 252141010 # number of ReadReq hits 145810585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 252141010 # number of ReadReq hits 145910585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 252141010 # number of demand (read+write) hits 146010585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 252141010 # number of demand (read+write) hits 146110585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 252141010 # number of overall hits 146210585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 252141010 # number of overall hits 146310585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 10004155 # number of ReadReq misses 146410585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 10004155 # number of ReadReq misses 146510585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 10004155 # number of demand (read+write) misses 146610585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 10004155 # number of demand (read+write) misses 146710585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 10004155 # number of overall misses 146810585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 10004155 # number of overall misses 146910585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 85019530358 # number of ReadReq miss cycles 147010585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 85019530358 # number of ReadReq miss cycles 147110585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 85019530358 # number of demand (read+write) miss cycles 147210585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::total 85019530358 # number of demand (read+write) miss cycles 147310585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 85019530358 # number of overall miss cycles 147410585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::total 85019530358 # number of overall miss cycles 147510585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 262145165 # number of ReadReq accesses(hits+misses) 147610585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 262145165 # number of ReadReq accesses(hits+misses) 147710585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 262145165 # number of demand (read+write) accesses 147810585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 262145165 # number of demand (read+write) accesses 147910585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 262145165 # number of overall (read+write) accesses 148010585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 262145165 # number of overall (read+write) accesses 148110585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.038163 # miss rate for ReadReq accesses 148210585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.038163 # miss rate for ReadReq accesses 148310585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.038163 # miss rate for demand accesses 148410585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.038163 # miss rate for demand accesses 148510585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.038163 # miss rate for overall accesses 148610585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.038163 # miss rate for overall accesses 148710585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8498.421941 # average ReadReq miss latency 148810585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 8498.421941 # average ReadReq miss latency 148910585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8498.421941 # average overall miss latency 149010585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 8498.421941 # average overall miss latency 149110585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8498.421941 # average overall miss latency 149210585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 8498.421941 # average overall miss latency 149310585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 149410585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 149510585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 149610585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 149710585Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 149810585Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 149910585Sandreas.hansson@arm.comsystem.cpu1.icache.fast_writes 0 # number of fast writes performed 150010585Sandreas.hansson@arm.comsystem.cpu1.icache.cache_copies 0 # number of cache copies performed 150110585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 10004155 # number of ReadReq MSHR misses 150210585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 10004155 # number of ReadReq MSHR misses 150310585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 10004155 # number of demand (read+write) MSHR misses 150410585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::total 10004155 # number of demand (read+write) MSHR misses 150510585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 10004155 # number of overall MSHR misses 150610585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::total 10004155 # number of overall MSHR misses 150710585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 70001431618 # number of ReadReq MSHR miss cycles 150810585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 70001431618 # number of ReadReq MSHR miss cycles 150910585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 70001431618 # number of demand (read+write) MSHR miss cycles 151010585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 70001431618 # number of demand (read+write) MSHR miss cycles 151110585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 70001431618 # number of overall MSHR miss cycles 151210585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 70001431618 # number of overall MSHR miss cycles 151310585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8751000 # number of ReadReq MSHR uncacheable cycles 151410585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8751000 # number of ReadReq MSHR uncacheable cycles 151510585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8751000 # number of overall MSHR uncacheable cycles 151610585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::total 8751000 # number of overall MSHR uncacheable cycles 151710585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.038163 # mshr miss rate for ReadReq accesses 151810585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.038163 # mshr miss rate for ReadReq accesses 151910585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.038163 # mshr miss rate for demand accesses 152010585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.038163 # mshr miss rate for demand accesses 152110585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.038163 # mshr miss rate for overall accesses 152210585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.038163 # mshr miss rate for overall accesses 152310585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6997.235810 # average ReadReq mshr miss latency 152410585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6997.235810 # average ReadReq mshr miss latency 152510585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6997.235810 # average overall mshr miss latency 152610585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 6997.235810 # average overall mshr miss latency 152710585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6997.235810 # average overall mshr miss latency 152810585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 6997.235810 # average overall mshr miss latency 152910585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 153010585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 153110585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 153210585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 153310585Sandreas.hansson@arm.comsystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 153410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 91266400 # number of hwpf identified 153510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 2590593 # number of hwpf that were already in mshr 153610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 83739964 # number of hwpf that were already in the cache 153710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 1124296 # number of hwpf that were already in the prefetch queue 153810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 153910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 159143 # number of hwpf removed because MSHR allocated 154010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 3652396 # number of hwpf issued 154110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 7945944 # number of hwpf spanning a virtual page 154210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 154310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.replacements 3964575 # number of replacements 154410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tagsinuse 13771.716542 # Cycle average of tags in use 154510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.total_refs 17209014 # Total number of references to valid blocks. 154610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.sampled_refs 3980703 # Sample count of references to valid blocks. 154710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.avg_refs 4.323109 # Average number of references to valid blocks. 154810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 9604482251250 # Cycle when the warmup percentage was hit. 154910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 4186.861890 # Average occupied blocks per requestor 155010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 66.243250 # Average occupied blocks per requestor 155110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 63.010570 # Average occupied blocks per requestor 155210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2902.209445 # Average occupied blocks per requestor 155310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6553.391387 # Average occupied blocks per requestor 155410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.255546 # Average percentage of cache occupancy 155510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004043 # Average percentage of cache occupancy 155610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003846 # Average percentage of cache occupancy 155710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.177137 # Average percentage of cache occupancy 155810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.399987 # Average percentage of cache occupancy 155910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.840559 # Average percentage of cache occupancy 156010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1022 9777 # Occupied blocks per task id 156110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 42 # Occupied blocks per task id 156210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 6309 # Occupied blocks per task id 156310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::0 89 # Occupied blocks per task id 156410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::1 734 # Occupied blocks per task id 156510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::2 4083 # Occupied blocks per task id 156610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::3 3317 # Occupied blocks per task id 156710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1554 # Occupied blocks per task id 156810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 156910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 36 # Occupied blocks per task id 157010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 157110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id 157210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id 157310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 691 # Occupied blocks per task id 157410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 3097 # Occupied blocks per task id 157510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1911 # Occupied blocks per task id 157610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 531 # Occupied blocks per task id 157710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1022 0.596741 # Percentage of cache occupancy per task id 157810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002563 # Percentage of cache occupancy per task id 157910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.385071 # Percentage of cache occupancy per task id 158010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tag_accesses 336896441 # Number of tag accesses 158110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.data_accesses 336896441 # Number of data accesses 158210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 545727 # number of ReadReq hits 158310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 151675 # number of ReadReq hits 158410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.inst 13043643 # number of ReadReq hits 158510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 13741045 # number of ReadReq hits 158610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_hits::writebacks 3739269 # number of Writeback hits 158710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_hits::total 3739269 # number of Writeback hits 158810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.inst 314994 # number of WriteInvalidateReq hits 158910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_hits::total 314994 # number of WriteInvalidateReq hits 159010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 88927 # number of UpgradeReq hits 159110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::total 88927 # number of UpgradeReq hits 159210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 41659 # number of SCUpgradeReq hits 159310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_hits::total 41659 # number of SCUpgradeReq hits 159410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.inst 944385 # number of ReadExReq hits 159510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 944385 # number of ReadExReq hits 159610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 545727 # number of demand (read+write) hits 159710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 151675 # number of demand (read+write) hits 159810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 13988028 # number of demand (read+write) hits 159910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::total 14685430 # number of demand (read+write) hits 160010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 545727 # number of overall hits 160110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 151675 # number of overall hits 160210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 13988028 # number of overall hits 160310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::total 14685430 # number of overall hits 160410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 14704 # number of ReadReq misses 160510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10320 # number of ReadReq misses 160610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.inst 1062508 # number of ReadReq misses 160710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 1087532 # number of ReadReq misses 160810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.inst 180857 # number of WriteInvalidateReq misses 160910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_misses::total 180857 # number of WriteInvalidateReq misses 161010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 132678 # number of UpgradeReq misses 161110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 132678 # number of UpgradeReq misses 161210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 147002 # number of SCUpgradeReq misses 161310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 147002 # number of SCUpgradeReq misses 161410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.inst 6 # number of SCUpgradeFailReq misses 161510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses 161610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.inst 238730 # number of ReadExReq misses 161710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 238730 # number of ReadExReq misses 161810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 14704 # number of demand (read+write) misses 161910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 10320 # number of demand (read+write) misses 162010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 1301238 # number of demand (read+write) misses 162110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::total 1326262 # number of demand (read+write) misses 162210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 14704 # number of overall misses 162310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 10320 # number of overall misses 162410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 1301238 # number of overall misses 162510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::total 1326262 # number of overall misses 162610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 525735124 # number of ReadReq miss cycles 162710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 414121710 # number of ReadReq miss cycles 162810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 33089400106 # number of ReadReq miss cycles 162910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::total 34029256940 # number of ReadReq miss cycles 163010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.inst 5173608568 # number of WriteInvalidateReq miss cycles 163110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 5173608568 # number of WriteInvalidateReq miss cycles 163210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 2603383383 # number of UpgradeReq miss cycles 163310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::total 2603383383 # number of UpgradeReq miss cycles 163410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 2990869344 # number of SCUpgradeReq miss cycles 163510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::total 2990869344 # number of SCUpgradeReq miss cycles 163610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 2444000 # number of SCUpgradeFailReq miss cycles 163710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2444000 # number of SCUpgradeFailReq miss cycles 163810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 9524400999 # number of ReadExReq miss cycles 163910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::total 9524400999 # number of ReadExReq miss cycles 164010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 525735124 # number of demand (read+write) miss cycles 164110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 414121710 # number of demand (read+write) miss cycles 164210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.inst 42613801105 # number of demand (read+write) miss cycles 164310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::total 43553657939 # number of demand (read+write) miss cycles 164410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 525735124 # number of overall miss cycles 164510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 414121710 # number of overall miss cycles 164610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.inst 42613801105 # number of overall miss cycles 164710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::total 43553657939 # number of overall miss cycles 164810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 560431 # number of ReadReq accesses(hits+misses) 164910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 161995 # number of ReadReq accesses(hits+misses) 165010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.inst 14106151 # number of ReadReq accesses(hits+misses) 165110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 14828577 # number of ReadReq accesses(hits+misses) 165210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_accesses::writebacks 3739269 # number of Writeback accesses(hits+misses) 165310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_accesses::total 3739269 # number of Writeback accesses(hits+misses) 165410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.inst 495851 # number of WriteInvalidateReq accesses(hits+misses) 165510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_accesses::total 495851 # number of WriteInvalidateReq accesses(hits+misses) 165610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 221605 # number of UpgradeReq accesses(hits+misses) 165710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 221605 # number of UpgradeReq accesses(hits+misses) 165810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 188661 # number of SCUpgradeReq accesses(hits+misses) 165910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 188661 # number of SCUpgradeReq accesses(hits+misses) 166010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.inst 6 # number of SCUpgradeFailReq accesses(hits+misses) 166110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) 166210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 1183115 # number of ReadExReq accesses(hits+misses) 166310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 1183115 # number of ReadExReq accesses(hits+misses) 166410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 560431 # number of demand (read+write) accesses 166510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 161995 # number of demand (read+write) accesses 166610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 15289266 # number of demand (read+write) accesses 166710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::total 16011692 # number of demand (read+write) accesses 166810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 560431 # number of overall (read+write) accesses 166910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 161995 # number of overall (read+write) accesses 167010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 15289266 # number of overall (read+write) accesses 167110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::total 16011692 # number of overall (read+write) accesses 167210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.026237 # miss rate for ReadReq accesses 167310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.063706 # miss rate for ReadReq accesses 167410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.075322 # miss rate for ReadReq accesses 167510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.073340 # miss rate for ReadReq accesses 167610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.inst 0.364741 # miss rate for WriteInvalidateReq accesses 167710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.364741 # miss rate for WriteInvalidateReq accesses 167810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.598714 # miss rate for UpgradeReq accesses 167910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 0.598714 # miss rate for UpgradeReq accesses 168010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.779186 # miss rate for SCUpgradeReq accesses 168110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.779186 # miss rate for SCUpgradeReq accesses 168210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.inst 1 # miss rate for SCUpgradeFailReq accesses 168310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 168410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.201781 # miss rate for ReadExReq accesses 168510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.201781 # miss rate for ReadExReq accesses 168610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.026237 # miss rate for demand accesses 168710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.063706 # miss rate for demand accesses 168810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.085108 # miss rate for demand accesses 168910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.082831 # miss rate for demand accesses 169010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.026237 # miss rate for overall accesses 169110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.063706 # miss rate for overall accesses 169210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.085108 # miss rate for overall accesses 169310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.082831 # miss rate for overall accesses 169410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 35754.565016 # average ReadReq miss latency 169510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 40128.072674 # average ReadReq miss latency 169610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 31142.730319 # average ReadReq miss latency 169710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::total 31290.350022 # average ReadReq miss latency 169810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.inst 28606.073130 # average WriteInvalidateReq miss latency 169910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 28606.073130 # average WriteInvalidateReq miss latency 170010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 19621.816601 # average UpgradeReq miss latency 170110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19621.816601 # average UpgradeReq miss latency 170210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 20345.773146 # average SCUpgradeReq miss latency 170310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20345.773146 # average SCUpgradeReq miss latency 170410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst 407333.333333 # average SCUpgradeFailReq miss latency 170510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 407333.333333 # average SCUpgradeFailReq miss latency 170610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 39896.121137 # average ReadExReq miss latency 170710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39896.121137 # average ReadExReq miss latency 170810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 35754.565016 # average overall miss latency 170910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 40128.072674 # average overall miss latency 171010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 32748.660203 # average overall miss latency 171110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::total 32839.407251 # average overall miss latency 171210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 35754.565016 # average overall miss latency 171310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 40128.072674 # average overall miss latency 171410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 32748.660203 # average overall miss latency 171510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::total 32839.407251 # average overall miss latency 171610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_mshrs 95890 # number of cycles access was blocked 171710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 171810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_mshrs 1623 # number of cycles access was blocked 171910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 172010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs 59.081947 # average number of cycles each access was blocked 172110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 172210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.fast_writes 0 # number of fast writes performed 172310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.cache_copies 0 # number of cache copies performed 172410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::writebacks 1340101 # number of writebacks 172510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::total 1340101 # number of writebacks 172610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits 172710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 3 # number of ReadReq MSHR hits 172810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 83863 # number of ReadReq MSHR hits 172910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::total 83867 # number of ReadReq MSHR hits 173010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.inst 117019 # number of WriteInvalidateReq MSHR hits 173110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total 117019 # number of WriteInvalidateReq MSHR hits 173210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 10752 # number of ReadExReq MSHR hits 173310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::total 10752 # number of ReadExReq MSHR hits 173410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits 173510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 3 # number of demand (read+write) MSHR hits 173610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.inst 94615 # number of demand (read+write) MSHR hits 173710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::total 94619 # number of demand (read+write) MSHR hits 173810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits 173910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 3 # number of overall MSHR hits 174010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.inst 94615 # number of overall MSHR hits 174110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::total 94619 # number of overall MSHR hits 174210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 14703 # number of ReadReq MSHR misses 174310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 10317 # number of ReadReq MSHR misses 174410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 978645 # number of ReadReq MSHR misses 174510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::total 1003665 # number of ReadReq MSHR misses 174610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 3652327 # number of HardPFReq MSHR misses 174710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::total 3652327 # number of HardPFReq MSHR misses 174810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.inst 63838 # number of WriteInvalidateReq MSHR misses 174910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 63838 # number of WriteInvalidateReq MSHR misses 175010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 132678 # number of UpgradeReq MSHR misses 175110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::total 132678 # number of UpgradeReq MSHR misses 175210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 147002 # number of SCUpgradeReq MSHR misses 175310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 147002 # number of SCUpgradeReq MSHR misses 175410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.inst 6 # number of SCUpgradeFailReq MSHR misses 175510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses 175610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 227978 # number of ReadExReq MSHR misses 175710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::total 227978 # number of ReadExReq MSHR misses 175810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 14703 # number of demand (read+write) MSHR misses 175910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 10317 # number of demand (read+write) MSHR misses 176010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.inst 1206623 # number of demand (read+write) MSHR misses 176110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::total 1231643 # number of demand (read+write) MSHR misses 176210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 14703 # number of overall MSHR misses 176310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 10317 # number of overall MSHR misses 176410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.inst 1206623 # number of overall MSHR misses 176510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 3652327 # number of overall MSHR misses 176610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::total 4883970 # number of overall MSHR misses 176710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 421971770 # number of ReadReq MSHR miss cycles 176810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 341099282 # number of ReadReq MSHR miss cycles 176910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 24526546457 # number of ReadReq MSHR miss cycles 177010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::total 25289617509 # number of ReadReq MSHR miss cycles 177110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 110063206845 # number of HardPFReq MSHR miss cycles 177210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 110063206845 # number of HardPFReq MSHR miss cycles 177310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.inst 1132471294 # number of WriteInvalidateReq MSHR miss cycles 177410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 1132471294 # number of WriteInvalidateReq MSHR miss cycles 177510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 2172031189 # number of UpgradeReq MSHR miss cycles 177610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2172031189 # number of UpgradeReq MSHR miss cycles 177710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 2030926339 # number of SCUpgradeReq MSHR miss cycles 177810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2030926339 # number of SCUpgradeReq MSHR miss cycles 177910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 2024000 # number of SCUpgradeFailReq MSHR miss cycles 178010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2024000 # number of SCUpgradeFailReq MSHR miss cycles 178110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 6846769063 # number of ReadExReq MSHR miss cycles 178210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 6846769063 # number of ReadExReq MSHR miss cycles 178310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 421971770 # number of demand (read+write) MSHR miss cycles 178410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 341099282 # number of demand (read+write) MSHR miss cycles 178510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 31373315520 # number of demand (read+write) MSHR miss cycles 178610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::total 32136386572 # number of demand (read+write) MSHR miss cycles 178710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 421971770 # number of overall MSHR miss cycles 178810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 341099282 # number of overall MSHR miss cycles 178910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 31373315520 # number of overall MSHR miss cycles 179010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 110063206845 # number of overall MSHR miss cycles 179110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::total 142199593417 # number of overall MSHR miss cycles 179210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3254469267 # number of ReadReq MSHR uncacheable cycles 179310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3254469267 # number of ReadReq MSHR uncacheable cycles 179410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 2984537511 # number of WriteReq MSHR uncacheable cycles 179510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2984537511 # number of WriteReq MSHR uncacheable cycles 179610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 6239006778 # number of overall MSHR uncacheable cycles 179710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::total 6239006778 # number of overall MSHR uncacheable cycles 179810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.026235 # mshr miss rate for ReadReq accesses 179910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.063687 # mshr miss rate for ReadReq accesses 180010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.069377 # mshr miss rate for ReadReq accesses 180110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.067685 # mshr miss rate for ReadReq accesses 180210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 180310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 180410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.inst 0.128744 # mshr miss rate for WriteInvalidateReq accesses 180510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.128744 # mshr miss rate for WriteInvalidateReq accesses 180610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.598714 # mshr miss rate for UpgradeReq accesses 180710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.598714 # mshr miss rate for UpgradeReq accesses 180810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.779186 # mshr miss rate for SCUpgradeReq accesses 180910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.779186 # mshr miss rate for SCUpgradeReq accesses 181010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.inst 1 # mshr miss rate for SCUpgradeFailReq accesses 181110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 181210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.192693 # mshr miss rate for ReadExReq accesses 181310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.192693 # mshr miss rate for ReadExReq accesses 181410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.026235 # mshr miss rate for demand accesses 181510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.063687 # mshr miss rate for demand accesses 181610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.078920 # mshr miss rate for demand accesses 181710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::total 0.076921 # mshr miss rate for demand accesses 181810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.026235 # mshr miss rate for overall accesses 181910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.063687 # mshr miss rate for overall accesses 182010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.078920 # mshr miss rate for overall accesses 182110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 182210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::total 0.305025 # mshr miss rate for overall accesses 182310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 28699.705502 # average ReadReq mshr miss latency 182410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 33061.867016 # average ReadReq mshr miss latency 182510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 25061.739913 # average ReadReq mshr miss latency 182610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25197.269516 # average ReadReq mshr miss latency 182710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30135.091093 # average HardPFReq mshr miss latency 182810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 30135.091093 # average HardPFReq mshr miss latency 182910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 17739.767756 # average WriteInvalidateReq mshr miss latency 183010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 17739.767756 # average WriteInvalidateReq mshr miss latency 183110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 16370.695888 # average UpgradeReq mshr miss latency 183210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16370.695888 # average UpgradeReq mshr miss latency 183310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13815.637468 # average SCUpgradeReq mshr miss latency 183410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13815.637468 # average SCUpgradeReq mshr miss latency 183510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst 337333.333333 # average SCUpgradeFailReq mshr miss latency 183610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 337333.333333 # average SCUpgradeFailReq mshr miss latency 183710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 30032.586754 # average ReadExReq mshr miss latency 183810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30032.586754 # average ReadExReq mshr miss latency 183910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 28699.705502 # average overall mshr miss latency 184010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 33061.867016 # average overall mshr miss latency 184110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26000.926155 # average overall mshr miss latency 184210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26092.290194 # average overall mshr miss latency 184310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 28699.705502 # average overall mshr miss latency 184410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 33061.867016 # average overall mshr miss latency 184510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26000.926155 # average overall mshr miss latency 184610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30135.091093 # average overall mshr miss latency 184710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29115.574710 # average overall mshr miss latency 184810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 184910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 185010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 185110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 185210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 185310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 185410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 185510585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 19283354 # Transaction distribution 185610585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 15081139 # Transaction distribution 185710585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 18583 # Transaction distribution 185810585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 18583 # Transaction distribution 185910585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::Writeback 3739269 # Transaction distribution 186010585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFReq 5170827 # Transaction distribution 186110585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 625737 # Transaction distribution 186210585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 495851 # Transaction distribution 186310585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 477449 # Transaction distribution 186410585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 330499 # Transaction distribution 186510585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 473092 # Transaction distribution 186610585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution 186710585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeFailResp 117 # Transaction distribution 186810585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 1314338 # Transaction distribution 186910585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 1188302 # Transaction distribution 187010585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 20008489 # Packet count per connected master and slave (bytes) 187110585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16359278 # Packet count per connected master and slave (bytes) 187210585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 359533 # Packet count per connected master and slave (bytes) 187310585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1226091 # Packet count per connected master and slave (bytes) 187410585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count::total 37953391 # Packet count per connected master and slave (bytes) 187510585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 640271616 # Cumulative packet size per connected master and slave (bytes) 187610585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 615594373 # Cumulative packet size per connected master and slave (bytes) 187710585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1295960 # Cumulative packet size per connected master and slave (bytes) 187810585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4483448 # Cumulative packet size per connected master and slave (bytes) 187910585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size::total 1261645397 # Cumulative packet size per connected master and slave (bytes) 188010585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoops 10423087 # Total snoops (count) 188110585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 30921485 # Request fanout histogram 188210585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 5.327379 # Request fanout histogram 188310585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.469257 # Request fanout histogram 188410585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 188510585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 188610585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 188710585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 188810585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 188910585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 189010585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::5 20798445 67.26% 67.26% # Request fanout histogram 189110585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::6 10123040 32.74% 100.00% # Request fanout histogram 189210585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 189310585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 189410585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 189510585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 30921485 # Request fanout histogram 189610585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.reqLayer0.occupancy 14664539498 # Layer occupancy (ticks) 189710585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 189810585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopLayer0.occupancy 176010242 # Layer occupancy (ticks) 189910585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 190010585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer0.occupancy 15012316370 # Layer occupancy (ticks) 190110585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 190210585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer1.occupancy 8461463125 # Layer occupancy (ticks) 190310585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 190410585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer2.occupancy 197959664 # Layer occupancy (ticks) 190510585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 190610585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer3.occupancy 666269864 # Layer occupancy (ticks) 190710585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 190810585Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 40348 # Transaction distribution 190910585Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 40348 # Transaction distribution 191010585Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 136740 # Transaction distribution 191110585Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 30012 # Transaction distribution 191210585Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution 191310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48044 # Packet count per connected master and slave (bytes) 191410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 191510585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 191610585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 191710585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 191810585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 191910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 192010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 192110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 192210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 192310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 192410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 192510585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 192610585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 192710585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 192810585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122926 # Packet count per connected master and slave (bytes) 192910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231170 # Packet count per connected master and slave (bytes) 193010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231170 # Packet count per connected master and slave (bytes) 193110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 193210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 193310585Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 354176 # Packet count per connected master and slave (bytes) 193410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48064 # Cumulative packet size per connected master and slave (bytes) 193510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 193610585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 193710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 193810585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 193910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 194010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 194110585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 194210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 194310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 194410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 194510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 194610585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 194710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 194810585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 194910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 156056 # Cumulative packet size per connected master and slave (bytes) 195010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338696 # Cumulative packet size per connected master and slave (bytes) 195110585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7338696 # Cumulative packet size per connected master and slave (bytes) 195210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 195310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 195410585Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 7496838 # Cumulative packet size per connected master and slave (bytes) 195510585Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 36517000 # Layer occupancy (ticks) 195610585Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 195710585Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 195810585Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 195910585Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 196010585Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 196110585Sandreas.hansson@arm.comsystem.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 196210585Sandreas.hansson@arm.comsystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 196310585Sandreas.hansson@arm.comsystem.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 196410585Sandreas.hansson@arm.comsystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 196510585Sandreas.hansson@arm.comsystem.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 196610585Sandreas.hansson@arm.comsystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 196710585Sandreas.hansson@arm.comsystem.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 196810585Sandreas.hansson@arm.comsystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 196910585Sandreas.hansson@arm.comsystem.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 197010585Sandreas.hansson@arm.comsystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 197110585Sandreas.hansson@arm.comsystem.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 197210585Sandreas.hansson@arm.comsystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 197310585Sandreas.hansson@arm.comsystem.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 197410585Sandreas.hansson@arm.comsystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 197510585Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) 197610585Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 197710585Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 197810585Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 197910585Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 198010585Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 198110585Sandreas.hansson@arm.comsystem.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 198210585Sandreas.hansson@arm.comsystem.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 198310585Sandreas.hansson@arm.comsystem.iobus.reqLayer27.occupancy 1042881499 # Layer occupancy (ticks) 198410585Sandreas.hansson@arm.comsystem.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 198510585Sandreas.hansson@arm.comsystem.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 198610585Sandreas.hansson@arm.comsystem.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 198710585Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 92917000 # Layer occupancy (ticks) 198810585Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 198910585Sandreas.hansson@arm.comsystem.iobus.respLayer3.occupancy 179159841 # Layer occupancy (ticks) 199010585Sandreas.hansson@arm.comsystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 199110585Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) 199210585Sandreas.hansson@arm.comsystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 199310585Sandreas.hansson@arm.comsystem.iocache.tags.replacements 115566 # number of replacements 199410585Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 11.298842 # Cycle average of tags in use 199510585Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 199610585Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 115582 # Sample count of references to valid blocks. 199710585Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 199810585Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 9120788284000 # Cycle when the warmup percentage was hit. 199910585Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 3.841658 # Average occupied blocks per requestor 200010585Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 7.457184 # Average occupied blocks per requestor 200110585Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.240104 # Average percentage of cache occupancy 200210585Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.466074 # Average percentage of cache occupancy 200310585Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.706178 # Average percentage of cache occupancy 200410585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 200510585Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 200610585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 200710585Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 1040622 # Number of tag accesses 200810585Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 1040622 # Number of data accesses 200910585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 201010585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ide 8857 # number of ReadReq misses 201110585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 8894 # number of ReadReq misses 201210585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 201310585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 201410585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses 201510585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses 201610585Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 201710585Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ide 8857 # number of demand (read+write) misses 201810585Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 8897 # number of demand (read+write) misses 201910585Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 202010585Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ide 8857 # number of overall misses 202110585Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 8897 # number of overall misses 202210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5707000 # number of ReadReq miss cycles 202310585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ide 1971462847 # number of ReadReq miss cycles 202410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 1977169847 # number of ReadReq miss cycles 202510585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::realview.ethernet 357000 # number of WriteReq miss cycles 202610585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::total 357000 # number of WriteReq miss cycles 202710585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_latency::realview.ide 28907198811 # number of WriteInvalidateReq miss cycles 202810585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_latency::total 28907198811 # number of WriteInvalidateReq miss cycles 202910585Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ethernet 6064000 # number of demand (read+write) miss cycles 203010585Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ide 1971462847 # number of demand (read+write) miss cycles 203110585Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 1977526847 # number of demand (read+write) miss cycles 203210585Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ethernet 6064000 # number of overall miss cycles 203310585Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ide 1971462847 # number of overall miss cycles 203410585Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 1977526847 # number of overall miss cycles 203510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 203610585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8857 # number of ReadReq accesses(hits+misses) 203710585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 8894 # number of ReadReq accesses(hits+misses) 203810585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 203910585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 204010585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) 204110585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) 204210585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 204310585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ide 8857 # number of demand (read+write) accesses 204410585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 8897 # number of demand (read+write) accesses 204510585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 204610585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 8857 # number of overall (read+write) accesses 204710585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 8897 # number of overall (read+write) accesses 204810585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 204910585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 205010585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 205110585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 205210585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 205310585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 205410585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 205510585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 205610585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 205710585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 205810585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 205910585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 206010585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 206110585Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243 # average ReadReq miss latency 206210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 222588.105115 # average ReadReq miss latency 206310585Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 222303.783112 # average ReadReq miss latency 206410585Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency 206510585Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency 206610585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270849.250534 # average WriteInvalidateReq miss latency 206710585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_avg_miss_latency::total 270849.250534 # average WriteInvalidateReq miss latency 206810585Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 151600 # average overall miss latency 206910585Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ide 222588.105115 # average overall miss latency 207010585Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 222268.949871 # average overall miss latency 207110585Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 151600 # average overall miss latency 207210585Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ide 222588.105115 # average overall miss latency 207310585Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 222268.949871 # average overall miss latency 207410585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 228015 # number of cycles access was blocked 207510585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 207610585Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 27566 # number of cycles access was blocked 207710585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 207810585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 8.271603 # average number of cycles each access was blocked 207910585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 208010585Sandreas.hansson@arm.comsystem.iocache.fast_writes 0 # number of fast writes performed 208110585Sandreas.hansson@arm.comsystem.iocache.cache_copies 0 # number of cache copies performed 208210585Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 106694 # number of writebacks 208310585Sandreas.hansson@arm.comsystem.iocache.writebacks::total 106694 # number of writebacks 208410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 208510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8857 # number of ReadReq MSHR misses 208610585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::total 8894 # number of ReadReq MSHR misses 208710585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 208810585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 208910585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses 209010585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses 209110585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 209210585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ide 8857 # number of demand (read+write) MSHR misses 209310585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::total 8897 # number of demand (read+write) MSHR misses 209410585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 209510585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ide 8857 # number of overall MSHR misses 209610585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::total 8897 # number of overall MSHR misses 209710585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3783000 # number of ReadReq MSHR miss cycles 209810585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1510755865 # number of ReadReq MSHR miss cycles 209910585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 1514538865 # number of ReadReq MSHR miss cycles 210010585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 210110585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 210210585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23356679475 # number of WriteInvalidateReq MSHR miss cycles 210310585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_miss_latency::total 23356679475 # number of WriteInvalidateReq MSHR miss cycles 210410585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3984000 # number of demand (read+write) MSHR miss cycles 210510585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ide 1510755865 # number of demand (read+write) MSHR miss cycles 210610585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 1514739865 # number of demand (read+write) MSHR miss cycles 210710585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3984000 # number of overall MSHR miss cycles 210810585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ide 1510755865 # number of overall MSHR miss cycles 210910585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 1514739865 # number of overall MSHR miss cycles 211010585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 211110585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 211210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 211310585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 211410585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 211510585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 211610585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 211710585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 211810585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 211910585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 212010585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 212110585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 212210585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 212310585Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243 # average ReadReq mshr miss latency 212410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 170571.961725 # average ReadReq mshr miss latency 212510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 170287.706881 # average ReadReq mshr miss latency 212610585Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 212710585Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 212810585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218843.035333 # average WriteInvalidateReq mshr miss latency 212910585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218843.035333 # average WriteInvalidateReq mshr miss latency 213010585Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency 213110585Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 170571.961725 # average overall mshr miss latency 213210585Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 170252.879060 # average overall mshr miss latency 213310585Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency 213410585Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 170571.961725 # average overall mshr miss latency 213510585Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 170252.879060 # average overall mshr miss latency 213610585Sandreas.hansson@arm.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 213710585Sandreas.hansson@arm.comsystem.l2c.tags.replacements 1797599 # number of replacements 213810585Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 64905.725288 # Cycle average of tags in use 213910585Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 8591301 # Total number of references to valid blocks. 214010585Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 1860596 # Sample count of references to valid blocks. 214110585Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 4.617499 # Average number of references to valid blocks. 214210585Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 6896032000 # Cycle when the warmup percentage was hit. 214310585Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 7600.616161 # Average occupied blocks per requestor 214410585Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 16.639535 # Average occupied blocks per requestor 214510585Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 9.409863 # Average occupied blocks per requestor 214610585Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 1890.006249 # Average occupied blocks per requestor 214710585Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 16961.129535 # Average occupied blocks per requestor 214810585Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 324.497512 # Average occupied blocks per requestor 214910585Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 441.216776 # Average occupied blocks per requestor 215010585Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 10554.786238 # Average occupied blocks per requestor 215110585Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 27107.423418 # Average occupied blocks per requestor 215210585Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.115976 # Average percentage of cache occupancy 215310585Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.000254 # Average percentage of cache occupancy 215410585Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.000144 # Average percentage of cache occupancy 215510585Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.028839 # Average percentage of cache occupancy 215610585Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.258806 # Average percentage of cache occupancy 215710585Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.004951 # Average percentage of cache occupancy 215810585Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.006732 # Average percentage of cache occupancy 215910585Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.161053 # Average percentage of cache occupancy 216010585Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.413626 # Average percentage of cache occupancy 216110585Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.990383 # Average percentage of cache occupancy 216210585Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1022 43530 # Occupied blocks per task id 216310585Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 179 # Occupied blocks per task id 216410585Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 19288 # Occupied blocks per task id 216510585Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::0 10 # Occupied blocks per task id 216610585Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::1 252 # Occupied blocks per task id 216710585Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::2 1656 # Occupied blocks per task id 216810585Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::3 6242 # Occupied blocks per task id 216910585Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::4 35370 # Occupied blocks per task id 217010585Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::1 6 # Occupied blocks per task id 217110585Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 173 # Occupied blocks per task id 217210585Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id 217310585Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id 217410585Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 846 # Occupied blocks per task id 217510585Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 1730 # Occupied blocks per task id 217610585Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 16555 # Occupied blocks per task id 217710585Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1022 0.664215 # Percentage of cache occupancy per task id 217810585Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.002731 # Percentage of cache occupancy per task id 217910585Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.294312 # Percentage of cache occupancy per task id 218010585Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 89688959 # Number of tag accesses 218110585Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 89688959 # Number of data accesses 218210585Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.dtb.walker 8987 # number of ReadReq hits 218310585Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.itb.walker 6604 # number of ReadReq hits 218410585Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.inst 578381 # number of ReadReq hits 218510585Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 2301852 # number of ReadReq hits 218610585Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.dtb.walker 8168 # number of ReadReq hits 218710585Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.itb.walker 5333 # number of ReadReq hits 218810585Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.inst 630016 # number of ReadReq hits 218910585Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 2353942 # number of ReadReq hits 219010585Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::total 5893283 # number of ReadReq hits 219110585Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::writebacks 2942617 # number of Writeback hits 219210585Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::total 2942617 # number of Writeback hits 219310585Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_hits::cpu0.inst 6235 # number of WriteInvalidateReq hits 219410585Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_hits::cpu1.inst 6750 # number of WriteInvalidateReq hits 219510585Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_hits::total 12985 # number of WriteInvalidateReq hits 219610585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.inst 39044 # number of UpgradeReq hits 219710585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.inst 35229 # number of UpgradeReq hits 219810585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 74273 # number of UpgradeReq hits 219910585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.inst 7514 # number of SCUpgradeReq hits 220010585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.inst 7779 # number of SCUpgradeReq hits 220110585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 15293 # number of SCUpgradeReq hits 220210585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.inst 64131 # number of ReadExReq hits 220310585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.inst 55187 # number of ReadExReq hits 220410585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 119318 # number of ReadExReq hits 220510585Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 8987 # number of demand (read+write) hits 220610585Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 6604 # number of demand (read+write) hits 220710585Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 642512 # number of demand (read+write) hits 220810585Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.l2cache.prefetcher 2301852 # number of demand (read+write) hits 220910585Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 8168 # number of demand (read+write) hits 221010585Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 5333 # number of demand (read+write) hits 221110585Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 685203 # number of demand (read+write) hits 221210585Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.l2cache.prefetcher 2353942 # number of demand (read+write) hits 221310585Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 6012601 # number of demand (read+write) hits 221410585Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 8987 # number of overall hits 221510585Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 6604 # number of overall hits 221610585Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 642512 # number of overall hits 221710585Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.l2cache.prefetcher 2301852 # number of overall hits 221810585Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 8168 # number of overall hits 221910585Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 5333 # number of overall hits 222010585Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 685203 # number of overall hits 222110585Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.l2cache.prefetcher 2353942 # number of overall hits 222210585Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 6012601 # number of overall hits 222310585Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.dtb.walker 1978 # number of ReadReq misses 222410585Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.itb.walker 1693 # number of ReadReq misses 222510585Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.inst 95514 # number of ReadReq misses 222610585Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 863521 # number of ReadReq misses 222710585Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.dtb.walker 2685 # number of ReadReq misses 222810585Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.itb.walker 2512 # number of ReadReq misses 222910585Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.inst 131326 # number of ReadReq misses 223010585Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 566480 # number of ReadReq misses 223110585Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::total 1665709 # number of ReadReq misses 223210585Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_misses::cpu0.inst 16918 # number of WriteInvalidateReq misses 223310585Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_misses::cpu1.inst 7174 # number of WriteInvalidateReq misses 223410585Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_misses::total 24092 # number of WriteInvalidateReq misses 223510585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.inst 36442 # number of UpgradeReq misses 223610585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.inst 33251 # number of UpgradeReq misses 223710585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 69693 # number of UpgradeReq misses 223810585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.inst 9494 # number of SCUpgradeReq misses 223910585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.inst 9010 # number of SCUpgradeReq misses 224010585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 18504 # number of SCUpgradeReq misses 224110585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.inst 45340 # number of ReadExReq misses 224210585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.inst 52041 # number of ReadExReq misses 224310585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 97381 # number of ReadExReq misses 224410585Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 1978 # number of demand (read+write) misses 224510585Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 1693 # number of demand (read+write) misses 224610585Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 140854 # number of demand (read+write) misses 224710585Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.l2cache.prefetcher 863521 # number of demand (read+write) misses 224810585Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 2685 # number of demand (read+write) misses 224910585Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.itb.walker 2512 # number of demand (read+write) misses 225010585Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 183367 # number of demand (read+write) misses 225110585Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.l2cache.prefetcher 566480 # number of demand (read+write) misses 225210585Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 1763090 # number of demand (read+write) misses 225310585Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 1978 # number of overall misses 225410585Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 1693 # number of overall misses 225510585Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 140854 # number of overall misses 225610585Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.l2cache.prefetcher 863521 # number of overall misses 225710585Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 2685 # number of overall misses 225810585Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.itb.walker 2512 # number of overall misses 225910585Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 183367 # number of overall misses 226010585Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.l2cache.prefetcher 566480 # number of overall misses 226110585Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 1763090 # number of overall misses 226210585Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu0.dtb.walker 165226748 # number of ReadReq miss cycles 226310585Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu0.itb.walker 144557248 # number of ReadReq miss cycles 226410585Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu0.inst 7974806913 # number of ReadReq miss cycles 226510585Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 129814567894 # number of ReadReq miss cycles 226610585Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu1.dtb.walker 222345248 # number of ReadReq miss cycles 226710585Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu1.itb.walker 209364000 # number of ReadReq miss cycles 226810585Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu1.inst 10644136699 # number of ReadReq miss cycles 226910585Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 70875583160 # number of ReadReq miss cycles 227010585Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::total 220050587910 # number of ReadReq miss cycles 227110585Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_miss_latency::cpu0.inst 3639850 # number of WriteInvalidateReq miss cycles 227210585Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_miss_latency::cpu1.inst 3440357 # number of WriteInvalidateReq miss cycles 227310585Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_miss_latency::total 7080207 # number of WriteInvalidateReq miss cycles 227410585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu0.inst 167282107 # number of UpgradeReq miss cycles 227510585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu1.inst 155790979 # number of UpgradeReq miss cycles 227610585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::total 323073086 # number of UpgradeReq miss cycles 227710585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu0.inst 53447323 # number of SCUpgradeReq miss cycles 227810585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu1.inst 50683879 # number of SCUpgradeReq miss cycles 227910585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::total 104131202 # number of SCUpgradeReq miss cycles 228010585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu0.inst 3468272337 # number of ReadExReq miss cycles 228110585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu1.inst 3934530582 # number of ReadExReq miss cycles 228210585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::total 7402802919 # number of ReadExReq miss cycles 228310585Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.dtb.walker 165226748 # number of demand (read+write) miss cycles 228410585Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.itb.walker 144557248 # number of demand (read+write) miss cycles 228510585Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.inst 11443079250 # number of demand (read+write) miss cycles 228610585Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 129814567894 # number of demand (read+write) miss cycles 228710585Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.dtb.walker 222345248 # number of demand (read+write) miss cycles 228810585Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.itb.walker 209364000 # number of demand (read+write) miss cycles 228910585Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.inst 14578667281 # number of demand (read+write) miss cycles 229010585Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 70875583160 # number of demand (read+write) miss cycles 229110585Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::total 227453390829 # number of demand (read+write) miss cycles 229210585Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.dtb.walker 165226748 # number of overall miss cycles 229310585Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.itb.walker 144557248 # number of overall miss cycles 229410585Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.inst 11443079250 # number of overall miss cycles 229510585Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 129814567894 # number of overall miss cycles 229610585Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.dtb.walker 222345248 # number of overall miss cycles 229710585Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.itb.walker 209364000 # number of overall miss cycles 229810585Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.inst 14578667281 # number of overall miss cycles 229910585Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 70875583160 # number of overall miss cycles 230010585Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::total 227453390829 # number of overall miss cycles 230110585Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.dtb.walker 10965 # number of ReadReq accesses(hits+misses) 230210585Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.itb.walker 8297 # number of ReadReq accesses(hits+misses) 230310585Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.inst 673895 # number of ReadReq accesses(hits+misses) 230410585Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 3165373 # number of ReadReq accesses(hits+misses) 230510585Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.dtb.walker 10853 # number of ReadReq accesses(hits+misses) 230610585Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.itb.walker 7845 # number of ReadReq accesses(hits+misses) 230710585Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.inst 761342 # number of ReadReq accesses(hits+misses) 230810585Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 2920422 # number of ReadReq accesses(hits+misses) 230910585Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::total 7558992 # number of ReadReq accesses(hits+misses) 231010585Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::writebacks 2942617 # number of Writeback accesses(hits+misses) 231110585Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::total 2942617 # number of Writeback accesses(hits+misses) 231210585Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_accesses::cpu0.inst 23153 # number of WriteInvalidateReq accesses(hits+misses) 231310585Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_accesses::cpu1.inst 13924 # number of WriteInvalidateReq accesses(hits+misses) 231410585Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_accesses::total 37077 # number of WriteInvalidateReq accesses(hits+misses) 231510585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.inst 75486 # number of UpgradeReq accesses(hits+misses) 231610585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.inst 68480 # number of UpgradeReq accesses(hits+misses) 231710585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 143966 # number of UpgradeReq accesses(hits+misses) 231810585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.inst 17008 # number of SCUpgradeReq accesses(hits+misses) 231910585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.inst 16789 # number of SCUpgradeReq accesses(hits+misses) 232010585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 33797 # number of SCUpgradeReq accesses(hits+misses) 232110585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.inst 109471 # number of ReadExReq accesses(hits+misses) 232210585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.inst 107228 # number of ReadExReq accesses(hits+misses) 232310585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 216699 # number of ReadExReq accesses(hits+misses) 232410585Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 10965 # number of demand (read+write) accesses 232510585Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 8297 # number of demand (read+write) accesses 232610585Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 783366 # number of demand (read+write) accesses 232710585Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.l2cache.prefetcher 3165373 # number of demand (read+write) accesses 232810585Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 10853 # number of demand (read+write) accesses 232910585Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 7845 # number of demand (read+write) accesses 233010585Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 868570 # number of demand (read+write) accesses 233110585Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.l2cache.prefetcher 2920422 # number of demand (read+write) accesses 233210585Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 7775691 # number of demand (read+write) accesses 233310585Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 10965 # number of overall (read+write) accesses 233410585Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 8297 # number of overall (read+write) accesses 233510585Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 783366 # number of overall (read+write) accesses 233610585Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.l2cache.prefetcher 3165373 # number of overall (read+write) accesses 233710585Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 10853 # number of overall (read+write) accesses 233810585Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 7845 # number of overall (read+write) accesses 233910585Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 868570 # number of overall (read+write) accesses 234010585Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.l2cache.prefetcher 2920422 # number of overall (read+write) accesses 234110585Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 7775691 # number of overall (read+write) accesses 234210585Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.180392 # miss rate for ReadReq accesses 234310585Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.204050 # miss rate for ReadReq accesses 234410585Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.inst 0.141734 # miss rate for ReadReq accesses 234510585Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.272802 # miss rate for ReadReq accesses 234610585Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.247397 # miss rate for ReadReq accesses 234710585Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.320204 # miss rate for ReadReq accesses 234810585Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.inst 0.172493 # miss rate for ReadReq accesses 234910585Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.193972 # miss rate for ReadReq accesses 235010585Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::total 0.220361 # miss rate for ReadReq accesses 235110585Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_miss_rate::cpu0.inst 0.730704 # miss rate for WriteInvalidateReq accesses 235210585Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_miss_rate::cpu1.inst 0.515226 # miss rate for WriteInvalidateReq accesses 235310585Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_miss_rate::total 0.649783 # miss rate for WriteInvalidateReq accesses 235410585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.inst 0.482765 # miss rate for UpgradeReq accesses 235510585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.inst 0.485558 # miss rate for UpgradeReq accesses 235610585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.484093 # miss rate for UpgradeReq accesses 235710585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.558208 # miss rate for SCUpgradeReq accesses 235810585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.536661 # miss rate for SCUpgradeReq accesses 235910585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.547504 # miss rate for SCUpgradeReq accesses 236010585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.inst 0.414174 # miss rate for ReadExReq accesses 236110585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.inst 0.485330 # miss rate for ReadExReq accesses 236210585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.449384 # miss rate for ReadExReq accesses 236310585Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.180392 # miss rate for demand accesses 236410585Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.204050 # miss rate for demand accesses 236510585Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.179806 # miss rate for demand accesses 236610585Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.272802 # miss rate for demand accesses 236710585Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.247397 # miss rate for demand accesses 236810585Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.320204 # miss rate for demand accesses 236910585Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.211114 # miss rate for demand accesses 237010585Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.193972 # miss rate for demand accesses 237110585Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.226744 # miss rate for demand accesses 237210585Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.180392 # miss rate for overall accesses 237310585Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.204050 # miss rate for overall accesses 237410585Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.179806 # miss rate for overall accesses 237510585Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.272802 # miss rate for overall accesses 237610585Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.247397 # miss rate for overall accesses 237710585Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.320204 # miss rate for overall accesses 237810585Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.211114 # miss rate for overall accesses 237910585Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.193972 # miss rate for overall accesses 238010585Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.226744 # miss rate for overall accesses 238110585Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 83532.228514 # average ReadReq miss latency 238210585Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 85385.261666 # average ReadReq miss latency 238310585Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu0.inst 83493.591651 # average ReadReq miss latency 238410585Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 150331.686078 # average ReadReq miss latency 238510585Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 82810.148231 # average ReadReq miss latency 238610585Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 83345.541401 # average ReadReq miss latency 238710585Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu1.inst 81051.251839 # average ReadReq miss latency 238810585Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 125115.773125 # average ReadReq miss latency 238910585Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::total 132106.261004 # average ReadReq miss latency 239010585Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.inst 215.146589 # average WriteInvalidateReq miss latency 239110585Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.inst 479.559102 # average WriteInvalidateReq miss latency 239210585Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_avg_miss_latency::total 293.882077 # average WriteInvalidateReq miss latency 239310585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 4590.365704 # average UpgradeReq miss latency 239410585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 4685.302066 # average UpgradeReq miss latency 239510585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::total 4635.660482 # average UpgradeReq miss latency 239610585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 5629.589530 # average SCUpgradeReq miss latency 239710585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 5625.291787 # average SCUpgradeReq miss latency 239810585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::total 5627.496866 # average SCUpgradeReq miss latency 239910585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu0.inst 76494.758205 # average ReadExReq miss latency 240010585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu1.inst 75604.438462 # average ReadExReq miss latency 240110585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::total 76018.965907 # average ReadExReq miss latency 240210585Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.dtb.walker 83532.228514 # average overall miss latency 240310585Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.itb.walker 85385.261666 # average overall miss latency 240410585Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.inst 81240.712014 # average overall miss latency 240510585Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 150331.686078 # average overall miss latency 240610585Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.dtb.walker 82810.148231 # average overall miss latency 240710585Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.itb.walker 83345.541401 # average overall miss latency 240810585Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.inst 79505.403268 # average overall miss latency 240910585Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 125115.773125 # average overall miss latency 241010585Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::total 129008.383480 # average overall miss latency 241110585Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.dtb.walker 83532.228514 # average overall miss latency 241210585Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.itb.walker 85385.261666 # average overall miss latency 241310585Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.inst 81240.712014 # average overall miss latency 241410585Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 150331.686078 # average overall miss latency 241510585Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.dtb.walker 82810.148231 # average overall miss latency 241610585Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.itb.walker 83345.541401 # average overall miss latency 241710585Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.inst 79505.403268 # average overall miss latency 241810585Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 125115.773125 # average overall miss latency 241910585Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::total 129008.383480 # average overall miss latency 242010585Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_mshrs 43295 # number of cycles access was blocked 242110515SAli.Saidi@ARM.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 242210585Sandreas.hansson@arm.comsystem.l2c.blocked::no_mshrs 946 # number of cycles access was blocked 242310515SAli.Saidi@ARM.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 242410585Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs 45.766385 # average number of cycles each access was blocked 242510515SAli.Saidi@ARM.comsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 242610515SAli.Saidi@ARM.comsystem.l2c.fast_writes 0 # number of fast writes performed 242710515SAli.Saidi@ARM.comsystem.l2c.cache_copies 0 # number of cache copies performed 242810585Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 1219289 # number of writebacks 242910585Sandreas.hansson@arm.comsystem.l2c.writebacks::total 1219289 # number of writebacks 243010585Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_hits::cpu0.inst 49 # number of ReadReq MSHR hits 243110585Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 228 # number of ReadReq MSHR hits 243210585Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_hits::cpu1.inst 53 # number of ReadReq MSHR hits 243310585Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 251 # number of ReadReq MSHR hits 243410585Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_hits::total 581 # number of ReadReq MSHR hits 243510585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu0.inst 49 # number of demand (read+write) MSHR hits 243610585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 228 # number of demand (read+write) MSHR hits 243710585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.inst 53 # number of demand (read+write) MSHR hits 243810585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 251 # number of demand (read+write) MSHR hits 243910585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::total 581 # number of demand (read+write) MSHR hits 244010585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu0.inst 49 # number of overall MSHR hits 244110585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 228 # number of overall MSHR hits 244210585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.inst 53 # number of overall MSHR hits 244310585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 251 # number of overall MSHR hits 244410585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::total 581 # number of overall MSHR hits 244510585Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1978 # number of ReadReq MSHR misses 244610585Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1693 # number of ReadReq MSHR misses 244710585Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu0.inst 95465 # number of ReadReq MSHR misses 244810585Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 863293 # number of ReadReq MSHR misses 244910585Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2685 # number of ReadReq MSHR misses 245010585Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2512 # number of ReadReq MSHR misses 245110585Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu1.inst 131273 # number of ReadReq MSHR misses 245210585Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 566229 # number of ReadReq MSHR misses 245310585Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::total 1665128 # number of ReadReq MSHR misses 245410585Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_mshr_misses::cpu0.inst 16918 # number of WriteInvalidateReq MSHR misses 245510585Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_mshr_misses::cpu1.inst 7174 # number of WriteInvalidateReq MSHR misses 245610585Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_mshr_misses::total 24092 # number of WriteInvalidateReq MSHR misses 245710585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu0.inst 36442 # number of UpgradeReq MSHR misses 245810585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu1.inst 33251 # number of UpgradeReq MSHR misses 245910585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::total 69693 # number of UpgradeReq MSHR misses 246010585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 9494 # number of SCUpgradeReq MSHR misses 246110585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 9010 # number of SCUpgradeReq MSHR misses 246210585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::total 18504 # number of SCUpgradeReq MSHR misses 246310585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu0.inst 45340 # number of ReadExReq MSHR misses 246410585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu1.inst 52041 # number of ReadExReq MSHR misses 246510585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::total 97381 # number of ReadExReq MSHR misses 246610585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.dtb.walker 1978 # number of demand (read+write) MSHR misses 246710585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.itb.walker 1693 # number of demand (read+write) MSHR misses 246810585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.inst 140805 # number of demand (read+write) MSHR misses 246910585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 863293 # number of demand (read+write) MSHR misses 247010585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.dtb.walker 2685 # number of demand (read+write) MSHR misses 247110585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.itb.walker 2512 # number of demand (read+write) MSHR misses 247210585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.inst 183314 # number of demand (read+write) MSHR misses 247310585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 566229 # number of demand (read+write) MSHR misses 247410585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::total 1762509 # number of demand (read+write) MSHR misses 247510585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.dtb.walker 1978 # number of overall MSHR misses 247610585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.itb.walker 1693 # number of overall MSHR misses 247710585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.inst 140805 # number of overall MSHR misses 247810585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 863293 # number of overall MSHR misses 247910585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.dtb.walker 2685 # number of overall MSHR misses 248010585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.itb.walker 2512 # number of overall MSHR misses 248110585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.inst 183314 # number of overall MSHR misses 248210585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 566229 # number of overall MSHR misses 248310585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::total 1762509 # number of overall MSHR misses 248410585Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 140499248 # number of ReadReq MSHR miss cycles 248510585Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 123414748 # number of ReadReq MSHR miss cycles 248610585Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::cpu0.inst 6776817493 # number of ReadReq MSHR miss cycles 248710585Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 119301017674 # number of ReadReq MSHR miss cycles 248810585Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 188732748 # number of ReadReq MSHR miss cycles 248910585Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 177898500 # number of ReadReq MSHR miss cycles 249010585Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::cpu1.inst 8997883953 # number of ReadReq MSHR miss cycles 249110585Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 63932898160 # number of ReadReq MSHR miss cycles 249210585Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::total 199639162524 # number of ReadReq MSHR miss cycles 249310585Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 385829647 # number of WriteInvalidateReq MSHR miss cycles 249410585Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.inst 157261640 # number of WriteInvalidateReq MSHR miss cycles 249510585Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_mshr_miss_latency::total 543091287 # number of WriteInvalidateReq MSHR miss cycles 249610585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 371667466 # number of UpgradeReq MSHR miss cycles 249710585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 338371346 # number of UpgradeReq MSHR miss cycles 249810585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::total 710038812 # number of UpgradeReq MSHR miss cycles 249910585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 97958865 # number of SCUpgradeReq MSHR miss cycles 250010585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 92039394 # number of SCUpgradeReq MSHR miss cycles 250110585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::total 189998259 # number of SCUpgradeReq MSHR miss cycles 250210585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 2897122081 # number of ReadExReq MSHR miss cycles 250310585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 3278712382 # number of ReadExReq MSHR miss cycles 250410585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::total 6175834463 # number of ReadExReq MSHR miss cycles 250510585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 140499248 # number of demand (read+write) MSHR miss cycles 250610585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.itb.walker 123414748 # number of demand (read+write) MSHR miss cycles 250710585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.inst 9673939574 # number of demand (read+write) MSHR miss cycles 250810585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 119301017674 # number of demand (read+write) MSHR miss cycles 250910585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 188732748 # number of demand (read+write) MSHR miss cycles 251010585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.itb.walker 177898500 # number of demand (read+write) MSHR miss cycles 251110585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.inst 12276596335 # number of demand (read+write) MSHR miss cycles 251210585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 63932898160 # number of demand (read+write) MSHR miss cycles 251310585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::total 205814996987 # number of demand (read+write) MSHR miss cycles 251410585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 140499248 # number of overall MSHR miss cycles 251510585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.itb.walker 123414748 # number of overall MSHR miss cycles 251610585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.inst 9673939574 # number of overall MSHR miss cycles 251710585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 119301017674 # number of overall MSHR miss cycles 251810585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 188732748 # number of overall MSHR miss cycles 251910585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.itb.walker 177898500 # number of overall MSHR miss cycles 252010585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.inst 12276596335 # number of overall MSHR miss cycles 252110585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 63932898160 # number of overall MSHR miss cycles 252210585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::total 205814996987 # number of overall MSHR miss cycles 252310585Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5245081248 # number of ReadReq MSHR uncacheable cycles 252410585Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2881233750 # number of ReadReq MSHR uncacheable cycles 252510585Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::total 8126314998 # number of ReadReq MSHR uncacheable cycles 252610585Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 2584862001 # number of WriteReq MSHR uncacheable cycles 252710585Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 2667893000 # number of WriteReq MSHR uncacheable cycles 252810585Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable_latency::total 5252755001 # number of WriteReq MSHR uncacheable cycles 252910585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.inst 7829943249 # number of overall MSHR uncacheable cycles 253010585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5549126750 # number of overall MSHR uncacheable cycles 253110585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::total 13379069999 # number of overall MSHR uncacheable cycles 253210585Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.180392 # mshr miss rate for ReadReq accesses 253310585Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.204050 # mshr miss rate for ReadReq accesses 253410585Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.141662 # mshr miss rate for ReadReq accesses 253510585Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.272730 # mshr miss rate for ReadReq accesses 253610585Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.247397 # mshr miss rate for ReadReq accesses 253710585Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.320204 # mshr miss rate for ReadReq accesses 253810585Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.172423 # mshr miss rate for ReadReq accesses 253910585Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.193886 # mshr miss rate for ReadReq accesses 254010585Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::total 0.220284 # mshr miss rate for ReadReq accesses 254110585Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.inst 0.730704 # mshr miss rate for WriteInvalidateReq accesses 254210585Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.inst 0.515226 # mshr miss rate for WriteInvalidateReq accesses 254310585Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.649783 # mshr miss rate for WriteInvalidateReq accesses 254410585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.482765 # mshr miss rate for UpgradeReq accesses 254510585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.485558 # mshr miss rate for UpgradeReq accesses 254610585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::total 0.484093 # mshr miss rate for UpgradeReq accesses 254710585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.558208 # mshr miss rate for SCUpgradeReq accesses 254810585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.536661 # mshr miss rate for SCUpgradeReq accesses 254910585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::total 0.547504 # mshr miss rate for SCUpgradeReq accesses 255010585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.414174 # mshr miss rate for ReadExReq accesses 255110585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.485330 # mshr miss rate for ReadExReq accesses 255210585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::total 0.449384 # mshr miss rate for ReadExReq accesses 255310585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.180392 # mshr miss rate for demand accesses 255410585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.204050 # mshr miss rate for demand accesses 255510585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.179744 # mshr miss rate for demand accesses 255610585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.272730 # mshr miss rate for demand accesses 255710585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.247397 # mshr miss rate for demand accesses 255810585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.320204 # mshr miss rate for demand accesses 255910585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.211053 # mshr miss rate for demand accesses 256010585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.193886 # mshr miss rate for demand accesses 256110585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::total 0.226669 # mshr miss rate for demand accesses 256210585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.180392 # mshr miss rate for overall accesses 256310585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.204050 # mshr miss rate for overall accesses 256410585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.179744 # mshr miss rate for overall accesses 256510585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.272730 # mshr miss rate for overall accesses 256610585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.247397 # mshr miss rate for overall accesses 256710585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.320204 # mshr miss rate for overall accesses 256810585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.211053 # mshr miss rate for overall accesses 256910585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.193886 # mshr miss rate for overall accesses 257010585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::total 0.226669 # mshr miss rate for overall accesses 257110585Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 71030.964611 # average ReadReq mshr miss latency 257210585Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 72897.075015 # average ReadReq mshr miss latency 257310585Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 70987.456062 # average ReadReq mshr miss latency 257410585Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 138192.963077 # average ReadReq mshr miss latency 257510585Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70291.526257 # average ReadReq mshr miss latency 257610585Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 70819.466561 # average ReadReq mshr miss latency 257710585Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 68543.294912 # average ReadReq mshr miss latency 257810585Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 112909.967805 # average ReadReq mshr miss latency 257910585Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::total 119894.183825 # average ReadReq mshr miss latency 258010585Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 22805.866355 # average WriteInvalidateReq mshr miss latency 258110585Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 21921.053805 # average WriteInvalidateReq mshr miss latency 258210585Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 22542.391126 # average WriteInvalidateReq mshr miss latency 258310585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10198.876736 # average UpgradeReq mshr miss latency 258410585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10176.275781 # average UpgradeReq mshr miss latency 258510585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 10188.093668 # average UpgradeReq mshr miss latency 258610585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10317.976090 # average SCUpgradeReq mshr miss latency 258710585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10215.249057 # average SCUpgradeReq mshr miss latency 258810585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10267.956064 # average SCUpgradeReq mshr miss latency 258910585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 63897.708006 # average ReadExReq mshr miss latency 259010585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 63002.486155 # average ReadExReq mshr miss latency 259110585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 63419.295992 # average ReadExReq mshr miss latency 259210585Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71030.964611 # average overall mshr miss latency 259310585Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 72897.075015 # average overall mshr miss latency 259410585Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68704.517411 # average overall mshr miss latency 259510585Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 138192.963077 # average overall mshr miss latency 259610585Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70291.526257 # average overall mshr miss latency 259710585Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 70819.466561 # average overall mshr miss latency 259810585Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66970.315060 # average overall mshr miss latency 259910585Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 112909.967805 # average overall mshr miss latency 260010585Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 116773.870084 # average overall mshr miss latency 260110585Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71030.964611 # average overall mshr miss latency 260210585Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 72897.075015 # average overall mshr miss latency 260310585Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68704.517411 # average overall mshr miss latency 260410585Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 138192.963077 # average overall mshr miss latency 260510585Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70291.526257 # average overall mshr miss latency 260610585Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 70819.466561 # average overall mshr miss latency 260710585Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66970.315060 # average overall mshr miss latency 260810585Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 112909.967805 # average overall mshr miss latency 260910585Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 116773.870084 # average overall mshr miss latency 261010515SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 261110515SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 261210515SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 261310515SAli.Saidi@ARM.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 261410515SAli.Saidi@ARM.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 261510515SAli.Saidi@ARM.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 261610515SAli.Saidi@ARM.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 261710515SAli.Saidi@ARM.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 261810515SAli.Saidi@ARM.comsystem.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 261910515SAli.Saidi@ARM.comsystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 262010585Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 1764688 # Transaction distribution 262110585Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 1764688 # Transaction distribution 262210585Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 38271 # Transaction distribution 262310585Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 38271 # Transaction distribution 262410585Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 1325983 # Transaction distribution 262510585Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteInvalidateReq 130519 # Transaction distribution 262610585Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteInvalidateResp 130519 # Transaction distribution 262710585Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 461811 # Transaction distribution 262810585Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 273493 # Transaction distribution 262910585Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 92294 # Transaction distribution 263010585Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 109929 # Transaction distribution 263110585Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 93588 # Transaction distribution 263210585Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122926 # Packet count per connected master and slave (bytes) 263310585Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) 263410585Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24884 # Packet count per connected master and slave (bytes) 263510585Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5737506 # Packet count per connected master and slave (bytes) 263610585Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 5885368 # Packet count per connected master and slave (bytes) 263710585Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336109 # Packet count per connected master and slave (bytes) 263810585Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 336109 # Packet count per connected master and slave (bytes) 263910585Sandreas.hansson@arm.comsystem.membus.pkt_count::total 6221477 # Packet count per connected master and slave (bytes) 264010585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156056 # Cumulative packet size per connected master and slave (bytes) 264110585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) 264210585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49768 # Cumulative packet size per connected master and slave (bytes) 264310585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 195441096 # Cumulative packet size per connected master and slave (bytes) 264410585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 195648244 # Cumulative packet size per connected master and slave (bytes) 264510585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14110976 # Cumulative packet size per connected master and slave (bytes) 264610585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 14110976 # Cumulative packet size per connected master and slave (bytes) 264710585Sandreas.hansson@arm.comsystem.membus.pkt_size::total 209759220 # Cumulative packet size per connected master and slave (bytes) 264810585Sandreas.hansson@arm.comsystem.membus.snoops 661928 # Total snoops (count) 264910585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 3975767 # Request fanout histogram 265010585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 265110585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 265210585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 265310585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 265410585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 3975767 100.00% 100.00% # Request fanout histogram 265510585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 265610585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 265710585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 265810585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 265910585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 3975767 # Request fanout histogram 266010585Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 109763969 # Layer occupancy (ticks) 266110585Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 266210585Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 34484 # Layer occupancy (ticks) 266310585Sandreas.hansson@arm.comsystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 266410585Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 20835993 # Layer occupancy (ticks) 266510585Sandreas.hansson@arm.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 266610585Sandreas.hansson@arm.comsystem.membus.reqLayer5.occupancy 15443357238 # Layer occupancy (ticks) 266710585Sandreas.hansson@arm.comsystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 266810585Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 16944581187 # Layer occupancy (ticks) 266910585Sandreas.hansson@arm.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 267010585Sandreas.hansson@arm.comsystem.membus.respLayer3.occupancy 187180159 # Layer occupancy (ticks) 267110585Sandreas.hansson@arm.comsystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 267210515SAli.Saidi@ARM.comsystem.realview.ethernet.txBytes 966 # Bytes Transmitted 267310515SAli.Saidi@ARM.comsystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 267410515SAli.Saidi@ARM.comsystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 267510515SAli.Saidi@ARM.comsystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 267610515SAli.Saidi@ARM.comsystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 267710515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 267810515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 267910515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 268010515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 268110515SAli.Saidi@ARM.comsystem.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 268210515SAli.Saidi@ARM.comsystem.realview.ethernet.totPackets 3 # Total Packets 268310515SAli.Saidi@ARM.comsystem.realview.ethernet.totBytes 966 # Total Bytes 268410515SAli.Saidi@ARM.comsystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 268510515SAli.Saidi@ARM.comsystem.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 268610515SAli.Saidi@ARM.comsystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 268710515SAli.Saidi@ARM.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 268810515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 268910515SAli.Saidi@ARM.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 269010515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 269110515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 269210515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 269310515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 269410515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 269510515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 269610515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 269710515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 269810515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 269910515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 270010515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 270110515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 270210515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 270310515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 270410515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 270510515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 270610515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 270710515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 270810515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 270910515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 271010515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 271110515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 271210515SAli.Saidi@ARM.comsystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 271310515SAli.Saidi@ARM.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 271410585Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 8566773 # Transaction distribution 271510585Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 8559524 # Transaction distribution 271610585Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 38271 # Transaction distribution 271710585Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 38271 # Transaction distribution 271810585Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::Writeback 2942617 # Transaction distribution 271910585Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteInvalidateReq 143810 # Transaction distribution 272010585Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteInvalidateResp 37077 # Transaction distribution 272110585Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 531990 # Transaction distribution 272210585Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 288786 # Transaction distribution 272310585Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 820776 # Transaction distribution 272410585Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeFailReq 117 # Transaction distribution 272510585Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeFailResp 117 # Transaction distribution 272610585Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 266520 # Transaction distribution 272710585Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 266520 # Transaction distribution 272810585Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10703555 # Packet count per connected master and slave (bytes) 272910585Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10080815 # Packet count per connected master and slave (bytes) 273010585Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 20784370 # Packet count per connected master and slave (bytes) 273110585Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 361515951 # Cumulative packet size per connected master and slave (bytes) 273210585Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 330513413 # Cumulative packet size per connected master and slave (bytes) 273310585Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 692029364 # Cumulative packet size per connected master and slave (bytes) 273410585Sandreas.hansson@arm.comsystem.toL2Bus.snoops 1718447 # Total snoops (count) 273510585Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 12650717 # Request fanout histogram 273610585Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 1.009140 # Request fanout histogram 273710585Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.095166 # Request fanout histogram 273810515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 273910515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 274010585Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 12535087 99.09% 99.09% # Request fanout histogram 274110585Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 115630 0.91% 100.00% # Request fanout histogram 274210515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 274310515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 274410515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 274510585Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 12650717 # Request fanout histogram 274610585Sandreas.hansson@arm.comsystem.toL2Bus.reqLayer0.occupancy 18290340474 # Layer occupancy (ticks) 274710515SAli.Saidi@ARM.comsystem.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 274810585Sandreas.hansson@arm.comsystem.toL2Bus.snoopLayer0.occupancy 7404000 # Layer occupancy (ticks) 274910515SAli.Saidi@ARM.comsystem.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 275010585Sandreas.hansson@arm.comsystem.toL2Bus.respLayer0.occupancy 20424320611 # Layer occupancy (ticks) 275110515SAli.Saidi@ARM.comsystem.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 275210585Sandreas.hansson@arm.comsystem.toL2Bus.respLayer1.occupancy 19750107809 # Layer occupancy (ticks) 275310515SAli.Saidi@ARM.comsystem.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 275410515SAli.Saidi@ARM.com 275510515SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 2756