stats.txt revision 10515
110515SAli.Saidi@ARM.com 210515SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 310515SAli.Saidi@ARM.comsim_seconds 47.349475 # Number of seconds simulated 410515SAli.Saidi@ARM.comsim_ticks 47349475204500 # Number of ticks simulated 510515SAli.Saidi@ARM.comfinal_tick 47349475204500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 710515SAli.Saidi@ARM.comhost_inst_rate 170024 # Simulator instruction rate (inst/s) 810515SAli.Saidi@ARM.comhost_op_rate 200007 # Simulator op (including micro ops) rate (op/s) 910515SAli.Saidi@ARM.comhost_tick_rate 9521770968 # Simulator tick rate (ticks/s) 1010515SAli.Saidi@ARM.comhost_mem_usage 827688 # Number of bytes of host memory used 1110515SAli.Saidi@ARM.comhost_seconds 4972.76 # Real time elapsed on the host 1210515SAli.Saidi@ARM.comsim_insts 845490438 # Number of instructions simulated 1310515SAli.Saidi@ARM.comsim_ops 994586036 # Number of ops (including micro ops) simulated 1410515SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610515SAli.Saidi@ARM.comsystem.physmem.bytes_read::realview.ide 457024 # Number of bytes read from this memory 1710515SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu0.dtb.walker 242432 # Number of bytes read from this memory 1810515SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu0.itb.walker 409152 # Number of bytes read from this memory 1910515SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu0.inst 13269720 # Number of bytes read from this memory 2010515SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu0.l2cache.prefetcher 28432512 # Number of bytes read from this memory 2110515SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu1.dtb.walker 254656 # Number of bytes read from this memory 2210515SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu1.itb.walker 419648 # Number of bytes read from this memory 2310515SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu1.inst 10291040 # Number of bytes read from this memory 2410515SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu1.l2cache.prefetcher 23441792 # Number of bytes read from this memory 2510515SAli.Saidi@ARM.comsystem.physmem.bytes_read::total 77217976 # Number of bytes read from this memory 2610515SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::cpu0.inst 3825664 # Number of instructions bytes read from this memory 2710515SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::cpu1.inst 566400 # Number of instructions bytes read from this memory 2810515SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::total 4392064 # Number of instructions bytes read from this memory 2910515SAli.Saidi@ARM.comsystem.physmem.bytes_written::writebacks 33722560 # Number of bytes written to this memory 3010515SAli.Saidi@ARM.comsystem.physmem.bytes_written::realview.ide 6830592 # Number of bytes written to this memory 3110515SAli.Saidi@ARM.comsystem.physmem.bytes_written::cpu0.inst 56250828 # Number of bytes written to this memory 3210515SAli.Saidi@ARM.comsystem.physmem.bytes_written::cpu1.inst 43534148 # Number of bytes written to this memory 3310515SAli.Saidi@ARM.comsystem.physmem.bytes_written::total 140338128 # Number of bytes written to this memory 3410515SAli.Saidi@ARM.comsystem.physmem.num_reads::realview.ide 7141 # Number of read requests responded to by this memory 3510515SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu0.dtb.walker 3788 # Number of read requests responded to by this memory 3610515SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu0.itb.walker 6393 # Number of read requests responded to by this memory 3710515SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu0.inst 207361 # Number of read requests responded to by this memory 3810515SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu0.l2cache.prefetcher 444258 # Number of read requests responded to by this memory 3910515SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu1.dtb.walker 3979 # Number of read requests responded to by this memory 4010515SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu1.itb.walker 6557 # Number of read requests responded to by this memory 4110515SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu1.inst 160812 # Number of read requests responded to by this memory 4210515SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu1.l2cache.prefetcher 366278 # Number of read requests responded to by this memory 4310515SAli.Saidi@ARM.comsystem.physmem.num_reads::total 1206567 # Number of read requests responded to by this memory 4410515SAli.Saidi@ARM.comsystem.physmem.num_writes::writebacks 526915 # Number of write requests responded to by this memory 4510515SAli.Saidi@ARM.comsystem.physmem.num_writes::realview.ide 106728 # Number of write requests responded to by this memory 4610515SAli.Saidi@ARM.comsystem.physmem.num_writes::cpu0.inst 881196 # Number of write requests responded to by this memory 4710515SAli.Saidi@ARM.comsystem.physmem.num_writes::cpu1.inst 680222 # Number of write requests responded to by this memory 4810515SAli.Saidi@ARM.comsystem.physmem.num_writes::total 2195061 # Number of write requests responded to by this memory 4910515SAli.Saidi@ARM.comsystem.physmem.bw_read::realview.ide 9652 # Total read bandwidth from this memory (bytes/s) 5010515SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu0.dtb.walker 5120 # Total read bandwidth from this memory (bytes/s) 5110515SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu0.itb.walker 8641 # Total read bandwidth from this memory (bytes/s) 5210515SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu0.inst 280251 # Total read bandwidth from this memory (bytes/s) 5310515SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu0.l2cache.prefetcher 600482 # Total read bandwidth from this memory (bytes/s) 5410515SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu1.dtb.walker 5378 # Total read bandwidth from this memory (bytes/s) 5510515SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu1.itb.walker 8863 # Total read bandwidth from this memory (bytes/s) 5610515SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu1.inst 217342 # Total read bandwidth from this memory (bytes/s) 5710515SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu1.l2cache.prefetcher 495080 # Total read bandwidth from this memory (bytes/s) 5810515SAli.Saidi@ARM.comsystem.physmem.bw_read::total 1630810 # Total read bandwidth from this memory (bytes/s) 5910515SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::cpu0.inst 80796 # Instruction read bandwidth from this memory (bytes/s) 6010515SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::cpu1.inst 11962 # Instruction read bandwidth from this memory (bytes/s) 6110515SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::total 92758 # Instruction read bandwidth from this memory (bytes/s) 6210515SAli.Saidi@ARM.comsystem.physmem.bw_write::writebacks 712206 # Write bandwidth from this memory (bytes/s) 6310515SAli.Saidi@ARM.comsystem.physmem.bw_write::realview.ide 144259 # Write bandwidth from this memory (bytes/s) 6410515SAli.Saidi@ARM.comsystem.physmem.bw_write::cpu0.inst 1187993 # Write bandwidth from this memory (bytes/s) 6510515SAli.Saidi@ARM.comsystem.physmem.bw_write::cpu1.inst 919422 # Write bandwidth from this memory (bytes/s) 6610515SAli.Saidi@ARM.comsystem.physmem.bw_write::total 2963879 # Write bandwidth from this memory (bytes/s) 6710515SAli.Saidi@ARM.comsystem.physmem.bw_total::writebacks 712206 # Total bandwidth to/from this memory (bytes/s) 6810515SAli.Saidi@ARM.comsystem.physmem.bw_total::realview.ide 153911 # Total bandwidth to/from this memory (bytes/s) 6910515SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu0.dtb.walker 5120 # Total bandwidth to/from this memory (bytes/s) 7010515SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu0.itb.walker 8641 # Total bandwidth to/from this memory (bytes/s) 7110515SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu0.inst 1468243 # Total bandwidth to/from this memory (bytes/s) 7210515SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu0.l2cache.prefetcher 600482 # Total bandwidth to/from this memory (bytes/s) 7310515SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu1.dtb.walker 5378 # Total bandwidth to/from this memory (bytes/s) 7410515SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu1.itb.walker 8863 # Total bandwidth to/from this memory (bytes/s) 7510515SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu1.inst 1136764 # Total bandwidth to/from this memory (bytes/s) 7610515SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu1.l2cache.prefetcher 495080 # Total bandwidth to/from this memory (bytes/s) 7710515SAli.Saidi@ARM.comsystem.physmem.bw_total::total 4594689 # Total bandwidth to/from this memory (bytes/s) 7810515SAli.Saidi@ARM.comsystem.physmem.readReqs 1206567 # Number of read requests accepted 7910515SAli.Saidi@ARM.comsystem.physmem.writeReqs 2195061 # Number of write requests accepted 8010515SAli.Saidi@ARM.comsystem.physmem.readBursts 1206567 # Number of DRAM read bursts, including those serviced by the write queue 8110515SAli.Saidi@ARM.comsystem.physmem.writeBursts 2195061 # Number of DRAM write bursts, including those merged in the write queue 8210515SAli.Saidi@ARM.comsystem.physmem.bytesReadDRAM 76928704 # Total number of bytes read from DRAM 8310515SAli.Saidi@ARM.comsystem.physmem.bytesReadWrQ 291584 # Total number of bytes read from write queue 8410515SAli.Saidi@ARM.comsystem.physmem.bytesWritten 135133184 # Total number of bytes written to DRAM 8510515SAli.Saidi@ARM.comsystem.physmem.bytesReadSys 77217976 # Total read bytes from the system interface side 8610515SAli.Saidi@ARM.comsystem.physmem.bytesWrittenSys 140338128 # Total written bytes from the system interface side 8710515SAli.Saidi@ARM.comsystem.physmem.servicedByWrQ 4556 # Number of DRAM read bursts serviced by the write queue 8810515SAli.Saidi@ARM.comsystem.physmem.mergedWrBursts 83588 # Number of DRAM write bursts merged with an existing one 8910515SAli.Saidi@ARM.comsystem.physmem.neitherReadNorWriteReqs 93227 # Number of requests that are neither read nor write 9010515SAli.Saidi@ARM.comsystem.physmem.perBankRdBursts::0 68916 # Per bank write bursts 9110515SAli.Saidi@ARM.comsystem.physmem.perBankRdBursts::1 78372 # Per bank write bursts 9210515SAli.Saidi@ARM.comsystem.physmem.perBankRdBursts::2 66961 # Per bank write bursts 9310515SAli.Saidi@ARM.comsystem.physmem.perBankRdBursts::3 74483 # Per bank write bursts 9410515SAli.Saidi@ARM.comsystem.physmem.perBankRdBursts::4 67860 # Per bank write bursts 9510515SAli.Saidi@ARM.comsystem.physmem.perBankRdBursts::5 84994 # Per bank write bursts 9610515SAli.Saidi@ARM.comsystem.physmem.perBankRdBursts::6 78873 # Per bank write bursts 9710515SAli.Saidi@ARM.comsystem.physmem.perBankRdBursts::7 74831 # Per bank write bursts 9810515SAli.Saidi@ARM.comsystem.physmem.perBankRdBursts::8 70689 # Per bank write bursts 9910515SAli.Saidi@ARM.comsystem.physmem.perBankRdBursts::9 121049 # Per bank write bursts 10010515SAli.Saidi@ARM.comsystem.physmem.perBankRdBursts::10 55712 # Per bank write bursts 10110515SAli.Saidi@ARM.comsystem.physmem.perBankRdBursts::11 71204 # Per bank write bursts 10210515SAli.Saidi@ARM.comsystem.physmem.perBankRdBursts::12 68805 # Per bank write bursts 10310515SAli.Saidi@ARM.comsystem.physmem.perBankRdBursts::13 80552 # Per bank write bursts 10410515SAli.Saidi@ARM.comsystem.physmem.perBankRdBursts::14 71313 # Per bank write bursts 10510515SAli.Saidi@ARM.comsystem.physmem.perBankRdBursts::15 67397 # Per bank write bursts 10610515SAli.Saidi@ARM.comsystem.physmem.perBankWrBursts::0 131295 # Per bank write bursts 10710515SAli.Saidi@ARM.comsystem.physmem.perBankWrBursts::1 120115 # Per bank write bursts 10810515SAli.Saidi@ARM.comsystem.physmem.perBankWrBursts::2 136218 # Per bank write bursts 10910515SAli.Saidi@ARM.comsystem.physmem.perBankWrBursts::3 122111 # Per bank write bursts 11010515SAli.Saidi@ARM.comsystem.physmem.perBankWrBursts::4 136290 # Per bank write bursts 11110515SAli.Saidi@ARM.comsystem.physmem.perBankWrBursts::5 134780 # Per bank write bursts 11210515SAli.Saidi@ARM.comsystem.physmem.perBankWrBursts::6 183921 # Per bank write bursts 11310515SAli.Saidi@ARM.comsystem.physmem.perBankWrBursts::7 113990 # Per bank write bursts 11410515SAli.Saidi@ARM.comsystem.physmem.perBankWrBursts::8 112648 # Per bank write bursts 11510515SAli.Saidi@ARM.comsystem.physmem.perBankWrBursts::9 120303 # Per bank write bursts 11610515SAli.Saidi@ARM.comsystem.physmem.perBankWrBursts::10 105255 # Per bank write bursts 11710515SAli.Saidi@ARM.comsystem.physmem.perBankWrBursts::11 150368 # Per bank write bursts 11810515SAli.Saidi@ARM.comsystem.physmem.perBankWrBursts::12 133266 # Per bank write bursts 11910515SAli.Saidi@ARM.comsystem.physmem.perBankWrBursts::13 132701 # Per bank write bursts 12010515SAli.Saidi@ARM.comsystem.physmem.perBankWrBursts::14 112511 # Per bank write bursts 12110515SAli.Saidi@ARM.comsystem.physmem.perBankWrBursts::15 165684 # Per bank write bursts 12210515SAli.Saidi@ARM.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 12310515SAli.Saidi@ARM.comsystem.physmem.numWrRetry 10 # Number of times write queue was full causing retry 12410515SAli.Saidi@ARM.comsystem.physmem.totGap 47349473266500 # Total gap between requests 12510515SAli.Saidi@ARM.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 12610515SAli.Saidi@ARM.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 12710515SAli.Saidi@ARM.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 12810515SAli.Saidi@ARM.comsystem.physmem.readPktSize::3 37 # Read request sizes (log2) 12910515SAli.Saidi@ARM.comsystem.physmem.readPktSize::4 5 # Read request sizes (log2) 13010515SAli.Saidi@ARM.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 13110515SAli.Saidi@ARM.comsystem.physmem.readPktSize::6 1206525 # Read request sizes (log2) 13210515SAli.Saidi@ARM.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 13310515SAli.Saidi@ARM.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 13410515SAli.Saidi@ARM.comsystem.physmem.writePktSize::2 2 # Write request sizes (log2) 13510515SAli.Saidi@ARM.comsystem.physmem.writePktSize::3 2601 # Write request sizes (log2) 13610515SAli.Saidi@ARM.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 13710515SAli.Saidi@ARM.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 13810515SAli.Saidi@ARM.comsystem.physmem.writePktSize::6 2192458 # Write request sizes (log2) 13910515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::0 701586 # What read queue length does an incoming req see 14010515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::1 159041 # What read queue length does an incoming req see 14110515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::2 78388 # What read queue length does an incoming req see 14210515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::3 62534 # What read queue length does an incoming req see 14310515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::4 48409 # What read queue length does an incoming req see 14410515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::5 42357 # What read queue length does an incoming req see 14510515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::6 36825 # What read queue length does an incoming req see 14610515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::7 30566 # What read queue length does an incoming req see 14710515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::8 24739 # What read queue length does an incoming req see 14810515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::9 6356 # What read queue length does an incoming req see 14910515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::10 3319 # What read queue length does an incoming req see 15010515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::11 2365 # What read queue length does an incoming req see 15110515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::12 1772 # What read queue length does an incoming req see 15210515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::13 1348 # What read queue length does an incoming req see 15310515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::14 953 # What read queue length does an incoming req see 15410515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::15 724 # What read queue length does an incoming req see 15510515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::16 286 # What read queue length does an incoming req see 15610515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::17 212 # What read queue length does an incoming req see 15710515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::18 134 # What read queue length does an incoming req see 15810515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::19 92 # What read queue length does an incoming req see 15910515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see 16010515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 16110515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 16210515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 16310515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 16410515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 16510515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 16610515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 16710515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 16810515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 16910515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 17010515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 17110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 17210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 17310515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 17410515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 17510515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 17610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 17710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 17810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 17910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 18010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 18110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 18210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 18310515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 18410515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 18510515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 18610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::15 77454 # What write queue length does an incoming req see 18710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::16 97715 # What write queue length does an incoming req see 18810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::17 98472 # What write queue length does an incoming req see 18910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::18 108608 # What write queue length does an incoming req see 19010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::19 137758 # What write queue length does an incoming req see 19110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::20 125184 # What write queue length does an incoming req see 19210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::21 127483 # What write queue length does an incoming req see 19310515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::22 141417 # What write queue length does an incoming req see 19410515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::23 129468 # What write queue length does an incoming req see 19510515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::24 120366 # What write queue length does an incoming req see 19610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::25 126014 # What write queue length does an incoming req see 19710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::26 120082 # What write queue length does an incoming req see 19810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::27 115005 # What write queue length does an incoming req see 19910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::28 123737 # What write queue length does an incoming req see 20010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::29 112481 # What write queue length does an incoming req see 20110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::30 110136 # What write queue length does an incoming req see 20210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::31 106316 # What write queue length does an incoming req see 20310515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::32 102758 # What write queue length does an incoming req see 20410515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::33 5440 # What write queue length does an incoming req see 20510515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::34 4456 # What write queue length does an incoming req see 20610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::35 3538 # What write queue length does an incoming req see 20710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::36 2946 # What write queue length does an incoming req see 20810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::37 2503 # What write queue length does an incoming req see 20910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::38 2161 # What write queue length does an incoming req see 21010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::39 1740 # What write queue length does an incoming req see 21110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::40 1473 # What write queue length does an incoming req see 21210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::41 1128 # What write queue length does an incoming req see 21310515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::42 896 # What write queue length does an incoming req see 21410515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::43 630 # What write queue length does an incoming req see 21510515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::44 501 # What write queue length does an incoming req see 21610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::45 456 # What write queue length does an incoming req see 21710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::46 392 # What write queue length does an incoming req see 21810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::47 367 # What write queue length does an incoming req see 21910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::48 336 # What write queue length does an incoming req see 22010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::49 298 # What write queue length does an incoming req see 22110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::50 282 # What write queue length does an incoming req see 22210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::51 248 # What write queue length does an incoming req see 22310515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::52 237 # What write queue length does an incoming req see 22410515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::53 208 # What write queue length does an incoming req see 22510515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::54 184 # What write queue length does an incoming req see 22610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::55 156 # What write queue length does an incoming req see 22710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::56 130 # What write queue length does an incoming req see 22810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::57 88 # What write queue length does an incoming req see 22910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::58 66 # What write queue length does an incoming req see 23010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::59 48 # What write queue length does an incoming req see 23110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::60 38 # What write queue length does an incoming req see 23210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::61 21 # What write queue length does an incoming req see 23310515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see 23410515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::63 21 # What write queue length does an incoming req see 23510515SAli.Saidi@ARM.comsystem.physmem.bytesPerActivate::samples 691339 # Bytes accessed per row activation 23610515SAli.Saidi@ARM.comsystem.physmem.bytesPerActivate::mean 306.739519 # Bytes accessed per row activation 23710515SAli.Saidi@ARM.comsystem.physmem.bytesPerActivate::gmean 163.472793 # Bytes accessed per row activation 23810515SAli.Saidi@ARM.comsystem.physmem.bytesPerActivate::stdev 357.323128 # Bytes accessed per row activation 23910515SAli.Saidi@ARM.comsystem.physmem.bytesPerActivate::0-127 329714 47.69% 47.69% # Bytes accessed per row activation 24010515SAli.Saidi@ARM.comsystem.physmem.bytesPerActivate::128-255 128094 18.53% 66.22% # Bytes accessed per row activation 24110515SAli.Saidi@ARM.comsystem.physmem.bytesPerActivate::256-383 46159 6.68% 72.90% # Bytes accessed per row activation 24210515SAli.Saidi@ARM.comsystem.physmem.bytesPerActivate::384-511 24419 3.53% 76.43% # Bytes accessed per row activation 24310515SAli.Saidi@ARM.comsystem.physmem.bytesPerActivate::512-639 20272 2.93% 79.36% # Bytes accessed per row activation 24410515SAli.Saidi@ARM.comsystem.physmem.bytesPerActivate::640-767 13585 1.97% 81.33% # Bytes accessed per row activation 24510515SAli.Saidi@ARM.comsystem.physmem.bytesPerActivate::768-895 10457 1.51% 82.84% # Bytes accessed per row activation 24610515SAli.Saidi@ARM.comsystem.physmem.bytesPerActivate::896-1023 11430 1.65% 84.49% # Bytes accessed per row activation 24710515SAli.Saidi@ARM.comsystem.physmem.bytesPerActivate::1024-1151 107209 15.51% 100.00% # Bytes accessed per row activation 24810515SAli.Saidi@ARM.comsystem.physmem.bytesPerActivate::total 691339 # Bytes accessed per row activation 24910515SAli.Saidi@ARM.comsystem.physmem.rdPerTurnAround::samples 99075 # Reads before turning the bus around for writes 25010515SAli.Saidi@ARM.comsystem.physmem.rdPerTurnAround::mean 12.132152 # Reads before turning the bus around for writes 25110515SAli.Saidi@ARM.comsystem.physmem.rdPerTurnAround::stdev 222.564559 # Reads before turning the bus around for writes 25210515SAli.Saidi@ARM.comsystem.physmem.rdPerTurnAround::0-2047 99072 100.00% 100.00% # Reads before turning the bus around for writes 25310515SAli.Saidi@ARM.comsystem.physmem.rdPerTurnAround::24576-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 25410515SAli.Saidi@ARM.comsystem.physmem.rdPerTurnAround::28672-30719 1 0.00% 100.00% # Reads before turning the bus around for writes 25510515SAli.Saidi@ARM.comsystem.physmem.rdPerTurnAround::57344-59391 1 0.00% 100.00% # Reads before turning the bus around for writes 25610515SAli.Saidi@ARM.comsystem.physmem.rdPerTurnAround::total 99075 # Reads before turning the bus around for writes 25710515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::samples 99075 # Writes before turning the bus around for reads 25810515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::mean 21.311693 # Writes before turning the bus around for reads 25910515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::gmean 20.731664 # Writes before turning the bus around for reads 26010515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::stdev 6.258880 # Writes before turning the bus around for reads 26110515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::16-19 33791 34.11% 34.11% # Writes before turning the bus around for reads 26210515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::20-23 48957 49.41% 83.52% # Writes before turning the bus around for reads 26310515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::24-27 10331 10.43% 93.95% # Writes before turning the bus around for reads 26410515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::28-31 2038 2.06% 96.01% # Writes before turning the bus around for reads 26510515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::32-35 1546 1.56% 97.57% # Writes before turning the bus around for reads 26610515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::36-39 746 0.75% 98.32% # Writes before turning the bus around for reads 26710515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::40-43 511 0.52% 98.83% # Writes before turning the bus around for reads 26810515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::44-47 316 0.32% 99.15% # Writes before turning the bus around for reads 26910515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::48-51 116 0.12% 99.27% # Writes before turning the bus around for reads 27010515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::52-55 38 0.04% 99.31% # Writes before turning the bus around for reads 27110515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::56-59 31 0.03% 99.34% # Writes before turning the bus around for reads 27210515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::60-63 20 0.02% 99.36% # Writes before turning the bus around for reads 27310515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::64-67 438 0.44% 99.80% # Writes before turning the bus around for reads 27410515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::68-71 35 0.04% 99.84% # Writes before turning the bus around for reads 27510515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::72-75 39 0.04% 99.88% # Writes before turning the bus around for reads 27610515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::76-79 38 0.04% 99.92% # Writes before turning the bus around for reads 27710515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::80-83 24 0.02% 99.94% # Writes before turning the bus around for reads 27810515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::84-87 3 0.00% 99.94% # Writes before turning the bus around for reads 27910515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::88-91 2 0.00% 99.94% # Writes before turning the bus around for reads 28010515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::92-95 1 0.00% 99.95% # Writes before turning the bus around for reads 28110515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::96-99 10 0.01% 99.96% # Writes before turning the bus around for reads 28210515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::104-107 7 0.01% 99.96% # Writes before turning the bus around for reads 28310515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::108-111 4 0.00% 99.97% # Writes before turning the bus around for reads 28410515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::112-115 3 0.00% 99.97% # Writes before turning the bus around for reads 28510515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::116-119 3 0.00% 99.97% # Writes before turning the bus around for reads 28610515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::128-131 17 0.02% 99.99% # Writes before turning the bus around for reads 28710515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::132-135 3 0.00% 99.99% # Writes before turning the bus around for reads 28810515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::136-139 1 0.00% 99.99% # Writes before turning the bus around for reads 28910515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::140-143 4 0.00% 100.00% # Writes before turning the bus around for reads 29010515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::172-175 1 0.00% 100.00% # Writes before turning the bus around for reads 29110515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::196-199 1 0.00% 100.00% # Writes before turning the bus around for reads 29210515SAli.Saidi@ARM.comsystem.physmem.wrPerTurnAround::total 99075 # Writes before turning the bus around for reads 29310515SAli.Saidi@ARM.comsystem.physmem.totQLat 32464480274 # Total ticks spent queuing 29410515SAli.Saidi@ARM.comsystem.physmem.totMemAccLat 55002186524 # Total ticks spent from burst creation until serviced by the DRAM 29510515SAli.Saidi@ARM.comsystem.physmem.totBusLat 6010055000 # Total ticks spent in databus transfers 29610515SAli.Saidi@ARM.comsystem.physmem.avgQLat 27008.47 # Average queueing delay per DRAM burst 29710515SAli.Saidi@ARM.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 29810515SAli.Saidi@ARM.comsystem.physmem.avgMemAccLat 45758.47 # Average memory access latency per DRAM burst 29910515SAli.Saidi@ARM.comsystem.physmem.avgRdBW 1.62 # Average DRAM read bandwidth in MiByte/s 30010515SAli.Saidi@ARM.comsystem.physmem.avgWrBW 2.85 # Average achieved write bandwidth in MiByte/s 30110515SAli.Saidi@ARM.comsystem.physmem.avgRdBWSys 1.63 # Average system read bandwidth in MiByte/s 30210515SAli.Saidi@ARM.comsystem.physmem.avgWrBWSys 2.96 # Average system write bandwidth in MiByte/s 30310515SAli.Saidi@ARM.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 30410515SAli.Saidi@ARM.comsystem.physmem.busUtil 0.03 # Data bus utilization in percentage 30510515SAli.Saidi@ARM.comsystem.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 30610515SAli.Saidi@ARM.comsystem.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 30710515SAli.Saidi@ARM.comsystem.physmem.avgRdQLen 1.40 # Average read queue length when enqueuing 30810515SAli.Saidi@ARM.comsystem.physmem.avgWrQLen 23.37 # Average write queue length when enqueuing 30910515SAli.Saidi@ARM.comsystem.physmem.readRowHits 944165 # Number of row buffer hits during reads 31010515SAli.Saidi@ARM.comsystem.physmem.writeRowHits 1677959 # Number of row buffer hits during writes 31110515SAli.Saidi@ARM.comsystem.physmem.readRowHitRate 78.55 # Row buffer hit rate for reads 31210515SAli.Saidi@ARM.comsystem.physmem.writeRowHitRate 79.47 # Row buffer hit rate for writes 31310515SAli.Saidi@ARM.comsystem.physmem.avgGap 13919650.61 # Average gap between requests 31410515SAli.Saidi@ARM.comsystem.physmem.pageHitRate 79.13 # Row buffer hit rate, read and write combined 31510515SAli.Saidi@ARM.comsystem.physmem.memoryStateTime::IDLE 45391806829500 # Time in different power states 31610515SAli.Saidi@ARM.comsystem.physmem.memoryStateTime::REF 1581102900000 # Time in different power states 31710515SAli.Saidi@ARM.comsystem.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 31810515SAli.Saidi@ARM.comsystem.physmem.memoryStateTime::ACT 376561525500 # Time in different power states 31910515SAli.Saidi@ARM.comsystem.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 32010515SAli.Saidi@ARM.comsystem.physmem.actEnergy::0 2682083880 # Energy for activate commands per rank (pJ) 32110515SAli.Saidi@ARM.comsystem.physmem.actEnergy::1 2544438960 # Energy for activate commands per rank (pJ) 32210515SAli.Saidi@ARM.comsystem.physmem.preEnergy::0 1463438625 # Energy for precharge commands per rank (pJ) 32310515SAli.Saidi@ARM.comsystem.physmem.preEnergy::1 1388334750 # Energy for precharge commands per rank (pJ) 32410515SAli.Saidi@ARM.comsystem.physmem.readEnergy::0 4643184000 # Energy for read commands per rank (pJ) 32510515SAli.Saidi@ARM.comsystem.physmem.readEnergy::1 4732392600 # Energy for read commands per rank (pJ) 32610515SAli.Saidi@ARM.comsystem.physmem.writeEnergy::0 6990105600 # Energy for write commands per rank (pJ) 32710515SAli.Saidi@ARM.comsystem.physmem.writeEnergy::1 6692129280 # Energy for write commands per rank (pJ) 32810515SAli.Saidi@ARM.comsystem.physmem.refreshEnergy::0 3092637272400 # Energy for refresh commands per rank (pJ) 32910515SAli.Saidi@ARM.comsystem.physmem.refreshEnergy::1 3092637272400 # Energy for refresh commands per rank (pJ) 33010515SAli.Saidi@ARM.comsystem.physmem.actBackEnergy::0 1220178523320 # Energy for active background per rank (pJ) 33110515SAli.Saidi@ARM.comsystem.physmem.actBackEnergy::1 1215644323230 # Energy for active background per rank (pJ) 33210515SAli.Saidi@ARM.comsystem.physmem.preBackEnergy::0 27339350706750 # Energy for precharge background per rank (pJ) 33310515SAli.Saidi@ARM.comsystem.physmem.preBackEnergy::1 27343328075250 # Energy for precharge background per rank (pJ) 33410515SAli.Saidi@ARM.comsystem.physmem.totalEnergy::0 31667945314575 # Total energy per rank (pJ) 33510515SAli.Saidi@ARM.comsystem.physmem.totalEnergy::1 31666966966470 # Total energy per rank (pJ) 33610515SAli.Saidi@ARM.comsystem.physmem.averagePower::0 668.813072 # Core power per rank (mW) 33710515SAli.Saidi@ARM.comsystem.physmem.averagePower::1 668.792410 # Core power per rank (mW) 33810515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::cpu0.inst 740 # Number of bytes read from this memory 33910515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::cpu1.inst 584 # Number of bytes read from this memory 34010515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory 34110515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory 34210515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory 34310515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory 34410515SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::cpu0.inst 16 # Number of read requests responded to by this memory 34510515SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory 34610515SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory 34710515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu0.inst 16 # Total read bandwidth from this memory (bytes/s) 34810515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s) 34910515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s) 35010515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) 35110515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s) 35210515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) 35310515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu0.inst 16 # Total bandwidth to/from this memory (bytes/s) 35410515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s) 35510515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) 35610515SAli.Saidi@ARM.comsystem.membus.trans_dist::ReadReq 1114990 # Transaction distribution 35710515SAli.Saidi@ARM.comsystem.membus.trans_dist::ReadResp 1114990 # Transaction distribution 35810515SAli.Saidi@ARM.comsystem.membus.trans_dist::WriteReq 37937 # Transaction distribution 35910515SAli.Saidi@ARM.comsystem.membus.trans_dist::WriteResp 37937 # Transaction distribution 36010515SAli.Saidi@ARM.comsystem.membus.trans_dist::Writeback 526915 # Transaction distribution 36110515SAli.Saidi@ARM.comsystem.membus.trans_dist::WriteInvalidateReq 1665543 # Transaction distribution 36210515SAli.Saidi@ARM.comsystem.membus.trans_dist::WriteInvalidateResp 1665543 # Transaction distribution 36310515SAli.Saidi@ARM.comsystem.membus.trans_dist::UpgradeReq 343558 # Transaction distribution 36410515SAli.Saidi@ARM.comsystem.membus.trans_dist::SCUpgradeReq 290459 # Transaction distribution 36510515SAli.Saidi@ARM.comsystem.membus.trans_dist::UpgradeResp 93233 # Transaction distribution 36610515SAli.Saidi@ARM.comsystem.membus.trans_dist::ReadExReq 145423 # Transaction distribution 36710515SAli.Saidi@ARM.comsystem.membus.trans_dist::ReadExResp 131308 # Transaction distribution 36810515SAli.Saidi@ARM.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122918 # Packet count per connected master and slave (bytes) 36910515SAli.Saidi@ARM.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) 37010515SAli.Saidi@ARM.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 23584 # Packet count per connected master and slave (bytes) 37110515SAli.Saidi@ARM.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6789962 # Packet count per connected master and slave (bytes) 37210515SAli.Saidi@ARM.comsystem.membus.pkt_count_system.l2c.mem_side::total 6936516 # Packet count per connected master and slave (bytes) 37310515SAli.Saidi@ARM.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 229526 # Packet count per connected master and slave (bytes) 37410515SAli.Saidi@ARM.comsystem.membus.pkt_count_system.iocache.mem_side::total 229526 # Packet count per connected master and slave (bytes) 37510515SAli.Saidi@ARM.comsystem.membus.pkt_count::total 7166042 # Packet count per connected master and slave (bytes) 37610515SAli.Saidi@ARM.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156048 # Cumulative packet size per connected master and slave (bytes) 37710515SAli.Saidi@ARM.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) 37810515SAli.Saidi@ARM.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 47168 # Cumulative packet size per connected master and slave (bytes) 37910515SAli.Saidi@ARM.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 210268488 # Cumulative packet size per connected master and slave (bytes) 38010515SAli.Saidi@ARM.comsystem.membus.pkt_size_system.l2c.mem_side::total 210473028 # Cumulative packet size per connected master and slave (bytes) 38110515SAli.Saidi@ARM.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7287616 # Cumulative packet size per connected master and slave (bytes) 38210515SAli.Saidi@ARM.comsystem.membus.pkt_size_system.iocache.mem_side::total 7287616 # Cumulative packet size per connected master and slave (bytes) 38310515SAli.Saidi@ARM.comsystem.membus.pkt_size::total 217760644 # Cumulative packet size per connected master and slave (bytes) 38410515SAli.Saidi@ARM.comsystem.membus.snoops 556693 # Total snoops (count) 38510515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::samples 3996553 # Request fanout histogram 38610515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 38710515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 38810515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 38910515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 39010515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::1 3996553 100.00% 100.00% # Request fanout histogram 39110515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 39210515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 39310515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 39410515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 39510515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::total 3996553 # Request fanout histogram 39610515SAli.Saidi@ARM.comsystem.membus.reqLayer0.occupancy 106711482 # Layer occupancy (ticks) 39710515SAli.Saidi@ARM.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 39810515SAli.Saidi@ARM.comsystem.membus.reqLayer1.occupancy 35984 # Layer occupancy (ticks) 39910515SAli.Saidi@ARM.comsystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 40010515SAli.Saidi@ARM.comsystem.membus.reqLayer2.occupancy 20060995 # Layer occupancy (ticks) 40110515SAli.Saidi@ARM.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 40210515SAli.Saidi@ARM.comsystem.membus.reqLayer5.occupancy 21791270978 # Layer occupancy (ticks) 40310515SAli.Saidi@ARM.comsystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 40410515SAli.Saidi@ARM.comsystem.membus.respLayer2.occupancy 13392760110 # Layer occupancy (ticks) 40510515SAli.Saidi@ARM.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 40610515SAli.Saidi@ARM.comsystem.membus.respLayer3.occupancy 187374753 # Layer occupancy (ticks) 40710515SAli.Saidi@ARM.comsystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 40810515SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 40910515SAli.Saidi@ARM.comsystem.l2c.tags.replacements 893379 # number of replacements 41010515SAli.Saidi@ARM.comsystem.l2c.tags.tagsinuse 64139.353797 # Cycle average of tags in use 41110515SAli.Saidi@ARM.comsystem.l2c.tags.total_refs 6866398 # Total number of references to valid blocks. 41210515SAli.Saidi@ARM.comsystem.l2c.tags.sampled_refs 953433 # Sample count of references to valid blocks. 41310515SAli.Saidi@ARM.comsystem.l2c.tags.avg_refs 7.201762 # Average number of references to valid blocks. 41410515SAli.Saidi@ARM.comsystem.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 41510515SAli.Saidi@ARM.comsystem.l2c.tags.occ_blocks::writebacks 10411.534254 # Average occupied blocks per requestor 41610515SAli.Saidi@ARM.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 170.665758 # Average occupied blocks per requestor 41710515SAli.Saidi@ARM.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 236.653363 # Average occupied blocks per requestor 41810515SAli.Saidi@ARM.comsystem.l2c.tags.occ_blocks::cpu0.inst 5522.014615 # Average occupied blocks per requestor 41910515SAli.Saidi@ARM.comsystem.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 25703.497535 # Average occupied blocks per requestor 42010515SAli.Saidi@ARM.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 145.004713 # Average occupied blocks per requestor 42110515SAli.Saidi@ARM.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 188.005532 # Average occupied blocks per requestor 42210515SAli.Saidi@ARM.comsystem.l2c.tags.occ_blocks::cpu1.inst 6322.307070 # Average occupied blocks per requestor 42310515SAli.Saidi@ARM.comsystem.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 15439.670958 # Average occupied blocks per requestor 42410515SAli.Saidi@ARM.comsystem.l2c.tags.occ_percent::writebacks 0.158867 # Average percentage of cache occupancy 42510515SAli.Saidi@ARM.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.002604 # Average percentage of cache occupancy 42610515SAli.Saidi@ARM.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.003611 # Average percentage of cache occupancy 42710515SAli.Saidi@ARM.comsystem.l2c.tags.occ_percent::cpu0.inst 0.084259 # Average percentage of cache occupancy 42810515SAli.Saidi@ARM.comsystem.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.392204 # Average percentage of cache occupancy 42910515SAli.Saidi@ARM.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.002213 # Average percentage of cache occupancy 43010515SAli.Saidi@ARM.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.002869 # Average percentage of cache occupancy 43110515SAli.Saidi@ARM.comsystem.l2c.tags.occ_percent::cpu1.inst 0.096471 # Average percentage of cache occupancy 43210515SAli.Saidi@ARM.comsystem.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.235591 # Average percentage of cache occupancy 43310515SAli.Saidi@ARM.comsystem.l2c.tags.occ_percent::total 0.978689 # Average percentage of cache occupancy 43410515SAli.Saidi@ARM.comsystem.l2c.tags.occ_task_id_blocks::1022 36012 # Occupied blocks per task id 43510515SAli.Saidi@ARM.comsystem.l2c.tags.occ_task_id_blocks::1023 260 # Occupied blocks per task id 43610515SAli.Saidi@ARM.comsystem.l2c.tags.occ_task_id_blocks::1024 23782 # Occupied blocks per task id 43710515SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id 43810515SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1022::1 41 # Occupied blocks per task id 43910515SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1022::2 716 # Occupied blocks per task id 44010515SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1022::3 1957 # Occupied blocks per task id 44110515SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1022::4 33290 # Occupied blocks per task id 44210515SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id 44310515SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1023::1 7 # Occupied blocks per task id 44410515SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id 44510515SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1023::3 51 # Occupied blocks per task id 44610515SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1023::4 190 # Occupied blocks per task id 44710515SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id 44810515SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1024::1 112 # Occupied blocks per task id 44910515SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1024::2 1450 # Occupied blocks per task id 45010515SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1024::3 3907 # Occupied blocks per task id 45110515SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1024::4 18298 # Occupied blocks per task id 45210515SAli.Saidi@ARM.comsystem.l2c.tags.occ_task_id_percent::1022 0.549500 # Percentage of cache occupancy per task id 45310515SAli.Saidi@ARM.comsystem.l2c.tags.occ_task_id_percent::1023 0.003967 # Percentage of cache occupancy per task id 45410515SAli.Saidi@ARM.comsystem.l2c.tags.occ_task_id_percent::1024 0.362885 # Percentage of cache occupancy per task id 45510515SAli.Saidi@ARM.comsystem.l2c.tags.tag_accesses 80317062 # Number of tag accesses 45610515SAli.Saidi@ARM.comsystem.l2c.tags.data_accesses 80317062 # Number of data accesses 45710515SAli.Saidi@ARM.comsystem.l2c.ReadReq_hits::cpu0.dtb.walker 7070 # number of ReadReq hits 45810515SAli.Saidi@ARM.comsystem.l2c.ReadReq_hits::cpu0.itb.walker 4466 # number of ReadReq hits 45910515SAli.Saidi@ARM.comsystem.l2c.ReadReq_hits::cpu0.inst 557041 # number of ReadReq hits 46010515SAli.Saidi@ARM.comsystem.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 2033838 # number of ReadReq hits 46110515SAli.Saidi@ARM.comsystem.l2c.ReadReq_hits::cpu1.dtb.walker 7318 # number of ReadReq hits 46210515SAli.Saidi@ARM.comsystem.l2c.ReadReq_hits::cpu1.itb.walker 4580 # number of ReadReq hits 46310515SAli.Saidi@ARM.comsystem.l2c.ReadReq_hits::cpu1.inst 521752 # number of ReadReq hits 46410515SAli.Saidi@ARM.comsystem.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 1881001 # number of ReadReq hits 46510515SAli.Saidi@ARM.comsystem.l2c.ReadReq_hits::total 5017066 # number of ReadReq hits 46610515SAli.Saidi@ARM.comsystem.l2c.Writeback_hits::writebacks 1844732 # number of Writeback hits 46710515SAli.Saidi@ARM.comsystem.l2c.Writeback_hits::total 1844732 # number of Writeback hits 46810515SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_hits::cpu0.inst 30097 # number of UpgradeReq hits 46910515SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_hits::cpu1.inst 27244 # number of UpgradeReq hits 47010515SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_hits::total 57341 # number of UpgradeReq hits 47110515SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_hits::cpu0.inst 7329 # number of SCUpgradeReq hits 47210515SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_hits::cpu1.inst 7124 # number of SCUpgradeReq hits 47310515SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_hits::total 14453 # number of SCUpgradeReq hits 47410515SAli.Saidi@ARM.comsystem.l2c.ReadExReq_hits::cpu0.inst 51408 # number of ReadExReq hits 47510515SAli.Saidi@ARM.comsystem.l2c.ReadExReq_hits::cpu1.inst 52005 # number of ReadExReq hits 47610515SAli.Saidi@ARM.comsystem.l2c.ReadExReq_hits::total 103413 # number of ReadExReq hits 47710515SAli.Saidi@ARM.comsystem.l2c.demand_hits::cpu0.dtb.walker 7070 # number of demand (read+write) hits 47810515SAli.Saidi@ARM.comsystem.l2c.demand_hits::cpu0.itb.walker 4466 # number of demand (read+write) hits 47910515SAli.Saidi@ARM.comsystem.l2c.demand_hits::cpu0.inst 608449 # number of demand (read+write) hits 48010515SAli.Saidi@ARM.comsystem.l2c.demand_hits::cpu0.l2cache.prefetcher 2033838 # number of demand (read+write) hits 48110515SAli.Saidi@ARM.comsystem.l2c.demand_hits::cpu1.dtb.walker 7318 # number of demand (read+write) hits 48210515SAli.Saidi@ARM.comsystem.l2c.demand_hits::cpu1.itb.walker 4580 # number of demand (read+write) hits 48310515SAli.Saidi@ARM.comsystem.l2c.demand_hits::cpu1.inst 573757 # number of demand (read+write) hits 48410515SAli.Saidi@ARM.comsystem.l2c.demand_hits::cpu1.l2cache.prefetcher 1881001 # number of demand (read+write) hits 48510515SAli.Saidi@ARM.comsystem.l2c.demand_hits::total 5120479 # number of demand (read+write) hits 48610515SAli.Saidi@ARM.comsystem.l2c.overall_hits::cpu0.dtb.walker 7070 # number of overall hits 48710515SAli.Saidi@ARM.comsystem.l2c.overall_hits::cpu0.itb.walker 4466 # number of overall hits 48810515SAli.Saidi@ARM.comsystem.l2c.overall_hits::cpu0.inst 608449 # number of overall hits 48910515SAli.Saidi@ARM.comsystem.l2c.overall_hits::cpu0.l2cache.prefetcher 2033838 # number of overall hits 49010515SAli.Saidi@ARM.comsystem.l2c.overall_hits::cpu1.dtb.walker 7318 # number of overall hits 49110515SAli.Saidi@ARM.comsystem.l2c.overall_hits::cpu1.itb.walker 4580 # number of overall hits 49210515SAli.Saidi@ARM.comsystem.l2c.overall_hits::cpu1.inst 573757 # number of overall hits 49310515SAli.Saidi@ARM.comsystem.l2c.overall_hits::cpu1.l2cache.prefetcher 1881001 # number of overall hits 49410515SAli.Saidi@ARM.comsystem.l2c.overall_hits::total 5120479 # number of overall hits 49510515SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::cpu0.dtb.walker 3788 # number of ReadReq misses 49610515SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::cpu0.itb.walker 6393 # number of ReadReq misses 49710515SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::cpu0.inst 87512 # number of ReadReq misses 49810515SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 444466 # number of ReadReq misses 49910515SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::cpu1.dtb.walker 3979 # number of ReadReq misses 50010515SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::cpu1.itb.walker 6557 # number of ReadReq misses 50110515SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::cpu1.inst 97026 # number of ReadReq misses 50210515SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 366468 # number of ReadReq misses 50310515SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::total 1016189 # number of ReadReq misses 50410515SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_misses::cpu0.inst 36620 # number of UpgradeReq misses 50510515SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_misses::cpu1.inst 34601 # number of UpgradeReq misses 50610515SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_misses::total 71221 # number of UpgradeReq misses 50710515SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_misses::cpu0.inst 9478 # number of SCUpgradeReq misses 50810515SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_misses::cpu1.inst 8512 # number of SCUpgradeReq misses 50910515SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_misses::total 17990 # number of SCUpgradeReq misses 51010515SAli.Saidi@ARM.comsystem.l2c.ReadExReq_misses::cpu0.inst 69660 # number of ReadExReq misses 51110515SAli.Saidi@ARM.comsystem.l2c.ReadExReq_misses::cpu1.inst 65667 # number of ReadExReq misses 51210515SAli.Saidi@ARM.comsystem.l2c.ReadExReq_misses::total 135327 # number of ReadExReq misses 51310515SAli.Saidi@ARM.comsystem.l2c.demand_misses::cpu0.dtb.walker 3788 # number of demand (read+write) misses 51410515SAli.Saidi@ARM.comsystem.l2c.demand_misses::cpu0.itb.walker 6393 # number of demand (read+write) misses 51510515SAli.Saidi@ARM.comsystem.l2c.demand_misses::cpu0.inst 157172 # number of demand (read+write) misses 51610515SAli.Saidi@ARM.comsystem.l2c.demand_misses::cpu0.l2cache.prefetcher 444466 # number of demand (read+write) misses 51710515SAli.Saidi@ARM.comsystem.l2c.demand_misses::cpu1.dtb.walker 3979 # number of demand (read+write) misses 51810515SAli.Saidi@ARM.comsystem.l2c.demand_misses::cpu1.itb.walker 6557 # number of demand (read+write) misses 51910515SAli.Saidi@ARM.comsystem.l2c.demand_misses::cpu1.inst 162693 # number of demand (read+write) misses 52010515SAli.Saidi@ARM.comsystem.l2c.demand_misses::cpu1.l2cache.prefetcher 366468 # number of demand (read+write) misses 52110515SAli.Saidi@ARM.comsystem.l2c.demand_misses::total 1151516 # number of demand (read+write) misses 52210515SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu0.dtb.walker 3788 # number of overall misses 52310515SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu0.itb.walker 6393 # number of overall misses 52410515SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu0.inst 157172 # number of overall misses 52510515SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu0.l2cache.prefetcher 444466 # number of overall misses 52610515SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu1.dtb.walker 3979 # number of overall misses 52710515SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu1.itb.walker 6557 # number of overall misses 52810515SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu1.inst 162693 # number of overall misses 52910515SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu1.l2cache.prefetcher 366468 # number of overall misses 53010515SAli.Saidi@ARM.comsystem.l2c.overall_misses::total 1151516 # number of overall misses 53110515SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_latency::cpu0.dtb.walker 295641239 # number of ReadReq miss cycles 53210515SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_latency::cpu0.itb.walker 507564744 # number of ReadReq miss cycles 53310515SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_latency::cpu0.inst 6935191428 # number of ReadReq miss cycles 53410515SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 45326284922 # number of ReadReq miss cycles 53510515SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_latency::cpu1.dtb.walker 312400496 # number of ReadReq miss cycles 53610515SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_latency::cpu1.itb.walker 512318742 # number of ReadReq miss cycles 53710515SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_latency::cpu1.inst 7688372365 # number of ReadReq miss cycles 53810515SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 38103566034 # number of ReadReq miss cycles 53910515SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_latency::total 99681339970 # number of ReadReq miss cycles 54010515SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_miss_latency::cpu0.inst 177719564 # number of UpgradeReq miss cycles 54110515SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_miss_latency::cpu1.inst 161535756 # number of UpgradeReq miss cycles 54210515SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_miss_latency::total 339255320 # number of UpgradeReq miss cycles 54310515SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_miss_latency::cpu0.inst 49426933 # number of SCUpgradeReq miss cycles 54410515SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_miss_latency::cpu1.inst 49799411 # number of SCUpgradeReq miss cycles 54510515SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_miss_latency::total 99226344 # number of SCUpgradeReq miss cycles 54610515SAli.Saidi@ARM.comsystem.l2c.ReadExReq_miss_latency::cpu0.inst 5124274653 # number of ReadExReq miss cycles 54710515SAli.Saidi@ARM.comsystem.l2c.ReadExReq_miss_latency::cpu1.inst 4787449538 # number of ReadExReq miss cycles 54810515SAli.Saidi@ARM.comsystem.l2c.ReadExReq_miss_latency::total 9911724191 # number of ReadExReq miss cycles 54910515SAli.Saidi@ARM.comsystem.l2c.demand_miss_latency::cpu0.dtb.walker 295641239 # number of demand (read+write) miss cycles 55010515SAli.Saidi@ARM.comsystem.l2c.demand_miss_latency::cpu0.itb.walker 507564744 # number of demand (read+write) miss cycles 55110515SAli.Saidi@ARM.comsystem.l2c.demand_miss_latency::cpu0.inst 12059466081 # number of demand (read+write) miss cycles 55210515SAli.Saidi@ARM.comsystem.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 45326284922 # number of demand (read+write) miss cycles 55310515SAli.Saidi@ARM.comsystem.l2c.demand_miss_latency::cpu1.dtb.walker 312400496 # number of demand (read+write) miss cycles 55410515SAli.Saidi@ARM.comsystem.l2c.demand_miss_latency::cpu1.itb.walker 512318742 # number of demand (read+write) miss cycles 55510515SAli.Saidi@ARM.comsystem.l2c.demand_miss_latency::cpu1.inst 12475821903 # number of demand (read+write) miss cycles 55610515SAli.Saidi@ARM.comsystem.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 38103566034 # number of demand (read+write) miss cycles 55710515SAli.Saidi@ARM.comsystem.l2c.demand_miss_latency::total 109593064161 # number of demand (read+write) miss cycles 55810515SAli.Saidi@ARM.comsystem.l2c.overall_miss_latency::cpu0.dtb.walker 295641239 # number of overall miss cycles 55910515SAli.Saidi@ARM.comsystem.l2c.overall_miss_latency::cpu0.itb.walker 507564744 # number of overall miss cycles 56010515SAli.Saidi@ARM.comsystem.l2c.overall_miss_latency::cpu0.inst 12059466081 # number of overall miss cycles 56110515SAli.Saidi@ARM.comsystem.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 45326284922 # number of overall miss cycles 56210515SAli.Saidi@ARM.comsystem.l2c.overall_miss_latency::cpu1.dtb.walker 312400496 # number of overall miss cycles 56310515SAli.Saidi@ARM.comsystem.l2c.overall_miss_latency::cpu1.itb.walker 512318742 # number of overall miss cycles 56410515SAli.Saidi@ARM.comsystem.l2c.overall_miss_latency::cpu1.inst 12475821903 # number of overall miss cycles 56510515SAli.Saidi@ARM.comsystem.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 38103566034 # number of overall miss cycles 56610515SAli.Saidi@ARM.comsystem.l2c.overall_miss_latency::total 109593064161 # number of overall miss cycles 56710515SAli.Saidi@ARM.comsystem.l2c.ReadReq_accesses::cpu0.dtb.walker 10858 # number of ReadReq accesses(hits+misses) 56810515SAli.Saidi@ARM.comsystem.l2c.ReadReq_accesses::cpu0.itb.walker 10859 # number of ReadReq accesses(hits+misses) 56910515SAli.Saidi@ARM.comsystem.l2c.ReadReq_accesses::cpu0.inst 644553 # number of ReadReq accesses(hits+misses) 57010515SAli.Saidi@ARM.comsystem.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 2478304 # number of ReadReq accesses(hits+misses) 57110515SAli.Saidi@ARM.comsystem.l2c.ReadReq_accesses::cpu1.dtb.walker 11297 # number of ReadReq accesses(hits+misses) 57210515SAli.Saidi@ARM.comsystem.l2c.ReadReq_accesses::cpu1.itb.walker 11137 # number of ReadReq accesses(hits+misses) 57310515SAli.Saidi@ARM.comsystem.l2c.ReadReq_accesses::cpu1.inst 618778 # number of ReadReq accesses(hits+misses) 57410515SAli.Saidi@ARM.comsystem.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 2247469 # number of ReadReq accesses(hits+misses) 57510515SAli.Saidi@ARM.comsystem.l2c.ReadReq_accesses::total 6033255 # number of ReadReq accesses(hits+misses) 57610515SAli.Saidi@ARM.comsystem.l2c.Writeback_accesses::writebacks 1844732 # number of Writeback accesses(hits+misses) 57710515SAli.Saidi@ARM.comsystem.l2c.Writeback_accesses::total 1844732 # number of Writeback accesses(hits+misses) 57810515SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_accesses::cpu0.inst 66717 # number of UpgradeReq accesses(hits+misses) 57910515SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_accesses::cpu1.inst 61845 # number of UpgradeReq accesses(hits+misses) 58010515SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_accesses::total 128562 # number of UpgradeReq accesses(hits+misses) 58110515SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_accesses::cpu0.inst 16807 # number of SCUpgradeReq accesses(hits+misses) 58210515SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_accesses::cpu1.inst 15636 # number of SCUpgradeReq accesses(hits+misses) 58310515SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_accesses::total 32443 # number of SCUpgradeReq accesses(hits+misses) 58410515SAli.Saidi@ARM.comsystem.l2c.ReadExReq_accesses::cpu0.inst 121068 # number of ReadExReq accesses(hits+misses) 58510515SAli.Saidi@ARM.comsystem.l2c.ReadExReq_accesses::cpu1.inst 117672 # number of ReadExReq accesses(hits+misses) 58610515SAli.Saidi@ARM.comsystem.l2c.ReadExReq_accesses::total 238740 # number of ReadExReq accesses(hits+misses) 58710515SAli.Saidi@ARM.comsystem.l2c.demand_accesses::cpu0.dtb.walker 10858 # number of demand (read+write) accesses 58810515SAli.Saidi@ARM.comsystem.l2c.demand_accesses::cpu0.itb.walker 10859 # number of demand (read+write) accesses 58910515SAli.Saidi@ARM.comsystem.l2c.demand_accesses::cpu0.inst 765621 # number of demand (read+write) accesses 59010515SAli.Saidi@ARM.comsystem.l2c.demand_accesses::cpu0.l2cache.prefetcher 2478304 # number of demand (read+write) accesses 59110515SAli.Saidi@ARM.comsystem.l2c.demand_accesses::cpu1.dtb.walker 11297 # number of demand (read+write) accesses 59210515SAli.Saidi@ARM.comsystem.l2c.demand_accesses::cpu1.itb.walker 11137 # number of demand (read+write) accesses 59310515SAli.Saidi@ARM.comsystem.l2c.demand_accesses::cpu1.inst 736450 # number of demand (read+write) accesses 59410515SAli.Saidi@ARM.comsystem.l2c.demand_accesses::cpu1.l2cache.prefetcher 2247469 # number of demand (read+write) accesses 59510515SAli.Saidi@ARM.comsystem.l2c.demand_accesses::total 6271995 # number of demand (read+write) accesses 59610515SAli.Saidi@ARM.comsystem.l2c.overall_accesses::cpu0.dtb.walker 10858 # number of overall (read+write) accesses 59710515SAli.Saidi@ARM.comsystem.l2c.overall_accesses::cpu0.itb.walker 10859 # number of overall (read+write) accesses 59810515SAli.Saidi@ARM.comsystem.l2c.overall_accesses::cpu0.inst 765621 # number of overall (read+write) accesses 59910515SAli.Saidi@ARM.comsystem.l2c.overall_accesses::cpu0.l2cache.prefetcher 2478304 # number of overall (read+write) accesses 60010515SAli.Saidi@ARM.comsystem.l2c.overall_accesses::cpu1.dtb.walker 11297 # number of overall (read+write) accesses 60110515SAli.Saidi@ARM.comsystem.l2c.overall_accesses::cpu1.itb.walker 11137 # number of overall (read+write) accesses 60210515SAli.Saidi@ARM.comsystem.l2c.overall_accesses::cpu1.inst 736450 # number of overall (read+write) accesses 60310515SAli.Saidi@ARM.comsystem.l2c.overall_accesses::cpu1.l2cache.prefetcher 2247469 # number of overall (read+write) accesses 60410515SAli.Saidi@ARM.comsystem.l2c.overall_accesses::total 6271995 # number of overall (read+write) accesses 60510515SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.348867 # miss rate for ReadReq accesses 60610515SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.588728 # miss rate for ReadReq accesses 60710515SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::cpu0.inst 0.135772 # miss rate for ReadReq accesses 60810515SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.179343 # miss rate for ReadReq accesses 60910515SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.352217 # miss rate for ReadReq accesses 61010515SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.588758 # miss rate for ReadReq accesses 61110515SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::cpu1.inst 0.156803 # miss rate for ReadReq accesses 61210515SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.163058 # miss rate for ReadReq accesses 61310515SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::total 0.168431 # miss rate for ReadReq accesses 61410515SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_miss_rate::cpu0.inst 0.548886 # miss rate for UpgradeReq accesses 61510515SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_miss_rate::cpu1.inst 0.559479 # miss rate for UpgradeReq accesses 61610515SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_miss_rate::total 0.553982 # miss rate for UpgradeReq accesses 61710515SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.563932 # miss rate for SCUpgradeReq accesses 61810515SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.544385 # miss rate for SCUpgradeReq accesses 61910515SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.554511 # miss rate for SCUpgradeReq accesses 62010515SAli.Saidi@ARM.comsystem.l2c.ReadExReq_miss_rate::cpu0.inst 0.575379 # miss rate for ReadExReq accesses 62110515SAli.Saidi@ARM.comsystem.l2c.ReadExReq_miss_rate::cpu1.inst 0.558051 # miss rate for ReadExReq accesses 62210515SAli.Saidi@ARM.comsystem.l2c.ReadExReq_miss_rate::total 0.566838 # miss rate for ReadExReq accesses 62310515SAli.Saidi@ARM.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.348867 # miss rate for demand accesses 62410515SAli.Saidi@ARM.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.588728 # miss rate for demand accesses 62510515SAli.Saidi@ARM.comsystem.l2c.demand_miss_rate::cpu0.inst 0.205287 # miss rate for demand accesses 62610515SAli.Saidi@ARM.comsystem.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.179343 # miss rate for demand accesses 62710515SAli.Saidi@ARM.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.352217 # miss rate for demand accesses 62810515SAli.Saidi@ARM.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.588758 # miss rate for demand accesses 62910515SAli.Saidi@ARM.comsystem.l2c.demand_miss_rate::cpu1.inst 0.220915 # miss rate for demand accesses 63010515SAli.Saidi@ARM.comsystem.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.163058 # miss rate for demand accesses 63110515SAli.Saidi@ARM.comsystem.l2c.demand_miss_rate::total 0.183596 # miss rate for demand accesses 63210515SAli.Saidi@ARM.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.348867 # miss rate for overall accesses 63310515SAli.Saidi@ARM.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.588728 # miss rate for overall accesses 63410515SAli.Saidi@ARM.comsystem.l2c.overall_miss_rate::cpu0.inst 0.205287 # miss rate for overall accesses 63510515SAli.Saidi@ARM.comsystem.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.179343 # miss rate for overall accesses 63610515SAli.Saidi@ARM.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.352217 # miss rate for overall accesses 63710515SAli.Saidi@ARM.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.588758 # miss rate for overall accesses 63810515SAli.Saidi@ARM.comsystem.l2c.overall_miss_rate::cpu1.inst 0.220915 # miss rate for overall accesses 63910515SAli.Saidi@ARM.comsystem.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.163058 # miss rate for overall accesses 64010515SAli.Saidi@ARM.comsystem.l2c.overall_miss_rate::total 0.183596 # miss rate for overall accesses 64110515SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 78046.789599 # average ReadReq miss latency 64210515SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 79393.828250 # average ReadReq miss latency 64310515SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_miss_latency::cpu0.inst 79248.462245 # average ReadReq miss latency 64410515SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 101979.195084 # average ReadReq miss latency 64510515SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 78512.313647 # average ReadReq miss latency 64610515SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 78133.100808 # average ReadReq miss latency 64710515SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_miss_latency::cpu1.inst 79240.331097 # average ReadReq miss latency 64810515SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 103975.152084 # average ReadReq miss latency 64910515SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_miss_latency::total 98093.307416 # average ReadReq miss latency 65010515SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 4853.073839 # average UpgradeReq miss latency 65110515SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 4668.528540 # average UpgradeReq miss latency 65210515SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_avg_miss_latency::total 4763.416970 # average UpgradeReq miss latency 65310515SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 5214.911690 # average SCUpgradeReq miss latency 65410515SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 5850.494713 # average SCUpgradeReq miss latency 65510515SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_avg_miss_latency::total 5515.638911 # average SCUpgradeReq miss latency 65610515SAli.Saidi@ARM.comsystem.l2c.ReadExReq_avg_miss_latency::cpu0.inst 73561.220973 # average ReadExReq miss latency 65710515SAli.Saidi@ARM.comsystem.l2c.ReadExReq_avg_miss_latency::cpu1.inst 72904.952838 # average ReadExReq miss latency 65810515SAli.Saidi@ARM.comsystem.l2c.ReadExReq_avg_miss_latency::total 73242.768930 # average ReadExReq miss latency 65910515SAli.Saidi@ARM.comsystem.l2c.demand_avg_miss_latency::cpu0.dtb.walker 78046.789599 # average overall miss latency 66010515SAli.Saidi@ARM.comsystem.l2c.demand_avg_miss_latency::cpu0.itb.walker 79393.828250 # average overall miss latency 66110515SAli.Saidi@ARM.comsystem.l2c.demand_avg_miss_latency::cpu0.inst 76727.827355 # average overall miss latency 66210515SAli.Saidi@ARM.comsystem.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 101979.195084 # average overall miss latency 66310515SAli.Saidi@ARM.comsystem.l2c.demand_avg_miss_latency::cpu1.dtb.walker 78512.313647 # average overall miss latency 66410515SAli.Saidi@ARM.comsystem.l2c.demand_avg_miss_latency::cpu1.itb.walker 78133.100808 # average overall miss latency 66510515SAli.Saidi@ARM.comsystem.l2c.demand_avg_miss_latency::cpu1.inst 76683.212572 # average overall miss latency 66610515SAli.Saidi@ARM.comsystem.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 103975.152084 # average overall miss latency 66710515SAli.Saidi@ARM.comsystem.l2c.demand_avg_miss_latency::total 95172.854012 # average overall miss latency 66810515SAli.Saidi@ARM.comsystem.l2c.overall_avg_miss_latency::cpu0.dtb.walker 78046.789599 # average overall miss latency 66910515SAli.Saidi@ARM.comsystem.l2c.overall_avg_miss_latency::cpu0.itb.walker 79393.828250 # average overall miss latency 67010515SAli.Saidi@ARM.comsystem.l2c.overall_avg_miss_latency::cpu0.inst 76727.827355 # average overall miss latency 67110515SAli.Saidi@ARM.comsystem.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 101979.195084 # average overall miss latency 67210515SAli.Saidi@ARM.comsystem.l2c.overall_avg_miss_latency::cpu1.dtb.walker 78512.313647 # average overall miss latency 67310515SAli.Saidi@ARM.comsystem.l2c.overall_avg_miss_latency::cpu1.itb.walker 78133.100808 # average overall miss latency 67410515SAli.Saidi@ARM.comsystem.l2c.overall_avg_miss_latency::cpu1.inst 76683.212572 # average overall miss latency 67510515SAli.Saidi@ARM.comsystem.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 103975.152084 # average overall miss latency 67610515SAli.Saidi@ARM.comsystem.l2c.overall_avg_miss_latency::total 95172.854012 # average overall miss latency 67710515SAli.Saidi@ARM.comsystem.l2c.blocked_cycles::no_mshrs 9985 # number of cycles access was blocked 67810515SAli.Saidi@ARM.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 67910515SAli.Saidi@ARM.comsystem.l2c.blocked::no_mshrs 293 # number of cycles access was blocked 68010515SAli.Saidi@ARM.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 68110515SAli.Saidi@ARM.comsystem.l2c.avg_blocked_cycles::no_mshrs 34.078498 # average number of cycles each access was blocked 68210515SAli.Saidi@ARM.comsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 68310515SAli.Saidi@ARM.comsystem.l2c.fast_writes 0 # number of fast writes performed 68410515SAli.Saidi@ARM.comsystem.l2c.cache_copies 0 # number of cache copies performed 68510515SAli.Saidi@ARM.comsystem.l2c.writebacks::writebacks 526915 # number of writebacks 68610515SAli.Saidi@ARM.comsystem.l2c.writebacks::total 526915 # number of writebacks 68710515SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_hits::cpu0.inst 41 # number of ReadReq MSHR hits 68810515SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 208 # number of ReadReq MSHR hits 68910515SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_hits::cpu1.inst 31 # number of ReadReq MSHR hits 69010515SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 190 # number of ReadReq MSHR hits 69110515SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_hits::total 470 # number of ReadReq MSHR hits 69210515SAli.Saidi@ARM.comsystem.l2c.demand_mshr_hits::cpu0.inst 41 # number of demand (read+write) MSHR hits 69310515SAli.Saidi@ARM.comsystem.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 208 # number of demand (read+write) MSHR hits 69410515SAli.Saidi@ARM.comsystem.l2c.demand_mshr_hits::cpu1.inst 31 # number of demand (read+write) MSHR hits 69510515SAli.Saidi@ARM.comsystem.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 190 # number of demand (read+write) MSHR hits 69610515SAli.Saidi@ARM.comsystem.l2c.demand_mshr_hits::total 470 # number of demand (read+write) MSHR hits 69710515SAli.Saidi@ARM.comsystem.l2c.overall_mshr_hits::cpu0.inst 41 # number of overall MSHR hits 69810515SAli.Saidi@ARM.comsystem.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 208 # number of overall MSHR hits 69910515SAli.Saidi@ARM.comsystem.l2c.overall_mshr_hits::cpu1.inst 31 # number of overall MSHR hits 70010515SAli.Saidi@ARM.comsystem.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 190 # number of overall MSHR hits 70110515SAli.Saidi@ARM.comsystem.l2c.overall_mshr_hits::total 470 # number of overall MSHR hits 70210515SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 3788 # number of ReadReq MSHR misses 70310515SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_misses::cpu0.itb.walker 6393 # number of ReadReq MSHR misses 70410515SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_misses::cpu0.inst 87471 # number of ReadReq MSHR misses 70510515SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 444258 # number of ReadReq MSHR misses 70610515SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 3979 # number of ReadReq MSHR misses 70710515SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_misses::cpu1.itb.walker 6557 # number of ReadReq MSHR misses 70810515SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_misses::cpu1.inst 96995 # number of ReadReq MSHR misses 70910515SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 366278 # number of ReadReq MSHR misses 71010515SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_misses::total 1015719 # number of ReadReq MSHR misses 71110515SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_mshr_misses::cpu0.inst 36620 # number of UpgradeReq MSHR misses 71210515SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_mshr_misses::cpu1.inst 34601 # number of UpgradeReq MSHR misses 71310515SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_mshr_misses::total 71221 # number of UpgradeReq MSHR misses 71410515SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 9478 # number of SCUpgradeReq MSHR misses 71510515SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 8512 # number of SCUpgradeReq MSHR misses 71610515SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_mshr_misses::total 17990 # number of SCUpgradeReq MSHR misses 71710515SAli.Saidi@ARM.comsystem.l2c.ReadExReq_mshr_misses::cpu0.inst 69660 # number of ReadExReq MSHR misses 71810515SAli.Saidi@ARM.comsystem.l2c.ReadExReq_mshr_misses::cpu1.inst 65667 # number of ReadExReq MSHR misses 71910515SAli.Saidi@ARM.comsystem.l2c.ReadExReq_mshr_misses::total 135327 # number of ReadExReq MSHR misses 72010515SAli.Saidi@ARM.comsystem.l2c.demand_mshr_misses::cpu0.dtb.walker 3788 # number of demand (read+write) MSHR misses 72110515SAli.Saidi@ARM.comsystem.l2c.demand_mshr_misses::cpu0.itb.walker 6393 # number of demand (read+write) MSHR misses 72210515SAli.Saidi@ARM.comsystem.l2c.demand_mshr_misses::cpu0.inst 157131 # number of demand (read+write) MSHR misses 72310515SAli.Saidi@ARM.comsystem.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 444258 # number of demand (read+write) MSHR misses 72410515SAli.Saidi@ARM.comsystem.l2c.demand_mshr_misses::cpu1.dtb.walker 3979 # number of demand (read+write) MSHR misses 72510515SAli.Saidi@ARM.comsystem.l2c.demand_mshr_misses::cpu1.itb.walker 6557 # number of demand (read+write) MSHR misses 72610515SAli.Saidi@ARM.comsystem.l2c.demand_mshr_misses::cpu1.inst 162662 # number of demand (read+write) MSHR misses 72710515SAli.Saidi@ARM.comsystem.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 366278 # number of demand (read+write) MSHR misses 72810515SAli.Saidi@ARM.comsystem.l2c.demand_mshr_misses::total 1151046 # number of demand (read+write) MSHR misses 72910515SAli.Saidi@ARM.comsystem.l2c.overall_mshr_misses::cpu0.dtb.walker 3788 # number of overall MSHR misses 73010515SAli.Saidi@ARM.comsystem.l2c.overall_mshr_misses::cpu0.itb.walker 6393 # number of overall MSHR misses 73110515SAli.Saidi@ARM.comsystem.l2c.overall_mshr_misses::cpu0.inst 157131 # number of overall MSHR misses 73210515SAli.Saidi@ARM.comsystem.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 444258 # number of overall MSHR misses 73310515SAli.Saidi@ARM.comsystem.l2c.overall_mshr_misses::cpu1.dtb.walker 3979 # number of overall MSHR misses 73410515SAli.Saidi@ARM.comsystem.l2c.overall_mshr_misses::cpu1.itb.walker 6557 # number of overall MSHR misses 73510515SAli.Saidi@ARM.comsystem.l2c.overall_mshr_misses::cpu1.inst 162662 # number of overall MSHR misses 73610515SAli.Saidi@ARM.comsystem.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 366278 # number of overall MSHR misses 73710515SAli.Saidi@ARM.comsystem.l2c.overall_mshr_misses::total 1151046 # number of overall MSHR misses 73810515SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 248599239 # number of ReadReq MSHR miss cycles 73910515SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 428022244 # number of ReadReq MSHR miss cycles 74010515SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_miss_latency::cpu0.inst 5837610680 # number of ReadReq MSHR miss cycles 74110515SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 39831799422 # number of ReadReq MSHR miss cycles 74210515SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 262923496 # number of ReadReq MSHR miss cycles 74310515SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 430600242 # number of ReadReq MSHR miss cycles 74410515SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_miss_latency::cpu1.inst 6471220731 # number of ReadReq MSHR miss cycles 74510515SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 33572512037 # number of ReadReq MSHR miss cycles 74610515SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_miss_latency::total 87083288091 # number of ReadReq MSHR miss cycles 74710515SAli.Saidi@ARM.comsystem.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 17889181875 # number of WriteInvalidateReq MSHR miss cycles 74810515SAli.Saidi@ARM.comsystem.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.inst 13903512484 # number of WriteInvalidateReq MSHR miss cycles 74910515SAli.Saidi@ARM.comsystem.l2c.WriteInvalidateReq_mshr_miss_latency::total 31792694359 # number of WriteInvalidateReq MSHR miss cycles 75010515SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 372768590 # number of UpgradeReq MSHR miss cycles 75110515SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 351692080 # number of UpgradeReq MSHR miss cycles 75210515SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_mshr_miss_latency::total 724460670 # number of UpgradeReq MSHR miss cycles 75310515SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 96695300 # number of SCUpgradeReq MSHR miss cycles 75410515SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 86940850 # number of SCUpgradeReq MSHR miss cycles 75510515SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::total 183636150 # number of SCUpgradeReq MSHR miss cycles 75610515SAli.Saidi@ARM.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 4247852269 # number of ReadExReq MSHR miss cycles 75710515SAli.Saidi@ARM.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 3960733380 # number of ReadExReq MSHR miss cycles 75810515SAli.Saidi@ARM.comsystem.l2c.ReadExReq_mshr_miss_latency::total 8208585649 # number of ReadExReq MSHR miss cycles 75910515SAli.Saidi@ARM.comsystem.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 248599239 # number of demand (read+write) MSHR miss cycles 76010515SAli.Saidi@ARM.comsystem.l2c.demand_mshr_miss_latency::cpu0.itb.walker 428022244 # number of demand (read+write) MSHR miss cycles 76110515SAli.Saidi@ARM.comsystem.l2c.demand_mshr_miss_latency::cpu0.inst 10085462949 # number of demand (read+write) MSHR miss cycles 76210515SAli.Saidi@ARM.comsystem.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 39831799422 # number of demand (read+write) MSHR miss cycles 76310515SAli.Saidi@ARM.comsystem.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 262923496 # number of demand (read+write) MSHR miss cycles 76410515SAli.Saidi@ARM.comsystem.l2c.demand_mshr_miss_latency::cpu1.itb.walker 430600242 # number of demand (read+write) MSHR miss cycles 76510515SAli.Saidi@ARM.comsystem.l2c.demand_mshr_miss_latency::cpu1.inst 10431954111 # number of demand (read+write) MSHR miss cycles 76610515SAli.Saidi@ARM.comsystem.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 33572512037 # number of demand (read+write) MSHR miss cycles 76710515SAli.Saidi@ARM.comsystem.l2c.demand_mshr_miss_latency::total 95291873740 # number of demand (read+write) MSHR miss cycles 76810515SAli.Saidi@ARM.comsystem.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 248599239 # number of overall MSHR miss cycles 76910515SAli.Saidi@ARM.comsystem.l2c.overall_mshr_miss_latency::cpu0.itb.walker 428022244 # number of overall MSHR miss cycles 77010515SAli.Saidi@ARM.comsystem.l2c.overall_mshr_miss_latency::cpu0.inst 10085462949 # number of overall MSHR miss cycles 77110515SAli.Saidi@ARM.comsystem.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 39831799422 # number of overall MSHR miss cycles 77210515SAli.Saidi@ARM.comsystem.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 262923496 # number of overall MSHR miss cycles 77310515SAli.Saidi@ARM.comsystem.l2c.overall_mshr_miss_latency::cpu1.itb.walker 430600242 # number of overall MSHR miss cycles 77410515SAli.Saidi@ARM.comsystem.l2c.overall_mshr_miss_latency::cpu1.inst 10431954111 # number of overall MSHR miss cycles 77510515SAli.Saidi@ARM.comsystem.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 33572512037 # number of overall MSHR miss cycles 77610515SAli.Saidi@ARM.comsystem.l2c.overall_mshr_miss_latency::total 95291873740 # number of overall MSHR miss cycles 77710515SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 4946669501 # number of ReadReq MSHR uncacheable cycles 77810515SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3170681000 # number of ReadReq MSHR uncacheable cycles 77910515SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_uncacheable_latency::total 8117350501 # number of ReadReq MSHR uncacheable cycles 78010515SAli.Saidi@ARM.comsystem.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 2118382500 # number of WriteReq MSHR uncacheable cycles 78110515SAli.Saidi@ARM.comsystem.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 3125324001 # number of WriteReq MSHR uncacheable cycles 78210515SAli.Saidi@ARM.comsystem.l2c.WriteReq_mshr_uncacheable_latency::total 5243706501 # number of WriteReq MSHR uncacheable cycles 78310515SAli.Saidi@ARM.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.inst 7065052001 # number of overall MSHR uncacheable cycles 78410515SAli.Saidi@ARM.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6296005001 # number of overall MSHR uncacheable cycles 78510515SAli.Saidi@ARM.comsystem.l2c.overall_mshr_uncacheable_latency::total 13361057002 # number of overall MSHR uncacheable cycles 78610515SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.348867 # mshr miss rate for ReadReq accesses 78710515SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.588728 # mshr miss rate for ReadReq accesses 78810515SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.135708 # mshr miss rate for ReadReq accesses 78910515SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.179259 # mshr miss rate for ReadReq accesses 79010515SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.352217 # mshr miss rate for ReadReq accesses 79110515SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.588758 # mshr miss rate for ReadReq accesses 79210515SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.156753 # mshr miss rate for ReadReq accesses 79310515SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.162974 # mshr miss rate for ReadReq accesses 79410515SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_miss_rate::total 0.168353 # mshr miss rate for ReadReq accesses 79510515SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.548886 # mshr miss rate for UpgradeReq accesses 79610515SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.559479 # mshr miss rate for UpgradeReq accesses 79710515SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_mshr_miss_rate::total 0.553982 # mshr miss rate for UpgradeReq accesses 79810515SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.563932 # mshr miss rate for SCUpgradeReq accesses 79910515SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.544385 # mshr miss rate for SCUpgradeReq accesses 80010515SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::total 0.554511 # mshr miss rate for SCUpgradeReq accesses 80110515SAli.Saidi@ARM.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.575379 # mshr miss rate for ReadExReq accesses 80210515SAli.Saidi@ARM.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.558051 # mshr miss rate for ReadExReq accesses 80310515SAli.Saidi@ARM.comsystem.l2c.ReadExReq_mshr_miss_rate::total 0.566838 # mshr miss rate for ReadExReq accesses 80410515SAli.Saidi@ARM.comsystem.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.348867 # mshr miss rate for demand accesses 80510515SAli.Saidi@ARM.comsystem.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.588728 # mshr miss rate for demand accesses 80610515SAli.Saidi@ARM.comsystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.205233 # mshr miss rate for demand accesses 80710515SAli.Saidi@ARM.comsystem.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.179259 # mshr miss rate for demand accesses 80810515SAli.Saidi@ARM.comsystem.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.352217 # mshr miss rate for demand accesses 80910515SAli.Saidi@ARM.comsystem.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.588758 # mshr miss rate for demand accesses 81010515SAli.Saidi@ARM.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.220873 # mshr miss rate for demand accesses 81110515SAli.Saidi@ARM.comsystem.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.162974 # mshr miss rate for demand accesses 81210515SAli.Saidi@ARM.comsystem.l2c.demand_mshr_miss_rate::total 0.183522 # mshr miss rate for demand accesses 81310515SAli.Saidi@ARM.comsystem.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.348867 # mshr miss rate for overall accesses 81410515SAli.Saidi@ARM.comsystem.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.588728 # mshr miss rate for overall accesses 81510515SAli.Saidi@ARM.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.205233 # mshr miss rate for overall accesses 81610515SAli.Saidi@ARM.comsystem.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.179259 # mshr miss rate for overall accesses 81710515SAli.Saidi@ARM.comsystem.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.352217 # mshr miss rate for overall accesses 81810515SAli.Saidi@ARM.comsystem.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.588758 # mshr miss rate for overall accesses 81910515SAli.Saidi@ARM.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.220873 # mshr miss rate for overall accesses 82010515SAli.Saidi@ARM.comsystem.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.162974 # mshr miss rate for overall accesses 82110515SAli.Saidi@ARM.comsystem.l2c.overall_mshr_miss_rate::total 0.183522 # mshr miss rate for overall accesses 82210515SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 65628.098997 # average ReadReq mshr miss latency 82310515SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 66951.704051 # average ReadReq mshr miss latency 82410515SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 66737.669399 # average ReadReq mshr miss latency 82510515SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 89659.160717 # average ReadReq mshr miss latency 82610515SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66077.782357 # average ReadReq mshr miss latency 82710515SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 65670.312948 # average ReadReq mshr miss latency 82810515SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 66717.054807 # average ReadReq mshr miss latency 82910515SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 91658.554532 # average ReadReq mshr miss latency 83010515SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_mshr_miss_latency::total 85735.610037 # average ReadReq mshr miss latency 83110515SAli.Saidi@ARM.comsystem.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst inf # average WriteInvalidateReq mshr miss latency 83210515SAli.Saidi@ARM.comsystem.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst inf # average WriteInvalidateReq mshr miss latency 83310515SAli.Saidi@ARM.comsystem.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 83410515SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10179.371655 # average UpgradeReq mshr miss latency 83510515SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10164.217219 # average UpgradeReq mshr miss latency 83610515SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 10172.009239 # average UpgradeReq mshr miss latency 83710515SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10202.078498 # average SCUpgradeReq mshr miss latency 83810515SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10213.915648 # average SCUpgradeReq mshr miss latency 83910515SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10207.679266 # average SCUpgradeReq mshr miss latency 84010515SAli.Saidi@ARM.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 60979.791401 # average ReadExReq mshr miss latency 84110515SAli.Saidi@ARM.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 60315.430582 # average ReadExReq mshr miss latency 84210515SAli.Saidi@ARM.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 60657.412408 # average ReadExReq mshr miss latency 84310515SAli.Saidi@ARM.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 65628.098997 # average overall mshr miss latency 84410515SAli.Saidi@ARM.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 66951.704051 # average overall mshr miss latency 84510515SAli.Saidi@ARM.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64185.061821 # average overall mshr miss latency 84610515SAli.Saidi@ARM.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 89659.160717 # average overall mshr miss latency 84710515SAli.Saidi@ARM.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66077.782357 # average overall mshr miss latency 84810515SAli.Saidi@ARM.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 65670.312948 # average overall mshr miss latency 84910515SAli.Saidi@ARM.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64132.705309 # average overall mshr miss latency 85010515SAli.Saidi@ARM.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 91658.554532 # average overall mshr miss latency 85110515SAli.Saidi@ARM.comsystem.l2c.demand_avg_mshr_miss_latency::total 82787.198548 # average overall mshr miss latency 85210515SAli.Saidi@ARM.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 65628.098997 # average overall mshr miss latency 85310515SAli.Saidi@ARM.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 66951.704051 # average overall mshr miss latency 85410515SAli.Saidi@ARM.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64185.061821 # average overall mshr miss latency 85510515SAli.Saidi@ARM.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 89659.160717 # average overall mshr miss latency 85610515SAli.Saidi@ARM.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66077.782357 # average overall mshr miss latency 85710515SAli.Saidi@ARM.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 65670.312948 # average overall mshr miss latency 85810515SAli.Saidi@ARM.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64132.705309 # average overall mshr miss latency 85910515SAli.Saidi@ARM.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 91658.554532 # average overall mshr miss latency 86010515SAli.Saidi@ARM.comsystem.l2c.overall_avg_mshr_miss_latency::total 82787.198548 # average overall mshr miss latency 86110515SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 86210515SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 86310515SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 86410515SAli.Saidi@ARM.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 86510515SAli.Saidi@ARM.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 86610515SAli.Saidi@ARM.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 86710515SAli.Saidi@ARM.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 86810515SAli.Saidi@ARM.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 86910515SAli.Saidi@ARM.comsystem.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 87010515SAli.Saidi@ARM.comsystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 87110515SAli.Saidi@ARM.comsystem.realview.ethernet.txBytes 966 # Bytes Transmitted 87210515SAli.Saidi@ARM.comsystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 87310515SAli.Saidi@ARM.comsystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 87410515SAli.Saidi@ARM.comsystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 87510515SAli.Saidi@ARM.comsystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 87610515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 87710515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 87810515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 87910515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 88010515SAli.Saidi@ARM.comsystem.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 88110515SAli.Saidi@ARM.comsystem.realview.ethernet.totPackets 3 # Total Packets 88210515SAli.Saidi@ARM.comsystem.realview.ethernet.totBytes 966 # Total Bytes 88310515SAli.Saidi@ARM.comsystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 88410515SAli.Saidi@ARM.comsystem.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 88510515SAli.Saidi@ARM.comsystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 88610515SAli.Saidi@ARM.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 88710515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 88810515SAli.Saidi@ARM.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 88910515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 89010515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 89110515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 89210515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 89310515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 89410515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 89510515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 89610515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 89710515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 89810515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 89910515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 90010515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 90110515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 90210515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 90310515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 90410515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 90510515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 90610515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 90710515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 90810515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 90910515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 91010515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 91110515SAli.Saidi@ARM.comsystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 91210515SAli.Saidi@ARM.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 91310515SAli.Saidi@ARM.comsystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 91410515SAli.Saidi@ARM.comsystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 91510515SAli.Saidi@ARM.comsystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 91610515SAli.Saidi@ARM.comsystem.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 91710515SAli.Saidi@ARM.comsystem.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 91810515SAli.Saidi@ARM.comsystem.cf0.dma_write_txs 1670 # Number of DMA write transactions. 91910515SAli.Saidi@ARM.comsystem.toL2Bus.trans_dist::ReadReq 6929805 # Transaction distribution 92010515SAli.Saidi@ARM.comsystem.toL2Bus.trans_dist::ReadResp 6922247 # Transaction distribution 92110515SAli.Saidi@ARM.comsystem.toL2Bus.trans_dist::WriteReq 37937 # Transaction distribution 92210515SAli.Saidi@ARM.comsystem.toL2Bus.trans_dist::WriteResp 37937 # Transaction distribution 92310515SAli.Saidi@ARM.comsystem.toL2Bus.trans_dist::Writeback 1844732 # Transaction distribution 92410515SAli.Saidi@ARM.comsystem.toL2Bus.trans_dist::WriteInvalidateReq 1665553 # Transaction distribution 92510515SAli.Saidi@ARM.comsystem.toL2Bus.trans_dist::WriteInvalidateResp 1558815 # Transaction distribution 92610515SAli.Saidi@ARM.comsystem.toL2Bus.trans_dist::UpgradeReq 396880 # Transaction distribution 92710515SAli.Saidi@ARM.comsystem.toL2Bus.trans_dist::SCUpgradeReq 304912 # Transaction distribution 92810515SAli.Saidi@ARM.comsystem.toL2Bus.trans_dist::UpgradeResp 701792 # Transaction distribution 92910515SAli.Saidi@ARM.comsystem.toL2Bus.trans_dist::SCUpgradeFailReq 122 # Transaction distribution 93010515SAli.Saidi@ARM.comsystem.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution 93110515SAli.Saidi@ARM.comsystem.toL2Bus.trans_dist::ReadExReq 286652 # Transaction distribution 93210515SAli.Saidi@ARM.comsystem.toL2Bus.trans_dist::ReadExResp 286652 # Transaction distribution 93310515SAli.Saidi@ARM.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10302950 # Packet count per connected master and slave (bytes) 93410515SAli.Saidi@ARM.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 9169444 # Packet count per connected master and slave (bytes) 93510515SAli.Saidi@ARM.comsystem.toL2Bus.pkt_count::total 19472394 # Packet count per connected master and slave (bytes) 93610515SAli.Saidi@ARM.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 332778181 # Cumulative packet size per connected master and slave (bytes) 93710515SAli.Saidi@ARM.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 290120831 # Cumulative packet size per connected master and slave (bytes) 93810515SAli.Saidi@ARM.comsystem.toL2Bus.pkt_size::total 622899012 # Cumulative packet size per connected master and slave (bytes) 93910515SAli.Saidi@ARM.comsystem.toL2Bus.snoops 1503135 # Total snoops (count) 94010515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::samples 11338555 # Request fanout histogram 94110515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::mean 1.010201 # Request fanout histogram 94210515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::stdev 0.100485 # Request fanout histogram 94310515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 94410515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 94510515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::1 11222888 98.98% 98.98% # Request fanout histogram 94610515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::2 115667 1.02% 100.00% # Request fanout histogram 94710515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 94810515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 94910515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 95010515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::total 11338555 # Request fanout histogram 95110515SAli.Saidi@ARM.comsystem.toL2Bus.reqLayer0.occupancy 19325316227 # Layer occupancy (ticks) 95210515SAli.Saidi@ARM.comsystem.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 95310515SAli.Saidi@ARM.comsystem.toL2Bus.snoopLayer0.occupancy 6157500 # Layer occupancy (ticks) 95410515SAli.Saidi@ARM.comsystem.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 95510515SAli.Saidi@ARM.comsystem.toL2Bus.respLayer0.occupancy 17505808152 # Layer occupancy (ticks) 95610515SAli.Saidi@ARM.comsystem.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 95710515SAli.Saidi@ARM.comsystem.toL2Bus.respLayer1.occupancy 16090621161 # Layer occupancy (ticks) 95810515SAli.Saidi@ARM.comsystem.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 95910515SAli.Saidi@ARM.comsystem.iobus.trans_dist::ReadReq 40386 # Transaction distribution 96010515SAli.Saidi@ARM.comsystem.iobus.trans_dist::ReadResp 40386 # Transaction distribution 96110515SAli.Saidi@ARM.comsystem.iobus.trans_dist::WriteReq 136543 # Transaction distribution 96210515SAli.Saidi@ARM.comsystem.iobus.trans_dist::WriteResp 136730 # Transaction distribution 96310515SAli.Saidi@ARM.comsystem.iobus.trans_dist::WriteInvalidateReq 187 # Transaction distribution 96410515SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48036 # Packet count per connected master and slave (bytes) 96510515SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 96610515SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 96710515SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 96810515SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 96910515SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 97010515SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 97110515SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 97210515SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 97310515SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 97410515SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 97510515SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 97610515SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 97710515SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 97810515SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 97910515SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::total 122918 # Packet count per connected master and slave (bytes) 98010515SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231234 # Packet count per connected master and slave (bytes) 98110515SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231234 # Packet count per connected master and slave (bytes) 98210515SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 98310515SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 98410515SAli.Saidi@ARM.comsystem.iobus.pkt_count::total 354232 # Packet count per connected master and slave (bytes) 98510515SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48056 # Cumulative packet size per connected master and slave (bytes) 98610515SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 98710515SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 98810515SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 98910515SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 99010515SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 99110515SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 99210515SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 99310515SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 99410515SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 99510515SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 99610515SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 99710515SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 99810515SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 99910515SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 100010515SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::total 156048 # Cumulative packet size per connected master and slave (bytes) 100110515SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338952 # Cumulative packet size per connected master and slave (bytes) 100210515SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7338952 # Cumulative packet size per connected master and slave (bytes) 100310515SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 100410515SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 100510515SAli.Saidi@ARM.comsystem.iobus.pkt_size::total 7497086 # Cumulative packet size per connected master and slave (bytes) 100610515SAli.Saidi@ARM.comsystem.iobus.reqLayer0.occupancy 36503000 # Layer occupancy (ticks) 100710515SAli.Saidi@ARM.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 100810515SAli.Saidi@ARM.comsystem.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 100910515SAli.Saidi@ARM.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 101010515SAli.Saidi@ARM.comsystem.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 101110515SAli.Saidi@ARM.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 101210515SAli.Saidi@ARM.comsystem.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 101310515SAli.Saidi@ARM.comsystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 101410515SAli.Saidi@ARM.comsystem.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 101510515SAli.Saidi@ARM.comsystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 101610515SAli.Saidi@ARM.comsystem.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 101710515SAli.Saidi@ARM.comsystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 101810515SAli.Saidi@ARM.comsystem.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 101910515SAli.Saidi@ARM.comsystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 102010515SAli.Saidi@ARM.comsystem.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 102110515SAli.Saidi@ARM.comsystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 102210515SAli.Saidi@ARM.comsystem.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 102310515SAli.Saidi@ARM.comsystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 102410515SAli.Saidi@ARM.comsystem.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 102510515SAli.Saidi@ARM.comsystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 102610515SAli.Saidi@ARM.comsystem.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) 102710515SAli.Saidi@ARM.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 102810515SAli.Saidi@ARM.comsystem.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 102910515SAli.Saidi@ARM.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 103010515SAli.Saidi@ARM.comsystem.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 103110515SAli.Saidi@ARM.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 103210515SAli.Saidi@ARM.comsystem.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 103310515SAli.Saidi@ARM.comsystem.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 103410515SAli.Saidi@ARM.comsystem.iobus.reqLayer27.occupancy 982100345 # Layer occupancy (ticks) 103510515SAli.Saidi@ARM.comsystem.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 103610515SAli.Saidi@ARM.comsystem.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 103710515SAli.Saidi@ARM.comsystem.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 103810515SAli.Saidi@ARM.comsystem.iobus.respLayer0.occupancy 92919000 # Layer occupancy (ticks) 103910515SAli.Saidi@ARM.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 104010515SAli.Saidi@ARM.comsystem.iobus.respLayer3.occupancy 179226247 # Layer occupancy (ticks) 104110515SAli.Saidi@ARM.comsystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 104210515SAli.Saidi@ARM.comsystem.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) 104310515SAli.Saidi@ARM.comsystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 104410515SAli.Saidi@ARM.comsystem.cpu0.branchPred.lookups 130284886 # Number of BP lookups 104510515SAli.Saidi@ARM.comsystem.cpu0.branchPred.condPredicted 91971902 # Number of conditional branches predicted 104610515SAli.Saidi@ARM.comsystem.cpu0.branchPred.condIncorrect 5996877 # Number of conditional branches incorrect 104710515SAli.Saidi@ARM.comsystem.cpu0.branchPred.BTBLookups 97983342 # Number of BTB lookups 104810515SAli.Saidi@ARM.comsystem.cpu0.branchPred.BTBHits 71203631 # Number of BTB hits 104910515SAli.Saidi@ARM.comsystem.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 105010515SAli.Saidi@ARM.comsystem.cpu0.branchPred.BTBHitPct 72.669119 # BTB Hit Percentage 105110515SAli.Saidi@ARM.comsystem.cpu0.branchPred.usedRAS 15456951 # Number of times the RAS was used to get a target. 105210515SAli.Saidi@ARM.comsystem.cpu0.branchPred.RASInCorrect 1030979 # Number of incorrect RAS predictions. 105310515SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 105410515SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 105510515SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 105610515SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 105710515SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 105810515SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 105910515SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 106010515SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 106110515SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 106210515SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 106310515SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 106410515SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 106510515SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 106610515SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 106710515SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 106810515SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 106910515SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 107010515SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 107110515SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 107210515SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 107310515SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 107410515SAli.Saidi@ARM.comsystem.cpu0.dtb.inst_hits 0 # ITB inst hits 107510515SAli.Saidi@ARM.comsystem.cpu0.dtb.inst_misses 0 # ITB inst misses 107610515SAli.Saidi@ARM.comsystem.cpu0.dtb.read_hits 84560824 # DTB read hits 107710515SAli.Saidi@ARM.comsystem.cpu0.dtb.read_misses 213472 # DTB read misses 107810515SAli.Saidi@ARM.comsystem.cpu0.dtb.write_hits 73762718 # DTB write hits 107910515SAli.Saidi@ARM.comsystem.cpu0.dtb.write_misses 44801 # DTB write misses 108010515SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 108110515SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 108210515SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb_mva_asid 38216 # Number of times TLB was flushed by MVA & ASID 108310515SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID 108410515SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_entries 35801 # Number of entries that have been flushed from TLB 108510515SAli.Saidi@ARM.comsystem.cpu0.dtb.align_faults 1794 # Number of TLB faults due to alignment restrictions 108610515SAli.Saidi@ARM.comsystem.cpu0.dtb.prefetch_faults 7921 # Number of TLB faults due to prefetch 108710515SAli.Saidi@ARM.comsystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 108810515SAli.Saidi@ARM.comsystem.cpu0.dtb.perms_faults 10648 # Number of TLB faults due to permissions restrictions 108910515SAli.Saidi@ARM.comsystem.cpu0.dtb.read_accesses 84774296 # DTB read accesses 109010515SAli.Saidi@ARM.comsystem.cpu0.dtb.write_accesses 73807519 # DTB write accesses 109110515SAli.Saidi@ARM.comsystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 109210515SAli.Saidi@ARM.comsystem.cpu0.dtb.hits 158323542 # DTB hits 109310515SAli.Saidi@ARM.comsystem.cpu0.dtb.misses 258273 # DTB misses 109410515SAli.Saidi@ARM.comsystem.cpu0.dtb.accesses 158581815 # DTB accesses 109510515SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 109610515SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 109710515SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 109810515SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 109910515SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 110010515SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 110110515SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 110210515SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 110310515SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 110410515SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 110510515SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 110610515SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 110710515SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 110810515SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 110910515SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 111010515SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 111110515SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 111210515SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 111310515SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 111410515SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 111510515SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 111610515SAli.Saidi@ARM.comsystem.cpu0.itb.inst_hits 233888906 # ITB inst hits 111710515SAli.Saidi@ARM.comsystem.cpu0.itb.inst_misses 61464 # ITB inst misses 111810515SAli.Saidi@ARM.comsystem.cpu0.itb.read_hits 0 # DTB read hits 111910515SAli.Saidi@ARM.comsystem.cpu0.itb.read_misses 0 # DTB read misses 112010515SAli.Saidi@ARM.comsystem.cpu0.itb.write_hits 0 # DTB write hits 112110515SAli.Saidi@ARM.comsystem.cpu0.itb.write_misses 0 # DTB write misses 112210515SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 112310515SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 112410515SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb_mva_asid 38216 # Number of times TLB was flushed by MVA & ASID 112510515SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID 112610515SAli.Saidi@ARM.comsystem.cpu0.itb.flush_entries 25786 # Number of entries that have been flushed from TLB 112710515SAli.Saidi@ARM.comsystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 112810515SAli.Saidi@ARM.comsystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 112910515SAli.Saidi@ARM.comsystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 113010515SAli.Saidi@ARM.comsystem.cpu0.itb.perms_faults 208811 # Number of TLB faults due to permissions restrictions 113110515SAli.Saidi@ARM.comsystem.cpu0.itb.read_accesses 0 # DTB read accesses 113210515SAli.Saidi@ARM.comsystem.cpu0.itb.write_accesses 0 # DTB write accesses 113310515SAli.Saidi@ARM.comsystem.cpu0.itb.inst_accesses 233950370 # ITB inst accesses 113410515SAli.Saidi@ARM.comsystem.cpu0.itb.hits 233888906 # DTB hits 113510515SAli.Saidi@ARM.comsystem.cpu0.itb.misses 61464 # DTB misses 113610515SAli.Saidi@ARM.comsystem.cpu0.itb.accesses 233950370 # DTB accesses 113710515SAli.Saidi@ARM.comsystem.cpu0.numCycles 883850249 # number of cpu cycles simulated 113810515SAli.Saidi@ARM.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 113910515SAli.Saidi@ARM.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 114010515SAli.Saidi@ARM.comsystem.cpu0.committedInsts 434327088 # Number of instructions committed 114110515SAli.Saidi@ARM.comsystem.cpu0.committedOps 509859279 # Number of ops (including micro ops) committed 114210515SAli.Saidi@ARM.comsystem.cpu0.discardedOps 43671037 # Number of ops (including micro ops) which were discarded before commit 114310515SAli.Saidi@ARM.comsystem.cpu0.numFetchSuspends 5040 # Number of times Execute suspended instruction fetching 114410515SAli.Saidi@ARM.comsystem.cpu0.quiesceCycles 93815840018 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 114510515SAli.Saidi@ARM.comsystem.cpu0.cpi 2.034988 # CPI: cycles per instruction 114610515SAli.Saidi@ARM.comsystem.cpu0.ipc 0.491403 # IPC: instructions per cycle 114710515SAli.Saidi@ARM.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 114810515SAli.Saidi@ARM.comsystem.cpu0.kern.inst.quiesce 5406 # number of quiesce instructions executed 114910515SAli.Saidi@ARM.comsystem.cpu0.tickCycles 675499590 # Number of cycles that the object actually ticked 115010515SAli.Saidi@ARM.comsystem.cpu0.idleCycles 208350659 # Total number of cycles that the object has spent stopped 115110515SAli.Saidi@ARM.comsystem.cpu0.icache.tags.replacements 9024677 # number of replacements 115210515SAli.Saidi@ARM.comsystem.cpu0.icache.tags.tagsinuse 511.937426 # Cycle average of tags in use 115310515SAli.Saidi@ARM.comsystem.cpu0.icache.tags.total_refs 224649292 # Total number of references to valid blocks. 115410515SAli.Saidi@ARM.comsystem.cpu0.icache.tags.sampled_refs 9025189 # Sample count of references to valid blocks. 115510515SAli.Saidi@ARM.comsystem.cpu0.icache.tags.avg_refs 24.891367 # Average number of references to valid blocks. 115610515SAli.Saidi@ARM.comsystem.cpu0.icache.tags.warmup_cycle 16724996500 # Cycle when the warmup percentage was hit. 115710515SAli.Saidi@ARM.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.937426 # Average occupied blocks per requestor 115810515SAli.Saidi@ARM.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999878 # Average percentage of cache occupancy 115910515SAli.Saidi@ARM.comsystem.cpu0.icache.tags.occ_percent::total 0.999878 # Average percentage of cache occupancy 116010515SAli.Saidi@ARM.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 116110515SAli.Saidi@ARM.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 159 # Occupied blocks per task id 116210515SAli.Saidi@ARM.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id 116310515SAli.Saidi@ARM.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id 116410515SAli.Saidi@ARM.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 116510515SAli.Saidi@ARM.comsystem.cpu0.icache.tags.tag_accesses 476374153 # Number of tag accesses 116610515SAli.Saidi@ARM.comsystem.cpu0.icache.tags.data_accesses 476374153 # Number of data accesses 116710515SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 224649292 # number of ReadReq hits 116810515SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_hits::total 224649292 # number of ReadReq hits 116910515SAli.Saidi@ARM.comsystem.cpu0.icache.demand_hits::cpu0.inst 224649292 # number of demand (read+write) hits 117010515SAli.Saidi@ARM.comsystem.cpu0.icache.demand_hits::total 224649292 # number of demand (read+write) hits 117110515SAli.Saidi@ARM.comsystem.cpu0.icache.overall_hits::cpu0.inst 224649292 # number of overall hits 117210515SAli.Saidi@ARM.comsystem.cpu0.icache.overall_hits::total 224649292 # number of overall hits 117310515SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 9025190 # number of ReadReq misses 117410515SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_misses::total 9025190 # number of ReadReq misses 117510515SAli.Saidi@ARM.comsystem.cpu0.icache.demand_misses::cpu0.inst 9025190 # number of demand (read+write) misses 117610515SAli.Saidi@ARM.comsystem.cpu0.icache.demand_misses::total 9025190 # number of demand (read+write) misses 117710515SAli.Saidi@ARM.comsystem.cpu0.icache.overall_misses::cpu0.inst 9025190 # number of overall misses 117810515SAli.Saidi@ARM.comsystem.cpu0.icache.overall_misses::total 9025190 # number of overall misses 117910515SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 76329373412 # number of ReadReq miss cycles 118010515SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_miss_latency::total 76329373412 # number of ReadReq miss cycles 118110515SAli.Saidi@ARM.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 76329373412 # number of demand (read+write) miss cycles 118210515SAli.Saidi@ARM.comsystem.cpu0.icache.demand_miss_latency::total 76329373412 # number of demand (read+write) miss cycles 118310515SAli.Saidi@ARM.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 76329373412 # number of overall miss cycles 118410515SAli.Saidi@ARM.comsystem.cpu0.icache.overall_miss_latency::total 76329373412 # number of overall miss cycles 118510515SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 233674482 # number of ReadReq accesses(hits+misses) 118610515SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_accesses::total 233674482 # number of ReadReq accesses(hits+misses) 118710515SAli.Saidi@ARM.comsystem.cpu0.icache.demand_accesses::cpu0.inst 233674482 # number of demand (read+write) accesses 118810515SAli.Saidi@ARM.comsystem.cpu0.icache.demand_accesses::total 233674482 # number of demand (read+write) accesses 118910515SAli.Saidi@ARM.comsystem.cpu0.icache.overall_accesses::cpu0.inst 233674482 # number of overall (read+write) accesses 119010515SAli.Saidi@ARM.comsystem.cpu0.icache.overall_accesses::total 233674482 # number of overall (read+write) accesses 119110515SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.038623 # miss rate for ReadReq accesses 119210515SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.038623 # miss rate for ReadReq accesses 119310515SAli.Saidi@ARM.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.038623 # miss rate for demand accesses 119410515SAli.Saidi@ARM.comsystem.cpu0.icache.demand_miss_rate::total 0.038623 # miss rate for demand accesses 119510515SAli.Saidi@ARM.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.038623 # miss rate for overall accesses 119610515SAli.Saidi@ARM.comsystem.cpu0.icache.overall_miss_rate::total 0.038623 # miss rate for overall accesses 119710515SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8457.370251 # average ReadReq miss latency 119810515SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 8457.370251 # average ReadReq miss latency 119910515SAli.Saidi@ARM.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8457.370251 # average overall miss latency 120010515SAli.Saidi@ARM.comsystem.cpu0.icache.demand_avg_miss_latency::total 8457.370251 # average overall miss latency 120110515SAli.Saidi@ARM.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8457.370251 # average overall miss latency 120210515SAli.Saidi@ARM.comsystem.cpu0.icache.overall_avg_miss_latency::total 8457.370251 # average overall miss latency 120310515SAli.Saidi@ARM.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 120410515SAli.Saidi@ARM.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 120510515SAli.Saidi@ARM.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 120610515SAli.Saidi@ARM.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 120710515SAli.Saidi@ARM.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 120810515SAli.Saidi@ARM.comsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 120910515SAli.Saidi@ARM.comsystem.cpu0.icache.fast_writes 0 # number of fast writes performed 121010515SAli.Saidi@ARM.comsystem.cpu0.icache.cache_copies 0 # number of cache copies performed 121110515SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9025190 # number of ReadReq MSHR misses 121210515SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_mshr_misses::total 9025190 # number of ReadReq MSHR misses 121310515SAli.Saidi@ARM.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 9025190 # number of demand (read+write) MSHR misses 121410515SAli.Saidi@ARM.comsystem.cpu0.icache.demand_mshr_misses::total 9025190 # number of demand (read+write) MSHR misses 121510515SAli.Saidi@ARM.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 9025190 # number of overall MSHR misses 121610515SAli.Saidi@ARM.comsystem.cpu0.icache.overall_mshr_misses::total 9025190 # number of overall MSHR misses 121710515SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 62781832574 # number of ReadReq MSHR miss cycles 121810515SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 62781832574 # number of ReadReq MSHR miss cycles 121910515SAli.Saidi@ARM.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 62781832574 # number of demand (read+write) MSHR miss cycles 122010515SAli.Saidi@ARM.comsystem.cpu0.icache.demand_mshr_miss_latency::total 62781832574 # number of demand (read+write) MSHR miss cycles 122110515SAli.Saidi@ARM.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 62781832574 # number of overall MSHR miss cycles 122210515SAli.Saidi@ARM.comsystem.cpu0.icache.overall_mshr_miss_latency::total 62781832574 # number of overall MSHR miss cycles 122310515SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4713380500 # number of ReadReq MSHR uncacheable cycles 122410515SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4713380500 # number of ReadReq MSHR uncacheable cycles 122510515SAli.Saidi@ARM.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4713380500 # number of overall MSHR uncacheable cycles 122610515SAli.Saidi@ARM.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::total 4713380500 # number of overall MSHR uncacheable cycles 122710515SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.038623 # mshr miss rate for ReadReq accesses 122810515SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.038623 # mshr miss rate for ReadReq accesses 122910515SAli.Saidi@ARM.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.038623 # mshr miss rate for demand accesses 123010515SAli.Saidi@ARM.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.038623 # mshr miss rate for demand accesses 123110515SAli.Saidi@ARM.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.038623 # mshr miss rate for overall accesses 123210515SAli.Saidi@ARM.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.038623 # mshr miss rate for overall accesses 123310515SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6956.289294 # average ReadReq mshr miss latency 123410515SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6956.289294 # average ReadReq mshr miss latency 123510515SAli.Saidi@ARM.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6956.289294 # average overall mshr miss latency 123610515SAli.Saidi@ARM.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 6956.289294 # average overall mshr miss latency 123710515SAli.Saidi@ARM.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6956.289294 # average overall mshr miss latency 123810515SAli.Saidi@ARM.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 6956.289294 # average overall mshr miss latency 123910515SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 124010515SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 124110515SAli.Saidi@ARM.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 124210515SAli.Saidi@ARM.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 124310515SAli.Saidi@ARM.comsystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 124410515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 16744363 # Transaction distribution 124510515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 13538941 # Transaction distribution 124610515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 16377 # Transaction distribution 124710515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 16377 # Transaction distribution 124810515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.trans_dist::Writeback 2993146 # Transaction distribution 124910515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.trans_dist::HardPFReq 4286145 # Transaction distribution 125010515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 125110515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1665553 # Transaction distribution 125210515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 878594 # Transaction distribution 125310515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 389729 # Transaction distribution 125410515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 340122 # Transaction distribution 125510515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 446153 # Transaction distribution 125610515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 67 # Transaction distribution 125710515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution 125810515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1234377 # Transaction distribution 125910515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1099479 # Transaction distribution 126010515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18154960 # Packet count per connected master and slave (bytes) 126110515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15139641 # Packet count per connected master and slave (bytes) 126210515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 334891 # Packet count per connected master and slave (bytes) 126310515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1016427 # Packet count per connected master and slave (bytes) 126410515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.pkt_count::total 34645919 # Packet count per connected master and slave (bytes) 126510515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 580958656 # Cumulative packet size per connected master and slave (bytes) 126610515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 555417413 # Cumulative packet size per connected master and slave (bytes) 126710515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1211560 # Cumulative packet size per connected master and slave (bytes) 126810515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3676024 # Cumulative packet size per connected master and slave (bytes) 126910515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.pkt_size::total 1141263653 # Cumulative packet size per connected master and slave (bytes) 127010515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.snoops 9180766 # Total snoops (count) 127110515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.snoop_fanout::samples 27586114 # Request fanout histogram 127210515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.snoop_fanout::mean 5.321691 # Request fanout histogram 127310515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.467125 # Request fanout histogram 127410515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 127510515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 127610515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 127710515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 127810515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 127910515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 128010515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.snoop_fanout::5 18711910 67.83% 67.83% # Request fanout histogram 128110515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.snoop_fanout::6 8874204 32.17% 100.00% # Request fanout histogram 128210515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 128310515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 128410515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 128510515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.snoop_fanout::total 27586114 # Request fanout histogram 128610515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.reqLayer0.occupancy 13279117937 # Layer occupancy (ticks) 128710515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 128810515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.snoopLayer0.occupancy 196246989 # Layer occupancy (ticks) 128910515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 129010515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.respLayer0.occupancy 13633302169 # Layer occupancy (ticks) 129110515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 129210515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.respLayer1.occupancy 7744080967 # Layer occupancy (ticks) 129310515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 129410515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.respLayer2.occupancy 184135419 # Layer occupancy (ticks) 129510515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 129610515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.respLayer3.occupancy 557460915 # Layer occupancy (ticks) 129710515SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 129810515SAli.Saidi@ARM.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 80006652 # number of hwpf identified 129910515SAli.Saidi@ARM.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 1538976 # number of hwpf that were already in mshr 130010515SAli.Saidi@ARM.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 75387543 # number of hwpf that were already in the cache 130110515SAli.Saidi@ARM.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 49644 # number of hwpf that were already in the prefetch queue 130210515SAli.Saidi@ARM.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 130310515SAli.Saidi@ARM.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2517 # number of hwpf removed because MSHR allocated 130410515SAli.Saidi@ARM.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 3027964 # number of hwpf issued 130510515SAli.Saidi@ARM.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 6795468 # number of hwpf spanning a virtual page 130610515SAli.Saidi@ARM.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 130710515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.replacements 3295318 # number of replacements 130810515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.tagsinuse 16239.521092 # Cycle average of tags in use 130910515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.total_refs 15183735 # Total number of references to valid blocks. 131010515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.sampled_refs 3311433 # Sample count of references to valid blocks. 131110515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.avg_refs 4.585246 # Average number of references to valid blocks. 131210515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.warmup_cycle 14515776000 # Cycle when the warmup percentage was hit. 131310515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 5108.942549 # Average occupied blocks per requestor 131410515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 64.019654 # Average occupied blocks per requestor 131510515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 70.169979 # Average occupied blocks per requestor 131610515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2735.324727 # Average occupied blocks per requestor 131710515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 8261.064181 # Average occupied blocks per requestor 131810515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.311825 # Average percentage of cache occupancy 131910515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003907 # Average percentage of cache occupancy 132010515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004283 # Average percentage of cache occupancy 132110515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.166951 # Average percentage of cache occupancy 132210515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.504215 # Average percentage of cache occupancy 132310515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.occ_percent::total 0.991182 # Average percentage of cache occupancy 132410515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1022 10731 # Occupied blocks per task id 132510515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 83 # Occupied blocks per task id 132610515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 5301 # Occupied blocks per task id 132710515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::0 116 # Occupied blocks per task id 132810515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::1 730 # Occupied blocks per task id 132910515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::2 2564 # Occupied blocks per task id 133010515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::3 4307 # Occupied blocks per task id 133110515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::4 3014 # Occupied blocks per task id 133210515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id 133310515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::1 6 # Occupied blocks per task id 133410515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 35 # Occupied blocks per task id 133510515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 30 # Occupied blocks per task id 133610515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id 133710515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 133810515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 447 # Occupied blocks per task id 133910515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1426 # Occupied blocks per task id 134010515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2059 # Occupied blocks per task id 134110515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1321 # Occupied blocks per task id 134210515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1022 0.654968 # Percentage of cache occupancy per task id 134310515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005066 # Percentage of cache occupancy per task id 134410515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.323547 # Percentage of cache occupancy per task id 134510515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.tag_accesses 302494843 # Number of tag accesses 134610515SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.data_accesses 302494843 # Number of data accesses 134710515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 445653 # number of ReadReq hits 134810515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 140462 # number of ReadReq hits 134910515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.inst 11717958 # number of ReadReq hits 135010515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_hits::total 12304073 # number of ReadReq hits 135110515SAli.Saidi@ARM.comsystem.cpu0.l2cache.Writeback_hits::writebacks 2993146 # number of Writeback hits 135210515SAli.Saidi@ARM.comsystem.cpu0.l2cache.Writeback_hits::total 2993146 # number of Writeback hits 135310515SAli.Saidi@ARM.comsystem.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 70651 # number of UpgradeReq hits 135410515SAli.Saidi@ARM.comsystem.cpu0.l2cache.UpgradeReq_hits::total 70651 # number of UpgradeReq hits 135510515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 35155 # number of SCUpgradeReq hits 135610515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeReq_hits::total 35155 # number of SCUpgradeReq hits 135710515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.inst 863705 # number of ReadExReq hits 135810515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadExReq_hits::total 863705 # number of ReadExReq hits 135910515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 445653 # number of demand (read+write) hits 136010515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 140462 # number of demand (read+write) hits 136110515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 12581663 # number of demand (read+write) hits 136210515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_hits::total 13167778 # number of demand (read+write) hits 136310515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 445653 # number of overall hits 136410515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 140462 # number of overall hits 136510515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 12581663 # number of overall hits 136610515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_hits::total 13167778 # number of overall hits 136710515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 13850 # number of ReadReq misses 136810515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10983 # number of ReadReq misses 136910515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.inst 913042 # number of ReadReq misses 137010515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_misses::total 937875 # number of ReadReq misses 137110515SAli.Saidi@ARM.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 117562 # number of UpgradeReq misses 137210515SAli.Saidi@ARM.comsystem.cpu0.l2cache.UpgradeReq_misses::total 117562 # number of UpgradeReq misses 137310515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 153389 # number of SCUpgradeReq misses 137410515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 153389 # number of SCUpgradeReq misses 137510515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.inst 3 # number of SCUpgradeFailReq misses 137610515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses 137710515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.inst 228005 # number of ReadExReq misses 137810515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadExReq_misses::total 228005 # number of ReadExReq misses 137910515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 13850 # number of demand (read+write) misses 138010515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 10983 # number of demand (read+write) misses 138110515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 1141047 # number of demand (read+write) misses 138210515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_misses::total 1165880 # number of demand (read+write) misses 138310515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 13850 # number of overall misses 138410515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 10983 # number of overall misses 138510515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 1141047 # number of overall misses 138610515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_misses::total 1165880 # number of overall misses 138710515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 571410377 # number of ReadReq miss cycles 138810515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 698481694 # number of ReadReq miss cycles 138910515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 26359609041 # number of ReadReq miss cycles 139010515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_miss_latency::total 27629501112 # number of ReadReq miss cycles 139110515SAli.Saidi@ARM.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 2365914343 # number of UpgradeReq miss cycles 139210515SAli.Saidi@ARM.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::total 2365914343 # number of UpgradeReq miss cycles 139310515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 3101977603 # number of SCUpgradeReq miss cycles 139410515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3101977603 # number of SCUpgradeReq miss cycles 139510515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 2176500 # number of SCUpgradeFailReq miss cycles 139610515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2176500 # number of SCUpgradeFailReq miss cycles 139710515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 9967705721 # number of ReadExReq miss cycles 139810515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadExReq_miss_latency::total 9967705721 # number of ReadExReq miss cycles 139910515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 571410377 # number of demand (read+write) miss cycles 140010515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 698481694 # number of demand (read+write) miss cycles 140110515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.inst 36327314762 # number of demand (read+write) miss cycles 140210515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_miss_latency::total 37597206833 # number of demand (read+write) miss cycles 140310515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 571410377 # number of overall miss cycles 140410515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 698481694 # number of overall miss cycles 140510515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.inst 36327314762 # number of overall miss cycles 140610515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_miss_latency::total 37597206833 # number of overall miss cycles 140710515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 459503 # number of ReadReq accesses(hits+misses) 140810515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 151445 # number of ReadReq accesses(hits+misses) 140910515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.inst 12631000 # number of ReadReq accesses(hits+misses) 141010515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_accesses::total 13241948 # number of ReadReq accesses(hits+misses) 141110515SAli.Saidi@ARM.comsystem.cpu0.l2cache.Writeback_accesses::writebacks 2993146 # number of Writeback accesses(hits+misses) 141210515SAli.Saidi@ARM.comsystem.cpu0.l2cache.Writeback_accesses::total 2993146 # number of Writeback accesses(hits+misses) 141310515SAli.Saidi@ARM.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 188213 # number of UpgradeReq accesses(hits+misses) 141410515SAli.Saidi@ARM.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 188213 # number of UpgradeReq accesses(hits+misses) 141510515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 188544 # number of SCUpgradeReq accesses(hits+misses) 141610515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 188544 # number of SCUpgradeReq accesses(hits+misses) 141710515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.inst 3 # number of SCUpgradeFailReq accesses(hits+misses) 141810515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) 141910515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 1091710 # number of ReadExReq accesses(hits+misses) 142010515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1091710 # number of ReadExReq accesses(hits+misses) 142110515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 459503 # number of demand (read+write) accesses 142210515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 151445 # number of demand (read+write) accesses 142310515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 13722710 # number of demand (read+write) accesses 142410515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_accesses::total 14333658 # number of demand (read+write) accesses 142510515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 459503 # number of overall (read+write) accesses 142610515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 151445 # number of overall (read+write) accesses 142710515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 13722710 # number of overall (read+write) accesses 142810515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_accesses::total 14333658 # number of overall (read+write) accesses 142910515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.030141 # miss rate for ReadReq accesses 143010515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.072521 # miss rate for ReadReq accesses 143110515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.072286 # miss rate for ReadReq accesses 143210515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.070826 # miss rate for ReadReq accesses 143310515SAli.Saidi@ARM.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.624622 # miss rate for UpgradeReq accesses 143410515SAli.Saidi@ARM.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 0.624622 # miss rate for UpgradeReq accesses 143510515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.813545 # miss rate for SCUpgradeReq accesses 143610515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.813545 # miss rate for SCUpgradeReq accesses 143710515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.inst 1 # miss rate for SCUpgradeFailReq accesses 143810515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 143910515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.208851 # miss rate for ReadExReq accesses 144010515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.208851 # miss rate for ReadExReq accesses 144110515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.030141 # miss rate for demand accesses 144210515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.072521 # miss rate for demand accesses 144310515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.083150 # miss rate for demand accesses 144410515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_miss_rate::total 0.081339 # miss rate for demand accesses 144510515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.030141 # miss rate for overall accesses 144610515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.072521 # miss rate for overall accesses 144710515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.083150 # miss rate for overall accesses 144810515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_miss_rate::total 0.081339 # miss rate for overall accesses 144910515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 41257.066931 # average ReadReq miss latency 145010515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 63596.621506 # average ReadReq miss latency 145110515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 28870.094739 # average ReadReq miss latency 145210515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::total 29459.683979 # average ReadReq miss latency 145310515SAli.Saidi@ARM.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 20124.822162 # average UpgradeReq miss latency 145410515SAli.Saidi@ARM.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 20124.822162 # average UpgradeReq miss latency 145510515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 20222.946906 # average SCUpgradeReq miss latency 145610515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20222.946906 # average SCUpgradeReq miss latency 145710515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst 725500 # average SCUpgradeFailReq miss latency 145810515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 725500 # average SCUpgradeFailReq miss latency 145910515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 43717.048841 # average ReadExReq miss latency 146010515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::total 43717.048841 # average ReadExReq miss latency 146110515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 41257.066931 # average overall miss latency 146210515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 63596.621506 # average overall miss latency 146310515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 31836.825969 # average overall miss latency 146410515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_avg_miss_latency::total 32247.921598 # average overall miss latency 146510515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 41257.066931 # average overall miss latency 146610515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 63596.621506 # average overall miss latency 146710515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 31836.825969 # average overall miss latency 146810515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_avg_miss_latency::total 32247.921598 # average overall miss latency 146910515SAli.Saidi@ARM.comsystem.cpu0.l2cache.blocked_cycles::no_mshrs 62612 # number of cycles access was blocked 147010515SAli.Saidi@ARM.comsystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 147110515SAli.Saidi@ARM.comsystem.cpu0.l2cache.blocked::no_mshrs 1060 # number of cycles access was blocked 147210515SAli.Saidi@ARM.comsystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 147310515SAli.Saidi@ARM.comsystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs 59.067925 # average number of cycles each access was blocked 147410515SAli.Saidi@ARM.comsystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 147510515SAli.Saidi@ARM.comsystem.cpu0.l2cache.fast_writes 0 # number of fast writes performed 147610515SAli.Saidi@ARM.comsystem.cpu0.l2cache.cache_copies 0 # number of cache copies performed 147710515SAli.Saidi@ARM.comsystem.cpu0.l2cache.writebacks::writebacks 1001402 # number of writebacks 147810515SAli.Saidi@ARM.comsystem.cpu0.l2cache.writebacks::total 1001402 # number of writebacks 147910515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 72428 # number of ReadReq MSHR hits 148010515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_mshr_hits::total 72428 # number of ReadReq MSHR hits 148110515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 6233 # number of ReadExReq MSHR hits 148210515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::total 6233 # number of ReadExReq MSHR hits 148310515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.inst 78661 # number of demand (read+write) MSHR hits 148410515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_mshr_hits::total 78661 # number of demand (read+write) MSHR hits 148510515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.inst 78661 # number of overall MSHR hits 148610515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_mshr_hits::total 78661 # number of overall MSHR hits 148710515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 13850 # number of ReadReq MSHR misses 148810515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 10983 # number of ReadReq MSHR misses 148910515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 840614 # number of ReadReq MSHR misses 149010515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_mshr_misses::total 865447 # number of ReadReq MSHR misses 149110515SAli.Saidi@ARM.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 3027916 # number of HardPFReq MSHR misses 149210515SAli.Saidi@ARM.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::total 3027916 # number of HardPFReq MSHR misses 149310515SAli.Saidi@ARM.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 117562 # number of UpgradeReq MSHR misses 149410515SAli.Saidi@ARM.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::total 117562 # number of UpgradeReq MSHR misses 149510515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 153389 # number of SCUpgradeReq MSHR misses 149610515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 153389 # number of SCUpgradeReq MSHR misses 149710515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.inst 3 # number of SCUpgradeFailReq MSHR misses 149810515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses 149910515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 221772 # number of ReadExReq MSHR misses 150010515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::total 221772 # number of ReadExReq MSHR misses 150110515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 13850 # number of demand (read+write) MSHR misses 150210515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 10983 # number of demand (read+write) MSHR misses 150310515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.inst 1062386 # number of demand (read+write) MSHR misses 150410515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_mshr_misses::total 1087219 # number of demand (read+write) MSHR misses 150510515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 13850 # number of overall MSHR misses 150610515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 10983 # number of overall MSHR misses 150710515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.inst 1062386 # number of overall MSHR misses 150810515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 3027916 # number of overall MSHR misses 150910515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_mshr_misses::total 4115135 # number of overall MSHR misses 151010515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 473721015 # number of ReadReq MSHR miss cycles 151110515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 620302796 # number of ReadReq MSHR miss cycles 151210515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 19074448661 # number of ReadReq MSHR miss cycles 151310515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::total 20168472472 # number of ReadReq MSHR miss cycles 151410515SAli.Saidi@ARM.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 79252881469 # number of HardPFReq MSHR miss cycles 151510515SAli.Saidi@ARM.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 79252881469 # number of HardPFReq MSHR miss cycles 151610515SAli.Saidi@ARM.comsystem.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 33127814392 # number of WriteInvalidateReq MSHR miss cycles 151710515SAli.Saidi@ARM.comsystem.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 33127814392 # number of WriteInvalidateReq MSHR miss cycles 151810515SAli.Saidi@ARM.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 2005449750 # number of UpgradeReq MSHR miss cycles 151910515SAli.Saidi@ARM.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2005449750 # number of UpgradeReq MSHR miss cycles 152010515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 2118741906 # number of SCUpgradeReq MSHR miss cycles 152110515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2118741906 # number of SCUpgradeReq MSHR miss cycles 152210515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst 1770500 # number of SCUpgradeFailReq MSHR miss cycles 152310515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1770500 # number of SCUpgradeFailReq MSHR miss cycles 152410515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 7853083593 # number of ReadExReq MSHR miss cycles 152510515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 7853083593 # number of ReadExReq MSHR miss cycles 152610515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 473721015 # number of demand (read+write) MSHR miss cycles 152710515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 620302796 # number of demand (read+write) MSHR miss cycles 152810515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 26927532254 # number of demand (read+write) MSHR miss cycles 152910515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_mshr_miss_latency::total 28021556065 # number of demand (read+write) MSHR miss cycles 153010515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 473721015 # number of overall MSHR miss cycles 153110515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 620302796 # number of overall MSHR miss cycles 153210515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 26927532254 # number of overall MSHR miss cycles 153310515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 79252881469 # number of overall MSHR miss cycles 153410515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_mshr_miss_latency::total 107274437534 # number of overall MSHR miss cycles 153510515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6580252048 # number of ReadReq MSHR uncacheable cycles 153610515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6580252048 # number of ReadReq MSHR uncacheable cycles 153710515SAli.Saidi@ARM.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 2399021553 # number of WriteReq MSHR uncacheable cycles 153810515SAli.Saidi@ARM.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2399021553 # number of WriteReq MSHR uncacheable cycles 153910515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 8979273601 # number of overall MSHR uncacheable cycles 154010515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::total 8979273601 # number of overall MSHR uncacheable cycles 154110515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.030141 # mshr miss rate for ReadReq accesses 154210515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.072521 # mshr miss rate for ReadReq accesses 154310515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.066552 # mshr miss rate for ReadReq accesses 154410515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.065356 # mshr miss rate for ReadReq accesses 154510515SAli.Saidi@ARM.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 154610515SAli.Saidi@ARM.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 154710515SAli.Saidi@ARM.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.624622 # mshr miss rate for UpgradeReq accesses 154810515SAli.Saidi@ARM.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.624622 # mshr miss rate for UpgradeReq accesses 154910515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.813545 # mshr miss rate for SCUpgradeReq accesses 155010515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.813545 # mshr miss rate for SCUpgradeReq accesses 155110515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst 1 # mshr miss rate for SCUpgradeFailReq accesses 155210515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 155310515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.203142 # mshr miss rate for ReadExReq accesses 155410515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.203142 # mshr miss rate for ReadExReq accesses 155510515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.030141 # mshr miss rate for demand accesses 155610515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.072521 # mshr miss rate for demand accesses 155710515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.077418 # mshr miss rate for demand accesses 155810515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_mshr_miss_rate::total 0.075851 # mshr miss rate for demand accesses 155910515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.030141 # mshr miss rate for overall accesses 156010515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.072521 # mshr miss rate for overall accesses 156110515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.077418 # mshr miss rate for overall accesses 156210515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 156310515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_mshr_miss_rate::total 0.287096 # mshr miss rate for overall accesses 156410515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 34203.683394 # average ReadReq mshr miss latency 156510515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 56478.448147 # average ReadReq mshr miss latency 156610515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22691.090870 # average ReadReq mshr miss latency 156710515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23304.110445 # average ReadReq mshr miss latency 156810515SAli.Saidi@ARM.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 26174.068722 # average HardPFReq mshr miss latency 156910515SAli.Saidi@ARM.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 26174.068722 # average HardPFReq mshr miss latency 157010515SAli.Saidi@ARM.comsystem.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst inf # average WriteInvalidateReq mshr miss latency 157110515SAli.Saidi@ARM.comsystem.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 157210515SAli.Saidi@ARM.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 17058.656283 # average UpgradeReq mshr miss latency 157310515SAli.Saidi@ARM.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17058.656283 # average UpgradeReq mshr miss latency 157410515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13812.867324 # average SCUpgradeReq mshr miss latency 157510515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13812.867324 # average SCUpgradeReq mshr miss latency 157610515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 590166.666667 # average SCUpgradeFailReq mshr miss latency 157710515SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 590166.666667 # average SCUpgradeFailReq mshr miss latency 157810515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 35410.618081 # average ReadExReq mshr miss latency 157910515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 35410.618081 # average ReadExReq mshr miss latency 158010515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 34203.683394 # average overall mshr miss latency 158110515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 56478.448147 # average overall mshr miss latency 158210515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25346.279275 # average overall mshr miss latency 158310515SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25773.607769 # average overall mshr miss latency 158410515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 34203.683394 # average overall mshr miss latency 158510515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 56478.448147 # average overall mshr miss latency 158610515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25346.279275 # average overall mshr miss latency 158710515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 26174.068722 # average overall mshr miss latency 158810515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::total 26068.266906 # average overall mshr miss latency 158910515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 159010515SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 159110515SAli.Saidi@ARM.comsystem.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 159210515SAli.Saidi@ARM.comsystem.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 159310515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 159410515SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 159510515SAli.Saidi@ARM.comsystem.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 159610515SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.replacements 5337320 # number of replacements 159710515SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.tagsinuse 473.198574 # Cycle average of tags in use 159810515SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.total_refs 150291577 # Total number of references to valid blocks. 159910515SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.sampled_refs 5337832 # Sample count of references to valid blocks. 160010515SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.avg_refs 28.155921 # Average number of references to valid blocks. 160110515SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.warmup_cycle 4951320000 # Cycle when the warmup percentage was hit. 160210515SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.inst 473.198574 # Average occupied blocks per requestor 160310515SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.occ_percent::cpu0.inst 0.924216 # Average percentage of cache occupancy 160410515SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.occ_percent::total 0.924216 # Average percentage of cache occupancy 160510515SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 160610515SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id 160710515SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 374 # Occupied blocks per task id 160810515SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id 160910515SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 161010515SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.tag_accesses 319289852 # Number of tag accesses 161110515SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.data_accesses 319289852 # Number of data accesses 161210515SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_hits::cpu0.inst 77767484 # number of ReadReq hits 161310515SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_hits::total 77767484 # number of ReadReq hits 161410515SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_hits::cpu0.inst 68524145 # number of WriteReq hits 161510515SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_hits::total 68524145 # number of WriteReq hits 161610515SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteInvalidateReq_hits::cpu0.inst 878594 # number of WriteInvalidateReq hits 161710515SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteInvalidateReq_hits::total 878594 # number of WriteInvalidateReq hits 161810515SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 1744720 # number of LoadLockedReq hits 161910515SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_hits::total 1744720 # number of LoadLockedReq hits 162010515SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.inst 1671495 # number of StoreCondReq hits 162110515SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_hits::total 1671495 # number of StoreCondReq hits 162210515SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_hits::cpu0.inst 146291629 # number of demand (read+write) hits 162310515SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_hits::total 146291629 # number of demand (read+write) hits 162410515SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_hits::cpu0.inst 146291629 # number of overall hits 162510515SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_hits::total 146291629 # number of overall hits 162610515SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_misses::cpu0.inst 3855307 # number of ReadReq misses 162710515SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_misses::total 3855307 # number of ReadReq misses 162810515SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_misses::cpu0.inst 2180509 # number of WriteReq misses 162910515SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_misses::total 2180509 # number of WriteReq misses 163010515SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 116717 # number of LoadLockedReq misses 163110515SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_misses::total 116717 # number of LoadLockedReq misses 163210515SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.inst 188600 # number of StoreCondReq misses 163310515SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_misses::total 188600 # number of StoreCondReq misses 163410515SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_misses::cpu0.inst 6035816 # number of demand (read+write) misses 163510515SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_misses::total 6035816 # number of demand (read+write) misses 163610515SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_misses::cpu0.inst 6035816 # number of overall misses 163710515SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_misses::total 6035816 # number of overall misses 163810515SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 52949262121 # number of ReadReq miss cycles 163910515SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_miss_latency::total 52949262121 # number of ReadReq miss cycles 164010515SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 36682258766 # number of WriteReq miss cycles 164110515SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_miss_latency::total 36682258766 # number of WriteReq miss cycles 164210515SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 1582680255 # number of LoadLockedReq miss cycles 164310515SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 1582680255 # number of LoadLockedReq miss cycles 164410515SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 3978646923 # number of StoreCondReq miss cycles 164510515SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 3978646923 # number of StoreCondReq miss cycles 164610515SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 2553000 # number of StoreCondFailReq miss cycles 164710515SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::total 2553000 # number of StoreCondFailReq miss cycles 164810515SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_miss_latency::cpu0.inst 89631520887 # number of demand (read+write) miss cycles 164910515SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_miss_latency::total 89631520887 # number of demand (read+write) miss cycles 165010515SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_miss_latency::cpu0.inst 89631520887 # number of overall miss cycles 165110515SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_miss_latency::total 89631520887 # number of overall miss cycles 165210515SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.inst 81622791 # number of ReadReq accesses(hits+misses) 165310515SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_accesses::total 81622791 # number of ReadReq accesses(hits+misses) 165410515SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.inst 70704654 # number of WriteReq accesses(hits+misses) 165510515SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_accesses::total 70704654 # number of WriteReq accesses(hits+misses) 165610515SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.inst 878594 # number of WriteInvalidateReq accesses(hits+misses) 165710515SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteInvalidateReq_accesses::total 878594 # number of WriteInvalidateReq accesses(hits+misses) 165810515SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 1861437 # number of LoadLockedReq accesses(hits+misses) 165910515SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 1861437 # number of LoadLockedReq accesses(hits+misses) 166010515SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 1860095 # number of StoreCondReq accesses(hits+misses) 166110515SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_accesses::total 1860095 # number of StoreCondReq accesses(hits+misses) 166210515SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_accesses::cpu0.inst 152327445 # number of demand (read+write) accesses 166310515SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_accesses::total 152327445 # number of demand (read+write) accesses 166410515SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_accesses::cpu0.inst 152327445 # number of overall (read+write) accesses 166510515SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_accesses::total 152327445 # number of overall (read+write) accesses 166610515SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.047233 # miss rate for ReadReq accesses 166710515SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.047233 # miss rate for ReadReq accesses 166810515SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.030840 # miss rate for WriteReq accesses 166910515SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.030840 # miss rate for WriteReq accesses 167010515SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.062703 # miss rate for LoadLockedReq accesses 167110515SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.062703 # miss rate for LoadLockedReq accesses 167210515SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.101393 # miss rate for StoreCondReq accesses 167310515SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.101393 # miss rate for StoreCondReq accesses 167410515SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_miss_rate::cpu0.inst 0.039624 # miss rate for demand accesses 167510515SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_miss_rate::total 0.039624 # miss rate for demand accesses 167610515SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_miss_rate::cpu0.inst 0.039624 # miss rate for overall accesses 167710515SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_miss_rate::total 0.039624 # miss rate for overall accesses 167810515SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 13734.123410 # average ReadReq miss latency 167910515SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 13734.123410 # average ReadReq miss latency 168010515SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 16822.796313 # average WriteReq miss latency 168110515SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 16822.796313 # average WriteReq miss latency 168210515SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 13559.980594 # average LoadLockedReq miss latency 168310515SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13559.980594 # average LoadLockedReq miss latency 168410515SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 21095.688881 # average StoreCondReq miss latency 168510515SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21095.688881 # average StoreCondReq miss latency 168610515SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency 168710515SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 168810515SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 14849.942557 # average overall miss latency 168910515SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_avg_miss_latency::total 14849.942557 # average overall miss latency 169010515SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 14849.942557 # average overall miss latency 169110515SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_avg_miss_latency::total 14849.942557 # average overall miss latency 169210515SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 169310515SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 169410515SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 169510515SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 169610515SAli.Saidi@ARM.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 169710515SAli.Saidi@ARM.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 169810515SAli.Saidi@ARM.comsystem.cpu0.dcache.fast_writes 878594 # number of fast writes performed 169910515SAli.Saidi@ARM.comsystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 170010515SAli.Saidi@ARM.comsystem.cpu0.dcache.writebacks::writebacks 2993146 # number of writebacks 170110515SAli.Saidi@ARM.comsystem.cpu0.dcache.writebacks::total 2993146 # number of writebacks 170210515SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 365860 # number of ReadReq MSHR hits 170310515SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 365860 # number of ReadReq MSHR hits 170410515SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 900170 # number of WriteReq MSHR hits 170510515SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 900170 # number of WriteReq MSHR hits 170610515SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 65 # number of LoadLockedReq MSHR hits 170710515SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 65 # number of LoadLockedReq MSHR hits 170810515SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.inst 53 # number of StoreCondReq MSHR hits 170910515SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_mshr_hits::total 53 # number of StoreCondReq MSHR hits 171010515SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_mshr_hits::cpu0.inst 1266030 # number of demand (read+write) MSHR hits 171110515SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_mshr_hits::total 1266030 # number of demand (read+write) MSHR hits 171210515SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_mshr_hits::cpu0.inst 1266030 # number of overall MSHR hits 171310515SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_mshr_hits::total 1266030 # number of overall MSHR hits 171410515SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 3489447 # number of ReadReq MSHR misses 171510515SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 3489447 # number of ReadReq MSHR misses 171610515SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 1279618 # number of WriteReq MSHR misses 171710515SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 1279618 # number of WriteReq MSHR misses 171810515SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 116652 # number of LoadLockedReq MSHR misses 171910515SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 116652 # number of LoadLockedReq MSHR misses 172010515SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 188547 # number of StoreCondReq MSHR misses 172110515SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 188547 # number of StoreCondReq MSHR misses 172210515SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.inst 4769065 # number of demand (read+write) MSHR misses 172310515SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_mshr_misses::total 4769065 # number of demand (read+write) MSHR misses 172410515SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.inst 4769065 # number of overall MSHR misses 172510515SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_mshr_misses::total 4769065 # number of overall MSHR misses 172610515SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 40912958493 # number of ReadReq MSHR miss cycles 172710515SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 40912958493 # number of ReadReq MSHR miss cycles 172810515SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 19695838269 # number of WriteReq MSHR miss cycles 172910515SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 19695838269 # number of WriteReq MSHR miss cycles 173010515SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 39725259601 # number of WriteInvalidateReq MSHR miss cycles 173110515SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 39725259601 # number of WriteInvalidateReq MSHR miss cycles 173210515SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 1347811737 # number of LoadLockedReq MSHR miss cycles 173310515SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1347811737 # number of LoadLockedReq MSHR miss cycles 173410515SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 3591126546 # number of StoreCondReq MSHR miss cycles 173510515SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3591126546 # number of StoreCondReq MSHR miss cycles 173610515SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 2234500 # number of StoreCondFailReq MSHR miss cycles 173710515SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2234500 # number of StoreCondFailReq MSHR miss cycles 173810515SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 60608796762 # number of demand (read+write) MSHR miss cycles 173910515SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 60608796762 # number of demand (read+write) MSHR miss cycles 174010515SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 60608796762 # number of overall MSHR miss cycles 174110515SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 60608796762 # number of overall MSHR miss cycles 174210515SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2590105703 # number of ReadReq MSHR uncacheable cycles 174310515SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2590105703 # number of ReadReq MSHR uncacheable cycles 174410515SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 2521930197 # number of WriteReq MSHR uncacheable cycles 174510515SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2521930197 # number of WriteReq MSHR uncacheable cycles 174610515SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 5112035900 # number of overall MSHR uncacheable cycles 174710515SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 5112035900 # number of overall MSHR uncacheable cycles 174810515SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.042751 # mshr miss rate for ReadReq accesses 174910515SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.042751 # mshr miss rate for ReadReq accesses 175010515SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.018098 # mshr miss rate for WriteReq accesses 175110515SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018098 # mshr miss rate for WriteReq accesses 175210515SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.062668 # mshr miss rate for LoadLockedReq accesses 175310515SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062668 # mshr miss rate for LoadLockedReq accesses 175410515SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.101364 # mshr miss rate for StoreCondReq accesses 175510515SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.101364 # mshr miss rate for StoreCondReq accesses 175610515SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.031308 # mshr miss rate for demand accesses 175710515SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.031308 # mshr miss rate for demand accesses 175810515SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.031308 # mshr miss rate for overall accesses 175910515SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.031308 # mshr miss rate for overall accesses 176010515SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11724.768564 # average ReadReq mshr miss latency 176110515SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11724.768564 # average ReadReq mshr miss latency 176210515SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 15391.967188 # average WriteReq mshr miss latency 176310515SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15391.967188 # average WriteReq mshr miss latency 176410515SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst inf # average WriteInvalidateReq mshr miss latency 176510515SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 176610515SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 11554.124550 # average LoadLockedReq mshr miss latency 176710515SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11554.124550 # average LoadLockedReq mshr miss latency 176810515SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19046.320260 # average StoreCondReq mshr miss latency 176910515SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19046.320260 # average StoreCondReq mshr miss latency 177010515SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency 177110515SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 177210515SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 12708.737826 # average overall mshr miss latency 177310515SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 12708.737826 # average overall mshr miss latency 177410515SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 12708.737826 # average overall mshr miss latency 177510515SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 12708.737826 # average overall mshr miss latency 177610515SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 177710515SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 177810515SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 177910515SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 178010515SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 178110515SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 178210515SAli.Saidi@ARM.comsystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 178310515SAli.Saidi@ARM.comsystem.cpu1.branchPred.lookups 124419206 # Number of BP lookups 178410515SAli.Saidi@ARM.comsystem.cpu1.branchPred.condPredicted 87805046 # Number of conditional branches predicted 178510515SAli.Saidi@ARM.comsystem.cpu1.branchPred.condIncorrect 6051921 # Number of conditional branches incorrect 178610515SAli.Saidi@ARM.comsystem.cpu1.branchPred.BTBLookups 92935126 # Number of BTB lookups 178710515SAli.Saidi@ARM.comsystem.cpu1.branchPred.BTBHits 66733716 # Number of BTB hits 178810515SAli.Saidi@ARM.comsystem.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 178910515SAli.Saidi@ARM.comsystem.cpu1.branchPred.BTBHitPct 71.806774 # BTB Hit Percentage 179010515SAli.Saidi@ARM.comsystem.cpu1.branchPred.usedRAS 14888837 # Number of times the RAS was used to get a target. 179110515SAli.Saidi@ARM.comsystem.cpu1.branchPred.RASInCorrect 1052333 # Number of incorrect RAS predictions. 179210515SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 179310515SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 179410515SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 179510515SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 179610515SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 179710515SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 179810515SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 179910515SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 180010515SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 180110515SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 180210515SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 180310515SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 180410515SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 180510515SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 180610515SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 180710515SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 180810515SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 180910515SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 181010515SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 181110515SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 181210515SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 181310515SAli.Saidi@ARM.comsystem.cpu1.dtb.inst_hits 0 # ITB inst hits 181410515SAli.Saidi@ARM.comsystem.cpu1.dtb.inst_misses 0 # ITB inst misses 181510515SAli.Saidi@ARM.comsystem.cpu1.dtb.read_hits 80858392 # DTB read hits 181610515SAli.Saidi@ARM.comsystem.cpu1.dtb.read_misses 227532 # DTB read misses 181710515SAli.Saidi@ARM.comsystem.cpu1.dtb.write_hits 71539111 # DTB write hits 181810515SAli.Saidi@ARM.comsystem.cpu1.dtb.write_misses 46368 # DTB write misses 181910515SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 182010515SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 182110515SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb_mva_asid 38216 # Number of times TLB was flushed by MVA & ASID 182210515SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID 182310515SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_entries 35324 # Number of entries that have been flushed from TLB 182410515SAli.Saidi@ARM.comsystem.cpu1.dtb.align_faults 1220 # Number of TLB faults due to alignment restrictions 182510515SAli.Saidi@ARM.comsystem.cpu1.dtb.prefetch_faults 8196 # Number of TLB faults due to prefetch 182610515SAli.Saidi@ARM.comsystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 182710515SAli.Saidi@ARM.comsystem.cpu1.dtb.perms_faults 10514 # Number of TLB faults due to permissions restrictions 182810515SAli.Saidi@ARM.comsystem.cpu1.dtb.read_accesses 81085924 # DTB read accesses 182910515SAli.Saidi@ARM.comsystem.cpu1.dtb.write_accesses 71585479 # DTB write accesses 183010515SAli.Saidi@ARM.comsystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 183110515SAli.Saidi@ARM.comsystem.cpu1.dtb.hits 152397503 # DTB hits 183210515SAli.Saidi@ARM.comsystem.cpu1.dtb.misses 273900 # DTB misses 183310515SAli.Saidi@ARM.comsystem.cpu1.dtb.accesses 152671403 # DTB accesses 183410515SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 183510515SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 183610515SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 183710515SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 183810515SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 183910515SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 184010515SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 184110515SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 184210515SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 184310515SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 184410515SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 184510515SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 184610515SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 184710515SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 184810515SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 184910515SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 185010515SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 185110515SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 185210515SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 185310515SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 185410515SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 185510515SAli.Saidi@ARM.comsystem.cpu1.itb.inst_hits 221287255 # ITB inst hits 185610515SAli.Saidi@ARM.comsystem.cpu1.itb.inst_misses 68040 # ITB inst misses 185710515SAli.Saidi@ARM.comsystem.cpu1.itb.read_hits 0 # DTB read hits 185810515SAli.Saidi@ARM.comsystem.cpu1.itb.read_misses 0 # DTB read misses 185910515SAli.Saidi@ARM.comsystem.cpu1.itb.write_hits 0 # DTB write hits 186010515SAli.Saidi@ARM.comsystem.cpu1.itb.write_misses 0 # DTB write misses 186110515SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 186210515SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 186310515SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb_mva_asid 38216 # Number of times TLB was flushed by MVA & ASID 186410515SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID 186510515SAli.Saidi@ARM.comsystem.cpu1.itb.flush_entries 25097 # Number of entries that have been flushed from TLB 186610515SAli.Saidi@ARM.comsystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 186710515SAli.Saidi@ARM.comsystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 186810515SAli.Saidi@ARM.comsystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 186910515SAli.Saidi@ARM.comsystem.cpu1.itb.perms_faults 202601 # Number of TLB faults due to permissions restrictions 187010515SAli.Saidi@ARM.comsystem.cpu1.itb.read_accesses 0 # DTB read accesses 187110515SAli.Saidi@ARM.comsystem.cpu1.itb.write_accesses 0 # DTB write accesses 187210515SAli.Saidi@ARM.comsystem.cpu1.itb.inst_accesses 221355295 # ITB inst accesses 187310515SAli.Saidi@ARM.comsystem.cpu1.itb.hits 221287255 # DTB hits 187410515SAli.Saidi@ARM.comsystem.cpu1.itb.misses 68040 # DTB misses 187510515SAli.Saidi@ARM.comsystem.cpu1.itb.accesses 221355295 # DTB accesses 187610515SAli.Saidi@ARM.comsystem.cpu1.numCycles 841372178 # number of cpu cycles simulated 187710515SAli.Saidi@ARM.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 187810515SAli.Saidi@ARM.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 187910515SAli.Saidi@ARM.comsystem.cpu1.committedInsts 411163350 # Number of instructions committed 188010515SAli.Saidi@ARM.comsystem.cpu1.committedOps 484726757 # Number of ops (including micro ops) committed 188110515SAli.Saidi@ARM.comsystem.cpu1.discardedOps 42974941 # Number of ops (including micro ops) which were discarded before commit 188210515SAli.Saidi@ARM.comsystem.cpu1.numFetchSuspends 4643 # Number of times Execute suspended instruction fetching 188310515SAli.Saidi@ARM.comsystem.cpu1.quiesceCycles 93858235376 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 188410515SAli.Saidi@ARM.comsystem.cpu1.cpi 2.046321 # CPI: cycles per instruction 188510515SAli.Saidi@ARM.comsystem.cpu1.ipc 0.488682 # IPC: instructions per cycle 188610515SAli.Saidi@ARM.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 188710515SAli.Saidi@ARM.comsystem.cpu1.kern.inst.quiesce 13250 # number of quiesce instructions executed 188810515SAli.Saidi@ARM.comsystem.cpu1.tickCycles 646022417 # Number of cycles that the object actually ticked 188910515SAli.Saidi@ARM.comsystem.cpu1.idleCycles 195349761 # Total number of cycles that the object has spent stopped 189010515SAli.Saidi@ARM.comsystem.cpu1.icache.tags.replacements 9199343 # number of replacements 189110515SAli.Saidi@ARM.comsystem.cpu1.icache.tags.tagsinuse 507.111645 # Cycle average of tags in use 189210515SAli.Saidi@ARM.comsystem.cpu1.icache.tags.total_refs 211878543 # Total number of references to valid blocks. 189310515SAli.Saidi@ARM.comsystem.cpu1.icache.tags.sampled_refs 9199855 # Sample count of references to valid blocks. 189410515SAli.Saidi@ARM.comsystem.cpu1.icache.tags.avg_refs 23.030639 # Average number of references to valid blocks. 189510515SAli.Saidi@ARM.comsystem.cpu1.icache.tags.warmup_cycle 8364993861000 # Cycle when the warmup percentage was hit. 189610515SAli.Saidi@ARM.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 507.111645 # Average occupied blocks per requestor 189710515SAli.Saidi@ARM.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.990452 # Average percentage of cache occupancy 189810515SAli.Saidi@ARM.comsystem.cpu1.icache.tags.occ_percent::total 0.990452 # Average percentage of cache occupancy 189910515SAli.Saidi@ARM.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 190010515SAli.Saidi@ARM.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 385 # Occupied blocks per task id 190110515SAli.Saidi@ARM.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id 190210515SAli.Saidi@ARM.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 190310515SAli.Saidi@ARM.comsystem.cpu1.icache.tags.tag_accesses 451356678 # Number of tag accesses 190410515SAli.Saidi@ARM.comsystem.cpu1.icache.tags.data_accesses 451356678 # Number of data accesses 190510515SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 211878543 # number of ReadReq hits 190610515SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_hits::total 211878543 # number of ReadReq hits 190710515SAli.Saidi@ARM.comsystem.cpu1.icache.demand_hits::cpu1.inst 211878543 # number of demand (read+write) hits 190810515SAli.Saidi@ARM.comsystem.cpu1.icache.demand_hits::total 211878543 # number of demand (read+write) hits 190910515SAli.Saidi@ARM.comsystem.cpu1.icache.overall_hits::cpu1.inst 211878543 # number of overall hits 191010515SAli.Saidi@ARM.comsystem.cpu1.icache.overall_hits::total 211878543 # number of overall hits 191110515SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 9199864 # number of ReadReq misses 191210515SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_misses::total 9199864 # number of ReadReq misses 191310515SAli.Saidi@ARM.comsystem.cpu1.icache.demand_misses::cpu1.inst 9199864 # number of demand (read+write) misses 191410515SAli.Saidi@ARM.comsystem.cpu1.icache.demand_misses::total 9199864 # number of demand (read+write) misses 191510515SAli.Saidi@ARM.comsystem.cpu1.icache.overall_misses::cpu1.inst 9199864 # number of overall misses 191610515SAli.Saidi@ARM.comsystem.cpu1.icache.overall_misses::total 9199864 # number of overall misses 191710515SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 77780449816 # number of ReadReq miss cycles 191810515SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_miss_latency::total 77780449816 # number of ReadReq miss cycles 191910515SAli.Saidi@ARM.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 77780449816 # number of demand (read+write) miss cycles 192010515SAli.Saidi@ARM.comsystem.cpu1.icache.demand_miss_latency::total 77780449816 # number of demand (read+write) miss cycles 192110515SAli.Saidi@ARM.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 77780449816 # number of overall miss cycles 192210515SAli.Saidi@ARM.comsystem.cpu1.icache.overall_miss_latency::total 77780449816 # number of overall miss cycles 192310515SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 221078407 # number of ReadReq accesses(hits+misses) 192410515SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_accesses::total 221078407 # number of ReadReq accesses(hits+misses) 192510515SAli.Saidi@ARM.comsystem.cpu1.icache.demand_accesses::cpu1.inst 221078407 # number of demand (read+write) accesses 192610515SAli.Saidi@ARM.comsystem.cpu1.icache.demand_accesses::total 221078407 # number of demand (read+write) accesses 192710515SAli.Saidi@ARM.comsystem.cpu1.icache.overall_accesses::cpu1.inst 221078407 # number of overall (read+write) accesses 192810515SAli.Saidi@ARM.comsystem.cpu1.icache.overall_accesses::total 221078407 # number of overall (read+write) accesses 192910515SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.041614 # miss rate for ReadReq accesses 193010515SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.041614 # miss rate for ReadReq accesses 193110515SAli.Saidi@ARM.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.041614 # miss rate for demand accesses 193210515SAli.Saidi@ARM.comsystem.cpu1.icache.demand_miss_rate::total 0.041614 # miss rate for demand accesses 193310515SAli.Saidi@ARM.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.041614 # miss rate for overall accesses 193410515SAli.Saidi@ARM.comsystem.cpu1.icache.overall_miss_rate::total 0.041614 # miss rate for overall accesses 193510515SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8454.521699 # average ReadReq miss latency 193610515SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 8454.521699 # average ReadReq miss latency 193710515SAli.Saidi@ARM.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8454.521699 # average overall miss latency 193810515SAli.Saidi@ARM.comsystem.cpu1.icache.demand_avg_miss_latency::total 8454.521699 # average overall miss latency 193910515SAli.Saidi@ARM.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8454.521699 # average overall miss latency 194010515SAli.Saidi@ARM.comsystem.cpu1.icache.overall_avg_miss_latency::total 8454.521699 # average overall miss latency 194110515SAli.Saidi@ARM.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 194210515SAli.Saidi@ARM.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 194310515SAli.Saidi@ARM.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 194410515SAli.Saidi@ARM.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 194510515SAli.Saidi@ARM.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 194610515SAli.Saidi@ARM.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 194710515SAli.Saidi@ARM.comsystem.cpu1.icache.fast_writes 0 # number of fast writes performed 194810515SAli.Saidi@ARM.comsystem.cpu1.icache.cache_copies 0 # number of cache copies performed 194910515SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9199864 # number of ReadReq MSHR misses 195010515SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_mshr_misses::total 9199864 # number of ReadReq MSHR misses 195110515SAli.Saidi@ARM.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 9199864 # number of demand (read+write) MSHR misses 195210515SAli.Saidi@ARM.comsystem.cpu1.icache.demand_mshr_misses::total 9199864 # number of demand (read+write) MSHR misses 195310515SAli.Saidi@ARM.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 9199864 # number of overall MSHR misses 195410515SAli.Saidi@ARM.comsystem.cpu1.icache.overall_mshr_misses::total 9199864 # number of overall MSHR misses 195510515SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 63970402202 # number of ReadReq MSHR miss cycles 195610515SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 63970402202 # number of ReadReq MSHR miss cycles 195710515SAli.Saidi@ARM.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 63970402202 # number of demand (read+write) MSHR miss cycles 195810515SAli.Saidi@ARM.comsystem.cpu1.icache.demand_mshr_miss_latency::total 63970402202 # number of demand (read+write) MSHR miss cycles 195910515SAli.Saidi@ARM.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 63970402202 # number of overall MSHR miss cycles 196010515SAli.Saidi@ARM.comsystem.cpu1.icache.overall_mshr_miss_latency::total 63970402202 # number of overall MSHR miss cycles 196110515SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8551999 # number of ReadReq MSHR uncacheable cycles 196210515SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8551999 # number of ReadReq MSHR uncacheable cycles 196310515SAli.Saidi@ARM.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8551999 # number of overall MSHR uncacheable cycles 196410515SAli.Saidi@ARM.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::total 8551999 # number of overall MSHR uncacheable cycles 196510515SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.041614 # mshr miss rate for ReadReq accesses 196610515SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.041614 # mshr miss rate for ReadReq accesses 196710515SAli.Saidi@ARM.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.041614 # mshr miss rate for demand accesses 196810515SAli.Saidi@ARM.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.041614 # mshr miss rate for demand accesses 196910515SAli.Saidi@ARM.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.041614 # mshr miss rate for overall accesses 197010515SAli.Saidi@ARM.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.041614 # mshr miss rate for overall accesses 197110515SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6953.407377 # average ReadReq mshr miss latency 197210515SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6953.407377 # average ReadReq mshr miss latency 197310515SAli.Saidi@ARM.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6953.407377 # average overall mshr miss latency 197410515SAli.Saidi@ARM.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 6953.407377 # average overall mshr miss latency 197510515SAli.Saidi@ARM.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6953.407377 # average overall mshr miss latency 197610515SAli.Saidi@ARM.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 6953.407377 # average overall mshr miss latency 197710515SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 197810515SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 197910515SAli.Saidi@ARM.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 198010515SAli.Saidi@ARM.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 198110515SAli.Saidi@ARM.comsystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 198210515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 16974832 # Transaction distribution 198310515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 13523495 # Transaction distribution 198410515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 21560 # Transaction distribution 198510515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 21560 # Transaction distribution 198610515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.trans_dist::Writeback 2756922 # Transaction distribution 198710515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.trans_dist::HardPFReq 3912463 # Transaction distribution 198810515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1665553 # Transaction distribution 198910515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 680221 # Transaction distribution 199010515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 382477 # Transaction distribution 199110515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 337171 # Transaction distribution 199210515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 432582 # Transaction distribution 199310515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution 199410515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution 199510515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 1151878 # Transaction distribution 199610515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 1012928 # Transaction distribution 199710515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18399906 # Packet count per connected master and slave (bytes) 199810515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 13962178 # Packet count per connected master and slave (bytes) 199910515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 374507 # Packet count per connected master and slave (bytes) 200010515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1077414 # Packet count per connected master and slave (bytes) 200110515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.pkt_count::total 33814005 # Packet count per connected master and slave (bytes) 200210515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 588796992 # Cumulative packet size per connected master and slave (bytes) 200310515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 509690879 # Cumulative packet size per connected master and slave (bytes) 200410515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1369000 # Cumulative packet size per connected master and slave (bytes) 200510515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3931224 # Cumulative packet size per connected master and slave (bytes) 200610515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.pkt_size::total 1103788095 # Cumulative packet size per connected master and slave (bytes) 200710515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.snoops 9217690 # Total snoops (count) 200810515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.snoop_fanout::samples 27159033 # Request fanout histogram 200910515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.snoop_fanout::mean 5.328913 # Request fanout histogram 201010515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.469818 # Request fanout histogram 201110515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 201210515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 201310515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 201410515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 201510515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 201610515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 201710515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.snoop_fanout::5 18226076 67.11% 67.11% # Request fanout histogram 201810515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.snoop_fanout::6 8932957 32.89% 100.00% # Request fanout histogram 201910515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 202010515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 202110515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 202210515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.snoop_fanout::total 27159033 # Request fanout histogram 202310515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.reqLayer0.occupancy 12584209028 # Layer occupancy (ticks) 202410515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 202510515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.snoopLayer0.occupancy 175099992 # Layer occupancy (ticks) 202610515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 202710515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.respLayer0.occupancy 13805070808 # Layer occupancy (ticks) 202810515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 202910515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.respLayer1.occupancy 7247611234 # Layer occupancy (ticks) 203010515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 203110515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.respLayer2.occupancy 204139691 # Layer occupancy (ticks) 203210515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 203310515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.respLayer3.occupancy 586587181 # Layer occupancy (ticks) 203410515SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 203510515SAli.Saidi@ARM.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 79358164 # number of hwpf identified 203610515SAli.Saidi@ARM.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 1355061 # number of hwpf that were already in mshr 203710515SAli.Saidi@ARM.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 75203006 # number of hwpf that were already in the cache 203810515SAli.Saidi@ARM.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 49096 # number of hwpf that were already in the prefetch queue 203910515SAli.Saidi@ARM.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 204010515SAli.Saidi@ARM.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 3073 # number of hwpf removed because MSHR allocated 204110515SAli.Saidi@ARM.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 2747928 # number of hwpf issued 204210515SAli.Saidi@ARM.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 6733876 # number of hwpf spanning a virtual page 204310515SAli.Saidi@ARM.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 204410515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.replacements 3063828 # number of replacements 204510515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.tagsinuse 13784.638052 # Cycle average of tags in use 204610515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.total_refs 15005563 # Total number of references to valid blocks. 204710515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.sampled_refs 3079680 # Sample count of references to valid blocks. 204810515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.avg_refs 4.872442 # Average number of references to valid blocks. 204910515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.warmup_cycle 9994842368500 # Cycle when the warmup percentage was hit. 205010515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 2928.842366 # Average occupied blocks per requestor 205110515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 67.432287 # Average occupied blocks per requestor 205210515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 61.914602 # Average occupied blocks per requestor 205310515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2764.974382 # Average occupied blocks per requestor 205410515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 7961.474415 # Average occupied blocks per requestor 205510515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.178762 # Average percentage of cache occupancy 205610515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004116 # Average percentage of cache occupancy 205710515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003779 # Average percentage of cache occupancy 205810515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.168761 # Average percentage of cache occupancy 205910515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.485930 # Average percentage of cache occupancy 206010515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.occ_percent::total 0.841348 # Average percentage of cache occupancy 206110515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1022 9851 # Occupied blocks per task id 206210515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 102 # Occupied blocks per task id 206310515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 5899 # Occupied blocks per task id 206410515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::1 232 # Occupied blocks per task id 206510515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::2 4639 # Occupied blocks per task id 206610515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::3 3547 # Occupied blocks per task id 206710515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1433 # Occupied blocks per task id 206810515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::1 5 # Occupied blocks per task id 206910515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 75 # Occupied blocks per task id 207010515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id 207110515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 207210515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id 207310515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2951 # Occupied blocks per task id 207410515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2204 # Occupied blocks per task id 207510515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 483 # Occupied blocks per task id 207610515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1022 0.601257 # Percentage of cache occupancy per task id 207710515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006226 # Percentage of cache occupancy per task id 207810515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.360046 # Percentage of cache occupancy per task id 207910515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.tag_accesses 294450591 # Number of tag accesses 208010515SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.data_accesses 294450591 # Number of data accesses 208110515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 477253 # number of ReadReq hits 208210515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 159835 # number of ReadReq hits 208310515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.inst 11727223 # number of ReadReq hits 208410515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_hits::total 12364311 # number of ReadReq hits 208510515SAli.Saidi@ARM.comsystem.cpu1.l2cache.Writeback_hits::writebacks 2756922 # number of Writeback hits 208610515SAli.Saidi@ARM.comsystem.cpu1.l2cache.Writeback_hits::total 2756922 # number of Writeback hits 208710515SAli.Saidi@ARM.comsystem.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 68490 # number of UpgradeReq hits 208810515SAli.Saidi@ARM.comsystem.cpu1.l2cache.UpgradeReq_hits::total 68490 # number of UpgradeReq hits 208910515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 32200 # number of SCUpgradeReq hits 209010515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeReq_hits::total 32200 # number of SCUpgradeReq hits 209110515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.inst 776956 # number of ReadExReq hits 209210515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_hits::total 776956 # number of ReadExReq hits 209310515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 477253 # number of demand (read+write) hits 209410515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 159835 # number of demand (read+write) hits 209510515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 12504179 # number of demand (read+write) hits 209610515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_hits::total 13141267 # number of demand (read+write) hits 209710515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 477253 # number of overall hits 209810515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 159835 # number of overall hits 209910515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 12504179 # number of overall hits 210010515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_hits::total 13141267 # number of overall hits 210110515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 14150 # number of ReadReq misses 210210515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 11290 # number of ReadReq misses 210310515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.inst 893170 # number of ReadReq misses 210410515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_misses::total 918610 # number of ReadReq misses 210510515SAli.Saidi@ARM.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 118620 # number of UpgradeReq misses 210610515SAli.Saidi@ARM.comsystem.cpu1.l2cache.UpgradeReq_misses::total 118620 # number of UpgradeReq misses 210710515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 151637 # number of SCUpgradeReq misses 210810515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 151637 # number of SCUpgradeReq misses 210910515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.inst 5 # number of SCUpgradeFailReq misses 211010515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses 211110515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.inst 230937 # number of ReadExReq misses 211210515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_misses::total 230937 # number of ReadExReq misses 211310515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 14150 # number of demand (read+write) misses 211410515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 11290 # number of demand (read+write) misses 211510515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 1124107 # number of demand (read+write) misses 211610515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_misses::total 1149547 # number of demand (read+write) misses 211710515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 14150 # number of overall misses 211810515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 11290 # number of overall misses 211910515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 1124107 # number of overall misses 212010515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_misses::total 1149547 # number of overall misses 212110515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 593312131 # number of ReadReq miss cycles 212210515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 709102173 # number of ReadReq miss cycles 212310515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 26528840524 # number of ReadReq miss cycles 212410515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_miss_latency::total 27831254828 # number of ReadReq miss cycles 212510515SAli.Saidi@ARM.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 2374329628 # number of UpgradeReq miss cycles 212610515SAli.Saidi@ARM.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::total 2374329628 # number of UpgradeReq miss cycles 212710515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 3078262421 # number of SCUpgradeReq miss cycles 212810515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3078262421 # number of SCUpgradeReq miss cycles 212910515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 2493000 # number of SCUpgradeFailReq miss cycles 213010515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2493000 # number of SCUpgradeFailReq miss cycles 213110515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 9672285471 # number of ReadExReq miss cycles 213210515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_miss_latency::total 9672285471 # number of ReadExReq miss cycles 213310515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 593312131 # number of demand (read+write) miss cycles 213410515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 709102173 # number of demand (read+write) miss cycles 213510515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.inst 36201125995 # number of demand (read+write) miss cycles 213610515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_miss_latency::total 37503540299 # number of demand (read+write) miss cycles 213710515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 593312131 # number of overall miss cycles 213810515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 709102173 # number of overall miss cycles 213910515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.inst 36201125995 # number of overall miss cycles 214010515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_miss_latency::total 37503540299 # number of overall miss cycles 214110515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 491403 # number of ReadReq accesses(hits+misses) 214210515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 171125 # number of ReadReq accesses(hits+misses) 214310515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.inst 12620393 # number of ReadReq accesses(hits+misses) 214410515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_accesses::total 13282921 # number of ReadReq accesses(hits+misses) 214510515SAli.Saidi@ARM.comsystem.cpu1.l2cache.Writeback_accesses::writebacks 2756922 # number of Writeback accesses(hits+misses) 214610515SAli.Saidi@ARM.comsystem.cpu1.l2cache.Writeback_accesses::total 2756922 # number of Writeback accesses(hits+misses) 214710515SAli.Saidi@ARM.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 187110 # number of UpgradeReq accesses(hits+misses) 214810515SAli.Saidi@ARM.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 187110 # number of UpgradeReq accesses(hits+misses) 214910515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 183837 # number of SCUpgradeReq accesses(hits+misses) 215010515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 183837 # number of SCUpgradeReq accesses(hits+misses) 215110515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.inst 5 # number of SCUpgradeFailReq accesses(hits+misses) 215210515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) 215310515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 1007893 # number of ReadExReq accesses(hits+misses) 215410515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_accesses::total 1007893 # number of ReadExReq accesses(hits+misses) 215510515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 491403 # number of demand (read+write) accesses 215610515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 171125 # number of demand (read+write) accesses 215710515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 13628286 # number of demand (read+write) accesses 215810515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_accesses::total 14290814 # number of demand (read+write) accesses 215910515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 491403 # number of overall (read+write) accesses 216010515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 171125 # number of overall (read+write) accesses 216110515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 13628286 # number of overall (read+write) accesses 216210515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_accesses::total 14290814 # number of overall (read+write) accesses 216310515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.028795 # miss rate for ReadReq accesses 216410515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.065975 # miss rate for ReadReq accesses 216510515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.070772 # miss rate for ReadReq accesses 216610515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.069157 # miss rate for ReadReq accesses 216710515SAli.Saidi@ARM.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.633959 # miss rate for UpgradeReq accesses 216810515SAli.Saidi@ARM.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 0.633959 # miss rate for UpgradeReq accesses 216910515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.824845 # miss rate for SCUpgradeReq accesses 217010515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.824845 # miss rate for SCUpgradeReq accesses 217110515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.inst 1 # miss rate for SCUpgradeFailReq accesses 217210515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 217310515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.229128 # miss rate for ReadExReq accesses 217410515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.229128 # miss rate for ReadExReq accesses 217510515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.028795 # miss rate for demand accesses 217610515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.065975 # miss rate for demand accesses 217710515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.082483 # miss rate for demand accesses 217810515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_miss_rate::total 0.080440 # miss rate for demand accesses 217910515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.028795 # miss rate for overall accesses 218010515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.065975 # miss rate for overall accesses 218110515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.082483 # miss rate for overall accesses 218210515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_miss_rate::total 0.080440 # miss rate for overall accesses 218310515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 41930.185936 # average ReadReq miss latency 218410515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 62807.986980 # average ReadReq miss latency 218510515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 29701.893843 # average ReadReq miss latency 218610515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::total 30297.138969 # average ReadReq miss latency 218710515SAli.Saidi@ARM.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 20016.267307 # average UpgradeReq miss latency 218810515SAli.Saidi@ARM.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 20016.267307 # average UpgradeReq miss latency 218910515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 20300.206552 # average SCUpgradeReq miss latency 219010515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20300.206552 # average SCUpgradeReq miss latency 219110515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst 498600 # average SCUpgradeFailReq miss latency 219210515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 498600 # average SCUpgradeFailReq miss latency 219310515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 41882.788254 # average ReadExReq miss latency 219410515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::total 41882.788254 # average ReadExReq miss latency 219510515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 41930.185936 # average overall miss latency 219610515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 62807.986980 # average overall miss latency 219710515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 32204.341753 # average overall miss latency 219810515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_avg_miss_latency::total 32624.625439 # average overall miss latency 219910515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 41930.185936 # average overall miss latency 220010515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 62807.986980 # average overall miss latency 220110515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 32204.341753 # average overall miss latency 220210515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_avg_miss_latency::total 32624.625439 # average overall miss latency 220310515SAli.Saidi@ARM.comsystem.cpu1.l2cache.blocked_cycles::no_mshrs 62499 # number of cycles access was blocked 220410515SAli.Saidi@ARM.comsystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 220510515SAli.Saidi@ARM.comsystem.cpu1.l2cache.blocked::no_mshrs 1018 # number of cycles access was blocked 220610515SAli.Saidi@ARM.comsystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 220710515SAli.Saidi@ARM.comsystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs 61.393910 # average number of cycles each access was blocked 220810515SAli.Saidi@ARM.comsystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 220910515SAli.Saidi@ARM.comsystem.cpu1.l2cache.fast_writes 0 # number of fast writes performed 221010515SAli.Saidi@ARM.comsystem.cpu1.l2cache.cache_copies 0 # number of cache copies performed 221110515SAli.Saidi@ARM.comsystem.cpu1.l2cache.writebacks::writebacks 843330 # number of writebacks 221210515SAli.Saidi@ARM.comsystem.cpu1.l2cache.writebacks::total 843330 # number of writebacks 221310515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 70371 # number of ReadReq MSHR hits 221410515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_mshr_hits::total 70371 # number of ReadReq MSHR hits 221510515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 5416 # number of ReadExReq MSHR hits 221610515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::total 5416 # number of ReadExReq MSHR hits 221710515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.inst 75787 # number of demand (read+write) MSHR hits 221810515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_mshr_hits::total 75787 # number of demand (read+write) MSHR hits 221910515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.inst 75787 # number of overall MSHR hits 222010515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_mshr_hits::total 75787 # number of overall MSHR hits 222110515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 14150 # number of ReadReq MSHR misses 222210515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 11290 # number of ReadReq MSHR misses 222310515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 822799 # number of ReadReq MSHR misses 222410515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_mshr_misses::total 848239 # number of ReadReq MSHR misses 222510515SAli.Saidi@ARM.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 2747875 # number of HardPFReq MSHR misses 222610515SAli.Saidi@ARM.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::total 2747875 # number of HardPFReq MSHR misses 222710515SAli.Saidi@ARM.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 118620 # number of UpgradeReq MSHR misses 222810515SAli.Saidi@ARM.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::total 118620 # number of UpgradeReq MSHR misses 222910515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 151637 # number of SCUpgradeReq MSHR misses 223010515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 151637 # number of SCUpgradeReq MSHR misses 223110515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.inst 5 # number of SCUpgradeFailReq MSHR misses 223210515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses 223310515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 225521 # number of ReadExReq MSHR misses 223410515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::total 225521 # number of ReadExReq MSHR misses 223510515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 14150 # number of demand (read+write) MSHR misses 223610515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 11290 # number of demand (read+write) MSHR misses 223710515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.inst 1048320 # number of demand (read+write) MSHR misses 223810515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_mshr_misses::total 1073760 # number of demand (read+write) MSHR misses 223910515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 14150 # number of overall MSHR misses 224010515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 11290 # number of overall MSHR misses 224110515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.inst 1048320 # number of overall MSHR misses 224210515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 2747875 # number of overall MSHR misses 224310515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_mshr_misses::total 3821635 # number of overall MSHR misses 224410515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 493428269 # number of ReadReq MSHR miss cycles 224510515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 628615807 # number of ReadReq MSHR miss cycles 224610515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 19412995328 # number of ReadReq MSHR miss cycles 224710515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::total 20535039404 # number of ReadReq MSHR miss cycles 224810515SAli.Saidi@ARM.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 69814591572 # number of HardPFReq MSHR miss cycles 224910515SAli.Saidi@ARM.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 69814591572 # number of HardPFReq MSHR miss cycles 225010515SAli.Saidi@ARM.comsystem.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.inst 25734891864 # number of WriteInvalidateReq MSHR miss cycles 225110515SAli.Saidi@ARM.comsystem.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 25734891864 # number of WriteInvalidateReq MSHR miss cycles 225210515SAli.Saidi@ARM.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 1991641357 # number of UpgradeReq MSHR miss cycles 225310515SAli.Saidi@ARM.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 1991641357 # number of UpgradeReq MSHR miss cycles 225410515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 2078386327 # number of SCUpgradeReq MSHR miss cycles 225510515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2078386327 # number of SCUpgradeReq MSHR miss cycles 225610515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 2045000 # number of SCUpgradeFailReq MSHR miss cycles 225710515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2045000 # number of SCUpgradeFailReq MSHR miss cycles 225810515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 7579512625 # number of ReadExReq MSHR miss cycles 225910515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7579512625 # number of ReadExReq MSHR miss cycles 226010515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 493428269 # number of demand (read+write) MSHR miss cycles 226110515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 628615807 # number of demand (read+write) MSHR miss cycles 226210515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 26992507953 # number of demand (read+write) MSHR miss cycles 226310515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_mshr_miss_latency::total 28114552029 # number of demand (read+write) MSHR miss cycles 226410515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 493428269 # number of overall MSHR miss cycles 226510515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 628615807 # number of overall MSHR miss cycles 226610515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 26992507953 # number of overall MSHR miss cycles 226710515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 69814591572 # number of overall MSHR miss cycles 226810515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_mshr_miss_latency::total 97929143601 # number of overall MSHR miss cycles 226910515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3580047284 # number of ReadReq MSHR uncacheable cycles 227010515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3580047284 # number of ReadReq MSHR uncacheable cycles 227110515SAli.Saidi@ARM.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 3492978036 # number of WriteReq MSHR uncacheable cycles 227210515SAli.Saidi@ARM.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3492978036 # number of WriteReq MSHR uncacheable cycles 227310515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7073025320 # number of overall MSHR uncacheable cycles 227410515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::total 7073025320 # number of overall MSHR uncacheable cycles 227510515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.028795 # mshr miss rate for ReadReq accesses 227610515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.065975 # mshr miss rate for ReadReq accesses 227710515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.065196 # mshr miss rate for ReadReq accesses 227810515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.063859 # mshr miss rate for ReadReq accesses 227910515SAli.Saidi@ARM.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 228010515SAli.Saidi@ARM.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 228110515SAli.Saidi@ARM.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.633959 # mshr miss rate for UpgradeReq accesses 228210515SAli.Saidi@ARM.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.633959 # mshr miss rate for UpgradeReq accesses 228310515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.824845 # mshr miss rate for SCUpgradeReq accesses 228410515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.824845 # mshr miss rate for SCUpgradeReq accesses 228510515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.inst 1 # mshr miss rate for SCUpgradeFailReq accesses 228610515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 228710515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.223755 # mshr miss rate for ReadExReq accesses 228810515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.223755 # mshr miss rate for ReadExReq accesses 228910515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.028795 # mshr miss rate for demand accesses 229010515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.065975 # mshr miss rate for demand accesses 229110515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.076922 # mshr miss rate for demand accesses 229210515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_mshr_miss_rate::total 0.075136 # mshr miss rate for demand accesses 229310515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.028795 # mshr miss rate for overall accesses 229410515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.065975 # mshr miss rate for overall accesses 229510515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.076922 # mshr miss rate for overall accesses 229610515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 229710515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_mshr_miss_rate::total 0.267419 # mshr miss rate for overall accesses 229810515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 34871.255760 # average ReadReq mshr miss latency 229910515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 55678.990877 # average ReadReq mshr miss latency 230010515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23593.848957 # average ReadReq mshr miss latency 230110515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 24209.025291 # average ReadReq mshr miss latency 230210515SAli.Saidi@ARM.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 25406.756702 # average HardPFReq mshr miss latency 230310515SAli.Saidi@ARM.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 25406.756702 # average HardPFReq mshr miss latency 230410515SAli.Saidi@ARM.comsystem.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst inf # average WriteInvalidateReq mshr miss latency 230510515SAli.Saidi@ARM.comsystem.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 230610515SAli.Saidi@ARM.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 16790.097429 # average UpgradeReq mshr miss latency 230710515SAli.Saidi@ARM.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16790.097429 # average UpgradeReq mshr miss latency 230810515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13706.327130 # average SCUpgradeReq mshr miss latency 230910515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13706.327130 # average SCUpgradeReq mshr miss latency 231010515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst 409000 # average SCUpgradeFailReq mshr miss latency 231110515SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 409000 # average SCUpgradeFailReq mshr miss latency 231210515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 33608.899504 # average ReadExReq mshr miss latency 231310515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33608.899504 # average ReadExReq mshr miss latency 231410515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 34871.255760 # average overall mshr miss latency 231510515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 55678.990877 # average overall mshr miss latency 231610515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 25748.347788 # average overall mshr miss latency 231710515SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26183.273757 # average overall mshr miss latency 231810515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 34871.255760 # average overall mshr miss latency 231910515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 55678.990877 # average overall mshr miss latency 232010515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 25748.347788 # average overall mshr miss latency 232110515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 25406.756702 # average overall mshr miss latency 232210515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25624.933726 # average overall mshr miss latency 232310515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 232410515SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 232510515SAli.Saidi@ARM.comsystem.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 232610515SAli.Saidi@ARM.comsystem.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 232710515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 232810515SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 232910515SAli.Saidi@ARM.comsystem.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 233010515SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.replacements 4834403 # number of replacements 233110515SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.tagsinuse 460.748614 # Cycle average of tags in use 233210515SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.total_refs 144950857 # Total number of references to valid blocks. 233310515SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.sampled_refs 4834915 # Sample count of references to valid blocks. 233410515SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.avg_refs 29.980022 # Average number of references to valid blocks. 233510515SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.warmup_cycle 8365240216000 # Cycle when the warmup percentage was hit. 233610515SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.inst 460.748614 # Average occupied blocks per requestor 233710515SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.occ_percent::cpu1.inst 0.899900 # Average percentage of cache occupancy 233810515SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.occ_percent::total 0.899900 # Average percentage of cache occupancy 233910515SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 234010515SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 385 # Occupied blocks per task id 234110515SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id 234210515SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 234310515SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.tag_accesses 306842506 # Number of tag accesses 234410515SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.data_accesses 306842506 # Number of data accesses 234510515SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_hits::cpu1.inst 74397461 # number of ReadReq hits 234610515SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_hits::total 74397461 # number of ReadReq hits 234710515SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_hits::cpu1.inst 66754653 # number of WriteReq hits 234810515SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_hits::total 66754653 # number of WriteReq hits 234910515SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteInvalidateReq_hits::cpu1.inst 680221 # number of WriteInvalidateReq hits 235010515SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteInvalidateReq_hits::total 680221 # number of WriteInvalidateReq hits 235110515SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 1623333 # number of LoadLockedReq hits 235210515SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_hits::total 1623333 # number of LoadLockedReq hits 235310515SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.inst 1553141 # number of StoreCondReq hits 235410515SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_hits::total 1553141 # number of StoreCondReq hits 235510515SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_hits::cpu1.inst 141152114 # number of demand (read+write) hits 235610515SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_hits::total 141152114 # number of demand (read+write) hits 235710515SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_hits::cpu1.inst 141152114 # number of overall hits 235810515SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_hits::total 141152114 # number of overall hits 235910515SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_misses::cpu1.inst 3628151 # number of ReadReq misses 236010515SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_misses::total 3628151 # number of ReadReq misses 236110515SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_misses::cpu1.inst 2024929 # number of WriteReq misses 236210515SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_misses::total 2024929 # number of WriteReq misses 236310515SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 114968 # number of LoadLockedReq misses 236410515SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_misses::total 114968 # number of LoadLockedReq misses 236510515SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.inst 183901 # number of StoreCondReq misses 236610515SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_misses::total 183901 # number of StoreCondReq misses 236710515SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_misses::cpu1.inst 5653080 # number of demand (read+write) misses 236810515SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_misses::total 5653080 # number of demand (read+write) misses 236910515SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_misses::cpu1.inst 5653080 # number of overall misses 237010515SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_misses::total 5653080 # number of overall misses 237110515SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 51111445827 # number of ReadReq miss cycles 237210515SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_miss_latency::total 51111445827 # number of ReadReq miss cycles 237310515SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 34750982270 # number of WriteReq miss cycles 237410515SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_miss_latency::total 34750982270 # number of WriteReq miss cycles 237510515SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 1576484749 # number of LoadLockedReq miss cycles 237610515SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 1576484749 # number of LoadLockedReq miss cycles 237710515SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 3893749340 # number of StoreCondReq miss cycles 237810515SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 3893749340 # number of StoreCondReq miss cycles 237910515SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 2823500 # number of StoreCondFailReq miss cycles 238010515SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::total 2823500 # number of StoreCondFailReq miss cycles 238110515SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_miss_latency::cpu1.inst 85862428097 # number of demand (read+write) miss cycles 238210515SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_miss_latency::total 85862428097 # number of demand (read+write) miss cycles 238310515SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_miss_latency::cpu1.inst 85862428097 # number of overall miss cycles 238410515SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_miss_latency::total 85862428097 # number of overall miss cycles 238510515SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.inst 78025612 # number of ReadReq accesses(hits+misses) 238610515SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_accesses::total 78025612 # number of ReadReq accesses(hits+misses) 238710515SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.inst 68779582 # number of WriteReq accesses(hits+misses) 238810515SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_accesses::total 68779582 # number of WriteReq accesses(hits+misses) 238910515SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.inst 680221 # number of WriteInvalidateReq accesses(hits+misses) 239010515SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteInvalidateReq_accesses::total 680221 # number of WriteInvalidateReq accesses(hits+misses) 239110515SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 1738301 # number of LoadLockedReq accesses(hits+misses) 239210515SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 1738301 # number of LoadLockedReq accesses(hits+misses) 239310515SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 1737042 # number of StoreCondReq accesses(hits+misses) 239410515SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_accesses::total 1737042 # number of StoreCondReq accesses(hits+misses) 239510515SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_accesses::cpu1.inst 146805194 # number of demand (read+write) accesses 239610515SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_accesses::total 146805194 # number of demand (read+write) accesses 239710515SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_accesses::cpu1.inst 146805194 # number of overall (read+write) accesses 239810515SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_accesses::total 146805194 # number of overall (read+write) accesses 239910515SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.046499 # miss rate for ReadReq accesses 240010515SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.046499 # miss rate for ReadReq accesses 240110515SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.029441 # miss rate for WriteReq accesses 240210515SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.029441 # miss rate for WriteReq accesses 240310515SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.066138 # miss rate for LoadLockedReq accesses 240410515SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066138 # miss rate for LoadLockedReq accesses 240510515SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.105870 # miss rate for StoreCondReq accesses 240610515SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.105870 # miss rate for StoreCondReq accesses 240710515SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_miss_rate::cpu1.inst 0.038507 # miss rate for demand accesses 240810515SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_miss_rate::total 0.038507 # miss rate for demand accesses 240910515SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_miss_rate::cpu1.inst 0.038507 # miss rate for overall accesses 241010515SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_miss_rate::total 0.038507 # miss rate for overall accesses 241110515SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14087.463787 # average ReadReq miss latency 241210515SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 14087.463787 # average ReadReq miss latency 241310515SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 17161.580613 # average WriteReq miss latency 241410515SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 17161.580613 # average WriteReq miss latency 241510515SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 13712.378653 # average LoadLockedReq miss latency 241610515SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13712.378653 # average LoadLockedReq miss latency 241710515SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 21173.073230 # average StoreCondReq miss latency 241810515SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21173.073230 # average StoreCondReq miss latency 241910515SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency 242010515SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 242110515SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 15188.610120 # average overall miss latency 242210515SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_avg_miss_latency::total 15188.610120 # average overall miss latency 242310515SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 15188.610120 # average overall miss latency 242410515SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_avg_miss_latency::total 15188.610120 # average overall miss latency 242510515SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 242610515SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 242710515SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 242810515SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 242910515SAli.Saidi@ARM.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 243010515SAli.Saidi@ARM.comsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 243110515SAli.Saidi@ARM.comsystem.cpu1.dcache.fast_writes 680221 # number of fast writes performed 243210515SAli.Saidi@ARM.comsystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 243310515SAli.Saidi@ARM.comsystem.cpu1.dcache.writebacks::writebacks 2756922 # number of writebacks 243410515SAli.Saidi@ARM.comsystem.cpu1.dcache.writebacks::total 2756922 # number of writebacks 243510515SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 322268 # number of ReadReq MSHR hits 243610515SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 322268 # number of ReadReq MSHR hits 243710515SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 829273 # number of WriteReq MSHR hits 243810515SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 829273 # number of WriteReq MSHR hits 243910515SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst 78 # number of LoadLockedReq MSHR hits 244010515SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 78 # number of LoadLockedReq MSHR hits 244110515SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.inst 59 # number of StoreCondReq MSHR hits 244210515SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_mshr_hits::total 59 # number of StoreCondReq MSHR hits 244310515SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_mshr_hits::cpu1.inst 1151541 # number of demand (read+write) MSHR hits 244410515SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_mshr_hits::total 1151541 # number of demand (read+write) MSHR hits 244510515SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_mshr_hits::cpu1.inst 1151541 # number of overall MSHR hits 244610515SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_mshr_hits::total 1151541 # number of overall MSHR hits 244710515SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 3305883 # number of ReadReq MSHR misses 244810515SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 3305883 # number of ReadReq MSHR misses 244910515SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 1194736 # number of WriteReq MSHR misses 245010515SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 1194736 # number of WriteReq MSHR misses 245110515SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 114890 # number of LoadLockedReq MSHR misses 245210515SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 114890 # number of LoadLockedReq MSHR misses 245310515SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 183842 # number of StoreCondReq MSHR misses 245410515SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 183842 # number of StoreCondReq MSHR misses 245510515SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.inst 4500619 # number of demand (read+write) MSHR misses 245610515SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_mshr_misses::total 4500619 # number of demand (read+write) MSHR misses 245710515SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.inst 4500619 # number of overall MSHR misses 245810515SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_mshr_misses::total 4500619 # number of overall MSHR misses 245910515SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 39848912237 # number of ReadReq MSHR miss cycles 246010515SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 39848912237 # number of ReadReq MSHR miss cycles 246110515SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 18776610903 # number of WriteReq MSHR miss cycles 246210515SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 18776610903 # number of WriteReq MSHR miss cycles 246310515SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.inst 30844406102 # number of WriteInvalidateReq MSHR miss cycles 246410515SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 30844406102 # number of WriteInvalidateReq MSHR miss cycles 246510515SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 1344930230 # number of LoadLockedReq MSHR miss cycles 246610515SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1344930230 # number of LoadLockedReq MSHR miss cycles 246710515SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 3516398127 # number of StoreCondReq MSHR miss cycles 246810515SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3516398127 # number of StoreCondReq MSHR miss cycles 246910515SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 2557000 # number of StoreCondFailReq MSHR miss cycles 247010515SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2557000 # number of StoreCondFailReq MSHR miss cycles 247110515SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 58625523140 # number of demand (read+write) MSHR miss cycles 247210515SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 58625523140 # number of demand (read+write) MSHR miss cycles 247310515SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 58625523140 # number of overall MSHR miss cycles 247410515SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 58625523140 # number of overall MSHR miss cycles 247510515SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3752867967 # number of ReadReq MSHR uncacheable cycles 247610515SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3752867967 # number of ReadReq MSHR uncacheable cycles 247710515SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 3654726713 # number of WriteReq MSHR uncacheable cycles 247810515SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3654726713 # number of WriteReq MSHR uncacheable cycles 247910515SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 7407594680 # number of overall MSHR uncacheable cycles 248010515SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 7407594680 # number of overall MSHR uncacheable cycles 248110515SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.042369 # mshr miss rate for ReadReq accesses 248210515SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042369 # mshr miss rate for ReadReq accesses 248310515SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.017371 # mshr miss rate for WriteReq accesses 248410515SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017371 # mshr miss rate for WriteReq accesses 248510515SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.066093 # mshr miss rate for LoadLockedReq accesses 248610515SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066093 # mshr miss rate for LoadLockedReq accesses 248710515SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.105836 # mshr miss rate for StoreCondReq accesses 248810515SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105836 # mshr miss rate for StoreCondReq accesses 248910515SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.030657 # mshr miss rate for demand accesses 249010515SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.030657 # mshr miss rate for demand accesses 249110515SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.030657 # mshr miss rate for overall accesses 249210515SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.030657 # mshr miss rate for overall accesses 249310515SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12053.939065 # average ReadReq mshr miss latency 249410515SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12053.939065 # average ReadReq mshr miss latency 249510515SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 15716.117120 # average WriteReq mshr miss latency 249610515SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15716.117120 # average WriteReq mshr miss latency 249710515SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst inf # average WriteInvalidateReq mshr miss latency 249810515SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 249910515SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 11706.242754 # average LoadLockedReq mshr miss latency 250010515SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11706.242754 # average LoadLockedReq mshr miss latency 250110515SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 19127.283901 # average StoreCondReq mshr miss latency 250210515SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19127.283901 # average StoreCondReq mshr miss latency 250310515SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency 250410515SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 250510515SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 13026.102218 # average overall mshr miss latency 250610515SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 13026.102218 # average overall mshr miss latency 250710515SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 13026.102218 # average overall mshr miss latency 250810515SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 13026.102218 # average overall mshr miss latency 250910515SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 251010515SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 251110515SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 251210515SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 251310515SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 251410515SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 251510515SAli.Saidi@ARM.comsystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 251610515SAli.Saidi@ARM.comsystem.iocache.tags.replacements 115612 # number of replacements 251710515SAli.Saidi@ARM.comsystem.iocache.tags.tagsinuse 11.299913 # Cycle average of tags in use 251810515SAli.Saidi@ARM.comsystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 251910515SAli.Saidi@ARM.comsystem.iocache.tags.sampled_refs 115628 # Sample count of references to valid blocks. 252010515SAli.Saidi@ARM.comsystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 252110515SAli.Saidi@ARM.comsystem.iocache.tags.warmup_cycle 9121131291000 # Cycle when the warmup percentage was hit. 252210515SAli.Saidi@ARM.comsystem.iocache.tags.occ_blocks::realview.ethernet 7.419527 # Average occupied blocks per requestor 252310515SAli.Saidi@ARM.comsystem.iocache.tags.occ_blocks::realview.ide 3.880386 # Average occupied blocks per requestor 252410515SAli.Saidi@ARM.comsystem.iocache.tags.occ_percent::realview.ethernet 0.463720 # Average percentage of cache occupancy 252510515SAli.Saidi@ARM.comsystem.iocache.tags.occ_percent::realview.ide 0.242524 # Average percentage of cache occupancy 252610515SAli.Saidi@ARM.comsystem.iocache.tags.occ_percent::total 0.706245 # Average percentage of cache occupancy 252710515SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 252810515SAli.Saidi@ARM.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 252910515SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 253010515SAli.Saidi@ARM.comsystem.iocache.tags.tag_accesses 1042406 # Number of tag accesses 253110515SAli.Saidi@ARM.comsystem.iocache.tags.data_accesses 1042406 # Number of data accesses 253210515SAli.Saidi@ARM.comsystem.iocache.WriteInvalidateReq_hits::realview.ide 106728 # number of WriteInvalidateReq hits 253310515SAli.Saidi@ARM.comsystem.iocache.WriteInvalidateReq_hits::total 106728 # number of WriteInvalidateReq hits 253410515SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 253510515SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::realview.ide 8889 # number of ReadReq misses 253610515SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::total 8926 # number of ReadReq misses 253710515SAli.Saidi@ARM.comsystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 253810515SAli.Saidi@ARM.comsystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 253910515SAli.Saidi@ARM.comsystem.iocache.WriteInvalidateReq_misses::realview.ide 187 # number of WriteInvalidateReq misses 254010515SAli.Saidi@ARM.comsystem.iocache.WriteInvalidateReq_misses::total 187 # number of WriteInvalidateReq misses 254110515SAli.Saidi@ARM.comsystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 254210515SAli.Saidi@ARM.comsystem.iocache.demand_misses::realview.ide 8889 # number of demand (read+write) misses 254310515SAli.Saidi@ARM.comsystem.iocache.demand_misses::total 8929 # number of demand (read+write) misses 254410515SAli.Saidi@ARM.comsystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 254510515SAli.Saidi@ARM.comsystem.iocache.overall_misses::realview.ide 8889 # number of overall misses 254610515SAli.Saidi@ARM.comsystem.iocache.overall_misses::total 8929 # number of overall misses 254710515SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5701000 # number of ReadReq miss cycles 254810515SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_latency::realview.ide 1965059357 # number of ReadReq miss cycles 254910515SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_latency::total 1970760357 # number of ReadReq miss cycles 255010515SAli.Saidi@ARM.comsystem.iocache.WriteReq_miss_latency::realview.ethernet 357000 # number of WriteReq miss cycles 255110515SAli.Saidi@ARM.comsystem.iocache.WriteReq_miss_latency::total 357000 # number of WriteReq miss cycles 255210515SAli.Saidi@ARM.comsystem.iocache.demand_miss_latency::realview.ethernet 6058000 # number of demand (read+write) miss cycles 255310515SAli.Saidi@ARM.comsystem.iocache.demand_miss_latency::realview.ide 1965059357 # number of demand (read+write) miss cycles 255410515SAli.Saidi@ARM.comsystem.iocache.demand_miss_latency::total 1971117357 # number of demand (read+write) miss cycles 255510515SAli.Saidi@ARM.comsystem.iocache.overall_miss_latency::realview.ethernet 6058000 # number of overall miss cycles 255610515SAli.Saidi@ARM.comsystem.iocache.overall_miss_latency::realview.ide 1965059357 # number of overall miss cycles 255710515SAli.Saidi@ARM.comsystem.iocache.overall_miss_latency::total 1971117357 # number of overall miss cycles 255810515SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 255910515SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::realview.ide 8889 # number of ReadReq accesses(hits+misses) 256010515SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::total 8926 # number of ReadReq accesses(hits+misses) 256110515SAli.Saidi@ARM.comsystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 256210515SAli.Saidi@ARM.comsystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 256310515SAli.Saidi@ARM.comsystem.iocache.WriteInvalidateReq_accesses::realview.ide 106915 # number of WriteInvalidateReq accesses(hits+misses) 256410515SAli.Saidi@ARM.comsystem.iocache.WriteInvalidateReq_accesses::total 106915 # number of WriteInvalidateReq accesses(hits+misses) 256510515SAli.Saidi@ARM.comsystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 256610515SAli.Saidi@ARM.comsystem.iocache.demand_accesses::realview.ide 8889 # number of demand (read+write) accesses 256710515SAli.Saidi@ARM.comsystem.iocache.demand_accesses::total 8929 # number of demand (read+write) accesses 256810515SAli.Saidi@ARM.comsystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 256910515SAli.Saidi@ARM.comsystem.iocache.overall_accesses::realview.ide 8889 # number of overall (read+write) accesses 257010515SAli.Saidi@ARM.comsystem.iocache.overall_accesses::total 8929 # number of overall (read+write) accesses 257110515SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 257210515SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 257310515SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 257410515SAli.Saidi@ARM.comsystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 257510515SAli.Saidi@ARM.comsystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 257610515SAli.Saidi@ARM.comsystem.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.001749 # miss rate for WriteInvalidateReq accesses 257710515SAli.Saidi@ARM.comsystem.iocache.WriteInvalidateReq_miss_rate::total 0.001749 # miss rate for WriteInvalidateReq accesses 257810515SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 257910515SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 258010515SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 258110515SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 258210515SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 258310515SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 258410515SAli.Saidi@ARM.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 154081.081081 # average ReadReq miss latency 258510515SAli.Saidi@ARM.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 221066.414332 # average ReadReq miss latency 258610515SAli.Saidi@ARM.comsystem.iocache.ReadReq_avg_miss_latency::total 220788.747143 # average ReadReq miss latency 258710515SAli.Saidi@ARM.comsystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency 258810515SAli.Saidi@ARM.comsystem.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency 258910515SAli.Saidi@ARM.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 151450 # average overall miss latency 259010515SAli.Saidi@ARM.comsystem.iocache.demand_avg_miss_latency::realview.ide 221066.414332 # average overall miss latency 259110515SAli.Saidi@ARM.comsystem.iocache.demand_avg_miss_latency::total 220754.547766 # average overall miss latency 259210515SAli.Saidi@ARM.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 151450 # average overall miss latency 259310515SAli.Saidi@ARM.comsystem.iocache.overall_avg_miss_latency::realview.ide 221066.414332 # average overall miss latency 259410515SAli.Saidi@ARM.comsystem.iocache.overall_avg_miss_latency::total 220754.547766 # average overall miss latency 259510515SAli.Saidi@ARM.comsystem.iocache.blocked_cycles::no_mshrs 54362 # number of cycles access was blocked 259610515SAli.Saidi@ARM.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 259710515SAli.Saidi@ARM.comsystem.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked 259810515SAli.Saidi@ARM.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 259910515SAli.Saidi@ARM.comsystem.iocache.avg_blocked_cycles::no_mshrs 9.902004 # average number of cycles each access was blocked 260010515SAli.Saidi@ARM.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 260110515SAli.Saidi@ARM.comsystem.iocache.fast_writes 106728 # number of fast writes performed 260210515SAli.Saidi@ARM.comsystem.iocache.cache_copies 0 # number of cache copies performed 260310515SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 260410515SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8889 # number of ReadReq MSHR misses 260510515SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_misses::total 8926 # number of ReadReq MSHR misses 260610515SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 260710515SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 260810515SAli.Saidi@ARM.comsystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 260910515SAli.Saidi@ARM.comsystem.iocache.demand_mshr_misses::realview.ide 8889 # number of demand (read+write) MSHR misses 261010515SAli.Saidi@ARM.comsystem.iocache.demand_mshr_misses::total 8929 # number of demand (read+write) MSHR misses 261110515SAli.Saidi@ARM.comsystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 261210515SAli.Saidi@ARM.comsystem.iocache.overall_mshr_misses::realview.ide 8889 # number of overall MSHR misses 261310515SAli.Saidi@ARM.comsystem.iocache.overall_mshr_misses::total 8929 # number of overall MSHR misses 261410515SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3777000 # number of ReadReq MSHR miss cycles 261510515SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1502702365 # number of ReadReq MSHR miss cycles 261610515SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_miss_latency::total 1506479365 # number of ReadReq MSHR miss cycles 261710515SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 261810515SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 261910515SAli.Saidi@ARM.comsystem.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6627847227 # number of WriteInvalidateReq MSHR miss cycles 262010515SAli.Saidi@ARM.comsystem.iocache.WriteInvalidateReq_mshr_miss_latency::total 6627847227 # number of WriteInvalidateReq MSHR miss cycles 262110515SAli.Saidi@ARM.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3978000 # number of demand (read+write) MSHR miss cycles 262210515SAli.Saidi@ARM.comsystem.iocache.demand_mshr_miss_latency::realview.ide 1502702365 # number of demand (read+write) MSHR miss cycles 262310515SAli.Saidi@ARM.comsystem.iocache.demand_mshr_miss_latency::total 1506680365 # number of demand (read+write) MSHR miss cycles 262410515SAli.Saidi@ARM.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3978000 # number of overall MSHR miss cycles 262510515SAli.Saidi@ARM.comsystem.iocache.overall_mshr_miss_latency::realview.ide 1502702365 # number of overall MSHR miss cycles 262610515SAli.Saidi@ARM.comsystem.iocache.overall_mshr_miss_latency::total 1506680365 # number of overall MSHR miss cycles 262710515SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 262810515SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 262910515SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 263010515SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 263110515SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 263210515SAli.Saidi@ARM.comsystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 263310515SAli.Saidi@ARM.comsystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 263410515SAli.Saidi@ARM.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 263510515SAli.Saidi@ARM.comsystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 263610515SAli.Saidi@ARM.comsystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 263710515SAli.Saidi@ARM.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 263810515SAli.Saidi@ARM.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102081.081081 # average ReadReq mshr miss latency 263910515SAli.Saidi@ARM.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 169051.902914 # average ReadReq mshr miss latency 264010515SAli.Saidi@ARM.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 168774.295877 # average ReadReq mshr miss latency 264110515SAli.Saidi@ARM.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 264210515SAli.Saidi@ARM.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 264310515SAli.Saidi@ARM.comsystem.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency 264410515SAli.Saidi@ARM.comsystem.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 264510515SAli.Saidi@ARM.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99450 # average overall mshr miss latency 264610515SAli.Saidi@ARM.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 169051.902914 # average overall mshr miss latency 264710515SAli.Saidi@ARM.comsystem.iocache.demand_avg_mshr_miss_latency::total 168740.101355 # average overall mshr miss latency 264810515SAli.Saidi@ARM.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99450 # average overall mshr miss latency 264910515SAli.Saidi@ARM.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 169051.902914 # average overall mshr miss latency 265010515SAli.Saidi@ARM.comsystem.iocache.overall_avg_mshr_miss_latency::total 168740.101355 # average overall mshr miss latency 265110515SAli.Saidi@ARM.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 265210515SAli.Saidi@ARM.com 265310515SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 2654